aboutsummaryrefslogtreecommitdiff
path: root/resources/libreboot
Commit message (Collapse)AuthorAgeFilesLines
...
* New board: Intel D510MOFrancis Rowe2016-01-305-0/+561
|
* New board: ASUS KCMA-D8 desktop/workstation motherboardFrancis Rowe2016-01-3049-0/+11060
|
* Revert "reset x60/t60/macbook21 to older coreboot revisions"Francis Rowe2016-01-2931-829/+435
| | | | This reverts commit 3b56767917dccd59c4af7c289450a053982e984a.
* reset x60/t60/macbook21 to older coreboot revisionsFrancis Rowe2016-01-2831-435/+829
| | | | This is a temporary fix for an upcoming release.
* Gigabyte GA-G41M-ES2L (desktop board) added to librebootFrancis Rowe2016-01-054-0/+517
|
* Use different coreboot revisions and patches per boardFrancis Rowe2016-01-04252-2394/+256
| | | | | | | | | | | | | | | | | | The release archives will be bigger, but this is a necessary change that makes libreboot development easier. At present, there are boards maintained in libreboot by different people. By doing it this way, that becomes much easier. This is in contrast to the present situation, where a change to one board potentially affects all other boards, especially when updating to a new version of coreboot. Coreboot-libre scripts, download scripts, build scripts - everything. The entire build system has been modified to reflect this change of development. For reasons of consistency, cbfstool and nvramtool are no longer included in the util archives.
* delete coreinfoFrancis Rowe2015-12-132-109/+0
|
* libpayload: use tinycurses, not pdcursesFrancis Rowe2015-12-091-2/+2
| | | | | | Fixes this error when running coreinfo on X200: initsrc(): Unable to create stdscr exited with status 1
* remove redundant filesFrancis Rowe2015-12-091-1/+0
|
* New payload: CoreinfoKlemens Nanni2015-12-093-0/+110
| | | | | | | | | | | | | | | Add coreinfo as optional payload providing various useful system information. As part of coreboot, coreinfo does not need to be downloaded seperately, just build it using $ ./build module coreinfo after downloading and building coreboot. See https://www.coreboot.org/Payloads#Coreinfo for more information.
* Update config for ASUS C201Francis Rowe2015-11-061-0/+4
|
* Replace Chromebook mentions with CrOS, that is more genericPaul Kocialkowski2015-11-062-0/+0
| | | | | | | | | | Not all CrOS devices are Chromebooks (laptops) or run on ARM, not all RK3288 CrOS devices are Chromebooks, either. We want to support more CrOS devices, including some that are not Chromebooks, such as the ASUS Chromebit! Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* veyron_speedy config update, depthcharge menus improvementPaul Kocialkowski2015-11-064-170/+20
|
* Update coreboot-libre configs (forgot to do it earlier)Francis Rowe2015-11-0620-34/+53
|
* Update coreboot to new version (use latest stable kgpe-d16 tree)Francis Rowe2015-11-06147-2495/+2285
|
* kgpe-d16: add configs for more flash chip sizes (4, 8 and 16 MiB)Francis Rowe2015-10-204-0/+1749
|
* KGPE-D16: update patch set (also update coreboot and vboot)Francis Rowe2015-10-19183-4326/+13579
| | | | | | | | | | | Also contains other fixes from coreboot, like: * 551cff0 Derive lvds_dual_channel from EDID timings. ^ makes single/dual channel LVDS selection on GM45 automatic * 26fc544 lenovo/t60: Enable native intel gfx init. ^ was being maintained in libreboot, now upstreamed so not needed Framebuffer mode was disabled for the KGPE-D16, because only text-mode works at the moment.
* New board: ASUS KGPE-D16Francis Rowe2015-10-17158-6/+54878
| | | | | | | | | | | | | | | | | | | | coreboot build errors: In file included from src/northbridge/amd/amdfam10/misc_control.c:35:0: src/include/option.h:13:27: error: static declaration of 'get_option' follows non-static declaration static inline enum cb_err get_option(void *dest, const char *name) ^ In file included from src/northbridge/amd/amdfam10/misc_control.c:34:0: src/include/pc80/mc146818rtc.h:176:13: note: previous declaration of 'get_option' was here enum cb_err get_option(void *dest, const char *name); Ping tpearson about this. Also ping him about the fact that there isn't actually an option to enable or disable native graphics initialization, but that the option MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is in fact available and set to Y in the Kconfig file. I think this is probably since there isn't even an option ROM available for the machine, so it's pointless to offer the setting.
* Add 2MiB option for KFSN4-DREFrancis Rowe2015-10-151-0/+564
|
* Revert "c201: rename config from veyron_speedy to c201"Francis Rowe2015-10-111-0/+0
| | | | This reverts commit a48c2ebe2733b3af0755c44dc6525ecf4f21c0ab.
* c201: rename config from veyron_speedy to c201Francis Rowe2015-10-111-0/+0
|
* Chromebook C201 (codename veyron_speedy) supportPaul Kocialkowski2015-10-1112-0/+1172
| | | | | | | | | | | | | | | | | This introduces Libreboot support for the Asus Chromebook C201 (codename veyron_speedy). At this point, this produces a standalone Libreboot image that can be flashed to the RO Coreboot partition of the SPI flash, as well as the Libreboot version that can be flash to the RO Firmware ID partition. Libreboot on the Chromebook C201 uses the depthcharge bootloader, modified to display text messages instead of ChromeOS bitmaps (that encourage the use of ChromeOS). For convenience, an installation script, chromebook-flash-replace, is provided along with a description of the flash layout, to ease the replacement of the Coreboot and RO Firmware ID partitions on the full SPI flash image. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* Add patches for R500 (will finish later, and upstream them)Francis Rowe2015-10-118-0/+2268
|
* Update coreboot-libre based on coreboot a2bed346aFrancis Rowe2015-10-1114-79/+88
| | | | | | | | | | | | | | | More microcode blobs were deleted upstream, which are therefore no longer deleted by coreboot-libre. util/broadcom/secimage/misc.c is not a blob. Some non-blobs were deleted upstream, which are therefore no longer listed in libreboot's nonblobs list. New non-blobs were found, added to the nonblobs list. vboot submodule was added, since there are parts of it that cbfstool needs. This submodule is now deblobbed by libreboot.
* Update coreboot to the latest as of 4 August 2015Francis Rowe2015-08-0430-1167/+994
|
* coreboot-libre: move GRUB configs to grub/Francis Rowe2015-06-2814-0/+0
|
* kfsn4-dre: Add CONFIG_VGA=y to the configFrancis Rowe2015-06-262-9/+30
| | | | Video initialization won't work without it.
* New board: ASUS KFSN4-DREFrancis Rowe2015-06-261-0/+573
|
* Update coreboot again (a patch was merged upstream)Francis Rowe2015-06-1614-41/+52
| | | | | | | | | | The patch for only requiring cmake for clang users was merged. This patch is important, because libreboot doesn't want to use clang, and doesn't want any dependences that it relies on which it doesn't need. Also, this and the other recent update re-add support for ACPI brightness methods on the Thinkpad X60 and T60.
* Update coreboot-libreFrancis Rowe2015-06-1638-3677/+1308
| | | | | | | | | | | | Rebase all patches. Remove the ones that are no longer needed. More CPU microcode updates were moved to coreboot's 3rdparty repository, so there are less blobs for libreboot to delete now (because the 3rdparty repository is not checked out in libreboot). Correct HDA verbs used for T400 (also R400, T500) (patch is in coreboot, merged).
* coreboot-libre configs: enable changing nvram settingsFrancis Rowe2015-06-1211-11/+11
|
* coreboot-libre: backport patches for X200 Tablet digitizer supportFrancis Rowe2015-05-173-2/+127
|
* coreboot-libre: delete unused code (reduce size of src archive)Francis Rowe2015-05-162-8/+0
|
* scripts/download/coreboot: use diffs, not gerritFrancis Rowe2015-05-1122-0/+3406
| | | | | | | Solves the problem where coreboot.org down down makes libreboot.git useless. Now if coreboot.org goes down, you can just use a backup coreboot repository and then run the script.
* Update coreboot + merge GM45 hybrid GPU patchesFrancis Rowe2015-05-0413-132/+276
| | | | | | | | | | | | | Also add power_on_after_fail to X200 and others (prevents the bug where the system would boot when connecting the AC adapter) (option in menuconfig to use CMOS/nvram settings is now enabled) Also NetDCDC is now the default USB debug dongle used (compatible with the BBB rev C). Add two new methods for managing coreboot configs: ./build config corebootreplace ./build config corebootmodify
* ThinkPad T500 supportFrancis Rowe2015-03-3110-0/+962
|
* New board: ThinkPad T400Francis Rowe2015-03-1811-0/+967
|
* Update corebootFrancis Rowe2015-03-1610-273/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update to new coreboot revision: 83b05eb0a85d7b7ac0837cece67afabbdb46ea65 Intel microcode updates are no longer deleted, because these no longer exist in the main coreboot branch. Instead, they exist in the optional 3rdparty repository which libreboot does not merge. note: the microcode in src/soc/intel/ still exists and is still deleted in libreboot, therefore TODO: delete the instructions in coreboot that download the 3rdparty branch MacBook2,1 cstate patch is no longer cherry picked, because this is now merged in the main coreboot repository. The patch to disable use of timestamps in non-git is now removed, because a better version of patch was submitted to and merged in coreboot. coreboot-libre: These blobs either don't exist in coreboot anymore, or have had their names changed. They are no longer listed in the deblob script: src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000025.c src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c src/cpu/amd/model_10xxx/mc_patch_01000086.h src/cpu/amd/model_10xxx/mc_patch_0100009f.h src/cpu/amd/model_10xxx/mc_patch_010000b6.h src/cpu/amd/model_10xxx/mc_patch_010000bf.h src/cpu/amd/model_10xxx/mc_patch_010000c4.h src/northbridge/amd/agesa/family12/ssdt.asl coreboot-libre: These nonblobs either don't exist in coreboot anymore, or have had their names changed. They are no longer listed in the nonblobs or nonblobs_notes files: ./src/mainboard/digitallogic/msm586seg/mainboard.c ./src/mainboard/intel/jarrell/irq_tables.c ./src/mainboard/supermicro/x6dai_g/irq_tables.c ./src/mainboard/technologic/ts5300/mainboard.c ./src/mainboard/via/epia/irq_tables.c ./src/northbridge/via/vx800/examples/chipset_init.c ./src/southbridge/amd/cs5530/bitmap.c ./src/southbridge/amd/pi/avalon/Kconfig ./src/mainboard/google/samus/samsung_8Gb.spd.hex ./src/mainboard/google/samus/empty.spd.hex ./src/mainboard/google/samus/elpida_4Gb.spd.hex ./src/mainboard/google/samus/elpida_8Gb.spd.hex ./src/mainboard/google/samus/samsung_4Gb.spd.hex coreboot-libre: The following were added to the nonblobs file: ./src/mainboard/google/samus/spd/samsung_4Gb.spd.hex ./src/mainboard/google/samus/spd/empty.spd.hex ./src/mainboard/google/samus/spd/elpida_8Gb.spd.hex ./src/mainboard/google/samus/spd/hynix_4Gb.spd.hex ./src/mainboard/google/samus/spd/samsung_8Gb.spd.hex ./src/mainboard/google/samus/spd/hynix_8Gb.spd.hex ./src/mainboard/google/samus/spd/elpida_4Gb.spd.hex ./src/drivers/xgi/common/vb_table.h ./src/drivers/xgi/common/vb_setmode.c ./src/drivers/xgi/common/XGI_main.h ./src/mainboard/siemens/mc_tcu3/romstage.c ./src/mainboard/siemens/mc_tcu3/lcd_panel.c ./src/mainboard/siemens/mc_tcu3/modhwinfo.c ./src/mainboard/pcengines/apu1/Kconfig ./src/mainboard/asus/kfsn4-dre/get_bus_conf.c ./src/mainboard/google/samus/spd/spd.c ./src/mainboard/hp/abm/mptable.c ./src/northbridge/amd/pi/00630F01/Kconfig ./src/cpu/amd/microcode/microcode.c ./src/lib/tlcl_structures.h coreboot-libre: New blobs in coreboot are now deleted in libreboot: src/soc/intel/baytrail/microcode/M0C3067_0000031E.h src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c src/cpu/amd/model_10xxx/mc_patch_010000d9.h src/cpu/amd/model_10xxx/mc_patch_010000dc.h src/cpu/amd/model_10xxx/mc_patch_010000db.h src/cpu/amd/model_10xxx/mc_patch_010000c7.h src/cpu/amd/model_10xxx/mc_patch_010000c8.h
* New board: ThinkPad R400 support added to libreboot.Francis Rowe2015-02-099-64/+1041
|
* X60, X60S and X60 Tablet now the same ROM images.Francis Rowe2015-02-012-489/+6
| | | | The same images are now used for all three variants.
* Add QEMU (q35/ich9) support to libreboot.Francis Rowe2015-01-301-0/+471
|
* Add QEMU (i440fx/piix4) support to librebootFrancis Rowe2015-01-301-0/+436
|
* Update coreboot (again)Francis Rowe2014-12-136-34/+93
| | | | Also improve the deblob utilities
* build: automatically find board names (configs) to build forFrancis Rowe2014-12-121-7/+0
|
* ThinkPad X200 support added to librebootFrancis Rowe2014-12-112-0/+920
|
* coreboot-libre config (all boards): enable USB dongle log outputFrancis Rowe2014-11-284-33/+4
| | | | For EHCI debugging on the BeagleBone Black
* Update corebootFrancis Rowe2014-11-236-136/+167
| | | | | | | | | | | | | | Some notes: DEBLOB script updated (more blobs added). i945: reverted to legacy brightness. i945: permanently set tft_brightness to 0xff (works around a bug on X60 where brightness loops to zero when at max brightness and trying to increase the brightness level) EHCI debug dongle (BeagleBone Black) now enabled on all boards.
* Revert "buildrom-withgrub: Only include 1 keymap file in GRUB memdisk."Francis Rowe2014-11-214-8/+16
| | | | This reverts commit 3e1712768172e53ed02da96e1bb392edaa219de7.
* buildrom-withgrub: Only include 1 keymap file in GRUB memdisk.Francis Rowe2014-11-214-16/+8
| | | | | | | | | | | | | This is to reduce the size of the image. To accomplish this, the payload in each coreboot configuration was set to 'None', after which the buildrom-withgrub script was modified to build a new grub.elf for each image. This is fast, since building the grub.elf only takes less than a second. The alternative was to build a new coreboot ROM per keymap, which would have been slow. Other files were also modified along with this, check the diff to see everything.
* T60: fix compilationFrancis Rowe2014-10-121-0/+12
|