From 3b93b0ffd99d0f4e85067da28b62e118a16e35c6 Mon Sep 17 00:00:00 2001
From: Francis Rowe <info@gluglug.org.uk>
Date: Wed, 11 Feb 2015 05:49:08 +0000
Subject: docs/install/x200_external: Mention GPIO33 non-descriptor mode

---
 docs/install/x200_external.html | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/docs/install/x200_external.html b/docs/install/x200_external.html
index d4f1a912..e0f21796 100644
--- a/docs/install/x200_external.html
+++ b/docs/install/x200_external.html
@@ -111,6 +111,9 @@ chip on those pins?
 				Check the list of SOIC-8 flash chips at <a href="../hcl/gm45_remove_me.html#flashchips">../hcl/gm45_remove_me.html#flashchips</a> but
 				do note that these are only 4MiB (32Mb) chips. The only X200 SPI chips with 8MiB capacity are SOIC-16. For 8MiB capacity in this case,
 				the X201 SOIC-8 flash chip (Macronix 25L6445E) might work.
+				<br/>
+				Another possible solution: ground GPIO33 and boot up in non-descriptor mode. This might make software flashing possible, if
+				it's possible to circumvent any flashing protections that might exist.
 			</p>
 
 			<h2>
-- 
cgit v1.2.3-70-g09d2