From 6ea2b7023b65755d2f68c625646d8927babe270b Mon Sep 17 00:00:00 2001 From: Swift Geek Date: Mon, 13 Nov 2017 05:53:57 +0000 Subject: Clarification on BUC.TS Missing trivia that can cause a brick --- docs/install/index.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/install/index.md b/docs/install/index.md index 70dd554e..ea48632d 100644 --- a/docs/install/index.md +++ b/docs/install/index.md @@ -283,6 +283,8 @@ ThinkPad X60/T60: Initial installation guide (if running the proprietary firmwar already have coreboot or libreboot running, then go to [\#flashrom](#flashrom) instead!* +*If you can, make sure that RTC battery is not discharged. Discharged RTC battery may lead to brick due to not holding BUC register value* + *If you are flashing a Lenovo ThinkPad T60, be sure to read [../hardware/\#supported\_t60\_list](../hardware/#supported_t60_list)* @@ -324,7 +326,7 @@ Seeing this means that the operation was a *resounding* success! See this link for more details: . -If the above is what you see, then *SHUT DOWN*. Wait a few seconds, +If the above is what you see, then *SHUT DOWN* (but do not remove power, especially RTC battery). Wait a few seconds, and then boot; libreboot is running, but there is a 2nd procedure needed (see below). -- cgit v1.2.3-70-g09d2 From dbf207f8f93ebf35b65554634b12210c7d938236 Mon Sep 17 00:00:00 2001 From: "konstantin.grudnev" Date: Mon, 20 Nov 2017 16:06:22 +0300 Subject: Core Quad update info about compatible CPUs for T500 --- docs/install/t500_external.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/docs/install/t500_external.md b/docs/install/t500_external.md index 37217337..c9b85a5d 100644 --- a/docs/install/t500_external.md +++ b/docs/install/t500_external.md @@ -39,6 +39,9 @@ Quad-core CPUs Very likely to be compatible, but requires hardware modification. Based on info from German forum post about installing Core Quad CPU on T500 found in coreboot mailing list. Currently work in progress and no guide available. +Q9100 is compatible and confirmed working (after hw mod), as reported by users in the IRC +channel + - [Coreboot mailing list post](https://mail.coreboot.org/pipermail/coreboot/2016-November/082463.html) - [German forum post about install Core Quad on T500](https://thinkpad-forum.de/threads/199129) -- cgit v1.2.3-70-g09d2 From d35277f7fee9bcc8d9c23bb5bc3dcaf844543066 Mon Sep 17 00:00:00 2001 From: Edgard Schmidt Date: Sat, 25 Nov 2017 17:31:22 +0100 Subject: Limit image size to viewport's width --- www/global.css | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/www/global.css b/www/global.css index 80309059..98adf82d 100644 --- a/www/global.css +++ b/www/global.css @@ -21,6 +21,10 @@ pre { margin-left: 2.5em } +img { + max-width: 100%; +} + #logo { width: 20%; float: right; -- cgit v1.2.3-70-g09d2 From 21f502b2088759b4dab9a2299ee03a50975b48bd Mon Sep 17 00:00:00 2001 From: Edgard Schmidt Date: Sat, 25 Nov 2017 17:31:51 +0100 Subject: Allow line breaks for bare URI links --- www/global.css | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/www/global.css b/www/global.css index 98adf82d..35df49d6 100644 --- a/www/global.css +++ b/www/global.css @@ -35,6 +35,11 @@ a { color: #22D; } +/* probably generated with autolink_bare_uris extension */ +a.uri { + word-wrap: break-word; +} + a:hover { color: #008; } -- cgit v1.2.3-70-g09d2 From 1096373b2330e64c3012f143f943f4723d526c16 Mon Sep 17 00:00:00 2001 From: Edgard Schmidt Date: Sat, 25 Nov 2017 17:32:04 +0100 Subject: Make code content and tables more responsive * 'pre' blocks and tables use scrollbars if the viewport is too narrow * Code content which is not within a 'pre' element wraps automatically * Code content and 'pre' blocks have a gray background color The added background color has two purposes: * The left-margin for pre blocks is removed, because it consumes too much space on narrow viewports. However by using a background color, the reader can still recognize 'pre' content as code blocks. * Code content which is *not* within a 'pre' element wraps automatically now. The background color allows the reader to recognize the "connection" between automatically splitted lines of a single code element. This way, nobody will mistake a one-liner for a multi-liner. --- www/global.css | 11 ++++++++++- www/template.html | 1 - 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/www/global.css b/www/global.css index 35df49d6..87df287d 100644 --- a/www/global.css +++ b/www/global.css @@ -18,7 +18,16 @@ body { } pre { - margin-left: 2.5em + padding: 0.3em; +} + +pre,table { + overflow-x: auto; + display: block; +} + +code, pre { + background-color: #DDD; } img { diff --git a/www/template.html b/www/template.html index 4ce72774..c2bdcda0 100644 --- a/www/template.html +++ b/www/template.html @@ -14,7 +14,6 @@ $if(keywords)$ $endif$ $if(title-prefix)$$title-prefix$ – $endif$$pagetitle$ - $if(quotes)$ $endif$ -- cgit v1.2.3-70-g09d2 From d43c6eaec611cc88309a9e09757dfba691e6f354 Mon Sep 17 00:00:00 2001 From: Edgard Schmidt Date: Sat, 25 Nov 2017 17:32:11 +0100 Subject: Markup more code content with code and pre tags --- docs/gnulinux/encrypted_parabola.md | 22 +++++++++++++++++----- docs/gnulinux/grub_hardening.md | 3 ++- docs/install/x60_unbrick.md | 13 ++++++------- docs/install/x60tablet_unbrick.md | 13 ++++++------- 4 files changed, 31 insertions(+), 20 deletions(-) diff --git a/docs/gnulinux/encrypted_parabola.md b/docs/gnulinux/encrypted_parabola.md index a4d7dd16..99a6fe0d 100644 --- a/docs/gnulinux/encrypted_parabola.md +++ b/docs/gnulinux/encrypted_parabola.md @@ -83,7 +83,9 @@ if it's not new, then there are two ways to handle it: you can either choose to fill it with zeroes or random data; I chose random data (e.g., `urandom`), because it's more secure. Depending on the size of the drive, this could take a while to complete: - `# dd if=/dev/urandom of=/dev/sdX; sync` + ~~~ + # dd if=/dev/urandom of=/dev/sdX; sync + ~~~ 2. If the drive were previously encrypted, all you need to do is wipe the LUKS header. The size of the header depends upon the specific model of the hard drive; @@ -91,7 +93,9 @@ you can find this information by doing some research online. Refer to this [article](https://www.lisenet.com/2013/luks-add-keys-backup-and-restore-volume-header/), for more information about LUKS headers. You can either fill the header with zeroes, or with random data; again, I chose random data, using `urandom`: - `# head -c 3145728 /dev/urandom > /dev/sdX; sync` + ~~~ + # head -c 3145728 /dev/urandom > /dev/sdX; sync + ~~~ Also, if you're using an SSD, there are a two things you should keep in mind: @@ -192,11 +196,15 @@ equally cleverly named as **rootvol**. Also, make sure to [choose an appropriate swap size](http://www.linux.com/news/software/applications/8208-all-about-linux-swap-space) (e.g., **2G** refers to two gigabytes; change this however you see fit): - `# lvcreate -L 2G matrix -n swapvol` + ~~~ + # lvcreate -L 2G matrix -n swapvol + ~~~ 2. Now, we will create a single, large partition in the rest of the space, for **rootvol**: - `# lvcreate -l +100%FREE matrix -n rootvol` + ~~~ + # lvcreate -l +100%FREE matrix -n rootvol + ~~~ You can also be flexible here, for example you can specify a **/boot**, a **/**, a **/home**, a **/var**, or a **/usr** volume. For example, if you will be running a @@ -313,7 +321,11 @@ There are several modifications that we need to make to the file: Make sure to separate each module by one space. 2. Change the value of the uncommented `HOOKS` line to the following: - “`base udev autodetect modconf block keyboard keymap consolefont encrypt lvm2 filesystems fsck shutdown`”; + + ~~~ + base udev autodetect modconf block keyboard keymap consolefont encrypt lvm2 filesystems fsck shutdown + ~~~ + here's what each module does: * `keymap` adds to *initramfs* the keymap that you specified in **/etc/vconsole.conf** diff --git a/docs/gnulinux/grub_hardening.md b/docs/gnulinux/grub_hardening.md index c32a0534..9eb7237e 100644 --- a/docs/gnulinux/grub_hardening.md +++ b/docs/gnulinux/grub_hardening.md @@ -81,7 +81,8 @@ installing GRUB version 2. Generate a key by giving it a password: grub-mkpasswd-pbkdf2 Its output will be a string of the following form: -grub.pbkdf2.sha512.10000.HEXDIGITS.MOREHEXDIGITS + + grub.pbkdf2.sha512.10000.HEXDIGITS.MOREHEXDIGITS Now open my.grubtest.cfg and put the following before the menu entries (prefered above the functions and after other directives). Of course use diff --git a/docs/install/x60_unbrick.md b/docs/install/x60_unbrick.md index 0f215302..d7cb17a8 100644 --- a/docs/install/x60_unbrick.md +++ b/docs/install/x60_unbrick.md @@ -20,13 +20,12 @@ two:\ \*Those dd commands should be applied to all newly compiled X60 ROM images (the ROM images in libreboot binary archives already have this -applied!):\ -dd if=coreboot.rom of=top64k.bin bs=1 skip=\$\[\$(stat -c %s -coreboot.rom) - 0x10000\] count=64k\ -dd if=coreboot.rom bs=1 skip=\$\[\$(stat -c %s coreboot.rom) - 0x20000\] -count=64k | hexdump\ -dd if=top64k.bin of=coreboot.rom bs=1 seek=\$\[\$(stat -c %s -coreboot.rom) - 0x20000\] count=64k conv=notrunc\ +applied!): + + dd if=coreboot.rom of=top64k.bin bs=1 skip=\$\[\$(stat -c %s coreboot.rom) - 0x10000\] count=64k + dd if=coreboot.rom bs=1 skip=\$\[\$(stat -c %s coreboot.rom) - 0x20000\] count=64k | hexdump + dd if=top64k.bin of=coreboot.rom bs=1 seek=\$\[\$(stat -c %s coreboot.rom) - 0x20000\] count=64k conv=notrunc + (doing this makes the ROM suitable for use when flashing a system that still has Lenovo BIOS running, using those instructions: . diff --git a/docs/install/x60tablet_unbrick.md b/docs/install/x60tablet_unbrick.md index f4baebf4..fe4352bc 100644 --- a/docs/install/x60tablet_unbrick.md +++ b/docs/install/x60tablet_unbrick.md @@ -20,13 +20,12 @@ two:\ \*Those dd commands should be applied to all newly compiled X60 ROM images (the ROM images in libreboot binary archives already have this -applied!):\ -dd if=coreboot.rom of=top64k.bin bs=1 skip=\$\[\$(stat -c %s -coreboot.rom) - 0x10000\] count=64k\ -dd if=coreboot.rom bs=1 skip=\$\[\$(stat -c %s coreboot.rom) - 0x20000\] -count=64k | hexdump\ -dd if=top64k.bin of=coreboot.rom bs=1 seek=\$\[\$(stat -c %s -coreboot.rom) - 0x20000\] count=64k conv=notrunc\ +applied!): + + dd if=coreboot.rom of=top64k.bin bs=1 skip=\$\[\$(stat -c %s coreboot.rom) - 0x10000\] count=64k + dd if=coreboot.rom bs=1 skip=\$\[\$(stat -c %s coreboot.rom) - 0x20000\] count=64k | hexdump + dd if=top64k.bin of=coreboot.rom bs=1 seek=\$\[\$(stat -c %s coreboot.rom) - 0x20000\] count=64k conv=notrunc + (doing this makes the ROM suitable for use when flashing a system that still has Lenovo BIOS running, using those instructions: . -- cgit v1.2.3-70-g09d2 From b31ec4fff0ac6c62f50d0e8d1770fb25c66e3cda Mon Sep 17 00:00:00 2001 From: Tobias Platen Date: Fri, 24 Nov 2017 21:58:02 +0100 Subject: add new supplier (Phreedom2600) --- www/suppliers.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/www/suppliers.md b/www/suppliers.md index 2c61164f..57b3045b 100644 --- a/www/suppliers.md +++ b/www/suppliers.md @@ -35,6 +35,16 @@ Merchendise: - [Libreboot X200 docking station](https://minifree.org/product/docking-station-for-libreboot-x200/) - [Libreboot stickers](https://minifree.org/product/libreboot-stickers/) +Phreedom 2600 +------------------ + +Phreedom 2600 sells the BeagleBone Black (which can be used for flashing Libreboot) +and the Thinkpad X200. All computers come with Parabola GNU/Linux preinstalled. +All products meets the criteria for [Respects Your Freedom](https://fsf.org/ryf). + +The webshop is here: + + Raptor Engineering ------------------ -- cgit v1.2.3-70-g09d2 From 971b440403059ffc2d5b3bd83330b550689ef9bd Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 30 Nov 2017 20:21:25 -0500 Subject: Update bucts URI to point to Libreboot's mirror stuge.se is, seemingly, down indefinitely which means users can no longer automatically clone bucts using the build scripts; by changing the repo URI to Libreboot's mirror this issue is resolved. --- projects/bucts/bucts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/bucts/bucts b/projects/bucts/bucts index a5feeabc..4456bb55 100644 --- a/projects/bucts/bucts +++ b/projects/bucts/bucts @@ -27,7 +27,7 @@ usage() { download() { local repository="$project" - project_download_git "$project" "$repository" 'git://git.stuge.se/bucts.git' "$@" + project_download_git "$project" "$repository" 'https://notabug.org/libreboot/bucts.git' "$@" } download_check() { -- cgit v1.2.3-70-g09d2 From 44858dd869d6c6e2dd18cf20dd991e187715c108 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 1 Dec 2017 18:45:20 +0000 Subject: link to guide for encrypted hyperbola gnu+linux install --- docs/gnulinux/encrypted_parabola.md | 2 ++ docs/gnulinux/index.md | 2 ++ 2 files changed, 4 insertions(+) diff --git a/docs/gnulinux/encrypted_parabola.md b/docs/gnulinux/encrypted_parabola.md index 99a6fe0d..b2e40a01 100644 --- a/docs/gnulinux/encrypted_parabola.md +++ b/docs/gnulinux/encrypted_parabola.md @@ -3,6 +3,8 @@ title: Installing Parabola or Arch GNU+Linux-Libre, with Full-Disk Encryption (i x-toc-enable: true ... +Also see: +[Installing Hyperbola GNU+Linux, with Full-Disk Encryption (including /boot)](https://wiki.hyperbola.info/en:guide:encrypted_installation) This guide covers how to install Parabola GNU+Linux-Libre, with full disk encryption, including **/boot** (the boot directory). On most systems, **/boot** has diff --git a/docs/gnulinux/index.md b/docs/gnulinux/index.md index f8738d4a..a2a411ab 100644 --- a/docs/gnulinux/index.md +++ b/docs/gnulinux/index.md @@ -20,6 +20,8 @@ However, with Libreboot, GRUB is already included directly (as a payload), so ev - Follow-Up Tutorial: [Configuring Parabola (Post-Install)](configuring_parabola.md) +- [Installing Hyperbola GNU+Linux, with Full-Disk Encryption (including /boot)](https://wiki.hyperbola.info/en:guide:encrypted_installation) + - [Installing Trisquel GNU+Linux-Libre, with Full-Disk Encryption (including /boot)](encrypted_trisquel.md) - [Installing Debian or Devuan GNU+Linux-Libre, with Full-Disk Encryption (including /boot)](encrypted_debian.md) -- cgit v1.2.3-70-g09d2 From 245f356688ea31f328458e30a8bd9a4fae17197e Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Tue, 5 Dec 2017 16:55:12 +0000 Subject: Re-add minifree libreboot x200 to suppliers page (PR not needed) Pull request not needed for this entry, since it's an entry regarding my own company --- www/suppliers.md | 1 + 1 file changed, 1 insertion(+) diff --git a/www/suppliers.md b/www/suppliers.md index 57b3045b..916804f2 100644 --- a/www/suppliers.md +++ b/www/suppliers.md @@ -22,6 +22,7 @@ endorsement on a computer system, and invests money directly into Libreboot. Laptops: +- [Libreboot X200 laptop](https://minifree.org/product/libreboot-x200/) (FSF RYF certified) - [Libreboot T400 laptop](https://minifree.org/product/libreboot-t400/) (FSF RYF certified) Services: -- cgit v1.2.3-70-g09d2 From 161bd2942ea1967e35469c3fa7c8cbc30653bf55 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Tue, 28 Nov 2017 21:01:18 -0500 Subject: Bump Depthcharge revision to origin/release-R63-10032.B "release-R63-10032.B" is a branch name in Depthcharge's remote repository corresponding to the latest release. --- projects/depthcharge/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/depthcharge/configs/revision b/projects/depthcharge/configs/revision index bc799613..ec6fe7d9 100644 --- a/projects/depthcharge/configs/revision +++ b/projects/depthcharge/configs/revision @@ -1 +1 @@ -66b58a339a7fcc79248b9ef7853449542683c45d +origin/release-R63-10032.B -- cgit v1.2.3-70-g09d2 From 944e51bc8caa05cc1db9bc0e603a6dfb7235557d Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Tue, 28 Nov 2017 21:52:48 -0500 Subject: Bump flashrom-CrOS revision to origin/release-R63-10032.B "release-R63-10032.B" is a branch name in CrOS flashrom's remote repository corresponding to the latest release. --- projects/flashrom-cros/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/flashrom-cros/configs/revision b/projects/flashrom-cros/configs/revision index 79d3a325..ec6fe7d9 100644 --- a/projects/flashrom-cros/configs/revision +++ b/projects/flashrom-cros/configs/revision @@ -1 +1 @@ -origin/release-R56-9000.B +origin/release-R63-10032.B -- cgit v1.2.3-70-g09d2 From 7a6370e9f87f506ee817d4bec587e10699fa6453 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Tue, 28 Nov 2017 22:27:44 -0500 Subject: Bump CrOS-EC revision to origin/release-R63-10032.B "release-R63-10032.B" is a branch name in CrOS-EC's remote repository corresponding to the latest release. --- projects/cros-ec/configs/nyan/revision | 2 +- projects/cros-ec/configs/veyron/revision | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/cros-ec/configs/nyan/revision b/projects/cros-ec/configs/nyan/revision index 7a809c4c..ec6fe7d9 100644 --- a/projects/cros-ec/configs/nyan/revision +++ b/projects/cros-ec/configs/nyan/revision @@ -1 +1 @@ -3c5457348e08d8606a8398cc9265cb144ec4baf6 +origin/release-R63-10032.B diff --git a/projects/cros-ec/configs/veyron/revision b/projects/cros-ec/configs/veyron/revision index e27b3d1c..ec6fe7d9 100644 --- a/projects/cros-ec/configs/veyron/revision +++ b/projects/cros-ec/configs/veyron/revision @@ -1 +1 @@ -242f6bd3e6f3b2d0b0e2b764c34fbab2db051189 +origin/release-R63-10032.B -- cgit v1.2.3-70-g09d2 From 9e4080e93b23323cc28c6015fbdb35dbb21b9c86 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Tue, 28 Nov 2017 22:38:42 -0500 Subject: Bump hdctools revision to origin/release-R63-10032.B "release-R63-10032.B" is a branch name in CrOS hdctools' remote repository corresponding to the latest release. --- projects/hdctools/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/hdctools/configs/revision b/projects/hdctools/configs/revision index 79d3a325..ec6fe7d9 100644 --- a/projects/hdctools/configs/revision +++ b/projects/hdctools/configs/revision @@ -1 +1 @@ -origin/release-R56-9000.B +origin/release-R63-10032.B -- cgit v1.2.3-70-g09d2 From 9f9828fda4993c1dd935def6c8b7e31415c9e3b3 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Tue, 28 Nov 2017 22:41:43 -0500 Subject: Bump mosys revision to origin/release-R63-10032.B "release-R63-10032.B" is a branch name in CrOS mosys' remote repository corresponding to the latest release. --- projects/mosys/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/mosys/configs/revision b/projects/mosys/configs/revision index 79d3a325..ec6fe7d9 100644 --- a/projects/mosys/configs/revision +++ b/projects/mosys/configs/revision @@ -1 +1 @@ -origin/release-R56-9000.B +origin/release-R63-10032.B -- cgit v1.2.3-70-g09d2 From f5db3f242e61f9d327b9a0d808f664607e506e24 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Tue, 28 Nov 2017 22:44:51 -0500 Subject: Bump vpd revision to origin/release-R63-10032.B "release-R63-10032.B" is a branch name in CrOS vpd's remote repository corresponding to the latest release. --- projects/vpd/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/vpd/configs/revision b/projects/vpd/configs/revision index 79d3a325..ec6fe7d9 100644 --- a/projects/vpd/configs/revision +++ b/projects/vpd/configs/revision @@ -1 +1 @@ -origin/release-R56-9000.B +origin/release-R63-10032.B -- cgit v1.2.3-70-g09d2 From f6943c87b2752efa36238c1d208ac66492055e48 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Tue, 28 Nov 2017 22:46:31 -0500 Subject: Bump vboot revision to origin/release-R63-10032.B "release-R63-10032.B" is a branch name in CrOS vboot's remote repository corresponding to the latest release. --- projects/vboot/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/vboot/configs/revision b/projects/vboot/configs/revision index 79d3a325..ec6fe7d9 100644 --- a/projects/vboot/configs/revision +++ b/projects/vboot/configs/revision @@ -1 +1 @@ -origin/release-R56-9000.B +origin/release-R63-10032.B -- cgit v1.2.3-70-g09d2 From 9bffb10f4ba8bc54aee2dedb798259041851bf97 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Tue, 28 Nov 2017 23:12:36 -0500 Subject: Bump flashmap revision to origin/release-R63-10032.B "release-R63-10032.B" is a branch name in CrOS flashmap's remote repository corresponding to the latest release. --- projects/flashmap/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/flashmap/configs/revision b/projects/flashmap/configs/revision index 79d3a325..ec6fe7d9 100644 --- a/projects/flashmap/configs/revision +++ b/projects/flashmap/configs/revision @@ -1 +1 @@ -origin/release-R56-9000.B +origin/release-R63-10032.B -- cgit v1.2.3-70-g09d2 From cf74d32d9a9fc2d98415084644073bbcc9669a11 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Tue, 28 Nov 2017 23:37:31 -0500 Subject: Bump Memtest86+ revision to remote HEAD --- projects/memtest86plus/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/memtest86plus/configs/revision b/projects/memtest86plus/configs/revision index e16bc904..8b866a4f 100644 --- a/projects/memtest86plus/configs/revision +++ b/projects/memtest86plus/configs/revision @@ -1 +1 @@ -1fa69864d4c0aa46bb3ebd7feb966c882fb81a84 +686a6739e5e0020262b45ad6e45795e7b1b7b67c -- cgit v1.2.3-70-g09d2 From 7c8bbf819e97f696d94b13fc50cc0e49c0c4684c Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Tue, 28 Nov 2017 23:40:38 -0500 Subject: Bump SeaBIOS revision to rel-1.11.0 This is the latest release of SeaBIOS. --- projects/seabios/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/seabios/configs/revision b/projects/seabios/configs/revision index f03e0556..3274dbdb 100644 --- a/projects/seabios/configs/revision +++ b/projects/seabios/configs/revision @@ -1 +1 @@ -19fdcca467ad3436d68ef88899b4dcd78154a9c6 +rel-1.11.0 -- cgit v1.2.3-70-g09d2 From 07d60787790e5d771f4bb1d76d48498b569c8487 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Tue, 5 Dec 2017 12:51:57 -0500 Subject: Correct revision used for bucts The upstream repository from which bucts is pulled has changed, necessitating a different revision pointing to HEAD. --- projects/bucts/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/bucts/configs/revision b/projects/bucts/configs/revision index 1ac89ef2..ee153928 100644 --- a/projects/bucts/configs/revision +++ b/projects/bucts/configs/revision @@ -1 +1 @@ -dc27919d7a66a6e8685ce07c71aefa4f03ef7c07 +6fa9d52277a76a1bace7458d8ed91acf8c94c0c1 -- cgit v1.2.3-70-g09d2 From d6b970f0dc6111489e354d80e391ea13e47efffc Mon Sep 17 00:00:00 2001 From: CoreShoe Date: Tue, 5 Dec 2017 18:37:37 +0000 Subject: Update 'projects/coreboot/configs/seabios/r400_16mb/config' --- projects/coreboot/configs/seabios/r400_16mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/r400_16mb/config b/projects/coreboot/configs/seabios/r400_16mb/config index d0be0b1a..6df1a028 100644 --- a/projects/coreboot/configs/seabios/r400_16mb/config +++ b/projects/coreboot/configs/seabios/r400_16mb/config @@ -113,7 +113,7 @@ CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad R400" CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_MAX_CPUS=2 +CONFIG_MAX_CPUS=4 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0xFFD000 CONFIG_VGA_BIOS_ID="8086,2a42" -- cgit v1.2.3-70-g09d2 From 9f2d33343b578fd9ec5ebb8ede9cf30ce32c6a7c Mon Sep 17 00:00:00 2001 From: CoreShoe Date: Tue, 5 Dec 2017 18:37:46 +0000 Subject: Update 'projects/coreboot/configs/seabios/r400_4mb/config' --- projects/coreboot/configs/seabios/r400_4mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/r400_4mb/config b/projects/coreboot/configs/seabios/r400_4mb/config index 13ea1c67..55c6a211 100644 --- a/projects/coreboot/configs/seabios/r400_4mb/config +++ b/projects/coreboot/configs/seabios/r400_4mb/config @@ -113,7 +113,7 @@ CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad R400" CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_MAX_CPUS=2 +CONFIG_MAX_CPUS=4 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0x3FD000 CONFIG_VGA_BIOS_ID="8086,2a42" -- cgit v1.2.3-70-g09d2 From 35f6cc4ca9f51aaa4d9efb71a3741e90001be111 Mon Sep 17 00:00:00 2001 From: CoreShoe Date: Tue, 5 Dec 2017 18:37:54 +0000 Subject: Update 'projects/coreboot/configs/seabios/r400_8mb/config' --- projects/coreboot/configs/seabios/r400_8mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/r400_8mb/config b/projects/coreboot/configs/seabios/r400_8mb/config index 56a22708..1b2e9374 100644 --- a/projects/coreboot/configs/seabios/r400_8mb/config +++ b/projects/coreboot/configs/seabios/r400_8mb/config @@ -113,7 +113,7 @@ CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad R400" CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_MAX_CPUS=2 +CONFIG_MAX_CPUS=4 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0x7FD000 CONFIG_VGA_BIOS_ID="8086,2a42" -- cgit v1.2.3-70-g09d2 From 663cc6a9b75a243df89d92ace4c1ddfb4b5c9bc5 Mon Sep 17 00:00:00 2001 From: CoreShoe Date: Tue, 5 Dec 2017 18:38:01 +0000 Subject: Update 'projects/coreboot/configs/seabios/t400_16mb/config' --- projects/coreboot/configs/seabios/t400_16mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/t400_16mb/config b/projects/coreboot/configs/seabios/t400_16mb/config index 69af9ed1..6158d98b 100644 --- a/projects/coreboot/configs/seabios/t400_16mb/config +++ b/projects/coreboot/configs/seabios/t400_16mb/config @@ -113,7 +113,7 @@ CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T400" CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_MAX_CPUS=2 +CONFIG_MAX_CPUS=4 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0xFFD000 CONFIG_VGA_BIOS_ID="8086,2a42" -- cgit v1.2.3-70-g09d2 From ceda5622c5379ba1f93b892ab4d8d1032603bb86 Mon Sep 17 00:00:00 2001 From: CoreShoe Date: Tue, 5 Dec 2017 18:38:09 +0000 Subject: Update 'projects/coreboot/configs/seabios/t400_4mb/config' --- projects/coreboot/configs/seabios/t400_4mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/t400_4mb/config b/projects/coreboot/configs/seabios/t400_4mb/config index 74287e71..a0663b75 100644 --- a/projects/coreboot/configs/seabios/t400_4mb/config +++ b/projects/coreboot/configs/seabios/t400_4mb/config @@ -113,7 +113,7 @@ CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T400" CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_MAX_CPUS=2 +CONFIG_MAX_CPUS=4 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0x3FD000 CONFIG_VGA_BIOS_ID="8086,2a42" -- cgit v1.2.3-70-g09d2 From e82404a80001834abf222510e2480e627fbdc017 Mon Sep 17 00:00:00 2001 From: CoreShoe Date: Tue, 5 Dec 2017 18:38:19 +0000 Subject: Update 'projects/coreboot/configs/seabios/t400_8mb/config' --- projects/coreboot/configs/seabios/t400_8mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/t400_8mb/config b/projects/coreboot/configs/seabios/t400_8mb/config index 76be1d08..fada3b93 100644 --- a/projects/coreboot/configs/seabios/t400_8mb/config +++ b/projects/coreboot/configs/seabios/t400_8mb/config @@ -113,7 +113,7 @@ CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T400" CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_MAX_CPUS=2 +CONFIG_MAX_CPUS=4 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0x7FD000 CONFIG_VGA_BIOS_ID="8086,2a42" -- cgit v1.2.3-70-g09d2 From 64203b42eedb242de76421569964b9838f91b416 Mon Sep 17 00:00:00 2001 From: CoreShoe Date: Tue, 5 Dec 2017 18:38:27 +0000 Subject: Update 'projects/coreboot/configs/seabios/t500_16mb/config' --- projects/coreboot/configs/seabios/t500_16mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/t500_16mb/config b/projects/coreboot/configs/seabios/t500_16mb/config index db78f75a..b4ba07f8 100644 --- a/projects/coreboot/configs/seabios/t500_16mb/config +++ b/projects/coreboot/configs/seabios/t500_16mb/config @@ -113,7 +113,7 @@ CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T500" CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_MAX_CPUS=2 +CONFIG_MAX_CPUS=4 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0xFFD000 CONFIG_VGA_BIOS_ID="8086,2a42" -- cgit v1.2.3-70-g09d2 From 6686d7f6c81865efdc596c13b2fc9369f09d8485 Mon Sep 17 00:00:00 2001 From: CoreShoe Date: Tue, 5 Dec 2017 18:38:36 +0000 Subject: Update 'projects/coreboot/configs/seabios/t500_4mb/config' --- projects/coreboot/configs/seabios/t500_4mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/t500_4mb/config b/projects/coreboot/configs/seabios/t500_4mb/config index 2d9c18c5..87b59c8e 100644 --- a/projects/coreboot/configs/seabios/t500_4mb/config +++ b/projects/coreboot/configs/seabios/t500_4mb/config @@ -113,7 +113,7 @@ CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T500" CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_MAX_CPUS=2 +CONFIG_MAX_CPUS=4 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0x3FD000 CONFIG_VGA_BIOS_ID="8086,2a42" -- cgit v1.2.3-70-g09d2 From f5cf9316cda217e9f17c064d5557cb7c3d51bd01 Mon Sep 17 00:00:00 2001 From: CoreShoe Date: Tue, 5 Dec 2017 18:38:43 +0000 Subject: Update 'projects/coreboot/configs/seabios/t500_8mb/config' --- projects/coreboot/configs/seabios/t500_8mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/t500_8mb/config b/projects/coreboot/configs/seabios/t500_8mb/config index d693bc98..c02c71a0 100644 --- a/projects/coreboot/configs/seabios/t500_8mb/config +++ b/projects/coreboot/configs/seabios/t500_8mb/config @@ -113,7 +113,7 @@ CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T500" CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_MAX_CPUS=2 +CONFIG_MAX_CPUS=4 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0x7FD000 CONFIG_VGA_BIOS_ID="8086,2a42" -- cgit v1.2.3-70-g09d2 From 7b5d31a5af3261d8a8bb4d30e945858fd625f64f Mon Sep 17 00:00:00 2001 From: CoreShoe Date: Tue, 5 Dec 2017 18:38:51 +0000 Subject: Update 'projects/coreboot/configs/seabios/w500_16mb/config' --- projects/coreboot/configs/seabios/w500_16mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/w500_16mb/config b/projects/coreboot/configs/seabios/w500_16mb/config index bbc29cba..205b5d1b 100644 --- a/projects/coreboot/configs/seabios/w500_16mb/config +++ b/projects/coreboot/configs/seabios/w500_16mb/config @@ -113,7 +113,7 @@ CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W500" CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_MAX_CPUS=2 +CONFIG_MAX_CPUS=4 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0xFFD000 CONFIG_VGA_BIOS_ID="8086,2a42" -- cgit v1.2.3-70-g09d2 From ed26735ba4c598aa444418e0548030cc7c990255 Mon Sep 17 00:00:00 2001 From: CoreShoe Date: Tue, 5 Dec 2017 18:38:57 +0000 Subject: Update 'projects/coreboot/configs/seabios/w500_4mb/config' --- projects/coreboot/configs/seabios/w500_4mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/w500_4mb/config b/projects/coreboot/configs/seabios/w500_4mb/config index d49c420d..201248b6 100644 --- a/projects/coreboot/configs/seabios/w500_4mb/config +++ b/projects/coreboot/configs/seabios/w500_4mb/config @@ -113,7 +113,7 @@ CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W500" CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_MAX_CPUS=2 +CONFIG_MAX_CPUS=4 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0x3FD000 CONFIG_VGA_BIOS_ID="8086,2a42" -- cgit v1.2.3-70-g09d2 From 0a9bd989a8a468095e4172688fd152ed379af22e Mon Sep 17 00:00:00 2001 From: CoreShoe Date: Tue, 5 Dec 2017 18:39:06 +0000 Subject: Update 'projects/coreboot/configs/seabios/w500_8mb/config' --- projects/coreboot/configs/seabios/w500_8mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/w500_8mb/config b/projects/coreboot/configs/seabios/w500_8mb/config index a03171ac..fecd941b 100644 --- a/projects/coreboot/configs/seabios/w500_8mb/config +++ b/projects/coreboot/configs/seabios/w500_8mb/config @@ -113,7 +113,7 @@ CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W500" CONFIG_MAINBOARD_VENDOR="LENOVO" -CONFIG_MAX_CPUS=2 +CONFIG_MAX_CPUS=4 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 CONFIG_CBFS_SIZE=0x7FD000 CONFIG_VGA_BIOS_ID="8086,2a42" -- cgit v1.2.3-70-g09d2 From 3418e6974d1bf8f44700eac00f70968d4cfca15e Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sun, 17 Dec 2017 01:33:50 -0500 Subject: Correct shell command returning CPUID on the X200 --- docs/hardware/x200.md | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/docs/hardware/x200.md b/docs/hardware/x200.md index c5f535cb..b7bb434b 100644 --- a/docs/hardware/x200.md +++ b/docs/hardware/x200.md @@ -236,9 +236,7 @@ different, so this page might be BS) pehjota started collecting some steppings for different CPUs on several X200 laptops. You can get the CPUID by running: - # dmesg | sed -n 's/\^.\* microcode: CPU0 - -sig=0x\\(\[\^,\]\*\\),.\*\$/\\1/p' + # dmesg | sed -n 's/.*microcode:.*sig=\([^,]*\),.*$/\1/p' | uniq What pehjota wrote: The laptops that have issues resuming from suspend, as well as a laptop that (as I mentioned earlier in \#libreboot) won't -- cgit v1.2.3-70-g09d2 From 38a97cb6839c74463fc9334681b2df15af268b63 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 21 Dec 2017 22:16:05 +0000 Subject: news article asking people to help with release testing --- www/news/MANIFEST | 1 + www/news/release-testing-20171221.md | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 www/news/release-testing-20171221.md diff --git a/www/news/MANIFEST b/www/news/MANIFEST index b092d469..45bc9cae 100644 --- a/www/news/MANIFEST +++ b/www/news/MANIFEST @@ -1,3 +1,4 @@ +news/release-testing-20171221.md news/lenovo-recall.md news/alyssa-resignation.md news/talos.md diff --git a/www/news/release-testing-20171221.md b/www/news/release-testing-20171221.md new file mode 100644 index 00000000..28c23ca0 --- /dev/null +++ b/www/news/release-testing-20171221.md @@ -0,0 +1,19 @@ +% Testers needed for a new upcoming Libreboot release +% Leah Rowe +% 21 Dec 2017 + +We need testers, especially hardware testers, for a new upcoming release of +Libreboot. + +Andrew Robbins, one of the developers, has done extensive work on the build +system in Libreboot and now we are rebasing all boards in Libreboot onto the +latest version of coreboot. Upstream coreboot has many bugfixes, which the +version that Libreboot uses (an older revision) does not have. + +We are currently assembling a team of testers. If you wish to participate, +then reply on this thread in our bug tracker: + + + +Any help would be appreciated. In general, testing is also needed (e.g. +build testing, documentation testing/improvements, etc). -- cgit v1.2.3-70-g09d2 From f48ed45ae98e8bafcb7bed055bbb01fd6088f082 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 21 Dec 2017 17:41:39 -0500 Subject: Bump Coreboot revision to current upstream HEAD --- projects/coreboot/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/revision b/projects/coreboot/configs/revision index 8f14f42e..6f2c9f24 100644 --- a/projects/coreboot/configs/revision +++ b/projects/coreboot/configs/revision @@ -1 +1 @@ -a19d44d2764be4dba55cad96abea12d92c8e1f0d +ceeafa45cae26ab857687082e02eae40d9621291 -- cgit v1.2.3-70-g09d2 From fb06ba3c110ccd01d87110595e73b47e7de9cffd Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 21 Dec 2017 18:19:13 -0500 Subject: Update Coreboot patch for removing git submodules This is an update to Paul Kocialkowski's previous patch. Only an absolute minimum of changes were made over those of Paul's in order for it to apply, successfully, hence keeping Paul as the author of the patch. --- ...1-Avoid-using-git-submodules-for-3rdparty.patch | 50 +++++++++++----------- 1 file changed, 24 insertions(+), 26 deletions(-) diff --git a/projects/coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch b/projects/coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch index da906849..6fd53217 100644 --- a/projects/coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch +++ b/projects/coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch @@ -1,13 +1,10 @@ -From 6c534728fde6a9582915995a2742808764fe4783 Mon Sep 17 00:00:00 2001 +From c47f1f9e3b5d1a77b5261ad7cb7538c384828487 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski -Date: Wed, 20 Jul 2016 16:03:30 +0200 -Subject: [PATCH 1/2] Avoid using git submodules for 3rdparty +Date: Thu, 21 Dec 2017 18:05:33 -0500 +Subject: [PATCH] Avoid using git submodules for 3rdparty This gets rid of git submodules entirely, to avoid the nuisance caused by automatically checking them out. - -Change-Id: I54de09656bd2dd9c308bd6c8dce554945aa8e535 -Signed-off-by: Paul Kocialkowski --- .gitmodules | 20 -------------------- 3rdparty/arm-trusted-firmware | 1 - @@ -16,8 +13,8 @@ Signed-off-by: Paul Kocialkowski 3rdparty/libgfxinit | 1 - 3rdparty/libhwbase | 1 - 3rdparty/vboot | 1 - - Makefile.inc | 11 ----------- - 8 files changed, 37 deletions(-) + Makefile.inc | 12 ------------ + 8 files changed, 38 deletions(-) delete mode 160000 3rdparty/arm-trusted-firmware delete mode 160000 3rdparty/blobs delete mode 160000 3rdparty/chromeec @@ -26,7 +23,7 @@ Signed-off-by: Paul Kocialkowski delete mode 160000 3rdparty/vboot diff --git a/.gitmodules b/.gitmodules -index c3270e6ae2..3a617c7dc5 100644 +index c3270e6..3a617c7 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,23 +1,3 @@ @@ -55,51 +52,51 @@ index c3270e6ae2..3a617c7dc5 100644 - url = ../libgfxinit.git diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware deleted file mode 160000 -index 236c27d21f..0000000000 +index b118723..0000000 --- a/3rdparty/arm-trusted-firmware +++ /dev/null @@ -1 +0,0 @@ --Subproject commit 236c27d21f52ad8f0a998e54774e3d8a4b59129d +-Subproject commit b1187232fdf819586ba8c8ece4a27a7515cbdc6d diff --git a/3rdparty/blobs b/3rdparty/blobs deleted file mode 160000 -index 8090bdd598..0000000000 +index d2e558a..0000000 --- a/3rdparty/blobs +++ /dev/null @@ -1 +0,0 @@ --Subproject commit 8090bdd59853599e469b7503ea473ca12e8c681b +-Subproject commit d2e558a81f95f7b9149bea6b8362bb43ade82584 diff --git a/3rdparty/chromeec b/3rdparty/chromeec deleted file mode 160000 -index bcffec7fdc..0000000000 +index 9fb1038..0000000 --- a/3rdparty/chromeec +++ /dev/null @@ -1 +0,0 @@ --Subproject commit bcffec7fdc50e959cb298d094d8af472777dba75 +-Subproject commit 9fb10386a720d270e37ce61da3ff3a6d5a69951e diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit deleted file mode 160000 -index 88a7f17b7d..0000000000 +index 42fb2d0..0000000 --- a/3rdparty/libgfxinit +++ /dev/null @@ -1 +0,0 @@ --Subproject commit 88a7f17b7d7a4f8a4d25ef6b87c71236b0862f5d +-Subproject commit 42fb2d065d604eb08c723ac6b96aeebb4c84cbd3 diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase deleted file mode 160000 -index aab715f166..0000000000 +index 6685971..0000000 --- a/3rdparty/libhwbase +++ /dev/null @@ -1 +0,0 @@ --Subproject commit aab715f166bf1b54cfbd6982e8df49248ea544d8 +-Subproject commit 66859712e4817288591908d737dbf41ddea31c3a diff --git a/3rdparty/vboot b/3rdparty/vboot deleted file mode 160000 -index adfafba793..0000000000 +index f6780a3..0000000 --- a/3rdparty/vboot +++ /dev/null @@ -1 +0,0 @@ --Subproject commit adfafba793684ed92965dfbd86b3fb3463975d8c +-Subproject commit f6780a36ff19b36abcdb5ace903c4ae2272fb574 diff --git a/Makefile.inc b/Makefile.inc -index c5ce30f2b1..919a5d4ac1 100644 +index 413f7ad..ed2d839 100644 --- a/Makefile.inc +++ b/Makefile.inc -@@ -183,17 +183,6 @@ ifeq ($(CONFIG_COVERAGE),y) +@@ -191,18 +191,6 @@ ifeq ($(CONFIG_COVERAGE),y) ramstage-c-ccopts += -fprofile-arcs -ftest-coverage endif @@ -111,12 +108,13 @@ index c5ce30f2b1..919a5d4ac1 100644 -# unless explicitly requested and enabled through --checkout -forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs)) -endif --export UPDATED_SUBMODULES:=1 +-UPDATED_SUBMODULES:=1 +-COREBOOT_EXPORTS += UPDATED_SUBMODULES -endif - + postcar-c-deps:=$$(OPTION_TABLE_H) ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) - libverstage-c-deps:=$$(OPTION_TABLE_H) -- -2.11.0 +1.9.1 -- cgit v1.2.3-70-g09d2 From 44ccbdc9dfd1bbfd2636ec9d36c930f38171093b Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 21 Dec 2017 18:30:51 -0500 Subject: Delete obsolete Coreboot patch from tree --- ...ad-Enable-USB-HID-in-veyron-configuration.patch | 27 ---------------------- 1 file changed, 27 deletions(-) delete mode 100644 projects/coreboot/patches/0002-libpayload-Enable-USB-HID-in-veyron-configuration.patch diff --git a/projects/coreboot/patches/0002-libpayload-Enable-USB-HID-in-veyron-configuration.patch b/projects/coreboot/patches/0002-libpayload-Enable-USB-HID-in-veyron-configuration.patch deleted file mode 100644 index aa76b57a..00000000 --- a/projects/coreboot/patches/0002-libpayload-Enable-USB-HID-in-veyron-configuration.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 417866c23c193a44a84d686ce1c2ee3d43284e05 Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski -Date: Mon, 19 Dec 2016 20:23:44 +0100 -Subject: [PATCH 2/2] libpayload: Enable USB HID in veyron configuration - -This enables USB HID support in the veyron config, since it seems to -work correctly and is needed for interaction with depthcharge on devices -without an embedded keyboard (such as veyron_mickey). - -Change-Id: Icae829e3a132005df17bcb6f7e6f8a190912576d -Signed-off-by: Paul Kocialkowski ---- - payloads/libpayload/configs/config.veyron | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/payloads/libpayload/configs/config.veyron b/payloads/libpayload/configs/config.veyron -index e80535c63e..b643e92a48 100644 ---- a/payloads/libpayload/configs/config.veyron -+++ b/payloads/libpayload/configs/config.veyron -@@ -4,4 +4,3 @@ CONFIG_LP_8250_SERIAL_CONSOLE=y - CONFIG_LP_TIMER_RK3288=y - CONFIG_LP_USB_EHCI=y - CONFIG_LP_USB_DWC2=y --# CONFIG_LP_USB_HID is not set --- -2.11.0 - -- cgit v1.2.3-70-g09d2 From a30938357f14bd236f44b9d19ae1930ff8bf49aa Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 21 Dec 2017 19:13:06 -0500 Subject: Delete board-specific Coreboot revision files Testing needs to be done on the revision specified at 'projects/coreboot/configs/revision', thus all board-specific revision files should be removed in order to avoid checking out an older commit in the meantime. --- projects/coreboot/configs/seabios/d510mo/revision | 1 - projects/coreboot/configs/seabios/d945gclf/revision | 1 - projects/coreboot/configs/seabios/ga-g41m-es2l/revision | 1 - projects/coreboot/configs/seabios/kcma-d8/revision | 1 - projects/coreboot/configs/seabios/kfsn4-dre/revision | 1 - projects/coreboot/configs/seabios/kgpe-d16/revision | 1 - projects/coreboot/configs/seabios/macbook21/revision | 1 - projects/coreboot/configs/seabios/qemu_i440fx_piix4/revision | 1 - projects/coreboot/configs/seabios/qemu_q35_ich9/revision | 1 - projects/coreboot/configs/seabios/r400_16mb/revision | 1 - projects/coreboot/configs/seabios/r400_4mb/revision | 1 - projects/coreboot/configs/seabios/r400_8mb/revision | 1 - projects/coreboot/configs/seabios/t400_16mb/revision | 1 - projects/coreboot/configs/seabios/t400_4mb/revision | 1 - projects/coreboot/configs/seabios/t400_8mb/revision | 1 - projects/coreboot/configs/seabios/t500_16mb/revision | 1 - projects/coreboot/configs/seabios/t500_4mb/revision | 1 - projects/coreboot/configs/seabios/t500_8mb/revision | 1 - projects/coreboot/configs/seabios/t60/revision | 1 - projects/coreboot/configs/seabios/w500_16mb/revision | 1 - projects/coreboot/configs/seabios/w500_4mb/revision | 1 - projects/coreboot/configs/seabios/w500_8mb/revision | 1 - projects/coreboot/configs/seabios/x200_16mb/revision | 1 - projects/coreboot/configs/seabios/x200_4mb/revision | 1 - projects/coreboot/configs/seabios/x200_8mb/revision | 1 - projects/coreboot/configs/seabios/x60/revision | 1 - 26 files changed, 26 deletions(-) delete mode 100644 projects/coreboot/configs/seabios/d510mo/revision delete mode 100644 projects/coreboot/configs/seabios/d945gclf/revision delete mode 100644 projects/coreboot/configs/seabios/ga-g41m-es2l/revision delete mode 100644 projects/coreboot/configs/seabios/kcma-d8/revision delete mode 100644 projects/coreboot/configs/seabios/kfsn4-dre/revision delete mode 100644 projects/coreboot/configs/seabios/kgpe-d16/revision delete mode 100644 projects/coreboot/configs/seabios/macbook21/revision delete mode 100644 projects/coreboot/configs/seabios/qemu_i440fx_piix4/revision delete mode 100644 projects/coreboot/configs/seabios/qemu_q35_ich9/revision delete mode 100644 projects/coreboot/configs/seabios/r400_16mb/revision delete mode 100644 projects/coreboot/configs/seabios/r400_4mb/revision delete mode 100644 projects/coreboot/configs/seabios/r400_8mb/revision delete mode 100644 projects/coreboot/configs/seabios/t400_16mb/revision delete mode 100644 projects/coreboot/configs/seabios/t400_4mb/revision delete mode 100644 projects/coreboot/configs/seabios/t400_8mb/revision delete mode 100644 projects/coreboot/configs/seabios/t500_16mb/revision delete mode 100644 projects/coreboot/configs/seabios/t500_4mb/revision delete mode 100644 projects/coreboot/configs/seabios/t500_8mb/revision delete mode 100644 projects/coreboot/configs/seabios/t60/revision delete mode 100644 projects/coreboot/configs/seabios/w500_16mb/revision delete mode 100644 projects/coreboot/configs/seabios/w500_4mb/revision delete mode 100644 projects/coreboot/configs/seabios/w500_8mb/revision delete mode 100644 projects/coreboot/configs/seabios/x200_16mb/revision delete mode 100644 projects/coreboot/configs/seabios/x200_4mb/revision delete mode 100644 projects/coreboot/configs/seabios/x200_8mb/revision delete mode 100644 projects/coreboot/configs/seabios/x60/revision diff --git a/projects/coreboot/configs/seabios/d510mo/revision b/projects/coreboot/configs/seabios/d510mo/revision deleted file mode 100644 index 1ab8299e..00000000 --- a/projects/coreboot/configs/seabios/d510mo/revision +++ /dev/null @@ -1 +0,0 @@ -2a3434757ef425dbdfedf1fc69e1a033a6e7310d diff --git a/projects/coreboot/configs/seabios/d945gclf/revision b/projects/coreboot/configs/seabios/d945gclf/revision deleted file mode 100644 index f6e726f0..00000000 --- a/projects/coreboot/configs/seabios/d945gclf/revision +++ /dev/null @@ -1 +0,0 @@ -36d405268f040208cd26902f3c0b5346f7d4d25b diff --git a/projects/coreboot/configs/seabios/ga-g41m-es2l/revision b/projects/coreboot/configs/seabios/ga-g41m-es2l/revision deleted file mode 100644 index e785a260..00000000 --- a/projects/coreboot/configs/seabios/ga-g41m-es2l/revision +++ /dev/null @@ -1 +0,0 @@ -7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b diff --git a/projects/coreboot/configs/seabios/kcma-d8/revision b/projects/coreboot/configs/seabios/kcma-d8/revision deleted file mode 100644 index a4c248f2..00000000 --- a/projects/coreboot/configs/seabios/kcma-d8/revision +++ /dev/null @@ -1 +0,0 @@ -eee0e229764e965996479d7eb07e6086176b8bf0 diff --git a/projects/coreboot/configs/seabios/kfsn4-dre/revision b/projects/coreboot/configs/seabios/kfsn4-dre/revision deleted file mode 100644 index fabe7537..00000000 --- a/projects/coreboot/configs/seabios/kfsn4-dre/revision +++ /dev/null @@ -1 +0,0 @@ -15fca66bf08db45937ce88b950491963654805b9 diff --git a/projects/coreboot/configs/seabios/kgpe-d16/revision b/projects/coreboot/configs/seabios/kgpe-d16/revision deleted file mode 100644 index a4c248f2..00000000 --- a/projects/coreboot/configs/seabios/kgpe-d16/revision +++ /dev/null @@ -1 +0,0 @@ -eee0e229764e965996479d7eb07e6086176b8bf0 diff --git a/projects/coreboot/configs/seabios/macbook21/revision b/projects/coreboot/configs/seabios/macbook21/revision deleted file mode 100644 index 1ab8299e..00000000 --- a/projects/coreboot/configs/seabios/macbook21/revision +++ /dev/null @@ -1 +0,0 @@ -2a3434757ef425dbdfedf1fc69e1a033a6e7310d diff --git a/projects/coreboot/configs/seabios/qemu_i440fx_piix4/revision b/projects/coreboot/configs/seabios/qemu_i440fx_piix4/revision deleted file mode 100644 index 1ab8299e..00000000 --- a/projects/coreboot/configs/seabios/qemu_i440fx_piix4/revision +++ /dev/null @@ -1 +0,0 @@ -2a3434757ef425dbdfedf1fc69e1a033a6e7310d diff --git a/projects/coreboot/configs/seabios/qemu_q35_ich9/revision b/projects/coreboot/configs/seabios/qemu_q35_ich9/revision deleted file mode 100644 index 1ab8299e..00000000 --- a/projects/coreboot/configs/seabios/qemu_q35_ich9/revision +++ /dev/null @@ -1 +0,0 @@ -2a3434757ef425dbdfedf1fc69e1a033a6e7310d diff --git a/projects/coreboot/configs/seabios/r400_16mb/revision b/projects/coreboot/configs/seabios/r400_16mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/r400_16mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/r400_4mb/revision b/projects/coreboot/configs/seabios/r400_4mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/r400_4mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/r400_8mb/revision b/projects/coreboot/configs/seabios/r400_8mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/r400_8mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/t400_16mb/revision b/projects/coreboot/configs/seabios/t400_16mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/t400_16mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/t400_4mb/revision b/projects/coreboot/configs/seabios/t400_4mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/t400_4mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/t400_8mb/revision b/projects/coreboot/configs/seabios/t400_8mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/t400_8mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/t500_16mb/revision b/projects/coreboot/configs/seabios/t500_16mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/t500_16mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/t500_4mb/revision b/projects/coreboot/configs/seabios/t500_4mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/t500_4mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/t500_8mb/revision b/projects/coreboot/configs/seabios/t500_8mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/t500_8mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/t60/revision b/projects/coreboot/configs/seabios/t60/revision deleted file mode 100644 index 1ab8299e..00000000 --- a/projects/coreboot/configs/seabios/t60/revision +++ /dev/null @@ -1 +0,0 @@ -2a3434757ef425dbdfedf1fc69e1a033a6e7310d diff --git a/projects/coreboot/configs/seabios/w500_16mb/revision b/projects/coreboot/configs/seabios/w500_16mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/w500_16mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/w500_4mb/revision b/projects/coreboot/configs/seabios/w500_4mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/w500_4mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/w500_8mb/revision b/projects/coreboot/configs/seabios/w500_8mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/w500_8mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/x200_16mb/revision b/projects/coreboot/configs/seabios/x200_16mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/x200_16mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/x200_4mb/revision b/projects/coreboot/configs/seabios/x200_4mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/x200_4mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/x200_8mb/revision b/projects/coreboot/configs/seabios/x200_8mb/revision deleted file mode 100644 index d4e47be8..00000000 --- a/projects/coreboot/configs/seabios/x200_8mb/revision +++ /dev/null @@ -1 +0,0 @@ -d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/projects/coreboot/configs/seabios/x60/revision b/projects/coreboot/configs/seabios/x60/revision deleted file mode 100644 index 1ab8299e..00000000 --- a/projects/coreboot/configs/seabios/x60/revision +++ /dev/null @@ -1 +0,0 @@ -2a3434757ef425dbdfedf1fc69e1a033a6e7310d -- cgit v1.2.3-70-g09d2 From bddb45d1e7962d538fd67c58102cbb15b87389ec Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Fri, 22 Dec 2017 20:24:12 -0500 Subject: Bring bucts source files into libreboot tree Considering bucts is no longer maintained by Peter Stuge--its original author--and it being integral to Librebooting the X60/T60, it seems best for bucts to be merged into the main Libreboot repository. --- projects/bucts/sources/Makefile | 20 +++++ projects/bucts/sources/bucts.c | 191 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 211 insertions(+) create mode 100644 projects/bucts/sources/Makefile create mode 100644 projects/bucts/sources/bucts.c diff --git a/projects/bucts/sources/Makefile b/projects/bucts/sources/Makefile new file mode 100644 index 00000000..b5f43d5f --- /dev/null +++ b/projects/bucts/sources/Makefile @@ -0,0 +1,20 @@ +CC:=gcc +OBJ:=bucts.o +VERSION:=withoutgit + +ifeq ($(shell uname), FreeBSD) + CFLAGS = -I/usr/local/include + LDFLAGS = -L/usr/local/lib +endif + +all: bucts + +bucts: $(OBJ) + $(CC) -o $@ $(OBJ) $(LDFLAGS) -lpci + +%.o: %.c + $(CC) $(CFLAGS) -DVERSION='"$(VERSION)"' -c $< + +.PHONY: clean +clean: + rm -f bucts $(OBJ) diff --git a/projects/bucts/sources/bucts.c b/projects/bucts/sources/bucts.c new file mode 100644 index 00000000..16e82c7a --- /dev/null +++ b/projects/bucts/sources/bucts.c @@ -0,0 +1,191 @@ +/* compile: gcc -s -o bucts bucts.c -lpci or: make + * run as root: ./bucts [0|1] + */ +/* + * Copyright (C) 2011 Peter Stuge + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(__GLIBC__) +#include +#endif +#include + +#if defined (__sun) && (defined(__i386) || defined(__amd64)) +#define MEM_DEV "/dev/xsvc" +#else +#define MEM_DEV "/dev/mem" +#endif + +static int fd_mem=-1; + +static void *sys_physmap(unsigned long phys_addr, size_t len) { + void *virt_addr = mmap(0, len, PROT_WRITE|PROT_READ, MAP_SHARED, fd_mem, (off_t)phys_addr); + return MAP_FAILED == virt_addr ? NULL : virt_addr; +} + +static void physunmap(void *virt_addr, size_t len) { + if (!len) { + printf("Not unmapping zero size at %p\n", virt_addr); + return; + } + munmap(virt_addr, len); +} + +static void *physmap(const char *descr, unsigned long phys_addr, size_t len) { + void *virt_addr; + + if (!descr) + descr = "memory"; + + if (!len) { + printf("Not mapping %s, zero size at 0x%08lx.\n", descr, phys_addr); + return NULL; + } + + if ((getpagesize() - 1) & len) + fprintf(stderr, "Unaligned size 0x%lx for %s at 0x%08lx!\n", (unsigned long)len, descr, phys_addr); + + if ((getpagesize() - 1) & phys_addr) + fprintf(stderr, "Unaligned address 0x%08lx for %s!\n", phys_addr, descr); + + virt_addr = sys_physmap(phys_addr, len); + if (!virt_addr) { + fprintf(stderr, "Error accessing 0x%lx bytes %s at 0x%08lx!\n", (unsigned long)len, descr, phys_addr); + perror("mmap(" MEM_DEV ")"); + if (EINVAL == errno) { + fprintf(stderr, "\n"); + fprintf(stderr, "In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),\n"); + fprintf(stderr, "CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.\n"); + fprintf(stderr, "Please check if either is enabled in your kernel before reporting a failure.\n"); + fprintf(stderr, "You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n"); + fprintf(stderr, "disabling the other option unfortunately requires a kernel recompile. Sorry!\n"); + } + } + + return virt_addr; +} + +int bucts(struct pci_dev *sb, int8_t newts) { + uint8_t buc, ts; + uint32_t rcba_addr; + volatile uint8_t *rcba; + const char *str[2]={ + "128kb address range 0xFFFE0000-0xFFFFFFFF is untranslated", + "64kb address ranges at 0xFFFE0000 and 0xFFFF0000 are swapped" + }; + + switch (sb->device_id) { + case 0x27b9: + rcba_addr = pci_read_long(sb, 0xf0) & ~1; + break; + default: + fprintf(stderr, "Unsupported LPC bridge. Sorry.\n"); + return 1; + } + + rcba = physmap("RCBA", rcba_addr, 0x4000); + if (!rcba) + return 1; + + buc = rcba[0x3414]; + ts = buc & 1; + printf("Current BUC.TS=%d - %s\n", ts, str[ts]); + + if (0 == newts || 1 == newts) { + if (ts == newts) { + printf("Not writing BUC register since TS is already correct.\n"); + goto unmap; + } + buc &= ~1; + buc |= newts; + rcba[0x3414] = buc; + buc = rcba[0x3414]; + ts = buc & 1; + printf("Updated BUC.TS=%d - %s\n", ts, str[ts]); + } + +unmap: + physunmap((void *)rcba, 0x4000); + return 0; +} + +int main(int argc, const char *argv[], const char *envp[]) { + int ret; + char *endp; + int8_t newts = -1; + struct pci_access *pacc; + struct pci_dev *dev, *sb = NULL; +#if defined(__FreeBSD__) + int io_fd; +#endif + + printf("bucts utility version '" VERSION "'\n"); + +#if defined(__FreeBSD__) + if ((io_fd = open("/dev/io", O_RDWR)) < 0) { + perror("open(/dev/io)"); +#else + if (iopl(3)) { + perror("iopl"); +#endif + printf("You need to be root.\n"); + return 1; + } + + if (-1 == (fd_mem = open(MEM_DEV, O_RDWR|O_SYNC))) { + perror("Error: open(" MEM_DEV ")"); + return 1; + } + + pacc=pci_alloc(); + pci_init(pacc); + pci_scan_bus(pacc); + for (dev=pacc->devices; dev && !sb; dev=dev->next) { + pci_fill_info(dev, PCI_FILL_IDENT|PCI_FILL_CLASS); + if (dev->vendor_id != 0x8086 || dev->device_class != 0x0601) + continue; + sb = dev; + } + if (!sb) { + fprintf(stderr, "Error: LPC bridge not found!\n"); + return 1; + } + + printf("Using LPC bridge %04x:%04x at %02x%02x:%02x.%02x\n", sb->vendor_id, sb->device_id, sb->domain, sb->bus, sb->dev, sb->func); + + if (argc > 1) { + newts = strtoul(argv[1], &endp, 10); + if (endp == argv[1]) { + fprintf(stderr, "Invalid new TS value '%s', please specify 0 or 1.\n", argv[1]); + newts = -1; + } + } + + ret = bucts(sb, newts); + + close(fd_mem); + return ret; +} -- cgit v1.2.3-70-g09d2 From 5100c4e7e9cc5e06cf32e06a5a0bd0d79d7655c6 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Fri, 22 Dec 2017 20:35:04 -0500 Subject: Statically link bucts --- projects/bucts/sources/Makefile | 2 +- projects/bucts/sources/bucts.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/bucts/sources/Makefile b/projects/bucts/sources/Makefile index b5f43d5f..2b165f3e 100644 --- a/projects/bucts/sources/Makefile +++ b/projects/bucts/sources/Makefile @@ -10,7 +10,7 @@ endif all: bucts bucts: $(OBJ) - $(CC) -o $@ $(OBJ) $(LDFLAGS) -lpci + $(CC) -o $@ $(OBJ) $(LDFLAGS) -lpci -lz -static %.o: %.c $(CC) $(CFLAGS) -DVERSION='"$(VERSION)"' -c $< diff --git a/projects/bucts/sources/bucts.c b/projects/bucts/sources/bucts.c index 16e82c7a..9e3c1708 100644 --- a/projects/bucts/sources/bucts.c +++ b/projects/bucts/sources/bucts.c @@ -1,4 +1,4 @@ -/* compile: gcc -s -o bucts bucts.c -lpci or: make +/* compile: gcc -s -o bucts bucts.c -lpci -lz -static or: make * run as root: ./bucts [0|1] */ /* -- cgit v1.2.3-70-g09d2 From 179e8629b590e7bb17b1664acf71482e267ff323 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Fri, 22 Dec 2017 20:38:59 -0500 Subject: Delete obsolete bucts patches --- .../patches/0001-Makefile-don-t-use-git.patch | 24 ---------------------- projects/bucts/patches/staticlink.diff | 13 ------------ 2 files changed, 37 deletions(-) delete mode 100644 projects/bucts/patches/0001-Makefile-don-t-use-git.patch delete mode 100644 projects/bucts/patches/staticlink.diff diff --git a/projects/bucts/patches/0001-Makefile-don-t-use-git.patch b/projects/bucts/patches/0001-Makefile-don-t-use-git.patch deleted file mode 100644 index 9a0e719c..00000000 --- a/projects/bucts/patches/0001-Makefile-don-t-use-git.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 63312528ea81207865077ab2c75963e3660859f0 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Sat, 14 Feb 2015 00:56:43 +0000 -Subject: [PATCH] Makefile: don't use git - ---- - Makefile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/Makefile b/Makefile -index 68541e6..b5f43d5 100644 ---- a/Makefile -+++ b/Makefile -@@ -1,6 +1,6 @@ - CC:=gcc - OBJ:=bucts.o --VERSION:=$(shell git describe) -+VERSION:=withoutgit - - ifeq ($(shell uname), FreeBSD) - CFLAGS = -I/usr/local/include --- -1.9.1 - diff --git a/projects/bucts/patches/staticlink.diff b/projects/bucts/patches/staticlink.diff deleted file mode 100644 index 52da8cc8..00000000 --- a/projects/bucts/patches/staticlink.diff +++ /dev/null @@ -1,13 +0,0 @@ -diff --git a/Makefile b/Makefile -index 68541e6..b8579eb 100644 ---- a/Makefile -+++ b/Makefile -@@ -10,7 +10,7 @@ endif - all: bucts - - bucts: $(OBJ) -- $(CC) -o $@ $(OBJ) $(LDFLAGS) -lpci -+ $(CC) -o $@ $(OBJ) $(LDFLAGS) -lpci -lz -static - - %.o: %.c - $(CC) $(CFLAGS) -DVERSION='"$(VERSION)"' -c $< -- cgit v1.2.3-70-g09d2 From 5cb6c2e097f403c421bddf06bb278c9969727b6f Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Fri, 22 Dec 2017 20:45:03 -0500 Subject: Remove bucts' download(), download_check() actions bucts is now merged in-tree, so the download() and download_check() actions are no longer necessary. --- projects/bucts/bucts | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/projects/bucts/bucts b/projects/bucts/bucts index 4456bb55..4b5d81bb 100644 --- a/projects/bucts/bucts +++ b/projects/bucts/bucts @@ -24,18 +24,6 @@ usage() { project_usage_arguments "$project" "$@" } -download() { - local repository="$project" - - project_download_git "$project" "$repository" 'https://notabug.org/libreboot/bucts.git' "$@" -} - -download_check() { - local repository="$project" - - project_download_check_git "$project" "$repository" "$@" -} - extract() { local repository="$project" -- cgit v1.2.3-70-g09d2 From c3aefd82ce5e458aed30419e58d55e60d33fa2ad Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Sat, 23 Dec 2017 19:52:25 +0100 Subject: Revert "Statically link bucts" This reverts commit 5100c4e7e9cc5e06cf32e06a5a0bd0d79d7655c6. We do not have yet libc and other deps for bucts inside libreboot --- projects/bucts/sources/Makefile | 2 +- projects/bucts/sources/bucts.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/bucts/sources/Makefile b/projects/bucts/sources/Makefile index 2b165f3e..b5f43d5f 100644 --- a/projects/bucts/sources/Makefile +++ b/projects/bucts/sources/Makefile @@ -10,7 +10,7 @@ endif all: bucts bucts: $(OBJ) - $(CC) -o $@ $(OBJ) $(LDFLAGS) -lpci -lz -static + $(CC) -o $@ $(OBJ) $(LDFLAGS) -lpci %.o: %.c $(CC) $(CFLAGS) -DVERSION='"$(VERSION)"' -c $< diff --git a/projects/bucts/sources/bucts.c b/projects/bucts/sources/bucts.c index 9e3c1708..16e82c7a 100644 --- a/projects/bucts/sources/bucts.c +++ b/projects/bucts/sources/bucts.c @@ -1,4 +1,4 @@ -/* compile: gcc -s -o bucts bucts.c -lpci -lz -static or: make +/* compile: gcc -s -o bucts bucts.c -lpci or: make * run as root: ./bucts [0|1] */ /* -- cgit v1.2.3-70-g09d2 From d65b8801af25c7581041d01479f03c3c6bd34cb6 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Wed, 3 Jan 2018 21:32:56 -0500 Subject: Prefer canonical flashrom repository over mirror --- projects/flashrom/flashrom | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/flashrom/flashrom b/projects/flashrom/flashrom index bc3199f0..e01b66be 100755 --- a/projects/flashrom/flashrom +++ b/projects/flashrom/flashrom @@ -27,7 +27,7 @@ usage() { download() { local repository=$project - project_download_git "$project" "$repository" "https://github.com/stefanct/flashrom.git" "$@" + project_download_git "$project" "$repository" 'https://review.coreboot.org/flashrom.git https://github.com/stefanct/flashrom.git' "$@" } download_check() { -- cgit v1.2.3-70-g09d2 From e8867d9fb6ac37d660a2239e7a362c6ad6b81571 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Wed, 3 Jan 2018 21:36:03 -0500 Subject: Bump flashrom revision to v1.0 --- projects/flashrom/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/flashrom/configs/revision b/projects/flashrom/configs/revision index 8031930e..6b3126ce 100644 --- a/projects/flashrom/configs/revision +++ b/projects/flashrom/configs/revision @@ -1 +1 @@ -v0.9.9 +v1.0 -- cgit v1.2.3-70-g09d2 From e5ba29629a36bbe91c78e8877005a502e0e67c95 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 11 Jan 2018 21:16:33 -0500 Subject: Update Coreboot config for board d510mo This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * UART_PCI_ADDR=0x0 --- projects/coreboot/configs/seabios/d510mo/config | 312 ++++++++++++++++-------- 1 file changed, 217 insertions(+), 95 deletions(-) diff --git a/projects/coreboot/configs/seabios/d510mo/config b/projects/coreboot/configs/seabios/d510mo/config index 168919ef..1000508c 100644 --- a/projects/coreboot/configs/seabios/d510mo/config +++ b/projects/coreboot/configs/seabios/d510mo/config @@ -6,44 +6,37 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_USE_OPTION_TABLE is not set CONFIG_COMPRESS_RAMSTAGE=y -# CONFIG_COMPRESS_PRERAM_STAGES is not set CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_EARLY_CBMEM_INIT is not set # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -CONFIG_FLASHMAP_OFFSET=0 -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_ACPI_SATA_GENERATOR is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set @@ -57,16 +50,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -83,6 +78,7 @@ CONFIG_VENDOR_INTEL=y # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -94,6 +90,7 @@ CONFIG_VENDOR_INTEL=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -105,56 +102,73 @@ CONFIG_VENDOR_INTEL=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="intel/d510mo" CONFIG_MAINBOARD_PART_NUMBER="D510MO" CONFIG_MAINBOARD_VENDOR="Intel" CONFIG_MAX_CPUS=4 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 +CONFIG_CBFS_SIZE=0x100000 CONFIG_VGA_BIOS_ID="8086,a001" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -# CONFIG_UDELAY_IO is not set CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" -CONFIG_DCACHE_RAM_BASE=0xffafc000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x4000 -CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel" +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y CONFIG_ID_SECTION_OFFSET=0x80 -CONFIG_RAMTOP=0x200000 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 -CONFIG_CBFS_SIZE=0x100000 CONFIG_POST_DEVICE=y +# CONFIG_VBOOT is not set +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set -# CONFIG_BOARD_INTEL_BAKERSPORT_FSP is not set # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set +# CONFIG_BOARD_INTEL_BAKERSPORT_FSP is not set # CONFIG_BOARD_INTEL_BAYLEYBAY_FSP is not set +# CONFIG_BOARD_INTEL_CAMELBACKMOUNTAIN_FSP is not set +# CONFIG_BOARD_INTEL_CANNONLAKE_RVPU is not set +# CONFIG_BOARD_INTEL_CANNONLAKE_RVPY is not set # CONFIG_BOARD_INTEL_COUGAR_CANYON2 is not set CONFIG_BOARD_INTEL_D510MO=y # CONFIG_BOARD_INTEL_D810E2CB is not set # CONFIG_BOARD_INTEL_D945GCLF is not set +# CONFIG_BOARD_INTEL_DG43GT is not set # CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set # CONFIG_BOARD_INTEL_GALILEO is not set +# CONFIG_BOARD_INTEL_GLKRVP is not set +# CONFIG_BOARD_INTEL_HARCUVAR is not set +# CONFIG_BOARD_INTEL_KBLRVP3 is not set +# CONFIG_BOARD_INTEL_KBLRVP7 is not set # CONFIG_BOARD_INTEL_KUNIMITSU is not set +# CONFIG_BOARD_INTEL_LEAFHILL is not set # CONFIG_BOARD_INTEL_LITTLEPLAINS is not set +# CONFIG_BOARD_INTEL_MINNOW3 is not set # CONFIG_BOARD_INTEL_MINNOWMAX is not set # CONFIG_BOARD_INTEL_MOHONPEAK is not set # CONFIG_BOARD_INTEL_MTARVON is not set +# CONFIG_BOARD_INTEL_SKLSDLBRK is not set # CONFIG_BOARD_INTEL_STARGO2 is not set # CONFIG_BOARD_INTEL_STRAGO is not set # CONFIG_BOARD_INTEL_TRUXTON is not set # CONFIG_BOARD_INTEL_WTM2 is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_INTEL_BASEBOARD_GLKRVP is not set CONFIG_CPU_ADDR_BITS=32 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set -CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -165,11 +179,14 @@ CONFIG_COREBOOT_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=1024 CONFIG_ROM_SIZE=0x100000 -CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set # CONFIG_SYSTEM_TYPE_LAPTOP is not set # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -180,20 +197,37 @@ CONFIG_FMDFILE="" # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/pineview/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_HEAP_SIZE=0x4000 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set # CONFIG_SOC_UCB_RISCV is not set @@ -213,25 +247,30 @@ CONFIG_CPU_INTEL_SOCKET_FCBGA559=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set CONFIG_UDELAY_LAPIC=y CONFIG_LAPIC_MONOTONIC_TIMER=y # CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set -# CONFIG_TSC_CALIBRATE_WITH_IO is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_SMM_TSEG is not set # CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set CONFIG_SERIALIZED_SMM_INITIALIZATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set -# CONFIG_PARALLEL_MP is not set -# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -246,15 +285,14 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y CONFIG_HPET_ADDRESS=0xfed00000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_MAX_PIRQ_LINKS=4 # @@ -264,12 +302,18 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y # # Super I/O # +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE=y CONFIG_SUPERIO_WINBOND_W83627THG=y @@ -277,7 +321,10 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y # Embedded Controllers # # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set # CONFIG_ARCH_VERSTAGE_ARM is not set @@ -293,6 +340,10 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -331,108 +382,160 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_USE_MARCH_586 is not set CONFIG_AP_IN_SIPI_WAIT=y CONFIG_SIPI_VECTOR_IN_ROM=y -CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y # CONFIG_ROMCC is not set -CONFIG_LATE_CBMEM_INIT=y +# CONFIG_CBMEM_TOP_BACKUP is not set +# CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y -# CONFIG_HAVE_CMOS_DEFAULT is not set +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set -# CONFIG_COMPILE_IN_DSDT is not set -CONFIG_ROMSTAGE_ADDR=0x2000000 -CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -# CONFIG_PXE_ROM is not set +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# - # # Generic Drivers # # CONFIG_DRIVERS_AS3722_RTC is not set # CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_SMM is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVERS_AMD_PI is not set # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +CONFIG_DRIVERS_I2C_CK505=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y -# CONFIG_INTEL_GMA_ACPI is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set # CONFIG_DRIVER_INTEL_I210 is not set -# CONFIG_IPMI_KCS is not set -# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set -# CONFIG_SPI_FLASH is not set -# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set -# CONFIG_DRIVERS_UART is not set -# CONFIG_NO_UART_ON_SUPERIO is not set -# CONFIG_DRIVERS_UART_8250MEM is not set -# CONFIG_DRIVERS_UART_8250MEM_32 is not set -# CONFIG_HAVE_UART_SPECIAL is not set -# CONFIG_DRIVERS_UART_OXPCIE is not set -# CONFIG_DRIVERS_UART_PL011 is not set -CONFIG_HAVE_USBDEBUG=y -# CONFIG_HAVE_USBDEBUG_OPTIONS is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set -CONFIG_RTC=y +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set -CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -449,7 +552,10 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set -# CONFIG_HAVE_ACPI_RESUME is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set @@ -457,13 +563,12 @@ CONFIG_HAVE_HARD_RESET=y CONFIG_HAVE_MONOTONIC_TIMER=y # CONFIG_GENERIC_UDELAY is not set # CONFIG_TIMER_QUEUE is not set -# CONFIG_HAVE_OPTION_TABLE is not set +CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_COMMON_FADT=y @@ -482,6 +587,7 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO" # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -490,10 +596,17 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# # CONFIG_COREINFO_SECONDARY_PAYLOAD is not set # CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set # # Debugging @@ -503,19 +616,28 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # CONFIG_REG_SCRIPT is not set -# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From c91fc33d02a77832801f980065d2d9488d875179 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 11 Jan 2018 21:17:56 -0500 Subject: Update Coreboot config for board d945gclf This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y --- projects/coreboot/configs/seabios/d945gclf/config | 229 ++++++++++++++-------- 1 file changed, 152 insertions(+), 77 deletions(-) diff --git a/projects/coreboot/configs/seabios/d945gclf/config b/projects/coreboot/configs/seabios/d945gclf/config index 2cb14518..b009e240 100644 --- a/projects/coreboot/configs/seabios/d945gclf/config +++ b/projects/coreboot/configs/seabios/d945gclf/config @@ -6,6 +6,7 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" CONFIG_COMPILER_GCC=y @@ -13,37 +14,26 @@ CONFIG_COMPILER_GCC=y # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y # CONFIG_STATIC_OPTION_TABLE is not set -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y -# CONFIG_EARLY_CBMEM_LIST is not set # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -CONFIG_DEVICETREE="devicetree.cb" -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -61,16 +51,18 @@ CONFIG_DEVICETREE="devicetree.cb" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -87,6 +79,7 @@ CONFIG_VENDOR_INTEL=y # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -98,6 +91,7 @@ CONFIG_VENDOR_INTEL=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -109,6 +103,7 @@ CONFIG_VENDOR_INTEL=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="intel/d945gclf" @@ -116,60 +111,68 @@ CONFIG_MAINBOARD_PART_NUMBER="D945GCLF" CONFIG_IRQ_SLOT_COUNT=18 CONFIG_MAINBOARD_VENDOR="Intel" CONFIG_MAX_CPUS=4 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0x80000 CONFIG_UART_FOR_CONSOLE=0 -CONFIG_VGA_BIOS_ID="8086,27a2" +CONFIG_VGA_BIOS_ID="8086,2772" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 -# CONFIG_HAS_LVDS is not set -CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel" +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y CONFIG_ID_SECTION_OFFSET=0x80 -# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set -# CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set -# CONFIG_BOARD_EMULATION_QEMU_POWER8 is not set -# CONFIG_BOARD_EMULATION_QEMU_X86_Q35 is not set -# CONFIG_BOARD_EMULATION_QEMU_UCB_RISCV is not set -# CONFIG_BOARD_EMULATION_SPIKE_UCB_RISCV is not set CONFIG_POST_DEVICE=y -# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_VBOOT is not set +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_TTYS0_LCS=3 -# CONFIG_BOARD_INTEL_AMENIA is not set # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set -# CONFIG_BOARD_INTEL_BAKERSPORT_FSP is not set # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set +# CONFIG_BOARD_INTEL_BAKERSPORT_FSP is not set # CONFIG_BOARD_INTEL_BAYLEYBAY_FSP is not set # CONFIG_BOARD_INTEL_CAMELBACKMOUNTAIN_FSP is not set +# CONFIG_BOARD_INTEL_CANNONLAKE_RVPU is not set +# CONFIG_BOARD_INTEL_CANNONLAKE_RVPY is not set # CONFIG_BOARD_INTEL_COUGAR_CANYON2 is not set # CONFIG_BOARD_INTEL_D510MO is not set # CONFIG_BOARD_INTEL_D810E2CB is not set CONFIG_BOARD_INTEL_D945GCLF=y +# CONFIG_BOARD_INTEL_DG43GT is not set # CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set # CONFIG_BOARD_INTEL_GALILEO is not set +# CONFIG_BOARD_INTEL_GLKRVP is not set +# CONFIG_BOARD_INTEL_HARCUVAR is not set +# CONFIG_BOARD_INTEL_KBLRVP3 is not set +# CONFIG_BOARD_INTEL_KBLRVP7 is not set # CONFIG_BOARD_INTEL_KUNIMITSU is not set +# CONFIG_BOARD_INTEL_LEAFHILL is not set # CONFIG_BOARD_INTEL_LITTLEPLAINS is not set +# CONFIG_BOARD_INTEL_MINNOW3 is not set # CONFIG_BOARD_INTEL_MINNOWMAX is not set # CONFIG_BOARD_INTEL_MOHONPEAK is not set # CONFIG_BOARD_INTEL_MTARVON is not set +# CONFIG_BOARD_INTEL_SKLSDLBRK is not set # CONFIG_BOARD_INTEL_STARGO2 is not set # CONFIG_BOARD_INTEL_STRAGO is not set # CONFIG_BOARD_INTEL_TRUXTON is not set # CONFIG_BOARD_INTEL_WTM2 is not set -# CONFIG_CONSOLE_POST is not set CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_INTEL_BASEBOARD_GLKRVP is not set CONFIG_CPU_ADDR_BITS=32 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 CONFIG_BOARD_ROMSIZE_KB_512=y @@ -181,13 +184,13 @@ CONFIG_COREBOOT_ROMSIZE_KB_512=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=512 CONFIG_ROM_SIZE=0x80000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set # CONFIG_SYSTEM_TYPE_LAPTOP is not set # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -199,22 +202,32 @@ CONFIG_FMDFILE="" # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" CONFIG_TTYS0_BASE=0x3f8 -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set +CONFIG_TTYS0_BAUD=115200 # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set @@ -241,6 +254,9 @@ CONFIG_SSE2=y CONFIG_CPU_INTEL_SOCKET_441=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set @@ -261,6 +277,7 @@ CONFIG_SERIALIZED_SMM_INITIALIZATION=y # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set # CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -275,19 +292,19 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_I945=y CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y # CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM is not set +# CONFIG_I945_LVDS is not set CONFIG_CHANNEL_XOR_RANDOMIZATION=y # CONFIG_OVERRIDE_CLOCK_DISABLE is not set -CONFIG_CHECK_SLFRCS_ON_RESUME=y +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set CONFIG_HPET_ADDRESS=0xfed00000 CONFIG_MAX_PIRQ_LINKS=4 @@ -298,22 +315,25 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y # # Super I/O # +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set CONFIG_SUPERIO_SMSC_LPC47M15X=y # # Embedded Controllers # -CONFIG_VBOOT_VBNV_OFFSET=0x26 -# CONFIG_VBOOT_VBNV_CMOS is not set -# CONFIG_VBOOT_VBNV_EC is not set -# CONFIG_VBOOT is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set # CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set @@ -332,6 +352,10 @@ CONFIG_VBOOT_VBNV_OFFSET=0x26 # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -371,46 +395,53 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_SIPI_VECTOR_IN_ROM=y # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set -# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# - # # Generic Drivers # @@ -418,11 +449,29 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set -# CONFIG_REALTEK_8168_RESET is not set -# CONFIG_SPI_FLASH is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_SMM is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set @@ -434,39 +483,59 @@ CONFIG_DRIVERS_UART=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVERS_AMD_PI is not set # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y # CONFIG_INTEL_INT15 is not set CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set # CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set CONFIG_BOOT_DEVICE_SPI_FLASH=y CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y # CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console @@ -489,10 +558,10 @@ CONFIG_CONSOLE_SERIAL_115200=y # CONFIG_CONSOLE_SERIAL_38400 is not set # CONFIG_CONSOLE_SERIAL_19200 is not set # CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -503,12 +572,15 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set @@ -523,7 +595,6 @@ CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -552,9 +623,6 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" -# CONFIG_SEABIOS_STABLE is not set -# CONFIG_SEABIOS_MASTER is not set -# CONFIG_SEABIOS_REVISION is not set CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y @@ -578,16 +646,18 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set # CONFIG_DEBUG_PIRQ is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -596,3 +666,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From 8d429b808775bbdbe1adfe25a9fddb54c80db1bf Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sun, 14 Jan 2018 21:47:25 -0500 Subject: Update Coreboot config for board ga-g41m-es2l This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * VGA_TEXT_FRAMEBUFFER=y * REALTEK_8168_MACADDRESS="00:f5:f0:40:71:fe" --- .../coreboot/configs/seabios/ga-g41m-es2l/config | 232 ++++++++++++++------- 1 file changed, 160 insertions(+), 72 deletions(-) diff --git a/projects/coreboot/configs/seabios/ga-g41m-es2l/config b/projects/coreboot/configs/seabios/ga-g41m-es2l/config index 196aea73..ba81aa1d 100644 --- a/projects/coreboot/configs/seabios/ga-g41m-es2l/config +++ b/projects/coreboot/configs/seabios/ga-g41m-es2l/config @@ -6,42 +6,33 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +# CONFIG_UTIL_GENPARSER is not set +# CONFIG_USE_OPTION_TABLE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y -# CONFIG_EARLY_CBMEM_LIST is not set # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -59,16 +50,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set CONFIG_VENDOR_GIGABYTE=y # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -85,6 +78,7 @@ CONFIG_VENDOR_GIGABYTE=y # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -96,6 +90,7 @@ CONFIG_VENDOR_GIGABYTE=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -107,29 +102,33 @@ CONFIG_VENDOR_GIGABYTE=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="gigabyte/ga-g41m-es2l" CONFIG_MAINBOARD_PART_NUMBER="GA-G41M-ES2L" CONFIG_MAINBOARD_VENDOR="GIGABYTE" -CONFIG_MAX_CPUS=1 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_MAX_CPUS=4 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0x100000 CONFIG_VGA_BIOS_ID="8086,2e32" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" CONFIG_DCACHE_RAM_BASE=0xfeffc000 CONFIG_DCACHE_RAM_SIZE=0x4000 -CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="GIGABYTE" +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y # CONFIG_BOARD_GIGABYTE_GA_6BXC is not set # CONFIG_BOARD_GIGABYTE_GA_6BXE is not set +# CONFIG_BOARD_GIGABYTE_GA_945GCM_S2L is not set +# CONFIG_BOARD_GIGABYTE_GA_945GCM_S2C is not set # CONFIG_BOARD_GIGABYTE_GA_B75M_D3H is not set # CONFIG_BOARD_GIGABYTE_GA_B75M_D3V is not set CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y @@ -138,13 +137,17 @@ CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y # CONFIG_BOARD_GIGABYTE_MA785GM is not set # CONFIG_BOARD_GIGABYTE_MA785GMT is not set # CONFIG_BOARD_GIGABYTE_MA78GM is not set -# CONFIG_DRIVERS_PS2_KEYBOARD is not set -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -155,13 +158,13 @@ CONFIG_COREBOOT_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=1024 CONFIG_ROM_SIZE=0x100000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set # CONFIG_SYSTEM_TYPE_LAPTOP is not set # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -173,24 +176,32 @@ CONFIG_FMDFILE="" # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_PCIEXP_ASPM=y +# CONFIG_PCIEXP_COMMON_CLOCK is not set +CONFIG_PCIEXP_CLK_PM=y CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/x4x/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -210,7 +221,6 @@ CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set -CONFIG_CPU_INTEL_MODEL_6EX=y CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_CPU_INTEL_MODEL_1067X=y CONFIG_CPU_INTEL_MODEL_F3X=y @@ -219,12 +229,15 @@ CONFIG_SSE2=y CONFIG_CPU_INTEL_SOCKET_LGA775=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set CONFIG_UDELAY_LAPIC=y -# CONFIG_LAPIC_MONOTONIC_TIMER is not set +CONFIG_LAPIC_MONOTONIC_TIMER=y # CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set @@ -237,7 +250,9 @@ CONFIG_LOGICAL_CPUS=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -252,11 +267,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_X4X=y @@ -270,20 +284,31 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y # # Super I/O # CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE=y +CONFIG_SUPERIO_ITE_ENV_CTRL=y +CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y +CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y CONFIG_SUPERIO_ITE_IT8718F=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -300,6 +325,10 @@ CONFIG_SUPERIO_ITE_IT8718F=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -339,46 +368,55 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y CONFIG_AP_IN_SIPI_WAIT=y CONFIG_SIPI_VECTOR_IN_ROM=y # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set -# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set -# CONFIG_ON_DEVICE_ROM_LOAD is not set +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -CONFIG_PCIEXP_ASPM=y -CONFIG_PCIEXP_CLK_PM=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# - # # Generic Drivers # @@ -386,11 +424,31 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_CACHE_MRC_SETTINGS is not set CONFIG_REALTEK_8168_RESET=y -# CONFIG_SPI_FLASH is not set +CONFIG_REALTEK_8168_MACADDRESS="00:f5:f0:40:71:fe" +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_SMM is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set @@ -402,53 +460,70 @@ CONFIG_REALTEK_8168_RESET=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVERS_AMD_PI is not set # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y # CONFIG_INTEL_INT15 is not set CONFIG_INTEL_GMA_ACPI=y +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -459,24 +534,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set -# CONFIG_HAVE_ACPI_RESUME is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set -# CONFIG_HAVE_OPTION_TABLE is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_COMMON_FADT=y @@ -495,6 +575,7 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="GA-G41M-ES2L" # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -523,16 +604,18 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -541,3 +624,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From 1a9ed55beaf5bc10e18ff5bc1ae13a17e360e511 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 11 Jan 2018 21:20:20 -0500 Subject: Update Coreboot config for board kcma-d8 This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * SOUTHBRIDGE_AMD_SB700_33MHZ_SPI=y * UART_PCI_ADDR=0x0 --- projects/coreboot/configs/seabios/kcma-d8/config | 213 +++++++++++++++-------- 1 file changed, 143 insertions(+), 70 deletions(-) diff --git a/projects/coreboot/configs/seabios/kcma-d8/config b/projects/coreboot/configs/seabios/kcma-d8/config index 3ae9245a..3e851573 100644 --- a/projects/coreboot/configs/seabios/kcma-d8/config +++ b/projects/coreboot/configs/seabios/kcma-d8/config @@ -6,46 +6,38 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_UBSAN is not set # CONFIG_RELOCATABLE_RAMSTAGE is not set -CONFIG_FLASHMAP_OFFSET=0 -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_ACPI_SATA_GENERATOR is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set @@ -59,16 +51,18 @@ CONFIG_VENDOR_ASUS=y # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -85,6 +79,7 @@ CONFIG_VENDOR_ASUS=y # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -96,6 +91,7 @@ CONFIG_VENDOR_ASUS=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -107,25 +103,28 @@ CONFIG_VENDOR_ASUS=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="asus/kcma-d8" CONFIG_MAINBOARD_PART_NUMBER="KCMA-D8" CONFIG_IRQ_SLOT_COUNT=13 CONFIG_MAINBOARD_VENDOR="ASUS" -CONFIG_APIC_ID_OFFSET=0 -CONFIG_HW_MEM_HOLE_SIZEK=0x100000 CONFIG_MAX_CPUS=16 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 +CONFIG_CBFS_SIZE=0x200000 +CONFIG_APIC_ID_OFFSET=0x0 +CONFIG_HW_MEM_HOLE_SIZEK=0x100000 CONFIG_MAX_PHYSICAL_CPUS=2 # CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC is not set CONFIG_HT_CHAIN_END_UNITID_BASE=0x20 CONFIG_HT_CHAIN_UNITID_BASE=0x0 CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" CONFIG_DCACHE_RAM_BASE=0xc2000 CONFIG_DCACHE_RAM_SIZE=0x1e000 -CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" # CONFIG_BOARD_ASUS_A8N_E is not set # CONFIG_BOARD_ASUS_A8N_SLI is not set @@ -133,6 +132,7 @@ CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" # CONFIG_BOARD_ASUS_A8V_E_SE is not set # CONFIG_BOARD_ASUS_DSBF is not set # CONFIG_BOARD_ASUS_F2A85_M is not set +# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set # CONFIG_BOARD_ASUS_F2A85_M_LE is not set # CONFIG_BOARD_ASUS_K8V_X is not set CONFIG_BOARD_ASUS_KCMA_D8=y @@ -154,19 +154,21 @@ CONFIG_BOARD_ASUS_KCMA_D8=y # CONFIG_BOARD_ASUS_P2B_LS is not set # CONFIG_BOARD_ASUS_P2B is not set # CONFIG_BOARD_ASUS_P3B_F is not set +# CONFIG_BOARD_ASUS_P5GC_MX is not set +CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 # CONFIG_POST_IO is not set +CONFIG_DEVICETREE="devicetree.cb" CONFIG_AGP_APERTURE_SIZE=0x4000000 CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/asus/kcma-d8/bootblock.c" CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD=0x3f CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL=y CONFIG_MAX_REBOOT_CNT=10 CONFIG_ID_SECTION_OFFSET=0x80 -CONFIG_RAMTOP=0x400000 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 -CONFIG_CBFS_SIZE=0x200000 # CONFIG_POST_DEVICE is not set -CONFIG_BOOT_MEDIA_SPI_BUS=0 -CONFIG_CONSOLE_POST=y +# CONFIG_VBOOT is not set +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y CONFIG_UDELAY_LAPIC_FIXED_FSB=200 CONFIG_CPU_ADDR_BITS=48 @@ -174,6 +176,7 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -184,11 +187,14 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 CONFIG_ROM_SIZE=0x200000 -CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set # CONFIG_SYSTEM_TYPE_LAPTOP is not set # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -199,22 +205,36 @@ CONFIG_FMDFILE="" # # SoC # -# CONFIG_SOC_BROADCOM_CYGNUS is not set CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BUS_NUMBER=256 +CONFIG_RAMTOP=0x400000 +CONFIG_HEAP_SIZE=0xc0000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +# CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/amd/amdfam10/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/sb700/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_HEAP_SIZE=0xc0000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x14 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set # CONFIG_SOC_ROCKCHIP_RK3399 is not set @@ -263,15 +283,17 @@ CONFIG_UDELAY_LAPIC=y # CONFIG_UDELAY_TIMER2 is not set CONFIG_TSC_SYNC_LFENCE=y # CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_SMM_TSEG is not set # CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set # CONFIG_SERIALIZED_SMM_INITIALIZATION is not set CONFIG_X86_AMD_FIXED_MTRRS=y # CONFIG_PLATFORM_USES_FSP1_0 is not set -# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_SSE=y @@ -285,7 +307,6 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set -CONFIG_MMCONF_BUS_NUMBER=256 CONFIG_NORTHBRIDGE_AMD_AMDFAM10=y CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=y # CONFIG_HT_CHAIN_DISTRIBUTE is not set @@ -303,14 +324,12 @@ CONFIG_DIMM_VOLTAGE_SET_SUPPORT=y CONFIG_LIMIT_HT_DOWN_WIDTH_16=y # CONFIG_LIMIT_HT_UP_WIDTH_8 is not set CONFIG_LIMIT_HT_UP_WIDTH_16=y +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_HPET_ADDRESS=0xfed00000 -CONFIG_HPET_MIN_TICKS=0x14 CONFIG_MAX_PIRQ_LINKS=4 # @@ -321,16 +340,23 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_AMD_SB700=y CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI=y CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100=y # CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT is not set CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA=y CONFIG_SOUTHBRIDGE_AMD_SR5650=y # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set # # Super I/O # +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE=y CONFIG_SUPERIO_WINBOND_W83667HG_A=y @@ -338,7 +364,9 @@ CONFIG_SUPERIO_WINBOND_W83667HG_A=y # Embedded Controllers # # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -355,6 +383,10 @@ CONFIG_SUPERIO_WINBOND_W83667HG_A=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -394,37 +426,40 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_AP_IN_SIPI_WAIT is not set # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set -CONFIG_VERSTAGE_ADDR=0x2000000 # CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # -# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -# CONFIG_VGA_ROM_RUN is not set -CONFIG_ON_DEVICE_ROM_LOAD=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y # CONFIG_MULTIPLE_VGA_ADAPTERS is not set CONFIG_SMBUS_HAS_AUX_CHANNELS=y -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -CONFIG_PCIEXP_COMMON_CLOCK=y -CONFIG_PCIEXP_ASPM=y -CONFIG_PCIEXP_CLK_PM=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_SOFTWARE_I2C is not set @@ -433,13 +468,15 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # Generic Drivers # # CONFIG_DRIVERS_AS3722_RTC is not set -# CONFIG_ELOG is not set # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set CONFIG_SPI_FLASH=y -CONFIG_SPI_ATOMIC_SEQUENCING=y -CONFIG_SPI_FLASH_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set # CONFIG_SPI_FLASH_NO_FAST_READ is not set CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y @@ -452,63 +489,88 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set # CONFIG_DRIVERS_UART_8250MEM_32 is not set # CONFIG_HAVE_UART_SPECIAL is not set # CONFIG_DRIVERS_UART_OXPCIE is not set # CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y -# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_ASPEED_AST2050=y -CONFIG_DEVICE_SPECIFIC_OPTIONS=y CONFIG_DRIVERS_ASPEED_AST_COMMON=y # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set CONFIG_DRIVERS_I2C_W83795=y -# CONFIG_INTEL_DP is not set # CONFIG_INTEL_DDI is not set # CONFIG_INTEL_EDID is not set # CONFIG_INTEL_INT15 is not set # CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -519,8 +581,11 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +CONFIG_CONSOLE_POST=y # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +CONFIG_ACPI_HUGE_LOWMEM_BACKUP=y CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y @@ -535,7 +600,6 @@ CONFIG_HAVE_OPTION_TABLE=y CONFIG_PCI_IO_CFG_EXT=y CONFIG_IOAPIC=y # CONFIG_USE_WATCHDOG_ON_BOOT is not set -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -556,6 +620,7 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KCMA-D8" # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -564,6 +629,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set @@ -573,6 +639,7 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_COREINFO_SECONDARY_PAYLOAD is not set # CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set # CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set # # Debugging @@ -590,13 +657,19 @@ CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_ACPI is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set CONFIG_ENABLE_APIC_EXT_ID=y CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # CONFIG_REG_SCRIPT is not set -# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From c906fd9aed509bf212c5b141f2c20069f40aa997 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 11 Jan 2018 21:21:40 -0500 Subject: Update Coreboot config for board kfsn4-dre This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * VGA_TEXT_FRAMEBUFFER=y * UART_PCI_ADDR=0x0 --- projects/coreboot/configs/seabios/kfsn4-dre/config | 260 ++++++++++++++------- 1 file changed, 173 insertions(+), 87 deletions(-) diff --git a/projects/coreboot/configs/seabios/kfsn4-dre/config b/projects/coreboot/configs/seabios/kfsn4-dre/config index f554fbfb..f85275f7 100644 --- a/projects/coreboot/configs/seabios/kfsn4-dre/config +++ b/projects/coreboot/configs/seabios/kfsn4-dre/config @@ -6,46 +6,38 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_UBSAN is not set # CONFIG_RELOCATABLE_RAMSTAGE is not set -CONFIG_FLASHMAP_OFFSET=0 -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_ACPI_SATA_GENERATOR is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set @@ -59,16 +51,18 @@ CONFIG_VENDOR_ASUS=y # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -85,6 +79,7 @@ CONFIG_VENDOR_ASUS=y # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -96,6 +91,7 @@ CONFIG_VENDOR_ASUS=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -107,25 +103,29 @@ CONFIG_VENDOR_ASUS=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="asus/kfsn4-dre" CONFIG_MAINBOARD_PART_NUMBER="KFSN4-DRE" CONFIG_IRQ_SLOT_COUNT=13 CONFIG_MAINBOARD_VENDOR="ASUS" -CONFIG_APIC_ID_OFFSET=0 -CONFIG_HW_MEM_HOLE_SIZEK=0x100000 CONFIG_MAX_CPUS=12 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 +CONFIG_CBFS_SIZE=0x100000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_APIC_ID_OFFSET=0x0 +CONFIG_HW_MEM_HOLE_SIZEK=0x100000 CONFIG_MAX_PHYSICAL_CPUS=2 # CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC is not set CONFIG_HT_CHAIN_END_UNITID_BASE=0x20 CONFIG_HT_CHAIN_UNITID_BASE=0x0 CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" CONFIG_DCACHE_RAM_BASE=0xc4000 CONFIG_DCACHE_RAM_SIZE=0x0c000 -CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" # CONFIG_BOARD_ASUS_A8N_E is not set # CONFIG_BOARD_ASUS_A8N_SLI is not set @@ -133,6 +133,7 @@ CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" # CONFIG_BOARD_ASUS_A8V_E_SE is not set # CONFIG_BOARD_ASUS_DSBF is not set # CONFIG_BOARD_ASUS_F2A85_M is not set +# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set # CONFIG_BOARD_ASUS_F2A85_M_LE is not set # CONFIG_BOARD_ASUS_K8V_X is not set # CONFIG_BOARD_ASUS_KCMA_D8 is not set @@ -154,29 +155,31 @@ CONFIG_BOARD_ASUS_KFSN4_DRE=y # CONFIG_BOARD_ASUS_P2B_LS is not set # CONFIG_BOARD_ASUS_P2B is not set # CONFIG_BOARD_ASUS_P3B_F is not set +# CONFIG_BOARD_ASUS_P5GC_MX is not set +CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_AGP_APERTURE_SIZE=0x4000000 CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/asus/kfsn4-dre/bootblock.c" CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL=y CONFIG_MAX_REBOOT_CNT=10 CONFIG_CK804_PCI_E_X=1 CONFIG_CK804_PCIE_PME_WAKE=y -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y -CONFIG_UART_FOR_CONSOLE=0 +CONFIG_USBDEBUG_HCD_INDEX=0 CONFIG_ID_SECTION_OFFSET=0x80 -CONFIG_RAMTOP=0x400000 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 -CONFIG_CBFS_SIZE=0x100000 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=0 +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_TTYS0_LCS=3 +CONFIG_DRIVERS_UART_8250IO=y CONFIG_UDELAY_LAPIC_FIXED_FSB=200 CONFIG_CPU_ADDR_BITS=48 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 CONFIG_USBDEBUG=y CONFIG_MAINBOARD_VERSION="1.0" CONFIG_DRIVERS_PS2_KEYBOARD=y -CONFIG_DRIVERS_UART_8250IO=y +CONFIG_PCIEXP_L1_SUB_STATE=y # CONFIG_NO_POST is not set CONFIG_CK804_NUM=1 CONFIG_BOARD_ROMSIZE_KB_1024=y @@ -188,11 +191,14 @@ CONFIG_COREBOOT_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=1024 CONFIG_ROM_SIZE=0x100000 -CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set # CONFIG_SYSTEM_TYPE_LAPTOP is not set # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -203,24 +209,40 @@ CONFIG_FMDFILE="" # # SoC # -# CONFIG_SOC_BROADCOM_CYGNUS is not set CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BUS_NUMBER=256 +CONFIG_RAMTOP=0x400000 +CONFIG_HEAP_SIZE=0xc0000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +# CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/amd/amdfam10/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/nvidia/ck804/bootblock.c" CONFIG_TTYS0_BASE=0x3f8 -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_HEAP_SIZE=0xc0000 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0xfa +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set +CONFIG_TTYS0_BAUD=115200 # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set # CONFIG_SOC_UCB_RISCV is not set @@ -263,15 +285,17 @@ CONFIG_UDELAY_LAPIC=y # CONFIG_UDELAY_TIMER2 is not set CONFIG_TSC_SYNC_LFENCE=y # CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_SMM_TSEG is not set # CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set # CONFIG_SERIALIZED_SMM_INITIALIZATION is not set CONFIG_X86_AMD_FIXED_MTRRS=y # CONFIG_PLATFORM_USES_FSP1_0 is not set -# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_SSE=y @@ -285,7 +309,6 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set -CONFIG_MMCONF_BUS_NUMBER=256 CONFIG_NORTHBRIDGE_AMD_AMDFAM10=y # CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY is not set # CONFIG_HT_CHAIN_DISTRIBUTE is not set @@ -303,14 +326,12 @@ CONFIG_DIMM_REGISTERED=y CONFIG_LIMIT_HT_DOWN_WIDTH_16=y # CONFIG_LIMIT_HT_UP_WIDTH_8 is not set CONFIG_LIMIT_HT_UP_WIDTH_16=y +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_HPET_ADDRESS=0xfed00000 -CONFIG_HPET_MIN_TICKS=0xfa CONFIG_MAX_PIRQ_LINKS=4 # @@ -321,6 +342,11 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_NVIDIA_CK804=y # CONFIG_CK804_USE_NIC is not set # CONFIG_CK804_USE_ACI is not set @@ -329,6 +355,7 @@ CONFIG_CK804B_PCI_E_X=4 # # Super I/O # +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE=y CONFIG_SUPERIO_WINBOND_W83627THG=y @@ -336,7 +363,10 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y # Embedded Controllers # # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set # CONFIG_ARCH_VERSTAGE_ARM is not set @@ -352,6 +382,10 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -391,100 +425,141 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_AP_IN_SIPI_WAIT is not set # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set -# CONFIG_COMPILE_IN_DSDT is not set -CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -# CONFIG_NATIVE_VGA_INIT_USE_EDID is not set -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -CONFIG_PCIEXP_COMMON_CLOCK=y -CONFIG_PCIEXP_ASPM=y -CONFIG_PCIEXP_CLK_PM=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -# CONFIG_PXE_ROM is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # # CONFIG_DRIVERS_AS3722_RTC is not set -CONFIG_DEVICE_SPECIFIC_OPTIONS=y # CONFIG_GIC is not set -# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set -# CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_I2C_W83793=y -# CONFIG_INTEL_DP is not set -# CONFIG_INTEL_DDI is not set -# CONFIG_INTEL_EDID is not set -# CONFIG_INTEL_INT15 is not set -# CONFIG_INTEL_GMA_ACPI is not set -# CONFIG_DRIVER_INTEL_I210 is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_DRIVER_MAXIM_MAX77686 is not set -# CONFIG_DRIVER_PARADE_PS8625 is not set -# CONFIG_DRIVER_PARADE_PS8640 is not set -CONFIG_DRIVERS_MC146818=y -# CONFIG_MAINBOARD_HAS_LPC_TPM is not set -# CONFIG_DRIVERS_RICOH_RCE822 is not set -# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set -# CONFIG_DRIVER_TI_TPS65090 is not set -# CONFIG_DRIVERS_TI_TPS65913 is not set -# CONFIG_DRIVERS_TI_TPS65913_RTC is not set CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set # CONFIG_DRIVERS_UART_8250MEM_32 is not set # CONFIG_HAVE_UART_SPECIAL is not set # CONFIG_DRIVERS_UART_OXPCIE is not set # CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y # CONFIG_HAVE_USBDEBUG_OPTIONS is not set CONFIG_USBDEBUG_IN_ROMSTAGE=y CONFIG_USBDEBUG_DEFAULT_PORT=0 CONFIG_USBDEBUG_DONGLE_STD=y # CONFIG_USBDEBUG_DONGLE_BEAGLEBONE is not set -# CONFIG_USBDEBUG_DONGLE_BEAGLEBONE_BLACK is not set # CONFIG_USBDEBUG_DONGLE_FTDI_FT232H is not set CONFIG_USBDEBUG_OPTIONAL_HUB_PORT=0 +# CONFIG_DRIVERS_AMD_PI is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +CONFIG_DRIVERS_I2C_W83793=y +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set CONFIG_DRIVERS_XGI_Z79_COMMON=y CONFIG_DRIVERS_XGI_Z9S=y # CONFIG_DRIVER_XPOWERS_AXP209 is not set -CONFIG_RTC=y +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console @@ -507,12 +582,11 @@ CONFIG_CONSOLE_SERIAL_115200=y # CONFIG_CONSOLE_SERIAL_38400 is not set # CONFIG_CONSOLE_SERIAL_19200 is not set # CONFIG_CONSOLE_SERIAL_9600 is not set -CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set CONFIG_CONSOLE_USB=y # CONFIG_CONSOLE_NE2K is not set -CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -529,7 +603,9 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y # CONFIG_HAVE_ACPI_RESUME is not set +CONFIG_ACPI_HUGE_LOWMEM_BACKUP=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set @@ -543,7 +619,6 @@ CONFIG_HAVE_OPTION_TABLE=y CONFIG_PCI_IO_CFG_EXT=y CONFIG_IOAPIC=y # CONFIG_USE_WATCHDOG_ON_BOOT is not set -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -564,6 +639,7 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KFSN4-DRE" # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -572,6 +648,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set @@ -580,6 +657,8 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y # # CONFIG_COREINFO_SECONDARY_PAYLOAD is not set # CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set # # Debugging @@ -598,13 +677,20 @@ CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_ACPI is not set # CONFIG_DEBUG_USBDEBUG is not set # CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +CONFIG_NO_EDID_FILL_FB=y CONFIG_ENABLE_APIC_EXT_ID=y CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # CONFIG_REG_SCRIPT is not set -# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From 4fa03206f9bf98b17c3a4993055acafd351e98ee Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 11 Jan 2018 21:22:37 -0500 Subject: Update Coreboot config for board kgpe-d16 This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * SOUTHBRIDGE_AMD_SB700_33MHZ_SPI=y * UART_PCI_ADDR=0x0 --- projects/coreboot/configs/seabios/kgpe-d16/config | 217 +++++++++++++++------- 1 file changed, 146 insertions(+), 71 deletions(-) diff --git a/projects/coreboot/configs/seabios/kgpe-d16/config b/projects/coreboot/configs/seabios/kgpe-d16/config index db0ab7f1..5bc73835 100644 --- a/projects/coreboot/configs/seabios/kgpe-d16/config +++ b/projects/coreboot/configs/seabios/kgpe-d16/config @@ -6,46 +6,38 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_UBSAN is not set # CONFIG_RELOCATABLE_RAMSTAGE is not set -CONFIG_FLASHMAP_OFFSET=0 -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_ACPI_SATA_GENERATOR is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set @@ -59,16 +51,18 @@ CONFIG_VENDOR_ASUS=y # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -85,6 +79,7 @@ CONFIG_VENDOR_ASUS=y # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -96,6 +91,7 @@ CONFIG_VENDOR_ASUS=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -107,25 +103,29 @@ CONFIG_VENDOR_ASUS=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="asus/kgpe-d16" CONFIG_MAINBOARD_PART_NUMBER="KGPE-D16" CONFIG_IRQ_SLOT_COUNT=13 CONFIG_MAINBOARD_VENDOR="ASUS" -CONFIG_APIC_ID_OFFSET=0 -CONFIG_HW_MEM_HOLE_SIZEK=0x100000 CONFIG_MAX_CPUS=32 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 +CONFIG_CBFS_SIZE=0x200000 +CONFIG_APIC_ID_OFFSET=0x0 +CONFIG_HW_MEM_HOLE_SIZEK=0x100000 CONFIG_MAX_PHYSICAL_CPUS=4 # CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC is not set CONFIG_HT_CHAIN_END_UNITID_BASE=0x20 CONFIG_HT_CHAIN_UNITID_BASE=0x0 +CONFIG_VGA_BIOS_ID="1a03,2000" CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" CONFIG_DCACHE_RAM_BASE=0xc2000 CONFIG_DCACHE_RAM_SIZE=0x1e000 -CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" # CONFIG_BOARD_ASUS_A8N_E is not set # CONFIG_BOARD_ASUS_A8N_SLI is not set @@ -133,6 +133,7 @@ CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" # CONFIG_BOARD_ASUS_A8V_E_SE is not set # CONFIG_BOARD_ASUS_DSBF is not set # CONFIG_BOARD_ASUS_F2A85_M is not set +# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set # CONFIG_BOARD_ASUS_F2A85_M_LE is not set # CONFIG_BOARD_ASUS_K8V_X is not set # CONFIG_BOARD_ASUS_KCMA_D8 is not set @@ -154,19 +155,21 @@ CONFIG_BOARD_ASUS_KGPE_D16=y # CONFIG_BOARD_ASUS_P2B_LS is not set # CONFIG_BOARD_ASUS_P2B is not set # CONFIG_BOARD_ASUS_P3B_F is not set +# CONFIG_BOARD_ASUS_P5GC_MX is not set +CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 # CONFIG_POST_IO is not set +CONFIG_DEVICETREE="devicetree.cb" CONFIG_AGP_APERTURE_SIZE=0x4000000 CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/asus/kgpe-d16/bootblock.c" CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD=0x3f CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL=y CONFIG_MAX_REBOOT_CNT=10 CONFIG_ID_SECTION_OFFSET=0x80 -CONFIG_RAMTOP=0x400000 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 -CONFIG_CBFS_SIZE=0x200000 # CONFIG_POST_DEVICE is not set -CONFIG_BOOT_MEDIA_SPI_BUS=0 -CONFIG_CONSOLE_POST=y +# CONFIG_VBOOT is not set +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y CONFIG_UDELAY_LAPIC_FIXED_FSB=200 CONFIG_CPU_ADDR_BITS=48 @@ -174,6 +177,7 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -184,11 +188,14 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 CONFIG_ROM_SIZE=0x200000 -CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set # CONFIG_SYSTEM_TYPE_LAPTOP is not set # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -199,22 +206,36 @@ CONFIG_FMDFILE="" # # SoC # -# CONFIG_SOC_BROADCOM_CYGNUS is not set CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_MMCONF_BUS_NUMBER=256 +CONFIG_RAMTOP=0x400000 +CONFIG_HEAP_SIZE=0xc0000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +# CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/amd/amdfam10/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/sb700/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_HEAP_SIZE=0xc0000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x14 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set # CONFIG_SOC_ROCKCHIP_RK3399 is not set @@ -263,15 +284,17 @@ CONFIG_UDELAY_LAPIC=y # CONFIG_UDELAY_TIMER2 is not set CONFIG_TSC_SYNC_LFENCE=y # CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_SMM_TSEG is not set # CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set # CONFIG_SERIALIZED_SMM_INITIALIZATION is not set CONFIG_X86_AMD_FIXED_MTRRS=y # CONFIG_PLATFORM_USES_FSP1_0 is not set -# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_SSE=y @@ -285,7 +308,6 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set -CONFIG_MMCONF_BUS_NUMBER=256 CONFIG_NORTHBRIDGE_AMD_AMDFAM10=y CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=y # CONFIG_HT_CHAIN_DISTRIBUTE is not set @@ -303,14 +325,12 @@ CONFIG_DIMM_VOLTAGE_SET_SUPPORT=y CONFIG_LIMIT_HT_DOWN_WIDTH_16=y # CONFIG_LIMIT_HT_UP_WIDTH_8 is not set CONFIG_LIMIT_HT_UP_WIDTH_16=y +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_HPET_ADDRESS=0xfed00000 -CONFIG_HPET_MIN_TICKS=0x14 CONFIG_MAX_PIRQ_LINKS=4 # @@ -321,16 +341,23 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_AMD_SB700=y CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI=y CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100=y # CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT is not set CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA=y CONFIG_SOUTHBRIDGE_AMD_SR5650=y # CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set # # Super I/O # +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE=y CONFIG_SUPERIO_WINBOND_W83667HG_A=y @@ -338,7 +365,9 @@ CONFIG_SUPERIO_WINBOND_W83667HG_A=y # Embedded Controllers # # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -355,6 +384,10 @@ CONFIG_SUPERIO_WINBOND_W83667HG_A=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -394,37 +427,40 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_AP_IN_SIPI_WAIT is not set # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set -CONFIG_VERSTAGE_ADDR=0x2000000 # CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # -# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -# CONFIG_VGA_ROM_RUN is not set -CONFIG_ON_DEVICE_ROM_LOAD=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y # CONFIG_MULTIPLE_VGA_ADAPTERS is not set CONFIG_SMBUS_HAS_AUX_CHANNELS=y -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT=y CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -CONFIG_PCIEXP_COMMON_CLOCK=y -CONFIG_PCIEXP_ASPM=y -CONFIG_PCIEXP_CLK_PM=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -CONFIG_PCIEXP_L1_SUB_STATE=y CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_SOFTWARE_I2C is not set @@ -433,13 +469,15 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # Generic Drivers # # CONFIG_DRIVERS_AS3722_RTC is not set -# CONFIG_ELOG is not set # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set CONFIG_SPI_FLASH=y -CONFIG_SPI_ATOMIC_SEQUENCING=y -CONFIG_SPI_FLASH_MEMORY_MAPPED=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set # CONFIG_SPI_FLASH_NO_FAST_READ is not set CONFIG_SPI_FLASH_ADESTO=y CONFIG_SPI_FLASH_AMIC=y @@ -452,63 +490,89 @@ CONFIG_SPI_FLASH_SST=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y # CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set # CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set # CONFIG_DRIVERS_UART_8250MEM_32 is not set # CONFIG_HAVE_UART_SPECIAL is not set # CONFIG_DRIVERS_UART_OXPCIE is not set # CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y -# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_ASPEED_AST2050=y -CONFIG_DEVICE_SPECIFIC_OPTIONS=y CONFIG_DRIVERS_ASPEED_AST_COMMON=y # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set CONFIG_DRIVERS_I2C_W83795=y -# CONFIG_INTEL_DP is not set # CONFIG_INTEL_DDI is not set # CONFIG_INTEL_EDID is not set # CONFIG_INTEL_INT15 is not set # CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y -# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_MAINBOARD_HAS_LPC_TPM=y +# CONFIG_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -519,8 +583,11 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +CONFIG_CONSOLE_POST=y # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +CONFIG_ACPI_HUGE_LOWMEM_BACKUP=y CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y @@ -535,7 +602,6 @@ CONFIG_HAVE_OPTION_TABLE=y CONFIG_PCI_IO_CFG_EXT=y CONFIG_IOAPIC=y # CONFIG_USE_WATCHDOG_ON_BOOT is not set -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -556,6 +622,7 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KGPE-D16" # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -564,6 +631,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set @@ -573,6 +641,7 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_COREINFO_SECONDARY_PAYLOAD is not set # CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set # CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set # # Debugging @@ -590,13 +659,19 @@ CONFIG_HAVE_DEBUG_SMBUS=y # CONFIG_DEBUG_ACPI is not set # CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set CONFIG_ENABLE_APIC_EXT_ID=y CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # CONFIG_REG_SCRIPT is not set -# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From 761fb612f9db23429076604300d1d65ef9471086 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 11 Jan 2018 21:23:33 -0500 Subject: Update Coreboot config for board macbook2,1 This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * VGA_TEXT_FRAMEBUFFER=y * UART_PCI_ADDR=0x0 Previously configured options which were changed with this commit: * LOCALVERSION="" --- projects/coreboot/configs/seabios/macbook21/config | 302 ++++++++++++++------- 1 file changed, 201 insertions(+), 101 deletions(-) diff --git a/projects/coreboot/configs/seabios/macbook21/config b/projects/coreboot/configs/seabios/macbook21/config index cdf23a4d..133db9d0 100644 --- a/projects/coreboot/configs/seabios/macbook21/config +++ b/projects/coreboot/configs/seabios/macbook21/config @@ -6,47 +6,38 @@ # # General setup # -CONFIG_LOCALVERSION=" MB21.88Z.00A5.B07.0706270922" +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y -# CONFIG_COMPRESS_PRERAM_STAGES is not set CONFIG_INCLUDE_CONFIG_FILE=y -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -CONFIG_FLASHMAP_OFFSET=0x0 -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_ACPI_SATA_GENERATOR is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set @@ -60,16 +51,18 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,38 +103,44 @@ CONFIG_VENDOR_APPLE=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="apple/macbook21" CONFIG_MAINBOARD_PART_NUMBER="MacBook2,1" CONFIG_MAINBOARD_VENDOR="Apple" CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 +CONFIG_CBFS_SIZE=0x200000 CONFIG_VGA_BIOS_ID="8086,27a2" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -# CONFIG_UDELAY_IO is not set CONFIG_MAINBOARD_SERIAL_NUMBER="W8724XXXXXX" -CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 -# CONFIG_BOARD_APPLE_MACBOOK11 is not set CONFIG_BOARD_APPLE_MACBOOK21=y +# CONFIG_BOARD_APPLE_MACBOOK11 is not set +# CONFIG_BOARD_APPLE_IMAC52 is not set # CONFIG_BOARD_APPLE_MACBOOKAIR4_2 is not set -CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Apple Inc." +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y CONFIG_ID_SECTION_OFFSET=0x80 -CONFIG_RAMTOP=0x200000 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 -CONFIG_CBFS_SIZE=0x200000 CONFIG_POST_DEVICE=y +# CONFIG_VBOOT is not set +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_DRIVERS_UART_8250IO=y CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set -CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 CONFIG_BOARD_ROMSIZE_KB_2048=y @@ -151,11 +152,14 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 CONFIG_ROM_SIZE=0x200000 -CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -166,20 +170,37 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_HEAP_SIZE=0x4000 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set # CONFIG_SOC_UCB_RISCV is not set @@ -200,25 +221,30 @@ CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set CONFIG_UDELAY_LAPIC=y CONFIG_LAPIC_MONOTONIC_TIMER=y # CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set -# CONFIG_TSC_CALIBRATE_WITH_IO is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_SMM_TSEG is not set CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_SERIALIZED_SMM_INITIALIZATION is not set # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set -# CONFIG_PARALLEL_MP is not set -# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -233,28 +259,20 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_I945=y # CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_I945_LVDS=y CONFIG_CHANNEL_XOR_RANDOMIZATION=y # CONFIG_OVERRIDE_CLOCK_DISABLE is not set # CONFIG_CHECK_SLFRCS_ON_RESUME is not set -# CONFIG_VRAM_SIZE_1MB is not set -# CONFIG_VRAM_SIZE_4MB is not set -# CONFIG_VRAM_SIZE_8MB is not set -# CONFIG_VRAM_SIZE_16MB is not set -# CONFIG_VRAM_SIZE_32MB is not set -# CONFIG_VRAM_SIZE_48MB is not set -CONFIG_VRAM_SIZE_64MB=y -CONFIG_VRAM_SIZE=0x70 CONFIG_HPET_ADDRESS=0xfed00000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_MAX_PIRQ_LINKS=4 # @@ -264,19 +282,28 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y # # Super I/O # +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set # CONFIG_ARCH_VERSTAGE_ARM is not set @@ -292,6 +319,10 @@ CONFIG_EC_ACPI=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -330,110 +361,161 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_USE_MARCH_586 is not set CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set -CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set -# CONFIG_COMPILE_IN_DSDT is not set -CONFIG_ROMSTAGE_ADDR=0x2000000 -CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -# CONFIG_PXE_ROM is not set +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # # CONFIG_DRIVERS_AS3722_RTC is not set # CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_SMM is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVERS_AMD_PI is not set # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set -# CONFIG_IPMI_KCS is not set -# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set -# CONFIG_SPI_FLASH is not set -# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set -# CONFIG_DRIVERS_UART is not set -# CONFIG_NO_UART_ON_SUPERIO is not set -# CONFIG_DRIVERS_UART_8250MEM is not set -# CONFIG_DRIVERS_UART_8250MEM_32 is not set -# CONFIG_HAVE_UART_SPECIAL is not set -# CONFIG_DRIVERS_UART_OXPCIE is not set -# CONFIG_DRIVERS_UART_PL011 is not set -CONFIG_HAVE_USBDEBUG=y -# CONFIG_HAVE_USBDEBUG_OPTIONS is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set -CONFIG_RTC=y +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set -CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -450,7 +532,9 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set @@ -465,7 +549,6 @@ CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -485,6 +568,7 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1" # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -493,10 +577,17 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# # CONFIG_COREINFO_SECONDARY_PAYLOAD is not set # CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set # # Debugging @@ -506,19 +597,28 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # CONFIG_REG_SCRIPT is not set -# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From e0c3ffa9b19ecd683227fbc7010b71fe093a81f5 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 11 Jan 2018 21:24:47 -0500 Subject: Update Coreboot config for board qemu_i440fx_piix4 This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * VGA_TEXT_FRAMEBUFFER=y * UART_PCI_ADDR=0x0 --- .../configs/seabios/qemu_i440fx_piix4/config | 256 ++++++++++++++------- 1 file changed, 167 insertions(+), 89 deletions(-) diff --git a/projects/coreboot/configs/seabios/qemu_i440fx_piix4/config b/projects/coreboot/configs/seabios/qemu_i440fx_piix4/config index 4ce855b1..d648f094 100644 --- a/projects/coreboot/configs/seabios/qemu_i440fx_piix4/config +++ b/projects/coreboot/configs/seabios/qemu_i440fx_piix4/config @@ -6,47 +6,38 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y -# CONFIG_COMPRESS_PRERAM_STAGES is not set CONFIG_INCLUDE_CONFIG_FILE=y -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_UBSAN is not set # CONFIG_RELOCATABLE_RAMSTAGE is not set -CONFIG_FLASHMAP_OFFSET=0x0 -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_ACPI_SATA_GENERATOR is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set CONFIG_VENDOR_EMULATION=y # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_VENDOR_EMULATION=y # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_EMULATION=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,6 +103,7 @@ CONFIG_VENDOR_EMULATION=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="emulation/qemu-i440fx" @@ -115,16 +111,18 @@ CONFIG_MAINBOARD_PART_NUMBER="QEMU x86 i440fx/piix4" CONFIG_IRQ_SLOT_COUNT=6 CONFIG_MAINBOARD_VENDOR="Emulation" CONFIG_MAX_CPUS=1 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 +CONFIG_CBFS_SIZE=0x800000 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_UDELAY_IO=y CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" CONFIG_DCACHE_RAM_BASE=0xd0000 CONFIG_DCACHE_RAM_SIZE=0x10000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Emulation" CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y CONFIG_ID_SECTION_OFFSET=0x80 # CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y @@ -133,15 +131,14 @@ CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y # CONFIG_BOARD_EMULATION_QEMU_UCB_RISCV is not set # CONFIG_BOARD_EMULATION_SPIKE_UCB_RISCV is not set CONFIG_BOARD_EMULATION_QEMU_X86=y -CONFIG_RAMTOP=0x200000 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 -CONFIG_CBFS_SIZE=0x800000 CONFIG_POST_DEVICE=y +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_DRIVERS_UART_8250IO=y CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set -CONFIG_DRIVERS_UART_8250IO=y # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_256=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -152,11 +149,14 @@ CONFIG_BOARD_ROMSIZE_KB_256=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=8192 CONFIG_ROM_SIZE=0x800000 -CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set # CONFIG_SYSTEM_TYPE_LAPTOP is not set # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -167,18 +167,33 @@ CONFIG_FMDFILE="" # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82371eb/bootblock.c" -CONFIG_HEAP_SIZE=0x4000 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set # CONFIG_SOC_UCB_RISCV is not set @@ -198,22 +213,24 @@ CONFIG_NUM_IPI_STARTS=2 CONFIG_CPU_QEMU_X86=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +CONFIG_UDELAY_IO=y # CONFIG_UDELAY_LAPIC is not set # CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set -# CONFIG_TSC_CALIBRATE_WITH_IO is not set # CONFIG_TSC_SYNC_LFENCE is not set # CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_SMM_TSEG is not set # CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set # CONFIG_SERIALIZED_SMM_INITIALIZATION is not set # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set -# CONFIG_PARALLEL_MP is not set -# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 # CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set @@ -226,11 +243,11 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +CONFIG_NO_MMCONF_SUPPORT=y # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_HPET_ADDRESS=0xfed00000 CONFIG_MAX_PIRQ_LINKS=4 @@ -240,19 +257,28 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_AMD_SB_CIMX is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set -# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y # CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82371EB=y # # Super I/O # +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set # CONFIG_ARCH_VERSTAGE_ARM is not set @@ -268,6 +294,10 @@ CONFIG_SOUTHBRIDGE_INTEL_I82371EB=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -306,111 +336,143 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_USE_MARCH_586 is not set # CONFIG_AP_IN_SIPI_WAIT is not set # CONFIG_SIPI_VECTOR_IN_ROM is not set -CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y -# CONFIG_HAVE_CMOS_DEFAULT is not set +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set -# CONFIG_COMPILE_IN_DSDT is not set -CONFIG_ROMSTAGE_ADDR=0x2000000 -CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +# CONFIG_MMCONF_SUPPORT is not set # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -# CONFIG_PXE_ROM is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y - # # Generic Drivers # # CONFIG_DRIVERS_AS3722_RTC is not set -CONFIG_DRIVERS_EMULATION_QEMU_BOCHS=y -CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES=800 -CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES=600 # CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +# CONFIG_HAVE_USBDEBUG is not set +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVERS_AMD_PI is not set +CONFIG_DRIVERS_EMULATION_QEMU_BOCHS=y # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set # CONFIG_INTEL_EDID is not set # CONFIG_INTEL_INT15 is not set # CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set # CONFIG_DRIVER_INTEL_I210 is not set -# CONFIG_IPMI_KCS is not set -# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set -# CONFIG_SPI_FLASH is not set -# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set -# CONFIG_DRIVERS_UART is not set -# CONFIG_NO_UART_ON_SUPERIO is not set -# CONFIG_DRIVERS_UART_8250MEM is not set -# CONFIG_DRIVERS_UART_8250MEM_32 is not set -# CONFIG_HAVE_UART_SPECIAL is not set -# CONFIG_DRIVERS_UART_OXPCIE is not set -# CONFIG_DRIVERS_UART_PL011 is not set -# CONFIG_HAVE_USBDEBUG is not set -# CONFIG_HAVE_USBDEBUG_OPTIONS is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set -CONFIG_RTC=y +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -# CONFIG_MMCONF_SUPPORT_DEFAULT is not set -# CONFIG_MMCONF_SUPPORT is not set -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set -CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_CONSOLE_QEMU_DEBUGCON=y CONFIG_CONSOLE_QEMU_DEBUGCON_PORT=0x402 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y @@ -429,7 +491,9 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y # CONFIG_HAVE_ACPI_RESUME is not set +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set # CONFIG_HAVE_HARD_RESET is not set # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set @@ -441,7 +505,6 @@ CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PCI_IO_CFG_EXT is not set # CONFIG_IOAPIC is not set # CONFIG_USE_WATCHDOG_ON_BOOT is not set -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_PIRQ_TABLE=y @@ -461,6 +524,7 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="QEMU x86 i440fx/piix4" # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -469,10 +533,17 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# # CONFIG_COREINFO_SECONDARY_PAYLOAD is not set # CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set # # Debugging @@ -482,17 +553,24 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_HAVE_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set # CONFIG_DEBUG_PIRQ is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # CONFIG_REG_SCRIPT is not set -# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From 9804479bdaa4594760a73a870bc459835f520068 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:39:51 -0500 Subject: Update Coreboot config for board qemu_q35_ich9 This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" * VGA_TEXT_FRAMEBUFFER=y * UART_PCI_ADDR=0x0 The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- .../coreboot/configs/seabios/qemu_q35_ich9/config | 277 ++++++++++++++------- 1 file changed, 183 insertions(+), 94 deletions(-) diff --git a/projects/coreboot/configs/seabios/qemu_q35_ich9/config b/projects/coreboot/configs/seabios/qemu_q35_ich9/config index eaa60108..aeee9cc9 100644 --- a/projects/coreboot/configs/seabios/qemu_q35_ich9/config +++ b/projects/coreboot/configs/seabios/qemu_q35_ich9/config @@ -6,45 +6,36 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_COMPRESS_RAMSTAGE=y -# CONFIG_COMPRESS_PRERAM_STAGES is not set CONFIG_INCLUDE_CONFIG_FILE=y -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_UBSAN is not set # CONFIG_RELOCATABLE_RAMSTAGE is not set -CONFIG_FLASHMAP_OFFSET=0x0 -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_ACPI_SATA_GENERATOR is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set @@ -58,16 +49,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set CONFIG_VENDOR_EMULATION=y # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -84,6 +77,7 @@ CONFIG_VENDOR_EMULATION=y # CONFIG_VENDOR_LENOVO is not set # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -95,6 +89,7 @@ CONFIG_VENDOR_EMULATION=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -106,24 +101,30 @@ CONFIG_VENDOR_EMULATION=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="emulation/qemu-q35" CONFIG_MAINBOARD_PART_NUMBER="QEMU x86 q35/ich9" CONFIG_MAINBOARD_VENDOR="Emulation" CONFIG_MAX_CPUS=1 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 +CONFIG_CBFS_SIZE=0x800000 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_UDELAY_IO=y CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" CONFIG_DCACHE_RAM_BASE=0xd0000 CONFIG_DCACHE_RAM_SIZE=0x10000 -CONFIG_MMCONF_BASE_ADDRESS=0xb0000000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Emulation" +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set +CONFIG_MMCONF_BASE_ADDRESS=0xb0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/emulation/qemu-q35/bootblock.c" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set CONFIG_ID_SECTION_OFFSET=0x80 # CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set # CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set @@ -132,18 +133,20 @@ CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y # CONFIG_BOARD_EMULATION_QEMU_UCB_RISCV is not set # CONFIG_BOARD_EMULATION_SPIKE_UCB_RISCV is not set CONFIG_BOARD_EMULATION_QEMU_X86=y -CONFIG_RAMTOP=0x200000 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 -CONFIG_CBFS_SIZE=0x800000 CONFIG_POST_DEVICE=y +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set -CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set -CONFIG_BOARD_ROMSIZE_KB_256=y +CONFIG_BOARD_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set # CONFIG_COREBOOT_ROMSIZE_KB_128 is not set # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set @@ -152,11 +155,14 @@ CONFIG_BOARD_ROMSIZE_KB_256=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=8192 CONFIG_ROM_SIZE=0x800000 -CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set # CONFIG_SYSTEM_TYPE_LAPTOP is not set # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -167,19 +173,35 @@ CONFIG_FMDFILE="" # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_HEAP_SIZE=0x4000 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set # CONFIG_SOC_UCB_RISCV is not set @@ -199,22 +221,24 @@ CONFIG_NUM_IPI_STARTS=2 CONFIG_CPU_QEMU_X86=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +CONFIG_UDELAY_IO=y # CONFIG_UDELAY_LAPIC is not set # CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set -# CONFIG_TSC_CALIBRATE_WITH_IO is not set # CONFIG_TSC_SYNC_LFENCE is not set # CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_SMM_TSEG is not set # CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set # CONFIG_SERIALIZED_SMM_INITIALIZATION is not set # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set -# CONFIG_PARALLEL_MP is not set -# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 # CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set @@ -227,13 +251,12 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_HPET_ADDRESS=0xfed00000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_MAX_PIRQ_LINKS=4 # @@ -243,18 +266,35 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set # CONFIG_ARCH_VERSTAGE_ARM is not set @@ -270,6 +310,10 @@ CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -308,111 +352,140 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_USE_MARCH_586 is not set # CONFIG_AP_IN_SIPI_WAIT is not set # CONFIG_SIPI_VECTOR_IN_ROM is not set -CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y -# CONFIG_HAVE_CMOS_DEFAULT is not set +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS=y -# CONFIG_COMPILE_IN_DSDT is not set -CONFIG_ROMSTAGE_ADDR=0x2000000 -CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -# CONFIG_PXE_ROM is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y - # # Generic Drivers # # CONFIG_DRIVERS_AS3722_RTC is not set -CONFIG_DRIVERS_EMULATION_QEMU_BOCHS=y -CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES=800 -CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES=600 # CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set +CONFIG_DRIVERS_EMULATION_QEMU_BOCHS=y # CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set # CONFIG_INTEL_EDID is not set # CONFIG_INTEL_INT15 is not set # CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set # CONFIG_DRIVER_INTEL_I210 is not set -# CONFIG_IPMI_KCS is not set -# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set -# CONFIG_SPI_FLASH is not set -# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set -# CONFIG_DRIVERS_UART is not set -# CONFIG_NO_UART_ON_SUPERIO is not set -# CONFIG_DRIVERS_UART_8250MEM is not set -# CONFIG_DRIVERS_UART_8250MEM_32 is not set -# CONFIG_HAVE_UART_SPECIAL is not set -# CONFIG_DRIVERS_UART_OXPCIE is not set -# CONFIG_DRIVERS_UART_PL011 is not set -CONFIG_HAVE_USBDEBUG=y -CONFIG_HAVE_USBDEBUG_OPTIONS=y # CONFIG_DRIVER_XPOWERS_AXP209 is not set -CONFIG_RTC=y +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set -CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_CONSOLE_QEMU_DEBUGCON=y CONFIG_CONSOLE_QEMU_DEBUGCON_PORT=0x402 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y @@ -431,7 +504,9 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y # CONFIG_HAVE_ACPI_RESUME is not set +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set @@ -443,7 +518,6 @@ CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y # CONFIG_COMMON_FADT is not set @@ -462,6 +536,7 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="QEMU x86 q35/ich9" # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -470,10 +545,17 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# # CONFIG_COREINFO_SECONDARY_PAYLOAD is not set # CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set # # Debugging @@ -482,19 +564,26 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_DEBUG_CBFS is not set # CONFIG_HAVE_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # CONFIG_REG_SCRIPT is not set -# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From 07fcd9511adaa8d94b97dd3c49ba302f851c52e0 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:40:33 -0500 Subject: Update Coreboot config for board r400_16mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/r400_16mb/config | 228 ++++++++++++++------- 1 file changed, 155 insertions(+), 73 deletions(-) diff --git a/projects/coreboot/configs/seabios/r400_16mb/config b/projects/coreboot/configs/seabios/r400_16mb/config index 6df1a028..5e18135a 100644 --- a/projects/coreboot/configs/seabios/r400_16mb/config +++ b/projects/coreboot/configs/seabios/r400_16mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad R400" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=4 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0xFFD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set CONFIG_BOARD_LENOVO_R400=y +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set # CONFIG_BOARD_LENOVO_T500 is not set # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 CONFIG_ROM_SIZE=0x1000000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -214,19 +231,22 @@ CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_CPU_INTEL_MODEL_1067X=y -CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_CPU_INTEL_SOCKET_MPGA478MN=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +258,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +275,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -271,22 +292,42 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +344,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -339,10 +384,12 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set -# CONFIG_AP_IN_SIPI_WAIT is not set +CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +400,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -391,11 +443,14 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set -CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set @@ -406,55 +461,71 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS=y # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -465,25 +536,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -502,6 +577,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -530,16 +606,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -548,3 +625,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From 28a82fc12dd9500ca007ed7c6ed9a054e9ecdc32 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:41:34 -0500 Subject: Update Coreboot config for board r400_4mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/r400_4mb/config | 228 +++++++++++++++------- 1 file changed, 155 insertions(+), 73 deletions(-) diff --git a/projects/coreboot/configs/seabios/r400_4mb/config b/projects/coreboot/configs/seabios/r400_4mb/config index 55c6a211..becebc06 100644 --- a/projects/coreboot/configs/seabios/r400_4mb/config +++ b/projects/coreboot/configs/seabios/r400_4mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad R400" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=4 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0x3FD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set CONFIG_BOARD_LENOVO_R400=y +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set # CONFIG_BOARD_LENOVO_T500 is not set # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set CONFIG_COREBOOT_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=4096 CONFIG_ROM_SIZE=0x400000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -214,19 +231,22 @@ CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_CPU_INTEL_MODEL_1067X=y -CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_CPU_INTEL_SOCKET_MPGA478MN=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +258,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +275,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -271,22 +292,42 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +344,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -339,10 +384,12 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set -# CONFIG_AP_IN_SIPI_WAIT is not set +CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +400,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -391,11 +443,14 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set -CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set @@ -406,55 +461,71 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS=y # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -465,25 +536,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -502,6 +577,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -530,16 +606,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -548,3 +625,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From 0013a6e0b2c65c5222c2694a82a316c884cb46e4 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:42:16 -0500 Subject: Update Coreboot config for board r400_8mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/r400_8mb/config | 228 +++++++++++++++------- 1 file changed, 155 insertions(+), 73 deletions(-) diff --git a/projects/coreboot/configs/seabios/r400_8mb/config b/projects/coreboot/configs/seabios/r400_8mb/config index 1b2e9374..14eb5497 100644 --- a/projects/coreboot/configs/seabios/r400_8mb/config +++ b/projects/coreboot/configs/seabios/r400_8mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad R400" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=4 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0x7FD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set CONFIG_BOARD_LENOVO_R400=y +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set # CONFIG_BOARD_LENOVO_T500 is not set # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=8192 CONFIG_ROM_SIZE=0x800000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -214,19 +231,22 @@ CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_CPU_INTEL_MODEL_1067X=y -CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_CPU_INTEL_SOCKET_MPGA478MN=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +258,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +275,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -271,22 +292,42 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +344,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -339,10 +384,12 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set -# CONFIG_AP_IN_SIPI_WAIT is not set +CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +400,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -391,11 +443,14 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set -CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set @@ -406,55 +461,71 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS=y # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -465,25 +536,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -502,6 +577,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -530,16 +606,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -548,3 +625,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From f85ff4ee20e18017f8c87d1af65908f3a06ecaf3 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:44:33 -0500 Subject: Update Coreboot config for board t400_16mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/t400_16mb/config | 228 ++++++++++++++------- 1 file changed, 155 insertions(+), 73 deletions(-) diff --git a/projects/coreboot/configs/seabios/t400_16mb/config b/projects/coreboot/configs/seabios/t400_16mb/config index 6158d98b..9368d339 100644 --- a/projects/coreboot/configs/seabios/t400_16mb/config +++ b/projects/coreboot/configs/seabios/t400_16mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T400" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=4 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0xFFD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set CONFIG_BOARD_LENOVO_T400=y # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set # CONFIG_BOARD_LENOVO_T500 is not set # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 CONFIG_ROM_SIZE=0x1000000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -214,19 +231,22 @@ CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_CPU_INTEL_MODEL_1067X=y -CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_CPU_INTEL_SOCKET_MPGA478MN=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +258,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +275,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -271,22 +292,42 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +344,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -339,10 +384,12 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set -# CONFIG_AP_IN_SIPI_WAIT is not set +CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +400,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -391,11 +443,14 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set -CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set @@ -406,55 +461,71 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS=y # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -465,25 +536,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -502,6 +577,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -530,16 +606,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -548,3 +625,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From f52e5c0784727f833b0b25e9d2b21cbd67db9570 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:45:00 -0500 Subject: Update Coreboot config for board t400_4mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/t400_4mb/config | 228 +++++++++++++++------- 1 file changed, 155 insertions(+), 73 deletions(-) diff --git a/projects/coreboot/configs/seabios/t400_4mb/config b/projects/coreboot/configs/seabios/t400_4mb/config index a0663b75..cc66b4bb 100644 --- a/projects/coreboot/configs/seabios/t400_4mb/config +++ b/projects/coreboot/configs/seabios/t400_4mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T400" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=4 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0x3FD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set CONFIG_BOARD_LENOVO_T400=y # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set # CONFIG_BOARD_LENOVO_T500 is not set # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set CONFIG_COREBOOT_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=4096 CONFIG_ROM_SIZE=0x400000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -214,19 +231,22 @@ CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_CPU_INTEL_MODEL_1067X=y -CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_CPU_INTEL_SOCKET_MPGA478MN=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +258,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +275,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -271,22 +292,42 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +344,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -339,10 +384,12 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set -# CONFIG_AP_IN_SIPI_WAIT is not set +CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +400,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -391,11 +443,14 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set -CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set @@ -406,55 +461,71 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS=y # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -465,25 +536,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -502,6 +577,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -530,16 +606,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -548,3 +625,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From 6164381d8ffc131b136433c47ac35d460f865f76 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:46:08 -0500 Subject: Update Coreboot config for board t400_8mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/t400_8mb/config | 228 +++++++++++++++------- 1 file changed, 155 insertions(+), 73 deletions(-) diff --git a/projects/coreboot/configs/seabios/t400_8mb/config b/projects/coreboot/configs/seabios/t400_8mb/config index fada3b93..cf20d266 100644 --- a/projects/coreboot/configs/seabios/t400_8mb/config +++ b/projects/coreboot/configs/seabios/t400_8mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T400" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=4 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0x7FD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set CONFIG_BOARD_LENOVO_T400=y # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set # CONFIG_BOARD_LENOVO_T500 is not set # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=8192 CONFIG_ROM_SIZE=0x800000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -214,19 +231,22 @@ CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_CPU_INTEL_MODEL_1067X=y -CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_CPU_INTEL_SOCKET_MPGA478MN=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +258,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +275,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -271,22 +292,42 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +344,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -339,10 +384,12 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set -# CONFIG_AP_IN_SIPI_WAIT is not set +CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +400,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -391,11 +443,14 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set -CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set @@ -406,55 +461,71 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS=y # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -465,25 +536,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -502,6 +577,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -530,16 +606,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -548,3 +625,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From 350cc6ca27da84b306cec5468acd133503c56387 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:46:57 -0500 Subject: Update Coreboot config for board t500_16mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/t500_16mb/config | 228 ++++++++++++++------- 1 file changed, 155 insertions(+), 73 deletions(-) diff --git a/projects/coreboot/configs/seabios/t500_16mb/config b/projects/coreboot/configs/seabios/t500_16mb/config index b4ba07f8..4a691bb4 100644 --- a/projects/coreboot/configs/seabios/t500_16mb/config +++ b/projects/coreboot/configs/seabios/t500_16mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T500" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=4 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0xFFD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set CONFIG_BOARD_LENOVO_T500=y # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 CONFIG_ROM_SIZE=0x1000000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -214,19 +231,22 @@ CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_CPU_INTEL_MODEL_1067X=y -CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_CPU_INTEL_SOCKET_MPGA478MN=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +258,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +275,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -271,22 +292,42 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +344,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -339,10 +384,12 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set -# CONFIG_AP_IN_SIPI_WAIT is not set +CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +400,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -391,11 +443,14 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set -CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set @@ -406,55 +461,71 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS=y # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -465,25 +536,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -502,6 +577,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -530,16 +606,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -548,3 +625,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From a2563025d3063340f75eaa4706c8694f4ada40aa Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:48:32 -0500 Subject: Update Coreboot config for board t500_4mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/t500_4mb/config | 228 +++++++++++++++------- 1 file changed, 155 insertions(+), 73 deletions(-) diff --git a/projects/coreboot/configs/seabios/t500_4mb/config b/projects/coreboot/configs/seabios/t500_4mb/config index 87b59c8e..ee8b1527 100644 --- a/projects/coreboot/configs/seabios/t500_4mb/config +++ b/projects/coreboot/configs/seabios/t500_4mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T500" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=4 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0x3FD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set CONFIG_BOARD_LENOVO_T500=y # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set CONFIG_COREBOOT_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=4096 CONFIG_ROM_SIZE=0x400000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -214,19 +231,22 @@ CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_CPU_INTEL_MODEL_1067X=y -CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_CPU_INTEL_SOCKET_MPGA478MN=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +258,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +275,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -271,22 +292,42 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +344,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -339,10 +384,12 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set -# CONFIG_AP_IN_SIPI_WAIT is not set +CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +400,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -391,11 +443,14 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set -CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set @@ -406,55 +461,71 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS=y # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -465,25 +536,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -502,6 +577,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -530,16 +606,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -548,3 +625,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From fc870f3c15151d139892eb5d63ab94f845f84c4d Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:49:32 -0500 Subject: Update Coreboot config for board t500_8mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/t500_8mb/config | 228 +++++++++++++++------- 1 file changed, 155 insertions(+), 73 deletions(-) diff --git a/projects/coreboot/configs/seabios/t500_8mb/config b/projects/coreboot/configs/seabios/t500_8mb/config index c02c71a0..d20cb720 100644 --- a/projects/coreboot/configs/seabios/t500_8mb/config +++ b/projects/coreboot/configs/seabios/t500_8mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T500" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=4 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0x7FD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set CONFIG_BOARD_LENOVO_T500=y # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=8192 CONFIG_ROM_SIZE=0x800000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -214,19 +231,22 @@ CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_CPU_INTEL_MODEL_1067X=y -CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_CPU_INTEL_SOCKET_MPGA478MN=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +258,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +275,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -271,22 +292,42 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +344,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -339,10 +384,12 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set -# CONFIG_AP_IN_SIPI_WAIT is not set +CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +400,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -391,11 +443,14 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set -CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set @@ -406,55 +461,71 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS=y # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -465,25 +536,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -502,6 +577,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -530,16 +606,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -548,3 +625,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From 100e35d70ace542ac0aa149d785044a8dcb51d8a Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 11 Jan 2018 21:34:16 -0500 Subject: Update Coreboot config for board t60 This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * VGA_TEXT_FRAMEBUFFER=y * UART_PCI_ADDR=0x0 Previously configured options which were changed with this commit: * LOCALVERSION="" --- projects/coreboot/configs/seabios/t60/config | 309 ++++++++++++++++++--------- 1 file changed, 208 insertions(+), 101 deletions(-) diff --git a/projects/coreboot/configs/seabios/t60/config b/projects/coreboot/configs/seabios/t60/config index 67d83d1f..8ccbacd1 100644 --- a/projects/coreboot/configs/seabios/t60/config +++ b/projects/coreboot/configs/seabios/t60/config @@ -6,47 +6,38 @@ # # General setup # -CONFIG_LOCALVERSION="79ETE7WW (2.27 )" +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y -# CONFIG_COMPRESS_PRERAM_STAGES is not set CONFIG_INCLUDE_CONFIG_FILE=y -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -CONFIG_FLASHMAP_OFFSET=0x0 -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_ACPI_SATA_GENERATOR is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,59 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t60" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T60" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 +CONFIG_CBFS_SIZE=0x200000 CONFIG_VGA_BIOS_ID="8086,27a2" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -# CONFIG_UDELAY_IO is not set -CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y CONFIG_ID_SECTION_OFFSET=0x80 -CONFIG_RAMTOP=0x200000 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 -CONFIG_CBFS_SIZE=0x200000 CONFIG_POST_DEVICE=y +# CONFIG_VBOOT is not set +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_DRIVERS_UART_8250IO=y # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set # CONFIG_BOARD_LENOVO_T500 is not set # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set CONFIG_BOARD_LENOVO_T60=y +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set -CONFIG_SEABIOS_PS2_TIMEOUT=3000 +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set -CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 CONFIG_BOARD_ROMSIZE_KB_2048=y @@ -161,11 +167,14 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 CONFIG_ROM_SIZE=0x200000 -CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -176,20 +185,37 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_HEAP_SIZE=0x4000 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set # CONFIG_SOC_UCB_RISCV is not set @@ -210,25 +236,30 @@ CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set CONFIG_UDELAY_LAPIC=y CONFIG_LAPIC_MONOTONIC_TIMER=y # CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set -# CONFIG_TSC_CALIBRATE_WITH_IO is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_SMM_TSEG is not set CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_SERIALIZED_SMM_INITIALIZATION is not set # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set -# CONFIG_PARALLEL_MP is not set -# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -243,28 +274,20 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_I945=y # CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_I945_LVDS=y CONFIG_CHANNEL_XOR_RANDOMIZATION=y # CONFIG_OVERRIDE_CLOCK_DISABLE is not set # CONFIG_CHECK_SLFRCS_ON_RESUME is not set -# CONFIG_VRAM_SIZE_1MB is not set -# CONFIG_VRAM_SIZE_4MB is not set -# CONFIG_VRAM_SIZE_8MB is not set -# CONFIG_VRAM_SIZE_16MB is not set -# CONFIG_VRAM_SIZE_32MB is not set -# CONFIG_VRAM_SIZE_48MB is not set -CONFIG_VRAM_SIZE_64MB=y -CONFIG_VRAM_SIZE=0x70 CONFIG_HPET_ADDRESS=0xfed00000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_MAX_PIRQ_LINKS=4 # @@ -274,7 +297,12 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_TI_PCI1X2X=y @@ -283,16 +311,22 @@ CONFIG_SOUTHBRIDGE_TI_PCI1X2X=y # CONFIG_SUPERIO_NSC_PC87382=y CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set # CONFIG_ARCH_VERSTAGE_ARM is not set @@ -308,6 +342,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -346,111 +384,162 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_USE_MARCH_586 is not set CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set -CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set -# CONFIG_COMPILE_IN_DSDT is not set -CONFIG_ROMSTAGE_ADDR=0x2000000 -CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -# CONFIG_PXE_ROM is not set +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # # CONFIG_DRIVERS_AS3722_RTC is not set # CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_SMM is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +CONFIG_DRIVERS_I2C_CK505=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set -# CONFIG_IPMI_KCS is not set -# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set -# CONFIG_SPI_FLASH is not set -# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set -# CONFIG_DRIVERS_UART is not set -# CONFIG_NO_UART_ON_SUPERIO is not set -# CONFIG_DRIVERS_UART_8250MEM is not set -# CONFIG_DRIVERS_UART_8250MEM_32 is not set -# CONFIG_HAVE_UART_SPECIAL is not set -# CONFIG_DRIVERS_UART_OXPCIE is not set -# CONFIG_DRIVERS_UART_PL011 is not set -CONFIG_HAVE_USBDEBUG=y -# CONFIG_HAVE_USBDEBUG_OPTIONS is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set -CONFIG_RTC=y +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set -CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -467,7 +556,9 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set @@ -482,7 +573,6 @@ CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -501,6 +591,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -509,10 +600,17 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# # CONFIG_COREINFO_SECONDARY_PAYLOAD is not set # CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set # # Debugging @@ -522,19 +620,28 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # CONFIG_REG_SCRIPT is not set -# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From be26534843184dca6f99ef9b0fb1c28b0d1e5a86 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:50:18 -0500 Subject: Update Coreboot config for board w500_16mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/w500_16mb/config | 230 ++++++++++++++------- 1 file changed, 156 insertions(+), 74 deletions(-) diff --git a/projects/coreboot/configs/seabios/w500_16mb/config b/projects/coreboot/configs/seabios/w500_16mb/config index 205b5d1b..4a691bb4 100644 --- a/projects/coreboot/configs/seabios/w500_16mb/config +++ b/projects/coreboot/configs/seabios/w500_16mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" -CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W500" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T500" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=4 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0xFFD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set CONFIG_BOARD_LENOVO_T500=y # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 CONFIG_ROM_SIZE=0x1000000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -214,19 +231,22 @@ CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_CPU_INTEL_MODEL_1067X=y -CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_CPU_INTEL_SOCKET_MPGA478MN=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +258,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +275,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -271,22 +292,42 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +344,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -339,10 +384,12 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set -# CONFIG_AP_IN_SIPI_WAIT is not set +CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +400,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -391,11 +443,14 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set -CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set @@ -406,55 +461,71 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS=y # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -465,25 +536,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -502,6 +577,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -530,16 +606,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -548,3 +625,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From 22f26981c40b32a5415310cbd503d004d0e5ef8b Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:50:54 -0500 Subject: Update Coreboot config for board w500_4mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/w500_4mb/config | 230 +++++++++++++++------- 1 file changed, 156 insertions(+), 74 deletions(-) diff --git a/projects/coreboot/configs/seabios/w500_4mb/config b/projects/coreboot/configs/seabios/w500_4mb/config index 201248b6..ee8b1527 100644 --- a/projects/coreboot/configs/seabios/w500_4mb/config +++ b/projects/coreboot/configs/seabios/w500_4mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" -CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W500" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T500" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=4 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0x3FD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set CONFIG_BOARD_LENOVO_T500=y # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set CONFIG_COREBOOT_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=4096 CONFIG_ROM_SIZE=0x400000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -214,19 +231,22 @@ CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_CPU_INTEL_MODEL_1067X=y -CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_CPU_INTEL_SOCKET_MPGA478MN=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +258,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +275,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -271,22 +292,42 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +344,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -339,10 +384,12 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set -# CONFIG_AP_IN_SIPI_WAIT is not set +CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +400,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -391,11 +443,14 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set -CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set @@ -406,55 +461,71 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS=y # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -465,25 +536,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -502,6 +577,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -530,16 +606,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -548,3 +625,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From aab8aee90c58e475739bf946acc0eba59a069b9d Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:51:37 -0500 Subject: Update Coreboot config for board w500_8mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/w500_8mb/config | 230 +++++++++++++++------- 1 file changed, 156 insertions(+), 74 deletions(-) diff --git a/projects/coreboot/configs/seabios/w500_8mb/config b/projects/coreboot/configs/seabios/w500_8mb/config index fecd941b..d20cb720 100644 --- a/projects/coreboot/configs/seabios/w500_8mb/config +++ b/projects/coreboot/configs/seabios/w500_8mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/t400" -CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W500" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T500" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=4 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0x7FD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set CONFIG_BOARD_LENOVO_T500=y # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=8192 CONFIG_ROM_SIZE=0x800000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -214,19 +231,22 @@ CONFIG_NUM_IPI_STARTS=2 # CONFIG_CPU_AMD_AGESA is not set # CONFIG_CPU_AMD_PI is not set # CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6FX=y CONFIG_CPU_INTEL_MODEL_1067X=y -CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_CPU_INTEL_SOCKET_MPGA478MN=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +258,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +275,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -271,22 +292,42 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +344,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -339,10 +384,12 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_ARCH_ROMSTAGE_X86_64 is not set # CONFIG_ARCH_RAMSTAGE_X86_64 is not set # CONFIG_USE_MARCH_586 is not set -# CONFIG_AP_IN_SIPI_WAIT is not set +CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +400,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -391,11 +443,14 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set -CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set # CONFIG_UART_OVERRIDE_REFCLK is not set # CONFIG_DRIVERS_UART_8250MEM is not set @@ -406,55 +461,71 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS=y # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -465,25 +536,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -502,6 +577,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -530,16 +606,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -548,3 +625,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From d0eceff7cf4bc96297ea2337ed876fa8170ad6b5 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:52:21 -0500 Subject: Update Coreboot config for board x200_16mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/x200_16mb/config | 209 +++++++++++++++------ 1 file changed, 147 insertions(+), 62 deletions(-) diff --git a/projects/coreboot/configs/seabios/x200_16mb/config b/projects/coreboot/configs/seabios/x200_16mb/config index 02cc1c72..87e0d4ed 100644 --- a/projects/coreboot/configs/seabios/x200_16mb/config +++ b/projects/coreboot/configs/seabios/x200_16mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/x200" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X200" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=2 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0xFFD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 # CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set # CONFIG_BOARD_LENOVO_T500 is not set # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set CONFIG_BOARD_LENOVO_X200=y # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set CONFIG_COREBOOT_ROMSIZE_KB_16384=y # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=16384 CONFIG_ROM_SIZE=0x1000000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -219,14 +236,16 @@ CONFIG_CPU_INTEL_SOCKET_BGA956=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +257,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +274,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -272,21 +292,39 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +341,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -342,7 +384,9 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_AP_IN_SIPI_WAIT is not set # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +397,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -394,8 +443,9 @@ CONFIG_DRIVERS_LENOVO_WACOM=y # CONFIG_DIGITIZER_AUTODETECT is not set CONFIG_DIGITIZER_PRESENT=y # CONFIG_DIGITIZER_ABSENT is not set -# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set @@ -410,37 +460,60 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console @@ -450,6 +523,7 @@ CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -460,25 +534,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -497,6 +575,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -525,16 +604,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -543,3 +623,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From ec4de71a09f55b79d66a9a9715b7be2e3e731265 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:53:07 -0500 Subject: Update Coreboot config for board x200_4mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/x200_4mb/config | 209 +++++++++++++++------- 1 file changed, 147 insertions(+), 62 deletions(-) diff --git a/projects/coreboot/configs/seabios/x200_4mb/config b/projects/coreboot/configs/seabios/x200_4mb/config index 22573e85..214128a1 100644 --- a/projects/coreboot/configs/seabios/x200_4mb/config +++ b/projects/coreboot/configs/seabios/x200_4mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/x200" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X200" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=2 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0x3FD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 # CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set # CONFIG_BOARD_LENOVO_T500 is not set # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set CONFIG_BOARD_LENOVO_X200=y # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set CONFIG_COREBOOT_ROMSIZE_KB_4096=y # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=4096 CONFIG_ROM_SIZE=0x400000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -219,14 +236,16 @@ CONFIG_CPU_INTEL_SOCKET_BGA956=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +257,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +274,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -272,21 +292,39 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +341,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -342,7 +384,9 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_AP_IN_SIPI_WAIT is not set # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +397,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -394,8 +443,9 @@ CONFIG_DRIVERS_LENOVO_WACOM=y # CONFIG_DIGITIZER_AUTODETECT is not set CONFIG_DIGITIZER_PRESENT=y # CONFIG_DIGITIZER_ABSENT is not set -# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set @@ -410,37 +460,60 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console @@ -450,6 +523,7 @@ CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -460,25 +534,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -497,6 +575,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -525,16 +604,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -543,3 +623,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From d18b155ec0c8e822fa5d0759fa08413b5bdddd0d Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 18:53:44 -0500 Subject: Update Coreboot config for board x200_8mb This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system. --- projects/coreboot/configs/seabios/x200_8mb/config | 209 +++++++++++++++------- 1 file changed, 147 insertions(+), 62 deletions(-) diff --git a/projects/coreboot/configs/seabios/x200_8mb/config b/projects/coreboot/configs/seabios/x200_8mb/config index 2ef9b6e0..4d9ef0b0 100644 --- a/projects/coreboot/configs/seabios/x200_8mb/config +++ b/projects/coreboot/configs/seabios/x200_8mb/config @@ -6,43 +6,34 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y CONFIG_INCLUDE_CONFIG_FILE=y -# CONFIG_NO_XIP_EARLY_STAGES is not set -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -# CONFIG_NO_STAGE_CACHE is not set -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,48 +103,63 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/x200" CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X200" CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=2 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 CONFIG_CBFS_SIZE=0x7FD000 CONFIG_VGA_BIOS_ID="8086,2a42" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_HAVE_IFD_BIN=y +# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_HAVE_GBE_BIN is not set +CONFIG_USBDEBUG_HCD_INDEX=2 CONFIG_ID_SECTION_OFFSET=0x80 CONFIG_POST_DEVICE=y -CONFIG_USBDEBUG_HCD_INDEX=2 -# CONFIG_CONSOLE_POST is not set +# CONFIG_VBOOT is not set +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 # CONFIG_DRIVERS_UART_8250IO is not set +CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set # CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set # CONFIG_BOARD_LENOVO_T500 is not set # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set CONFIG_BOARD_LENOVO_X200=y # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set # CONFIG_BOARD_LENOVO_X60 is not set +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -160,13 +170,13 @@ CONFIG_BOARD_ROMSIZE_KB_8192=y # CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=8192 CONFIG_ROM_SIZE=0x800000 -CONFIG_FMDFILE="" # CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -178,24 +188,31 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_RAMTOP=0x200000 -CONFIG_HEAP_SIZE=0x4000 +CONFIG_STACK_SIZE=0x1000 CONFIG_CONSOLE_CBMEM=y CONFIG_UART_PCI_ADDR=0x0 CONFIG_HPET_MIN_TICKS=0x80 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set @@ -219,14 +236,16 @@ CONFIG_CPU_INTEL_SOCKET_BGA956=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set # CONFIG_PARALLEL_MP is not set # CONFIG_UDELAY_IO is not set -# CONFIG_UDELAY_LAPIC is not set -CONFIG_UDELAY_TSC=y -# CONFIG_TSC_CONSTANT_RATE is not set -# CONFIG_TSC_MONOTONIC_TIMER is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y @@ -238,7 +257,9 @@ CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -253,11 +274,10 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 # CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_GM45=y @@ -272,21 +292,39 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y +# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O # CONFIG_SUPERIO_NSC_PC87382=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y CONFIG_EC_LENOVO_PMH7=y +CONFIG_HAVE_INTEL_FIRMWARE=y + +# +# Intel Firmware +# +# CONFIG_EM100 is not set +# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set # CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set @@ -303,6 +341,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -342,7 +384,9 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_AP_IN_SIPI_WAIT is not set # CONFIG_SIPI_VECTOR_IN_ROM is not set # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set # CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set @@ -353,37 +397,42 @@ CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_POSTCAR_STAGE is not set # CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set # CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # @@ -394,8 +443,9 @@ CONFIG_DRIVERS_LENOVO_WACOM=y # CONFIG_DIGITIZER_AUTODETECT is not set CONFIG_DIGITIZER_PRESENT=y # CONFIG_DIGITIZER_ABSENT is not set -# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set -# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set # CONFIG_DRIVERS_UART is not set @@ -410,37 +460,60 @@ CONFIG_NO_UART_ON_SUPERIO=y # CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set CONFIG_HAVE_USBDEBUG=y CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_DRIVERS_GENERIC_IOAPIC=y CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set # CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set # CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set # CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# # CONFIG_ACPI_SATA_GENERATOR is not set # CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set # CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console @@ -450,6 +523,7 @@ CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_NE2K is not set CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -460,25 +534,29 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set # CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set -# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set CONFIG_HAVE_OPTION_TABLE=y # CONFIG_PIRQ_ROUTE is not set CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -497,6 +575,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -525,16 +604,17 @@ CONFIG_COMPRESSED_PAYLOAD_LZMA=y CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set # CONFIG_TRACE is not set # CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set @@ -543,3 +623,8 @@ CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_REG_SCRIPT is not set # CONFIG_CREATE_BOARD_CHECKLIST is not set # CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From b4a5e6c1ff7ae916b9dc4cf3dbcfcf47d10a7b3b Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 11 Jan 2018 21:38:52 -0500 Subject: Update Coreboot config for board x60 This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * VGA_TEXT_FRAMEBUFFER=y * UART_PCI_ADDR=0x0 --- projects/coreboot/configs/seabios/x60/config | 313 ++++++++++++++++++--------- 1 file changed, 210 insertions(+), 103 deletions(-) diff --git a/projects/coreboot/configs/seabios/x60/config b/projects/coreboot/configs/seabios/x60/config index f73cd211..952be764 100644 --- a/projects/coreboot/configs/seabios/x60/config +++ b/projects/coreboot/configs/seabios/x60/config @@ -6,47 +6,38 @@ # # General setup # +CONFIG_COREBOOT_BUILD=y CONFIG_LOCALVERSION="" CONFIG_CBFS_PREFIX="fallback" -# CONFIG_MULTIPLE_CBFS_INSTANCES is not set CONFIG_COMPILER_GCC=y # CONFIG_COMPILER_LLVM_CLANG is not set # CONFIG_ANY_TOOLCHAIN is not set # CONFIG_CCACHE is not set # CONFIG_FMD_GENPARSER is not set -# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set CONFIG_USE_OPTION_TABLE=y CONFIG_STATIC_OPTION_TABLE=y -# CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y -# CONFIG_COMPRESS_PRERAM_STAGES is not set CONFIG_INCLUDE_CONFIG_FILE=y -CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set # CONFIG_USE_BLOBS is not set # CONFIG_COVERAGE is not set -# CONFIG_RELOCATABLE_MODULES is not set -# CONFIG_RELOCATABLE_RAMSTAGE is not set -CONFIG_FLASHMAP_OFFSET=0x0 -CONFIG_BOOTBLOCK_SIMPLE=y -# CONFIG_BOOTBLOCK_NORMAL is not set -CONFIG_BOOTBLOCK_CUSTOM=y -CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" -# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y # CONFIG_UPDATE_IMAGE is not set -# CONFIG_GENERIC_GPIO_LIB is not set -# CONFIG_BOARD_ID_AUTO is not set -# CONFIG_BOARD_ID_MANUAL is not set -# CONFIG_RAM_CODE_SUPPORT is not set # CONFIG_BOOTSPLASH_IMAGE is not set -# CONFIG_ACPI_SATA_GENERATOR is not set # # Mainboard # + +# +# Important: Run 'make distclean' before switching boards +# # CONFIG_VENDOR_A_TREND is not set # CONFIG_VENDOR_AAEON is not set # CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set # CONFIG_VENDOR_ADLINK is not set # CONFIG_VENDOR_ADVANSUS is not set # CONFIG_VENDOR_AMD is not set @@ -60,16 +51,18 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # CONFIG_VENDOR_BACHMANN is not set # CONFIG_VENDOR_BAP is not set # CONFIG_VENDOR_BCOM is not set -# CONFIG_VENDOR_BIFFEROS is not set # CONFIG_VENDOR_BIOSTAR is not set # CONFIG_VENDOR_BROADCOM is not set # CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set # CONFIG_VENDOR_CUBIETECH is not set # CONFIG_VENDOR_DIGITALLOGIC is not set # CONFIG_VENDOR_DMP is not set # CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set # CONFIG_VENDOR_EMULATION is not set # CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set # CONFIG_VENDOR_GETAC is not set # CONFIG_VENDOR_GIGABYTE is not set # CONFIG_VENDOR_GIZMOSPHERE is not set @@ -86,6 +79,7 @@ CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_LINUTOP is not set # CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set # CONFIG_VENDOR_MITAC is not set # CONFIG_VENDOR_MSI is not set # CONFIG_VENDOR_NEC is not set @@ -97,6 +91,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_RCA is not set # CONFIG_VENDOR_RODA is not set # CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set # CONFIG_VENDOR_SIEMENS is not set # CONFIG_VENDOR_SOYO is not set # CONFIG_VENDOR_SUNW is not set @@ -108,6 +103,7 @@ CONFIG_VENDOR_LENOVO=y # CONFIG_VENDOR_TYAN is not set # CONFIG_VENDOR_VIA is not set # CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set # CONFIG_VENDOR_WYSE is not set CONFIG_BOARD_SPECIFIC_OPTIONS=y CONFIG_MAINBOARD_DIR="lenovo/x60" @@ -115,42 +111,52 @@ CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60" CONFIG_IRQ_SLOT_COUNT=18 CONFIG_MAINBOARD_VENDOR="LENOVO" CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 +CONFIG_CBFS_SIZE=0x200000 CONFIG_VGA_BIOS_ID="8086,27a2" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 # CONFIG_VGA_BIOS is not set -# CONFIG_UDELAY_IO is not set -CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_BASE=0xfefc0000 CONFIG_DCACHE_RAM_SIZE=0x8000 CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" CONFIG_MAX_REBOOT_CNT=3 -CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y CONFIG_ID_SECTION_OFFSET=0x80 -CONFIG_RAMTOP=0x200000 -CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 -CONFIG_CBFS_SIZE=0x200000 CONFIG_POST_DEVICE=y +# CONFIG_VBOOT is not set +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_DRIVERS_UART_8250IO=y # CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set # CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set # CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set # CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set # CONFIG_BOARD_LENOVO_T430S is not set # CONFIG_BOARD_LENOVO_T500 is not set # CONFIG_BOARD_LENOVO_T520 is not set # CONFIG_BOARD_LENOVO_T530 is not set # CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set # CONFIG_BOARD_LENOVO_X200 is not set # CONFIG_BOARD_LENOVO_X201 is not set # CONFIG_BOARD_LENOVO_X220 is not set # CONFIG_BOARD_LENOVO_X220I is not set # CONFIG_BOARD_LENOVO_X230 is not set CONFIG_BOARD_LENOVO_X60=y -CONFIG_SEABIOS_PS2_TIMEOUT=3000 +# CONFIG_BOARD_LENOVO_Z61T is not set CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set -CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_PCIEXP_L1_SUB_STATE is not set # CONFIG_NO_POST is not set CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 CONFIG_BOARD_ROMSIZE_KB_2048=y @@ -162,11 +168,14 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y CONFIG_COREBOOT_ROMSIZE_KB_2048=y # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set # CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set CONFIG_COREBOOT_ROMSIZE_KB=2048 CONFIG_ROM_SIZE=0x200000 -CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set CONFIG_SYSTEM_TYPE_LAPTOP=y # CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set @@ -177,20 +186,37 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y # # SoC # +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" # CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" -CONFIG_EHCI_BAR=0xfef00000 -CONFIG_HEAP_SIZE=0x4000 -# CONFIG_SOC_MARVELL_ARMADA38X is not set -# CONFIG_SOC_MARVELL_BG4CD is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set # CONFIG_SOC_NVIDIA_TEGRA124 is not set -# CONFIG_SOC_NVIDIA_TEGRA132 is not set # CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set # CONFIG_SOC_UCB_RISCV is not set @@ -211,25 +237,30 @@ CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y CONFIG_SSE2=y # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set CONFIG_UDELAY_LAPIC=y CONFIG_LAPIC_MONOTONIC_TIMER=y # CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set -# CONFIG_TSC_CALIBRATE_WITH_IO is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_SMM_TSEG is not set CONFIG_SMM_LAPIC_REMAP_MITIGATION=y # CONFIG_SERIALIZED_SMM_INITIALIZATION is not set # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set -# CONFIG_PARALLEL_MP is not set -# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set CONFIG_SMP=y CONFIG_AP_SIPI_VECTOR=0xfffff000 CONFIG_MMX=y @@ -244,28 +275,20 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y # Northbridge # # CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set # CONFIG_AMD_NB_CIMX is not set # CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set -CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set -CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_I945=y # CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_I945_LVDS=y CONFIG_CHANNEL_XOR_RANDOMIZATION=y # CONFIG_OVERRIDE_CLOCK_DISABLE is not set # CONFIG_CHECK_SLFRCS_ON_RESUME is not set -# CONFIG_VRAM_SIZE_1MB is not set -# CONFIG_VRAM_SIZE_4MB is not set -# CONFIG_VRAM_SIZE_8MB is not set -# CONFIG_VRAM_SIZE_16MB is not set -# CONFIG_VRAM_SIZE_32MB is not set -# CONFIG_VRAM_SIZE_48MB is not set -CONFIG_VRAM_SIZE_64MB=y -CONFIG_VRAM_SIZE=0x70 CONFIG_HPET_ADDRESS=0xfed00000 -CONFIG_HPET_MIN_TICKS=0x80 CONFIG_MAX_PIRQ_LINKS=4 # @@ -275,7 +298,12 @@ CONFIG_MAX_PIRQ_LINKS=4 # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set # CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set CONFIG_SOUTHBRIDGE_INTEL_COMMON=y -# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y @@ -284,16 +312,22 @@ CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y # CONFIG_SUPERIO_NSC_PC87382=y CONFIG_SUPERIO_NSC_PC87392=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set # # Embedded Controllers # CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y # CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set # CONFIG_ARCH_VERSTAGE_ARM is not set @@ -309,6 +343,10 @@ CONFIG_EC_LENOVO_PMH7=y # CONFIG_ARCH_RAMSTAGE_ARMV7 is not set # CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set # CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set # CONFIG_ARM_LPAE is not set # CONFIG_ARCH_ARM64 is not set # CONFIG_ARCH_BOOTBLOCK_ARM64 is not set @@ -347,114 +385,165 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_USE_MARCH_586 is not set CONFIG_AP_IN_SIPI_WAIT=y # CONFIG_SIPI_VECTOR_IN_ROM is not set -CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y # CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set # CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set CONFIG_HAVE_CMOS_DEFAULT=y CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set -# CONFIG_COMPILE_IN_DSDT is not set -CONFIG_ROMSTAGE_ADDR=0x2000000 -CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" # # Devices # +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_LINEAR_FRAMEBUFFER=y CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y -CONFIG_NATIVE_VGA_INIT_USE_EDID=y -CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y -CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set # CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set # CONFIG_SMBUS_HAS_AUX_CHANNELS is not set -# CONFIG_SPD_CACHE is not set CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y # CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set CONFIG_PCIX_PLUGIN_SUPPORT=y -CONFIG_PCIEXP_PLUGIN_SUPPORT=y CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_AZALIA_PLUGIN_SUPPORT is not set -# CONFIG_PCIEXP_COMMON_CLOCK is not set -# CONFIG_PCIEXP_ASPM is not set -# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y # CONFIG_EARLY_PCI_BRIDGE is not set -# CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -# CONFIG_PXE_ROM is not set +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set # CONFIG_SOFTWARE_I2C is not set -# -# Display -# -# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set - # # Generic Drivers # # CONFIG_DRIVERS_AS3722_RTC is not set # CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +CONFIG_DRIVERS_LENOVO_WACOM=y +# CONFIG_DIGITIZER_AUTODETECT is not set +CONFIG_DIGITIZER_PRESENT=y +# CONFIG_DIGITIZER_ABSENT is not set +# CONFIG_CACHE_MRC_SETTINGS is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_SMM is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVERS_AMD_PI is not set CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +CONFIG_DRIVERS_I2C_CK505=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set # CONFIG_DRIVERS_I2C_RTD2132 is not set -CONFIG_DRIVERS_ICS_954309=y -# CONFIG_INTEL_DP is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set # CONFIG_INTEL_DDI is not set CONFIG_INTEL_EDID=y CONFIG_INTEL_INT15=y CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y # CONFIG_DRIVER_INTEL_I210 is not set -# CONFIG_IPMI_KCS is not set -CONFIG_DRIVERS_LENOVO_WACOM=y -# CONFIG_DIGITIZER_AUTODETECT is not set -CONFIG_DIGITIZER_PRESENT=y -# CONFIG_DIGITIZER_ABSENT is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set # CONFIG_DRIVER_MAXIM_MAX77686 is not set # CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set CONFIG_DRIVERS_MC146818=y # CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y # CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set # CONFIG_DRIVERS_SIL_3114 is not set -# CONFIG_SPI_FLASH is not set -# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set # CONFIG_DRIVER_TI_TPS65090 is not set # CONFIG_DRIVERS_TI_TPS65913 is not set # CONFIG_DRIVERS_TI_TPS65913_RTC is not set -# CONFIG_DRIVERS_UART is not set -# CONFIG_NO_UART_ON_SUPERIO is not set -# CONFIG_DRIVERS_UART_8250MEM is not set -# CONFIG_DRIVERS_UART_8250MEM_32 is not set -# CONFIG_HAVE_UART_SPECIAL is not set -# CONFIG_DRIVERS_UART_OXPCIE is not set -# CONFIG_DRIVERS_UART_PL011 is not set -CONFIG_HAVE_USBDEBUG=y -# CONFIG_HAVE_USBDEBUG_OPTIONS is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set -CONFIG_RTC=y +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set # CONFIG_TPM is not set -CONFIG_STACK_SIZE=0x1000 -CONFIG_MMCONF_SUPPORT_DEFAULT=y -CONFIG_MMCONF_SUPPORT=y -# CONFIG_BOOTMODE_STRAPS is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set # # Console # CONFIG_SQUELCH_EARLY_SMP=y # CONFIG_CONSOLE_SERIAL is not set -# CONFIG_CONSOLE_SERIAL_921600 is not set -# CONFIG_CONSOLE_SERIAL_460800 is not set -# CONFIG_CONSOLE_SERIAL_230400 is not set -# CONFIG_CONSOLE_SERIAL_115200 is not set -# CONFIG_CONSOLE_SERIAL_57600 is not set -# CONFIG_CONSOLE_SERIAL_38400 is not set -# CONFIG_CONSOLE_SERIAL_19200 is not set -# CONFIG_CONSOLE_SERIAL_9600 is not set # CONFIG_SPKMODEM is not set # CONFIG_CONSOLE_NE2K is not set -CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 # CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +# CONFIG_CONSOLE_SPI_FLASH is not set CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set @@ -471,7 +560,9 @@ CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_PCI_PCIE is not set CONFIG_POST_IO_PORT=0x80 # CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set CONFIG_RESUME_PATH_SAME_AS_BOOT=y CONFIG_HAVE_HARD_RESET=y # CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set @@ -486,7 +577,6 @@ CONFIG_HAVE_SMI_HANDLER=y # CONFIG_PCI_IO_CFG_EXT is not set CONFIG_IOAPIC=y CONFIG_USE_WATCHDOG_ON_BOOT=y -CONFIG_VGA=y # CONFIG_GFXUMA is not set CONFIG_HAVE_ACPI_TABLES=y CONFIG_HAVE_MP_TABLE=y @@ -506,6 +596,7 @@ CONFIG_GENERATE_SMBIOS_TABLES=y # # CONFIG_PAYLOAD_NONE is not set CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set # CONFIG_PAYLOAD_FILO is not set # CONFIG_PAYLOAD_GRUB2 is not set # CONFIG_PAYLOAD_SEABIOS is not set @@ -514,10 +605,17 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_TIANOCORE is not set CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# # CONFIG_COREINFO_SECONDARY_PAYLOAD is not set # CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set # # Debugging @@ -528,19 +626,28 @@ CONFIG_HAVE_DEBUG_RAM_SETUP=y # CONFIG_DEBUG_RAM_SETUP is not set # CONFIG_HAVE_DEBUG_CAR is not set # CONFIG_DEBUG_PIRQ is not set -# CONFIG_HAVE_DEBUG_SMBUS is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set # CONFIG_DEBUG_SMI is not set # CONFIG_DEBUG_SMM_RELOCATION is not set # CONFIG_DEBUG_MALLOC is not set # CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_SPI_FLASH is not set # CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set # CONFIG_ENABLE_APIC_EXT_ID is not set CONFIG_WARNINGS_ARE_ERRORS=y -CONFIG_IASL_WARNINGS_ARE_ERRORS=y # CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set # CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set # CONFIG_POWER_BUTTON_FORCE_ENABLE is not set # CONFIG_POWER_BUTTON_FORCE_DISABLE is not set # CONFIG_POWER_BUTTON_IS_OPTIONAL is not set # CONFIG_REG_SCRIPT is not set -# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y -- cgit v1.2.3-70-g09d2 From a8e95c3d8b30739ce1d64027c792ef310b4d1b84 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sun, 14 Jan 2018 23:22:35 -0500 Subject: Use project_sources_path() in archive creation Previously, the function 'project_release_sources_archive_path' assumed that a project's source files would always be located within "$root/$SOURCES" in a directory named after the project. However, this does not account for projects such as bucts whose source files are located in "$root/$PROJECTS/$project/sources". In order to address this, trivial changes were made to leverage project_sources_path() as it returns nearly all the information needed to create the path to the archive file. --- libs/project | 31 ++++--------------------------- 1 file changed, 4 insertions(+), 27 deletions(-) diff --git a/libs/project b/libs/project index 4c8b2fff..e5162fb5 100755 --- a/libs/project +++ b/libs/project @@ -1081,34 +1081,11 @@ project_release_sources_archive_path() { local project=$1 shift - local sources_path="$root/$SOURCES/" - local release_path - local argument - local path="$project" - - for argument in "" "$@" - do - if [[ -n "$argument" ]] - then - path="$path-$argument" - fi - - local directory_path="$sources_path/$path" + local repository="$project" + local sources_path="$(project_sources_path "$project" "$repository" "$@")" + local archive_path="$root/$RELEASE/$SOURCES/$project/${sources_path##*/}.$ARCHIVE" - if ! directory_filled_check "$directory_path" - then - continue - fi - - release_path=$path - done - - if [[ -n "$release_path" ]] - then - local archive_path="$root/$RELEASE/$SOURCES/$project/$release_path.$ARCHIVE" - - printf '%s\n' "$archive_path" - fi + printf '%s\n' "$archive_path" } project_release_sources_archive_create() { -- cgit v1.2.3-70-g09d2 From b2321c6f7be6e0d9fe1e9ef01427f353a0eb55a7 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 13 Jan 2018 16:59:15 -0500 Subject: Copy ich9gen sources into projects/ich9gen/sources Sources for ich9deblob and demefactory are included alongside ich9gen and preserved for future applications. --- projects/ich9gen/sources/Makefile | 92 +++ projects/ich9gen/sources/obj/.empty | 0 projects/ich9gen/sources/obj/common/.empty | 0 projects/ich9gen/sources/obj/descriptor/.empty | 0 projects/ich9gen/sources/obj/gbe/.empty | 0 projects/ich9gen/sources/obj/ich9gen/.empty | 0 .../ich9gen/sources/src/common/descriptor_gbe.c | 90 +++ .../ich9gen/sources/src/common/descriptor_gbe.h | 37 ++ .../ich9gen/sources/src/common/x86compatibility.c | 161 +++++ .../ich9gen/sources/src/common/x86compatibility.h | 42 ++ projects/ich9gen/sources/src/demefactory.c | 141 +++++ projects/ich9gen/sources/src/demefactory.h | 34 ++ .../ich9gen/sources/src/descriptor/descriptor.c | 665 +++++++++++++++++++++ .../ich9gen/sources/src/descriptor/descriptor.h | 333 +++++++++++ projects/ich9gen/sources/src/gbe/gbe.c | 454 ++++++++++++++ projects/ich9gen/sources/src/gbe/gbe.h | 435 ++++++++++++++ projects/ich9gen/sources/src/ich9deblob.c | 221 +++++++ projects/ich9gen/sources/src/ich9deblob.h | 38 ++ projects/ich9gen/sources/src/ich9gen.c | 150 +++++ projects/ich9gen/sources/src/ich9gen.h | 39 ++ .../ich9gen/sources/src/ich9gen/mkdescriptor.c | 229 +++++++ .../ich9gen/sources/src/ich9gen/mkdescriptor.h | 27 + projects/ich9gen/sources/src/ich9gen/mkgbe.c | 257 ++++++++ projects/ich9gen/sources/src/ich9gen/mkgbe.h | 29 + 24 files changed, 3474 insertions(+) create mode 100644 projects/ich9gen/sources/Makefile create mode 100644 projects/ich9gen/sources/obj/.empty create mode 100644 projects/ich9gen/sources/obj/common/.empty create mode 100644 projects/ich9gen/sources/obj/descriptor/.empty create mode 100644 projects/ich9gen/sources/obj/gbe/.empty create mode 100644 projects/ich9gen/sources/obj/ich9gen/.empty create mode 100644 projects/ich9gen/sources/src/common/descriptor_gbe.c create mode 100644 projects/ich9gen/sources/src/common/descriptor_gbe.h create mode 100644 projects/ich9gen/sources/src/common/x86compatibility.c create mode 100644 projects/ich9gen/sources/src/common/x86compatibility.h create mode 100644 projects/ich9gen/sources/src/demefactory.c create mode 100644 projects/ich9gen/sources/src/demefactory.h create mode 100644 projects/ich9gen/sources/src/descriptor/descriptor.c create mode 100644 projects/ich9gen/sources/src/descriptor/descriptor.h create mode 100644 projects/ich9gen/sources/src/gbe/gbe.c create mode 100644 projects/ich9gen/sources/src/gbe/gbe.h create mode 100644 projects/ich9gen/sources/src/ich9deblob.c create mode 100644 projects/ich9gen/sources/src/ich9deblob.h create mode 100644 projects/ich9gen/sources/src/ich9gen.c create mode 100644 projects/ich9gen/sources/src/ich9gen.h create mode 100644 projects/ich9gen/sources/src/ich9gen/mkdescriptor.c create mode 100644 projects/ich9gen/sources/src/ich9gen/mkdescriptor.h create mode 100644 projects/ich9gen/sources/src/ich9gen/mkgbe.c create mode 100644 projects/ich9gen/sources/src/ich9gen/mkgbe.h diff --git a/projects/ich9gen/sources/Makefile b/projects/ich9gen/sources/Makefile new file mode 100644 index 00000000..dad57e7f --- /dev/null +++ b/projects/ich9gen/sources/Makefile @@ -0,0 +1,92 @@ +# +# Makefile for ich9deblob utility from libreboot project +# +# Copyright (C) 2014, 2015 Leah Rowe +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +CC=gcc +FORCEC99=-std=c99 +CFLAGS=-I. -Wall -Wextra -g $(FORCEC99) +NOLINKER=-c + +all: ich9deblob ich9gen demefactory + +ich9deblob: obj/ich9deblob.o obj/common/descriptor_gbe.o \ + obj/descriptor/descriptor.o obj/gbe/gbe.o obj/common/x86compatibility.o + + $(CC) $(CFLAGS) obj/ich9deblob.o obj/common/descriptor_gbe.o \ + obj/common/x86compatibility.o obj/descriptor/descriptor.o obj/gbe/gbe.o \ + -o ich9deblob + +ich9gen: obj/ich9gen.o obj/ich9gen/mkdescriptor.o obj/ich9gen/mkgbe.o \ + obj/common/descriptor_gbe.o \ + obj/descriptor/descriptor.o obj/gbe/gbe.o obj/common/x86compatibility.o + + $(CC) $(CFLAGS) obj/ich9gen.o obj/ich9gen/mkdescriptor.o obj/ich9gen/mkgbe.o \ + obj/common/descriptor_gbe.o \ + obj/common/x86compatibility.o obj/descriptor/descriptor.o obj/gbe/gbe.o \ + -o ich9gen + +demefactory: obj/demefactory.o obj/common/descriptor_gbe.o \ + obj/descriptor/descriptor.o obj/gbe/gbe.o obj/common/x86compatibility.o + + $(CC) $(CFLAGS) obj/demefactory.o obj/common/descriptor_gbe.o \ + obj/common/x86compatibility.o obj/descriptor/descriptor.o obj/gbe/gbe.o \ + -o demefactory + +# for demefactory +# ---------------------------------------------------------------------- + +obj/demefactory.o: + $(CC) $(CFLAGS) $(NOLINKER) src/demefactory.c -o obj/demefactory.o + +# for ich9deblob +# ---------------------------------------------------------------------- + +obj/ich9deblob.o: + $(CC) $(CFLAGS) $(NOLINKER) src/ich9deblob.c -o obj/ich9deblob.o + +# for ich9gen +# ---------------------------------------------------------------------- + +obj/ich9gen.o: + $(CC) $(CFLAGS) $(NOLINKER) src/ich9gen.c -o obj/ich9gen.o + +obj/ich9gen/mkdescriptor.o: + $(CC) $(CFLAGS) $(NOLINKER) src/ich9gen/mkdescriptor.c -o obj/ich9gen/mkdescriptor.o + +obj/ich9gen/mkgbe.o: + $(CC) $(CFLAGS) $(NOLINKER) src/ich9gen/mkgbe.c -o obj/ich9gen/mkgbe.o + +# for demefactory, ich9deblob and ich9gen: +# ---------------------------------------------------------------------- + +obj/common/descriptor_gbe.o: + $(CC) $(CFLAGS) $(NOLINKER) src/common/descriptor_gbe.c -o obj/common/descriptor_gbe.o + +obj/common/x86compatibility.o: + $(CC) $(CFLAGS) $(NOLINKER) src/common/x86compatibility.c -o obj/common/x86compatibility.o + +obj/descriptor/descriptor.o: + $(CC) $(CFLAGS) $(NOLINKER) src/descriptor/descriptor.c -o obj/descriptor/descriptor.o + +obj/gbe/gbe.o: + $(CC) $(CFLAGS) $(NOLINKER) src/gbe/gbe.c -o obj/gbe/gbe.o + +# make clean +# ---------------------------------------------------------------------- +clean: + rm -Rf ich9deblob ich9gen demefactory obj/*.o obj/*/*.o diff --git a/projects/ich9gen/sources/obj/.empty b/projects/ich9gen/sources/obj/.empty new file mode 100644 index 00000000..e69de29b diff --git a/projects/ich9gen/sources/obj/common/.empty b/projects/ich9gen/sources/obj/common/.empty new file mode 100644 index 00000000..e69de29b diff --git a/projects/ich9gen/sources/obj/descriptor/.empty b/projects/ich9gen/sources/obj/descriptor/.empty new file mode 100644 index 00000000..e69de29b diff --git a/projects/ich9gen/sources/obj/gbe/.empty b/projects/ich9gen/sources/obj/gbe/.empty new file mode 100644 index 00000000..e69de29b diff --git a/projects/ich9gen/sources/obj/ich9gen/.empty b/projects/ich9gen/sources/obj/ich9gen/.empty new file mode 100644 index 00000000..e69de29b diff --git a/projects/ich9gen/sources/src/common/descriptor_gbe.c b/projects/ich9gen/sources/src/common/descriptor_gbe.c new file mode 100644 index 00000000..1c1ad32b --- /dev/null +++ b/projects/ich9gen/sources/src/common/descriptor_gbe.c @@ -0,0 +1,90 @@ +/* + * descriptor_gbe.c + * This file is part of the ich9deblob utility from the libreboot project + * + * Purpose: common descriptor/gbe functions used by ich9deblob + * + * Copyright (C) 2014, 2015 Leah Rowe + * Copyright (C) 2014 Steve Shenton + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "descriptor_gbe.h" + +/* + * create 12KiB file with descriptor, and then gbe immediately after. + */ +int notCreatedDescriptorGbeFile(struct DESCRIPTORREGIONRECORD descriptorStruct, struct GBEREGIONRECORD_8K gbeStruct8k, char* fileName) +{ + FILE* fileStream = NULL; + + /* delete old file before continuing */ + remove(fileName); + + /* open new file for writing the descriptor+gbe */ + fileStream = fopen(fileName, "ab"); + + /* write the descriptor region into the first part */ + if (DESCRIPTORREGIONSIZE != fwrite((uint8_t*)&descriptorStruct, 1, sizeof(descriptorStruct), fileStream)) + { + printf("\nerror: writing descriptor region failed\n"); + return 1; + } + + /* add gbe to the end of the file */ + if (GBEREGIONSIZE_8K != fwrite((uint8_t*)&gbeStruct8k, 1, sizeof(gbeStruct8k), fileStream)) + { + printf("\nerror: writing GBe region failed\n"); + return 1; + } + + fclose(fileStream); + + printf("descriptor and gbe successfully written to the file: %s\n", fileName); + printf("Now do: dd if=%s of=libreboot.rom bs=1 count=12k conv=notrunc\n", fileName); + printf("(in other words, add the modified descriptor+gbe to your ROM image)\n\n"); + + return 0; +} + +/* + * create 4KiB file with descriptor + */ +int notCreated4kDescriptorFile(struct DESCRIPTORREGIONRECORD descriptorStruct, char* fileName) +{ + FILE* fileStream = NULL; + + /* delete old file before continuing */ + remove(fileName); + + /* open new file for writing the descriptor+gbe */ + fileStream = fopen(fileName, "ab"); + + /* write the descriptor region into the first part */ + if (DESCRIPTORREGIONSIZE != fwrite((uint8_t*)&descriptorStruct, 1, sizeof(descriptorStruct), fileStream)) + { + printf("\nerror: writing descriptor region failed\n"); + return 1; + } + + + fclose(fileStream); + + printf("descriptor successfully written to the file: %s\n", fileName); + printf("Now do: dd if=%s of=yourrom.rom bs=1 count=4k conv=notrunc\n", fileName); + printf("(in other words, add the modified descriptor to your ROM image)\n\n"); + + return 0; +} diff --git a/projects/ich9gen/sources/src/common/descriptor_gbe.h b/projects/ich9gen/sources/src/common/descriptor_gbe.h new file mode 100644 index 00000000..b3713c80 --- /dev/null +++ b/projects/ich9gen/sources/src/common/descriptor_gbe.h @@ -0,0 +1,37 @@ +/* + * gbe_descriptor.h + * This file is part of the ich9deblob utility from the libreboot project + * + * Purpose: header file for descriptor_gbe.c + * + * Copyright (C) 2014, 2015 Leah Rowe + * Copyright (C) 2014 Steve Shenton + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef COMMON_DESCRIPTOR_GBE_H +#define COMMON_DESCRIPTOR_GBE_H + +#include +#include +#include + +#include "../descriptor/descriptor.h" /* structs describing what's in the descriptor region */ +#include "../gbe/gbe.h" /* structs describing what's in the gbe region */ + +int notCreatedDescriptorGbeFile(struct DESCRIPTORREGIONRECORD descriptorStruct, struct GBEREGIONRECORD_8K gbeStruct8k, char* fileName); +int notCreated4kDescriptorFile(struct DESCRIPTORREGIONRECORD descriptorStruct, char* fileName); + +#endif diff --git a/projects/ich9gen/sources/src/common/x86compatibility.c b/projects/ich9gen/sources/src/common/x86compatibility.c new file mode 100644 index 00000000..362c634b --- /dev/null +++ b/projects/ich9gen/sources/src/common/x86compatibility.c @@ -0,0 +1,161 @@ +/* + * x86compatibility.c + * This file is part of the ich9deblob utility from the libreboot project + * + * Purpose: compiler/cpu compatibility checks. ich9deblob is not portable, yet. + * + * Copyright (C) 2014 Steve Shenton + * Leah Rowe + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "x86compatibility.h" + +/* + * --------------------------------------------------------------------- + * x86 compatibility checking: + * --------------------------------------------------------------------- + */ + +/* fail if struct size is incorrect */ +int structSizesIncorrect(struct DESCRIPTORREGIONRECORD descriptorDummy, struct GBEREGIONRECORD_8K gbe8kDummy) +{ + unsigned int descriptorRegionStructSize = sizeof(descriptorDummy); + unsigned int gbeRegion8kStructSize = sizeof(gbe8kDummy); + + /* check compiler bit-packs in a compatible way. basically, it is expected that this code will be used on x86 */ + if (DESCRIPTORREGIONSIZE != descriptorRegionStructSize){ + printf("\nerror: compiler incompatibility: descriptor struct length is %i bytes (should be %i)\n", descriptorRegionStructSize, DESCRIPTORREGIONSIZE); + return 1; + } + if (GBEREGIONSIZE_8K != gbeRegion8kStructSize){ + printf("\nerror: compiler incompatibility: gbe struct length is %i bytes (should be %i)\n", gbeRegion8kStructSize, GBEREGIONSIZE_8K); + return 1; + } + + return 0; +} + +/* fail if members are presented in the wrong order */ +int structMembersWrongOrder() +{ + int i; + struct DESCRIPTORREGIONRECORD descriptorDummy; + uint8_t *meVsccTablePtr = (uint8_t*)&descriptorDummy.meVsccTable; + + /* These do not use bitfields. */ + descriptorDummy.meVsccTable.jid0 = 0x01020304; /* unsigned int 32-bit */ + descriptorDummy.meVsccTable.vscc0 = 0x10203040; /* unsigned int 32-bit */ + descriptorDummy.meVsccTable.jid1 = 0x11223344; /* unsigned int 32-bit */ + descriptorDummy.meVsccTable.vscc1 = 0x05060708; /* unsigned int 32-bit */ + descriptorDummy.meVsccTable.jid2 = 0x50607080; /* unsigned int 32-bit */ + descriptorDummy.meVsccTable.vscc2 = 0x55667788; /* unsigned int 32-bit */ + descriptorDummy.meVsccTable.padding[0] = 0xAA; /* unsigned char 8-bit */ + descriptorDummy.meVsccTable.padding[1] = 0xBB; /* unsigned char 8-bit */ + descriptorDummy.meVsccTable.padding[2] = 0xCC; /* unsigned char 8-bit */ + descriptorDummy.meVsccTable.padding[3] = 0xDD; /* unsigned char 8-bit */ + + /* + * Look from the top down, and concatenate the unsigned ints but + * with each unsigned in little endian order. + * Then, concatenate the unsigned chars in big endian order. (in the padding array) + * + * combined, these should become: + * 01020304 10203040 11223344 05060708 50607080 55667788 AA BB CC DD (ignore this. big endian. just working it out manually:) + * 04030201 40302010 44332211 08070605 80706050 88776655 AA BB CC DD (ignore this. not byte-separated, just working it out:) + * 04 03 02 01 40 30 20 10 44 33 22 11 08 07 06 05 80 70 60 50 88 77 66 55 AA BB CC DD <-- it should match this + */ + + if ( + ! + ( + *meVsccTablePtr == 0x04 && *(meVsccTablePtr+1) == 0x03 && *(meVsccTablePtr+2) == 0x02 && *(meVsccTablePtr+3) == 0x01 + && *(meVsccTablePtr+4) == 0x40 && *(meVsccTablePtr+5) == 0x30 && *(meVsccTablePtr+6) == 0x20 && *(meVsccTablePtr+7) == 0x10 + && *(meVsccTablePtr+8) == 0x44 && *(meVsccTablePtr+9) == 0x33 && *(meVsccTablePtr+10) == 0x22 && *(meVsccTablePtr+11) == 0x11 + && *(meVsccTablePtr+12) == 0x08 && *(meVsccTablePtr+13) == 0x07 && *(meVsccTablePtr+14) == 0x06 && *(meVsccTablePtr+15) == 0x05 + && *(meVsccTablePtr+16) == 0x80 && *(meVsccTablePtr+17) == 0x70 && *(meVsccTablePtr+18) == 0x60 && *(meVsccTablePtr+19) == 0x50 + && *(meVsccTablePtr+20) == 0x88 && *(meVsccTablePtr+21) == 0x77 && *(meVsccTablePtr+22) == 0x66 && *(meVsccTablePtr+23) == 0x55 + && *(meVsccTablePtr+24) == 0xAA && *(meVsccTablePtr+25) == 0xBB && *(meVsccTablePtr+26) == 0xCC && *(meVsccTablePtr+27) == 0xDD + ) + ) { + + printf("\nStruct member order check (descriptorDummy.meVsccTable) with junk/dummy data:"); + printf("\nShould be: 04 03 02 01 40 30 20 10 44 33 22 11 08 07 06 05 80 70 60 50 88 77 66 55 aa bb cc dd "); + printf("\nAnd it is: "); + + for (i = 0; i < 28; i++) { + printf("%02x ", *(meVsccTablePtr + i)); + } + printf("\nIncorrect order.\n"); + + return 1; + } + + return 0; +} + +/* fail if bit fields are presented in the wrong order */ +int structBitfieldWrongOrder() +{ + int i; + struct DESCRIPTORREGIONRECORD descriptorDummy; + uint8_t *flMap0Ptr = (uint8_t*)&descriptorDummy.flMaps.flMap0; + + descriptorDummy.flMaps.flMap0.FCBA = 0xA2; /* :8 --> 10100010 */ + descriptorDummy.flMaps.flMap0.NC = 0x02; /* :2 --> 10 */ + descriptorDummy.flMaps.flMap0.reserved1 = 0x38; /* :6 --> 111000 */ + descriptorDummy.flMaps.flMap0.FRBA = 0xD2; /* :8 --> 11010010 */ + descriptorDummy.flMaps.flMap0.NR = 0x05; /* :3 --> 101 */ + descriptorDummy.flMaps.flMap0.reserved2 = 0x1C; /* :5 --> 11100 */ + + /* + * Look from the top bottom up, and concatenate the binary strings. + * Then, convert the 8-bit groups to hex and reverse the (8-bit)byte order + * + * combined, these should become (in memory), in binary: + * 10100010 11100010 11010010 11100101 + * or in hex: + * A2 E2 D2 E5 + */ + + if (!(*flMap0Ptr == 0xA2 && *(flMap0Ptr+1) == 0xE2 && *(flMap0Ptr+2) == 0xD2 && *(flMap0Ptr+3) == 0xE5)) + { + printf("\nBitfield order check (descriptorDummy.flMaps.flMaps0) with junk/dummy data:"); + printf("\nShould be: a2 e2 d2 e5 "); + printf("\nAnd it is: "); + + for (i = 0; i < 4; i++) { + printf("%02x ", *(flMap0Ptr + i)); + } + printf("\nIncorrect order.\n"); + + return 1; + } + + return 0; +} + +/* Compatibility checks. This version of ich9deblob is not yet porable. */ +int systemOrCompilerIncompatible(struct DESCRIPTORREGIONRECORD descriptorStruct, struct GBEREGIONRECORD_8K gbeStruct8k) +{ + if (structSizesIncorrect(descriptorStruct, gbeStruct8k)) return 1; + if (IS_BIG_ENDIAN) { + printf("big endian not supported\n"); + return 1; + } + if (structBitfieldWrongOrder()) return 1; + if (structMembersWrongOrder()) return 1; + return 0; +} diff --git a/projects/ich9gen/sources/src/common/x86compatibility.h b/projects/ich9gen/sources/src/common/x86compatibility.h new file mode 100644 index 00000000..5a598adc --- /dev/null +++ b/projects/ich9gen/sources/src/common/x86compatibility.h @@ -0,0 +1,42 @@ +/* + * x86compatibility.h + * This file is part of the ich9deblob utility from the libreboot project + * + * Purpose: keep gcc/make happy. no actual code here, just function definitions. + * + * Copyright (C) 2014 Steve Shenton + * Leah Rowe + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef X86COMPATIBILITY_H +#define X86COMPATIBILITY_H + +#include +#include +#include + +/* http://esr.ibiblio.org/?p=5095 */ +#define IS_BIG_ENDIAN (*(uint16_t *)"\0\xff" < 0x100) + +#include "../descriptor/descriptor.h" /* structs describing what's in the descriptor region */ +#include "../gbe/gbe.h" /* structs describing what's in the gbe region */ + +int structSizesIncorrect(struct DESCRIPTORREGIONRECORD descriptorDummy, struct GBEREGIONRECORD_8K gbe8kDummy); +int structMembersWrongOrder(); +int structBitfieldWrongOrder(); +int systemOrCompilerIncompatible(struct DESCRIPTORREGIONRECORD descriptorStruct, struct GBEREGIONRECORD_8K gbeStruct8k); + +#endif diff --git a/projects/ich9gen/sources/src/demefactory.c b/projects/ich9gen/sources/src/demefactory.c new file mode 100644 index 00000000..596118cf --- /dev/null +++ b/projects/ich9gen/sources/src/demefactory.c @@ -0,0 +1,141 @@ +/* + * demefactory.c + * This file is part of the demefactory utility from the libreboot project + * + * Purpose: disable ME on GM45 factory firmware, but leave region intact + * enable read-write on all regions + * + * Copyright (C) 2014, 2015 Leah Rowe + * Copyright (C) 2014 Steve Shenton + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * demfactory utility - main + */ + +#include "demefactory.h" + +int main() +{ + struct DESCRIPTORREGIONRECORD descriptorStruct; + uint8_t* descriptorBuffer = (uint8_t*)&descriptorStruct; + + struct GBEREGIONRECORD_8K gbeStruct8k; /* not needed, except for compatibility checking */ + + char* romFilename = "factory.rom"; + char* descriptorFilename = "demefactory_4kdescriptor.bin"; + + unsigned int bufferLength; + unsigned int romSize; + + /* + * ------------------------------------------------------------------ + * Compatibility checks. This version of ich9deblob is not yet portable. + * ------------------------------------------------------------------ + */ + + if (systemOrCompilerIncompatible(descriptorStruct, gbeStruct8k)) return 1; + /* If true, fail with error message */ + + /* + * ------------------------------------------------------------------ + * Extract the descriptor region from the factory.rom dump + * ------------------------------------------------------------------ + */ + FILE* fp = NULL; + fp = fopen(romFilename, "rb"); /* open factory.rom */ + if (NULL == fp) + { + printf("\nerror: could not open %s\n", romFilename); + fclose(fp); + return 1; + } + printf("\n%s opened successfully\n", romFilename); + + /* + * Get the descriptor region dump from the factory.rom + * (goes in factoryDescriptorBuffer variable) + */ + bufferLength = fread(descriptorBuffer, 1, DESCRIPTORREGIONSIZE, fp); + if (DESCRIPTORREGIONSIZE != bufferLength) // + { + printf("\nerror: could not read descriptor from %s (%i) bytes read\n", romFilename, bufferLength); + fclose(fp); + return 1; + } + printf("\ndescriptor region read successfully\n"); + + /* ------------------------------------------------- */ + + fseek(fp, 0L, SEEK_END); + romSize = ftell(fp); + printf("\n%s size: [%i] bytes\n", romFilename, romSize); + + /* -------------------------------------------------- */ + + fclose(fp); + + /* Debugging (before modification) */ + printDescriptorRegionLocations(descriptorStruct, "Original"); + + /* + * ------------------------------------------------------------------ + * Modify the descriptor region, ready to go in the modified factory.rom + * ------------------------------------------------------------------ + */ + + // Disable the ME/TPM: + descriptorStruct = descriptorDisableMe(descriptorStruct); + descriptorStruct = descriptorDisableTpm(descriptorStruct); + + /* Host/CPU is allowed to read/write all regions. */ + descriptorStruct = descriptorHostRegionsUnlocked(descriptorStruct); + /* The ME is disallowed read-write access to all regions + * (this is probably redundant, since the ME is already removed from libreboot) */ + descriptorStruct = descriptorMeRegionsForbidden(descriptorStruct); + + /* Debugging (after modifying the descriptor region) */ + printDescriptorRegionLocations(descriptorStruct, "Modified"); + + /* + * ------------------------------------------------------------------ + * Create the file with the modified descriptor inside + * ------------------------------------------------------------------ + */ + + printf("\n"); + if (notCreated4kDescriptorFile(descriptorStruct, descriptorFilename)) { + return 1; + } + + /* + * ------------------------------------------------------------------ + * Generate ich9gen data (C code that will recreate the deactivatedME descriptor from scratch) + * ------------------------------------------------------------------ + */ + /* Code for generating the Descriptor struct */ + /* mkdescriptor.h */ + if (notCreatedHFileForDescriptorCFile("mkdescriptor.h", "mkdescriptor.c")) { + return 1; + } /* and now mkdescriptor.c */ + if (notCreatedCFileFromDescriptorStruct(descriptorStruct, "mkdescriptor.c", "mkdescriptor.h")) { + return 1; + } + + printf("The modified descriptor region has also been dumped as src files: mkdescriptor.c, mkdescriptor.h\n\n"); + + return 0; +} diff --git a/projects/ich9gen/sources/src/demefactory.h b/projects/ich9gen/sources/src/demefactory.h new file mode 100644 index 00000000..7226886b --- /dev/null +++ b/projects/ich9gen/sources/src/demefactory.h @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2015 Leah Rowe + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Header file for demefactory.c */ + +#ifndef DEMEFACTORY_H +#define DEMEFACTORY_H + +#include +#include +#include + +#include "common/descriptor_gbe.h" /* common descriptor/gbe functions used by ich9deblob */ +#include "common/x86compatibility.h" /* system/compiler compatibility checks. This code is not portable. */ +#include "descriptor/descriptor.h" /* structs describing what's in the descriptor region */ +#include "gbe/gbe.h" /* structs describing what's in the gbe region */ + +int main(); + +#endif diff --git a/projects/ich9gen/sources/src/descriptor/descriptor.c b/projects/ich9gen/sources/src/descriptor/descriptor.c new file mode 100644 index 00000000..18e4e17a --- /dev/null +++ b/projects/ich9gen/sources/src/descriptor/descriptor.c @@ -0,0 +1,665 @@ +/* + * descriptor/descriptor.c + * This file is part of the ich9deblob utility from the libreboot project + * + * Copyright (C) 2014, 2015 Leah Rowe + * Copyright (C) 2014 Steve Shenton + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Provide descriptor related functions. + */ + +/* structs describing the data in descriptor region */ +#include "descriptor.h" + +/* + * --------------------------------------------------------------------- + * Descriptor related functions + * --------------------------------------------------------------------- + */ + +/* Set the Host CPU / BIOS region to have read-write access on all regions */ +struct DESCRIPTORREGIONRECORD descriptorHostRegionsUnlocked(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.masterAccessSection.flMstr1.fdRegionReadAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.biosRegionReadAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.meRegionReadAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.gbeRegionReadAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.pdRegionReadAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x1; + + return descriptorStruct; +} + +/* Set the ME to have *no* read-write access on any region */ +struct DESCRIPTORREGIONRECORD descriptorMeRegionsForbidden(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.masterAccessSection.flMstr2.fdRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.biosRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.meRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.gbeRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.pdRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.fdRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.biosRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.meRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.gbeRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr2.pdRegionWriteAccess = 0x0; + + return descriptorStruct; +} + +/* Disable (delete) the ME region */ +struct DESCRIPTORREGIONRECORD descriptorMeRegionRemoved(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.regionSection.flReg2.BASE = 0x1FFF; + descriptorStruct.regionSection.flReg2.LIMIT = 0; + + return descriptorStruct; +} + +/* Disable (delete) the Platform region */ +struct DESCRIPTORREGIONRECORD descriptorPlatformRegionRemoved(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.regionSection.flReg4.BASE = 0x1FFF; + descriptorStruct.regionSection.flReg4.LIMIT = 0; + + return descriptorStruct; +} + +/* Disable the ME in ICHSTRAP0 and MCHSTRAP0 */ +struct DESCRIPTORREGIONRECORD descriptorDisableMe(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.ichStraps.ichStrap0.meDisable = 1; + descriptorStruct.mchStraps.mchStrap0.meDisable = 1; + + return descriptorStruct; +} + +/* Disable the TPM in MCHSTRAP0 */ +struct DESCRIPTORREGIONRECORD descriptorDisableTpm(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.mchStraps.mchStrap0.tpmDisable = 1; + + return descriptorStruct; +} + +/* Relocate the Gbe region to begin at 4KiB (immediately after the flash descriptor) */ +struct DESCRIPTORREGIONRECORD descriptorMoveGbeToStart(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.regionSection.flReg3.BASE = DESCRIPTORREGIONSIZE >> FLREGIONBITSHIFT; + descriptorStruct.regionSection.flReg3.LIMIT = GBEREGIONSIZE_8K >> FLREGIONBITSHIFT; + + return descriptorStruct; +} + +/* Disable (delete) the GbE region */ +struct DESCRIPTORREGIONRECORD descriptorGbeRegionRemoved(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.regionSection.flReg3.BASE = 0x1FFF; + descriptorStruct.regionSection.flReg3.LIMIT = 0; + + return descriptorStruct; +} + +/* BIOS Region begin after descriptor+gbe at first 12KiB, fills the rest of the image */ +struct DESCRIPTORREGIONRECORD descriptorBiosRegionFillImageAfterGbe(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize) +{ + descriptorStruct.regionSection.flReg1.BASE = (DESCRIPTORREGIONSIZE + GBEREGIONSIZE_8K) >> FLREGIONBITSHIFT; + descriptorStruct.regionSection.flReg1.LIMIT = (romSize >> FLREGIONBITSHIFT) - 1; + + return descriptorStruct; +} + +/* BIOS Region begin after descriptor at first 4KiB, fills the rest of the image */ +struct DESCRIPTORREGIONRECORD descriptorBiosRegionFillImageAfterDescriptor(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize) +{ + descriptorStruct.regionSection.flReg1.BASE = DESCRIPTORREGIONSIZE >> FLREGIONBITSHIFT; + descriptorStruct.regionSection.flReg1.LIMIT = (romSize >> FLREGIONBITSHIFT) - 1; + + return descriptorStruct; +} + +/* Set OEM string to "LIBERATE" */ +struct DESCRIPTORREGIONRECORD descriptorOemString(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + descriptorStruct.oemSection.magicString[0] = 0x4C; + descriptorStruct.oemSection.magicString[1] = 0x49; + descriptorStruct.oemSection.magicString[2] = 0x42; + descriptorStruct.oemSection.magicString[3] = 0x45; + descriptorStruct.oemSection.magicString[4] = 0x52; + descriptorStruct.oemSection.magicString[5] = 0x41; + descriptorStruct.oemSection.magicString[6] = 0x54; + descriptorStruct.oemSection.magicString[7] = 0x45; + + return descriptorStruct; +} + +/* Check whether a GbE region is defined by this descriptor. + * Not thorough, but should work in most cases */ +int descriptorDefinesGbeRegion(struct DESCRIPTORREGIONRECORD descriptorStruct) +{ + if ( + (descriptorStruct.regionSection.flReg3.BASE == 0x1FFF || descriptorStruct.regionSection.flReg3.BASE == 0xFFF) + && + (descriptorStruct.regionSection.flReg3.LIMIT == 0) + ) + return 0; /* has no GbE region */ + else if ( + descriptorStruct.ichStraps.ichStrap0.integratedGbe == 0 + || + descriptorStruct.ichStraps.ichStrap0.lanPhy == 0 + ) + return 0; /* has no GbE region */ + else + return 1; /* has a GbE region */ +} + +/* Configure the BIOS and GbE regions, as required by libreboot. + * Enable or disable the GbE region, based on what's in the descriptor */ +struct DESCRIPTORREGIONRECORD librebootSetGbeBiosDescriptorRegions(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize) +{ + if (descriptorDefinesGbeRegion(descriptorStruct)) + { + /* + * set number of regions from 4 -> 2 (0 based, so 4 means 5 and 2 + * means 3. We want 3 regions: descriptor, gbe and bios, in that order) + */ + descriptorStruct.flMaps.flMap0.NR = 2; + /* Move GbE region to the start of the image (after the descriptor) */ + descriptorStruct = descriptorMoveGbeToStart(descriptorStruct); + /* BIOS region fills the remaining space */ + descriptorStruct = descriptorBiosRegionFillImageAfterGbe(descriptorStruct, romSize); + + /* GbE region means that an Intel NIC is to be present */ + descriptorStruct.ichStraps.ichStrap0.integratedGbe = 0x1; + descriptorStruct.ichStraps.ichStrap0.lanPhy = 0x1; + } + else { + /* + * set number of regions from 4 -> 2 (0 based, so 4 means 5 and 1 + * means 2. We want 2 regions: descriptor and bios, in that order) + */ + descriptorStruct.flMaps.flMap0.NR = 1; + /* Disable the GbE region */ + descriptorStruct = descriptorGbeRegionRemoved(descriptorStruct); + /* BIOS region fills the remaining space, after the descriptor */ + descriptorStruct = descriptorBiosRegionFillImageAfterDescriptor(descriptorStruct, romSize); + + /* No GbE region means that an onboard NIC is still used, but it's discrete (eg Broadcom) */ + descriptorStruct.ichStraps.ichStrap0.integratedGbe = 0x0; + descriptorStruct.ichStraps.ichStrap0.lanPhy = 0x0; + } + + return descriptorStruct; +} + +uint8_t componentDensity(unsigned int romSizeInBytes) +{ + /* component density, see Component Section Record. page 848 in the datasheet */ + switch (romSizeInBytes) + { + case ROMSIZE_512KB: return 0; + case ROMSIZE_1MB: return 1; + case ROMSIZE_2MB: return 2; + case ROMSIZE_4MB: return 3; + case ROMSIZE_8MB: return 4; + case ROMSIZE_16MB: return 5; + default: return 0x7; /* reserved value */ + } +} + +/* From a factory.rom image, create a modified descriptor region, suitable + * for use by the libreboot project */ +struct DESCRIPTORREGIONRECORD librebootDescriptorStructFromFactory(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize) +{ + /* Enable or disable the GbE region, from what's in the descriptor */ + descriptorStruct = librebootSetGbeBiosDescriptorRegions(descriptorStruct, romSize); + + /* Disable the ME/TPM and remove the ME/Platform regions: */ + descriptorStruct = descriptorMeRegionRemoved(descriptorStruct); + /* Disable the ME/TPM and remove the ME/Platform regions: */ + descriptorStruct = descriptorPlatformRegionRemoved(descriptorStruct); + + /* Disable the ME itself, so that it doesn't try to start when this descriptor is in use */ + descriptorStruct = descriptorDisableMe(descriptorStruct); + /* Also disable the TPM, by default */ + descriptorStruct = descriptorDisableTpm(descriptorStruct); + + return descriptorStruct; +} + +/* + * --------------------------------------------------------------------- + * C code generator (self-writing code) + * --------------------------------------------------------------------- + */ + +/* + * Generate a C (.h) header file for the C source file made by notCreatedCFileFromDescriptorStruct() + * + * Output it to a file. + */ +int notCreatedHFileForDescriptorCFile(char* outFileName, char* cFileName) +{ + remove(outFileName); /* Remove the old file before continuing */ + + /* Open the file that will be written to */ + FILE* fp = fopen(outFileName, "w+"); + + /* ------------------------------ */ + + fprintf(fp, "/* %s: generated C code from ich9deblob */\n", outFileName); + fprintf(fp, "/* .h header file for the descriptor-generating C code (%s) */\n\n", cFileName); + + fprintf(fp, "#ifndef ICH9GEN_MKDESCRIPTOR_H\n"); + fprintf(fp, "#define ICH9GEN_MKDESCRIPTOR_H\n\n"); + + fprintf(fp, "#include \n"); + fprintf(fp, "#include \n"); + fprintf(fp, "#include \"../descriptor/descriptor.h\"\n\n"); + + fprintf(fp, "struct DESCRIPTORREGIONRECORD generatedDescriptorStruct(unsigned int romSize, int hasGbe);\n"); + + fprintf(fp, "#endif\n"); + + /* ------------------------------ */ + + fclose(fp); /* Always close the file when done. */ + + return 0; +} + +/* + * Generate a C source file that initializes the same data from a given + * 4KiB Descriptor data structure. + * + * Output it to a file. + */ +int notCreatedCFileFromDescriptorStruct(struct DESCRIPTORREGIONRECORD descriptorStruct, char* outFileName, char* headerFileName) +{ + int i, j; + + remove(outFileName); /* Remove the old file before continuing */ + + /* Open the file that will be written to */ + FILE* fp = fopen(outFileName, "w+"); + + /* ------------------------------ */ + + fprintf(fp, "/* %s: generated C code from ich9deblob */\n", outFileName); + fprintf(fp, "/* .c source file for the descriptor-generating C code */\n\n"); + + fprintf(fp, "#include \"%s\"\n\n", headerFileName); + + fprintf(fp, "/* Generate a 4KiB Descriptor struct, with default values. */\n"); + fprintf(fp, "/* Read ../descriptor/descriptor.h for an explanation of the default values used here */\n\n"); + + fprintf(fp, "struct DESCRIPTORREGIONRECORD generatedDescriptorStruct(unsigned int romSize, int hasGbe)\n"); + fprintf(fp, "{\n"); + fprintf(fp, " int i;\n"); + fprintf(fp, " struct DESCRIPTORREGIONRECORD descriptorStruct;\n"); + fprintf(fp, "\n"); + /* Flash Valid Signature Register */ + fprintf(fp, " /* Flash Valid Signature Register */\n"); + fprintf(fp, " descriptorStruct.flValSig.signature = 0x%08x;\n", descriptorStruct.flValSig.signature); + fprintf(fp, "\n"); + /* Flash Map Registers */ + fprintf(fp, " /* Flash Map Registers */\n"); + fprintf(fp, " /* FLMAP0 */\n"); + fprintf(fp, " descriptorStruct.flMaps.flMap0.FCBA = 0x%02x;\n", descriptorStruct.flMaps.flMap0.FCBA); + fprintf(fp, " descriptorStruct.flMaps.flMap0.NC = 0x%01x;\n", descriptorStruct.flMaps.flMap0.NC); + fprintf(fp, " descriptorStruct.flMaps.flMap0.reserved1 = 0x%02x;\n", descriptorStruct.flMaps.flMap0.reserved1); + fprintf(fp, " descriptorStruct.flMaps.flMap0.FRBA = 0x%02x;\n", descriptorStruct.flMaps.flMap0.FRBA); + fprintf(fp, " /* descriptorStruct.flMaps.flMap0.NR = 0x%01x; */ /* see ../descriptor/descriptor.c */\n", descriptorStruct.flMaps.flMap0.NR); + fprintf(fp, " descriptorStruct.flMaps.flMap0.NR = hasGbe ? 0x2 : 0x1; /* see ../descriptor/descriptor.c */\n"); + fprintf(fp, " descriptorStruct.flMaps.flMap0.reserved2 = 0x%02x;\n", descriptorStruct.flMaps.flMap0.reserved2); + fprintf(fp, " /* FLMAP1 */\n"); + fprintf(fp, " descriptorStruct.flMaps.flMap1.FMBA = 0x%02x;\n", descriptorStruct.flMaps.flMap1.FMBA); + fprintf(fp, " descriptorStruct.flMaps.flMap1.NM = 0x%01x;\n", descriptorStruct.flMaps.flMap1.NM); + fprintf(fp, " descriptorStruct.flMaps.flMap1.reserved = 0x%02x;\n", descriptorStruct.flMaps.flMap1.reserved); + fprintf(fp, " descriptorStruct.flMaps.flMap1.FISBA = 0x%02x;\n", descriptorStruct.flMaps.flMap1.FISBA); + fprintf(fp, " descriptorStruct.flMaps.flMap1.ISL = 0x%02x;\n", descriptorStruct.flMaps.flMap1.ISL); + fprintf(fp, " /* FLMAP2 */\n"); + fprintf(fp, " descriptorStruct.flMaps.flMap2.FMSBA = 0x%02x;\n", descriptorStruct.flMaps.flMap2.FMSBA); + fprintf(fp, " descriptorStruct.flMaps.flMap2.MSL = 0x%02x;\n", descriptorStruct.flMaps.flMap2.MSL); + fprintf(fp, " descriptorStruct.flMaps.flMap2.reserved = 0x%04x;\n", descriptorStruct.flMaps.flMap2.reserved); + fprintf(fp, "\n"); + /* Component Section Record */ + fprintf(fp, " /* Component Section Record */\n"); + fprintf(fp, " /* FLCOMP */\n"); + fprintf(fp, " /* descriptorStruct.componentSection.flcomp.component1Density = 0x%01x; */\n", descriptorStruct.componentSection.flcomp.component1Density); + fprintf(fp, " /* descriptorStruct.componentSection.flcomp.component2Density = 0x%01x; */\n", descriptorStruct.componentSection.flcomp.component2Density); + fprintf(fp, " descriptorStruct.componentSection.flcomp.component1Density = componentDensity(romSize);\n"); + fprintf(fp, " descriptorStruct.componentSection.flcomp.component2Density = componentDensity(romSize);\n"); + fprintf(fp, " descriptorStruct.componentSection.flcomp.reserved1 = 0x%01x;\n", descriptorStruct.componentSection.flcomp.reserved1); + fprintf(fp, " descriptorStruct.componentSection.flcomp.reserved2 = 0x%02x;\n", descriptorStruct.componentSection.flcomp.reserved2); + fprintf(fp, " descriptorStruct.componentSection.flcomp.reserved3 = 0x%01x;\n", descriptorStruct.componentSection.flcomp.reserved3); + fprintf(fp, " descriptorStruct.componentSection.flcomp.readClockFrequency = 0x%01x;\n", descriptorStruct.componentSection.flcomp.readClockFrequency); + fprintf(fp, " descriptorStruct.componentSection.flcomp.fastReadSupport = 0x%01x;\n", descriptorStruct.componentSection.flcomp.fastReadSupport); + fprintf(fp, " descriptorStruct.componentSection.flcomp.fastreadClockFrequency = 0x%01x;\n", descriptorStruct.componentSection.flcomp.fastreadClockFrequency); + fprintf(fp, " descriptorStruct.componentSection.flcomp.writeEraseClockFrequency = 0x%01x;\n", descriptorStruct.componentSection.flcomp.writeEraseClockFrequency); + fprintf(fp, " descriptorStruct.componentSection.flcomp.readStatusClockFrequency = 0x%01x;\n", descriptorStruct.componentSection.flcomp.readStatusClockFrequency); + fprintf(fp, " descriptorStruct.componentSection.flcomp.reserved4 = 0x%01x;\n", descriptorStruct.componentSection.flcomp.reserved4); + fprintf(fp, " /* FLILL */\n"); + fprintf(fp, " descriptorStruct.componentSection.flill = 0x%08x;\n", descriptorStruct.componentSection.flill); + fprintf(fp, " /* FLPB */\n"); + fprintf(fp, " descriptorStruct.componentSection.flpb = 0x%08x;\n", descriptorStruct.componentSection.flpb); + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 36; i++) { + if (descriptorStruct.componentSection.padding[i] != 0xFF) { + for (j = 0; j < 36; j++) { + fprintf(fp, " descriptorStruct.componentSection.padding[%d] = 0x%02x;\n", j, descriptorStruct.componentSection.padding[j]); + } + break; + } else if (i == 35) { + fprintf(fp, " for (i = 0; i < 36; i++) {\n"); + fprintf(fp, " descriptorStruct.componentSection.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + /* Flash Descriptor Region Section */ + fprintf(fp, " /* Flash Descriptor Region Section */\n"); + fprintf(fp, " /* FLREG0 (Descriptor) */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg0.BASE = 0x%04x;\n", descriptorStruct.regionSection.flReg0.BASE); + fprintf(fp, " descriptorStruct.regionSection.flReg0.reserved1 = 0x%01x;\n", descriptorStruct.regionSection.flReg0.reserved1); + fprintf(fp, " descriptorStruct.regionSection.flReg0.LIMIT = 0x%04x;\n", descriptorStruct.regionSection.flReg0.LIMIT); + fprintf(fp, " descriptorStruct.regionSection.flReg0.reserved2 = 0x%01x;\n", descriptorStruct.regionSection.flReg0.reserved2); + fprintf(fp, " /* FLREG1 (BIOS) */\n"); + fprintf(fp, " /* descriptorStruct.regionSection.flReg1.BASE = 0x%04x; */\n", descriptorStruct.regionSection.flReg1.BASE); + fprintf(fp, " descriptorStruct.regionSection.flReg1.BASE = (DESCRIPTORREGIONSIZE + (hasGbe ? GBEREGIONSIZE_8K : 0)) >> FLREGIONBITSHIFT; /* see ../descriptor/descriptor.c */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg1.reserved1 = 0x%01x;\n", descriptorStruct.regionSection.flReg1.reserved1); + fprintf(fp, " /* descriptorStruct.regionSection.flReg1.LIMIT = 0x%04x; */\n", descriptorStruct.regionSection.flReg1.LIMIT); + fprintf(fp, " descriptorStruct.regionSection.flReg1.LIMIT = ((romSize >> FLREGIONBITSHIFT) - 1); /* see ../descriptor/descriptor.c */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg1.reserved2 = 0x%01x;\n", descriptorStruct.regionSection.flReg1.reserved2); + fprintf(fp, " /* FLREG2 (ME) */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg2.BASE = 0x%04x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.regionSection.flReg2.BASE); + fprintf(fp, " descriptorStruct.regionSection.flReg2.reserved1 = 0x%01x;\n", descriptorStruct.regionSection.flReg2.reserved1); + fprintf(fp, " descriptorStruct.regionSection.flReg2.LIMIT = 0x%04x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.regionSection.flReg2.LIMIT); + fprintf(fp, " descriptorStruct.regionSection.flReg2.reserved2 = 0x%01x;\n", descriptorStruct.regionSection.flReg2.reserved2); + fprintf(fp, " /* FLREG3 (Gbe) */\n"); + fprintf(fp, " /* descriptorStruct.regionSection.flReg3.BASE = 0x%04x; */\n", descriptorStruct.regionSection.flReg3.BASE); + fprintf(fp, " descriptorStruct.regionSection.flReg3.BASE = hasGbe ? (DESCRIPTORREGIONSIZE >> FLREGIONBITSHIFT) : 0x1fff; /* see ../descriptor/descriptor.c */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg3.reserved1 = 0x%01x;\n", descriptorStruct.regionSection.flReg3.reserved1); + fprintf(fp, " /* descriptorStruct.regionSection.flReg3.LIMIT = 0x%04x; */\n", descriptorStruct.regionSection.flReg3.LIMIT); + fprintf(fp, " descriptorStruct.regionSection.flReg3.LIMIT = hasGbe ? (GBEREGIONSIZE_8K >> FLREGIONBITSHIFT) : 0x0000; /* see ../descriptor/descriptor.c */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg3.reserved2 = 0x%01x;\n", descriptorStruct.regionSection.flReg3.reserved2); + fprintf(fp, " /* FLREG4 (Platform) */\n"); + fprintf(fp, " descriptorStruct.regionSection.flReg4.BASE = 0x%04x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.regionSection.flReg4.BASE); + fprintf(fp, " descriptorStruct.regionSection.flReg4.reserved1 = 0x%01x;\n", descriptorStruct.regionSection.flReg4.reserved1); + fprintf(fp, " descriptorStruct.regionSection.flReg4.LIMIT = 0x%04x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.regionSection.flReg4.LIMIT); + fprintf(fp, " descriptorStruct.regionSection.flReg4.reserved2 = 0x%01x;\n", descriptorStruct.regionSection.flReg4.reserved2); + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 12; i++) { + if (descriptorStruct.regionSection.padding[i] != 0xFF) { + for (j = 0; j < 12; j++) { + fprintf(fp, " descriptorStruct.regionSection.padding[%d] = 0x%02x;\n", j, descriptorStruct.regionSection.padding[j]); + } + break; + } else if (i == 11) { + fprintf(fp, " for (i = 0; i < 12; i++) {\n"); + fprintf(fp, " descriptorStruct.regionSection.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + /* Master Access Section */ + fprintf(fp, " /* Master Access Section */\n"); + fprintf(fp, " /* FLMSTR1 (Host CPU / BIOS) */\n"); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.requesterId = 0x%04x;\n", descriptorStruct.masterAccessSection.flMstr1.requesterId); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.fdRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.fdRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.biosRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.biosRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.meRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.meRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.gbeRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.gbeRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.pdRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.pdRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.reserved1 = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr1.reserved1); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr1.reserved2 = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr1.reserved2); + fprintf(fp, " /* FLMSTR2 (ME) */\n"); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.requesterId = 0x%04x;\n", descriptorStruct.masterAccessSection.flMstr2.requesterId); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.fdRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.fdRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.biosRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.biosRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.meRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.meRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.gbeRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.gbeRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.pdRegionReadAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.pdRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.reserved1 = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr2.reserved1); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.fdRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.fdRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.biosRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.biosRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.meRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.meRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.gbeRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.gbeRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.pdRegionWriteAccess = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.masterAccessSection.flMstr2.pdRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr2.reserved2 = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr2.reserved2); + fprintf(fp, " /* FLMSTR3 (Gbe) */\n"); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.requesterId = 0x%04x;\n", descriptorStruct.masterAccessSection.flMstr3.requesterId); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.fdRegionReadAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.fdRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.biosRegionReadAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.biosRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.meRegionReadAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.meRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.gbeRegionReadAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.gbeRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.pdRegionReadAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.pdRegionReadAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.reserved1 = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.reserved1); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.fdRegionWriteAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.fdRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.biosRegionWriteAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.biosRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.meRegionWriteAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.meRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.gbeRegionWriteAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.gbeRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.pdRegionWriteAccess = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.pdRegionWriteAccess); + fprintf(fp, " descriptorStruct.masterAccessSection.flMstr3.reserved2 = 0x%01x;\n", descriptorStruct.masterAccessSection.flMstr3.reserved2); + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 148; i++) { + if (descriptorStruct.masterAccessSection.padding[i] != 0xFF) { + for (j = 0; j < 148; j++) { + fprintf(fp, " descriptorStruct.masterAccessSection.padding[%d] = 0x%02x;\n", j, descriptorStruct.masterAccessSection.padding[j]); + } + break; + } else if (i == 147) { + fprintf(fp, " for (i = 0; i < 148; i++) {\n"); + fprintf(fp, " descriptorStruct.masterAccessSection.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + /* ICH straps */ + fprintf(fp, " /* ICH straps */\n"); + fprintf(fp, " /* ICHSTRAP0 */\n"); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.meDisable = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.ichStraps.ichStrap0.meDisable); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.reserved1 = 0x%02x;\n", descriptorStruct.ichStraps.ichStrap0.reserved1); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.tcoMode = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap0.tcoMode); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.smBusAddress = 0x%02x;\n", descriptorStruct.ichStraps.ichStrap0.smBusAddress); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.bmcMode = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap0.bmcMode); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.tripPointSelect = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap0.tripPointSelect); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.reserved2 = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap0.reserved2); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.integratedGbe = hasGbe ? 0x1 : 0x0;\n"); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.lanPhy = hasGbe ? 0x1 : 0x0;\n"); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.reserved3 = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap0.reserved3); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.dmiRequesterId = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap0.dmiRequesterId); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap0.smBus2Address = 0x%02x;\n", descriptorStruct.ichStraps.ichStrap0.smBus2Address); + fprintf(fp, " /* ICHSTRAP1 */\n"); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.northMlink = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap1.northMlink); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.southMlink = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap1.southMlink); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.meSmbus = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap1.meSmbus); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.sstDynamic = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap1.sstDynamic); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.reserved1 = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap1.reserved1); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.northMlink2 = 0x%01x;\n", descriptorStruct.ichStraps.ichStrap1.northMlink2); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.reserved2 = 0x%02x;\n", descriptorStruct.ichStraps.ichStrap1.reserved2); + fprintf(fp, " descriptorStruct.ichStraps.ichStrap1.reserved3 = 0x%04x;\n", descriptorStruct.ichStraps.ichStrap1.reserved3); + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 248; i++) { + if (descriptorStruct.ichStraps.padding[i] != 0xFF) { + for (j = 0; j < 248; j++) { + fprintf(fp, " descriptorStruct.ichStraps.padding[%d] = 0x%02x;\n", j, descriptorStruct.ichStraps.padding[j]); + } + break; + } else if (i == 247) { + fprintf(fp, " for (i = 0; i < 248; i++) {\n"); + fprintf(fp, " descriptorStruct.ichStraps.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + /* MCH straps */ + fprintf(fp, " /* MCH straps */\n"); + fprintf(fp, " /* MCHSTRAP0 */\n"); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.meDisable = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.mchStraps.mchStrap0.meDisable); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.meBootFromFlash = 0x%01x;\n", descriptorStruct.mchStraps.mchStrap0.meBootFromFlash); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.tpmDisable = 0x%01x; /* see ../descriptor/descriptor.c */\n", descriptorStruct.mchStraps.mchStrap0.tpmDisable); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.reserved1 = 0x%01x;\n", descriptorStruct.mchStraps.mchStrap0.reserved1); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.spiFingerprint = 0x%01x;\n", descriptorStruct.mchStraps.mchStrap0.spiFingerprint); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.meAlternateDisable = 0x%01x;\n", descriptorStruct.mchStraps.mchStrap0.meAlternateDisable); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.reserved2 = 0x%02x;\n", descriptorStruct.mchStraps.mchStrap0.reserved2); + fprintf(fp, " descriptorStruct.mchStraps.mchStrap0.reserved3 = 0x%04x;\n", descriptorStruct.mchStraps.mchStrap0.reserved3); + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 3292; i++) { + if (descriptorStruct.mchStraps.padding[i] != 0xFF) { + for (j = 0; j < 3292; j++) { + fprintf(fp, " descriptorStruct.mchStraps.padding[%d] = 0x%02x;\n", j, descriptorStruct.mchStraps.padding[j]); + } + break; + } else if (i == 3291) { + fprintf(fp, " for (i = 0; i < 3292; i++) {\n"); + fprintf(fp, " descriptorStruct.mchStraps.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + /* ME VSCC Table */ + fprintf(fp, " /* ME VSCC Table */\n"); + fprintf(fp, " descriptorStruct.meVsccTable.jid0 = 0x%08x;\n", descriptorStruct.meVsccTable.jid0); + fprintf(fp, " descriptorStruct.meVsccTable.vscc0 = 0x%08x;\n", descriptorStruct.meVsccTable.vscc0); + fprintf(fp, " descriptorStruct.meVsccTable.jid1 = 0x%08x;\n", descriptorStruct.meVsccTable.jid1); + fprintf(fp, " descriptorStruct.meVsccTable.vscc1 = 0x%08x;\n", descriptorStruct.meVsccTable.vscc1); + fprintf(fp, " descriptorStruct.meVsccTable.jid2 = 0x%08x;\n", descriptorStruct.meVsccTable.jid2); + fprintf(fp, " descriptorStruct.meVsccTable.vscc2 = 0x%08x;\n", descriptorStruct.meVsccTable.vscc2); + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 4; i++) { + if (descriptorStruct.meVsccTable.padding[i] != 0xFF) { + for (j = 0; j < 4; j++) { + fprintf(fp, " descriptorStruct.meVsccTable.padding[%d] = 0x%02x;\n", j, descriptorStruct.meVsccTable.padding[j]); + } + break; + } else if (i == 3) { + fprintf(fp, " for (i = 0; i < 4; i++) {\n"); + fprintf(fp, " descriptorStruct.meVsccTable.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + /* Descriptor Map 2 Record */ + fprintf(fp, " /* Descriptor Map 2 Record */\n"); + fprintf(fp, " descriptorStruct.descriptor2Map.meVsccTableBaseAddress = 0x%02x;\n", descriptorStruct.descriptor2Map.meVsccTableBaseAddress); + fprintf(fp, " descriptorStruct.descriptor2Map.meVsccTableLength = 0x%02x;\n", descriptorStruct.descriptor2Map.meVsccTableLength); + fprintf(fp, " descriptorStruct.descriptor2Map.reserved = 0x%04x;\n", descriptorStruct.descriptor2Map.reserved); + fprintf(fp, "\n"); + /* OEM section */ + fprintf(fp, " /* OEM section */\n"); + fprintf(fp, " /* see ../descriptor/descriptor.c */\n"); + fprintf(fp, " /* Magic String (ascii characters) */\n"); + for(i = 0; i < 8; i++) { + fprintf(fp, " descriptorStruct.oemSection.magicString[%d] = 0x%02x;\n", i, descriptorStruct.oemSection.magicString[i]); + } + fprintf(fp, " /* Padding */\n"); + for (i = 0; i < 248; i++) { + if (descriptorStruct.oemSection.padding[i] != 0xFF) { + for (j = 0; j < 248; j++) { + fprintf(fp, " descriptorStruct.oemSection.padding[%d] = 0x%02x;\n", j, descriptorStruct.oemSection.padding[j]); + } + break; + } else if (i == 247) { + fprintf(fp, " for (i = 0; i < 248; i++) {\n"); + fprintf(fp, " descriptorStruct.oemSection.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + break; + } + } + fprintf(fp, "\n"); + fprintf(fp, " return descriptorStruct;\n"); + fprintf(fp, "}\n\n"); + + /* ------------------------------ */ + + fclose(fp); /* Always close the file when done. */ + + return 0; +} + +/* + * --------------------------------------------------------------------- + * Debugging functions: + * --------------------------------------------------------------------- + */ + +/* + * show debugging info: descriptor region boundaries, in a 4KB struct. + */ +void printDescriptorRegionLocations(struct DESCRIPTORREGIONRECORD descriptorStruct, char* romName) +{ + printf("\n"); + + /* Descriptor region */ + printf( + "%s: Descriptor start block: %08x ; Descriptor end block: %08x\n", + romName, + descriptorStruct.regionSection.flReg0.BASE << FLREGIONBITSHIFT, + descriptorStruct.regionSection.flReg0.LIMIT << FLREGIONBITSHIFT + ); + + /* BIOS region */ + printf( + "%s: BIOS start block: %08x ; BIOS end block: %08x\n", + romName, + descriptorStruct.regionSection.flReg1.BASE << FLREGIONBITSHIFT, + descriptorStruct.regionSection.flReg1.LIMIT << FLREGIONBITSHIFT + ); + + /* ME region */ + printf( + "%s: ME start block: %08x ; ME end block: %08x\n", + romName, + descriptorStruct.regionSection.flReg2.BASE << FLREGIONBITSHIFT, + descriptorStruct.regionSection.flReg2.LIMIT << FLREGIONBITSHIFT + ); + + /* GBe region */ + printf( + "%s: GBe start block: %08x ; GBe end block: %08x\n", + romName, + descriptorStruct.regionSection.flReg3.BASE << FLREGIONBITSHIFT, + descriptorStruct.regionSection.flReg3.LIMIT << FLREGIONBITSHIFT + ); + + /* Platform region */ + printf( + "%s: Platform start block: %08x ; Platform end block: %08x\n", + romName, + descriptorStruct.regionSection.flReg4.BASE << FLREGIONBITSHIFT, + descriptorStruct.regionSection.flReg4.LIMIT << FLREGIONBITSHIFT + ); + + return; +} diff --git a/projects/ich9gen/sources/src/descriptor/descriptor.h b/projects/ich9gen/sources/src/descriptor/descriptor.h new file mode 100644 index 00000000..7fb5c257 --- /dev/null +++ b/projects/ich9gen/sources/src/descriptor/descriptor.h @@ -0,0 +1,333 @@ +/* + * descriptor/descriptor.h + * This file is part of the ich9deblob utility from the libreboot project + * + * Copyright (C) 2014, 2015 Leah Rowe + * Copyright (C) 2014 Steve Shenton + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Purpose: provide struct representing descriptor region. + * Map actual buffers of this regions, directly to instances of these + * structs. This makes working with descriptor really easy. + * + * bit fields used, corresponding to datasheet. See links to datasheets + * and documentation in ich9deblob.c + */ + +/* + * See docs/hardware/x200_remove_me.html for info plus links to datasheet (also linked below) + * + * Info about flash descriptor (read page 845 onwards): + * http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datasheet.pdf + */ + +#ifndef DESCRIPTORSTRUCT_H +#define DESCRIPTORSTRUCT_H + +#include +#include +#include +#include "../gbe/gbe.h" /* Needed for GBEREGIONSIZE_4K/8K define */ + +/* size of the descriptor in bytes */ +#define DESCRIPTORREGIONSIZE 0x1000 + +/* ROM image sizes in bytes */ +#define ROMSIZE_512KB 0x80000 +#define ROMSIZE_1MB 0x100000 +#define ROMSIZE_2MB 0x200000 +#define ROMSIZE_4MB 0x400000 +#define ROMSIZE_8MB 0x800000 +#define ROMSIZE_16MB 0x1000000 + +/* + * Related to the flash descriptor + * bits 12(0xC)-24(0x18) are represented for words found in the flash descriptor + * To manipulate these easily in C, we shift them by FLREGIONBITSHIFT and then shift them back when done + * (because this is how data is stored in the flash descriptor) + */ +#define FLREGIONBITSHIFT 0xC + +/* + * --------------------------------------------------------------------- + * Descriptor struct representing the data + * --------------------------------------------------------------------- + */ + +/* Flash Valid Signature Register */ +struct FLVALSIG +{ + /* + * 4 bytes. + * descriptor mode = 0FF0A55A (hex, big endian). Note: stored in ROM in little endian order. + * Anything else is considered invalid and will put the system in non-descriptor mode. + */ + uint32_t signature; /* Put 0x0FF0A55A here. confirmed in deblobbed_descriptor.bin */ +}; + +/* */ +struct FLMAP0 +{ + /* least signicant bits */ + uint8_t FCBA : 8; + uint8_t NC : 2; + uint8_t reserved1 : 6; + uint8_t FRBA : 8; + uint8_t NR : 3; + uint8_t reserved2 : 5; + /* most significant bits. */ +}; + +struct FLMAP1 +{ + /* least significant bits */ + uint8_t FMBA : 8; + uint8_t NM : 3; + uint8_t reserved : 5; + uint8_t FISBA : 8; + uint8_t ISL : 8; + /* most significant bits */ +}; + +struct FLMAP2 +{ + /* least significant bits */ + uint8_t FMSBA : 8; + uint8_t MSL : 8; + uint16_t reserved : 16; + /* most significant bits */ +}; + +/* Flash Map Registers */ +struct FLMAPS +{ + struct FLMAP0 flMap0; + struct FLMAP1 flMap1; + struct FLMAP2 flMap2; +}; + +/* Flash Components Register */ +struct FLCOMP +{ + /* least significant bits */ + uint8_t component1Density : 3; + uint8_t component2Density : 3; + uint8_t reserved1 : 2; + uint8_t reserved2 : 8; + uint8_t reserved3 : 1; + uint8_t readClockFrequency : 3; + uint8_t fastReadSupport : 1; + uint8_t fastreadClockFrequency : 3; + uint8_t writeEraseClockFrequency : 3; + uint8_t readStatusClockFrequency : 3; + uint8_t reserved4 : 2; + /* most significant bits */ +}; + +struct COMPONENTSECTIONRECORD +{ + struct FLCOMP flcomp; + uint32_t flill; + uint32_t flpb; + uint8_t padding[36]; +}; + +struct FLREG +{ + /* least significant bits */ + uint16_t BASE : 13; + uint16_t reserved1 : 3; + uint16_t LIMIT : 13; + uint16_t reserved2 : 3; + /* most significant bits */ +}; + +/* Flash Descriptor Region Section */ +/* + * Defines where all the regions begin/end. + * This is very important for disabling ME/AMT + */ +struct REGIONSECTIONRECORD +{ + struct FLREG flReg0; /* Descriptor */ + struct FLREG flReg1; /* BIOS */ + struct FLREG flReg2; /* ME */ + struct FLREG flReg3; /* Gbe */ + struct FLREG flReg4; /* Platform */ + uint8_t padding[12]; +}; + +struct FLMSTR +{ + /* least significant bits */ + uint16_t requesterId : 16; + uint8_t fdRegionReadAccess : 1; + uint8_t biosRegionReadAccess : 1; + uint8_t meRegionReadAccess : 1; + uint8_t gbeRegionReadAccess : 1; + uint8_t pdRegionReadAccess : 1; + uint8_t reserved1 : 3; /* Must be zero, according to datasheet */ + uint8_t fdRegionWriteAccess : 1; + uint8_t biosRegionWriteAccess : 1; + uint8_t meRegionWriteAccess : 1; + uint8_t gbeRegionWriteAccess : 1; + uint8_t pdRegionWriteAccess : 1; + uint8_t reserved2 : 3; /* Must be zero, according to datasheet */ + /* most significant bits */ +}; + +/* Master Access Section */ +struct MASTERACCESSSECTIONRECORD +{ + struct FLMSTR flMstr1; /* Flash Master 1 (Host CPU / BIOS) */ + struct FLMSTR flMstr2; /* Flash Master 2 (ME) */ + struct FLMSTR flMstr3; /* Flash Master 3 (Gbe) */ + uint8_t padding[148]; +}; + +struct ICHSTRAP0 +{ + /* least significant bits */ + /* todo: add MeSmBus2Sel (boring setting) */ + uint8_t meDisable : 1; /* If true, ME is disabled. */ + uint8_t reserved1 : 6; + uint8_t tcoMode : 1; /* TCO Mode: (Legacy,TCO Mode) The TCO Mode, along with the BMCMODE strap, determines the behavior of the IAMT SmBus controller. */ + uint8_t smBusAddress : 7; /* The ME SmBus 7-bit address. */ + uint8_t bmcMode : 1; /* BMC mode: If true, device is in BMC mode. If Intel(R) AMT or ASF using Intel integrated LAN then this should be false. */ + uint8_t tripPointSelect : 1; /* Trip Point Select: false the NJCLK input buffer is matched to 3.3v signal from the external PHY device, true is matched to 1.8v. */ + uint8_t reserved2 : 2; + uint8_t integratedGbe : 1; /* Integrated GbE or PCI Express select: (PCI Express,,Integrated GbE) Defines what PCIe Port 6 is used for. */ + uint8_t lanPhy : 1; /* LANPHYPC_GP12_SEL: Set to 0 for GP12 to be used as GPIO (General Purpose Input/Output), or 1 for GP12 to be used for native mode as LAN_PHYPC for 82566 LCD device */ + uint8_t reserved3 : 3; + uint8_t dmiRequesterId : 1; /* DMI requestor ID security check disable: The primary purpose of this strap is to support server environments with multiple CPUs that each have a different RequesterID that can access the Flash. */ + uint8_t smBus2Address : 7; /* The ME SmBus 2 7-bit address. */ + /* most significant bits */ +}; + +struct ICHSTRAP1 +{ + /* least significant bits */ + uint8_t northMlink : 1; /* North MLink Dynamic Clock Gate Disable : Sets the default value for the South MLink Dynamic Clock Gate Enable registers. */ + uint8_t southMlink : 1; /* South MLink Dynamic Clock Gate Enable : Sets the default value for the South MLink Dynamic Clock Gate Enable registers. */ + uint8_t meSmbus : 1; /* ME SmBus Dynamic Clock Gate Enable : Sets the default value for the ME SMBus Dynamic Clock Gate Enable for both the ME SmBus controllers. */ + uint8_t sstDynamic : 1; /* SST Dynamic Clock Gate Enable : Sets the default value for the SST Clock Gate Enable registers. */ + uint8_t reserved1 : 4; + uint8_t northMlink2 : 1; /* North MLink 2 Non-Posted Enable : 'true':North MLink supports two downstream non-posted requests. 'false':North MLink supports one downstream non-posted requests. */ + uint8_t reserved2 : 7; + uint16_t reserved3 : 16; + /* most significant bits */ +}; + +/* ICH straps */ +struct ICHSTRAPSRECORD +{ + struct ICHSTRAP0 ichStrap0; + struct ICHSTRAP1 ichStrap1; + uint8_t padding[248]; +}; + +struct MCHSTRAP0 +{ + /* least significant bits */ + uint8_t meDisable : 1; /* If true, ME is disabled. */ + uint8_t meBootFromFlash : 1; /* ME boot from Flash - guessed location */ + uint8_t tpmDisable : 1; /* iTPM Disable : When set true, iTPM Host Interface is disabled. When set false (default), iTPM is enabled. */ + uint8_t reserved1 : 3; + uint8_t spiFingerprint : 1; /* SPI Fingerprint Sensor Present: Indicates if an SPI Fingerprint sensor is present at CS#1. */ + uint8_t meAlternateDisable : 1; /* ME Alternate Disable: Setting this bit allows ME to perform critical chipset functions but prevents loading of any ME FW applications. */ + uint8_t reserved2 : 8; + uint16_t reserved3 : 16; + /* most significant bits */ +}; + +/* MCH straps */ +struct MCHSTRAPSRECORD +{ + struct MCHSTRAP0 mchStrap0; + uint8_t padding[3292]; +}; + +/* ME VSCC Table */ +struct MEVSCCTABLERECORD +{ + uint32_t jid0; + uint32_t vscc0; + uint32_t jid1; + uint32_t vscc1; + uint32_t jid2; + uint32_t vscc2; + uint8_t padding[4]; +}; + +/* Descriptor Map 2 Record */ +struct DESCRIPTORMAP2RECORD +{ + /* least significant bits */ + uint8_t meVsccTableBaseAddress : 8; + uint8_t meVsccTableLength : 8; + uint16_t reserved : 16; + /* most significant bits */ +}; + +/* OEM section */ +struct OEMSECTIONRECORD +{ + uint8_t magicString[8]; + uint8_t padding[248]; +}; + +/* 4KiB descriptor region, goes at the beginning of the ROM image */ +struct DESCRIPTORREGIONRECORD +{ + struct FLVALSIG flValSig; /* Flash Valid Signature Register */ + struct FLMAPS flMaps; /* Flash Map Registers */ + struct COMPONENTSECTIONRECORD componentSection; /* Component Section Record */ + struct REGIONSECTIONRECORD regionSection; /* Flash Descriptor Region Section */ + struct MASTERACCESSSECTIONRECORD masterAccessSection; /* Master Access Section */ + struct ICHSTRAPSRECORD ichStraps; /* ICH straps */ + struct MCHSTRAPSRECORD mchStraps; /* MCH straps */ + struct MEVSCCTABLERECORD meVsccTable; /* ME VSCC Table */ + struct DESCRIPTORMAP2RECORD descriptor2Map; /* Descriptor Map 2 Record */ + struct OEMSECTIONRECORD oemSection; /* OEM section */ +}; + +/* + * --------------------------------------------------------------------- + * Function declarations (keep gcc/make happy. check them in descriptor.c) + * --------------------------------------------------------------------- + */ + +struct DESCRIPTORREGIONRECORD descriptorHostRegionsUnlocked(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorMeRegionsForbidden(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorMeRegionRemoved(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorPlatformRegionRemoved(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorDisableMe(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorDisableTpm(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorMoveGbeToStart(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorGbeRegionRemoved(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD descriptorBiosRegionFillImageAfterGbe(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize); +struct DESCRIPTORREGIONRECORD descriptorBiosRegionFillImageAfterDescriptor(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize); +struct DESCRIPTORREGIONRECORD descriptorOemString(struct DESCRIPTORREGIONRECORD descriptorStruct); +int descriptorDefinesGbeRegion(struct DESCRIPTORREGIONRECORD descriptorStruct); +struct DESCRIPTORREGIONRECORD librebootSetGbeBiosDescriptorRegions(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize); +uint8_t componentDensity(unsigned int romSizeInBytes); +struct DESCRIPTORREGIONRECORD librebootDescriptorStructFromFactory(struct DESCRIPTORREGIONRECORD descriptorStruct, unsigned int romSize); +int notCreatedHFileForDescriptorCFile(char* outFileName, char* cFileName); +int notCreatedCFileFromDescriptorStruct(struct DESCRIPTORREGIONRECORD descriptorStruct, char* outFileName, char* headerFileName); +void printDescriptorRegionLocations(struct DESCRIPTORREGIONRECORD descriptorStruct, char* romName); + +#endif diff --git a/projects/ich9gen/sources/src/gbe/gbe.c b/projects/ich9gen/sources/src/gbe/gbe.c new file mode 100644 index 00000000..d04b8f2a --- /dev/null +++ b/projects/ich9gen/sources/src/gbe/gbe.c @@ -0,0 +1,454 @@ +/* + * gbe/gbe.c + * This file is part of the ich9deblob utility from the libreboot project + * + * Copyright (C) 2014 Steve Shenton + * Leah Rowe + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Provide gbe related functions. + */ + +/* structs describing the data from gbe region */ +#include "gbe.h" + +/* + * --------------------------------------------------------------------- + * Gbe functions: + * --------------------------------------------------------------------- + */ + +/* gbe checksum calculation (algorithm based on datasheet) */ +uint16_t gbeGetChecksumFrom4kBuffer(uint16_t* gbeWord, uint16_t desiredValue, int gbeRegionBase) +{ + int wordOffset; + uint16_t total = 0; + + for (wordOffset = 0; wordOffset < 0x3F; wordOffset++) + total += gbeWord[wordOffset + (gbeRegionBase>>1)]; + + return desiredValue - total; +} + +/* checksum calculation for 4k gbe struct (algorithm based on datasheet) */ +uint16_t gbeGetChecksumFrom4kStruct(struct GBEREGIONRECORD_4K gbeStruct4k, uint16_t desiredValue) +{ + return gbeGetChecksumFrom4kBuffer((uint16_t*)&gbeStruct4k, desiredValue, 0); +} + +/* modify the gbe region extracted from a factory.rom dump */ +struct GBEREGIONRECORD_8K deblobbedGbeStructFromFactory(struct GBEREGIONRECORD_8K gbeStruct8k) +{ + unsigned int i; + + /* + * http://www.intel.co.uk/content/dam/doc/application-note/82573-nvm-map-appl-note.pdf + * That is a datasheet for a later chipset. Word 40H-53H seems (as per this datasheet) to be for AMT. + * Writing over it doesn't seem to cause any harm, since the ME/AMT is already removed in libreboot. + */ + for(i = 0; i < sizeof(gbeStruct8k.backup.padding); i++) { + gbeStruct8k.backup.padding[i] = 0xFF; /* FF is correct. In the struct, this is a char buffer. */ + } /* We really only need to do this for words 40h-53h, but let's just nuke the whole lot. It's all 0xFF anyway. */ + + /* Fix the checksum */ + gbeStruct8k.backup.checkSum = gbeGetChecksumFrom4kStruct(gbeStruct8k.backup, GBECHECKSUMTOTAL); + + /* Main Gbe region on X200 (as shipped by Lenovo) is broken. Fix it by over-writing it with the contents of the backup */ + memcpy(&gbeStruct8k.main, &gbeStruct8k.backup, GBEREGIONSIZE_4K); + + return gbeStruct8k; +} + +/* + * --------------------------------------------------------------------- + * C code generator (self-writing code) + * --------------------------------------------------------------------- + */ + +/* + * Generate a C (.h) header file for the C source file made by notCreatedCFileFromGbeStruct4k() + * + * Output it to a file. + */ +int notCreatedHFileForGbeCFile(char* outFileName, char* cFileName) +{ + remove(outFileName); /* Remove the old file before continuing */ + + /* Open the file that will be written to */ + FILE* fp = fopen(outFileName, "w+"); + + /* ------------------------------ */ + + fprintf(fp, "/* %s: generated C code from ich9deblob */\n", outFileName); + fprintf(fp, "/* .h header file for the gbe-generating C code (%s) */\n\n", cFileName); + + fprintf(fp, "#ifndef ICH9GEN_MKGBE_H\n"); + fprintf(fp, "#define ICH9GEN_MKGBE_H\n\n"); + + fprintf(fp, "#include \n"); + fprintf(fp, "#include \n"); + fprintf(fp, "#include \"../gbe/gbe.h\"\n\n"); + + fprintf(fp, "struct GBEREGIONRECORD_4K generatedGbeStruct4k();\n"); + fprintf(fp, "struct GBEREGIONRECORD_8K generatedGbeStruct8k();\n\n"); + + fprintf(fp, "#endif\n"); + + /* ------------------------------ */ + + fclose(fp); /* Always close the file when done. */ + + return 0; +} +/* + * Generate a C source file that initializes the same data from a given + * 4KiB Gbe data structure. + * + * It will simply copy the 4KiB struct at the end to make a full 8KiB struct. + * So just pass a working 4KiB Gbe struct here and you're good to go. + * + * Output it to a file. + */ +int notCreatedCFileFromGbeStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* outFileName, char* headerFileName) +{ + int i; + int paddingSize; + int paddingIdentical; + + remove(outFileName); /* Remove the old file before continuing */ + + /* Open the file that will be written to */ + FILE* fp = fopen(outFileName, "w+"); + + /* ------------------------------ */ + + fprintf(fp, "/* %s: generated C code from ich9deblob */\n", outFileName); + fprintf(fp, "/* .c source file for the gbe-generating C code */\n\n"); + + fprintf(fp, "#include \"%s\"\n\n", headerFileName); + + fprintf(fp, "/* Generate a 4KiB Gbe struct, with default values. */\n"); + fprintf(fp, "/* Read ../gbe/gbe.h for an explanation of the default values used here */\n\n"); + + fprintf(fp, "struct GBEREGIONRECORD_4K generatedGbeStruct4k()\n"); + fprintf(fp, "{\n"); + fprintf(fp, " int i;\n"); + fprintf(fp, " struct GBEREGIONRECORD_4K gbeStruct4k;\n"); + fprintf(fp, "\n"); + /* Words 00h to 02h: MAC Address */ + fprintf(fp, " /* MAC address (words 00h to 02h) */\n"); + fprintf(fp, " /* see ../gbe/gbe.c */\n"); + for (i = 0; i < 6; i++) { + fprintf(fp, " gbeStruct4k.macAddress[%d] = 0x%02x;\n", i, gbeStruct4k.macAddress[i]); + } + fprintf(fp, "\n"); + /* Word 03h (Reserved) */ + fprintf(fp, " /* Word 03h (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord03h.reserved1_0 = 0x%02x;\n", gbeStruct4k.reservedWord03h.reserved1_0); + fprintf(fp, " gbeStruct4k.reservedWord03h.reserved1_1 = 0x%01x;\n", gbeStruct4k.reservedWord03h.reserved1_1); + fprintf(fp, " gbeStruct4k.reservedWord03h.ibaLom = 0x%01x;\n", gbeStruct4k.reservedWord03h.ibaLom); + fprintf(fp, " gbeStruct4k.reservedWord03h.reserved2 = 0x%01x;\n", gbeStruct4k.reservedWord03h.reserved2); + fprintf(fp, "\n"); + /* Word 04h (Reserved) */ + fprintf(fp, " /* Word 04h (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord04h = 0x%04x;\n", gbeStruct4k.reservedWord04h); + fprintf(fp, "\n"); + /* Word 05h (Image Version Information) */ + fprintf(fp, " /* Word 05h (Image Version Information) */\n"); + fprintf(fp, " gbeStruct4k.imageVersionInformation = 0x%04x;\n", gbeStruct4k.imageVersionInformation); + fprintf(fp, "\n"); + /* Words 06h and 07h (Reserved) */ + fprintf(fp, " /* Words 06h and 07h (Reserved) */\n"); + for (i = 0; i < 2; i++) { + fprintf(fp, " gbeStruct4k.reservedWords06h07h[%d] = 0x%04x;\n", i, gbeStruct4k.reservedWords06h07h[i]); + } + fprintf(fp, "\n"); + /* Words 08h and 09h (PBA Low and PBA High) */ + fprintf(fp, " /* Word 08h and 09h (PBA Low and PBA High) */\n"); + fprintf(fp, " gbeStruct4k.pbaLow = 0x%04x;\n", gbeStruct4k.pbaLow); + fprintf(fp, " gbeStruct4k.pbaHigh = 0x%04x;\n", gbeStruct4k.pbaHigh); + fprintf(fp, "\n"); + /* Word 0Ah (PCI Initialization Control Word) */ + fprintf(fp, " /* Word 0Ah (PCI Initialization Control Word) */\n"); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.loadVendorDeviceId = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.loadVendorDeviceId); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.loadSubsystemId = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.loadSubsystemId); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.reserved1 = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.reserved1); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.reserved2 = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.reserved2); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.pmEnable = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.pmEnable); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.auxPwr = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.auxPwr); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.reserved3 = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.reserved3); + fprintf(fp, " gbeStruct4k.pciInitializationControlWord.reserved4 = 0x%01x;\n", gbeStruct4k.pciInitializationControlWord.reserved4); + fprintf(fp, "\n"); + /* Word 0Bh (Subsystem ID) */ + fprintf(fp, " /* Word 0Bh (Subsystem ID) */\n"); + fprintf(fp, " gbeStruct4k.subsystemId = 0x%04x;\n", gbeStruct4k.subsystemId); + fprintf(fp, "\n"); + /* Word 0Ch (Subsystem Vendor ID) */ + fprintf(fp, " /* Word 0Ch (Subsystem Vendor ID) */\n"); + fprintf(fp, " gbeStruct4k.subsystemVendorId = 0x%04x;\n", gbeStruct4k.subsystemVendorId); + fprintf(fp, "\n"); + /* Word 0Dh (Device ID) */ + fprintf(fp, " /* Word 0Dh (Device ID) */\n"); + fprintf(fp, " gbeStruct4k.deviceId = 0x%04x;\n", gbeStruct4k.deviceId); + fprintf(fp, "\n"); + /* Word 0Eh (Vendor ID) */ + fprintf(fp, " /* Word 0Eh (Vendor ID) */\n"); + fprintf(fp, " gbeStruct4k.vendorId = 0x%04x;\n", gbeStruct4k.vendorId); + fprintf(fp, "\n"); + /* Word 0Fh (Device Revision ID) */ + fprintf(fp, " /* Word 0Fh (Device Revision ID) */\n"); + fprintf(fp, " gbeStruct4k.deviceRevId = 0x%04x;\n", gbeStruct4k.deviceRevId); + fprintf(fp, "\n"); + /* Word 10h (LAN Power Consumption) */ + fprintf(fp, " /* Word 10h (LAN Power Consumption) */\n"); + fprintf(fp, " gbeStruct4k.lanPowerConsumption.lanD3Power = 0x%02x;\n", gbeStruct4k.lanPowerConsumption.lanD3Power); + fprintf(fp, " gbeStruct4k.lanPowerConsumption.reserved = 0x%01x;\n", gbeStruct4k.lanPowerConsumption.reserved); + fprintf(fp, " gbeStruct4k.lanPowerConsumption.lanD0Power = 0x%02x;\n", gbeStruct4k.lanPowerConsumption.lanD0Power); + fprintf(fp, "\n"); + /* Words 11h and 12h (Reserved) */ + fprintf(fp, " /* Words 11h and 12h (Reserved) */\n"); + for (i = 0; i < 2; i++) { + fprintf(fp, " gbeStruct4k.reservedWords11h12h[%d] = 0x%04x;\n", i, gbeStruct4k.reservedWords11h12h[i]); + } + fprintf(fp, "\n"); + /* Word 13h (Shared Initialization Control Word) */ + fprintf(fp, " /* Word 13h (Shared Initialization Control Word) */\n"); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.reserved1 = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.reserved1); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.forceDuplex = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.forceDuplex); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.forceSpeedEnable = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.forceSpeedEnable); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.reserved2_0 = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.reserved2_0); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.reserved2_1 = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.reserved2_1); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.phyPowerDownEnable = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.phyPowerDownEnable); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.reserved3 = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.reserved3); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.reserved4 = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.reserved4); + fprintf(fp, " gbeStruct4k.sharedInitializationControlWord.sign = 0x%01x;\n", gbeStruct4k.sharedInitializationControlWord.sign); + fprintf(fp, "\n"); + /* Word 14h (Extended Configuration Control Word 1) */ + fprintf(fp, " /* Word 14h (Extended Configuration Control Word 1) */\n"); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord1.extendedConfigurationPointer = 0x%03x;\n", gbeStruct4k.extendedConfigurationControlWord1.extendedConfigurationPointer); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord1.oemWriteEnable = 0x%01x;\n", gbeStruct4k.extendedConfigurationControlWord1.oemWriteEnable); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord1.reserved1 = 0x%01x;\n", gbeStruct4k.extendedConfigurationControlWord1.reserved1); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord1.reserved2 = 0x%01x;\n", gbeStruct4k.extendedConfigurationControlWord1.reserved2); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord1.reserved3 = 0x%01x;\n", gbeStruct4k.extendedConfigurationControlWord1.reserved3); + fprintf(fp, "\n"); + /* Word 15h (Extended Configuration Control Word 2) */ + fprintf(fp, " /* Word 15h (Extended Configuration Control Word 2) */\n"); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord2.reserved = 0x%02x;\n", gbeStruct4k.extendedConfigurationControlWord2.reserved); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord2.extendedPhyLength = 0x%02x;\n", gbeStruct4k.extendedConfigurationControlWord2.extendedPhyLength); + fprintf(fp, "\n"); + /* Word 16h (Extended Configuration Control Word 3) */ + fprintf(fp, " /* Word 16h (Extended Configuration Control Word 3) */\n"); + fprintf(fp, " gbeStruct4k.extendedConfigurationControlWord3 = 0x%04x;\n", gbeStruct4k.extendedConfigurationControlWord3); + fprintf(fp, "\n"); + /* Word 17h (LED 1 Configuration and Power Management) */ + fprintf(fp, " /* Word 17h (LED 1 Configuration and Power Management) */\n"); + fprintf(fp, " gbeStruct4k.ledCtl1.led1Mode = 0x%01x;\n", gbeStruct4k.ledCtl1.led1Mode); + fprintf(fp, " gbeStruct4k.ledCtl1.reserved1 = 0x%01x;\n", gbeStruct4k.ledCtl1.reserved1); + fprintf(fp, " gbeStruct4k.ledCtl1.led1BlinkMode = 0x%01x;\n", gbeStruct4k.ledCtl1.led1BlinkMode); + fprintf(fp, " gbeStruct4k.ledCtl1.led1Invert = 0x%01x;\n", gbeStruct4k.ledCtl1.led1Invert); + fprintf(fp, " gbeStruct4k.ledCtl1.led1Blink = 0x%01x;\n", gbeStruct4k.ledCtl1.led1Blink); + fprintf(fp, " gbeStruct4k.ledCtl1.reserved2 = 0x%01x;\n", gbeStruct4k.ledCtl1.reserved2); + fprintf(fp, " gbeStruct4k.ledCtl1.lpluEnable = 0x%01x;\n", gbeStruct4k.ledCtl1.lpluEnable); + fprintf(fp, " gbeStruct4k.ledCtl1.lpluEnableNonD0a = 0x%01x;\n", gbeStruct4k.ledCtl1.lpluEnableNonD0a); + fprintf(fp, " gbeStruct4k.ledCtl1.gbeDisableNonD0a = 0x%01x;\n", gbeStruct4k.ledCtl1.gbeDisableNonD0a); + fprintf(fp, " gbeStruct4k.ledCtl1.reserved3 = 0x%01x;\n", gbeStruct4k.ledCtl1.reserved3); + fprintf(fp, " gbeStruct4k.ledCtl1.gbeDisable = 0x%01x;\n", gbeStruct4k.ledCtl1.gbeDisable); + fprintf(fp, " gbeStruct4k.ledCtl1.reserved4 = 0x%01x;\n", gbeStruct4k.ledCtl1.reserved4); + fprintf(fp, "\n"); + /* Word 18h (LED 0 and 2 Configuration Defaults) */ + fprintf(fp, " /* Word 18h (LED 0 and 2 Configuration Defaults) */\n"); + fprintf(fp, " gbeStruct4k.ledCtl02.led0Mode = 0x%01x;\n", gbeStruct4k.ledCtl02.led0Mode); + fprintf(fp, " gbeStruct4k.ledCtl02.reserved1 = 0x%01x;\n", gbeStruct4k.ledCtl02.reserved1); + fprintf(fp, " gbeStruct4k.ledCtl02.led0BlinkMode = 0x%01x;\n", gbeStruct4k.ledCtl02.led0BlinkMode); + fprintf(fp, " gbeStruct4k.ledCtl02.led0Invert = 0x%01x;\n", gbeStruct4k.ledCtl02.led0Invert); + fprintf(fp, " gbeStruct4k.ledCtl02.led0Blink = 0x%01x;\n", gbeStruct4k.ledCtl02.led0Blink); + fprintf(fp, " gbeStruct4k.ledCtl02.led2Mode = 0x%01x;\n", gbeStruct4k.ledCtl02.led2Mode); + fprintf(fp, " gbeStruct4k.ledCtl02.reserved2 = 0x%01x;\n", gbeStruct4k.ledCtl02.reserved2); + fprintf(fp, " gbeStruct4k.ledCtl02.led2BlinkMode = 0x%01x;\n", gbeStruct4k.ledCtl02.led2BlinkMode); + fprintf(fp, " gbeStruct4k.ledCtl02.led2Invert = 0x%01x;\n", gbeStruct4k.ledCtl02.led2Invert); + fprintf(fp, " gbeStruct4k.ledCtl02.led2Blink = 0x%01x;\n", gbeStruct4k.ledCtl02.led2Blink); + fprintf(fp, "\n"); + /* Word 19h (Reserved) */ + fprintf(fp, " /* Word 19h (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord19h = 0x%04x;\n", gbeStruct4k.reservedWord19h); + fprintf(fp, "\n"); + /* Word 1Ah (Reserved) */ + fprintf(fp, " /* Word 1Ah (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord1Ah = 0x%04x;\n", gbeStruct4k.reservedWord1Ah); + fprintf(fp, "\n"); + /* Word 1Bh (Reserved) */ + fprintf(fp, " /* Word 1Bh (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord1Bh = 0x%04x;\n", gbeStruct4k.reservedWord1Bh); + fprintf(fp, "\n"); + /* Word 1Ch (Reserved) */ + fprintf(fp, " /* Word 1Ch (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord1Ch = 0x%04x;\n", gbeStruct4k.reservedWord1Ch); + fprintf(fp, "\n"); + /* Word 1Dh (Reserved) */ + fprintf(fp, " /* Word 1Dh (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord1Dh = 0x%04x;\n", gbeStruct4k.reservedWord1Dh); + fprintf(fp, "\n"); + /* Word 1Eh (Device ID for Intel 82567LM gigabit ethernet controller) */ + fprintf(fp, " /* Word 1Eh (Device ID for Intel 82567LM gigabit ethernet controller) */\n"); + fprintf(fp, " gbeStruct4k._82567lmDeviceId = 0x%04x;\n", gbeStruct4k._82567lmDeviceId); + fprintf(fp, "\n"); + /* Word 1Fh (Device ID for Intel 82567LF gigabit ethernet controller) */ + fprintf(fp, " /* Word 1Fh (Device ID for Intel 82567LF gigabit ethernet controller) */\n"); + fprintf(fp, " gbeStruct4k._82567lfDeviceId = 0x%04x;\n", gbeStruct4k._82567lfDeviceId); + fprintf(fp, "\n"); + /* Word 20h (Reserved) */ + fprintf(fp, " /* Word 20h (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord20h = 0x%04x;\n", gbeStruct4k.reservedWord20h); + fprintf(fp, "\n"); + /* Word 21h (Device ID for Intel 82567V gigabit ethernet controller) */ + fprintf(fp, " /* Word 21h (Device ID for Intel 82567V gigabit ethernet controller) */\n"); + fprintf(fp, " gbeStruct4k._82567vDeviceId = 0x%04x;\n", gbeStruct4k._82567vDeviceId); + fprintf(fp, "\n"); + /* Word 22h (Reserved) */ + fprintf(fp, " /* Word 22h (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord22h = 0x%04x;\n", gbeStruct4k.reservedWord22h); + fprintf(fp, "\n"); + /* Word 23h (Reserved) */ + fprintf(fp, " /* Word 23h (Reserved) */\n"); + fprintf(fp, " gbeStruct4k.reservedWord23h = 0x%04x;\n", gbeStruct4k.reservedWord23h); + fprintf(fp, "\n"); + /* Words 24h to 2Fh (Reserved) */ + fprintf(fp, " /* Words 24h to 2Fh (Reserved) */\n"); + for (i = 0; i < 12; i++) { + fprintf(fp, " gbeStruct4k.reservedWords24to2Fh[%d] = 0x%04x;\n", i, gbeStruct4k.reservedWords24to2Fh[i]); + } + fprintf(fp, "\n"); + /* Words 30h to 3Eh (PXE Software Region) */ + fprintf(fp, " /* Words 30h to 3Eh (PXE Software Region) */\n"); + fprintf(fp, " /* Boot Agent Main Setup Options (Word 30h) */\n"); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.protocolSelect = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.protocolSelect); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved1 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved1); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.defaultBootSelection = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.defaultBootSelection); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved2 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved2); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.promptTime = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.promptTime); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.displaySetupMessage = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.displaySetupMessage); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved3 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved3); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.forceSpeed = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.forceSpeed); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.forceFullDuplex = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.forceFullDuplex); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved4 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved4); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.efiPresence = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.efiPresence); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.pxePresence = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.pxePresence); + fprintf(fp, " /* Boot Agent Configuration Customization Options (Word 31h) */\n"); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableSetupMenu = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableSetupMenu); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableTitleMessage = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableTitleMessage); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableProtocolSelect = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableProtocolSelect); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableBootSelection = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableBootSelection); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableLegacyWakeupSupport = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableLegacyWakeupSupport); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableFlashUpdate = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableFlashUpdate); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.reserved1 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.reserved1); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.ibaBootOrderSetupMode = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.ibaBootOrderSetupMode); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.reserved2 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.reserved2); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.signature = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.signature); + fprintf(fp, " /* Boot Agent Configuration Customization Options (Word 32h) */\n"); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.buildNumber = 0x%02x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.buildNumber); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.minorVersionNumber = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.minorVersionNumber); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.majorVersionNumber = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.majorVersionNumber); + fprintf(fp, " /* IBA Capabilities (Word 33h) */\n"); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.baseCodePresent = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.baseCodePresent); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.undiCapabilityPresent = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.undiCapabilityPresent); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved1 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved1); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.efiUndiCapabilityPresent = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.efiUndiCapabilityPresent); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved2_0 = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved2_0); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved2_1 = 0x%02x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved2_1); + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.signature = 0x%01x;\n", gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.signature); + fprintf(fp, " /* Padding (Words 34h to 3Eh) */\n"); + for (i = 0; i < 11; i++) { + fprintf(fp, " gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[%d] = 0x%04x;\n", i, gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[i]); + } + fprintf(fp, "\n"); + /* Word 3Fh (Checksum) */ + fprintf(fp, " /* Word 3Fh (Checksum) */\n"); + fprintf(fp, " gbeStruct4k.checkSum = 0x%04x;\n", gbeStruct4k.checkSum); + fprintf(fp, "\n"); + /* The rest of Gbe is just padding */ + paddingSize = sizeof(gbeStruct4k.padding); + paddingIdentical = 1; /* Assume that it's all 0xFF, then try to disprove it */ + for (i = 0; i < paddingSize; i++) { /* check whether contents differ */ + if (gbeStruct4k.padding[i] != 0xFF) { + paddingIdentical = 0; + break; + } + } + if (!paddingIdentical) { + fprintf(fp, " /* The rest of Gbe (word 40h or byte 80h onwards) is just padding */\n"); + for (i = 0; i < paddingSize; i++) { /* contents are not all 0xFF, just spit them all out one by one */ + fprintf(fp, " gbeStruct4k.padding[%d] = 0x%02x;\n", i, gbeStruct4k.padding[i]); + } + } else { /* contents are all 0xFF. Generate a small for loop that sets them all to 0xFF */ + fprintf(fp, " /* The rest of Gbe (word 40h or byte 80h onwards) is just padding (0xFF) */\n"); + fprintf(fp, " for (i = 0; i < %d; i++) {\n", paddingSize); + fprintf(fp, " gbeStruct4k.padding[i] = 0xFF;\n"); + fprintf(fp, " }\n"); + } + fprintf(fp, "\n"); + fprintf(fp, " return gbeStruct4k;\n"); + fprintf(fp, "}\n\n"); + + fprintf(fp, "struct GBEREGIONRECORD_8K generatedGbeStruct8k()\n"); + fprintf(fp, "{\n"); + fprintf(fp, " struct GBEREGIONRECORD_8K gbeStruct8k;\n"); + fprintf(fp, " gbeStruct8k.main = generatedGbeStruct4k();\n"); + fprintf(fp, " memcpy(&gbeStruct8k.backup, &gbeStruct8k.main, GBEREGIONSIZE_4K);\n"); + fprintf(fp, " return gbeStruct8k;\n"); + fprintf(fp, "}\n\n"); + + /* ------------------------------ */ + + fclose(fp); /* Always close the file when done. */ + + return 0; +} + +/* + * --------------------------------------------------------------------- + * Debugging functions: + * --------------------------------------------------------------------- + */ + +/* + * show debugging info: show calculated (correct) gbe checksum and what + * is actually stored, in a 4K gbe struct. Only for a single region. + */ +void printGbeChecksumDataFromStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* romName, char* regionName) +{ + printf( + "%s Gbe (%s): calculated Gbe checksum: 0x%hx and actual GBe checksum: 0x%hx\n", + romName, + regionName, + gbeGetChecksumFrom4kStruct(gbeStruct4k, GBECHECKSUMTOTAL), + gbeStruct4k.checkSum + ); + + return; +} + +/* + * show debugging info: show calculated (correct) gbe checksum and what + * is actually stored, in a 8K gbe struct. Do so for main and backup regions. + */ +void printGbeChecksumDataFromStruct8k(struct GBEREGIONRECORD_8K gbeStruct8k, char* romName) +{ + printGbeChecksumDataFromStruct4k(gbeStruct8k.main, romName, "main"); + printGbeChecksumDataFromStruct4k(gbeStruct8k.backup, romName, "backup"); + + return; +} diff --git a/projects/ich9gen/sources/src/gbe/gbe.h b/projects/ich9gen/sources/src/gbe/gbe.h new file mode 100644 index 00000000..a1350fdd --- /dev/null +++ b/projects/ich9gen/sources/src/gbe/gbe.h @@ -0,0 +1,435 @@ +/* + * gbe/gbe.h + * This file is part of the ich9deblob utility from the libreboot project + * + * Copyright (C) 2014 Steve Shenton + * Leah Rowe + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* + * Purpose: provide struct representing gbe region. + * Map actual buffers of this regions, directly to instances of these + * structs. This makes working with gbe really easy. + */ + +/* + * bit fields used, corresponding to datasheet. See links to datasheets + * and documentation in ich9deblob.c + */ + + /* + * See docs/hardware/x200_remove_me.html for info plus links to datasheet (also linked below) + * + * Info about Gbe region (read whole datasheet): + * http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf + * https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums + */ + +#ifndef GBESTRUCT_H +#define GBESTRUCT_H + +#include +#include +#include +#include "../descriptor/descriptor.h" + +/* Size of the full gbe region in bytes */ +#define GBEREGIONSIZE_8K 0x2000 +/* + * Size of each sub-region in gbe. + * gbe contains two regions which + * can be identical: main and backup. + * These are each half the size of the full region + */ +#define GBEREGIONSIZE_4K 0x1000 + +/* + * When adding up the first 0x3F 16-bit words + * in a 4KiB GBE region, it should be equal + * to 0xBABA + */ +#define GBECHECKSUMTOTAL 0xBABA + +/* + * These will have a modified descriptor+gbe based on what's in the factory.rom + * These will be joined into a single 12KiB buffer (descriptor, then gbe) and saved to a file + * NOTE: The GBE region of 8K is actually 2x 4K regions in a single region; both 4K blocks can be identical (and by default, are) + * The 2nd one is a "backup", but we don't know when it's used. perhaps it's used when the checksum on the first one does not match? + */ + +/* + * --------------------------------------------------------------------- + * Gbe struct representing the data: + * --------------------------------------------------------------------- + */ + +struct GBE_RESERVED_WORD_03H { + /* least significant bits */ + uint8_t reserved1_0 : 8; /* bits should all be set to zero */ + uint8_t reserved1_1 : 3; /* ^ part of above. Separated so that the bitfields align */ + uint8_t ibaLom : 1; /* set to 1 for intel boot agent to work (i.e. set it to 0) */ + uint8_t reserved2 : 4; /* bits should all be set to zero */ + /* most significant bits */ +}; + +/* Word 0A */ +struct GBE_PCI_INITIALIZATION_CONTROL_WORD { + /* least significant bits */ + uint8_t loadVendorDeviceId : 1; /* 1 = load from NVM. 0 = load from MAC fuses. It's 1 in my deblobbed_descriptor.bin */ + uint8_t loadSubsystemId : 1; /* 1 = load from NVM. 0 = load from MAC fuses. It's 1 in my deblobbed_descriptor.bin */ + uint8_t reserved1 : 1; /* Reserved. Set to 0 (according to datasheet). 0 in my deblobbed_descriptor.bin */ + uint8_t reserved2 : 3; /* Reserved. Set them to 0 (according to datasheet). 0 in my deblobbed_descriptor.bin */ + uint8_t pmEnable : 1; /* Power Management Enable. 1=Enable. It's 1 in my deblobbed_descriptor.bin */ + uint8_t auxPwr : 1; /* Auxiliary Power Indication. See datasheet. it's 1 in my deblobbed_descriptor.bin */ + uint8_t reserved3 : 4; /* Reserved. Set to 0000 (according to datasheet). */ + uint8_t reserved4 : 4; /* Reserved. Set to 0001 (according to datasheet). */ + /* most significant bits */ +}; + +/* Word 10h. */ +struct GBE_LAN_POWER_CONSUMPTION { + /* least significant bits */ + uint8_t lanD3Power : 5; /* It's 00001b (0x1) in deblobbed_descriptor.bin */ + uint8_t reserved : 3; /* Reserved. These bits should all be 0. confirmed from deblobbed_descriptor.bin */ + uint8_t lanD0Power : 8; /* default value: 0x0D (according to datasheet). confirmed from deblobbed_descriptor.bin */ + /* most significant bits */ +}; + +/* Word 13h */ +struct GBE_SHARED_INITIALIZATION_CONTROL_WORD { + /* least significant bits */ + uint8_t reserved1 : 3; /* Reserved. These bits should be set to 101 (0x5) in binary (according to datasheet and deblobbed_descriptor.bin) */ + uint8_t forceDuplex : 1; /* Hardware default is 0 according to datasheet and deblobbed_descriptor.bin. Presumably to set whether the chipset is to operate at full- or half-duplex */ + uint8_t forceSpeedEnable : 1; /* Hardware default is 0. Presumably to limited speed eg 10, 10/100, 10/100/1000 */ + uint8_t reserved2_0 : 3; /* Reserved. All bits should be set to 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t reserved2_1 : 1; /* ^ part of above. separated so that bitfields align */ + uint8_t phyPowerDownEnable : 1; /* PHY Power Down in D3/Dr (if WoL is disabled), 1 means Enable power down. deblobbed_descriptor.bin says 1 */ + uint8_t reserved3 : 1; /* Reserved. Should be set to 1 according to datasheet and deblobbed_descriptor.bin */ + uint8_t reserved4 : 3; /* Reserved. These bits should all be 0 according to datasheet and deblobbed_descriptor.bin */ + /* ^ reserved4: indicates whether a valid NVM is present. If invalid, MAC does not read NVM and uses default values. */ + /* 00 = invalid NVM, 01 = invalid NVM, 10 = valid NVM present, 11 = invalid NVM */ + /* Default should be 10 (binary) according to datasheet and deblobbed_descriptor.bin */ + uint8_t sign : 2; /* Make sure to set this to 0x2 (10 in binary) */ + /* most significant bits */ +}; + +/* Word 14h */ +struct GBE_EXTENDED_CONFIGURATION_CONTROL_WORD_1 { + /* least significant bits */ + uint16_t extendedConfigurationPointer: 12; /* dword: base address of extended configuration area in NVM. should not be zero. Default is 020h according to datasheet and deblobbed_descriptor.bin */ + uint8_t oemWriteEnable : 1; /* 1=enable. if set, loads oem bits from phy_ctrl register to the 82567. loaded to EXTCNF_CTRL register. default is 1 according to datasheet and deblobbed_descriptor.bin */ + uint8_t reserved1 : 1; /* Reserved. default value 1 according to datasheet and deblobed_descriptor.bin */ + uint8_t reserved2 : 1; /* Reserved. default value 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t reserved3 : 1; /* Reserved. default value 0 according to datasheet and deblobbed_descriptor.bin */ + /* most significant bits */ +}; + +/* Word 15h */ +struct GBE_EXTENDED_CONFIGURATION_CONTROL_WORD_2 { + /* least significant bits */ + uint8_t reserved : 8; /* Reserved. Should be 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t extendedPhyLength : 8; /* dword: size of extended phy configuration area. most be 0 if phy config area is disabled. default is 0000101 (binary) or 05 (hex) according to datasheet, but 00001010 (0A) according to deblobbed_descriptor.bin. Is 0000101 (in the datasheet) a typo that actually means 00001010? */ + /* most significant bits */ +}; + +/* + * Word 17h: LED 1 Configuration and Power Management + * + * Default values for LEDCTL register fields controlling LED1 (LINK_1000) + * output behaviours and OEM fields that define PHY power management + * parameters loaded to the PHY_CTRL register. + */ +struct LED_CTL_1 { + /* least significant bits */ + + /* See page 16 in the datasheet to show the different modes. deblobbed_descriptor.bin has "ACTIVITY" mode set */ + uint8_t led1Mode : 4; /* Default value 0111 (bin) 7 (hex) says datasheet. 1011 (bin) B (hex) according to deblobbed_descriptor.bin */ + + uint8_t reserved1 : 1; /* Reserved. Should be 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led1BlinkMode : 1; /* 0 = slow blink, 1 = fast blink. should be identical to led0 blink mode. Default is 0 according to datasheet and deblobbed_descriptor.bin */ + /* By setting this and led0 blink mode (see word 18h) to 1, you could enable a faster blinking on the LED's where the ethernet cable goes + * on the gigabit ethernet port. Not really useful. Slow blink is fine, and probably better (the LED will probably last longer) */ + + uint8_t led1Invert : 1; /* initial value of LED1_IVRT field. 0 = led1 has active low output, 1 is high active output. Default is 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led1Blink : 1; /* 1 = led1 blinks, 0 = it does not. default 0 according to datasheet, but it's 1 in deblobbed_descriptor.bin */ + uint8_t reserved2 : 1; /* Reserved. should be 1 according to datasheet and deblobbed_descriptor.bin */ + uint8_t lpluEnable : 1; /* Low Power Link Up. Enable links at lowest supported speed by both link partners in all power states. 1=enabled(all power states), 0=disabled. Default is 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t lpluEnableNonD0a : 1; /* Low Power Link up (non-D0a states). Same as above but only for non-D0a states. default is 1 according to and deblobbed_descriptor.bin */ + uint8_t gbeDisableNonD0a : 1; /* If set to 1, disable gigabit speeds in non-D0a power states. Must be 1 (according to datasheet) because GbE is not supported in Sx mode. It's also set to 1 in deblobbed_descriptor.bin */ + uint8_t reserved3 : 2; /* Reserved. Datasheet says both bits should be 0 (confirmed in deblobbed_descriptor.bin) */ + uint8_t gbeDisable : 1; /* When 1, gigabit speeds are disabled in all power states including D0a. Default is 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t reserved4 : 1; /* Reserved. Should be 1, according to datasheet and deblobbed_descriptor.bin */ + /* most significant bits */ +}; + +/* + * Word 18: LED 0 and 2 Configuration Defaults + * + * Hardware defaults for LEDCTL register fields controlling LED0 (LINK/ACTIVITY) + * and LED2 (LINK_100) output behaviours. + */ +struct LED_CTL_02 { + /* least significant bits */ + + /* see page 16 in datasheet to show the different modes. deblobbed_descriptor has "LINK-UP" mode set */ + uint8_t led0Mode : 4; /* default value 0100 (bin) or 4 (hex) according to datasheet. It's 0010 (bin) or 2 (hex) according to deblobbed_descriptor.bin */ + + uint8_t reserved1 : 1; /* Reserved. Should be set to 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led0BlinkMode : 1; /* This should be the same as led1BlinkMode (see word 17h). Default is 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led0Invert : 1; /* initial value of LED0_IVRT field. 0 = led0 has active low output, 1 is high active output. Default is 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led0Blink : 1; /* LED0_BLINK field. Should be 0 according to datasheet and deblobbed_descriptor.bin */ + + /* see page 16 in datasheet to shew the different modes. deblobbed_descriptor has "LINK_100" mode set */ + uint8_t led2Mode : 4; /* default value 0110 (bin) or 6 (hex) according to datasheet and deblobbed_descriptor.bin */ + + uint8_t reserved2 : 1; /* Reserved. Should be 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led2BlinkMode : 1; /* 0 = slow blink. 1 = fast. default 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led2Invert : 1; /* LED2_IVRT field. Should be 0 according to datasheet and deblobbed_descriptor.bin */ + uint8_t led2Blink : 1; /* LED2_BLINK field. should be 0 according to datasheet and deblobbed_descriptor.bin */ + /* most significant bits */ +}; + +/* Word 30h */ +struct GBE_PXE_BOOT_AGENT_MAIN_SETUP_OPTIONS { + /* least significant bits */ + uint8_t protocolSelect : 2; /* Default 00 binary (PXE) according to datasheet. 01 is reserved. 10/11 are undefined. deblobbed_descriptor.bin says 00 */ + uint8_t reserved1 : 1; /* Reserved. deblobbed_descriptor.bin says 0 */ + uint8_t defaultBootSelection : 2; /* deblobbed_descriptor.bin says 00 (binary). 00 is network boot, then local. 01 is local boot, then network. 10 is network boot only. 11 is local boot only */ + uint8_t reserved2 : 1; /* Reserved. deblobbed_descriptor.bin says 0. */ + uint8_t promptTime : 2; /* deblobbed_descriptor.bin says 00. delay for how long "press ctrl-s" setup prompt message appears. 00 = 2 secs, 01 is 3 secs, 10 is 5 secs, 11 is 0 secs. */ + uint8_t displaySetupMessage : 1; /* default 1 says datasheet. deblobbed_descriptor.bin says 1. if 1, "ctrl-s" setup prompt message appears after the title message. */ + uint8_t reserved3 : 1; /* Datasheet says to set 0. deblobbed_descriptor.bin says 0. */ + uint8_t forceSpeed : 2; /* deblobbed_descriptor.bin says 00. 00 = auto-negotiate, 01 = 10Mbps, 10 = 100Mbps, 11 = "not allowed" */ + uint8_t forceFullDuplex : 1; /* deblobbed_descriptor.bin says 0. Only relevant when bits 10/11 are set; if so, then: 0 = half duplex, 1 = full duplex */ + uint8_t reserved4 : 1; /* Reserved. deblobbed_descriptor.bin says 0. datasheet recommends 0. */ + uint8_t efiPresence : 1; /* 1 means that an EFI image is present (0 means not present). deblobbed_descriptor.bin says 0. if 1, eeprom word 33h (efi version) becomes valid. if pxePresent is 1, that means EFI and PXE are both present.*/ + uint8_t pxePresence : 1; /* 0 means that a PXE image is present. 1 means to pxe present. deblobbed_descriptor.bin says 0. if 0, then word 32h (PXE version) in eeprom becomes valid */ + /* most significant bits */ + + /* This whole data structure is pointless, since libreboot doesn't (read: won't) + * include the proprietary intel boot agent. Struct exists here simply for documentations sake. */ +}; +/* Word 31h */ +struct GBE_PXE_BOOT_AGENT_CONFIGURATION_CUSTOMIZATION_OPTIONS_31H { + /* least significant bits */ + uint8_t disableSetupMenu : 1; /* 1 means invoking setup menu with ctrl-s won't work. deblobbed_descriptor.bin says 0 (as is default, per datasheet) */ + uint8_t disableTitleMessage : 1; /* 1 means that title in boot agent screen is suppressed, as is ctrl-s message. default is 0, and deblobbed_descriptor.bin says 0 */ + uint8_t disableProtocolSelect : 1; /* 1 means no changes to boot protocol are allowed. default is 0, and deblobbed_descriptor.bin says 0 */ + uint8_t disableBootSelection : 1; /* 1 means no changes in boot order option menu are allowed. default is 0, and deblobbed_descriptor.bin says 0 */ + uint8_t disableLegacyWakeupSupport : 1; /* 1 means no changes in legacy wakeup support menu is allowed. default is 0, and deblobbed_descriptor.bin says 0 */ + uint8_t disableFlashUpdate : 1; /* 1 means no changes to flash image using PROset is allowed. default is 0, and deblobbed_descriptor.bin says 0 */ + uint8_t reserved1 : 2; /* Reserved. Datasheet says these must be 0, and deblobbed_descriptor.bin sets them to 0. */ + + /* + * deblobbed_descriptor says 000 + * 000 = normal behaviour + * see datasheet (page 21) for other modes. + */ + uint8_t ibaBootOrderSetupMode : 3; + + uint8_t reserved2 : 3; /* Reserved. Datasheet says these must be set to 0, and deblobbed_descriptor.bin sets them to 0. */ + uint8_t signature : 2; /* Must be set to 01 to indicate that this whole word has been configured by the agent or other software. deblobbed_descriptor.bin says 01. */ + /* most significant bits */ + + /* This whole data structure is pointless, since libreboot doesn't (read: won't) + * include the proprietary intel boot agent. Struct exists here simply for documentations sake. */ +}; +/* Word 32h */ +struct GBE_PXE_BOOT_AGENT_CONFIGURATION_CUSTOMIZATION_OPTIONS_32H { + /* least significant bits */ + uint8_t buildNumber : 8; /* PXE boot agent build number. default is 28 (hex). deblobbed_descriptor.bin says 18 (hex) */ + uint8_t minorVersionNumber : 4; /* PXE boot agent minor number. default is 2 (hex). deblobbed_descriptor.bin says 3 (hex) */ + uint8_t majorVersionNumber : 4; /* PXE boot agent major number. default is F (hex). deblobbed_descriptor.bin says 1 (hex) */ + /* most significant bits */ + + /* This whole data structure is pointless, since libreboot doesn't (read: won't) + * include the proprietary intel boot agent. Struct exists here simply for documentations sake. */ +}; +/* Word 33h */ +struct GBE_PXE_IBA_CAPABILITIES { + /* least significant bits */ + uint8_t baseCodePresent : 1; /* 0 means PXE base code is indicated as being present. 1 (default) means not. deblobbed_descriptor.bin says 1 */ + uint8_t undiCapabilityPresent : 1; /* 1 (default) means pxe/undi capability is indicated present. 0 means not present. deblobbed_descriptor.bin says 1 */ + uint8_t reserved1 : 1; /* Reserved. Must be 1. deblobbed_descriptor.bin says 1 */ + uint8_t efiUndiCapabilityPresent : 1; /* EFI UNDI capability present: 0 (default) means not present. 1 means present. deblobbed_descriptor.bin says 0 */ + uint8_t reserved2_0 : 4; /* reserved. all bits must be 0. deblobbed_descriptor.bin sets them to 0. */ + uint8_t reserved2_1 : 6; /* ^ part of reserved2_0. split this way so that the bitfields align */ + uint8_t signature : 2; /* must be 01 to indicate that the word is configured by the agent or other software. deblobbed_descriptor.bin says 01 */ + /* most significant bits */ + + /* This whole data structure is pointless, since libreboot doesn't (read: won't) + * include the proprietary intel boot agent. Struct exists here simply for documentations sake. */ +}; +/* Words 30h to 3Eh */ +struct GBE_PXE_SOFTWARE_REGION { + struct GBE_PXE_BOOT_AGENT_MAIN_SETUP_OPTIONS bootAgentMainSetupOptions; /* Word 30h */ + struct GBE_PXE_BOOT_AGENT_CONFIGURATION_CUSTOMIZATION_OPTIONS_31H bootAgentConfigurationCustomizationOptions31h; /* Word 31h */ + struct GBE_PXE_BOOT_AGENT_CONFIGURATION_CUSTOMIZATION_OPTIONS_32H bootAgentConfigurationCustomizationOptions32h; /* Word 32h */ + struct GBE_PXE_IBA_CAPABILITIES ibaCapabilities; /* Word 33h */ + + /* Words 34h to 3Eh (padding). Set these to 0xFFFF (according to deblobbed_descriptor.bin) */ + uint16_t paddingWords34hTo3Eh[11]; + + /* + * the pxe software region is practically useless in libreboot, since + * libreboot does not include the intel boot agent (it's proprietary software). + * + * Having this struct in place is simply for documentations sake. It is completely + * irrelevant what you put here. filling it with 0xFFFF would probably be fine. + */ +}; + +struct GBEREGIONRECORD_4K { + uint8_t macAddress[6]; /* Word 00 to 02 */ + struct GBE_RESERVED_WORD_03H reservedWord03h; /* Reserved word 03. */ + uint16_t reservedWord04h; /* Reserved word 04: set it to 0xFFFF (according to datasheet and deblobbed_descriptor.bin) */ + uint16_t imageVersionInformation; /* Reserved word 05: 83 10 (little endian) in my deblobbed_descriptor.bin. Set this to 0x1083 (in C, assuming little endian byte order). "cannot be changed" according to datasheet */ + uint16_t reservedWords06h07h[2]; /* Reserved words 06-07: set both to 0xFFFF (according to datasheet and deblobbed_descriptor.bin) */ + + /* + * Word 08 and 09 (pba low and pba high): + * + * Both of these should be set to 0xFFFF by default, according to the datasheet. + * "nine digit printed board assembly (PBA) number" for intel cards to be stored + * in a 4 byte (read: 2 word) field. + * + * Example: if pba number is 123456-003, then word 08 should be 1234h and word 09 becomes 5603. + * Note: 1234 and 5603 above are big endian. In the image it would actually be 34 12 and 0356 + * + * Example: in mine it was (in the image): 08 10 FF FF. That becomes 1008h and FFFFh, or + * basically: 1008FF-0FF. The same was observed in another. + * + * Setting it to FF FF FF FF should be fine, according to the datasheet. + */ + uint16_t pbaLow; /* Word 08. Set it to 0x1008 (according to deblobbed_descriptor.bin). */ + uint16_t pbaHigh; /* Word 09. Set it to 0xFFFF (according to deblobbed_descriptor.bin). */ + + /* Word 0A */ + struct GBE_PCI_INITIALIZATION_CONTROL_WORD pciInitializationControlWord; + + /* + * Word 0B; subsystem ID + * + * If load subsystem ID bit of word 0A (pci init control word) is + * set to 1 (read: it is. in my deblobbed_descriptor.bin), store + * the subsystem id here. Datasheet says that the default value is + * 0000h, but you should set this to 20EEh (little endian: EE 20) + */ + uint16_t subsystemId; /* Set this to 0x20EE */ + + /* + * Word 0C; subsystem vendor ID + * + * If load subsystem vendor ID bit of word 0A (pci init control word) + * is set to 1 (read: it is. in my deblobbed_descriptor.bin), store + * the subsystem vendor id here. Datasheet says that the default + * value is 8086h, but you should set this to 17AAh (lendian: AA 17). + */ + uint16_t subsystemVendorId; /* Set this to 0x17AA */ + + /* + * Word 0D: device ID + * + * If load vendor/device ID in word 0A (pci init control word) is 1 + * (it is) then this word is used to init device id using word 21h, + * 1Eh or 1Fh. In my case, deviceId is 0x10F5. Word 21h is set to + * 0x10CB, word 1Eh is 0x10F5 and 1Fh is 0x10BF + * + * The datasheet says that 10F5 is for Intel 82567LM gigabit ethernet + * controller; 10BF is for Intel 82567LF and 10CB is for Intel 82567V. + * + * Based on this, the X200 is shown to have the Intel 82567LM ethernet + * controller. + */ + uint16_t deviceId; /* Set this to 0x10F5. */ + /* It is important that this is correct, for the linux kernel driver */ + + /* + * Word 0E: vendor ID + * + * If load vendor/device ID in word 0A (pci init control) is 1 (it is), + * then this word used read to initialize the PCI vendor ID. Default + * value is 8086 according to datasheets, and deblobbed_descriptor.bin. + * + * Intel is often 8086 as a PCI vendor ID. Because 8086. As in the CPU architecture. + */ + uint16_t vendorId; + + uint16_t deviceRevId; /* Word 0F: reserved bits. Set all bits to 0. */ + struct GBE_LAN_POWER_CONSUMPTION lanPowerConsumption; /* Word 10: LAN Power Consumption (see struct definition) */ + uint16_t reservedWords11h12h[2]; /* Words 11-12: Reserved. Set both of them to 0x0000 (according to datasheet). */ + + /* Word 13: Shared Initialization Control Word */ + struct GBE_SHARED_INITIALIZATION_CONTROL_WORD sharedInitializationControlWord; + + /* Word 14: Extended Configuration Control Word 1 */ + struct GBE_EXTENDED_CONFIGURATION_CONTROL_WORD_1 extendedConfigurationControlWord1; + + /* Word 15: Extended Configuration Control Word 2 */ + struct GBE_EXTENDED_CONFIGURATION_CONTROL_WORD_2 extendedConfigurationControlWord2; + + /* Word 16: Extended Configuration Control Word 3 */ + /* All bits reserved. Datasheet and deblobbed_descriptor.bin say to set it to zero */ + uint16_t extendedConfigurationControlWord3; + + struct LED_CTL_1 ledCtl1; /* Word 17: LED 1 Configuration and Power Management */ + struct LED_CTL_02 ledCtl02; /* Word 18: LED 0 and 2 Configuration Defaults */ + uint16_t reservedWord19h; /* Word 19: Reserved. Default is 0x2B00 according to datasheet, but in deblobbed_descriptor.bin it is 0x2B40 */ + uint16_t reservedWord1Ah; /* Word 1A: Reserved. Default is 0x0043 according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWord1Bh; /* Word 1B: Reserved. Should be 0x0000 according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWord1Ch; /* Word 1C: Reserved. Should be 0x10F5 according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWord1Dh; /* Word 1D: Reserved. Should be 0xBAAD according to datasheet and deblobbed_descriptor.bin */ + uint16_t _82567lmDeviceId; /* Word 1E: Device ID for Intel 82567LM gigabit ethernet controller (note: X200 uses this). Should be 0x10F5 according to datasheet and deblobbed_descriptor.bin*/ + uint16_t _82567lfDeviceId; /* Word 1F: Device ID for Intel 82567LF gigabit ethernet controller. Should be 0x10BF according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWord20h; /* Word 20: Reserved. Should be 0xBAAD according to datasheet and deblobbed_descriptor.bin */ + uint16_t _82567vDeviceId; /* Word 21: Device ID for Intel 82567V gigabit ethernet controller. Should be 0x10CB according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWord22h; /* Word 22: Reserved. Should be 0xBAAD according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWord23h; /* Word 23: Reserved. Should be 0xBAAD according to datasheet and deblobbed_descriptor.bin */ + uint16_t reservedWords24to2Fh[12]; /* Words 24-2F: Reserved. These should all be 0x0000 according to datasheet and deblobbed_descriptor.bin */ + struct GBE_PXE_SOFTWARE_REGION pxeSoftwareRegion; /* Words 30-3E: PXE Software Region */ + uint16_t checkSum; /* when added to the sum of all words above, this should match GBECHECKSUMTOTAL */ + + /* set all bytes in here to 0xFF */ + uint8_t padding[3968]; +}; + +/* main and backup region in gbe */ +struct GBEREGIONRECORD_8K { + struct GBEREGIONRECORD_4K main; + struct GBEREGIONRECORD_4K backup; + /* + * Backup region: + * This is actually "main" on X200, since the real main has a bad checksum + * and other errors. You should do what you need on this one (if modifying + * lenovobios's gbe region) and then copy to main + */ +}; + +/* + * --------------------------------------------------------------------- + * Function declarations (keep gcc/make happy. check them in gbe.c) + * --------------------------------------------------------------------- + */ + +uint16_t gbeGetChecksumFrom4kBuffer(uint16_t* gbeWord, uint16_t desiredValue, int gbeRegionBase); +uint16_t gbeGetChecksumFrom4kStruct(struct GBEREGIONRECORD_4K gbeStruct4k, uint16_t desiredValue); +struct GBEREGIONRECORD_8K deblobbedGbeStructFromFactory(struct GBEREGIONRECORD_8K factoryGbeStruct8k); +int notCreatedHFileForGbeCFile(char* outFileName, char* cFileName); +int notCreatedCFileFromGbeStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* outFileName, char* headerFileName); +void printGbeChecksumDataFromStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* romName, char* regionName); +void printGbeChecksumDataFromStruct8k(struct GBEREGIONRECORD_8K gbeStruct8k, char* romName); + +#endif diff --git a/projects/ich9gen/sources/src/ich9deblob.c b/projects/ich9gen/sources/src/ich9deblob.c new file mode 100644 index 00000000..d79a3a89 --- /dev/null +++ b/projects/ich9gen/sources/src/ich9deblob.c @@ -0,0 +1,221 @@ +/* + * ich9deblob.c + * This file is part of the ich9deblob utility from the libreboot project + * + * Purpose: disable and remove the ME from ich9m/gm45 systems in coreboot. + * + * Copyright (C) 2014 Steve Shenton + * Copyright (C) 2014,2015 Leah Rowe + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Initially based on proof of concept by Steve Shenton. */ +/* Original utility can be found at https://gitorious.org/ich9descriptortool */ + +/* + * Read a factory.rom dump (ich9m/gm45 systems) and + * modify the flash descriptor to remove all regions except descriptor, + * Gbe and BIOS. Set BIOS region to full size of the ROM image (after + * the flash descriptor and gbe). Basically, deblob the descriptor. + * + * This will will generate a concatenated descriptor+gbe dump suitable + * for use in libreboot. Currently tested: ThinkPad X200 (coreboot/libreboot) + */ + +/* + * See docs/hardware/x200_remove_me.html for info plus links to datasheet (also linked below) + * + * Info about flash descriptor (read page 845 onwards): + * http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datasheet.pdf + * + * Info about Gbe region (read whole datasheet): + * http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf + * https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums + */ + +#include "ich9deblob.h" + +int main() +{ + struct DESCRIPTORREGIONRECORD descriptorStruct; + uint8_t* descriptorBuffer = (uint8_t*)&descriptorStruct; + + struct GBEREGIONRECORD_8K gbeStruct8k; + uint8_t* gbeBuffer8k = (uint8_t*)&gbeStruct8k; + uint32_t gbeRegionStart; + + char* romFilename = "factory.rom"; + char* descriptorGbeFilename = "deblobbed_descriptor.bin"; + char* descriptorNoGbeFilename = "deblobbed_4kdescriptor.bin"; + + unsigned int bufferLength; + unsigned int romSize; + + /* + * ------------------------------------------------------------------ + * Compatibility checks. This version of ich9deblob is not yet portable. + * ------------------------------------------------------------------ + */ + + if (systemOrCompilerIncompatible(descriptorStruct, gbeStruct8k)) return 1; + /* If true, fail with error message */ + + /* + * ------------------------------------------------------------------ + * Extract the descriptor and gbe regions from the factory.rom dump + * ------------------------------------------------------------------ + */ + FILE* fp = NULL; + fp = fopen(romFilename, "rb"); /* open factory.rom */ + if (NULL == fp) + { + printf("\nerror: could not open %s\n", romFilename); + fclose(fp); + return 1; + } + printf("\n%s opened successfully\n", romFilename); + + /* + * Get the descriptor region dump from the factory.rom + * (goes in factoryDescriptorBuffer variable) + */ + bufferLength = fread(descriptorBuffer, 1, DESCRIPTORREGIONSIZE, fp); + if (DESCRIPTORREGIONSIZE != bufferLength) // + { + printf("\nerror: could not read descriptor from %s (%i) bytes read\n", romFilename, bufferLength); + fclose(fp); + return 1; + } + printf("\ndescriptor region read successfully\n"); + + if (descriptorDefinesGbeRegion(descriptorStruct)) + { + gbeRegionStart = descriptorStruct.regionSection.flReg3.BASE << FLREGIONBITSHIFT; + + /* + * Set offset so that we can read the data from + * the gbe region + */ + fseek(fp, gbeRegionStart, SEEK_SET); + /* Read the gbe data from the factory.rom and put it in factoryGbeBuffer8k */ + bufferLength = fread(gbeBuffer8k, 1, GBEREGIONSIZE_8K, fp); + if (GBEREGIONSIZE_8K != bufferLength) + { + printf("\nerror: could not read GBe region from %s (%i) bytes read\n", romFilename, bufferLength); + fclose(fp); + return 1; + } + printf("\ngbe (8KiB) region read successfully\n"); + } + + fseek(fp, 0L, SEEK_END); + romSize = ftell(fp); + printf("\n%s size: [%i] bytes\n", romFilename, romSize); + + fclose(fp); + + /* Debugging (before modification) */ + printDescriptorRegionLocations(descriptorStruct, "Original"); + if (descriptorDefinesGbeRegion(descriptorStruct)) + printGbeChecksumDataFromStruct8k(gbeStruct8k, "Original"); + else printf("NO GBE REGION\n"); + + /* + * ------------------------------------------------------------------ + * Modify the descriptor and gbe regions, ready to go in libreboot.rom + * ------------------------------------------------------------------ + */ + + /* Delete the ME/Platform regions, place Gbe after the descriptor, resize BIOS region to fill the gap */ + descriptorStruct = librebootDescriptorStructFromFactory(descriptorStruct, romSize); + + /* The ME is disallowed read-write access to all regions + * (this is probably redundant, since the ME firmware is already removed from libreboot) */ + descriptorStruct = descriptorMeRegionsForbidden(descriptorStruct); + /* Host/CPU is allowed to read/write all regions. + * This makes flashrom -p internal work */ + descriptorStruct = descriptorHostRegionsUnlocked(descriptorStruct); + + /* Set OEM string */ + descriptorStruct = descriptorOemString(descriptorStruct); + + /* Modify the Gbe region (see function for details) */ + if (descriptorDefinesGbeRegion(descriptorStruct)) + gbeStruct8k = deblobbedGbeStructFromFactory(gbeStruct8k); + + /* Debugging (after modifying the descriptor and gbe regions) */ + printDescriptorRegionLocations(descriptorStruct, "Modified"); + if (descriptorDefinesGbeRegion(descriptorStruct)) + printGbeChecksumDataFromStruct8k(gbeStruct8k, "Modified"); + else printf("NO GBE REGION\n"); + + /* + * ------------------------------------------------------------------ + * Create the file with the modified descriptor and gbe inside + * ------------------------------------------------------------------ + */ + printf("\n"); + if (descriptorDefinesGbeRegion(descriptorStruct)) + { + if (notCreatedDescriptorGbeFile(descriptorStruct, gbeStruct8k, descriptorGbeFilename)) { + return 1; + } + } + else + { + if (notCreated4kDescriptorFile(descriptorStruct, descriptorNoGbeFilename)) { + return 1; + } + } + + /* + * ------------------------------------------------------------------ + * Generate ich9gen data (C code that will recreate the deblobbed descriptor+gbe from scratch) + * ------------------------------------------------------------------ + */ + /* Code for generating the Descriptor struct */ + /* mkdescriptor.h */ + if (notCreatedHFileForDescriptorCFile("mkdescriptor.h", "mkdescriptor.c")) { + return 1; + } /* and now mkdescriptor.c */ + if (notCreatedCFileFromDescriptorStruct(descriptorStruct, "mkdescriptor.c", "mkdescriptor.h")) { + return 1; + } + + if (descriptorDefinesGbeRegion(descriptorStruct)) + { + /* Code for generating the Gbe struct */ + /* mkgbe.h */ + if (notCreatedHFileForGbeCFile("mkgbe.h", "mkgbe.c")) { + return 1; + } /* and now mkgbe.c */ + if (notCreatedCFileFromGbeStruct4k(gbeStruct8k.backup, "mkgbe.c", "mkgbe.h")) { + return 1; + } + } + + if (descriptorDefinesGbeRegion(descriptorStruct)) + { + printf("The modified descriptor and gbe regions have also been dumped as src files: mkdescriptor.c, mkdescriptor.h, mkgbe.c, mkgbe.h\n"); + printf("To use these in ich9gen, place them in src/ich9gen/ and re-build ich9gen.\n\n"); + } + else + { + printf("The modified descriptor region have also been dumped as src files: mkdescriptor.c, mkdescriptor.h\n"); + printf("To use these in ich9gen, place them in src/ich9gen/ and re-build ich9gen.\n\n"); + } + + return 0; +} diff --git a/projects/ich9gen/sources/src/ich9deblob.h b/projects/ich9gen/sources/src/ich9deblob.h new file mode 100644 index 00000000..c11ea290 --- /dev/null +++ b/projects/ich9gen/sources/src/ich9deblob.h @@ -0,0 +1,38 @@ +/* + * ich9deblob.h + * This file is part of the ich9deblob utility from the libreboot project + * + * Purpose: header file for ich9deblob.c + * + * Copyright (C) 2014 Steve Shenton + * Leah Rowe + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef ICH9DEBLOB_H +#define ICH9DEBLOB_H + +#include +#include +#include + +#include "common/descriptor_gbe.h" /* common descriptor/gbe functions used by ich9deblob */ +#include "common/x86compatibility.h" /* system/compiler compatibility checks. This code is not portable. */ +#include "descriptor/descriptor.h" /* structs describing what's in the descriptor region */ +#include "gbe/gbe.h" /* structs describing what's in the gbe region */ + +int main(); + +#endif diff --git a/projects/ich9gen/sources/src/ich9gen.c b/projects/ich9gen/sources/src/ich9gen.c new file mode 100644 index 00000000..b3a2c9f1 --- /dev/null +++ b/projects/ich9gen/sources/src/ich9gen.c @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2014, 2015 Leah Rowe + * Copyright (C) 2016 Swift Geek + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Generate deblobbed descriptor and gbe 12KiB file from scratch + * without relying on a factory.rom dump */ + +#include "ich9gen.h" + +int main(int argc, char *argv[]) +{ + int i, j; + + struct GBEREGIONRECORD_8K gbeStruct8k = generatedGbeStruct8k(); + struct DESCRIPTORREGIONRECORD descriptorStruct4M = generatedDescriptorStruct(ROMSIZE_4MB, WITHGBE); + struct DESCRIPTORREGIONRECORD descriptorStruct8M = generatedDescriptorStruct(ROMSIZE_8MB, WITHGBE); + struct DESCRIPTORREGIONRECORD descriptorStruct16M = generatedDescriptorStruct(ROMSIZE_16MB, WITHGBE); + struct DESCRIPTORREGIONRECORD descriptorStructNoGbe4M = generatedDescriptorStruct(ROMSIZE_4MB, WITHOUTGBE); + struct DESCRIPTORREGIONRECORD descriptorStructNoGbe8M = generatedDescriptorStruct(ROMSIZE_8MB, WITHOUTGBE); + struct DESCRIPTORREGIONRECORD descriptorStructNoGbe16M = generatedDescriptorStruct(ROMSIZE_16MB, WITHOUTGBE); + + /* Only for the compatibility checks */ + struct DESCRIPTORREGIONRECORD dummyDescriptorStruct; + struct GBEREGIONRECORD_8K dummyGbeStruct8k; + + /* + * ------------------------------------------------------------------ + * Compatibility checks. This version of ich9deblob is not yet portable. + * ------------------------------------------------------------------ + */ + + if (systemOrCompilerIncompatible(dummyDescriptorStruct, dummyGbeStruct8k)) return 1; + /* If true, fail with error message */ + + /* + * ------------------------------------------------------------------ + * Arguments given on the terminal + * ------------------------------------------------------------------ + */ + + + if(argc==3) { + + /* If user provides their own MAC address, it will be used. + * Otherwise, ich9gen will simply use the default one. + * + * However, if the user provides an invalid MAC address, then ich9gen + * will exit. */ + if(0==strcmp(argv[1],"--macaddress")) { + /* 6 hex chars format (example): AA:BB:CC:DD:EE:FF */ + if (strlen(argv[2]) != 17) { + printf("ich9gen: invalid mac address format (wrong length)\n"); + return 1; + } + for(i=2; i<14; i+=3) { + if(argv[2][i]!=':') { + printf("ich9gen: invalid mac address format (non-colon characters used as spacing)\n"); + return 1; + } + } + for(i=0; i<6; i++) { + gbeStruct8k.main.macAddress[i] = 0; + + /* Go through each nibble of the byte */ + for(j=0; j<2; j++) { + if(argv[2][(i*3)+j]>='a' && argv[2][(i*3)+j]<='f') + gbeStruct8k.main.macAddress[i] |= (uint8_t)((argv[2][(i*3)+j] - 87) << ((j^1) << 2)); + else if(argv[2][(i*3)+j]>='A' && argv[2][(i*3)+j]<='F') + gbeStruct8k.main.macAddress[i] |= (uint8_t)((argv[2][(i*3)+j] - 55) << ((j^1) << 2)); + else if(argv[2][(i*3)+j]>='0' && argv[2][(i*3)+j]<='9') + gbeStruct8k.main.macAddress[i] |= (uint8_t)((argv[2][(i*3)+j] - 48) << ((j^1) << 2)); + else { + printf("ich9gen: invalid mac address format (non-hex characters)\n"); + return 1; + } + } + } + + gbeStruct8k.main.checkSum = gbeGetChecksumFrom4kStruct(gbeStruct8k.main, GBECHECKSUMTOTAL); /* Fix the checksum */ + memcpy(&gbeStruct8k.backup, &gbeStruct8k.main, GBEREGIONSIZE_4K); /* Copy to the backup */ + + /* Generate ich9gen data (C code for Gbe region): */ + + /* mkgbe.h */ + if (notCreatedHFileForGbeCFile("mkgbe.h", "mkgbe.c")) { + return 1; + } /* and now mkgbe.c */ + if (notCreatedCFileFromGbeStruct4k(gbeStruct8k.backup, "mkgbe.c", "mkgbe.h")) { + return 1; + } + + printf("You selected to change the MAC address in the Gbe section. This has been done.\n\n"); + + printf("The modified gbe region has also been dumped as src files: mkgbe.c, mkgbe.h\n"); + printf("To use these in ich9gen, place them in src/ich9gen/ and re-build ich9gen.\n\n"); + } + + } + + /* + * ------------------------------------------------------------------ + * Generate the 12KiB files, ready to be used in a libreboot image + * ------------------------------------------------------------------ + */ + + if (notCreatedDescriptorGbeFile(descriptorStruct4M, gbeStruct8k, "ich9fdgbe_4m.bin")) { + return 1; + } + + if (notCreatedDescriptorGbeFile(descriptorStruct8M, gbeStruct8k, "ich9fdgbe_8m.bin")) { + return 1; + } + + if (notCreatedDescriptorGbeFile(descriptorStruct16M, gbeStruct8k, "ich9fdgbe_16m.bin")) { + return 1; + } + /* + * ------------------------------------------------------------------ + * Generate the 4KiB files (descriptors without GbE), ready to be used in a libreboot image + * In these descriptors, the onboard Intel GbE NIC is disabled; a discrete one is used instead + * ------------------------------------------------------------------ + */ + + if (notCreated4kDescriptorFile(descriptorStructNoGbe4M, "ich9fdnogbe_4m.bin")) { + return 1; + } + + if (notCreated4kDescriptorFile(descriptorStructNoGbe8M, "ich9fdnogbe_8m.bin")) { + return 1; + } + + if (notCreated4kDescriptorFile(descriptorStructNoGbe16M, "ich9fdnogbe_16m.bin")) { + return 1; + } + return 0; +} diff --git a/projects/ich9gen/sources/src/ich9gen.h b/projects/ich9gen/sources/src/ich9gen.h new file mode 100644 index 00000000..6b346b06 --- /dev/null +++ b/projects/ich9gen/sources/src/ich9gen.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2014 Leah Rowe + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +/* Header file for ich9gen.c */ + +#ifndef ICH9GEN_H +#define ICH9GEN_H + +#include +#include +#include + +#include "ich9gen/mkdescriptor.h" +#include "ich9gen/mkgbe.h" +#include "common/descriptor_gbe.h" /* common descriptor/gbe functions used by ich9deblob */ +#include "common/x86compatibility.h" /* system/compiler compatibility checks. This code is not portable. */ +#include "descriptor/descriptor.h" /* structs describing what's in the descriptor region */ +#include "gbe/gbe.h" /* structs describing what's in the gbe region */ + +#define WITHGBE 1 +#define WITHOUTGBE 0 + +int main(int argc, char *argv[]); + +#endif diff --git a/projects/ich9gen/sources/src/ich9gen/mkdescriptor.c b/projects/ich9gen/sources/src/ich9gen/mkdescriptor.c new file mode 100644 index 00000000..3b97a97b --- /dev/null +++ b/projects/ich9gen/sources/src/ich9gen/mkdescriptor.c @@ -0,0 +1,229 @@ +/* + * Copyright (C) 2014, 2015 Leah Rowe + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "mkdescriptor.h" + +/* Generate a 4KiB Descriptor struct, with default values. */ +/* Read ../descriptor/descriptor.h for an explanation of the default values used here */ + +struct DESCRIPTORREGIONRECORD generatedDescriptorStruct(unsigned int romSize, int hasGbe) +{ + int i; + struct DESCRIPTORREGIONRECORD descriptorStruct; + + /* Flash Valid Signature Register */ + descriptorStruct.flValSig.signature = 0x0ff0a55a; + + /* Flash Map Registers */ + /* FLMAP0 */ + descriptorStruct.flMaps.flMap0.FCBA = 0x01; + descriptorStruct.flMaps.flMap0.NC = 0x0; + descriptorStruct.flMaps.flMap0.reserved1 = 0x00; + descriptorStruct.flMaps.flMap0.FRBA = 0x04; + descriptorStruct.flMaps.flMap0.NR = hasGbe ? 0x2 : 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.flMaps.flMap0.reserved2 = 0x00; + /* FLMAP1 */ + descriptorStruct.flMaps.flMap1.FMBA = 0x06; + descriptorStruct.flMaps.flMap1.NM = 0x2; + descriptorStruct.flMaps.flMap1.reserved = 0x00; + descriptorStruct.flMaps.flMap1.FISBA = 0x10; + descriptorStruct.flMaps.flMap1.ISL = 0x02; + /* FLMAP2 */ + descriptorStruct.flMaps.flMap2.FMSBA = 0x20; + descriptorStruct.flMaps.flMap2.MSL = 0x01; + descriptorStruct.flMaps.flMap2.reserved = 0x0000; + + /* Component Section Record */ + /* FLCOMP */ + descriptorStruct.componentSection.flcomp.component1Density = componentDensity(romSize); + descriptorStruct.componentSection.flcomp.component2Density = componentDensity(romSize); + descriptorStruct.componentSection.flcomp.reserved1 = 0x0; + descriptorStruct.componentSection.flcomp.reserved2 = 0x00; + descriptorStruct.componentSection.flcomp.reserved3 = 0x0; + descriptorStruct.componentSection.flcomp.readClockFrequency = 0x0; + descriptorStruct.componentSection.flcomp.fastReadSupport = 0x1; + descriptorStruct.componentSection.flcomp.fastreadClockFrequency = 0x1; + descriptorStruct.componentSection.flcomp.writeEraseClockFrequency = 0x0; + descriptorStruct.componentSection.flcomp.readStatusClockFrequency = 0x0; + descriptorStruct.componentSection.flcomp.reserved4 = 0x0; + /* FLILL */ + descriptorStruct.componentSection.flill = 0x00000000; + /* FLPB */ + descriptorStruct.componentSection.flpb = 0x00000000; + /* Padding */ + for (i = 0; i < 36; i++) { + descriptorStruct.componentSection.padding[i] = 0xFF; + } + + /* Flash Descriptor Region Section */ + /* FLREG0 (Descriptor) */ + descriptorStruct.regionSection.flReg0.BASE = 0x0000; + descriptorStruct.regionSection.flReg0.reserved1 = 0x0; + descriptorStruct.regionSection.flReg0.LIMIT = 0x0000; + descriptorStruct.regionSection.flReg0.reserved2 = 0x0; + /* FLREG1 (BIOS) */ + descriptorStruct.regionSection.flReg1.BASE = (DESCRIPTORREGIONSIZE + (hasGbe ? GBEREGIONSIZE_8K : 0)) >> FLREGIONBITSHIFT; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg1.reserved1 = 0x0; + descriptorStruct.regionSection.flReg1.LIMIT = ((romSize >> FLREGIONBITSHIFT) - 1); /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg1.reserved2 = 0x0; + /* FLREG2 (ME) */ + descriptorStruct.regionSection.flReg2.BASE = 0x1fff; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg2.reserved1 = 0x0; + descriptorStruct.regionSection.flReg2.LIMIT = 0x0000; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg2.reserved2 = 0x0; + /* FLREG3 (Gbe) */ + descriptorStruct.regionSection.flReg3.BASE = hasGbe ? (DESCRIPTORREGIONSIZE >> FLREGIONBITSHIFT) : 0x1fff; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg3.reserved1 = 0x0; + descriptorStruct.regionSection.flReg3.LIMIT = hasGbe ? (GBEREGIONSIZE_8K >> FLREGIONBITSHIFT) : 0x0000; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg3.reserved2 = 0x0; + /* FLREG4 (Platform) */ + descriptorStruct.regionSection.flReg4.BASE = 0x1fff; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg4.reserved1 = 0x0; + descriptorStruct.regionSection.flReg4.LIMIT = 0x0000; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg4.reserved2 = 0x0; + /* Padding */ + for (i = 0; i < 12; i++) { + descriptorStruct.regionSection.padding[i] = 0xFF; + } + + /* Master Access Section */ + /* FLMSTR1 (Host CPU / BIOS) */ + descriptorStruct.masterAccessSection.flMstr1.requesterId = 0x0000; + descriptorStruct.masterAccessSection.flMstr1.fdRegionReadAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.biosRegionReadAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.meRegionReadAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.gbeRegionReadAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.pdRegionReadAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.reserved1 = 0x0; + descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.reserved2 = 0x0; + /* FLMSTR2 (ME) */ + descriptorStruct.masterAccessSection.flMstr2.requesterId = 0x0000; + descriptorStruct.masterAccessSection.flMstr2.fdRegionReadAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.biosRegionReadAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.meRegionReadAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.gbeRegionReadAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.pdRegionReadAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.reserved1 = 0x0; + descriptorStruct.masterAccessSection.flMstr2.fdRegionWriteAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.biosRegionWriteAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.meRegionWriteAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.gbeRegionWriteAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.pdRegionWriteAccess = 0x0; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr2.reserved2 = 0x0; + /* FLMSTR3 (Gbe) */ + descriptorStruct.masterAccessSection.flMstr3.requesterId = 0x0218; + descriptorStruct.masterAccessSection.flMstr3.fdRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.biosRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.meRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.gbeRegionReadAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr3.pdRegionReadAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.reserved1 = 0x0; + descriptorStruct.masterAccessSection.flMstr3.fdRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.biosRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.meRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.gbeRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr3.pdRegionWriteAccess = 0x0; + descriptorStruct.masterAccessSection.flMstr3.reserved2 = 0x0; + /* Padding */ + for (i = 0; i < 148; i++) { + descriptorStruct.masterAccessSection.padding[i] = 0xFF; + } + + /* ICH straps */ + /* ICHSTRAP0 */ + descriptorStruct.ichStraps.ichStrap0.meDisable = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.ichStraps.ichStrap0.reserved1 = 0x04; + descriptorStruct.ichStraps.ichStrap0.tcoMode = 0x1; + descriptorStruct.ichStraps.ichStrap0.smBusAddress = 0x64; + descriptorStruct.ichStraps.ichStrap0.bmcMode = 0x0; + descriptorStruct.ichStraps.ichStrap0.tripPointSelect = 0x0; + descriptorStruct.ichStraps.ichStrap0.reserved2 = 0x0; + descriptorStruct.ichStraps.ichStrap0.integratedGbe = hasGbe ? 0x1 : 0x0; + descriptorStruct.ichStraps.ichStrap0.lanPhy = hasGbe ? 0x1 : 0x0; + descriptorStruct.ichStraps.ichStrap0.reserved3 = 0x0; + descriptorStruct.ichStraps.ichStrap0.dmiRequesterId = 0x0; + descriptorStruct.ichStraps.ichStrap0.smBus2Address = 0x00; + /* ICHSTRAP1 */ + descriptorStruct.ichStraps.ichStrap1.northMlink = 0x1; + descriptorStruct.ichStraps.ichStrap1.southMlink = 0x1; + descriptorStruct.ichStraps.ichStrap1.meSmbus = 0x1; + descriptorStruct.ichStraps.ichStrap1.sstDynamic = 0x1; + descriptorStruct.ichStraps.ichStrap1.reserved1 = 0x0; + descriptorStruct.ichStraps.ichStrap1.northMlink2 = 0x1; + descriptorStruct.ichStraps.ichStrap1.reserved2 = 0x00; + descriptorStruct.ichStraps.ichStrap1.reserved3 = 0x0000; + /* Padding */ + for (i = 0; i < 248; i++) { + descriptorStruct.ichStraps.padding[i] = 0xFF; + } + + /* MCH straps */ + /* MCHSTRAP0 */ + descriptorStruct.mchStraps.mchStrap0.meDisable = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.mchStraps.mchStrap0.meBootFromFlash = 0x0; + descriptorStruct.mchStraps.mchStrap0.tpmDisable = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.mchStraps.mchStrap0.reserved1 = 0x7; + descriptorStruct.mchStraps.mchStrap0.spiFingerprint = 0x1; + descriptorStruct.mchStraps.mchStrap0.meAlternateDisable = 0x0; + descriptorStruct.mchStraps.mchStrap0.reserved2 = 0xff; + descriptorStruct.mchStraps.mchStrap0.reserved3 = 0xffff; + /* Padding */ + for (i = 0; i < 3292; i++) { + descriptorStruct.mchStraps.padding[i] = 0xFF; + } + + /* ME VSCC Table */ + descriptorStruct.meVsccTable.jid0 = 0x001720c2; + descriptorStruct.meVsccTable.vscc0 = 0x20052005; + descriptorStruct.meVsccTable.jid1 = 0x001730ef; + descriptorStruct.meVsccTable.vscc1 = 0x20052005; + descriptorStruct.meVsccTable.jid2 = 0x0000481f; + descriptorStruct.meVsccTable.vscc2 = 0x20152015; + /* Padding */ + for (i = 0; i < 4; i++) { + descriptorStruct.meVsccTable.padding[i] = 0xFF; + } + + /* Descriptor Map 2 Record */ + descriptorStruct.descriptor2Map.meVsccTableBaseAddress = 0xee; + descriptorStruct.descriptor2Map.meVsccTableLength = 0x06; + descriptorStruct.descriptor2Map.reserved = 0x0000; + + /* OEM section */ + /* see ../descriptor/descriptor.c */ + /* Magic String (ascii characters) */ + descriptorStruct.oemSection.magicString[0] = 0x4c; + descriptorStruct.oemSection.magicString[1] = 0x49; + descriptorStruct.oemSection.magicString[2] = 0x42; + descriptorStruct.oemSection.magicString[3] = 0x45; + descriptorStruct.oemSection.magicString[4] = 0x52; + descriptorStruct.oemSection.magicString[5] = 0x41; + descriptorStruct.oemSection.magicString[6] = 0x54; + descriptorStruct.oemSection.magicString[7] = 0x45; + /* Padding */ + for (i = 0; i < 248; i++) { + descriptorStruct.oemSection.padding[i] = 0xFF; + } + + return descriptorStruct; +} + diff --git a/projects/ich9gen/sources/src/ich9gen/mkdescriptor.h b/projects/ich9gen/sources/src/ich9gen/mkdescriptor.h new file mode 100644 index 00000000..8663db8c --- /dev/null +++ b/projects/ich9gen/sources/src/ich9gen/mkdescriptor.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2014 Leah Rowe + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef ICH9GEN_MKDESCRIPTOR_H +#define ICH9GEN_MKDESCRIPTOR_H + +#include +#include +#include +#include "../descriptor/descriptor.h" + +struct DESCRIPTORREGIONRECORD generatedDescriptorStruct(unsigned int romSize, int hasGbe); +#endif diff --git a/projects/ich9gen/sources/src/ich9gen/mkgbe.c b/projects/ich9gen/sources/src/ich9gen/mkgbe.c new file mode 100644 index 00000000..d6865823 --- /dev/null +++ b/projects/ich9gen/sources/src/ich9gen/mkgbe.c @@ -0,0 +1,257 @@ +/* + * Copyright (C) 2014 Leah Rowe + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "mkgbe.h" + +/* Generate a 4KiB Gbe struct, with default values. */ +/* Read ../gbe/gbe.h for an explanation of the default values used here */ + +struct GBEREGIONRECORD_4K generatedGbeStruct4k() +{ + int i; + struct GBEREGIONRECORD_4K gbeStruct4k; + + /* MAC address (words 00h to 02h) */ + /* see ../gbe/gbe.c */ + gbeStruct4k.macAddress[0] = 0x00; + gbeStruct4k.macAddress[1] = 0xDE; + gbeStruct4k.macAddress[2] = 0xAD; + gbeStruct4k.macAddress[3] = 0xC0; + gbeStruct4k.macAddress[4] = 0xFF; + gbeStruct4k.macAddress[5] = 0xEE; + + /* Word 03h (Reserved) */ + gbeStruct4k.reservedWord03h.reserved1_0 = 0x00; + gbeStruct4k.reservedWord03h.reserved1_1 = 0x0; + gbeStruct4k.reservedWord03h.ibaLom = 0x1; + gbeStruct4k.reservedWord03h.reserved2 = 0x0; + + /* Word 04h (Reserved) */ + gbeStruct4k.reservedWord04h = 0xffff; + + /* Word 05h (Image Version Information) */ + gbeStruct4k.imageVersionInformation = 0x1083; + + /* Words 06h and 07h (Reserved) */ + gbeStruct4k.reservedWords06h07h[0] = 0xffff; + gbeStruct4k.reservedWords06h07h[1] = 0xffff; + + /* Word 08h and 09h (PBA Low and PBA High) */ + gbeStruct4k.pbaLow = 0x1008; + gbeStruct4k.pbaHigh = 0xffff; + + /* Word 0Ah (PCI Initialization Control Word) */ + gbeStruct4k.pciInitializationControlWord.loadVendorDeviceId = 0x1; + gbeStruct4k.pciInitializationControlWord.loadSubsystemId = 0x1; + gbeStruct4k.pciInitializationControlWord.reserved1 = 0x0; + gbeStruct4k.pciInitializationControlWord.reserved2 = 0x0; + gbeStruct4k.pciInitializationControlWord.pmEnable = 0x1; + gbeStruct4k.pciInitializationControlWord.auxPwr = 0x1; + gbeStruct4k.pciInitializationControlWord.reserved3 = 0x0; + gbeStruct4k.pciInitializationControlWord.reserved4 = 0x1; + + /* Word 0Bh (Subsystem ID) */ + gbeStruct4k.subsystemId = 0x20ee; + + /* Word 0Ch (Subsystem Vendor ID) */ + gbeStruct4k.subsystemVendorId = 0x17aa; + + /* Word 0Dh (Device ID) */ + gbeStruct4k.deviceId = 0x10f5; + + /* Word 0Eh (Vendor ID) */ + gbeStruct4k.vendorId = 0x8086; + + /* Word 0Fh (Device Revision ID) */ + gbeStruct4k.deviceRevId = 0x0000; + + /* Word 10h (LAN Power Consumption) */ + gbeStruct4k.lanPowerConsumption.lanD3Power = 0x01; + gbeStruct4k.lanPowerConsumption.reserved = 0x0; + gbeStruct4k.lanPowerConsumption.lanD0Power = 0x0d; + + /* Words 11h and 12h (Reserved) */ + gbeStruct4k.reservedWords11h12h[0] = 0x0000; + gbeStruct4k.reservedWords11h12h[1] = 0x0000; + + /* Word 13h (Shared Initialization Control Word) */ + gbeStruct4k.sharedInitializationControlWord.reserved1 = 0x5; + gbeStruct4k.sharedInitializationControlWord.forceDuplex = 0x0; + gbeStruct4k.sharedInitializationControlWord.forceSpeedEnable = 0x0; + gbeStruct4k.sharedInitializationControlWord.reserved2_0 = 0x0; + gbeStruct4k.sharedInitializationControlWord.reserved2_1 = 0x0; + gbeStruct4k.sharedInitializationControlWord.phyPowerDownEnable = 0x1; + gbeStruct4k.sharedInitializationControlWord.reserved3 = 0x1; + gbeStruct4k.sharedInitializationControlWord.reserved4 = 0x0; + gbeStruct4k.sharedInitializationControlWord.sign = 0x2; + + /* Word 14h (Extended Configuration Control Word 1) */ + gbeStruct4k.extendedConfigurationControlWord1.extendedConfigurationPointer = 0x020; + gbeStruct4k.extendedConfigurationControlWord1.oemWriteEnable = 0x1; + gbeStruct4k.extendedConfigurationControlWord1.reserved1 = 0x1; + gbeStruct4k.extendedConfigurationControlWord1.reserved2 = 0x0; + gbeStruct4k.extendedConfigurationControlWord1.reserved3 = 0x0; + + /* Word 15h (Extended Configuration Control Word 2) */ + gbeStruct4k.extendedConfigurationControlWord2.reserved = 0x00; + gbeStruct4k.extendedConfigurationControlWord2.extendedPhyLength = 0x0a; + + /* Word 16h (Extended Configuration Control Word 3) */ + gbeStruct4k.extendedConfigurationControlWord3 = 0x0000; + + /* Word 17h (LED 1 Configuration and Power Management) */ + gbeStruct4k.ledCtl1.led1Mode = 0xb; + gbeStruct4k.ledCtl1.reserved1 = 0x0; + gbeStruct4k.ledCtl1.led1BlinkMode = 0x0; + gbeStruct4k.ledCtl1.led1Invert = 0x0; + gbeStruct4k.ledCtl1.led1Blink = 0x1; + gbeStruct4k.ledCtl1.reserved2 = 0x1; + gbeStruct4k.ledCtl1.lpluEnable = 0x0; + gbeStruct4k.ledCtl1.lpluEnableNonD0a = 0x1; + gbeStruct4k.ledCtl1.gbeDisableNonD0a = 0x1; + gbeStruct4k.ledCtl1.reserved3 = 0x0; + gbeStruct4k.ledCtl1.gbeDisable = 0x0; + gbeStruct4k.ledCtl1.reserved4 = 0x1; + + /* Word 18h (LED 0 and 2 Configuration Defaults) */ + gbeStruct4k.ledCtl02.led0Mode = 0x2; + gbeStruct4k.ledCtl02.reserved1 = 0x0; + gbeStruct4k.ledCtl02.led0BlinkMode = 0x0; + gbeStruct4k.ledCtl02.led0Invert = 0x0; + gbeStruct4k.ledCtl02.led0Blink = 0x0; + gbeStruct4k.ledCtl02.led2Mode = 0x6; + gbeStruct4k.ledCtl02.reserved2 = 0x0; + gbeStruct4k.ledCtl02.led2BlinkMode = 0x0; + gbeStruct4k.ledCtl02.led2Invert = 0x0; + gbeStruct4k.ledCtl02.led2Blink = 0x0; + + /* Word 19h (Reserved) */ + gbeStruct4k.reservedWord19h = 0x2b40; + + /* Word 1Ah (Reserved) */ + gbeStruct4k.reservedWord1Ah = 0x0043; + + /* Word 1Bh (Reserved) */ + gbeStruct4k.reservedWord1Bh = 0x0000; + + /* Word 1Ch (Reserved) */ + gbeStruct4k.reservedWord1Ch = 0x10f5; + + /* Word 1Dh (Reserved) */ + gbeStruct4k.reservedWord1Dh = 0xbaad; + + /* Word 1Eh (Device ID for Intel 82567LM gigabit ethernet controller) */ + gbeStruct4k._82567lmDeviceId = 0x10f5; + + /* Word 1Fh (Device ID for Intel 82567LF gigabit ethernet controller) */ + gbeStruct4k._82567lfDeviceId = 0x10bf; + + /* Word 20h (Reserved) */ + gbeStruct4k.reservedWord20h = 0xbaad; + + /* Word 21h (Device ID for Intel 82567V gigabit ethernet controller) */ + gbeStruct4k._82567vDeviceId = 0x10cb; + + /* Word 22h (Reserved) */ + gbeStruct4k.reservedWord22h = 0xbaad; + + /* Word 23h (Reserved) */ + gbeStruct4k.reservedWord23h = 0xbaad; + + /* Words 24h to 2Fh (Reserved) */ + gbeStruct4k.reservedWords24to2Fh[0] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[1] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[2] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[3] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[4] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[5] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[6] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[7] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[8] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[9] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[10] = 0x0000; + gbeStruct4k.reservedWords24to2Fh[11] = 0x0000; + + /* Words 30h to 3Eh (PXE Software Region) */ + /* Boot Agent Main Setup Options (Word 30h) */ + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.protocolSelect = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved1 = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.defaultBootSelection = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved2 = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.promptTime = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.displaySetupMessage = 0x1; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved3 = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.forceSpeed = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.forceFullDuplex = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.reserved4 = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.efiPresence = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentMainSetupOptions.pxePresence = 0x0; + /* Boot Agent Configuration Customization Options (Word 31h) */ + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableSetupMenu = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableTitleMessage = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableProtocolSelect = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableBootSelection = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableLegacyWakeupSupport = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.disableFlashUpdate = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.reserved1 = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.ibaBootOrderSetupMode = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.reserved2 = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.signature = 0x1; + /* Boot Agent Configuration Customization Options (Word 32h) */ + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.buildNumber = 0x18; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.minorVersionNumber = 0x3; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.majorVersionNumber = 0x1; + /* IBA Capabilities (Word 33h) */ + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.baseCodePresent = 0x1; + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.undiCapabilityPresent = 0x1; + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved1 = 0x1; + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.efiUndiCapabilityPresent = 0x0; + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved2_0 = 0x0; + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.reserved2_1 = 0x00; + gbeStruct4k.pxeSoftwareRegion.ibaCapabilities.signature = 0x1; + /* Padding (Words 34h to 3Eh) */ + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[0] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[1] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[2] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[3] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[4] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[5] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[6] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[7] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[8] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[9] = 0xffff; + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[10] = 0xffff; + + /* Word 3Fh (Checksum) */ + gbeStruct4k.checkSum = 0x348a; + + /* The rest of Gbe (word 40h or byte 80h onwards) is just padding (0xFF) */ + for (i = 0; i < 3968; i++) { + gbeStruct4k.padding[i] = 0xFF; + } + + return gbeStruct4k; +} + +struct GBEREGIONRECORD_8K generatedGbeStruct8k() +{ + struct GBEREGIONRECORD_8K gbeStruct8k; + gbeStruct8k.main = generatedGbeStruct4k(); + memcpy(&gbeStruct8k.backup, &gbeStruct8k.main, GBEREGIONSIZE_4K); + return gbeStruct8k; +} + diff --git a/projects/ich9gen/sources/src/ich9gen/mkgbe.h b/projects/ich9gen/sources/src/ich9gen/mkgbe.h new file mode 100644 index 00000000..16974172 --- /dev/null +++ b/projects/ich9gen/sources/src/ich9gen/mkgbe.h @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2014 Leah Rowe + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef ICH9GEN_MKGBE_H +#define ICH9GEN_MKGBE_H + +#include +#include +#include +#include "../gbe/gbe.h" + +struct GBEREGIONRECORD_4K generatedGbeStruct4k(); +struct GBEREGIONRECORD_8K generatedGbeStruct8k(); + +#endif -- cgit v1.2.3-70-g09d2 From 115fe0d7fe537a3069ba2051942c2f3333d0baa5 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Mon, 15 Jan 2018 21:47:32 -0500 Subject: Delete trailing whitespace from ich9gen & co. --- projects/ich9gen/sources/Makefile | 16 +-- .../ich9gen/sources/src/common/descriptor_gbe.c | 36 +++---- .../ich9gen/sources/src/common/descriptor_gbe.h | 4 +- .../ich9gen/sources/src/common/x86compatibility.c | 48 ++++----- .../ich9gen/sources/src/common/x86compatibility.h | 4 +- projects/ich9gen/sources/src/demefactory.c | 38 +++---- projects/ich9gen/sources/src/demefactory.h | 4 +- .../ich9gen/sources/src/descriptor/descriptor.c | 94 ++++++++--------- .../ich9gen/sources/src/descriptor/descriptor.h | 44 ++++---- projects/ich9gen/sources/src/gbe/gbe.c | 78 +++++++------- projects/ich9gen/sources/src/gbe/gbe.h | 116 ++++++++++----------- projects/ich9gen/sources/src/ich9deblob.c | 44 ++++---- projects/ich9gen/sources/src/ich9deblob.h | 4 +- projects/ich9gen/sources/src/ich9gen.c | 46 ++++---- projects/ich9gen/sources/src/ich9gen.h | 4 +- .../ich9gen/sources/src/ich9gen/mkdescriptor.c | 1 - projects/ich9gen/sources/src/ich9gen/mkgbe.c | 1 - 17 files changed, 290 insertions(+), 292 deletions(-) diff --git a/projects/ich9gen/sources/Makefile b/projects/ich9gen/sources/Makefile index dad57e7f..e16b63f0 100644 --- a/projects/ich9gen/sources/Makefile +++ b/projects/ich9gen/sources/Makefile @@ -1,4 +1,4 @@ -# +# # Makefile for ich9deblob utility from libreboot project # # Copyright (C) 2014, 2015 Leah Rowe @@ -26,15 +26,15 @@ all: ich9deblob ich9gen demefactory ich9deblob: obj/ich9deblob.o obj/common/descriptor_gbe.o \ obj/descriptor/descriptor.o obj/gbe/gbe.o obj/common/x86compatibility.o - + $(CC) $(CFLAGS) obj/ich9deblob.o obj/common/descriptor_gbe.o \ obj/common/x86compatibility.o obj/descriptor/descriptor.o obj/gbe/gbe.o \ -o ich9deblob - + ich9gen: obj/ich9gen.o obj/ich9gen/mkdescriptor.o obj/ich9gen/mkgbe.o \ obj/common/descriptor_gbe.o \ obj/descriptor/descriptor.o obj/gbe/gbe.o obj/common/x86compatibility.o - + $(CC) $(CFLAGS) obj/ich9gen.o obj/ich9gen/mkdescriptor.o obj/ich9gen/mkgbe.o \ obj/common/descriptor_gbe.o \ obj/common/x86compatibility.o obj/descriptor/descriptor.o obj/gbe/gbe.o \ @@ -42,7 +42,7 @@ ich9gen: obj/ich9gen.o obj/ich9gen/mkdescriptor.o obj/ich9gen/mkgbe.o \ demefactory: obj/demefactory.o obj/common/descriptor_gbe.o \ obj/descriptor/descriptor.o obj/gbe/gbe.o obj/common/x86compatibility.o - + $(CC) $(CFLAGS) obj/demefactory.o obj/common/descriptor_gbe.o \ obj/common/x86compatibility.o obj/descriptor/descriptor.o obj/gbe/gbe.o \ -o demefactory @@ -64,7 +64,7 @@ obj/ich9deblob.o: obj/ich9gen.o: $(CC) $(CFLAGS) $(NOLINKER) src/ich9gen.c -o obj/ich9gen.o - + obj/ich9gen/mkdescriptor.o: $(CC) $(CFLAGS) $(NOLINKER) src/ich9gen/mkdescriptor.c -o obj/ich9gen/mkdescriptor.o @@ -76,7 +76,7 @@ obj/ich9gen/mkgbe.o: obj/common/descriptor_gbe.o: $(CC) $(CFLAGS) $(NOLINKER) src/common/descriptor_gbe.c -o obj/common/descriptor_gbe.o - + obj/common/x86compatibility.o: $(CC) $(CFLAGS) $(NOLINKER) src/common/x86compatibility.c -o obj/common/x86compatibility.o @@ -85,7 +85,7 @@ obj/descriptor/descriptor.o: obj/gbe/gbe.o: $(CC) $(CFLAGS) $(NOLINKER) src/gbe/gbe.c -o obj/gbe/gbe.o - + # make clean # ---------------------------------------------------------------------- clean: diff --git a/projects/ich9gen/sources/src/common/descriptor_gbe.c b/projects/ich9gen/sources/src/common/descriptor_gbe.c index 1c1ad32b..bce8afc3 100644 --- a/projects/ich9gen/sources/src/common/descriptor_gbe.c +++ b/projects/ich9gen/sources/src/common/descriptor_gbe.c @@ -1,7 +1,7 @@ /* * descriptor_gbe.c * This file is part of the ich9deblob utility from the libreboot project - * + * * Purpose: common descriptor/gbe functions used by ich9deblob * * Copyright (C) 2014, 2015 Leah Rowe @@ -20,71 +20,71 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + #include "descriptor_gbe.h" -/* +/* * create 12KiB file with descriptor, and then gbe immediately after. */ int notCreatedDescriptorGbeFile(struct DESCRIPTORREGIONRECORD descriptorStruct, struct GBEREGIONRECORD_8K gbeStruct8k, char* fileName) { FILE* fileStream = NULL; - + /* delete old file before continuing */ remove(fileName); - + /* open new file for writing the descriptor+gbe */ fileStream = fopen(fileName, "ab"); - + /* write the descriptor region into the first part */ if (DESCRIPTORREGIONSIZE != fwrite((uint8_t*)&descriptorStruct, 1, sizeof(descriptorStruct), fileStream)) { printf("\nerror: writing descriptor region failed\n"); return 1; } - + /* add gbe to the end of the file */ if (GBEREGIONSIZE_8K != fwrite((uint8_t*)&gbeStruct8k, 1, sizeof(gbeStruct8k), fileStream)) { printf("\nerror: writing GBe region failed\n"); return 1; } - + fclose(fileStream); - + printf("descriptor and gbe successfully written to the file: %s\n", fileName); printf("Now do: dd if=%s of=libreboot.rom bs=1 count=12k conv=notrunc\n", fileName); printf("(in other words, add the modified descriptor+gbe to your ROM image)\n\n"); - + return 0; } -/* +/* * create 4KiB file with descriptor */ int notCreated4kDescriptorFile(struct DESCRIPTORREGIONRECORD descriptorStruct, char* fileName) { FILE* fileStream = NULL; - + /* delete old file before continuing */ remove(fileName); - + /* open new file for writing the descriptor+gbe */ fileStream = fopen(fileName, "ab"); - + /* write the descriptor region into the first part */ if (DESCRIPTORREGIONSIZE != fwrite((uint8_t*)&descriptorStruct, 1, sizeof(descriptorStruct), fileStream)) { printf("\nerror: writing descriptor region failed\n"); return 1; } - - + + fclose(fileStream); - + printf("descriptor successfully written to the file: %s\n", fileName); printf("Now do: dd if=%s of=yourrom.rom bs=1 count=4k conv=notrunc\n", fileName); printf("(in other words, add the modified descriptor to your ROM image)\n\n"); - + return 0; } diff --git a/projects/ich9gen/sources/src/common/descriptor_gbe.h b/projects/ich9gen/sources/src/common/descriptor_gbe.h index b3713c80..ff685720 100644 --- a/projects/ich9gen/sources/src/common/descriptor_gbe.h +++ b/projects/ich9gen/sources/src/common/descriptor_gbe.h @@ -1,7 +1,7 @@ /* * gbe_descriptor.h * This file is part of the ich9deblob utility from the libreboot project - * + * * Purpose: header file for descriptor_gbe.c * * Copyright (C) 2014, 2015 Leah Rowe @@ -20,7 +20,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + #ifndef COMMON_DESCRIPTOR_GBE_H #define COMMON_DESCRIPTOR_GBE_H diff --git a/projects/ich9gen/sources/src/common/x86compatibility.c b/projects/ich9gen/sources/src/common/x86compatibility.c index 362c634b..522f3e29 100644 --- a/projects/ich9gen/sources/src/common/x86compatibility.c +++ b/projects/ich9gen/sources/src/common/x86compatibility.c @@ -1,7 +1,7 @@ /* * x86compatibility.c * This file is part of the ich9deblob utility from the libreboot project - * + * * Purpose: compiler/cpu compatibility checks. ich9deblob is not portable, yet. * * Copyright (C) 2014 Steve Shenton @@ -30,11 +30,11 @@ */ /* fail if struct size is incorrect */ -int structSizesIncorrect(struct DESCRIPTORREGIONRECORD descriptorDummy, struct GBEREGIONRECORD_8K gbe8kDummy) +int structSizesIncorrect(struct DESCRIPTORREGIONRECORD descriptorDummy, struct GBEREGIONRECORD_8K gbe8kDummy) { unsigned int descriptorRegionStructSize = sizeof(descriptorDummy); unsigned int gbeRegion8kStructSize = sizeof(gbe8kDummy); - + /* check compiler bit-packs in a compatible way. basically, it is expected that this code will be used on x86 */ if (DESCRIPTORREGIONSIZE != descriptorRegionStructSize){ printf("\nerror: compiler incompatibility: descriptor struct length is %i bytes (should be %i)\n", descriptorRegionStructSize, DESCRIPTORREGIONSIZE); @@ -44,7 +44,7 @@ int structSizesIncorrect(struct DESCRIPTORREGIONRECORD descriptorDummy, struct G printf("\nerror: compiler incompatibility: gbe struct length is %i bytes (should be %i)\n", gbeRegion8kStructSize, GBEREGIONSIZE_8K); return 1; } - + return 0; } @@ -54,7 +54,7 @@ int structMembersWrongOrder() int i; struct DESCRIPTORREGIONRECORD descriptorDummy; uint8_t *meVsccTablePtr = (uint8_t*)&descriptorDummy.meVsccTable; - + /* These do not use bitfields. */ descriptorDummy.meVsccTable.jid0 = 0x01020304; /* unsigned int 32-bit */ descriptorDummy.meVsccTable.vscc0 = 0x10203040; /* unsigned int 32-bit */ @@ -66,10 +66,10 @@ int structMembersWrongOrder() descriptorDummy.meVsccTable.padding[1] = 0xBB; /* unsigned char 8-bit */ descriptorDummy.meVsccTable.padding[2] = 0xCC; /* unsigned char 8-bit */ descriptorDummy.meVsccTable.padding[3] = 0xDD; /* unsigned char 8-bit */ - + /* * Look from the top down, and concatenate the unsigned ints but - * with each unsigned in little endian order. + * with each unsigned in little endian order. * Then, concatenate the unsigned chars in big endian order. (in the padding array) * * combined, these should become: @@ -77,7 +77,7 @@ int structMembersWrongOrder() * 04030201 40302010 44332211 08070605 80706050 88776655 AA BB CC DD (ignore this. not byte-separated, just working it out:) * 04 03 02 01 40 30 20 10 44 33 22 11 08 07 06 05 80 70 60 50 88 77 66 55 AA BB CC DD <-- it should match this */ - + if ( ! ( @@ -90,65 +90,65 @@ int structMembersWrongOrder() && *(meVsccTablePtr+24) == 0xAA && *(meVsccTablePtr+25) == 0xBB && *(meVsccTablePtr+26) == 0xCC && *(meVsccTablePtr+27) == 0xDD ) ) { - + printf("\nStruct member order check (descriptorDummy.meVsccTable) with junk/dummy data:"); printf("\nShould be: 04 03 02 01 40 30 20 10 44 33 22 11 08 07 06 05 80 70 60 50 88 77 66 55 aa bb cc dd "); printf("\nAnd it is: "); - + for (i = 0; i < 28; i++) { - printf("%02x ", *(meVsccTablePtr + i)); + printf("%02x ", *(meVsccTablePtr + i)); } printf("\nIncorrect order.\n"); - + return 1; } - + return 0; } /* fail if bit fields are presented in the wrong order */ -int structBitfieldWrongOrder() +int structBitfieldWrongOrder() { int i; struct DESCRIPTORREGIONRECORD descriptorDummy; uint8_t *flMap0Ptr = (uint8_t*)&descriptorDummy.flMaps.flMap0; - + descriptorDummy.flMaps.flMap0.FCBA = 0xA2; /* :8 --> 10100010 */ descriptorDummy.flMaps.flMap0.NC = 0x02; /* :2 --> 10 */ descriptorDummy.flMaps.flMap0.reserved1 = 0x38; /* :6 --> 111000 */ descriptorDummy.flMaps.flMap0.FRBA = 0xD2; /* :8 --> 11010010 */ descriptorDummy.flMaps.flMap0.NR = 0x05; /* :3 --> 101 */ descriptorDummy.flMaps.flMap0.reserved2 = 0x1C; /* :5 --> 11100 */ - + /* * Look from the top bottom up, and concatenate the binary strings. * Then, convert the 8-bit groups to hex and reverse the (8-bit)byte order - * + * * combined, these should become (in memory), in binary: * 10100010 11100010 11010010 11100101 * or in hex: * A2 E2 D2 E5 */ - - if (!(*flMap0Ptr == 0xA2 && *(flMap0Ptr+1) == 0xE2 && *(flMap0Ptr+2) == 0xD2 && *(flMap0Ptr+3) == 0xE5)) + + if (!(*flMap0Ptr == 0xA2 && *(flMap0Ptr+1) == 0xE2 && *(flMap0Ptr+2) == 0xD2 && *(flMap0Ptr+3) == 0xE5)) { printf("\nBitfield order check (descriptorDummy.flMaps.flMaps0) with junk/dummy data:"); printf("\nShould be: a2 e2 d2 e5 "); printf("\nAnd it is: "); for (i = 0; i < 4; i++) { - printf("%02x ", *(flMap0Ptr + i)); + printf("%02x ", *(flMap0Ptr + i)); } printf("\nIncorrect order.\n"); - + return 1; } - + return 0; } /* Compatibility checks. This version of ich9deblob is not yet porable. */ -int systemOrCompilerIncompatible(struct DESCRIPTORREGIONRECORD descriptorStruct, struct GBEREGIONRECORD_8K gbeStruct8k) +int systemOrCompilerIncompatible(struct DESCRIPTORREGIONRECORD descriptorStruct, struct GBEREGIONRECORD_8K gbeStruct8k) { if (structSizesIncorrect(descriptorStruct, gbeStruct8k)) return 1; if (IS_BIG_ENDIAN) { @@ -156,6 +156,6 @@ int systemOrCompilerIncompatible(struct DESCRIPTORREGIONRECORD descriptorStruct, return 1; } if (structBitfieldWrongOrder()) return 1; - if (structMembersWrongOrder()) return 1; + if (structMembersWrongOrder()) return 1; return 0; } diff --git a/projects/ich9gen/sources/src/common/x86compatibility.h b/projects/ich9gen/sources/src/common/x86compatibility.h index 5a598adc..a4829888 100644 --- a/projects/ich9gen/sources/src/common/x86compatibility.h +++ b/projects/ich9gen/sources/src/common/x86compatibility.h @@ -1,7 +1,7 @@ /* * x86compatibility.h * This file is part of the ich9deblob utility from the libreboot project - * + * * Purpose: keep gcc/make happy. no actual code here, just function definitions. * * Copyright (C) 2014 Steve Shenton @@ -20,7 +20,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + #ifndef X86COMPATIBILITY_H #define X86COMPATIBILITY_H diff --git a/projects/ich9gen/sources/src/demefactory.c b/projects/ich9gen/sources/src/demefactory.c index 596118cf..96bb0d41 100644 --- a/projects/ich9gen/sources/src/demefactory.c +++ b/projects/ich9gen/sources/src/demefactory.c @@ -1,12 +1,12 @@ /* * demefactory.c * This file is part of the demefactory utility from the libreboot project - * + * * Purpose: disable ME on GM45 factory firmware, but leave region intact * enable read-write on all regions * * Copyright (C) 2014, 2015 Leah Rowe - * Copyright (C) 2014 Steve Shenton + * Copyright (C) 2014 Steve Shenton * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +21,8 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - -/* + +/* * demfactory utility - main */ @@ -32,15 +32,15 @@ int main() { struct DESCRIPTORREGIONRECORD descriptorStruct; uint8_t* descriptorBuffer = (uint8_t*)&descriptorStruct; - + struct GBEREGIONRECORD_8K gbeStruct8k; /* not needed, except for compatibility checking */ - + char* romFilename = "factory.rom"; char* descriptorFilename = "demefactory_4kdescriptor.bin"; - + unsigned int bufferLength; unsigned int romSize; - + /* * ------------------------------------------------------------------ * Compatibility checks. This version of ich9deblob is not yet portable. @@ -49,7 +49,7 @@ int main() if (systemOrCompilerIncompatible(descriptorStruct, gbeStruct8k)) return 1; /* If true, fail with error message */ - + /* * ------------------------------------------------------------------ * Extract the descriptor region from the factory.rom dump @@ -64,33 +64,33 @@ int main() return 1; } printf("\n%s opened successfully\n", romFilename); - - /* + + /* * Get the descriptor region dump from the factory.rom * (goes in factoryDescriptorBuffer variable) */ bufferLength = fread(descriptorBuffer, 1, DESCRIPTORREGIONSIZE, fp); - if (DESCRIPTORREGIONSIZE != bufferLength) // + if (DESCRIPTORREGIONSIZE != bufferLength) // { printf("\nerror: could not read descriptor from %s (%i) bytes read\n", romFilename, bufferLength); fclose(fp); return 1; } printf("\ndescriptor region read successfully\n"); - + /* ------------------------------------------------- */ fseek(fp, 0L, SEEK_END); romSize = ftell(fp); printf("\n%s size: [%i] bytes\n", romFilename, romSize); - + /* -------------------------------------------------- */ fclose(fp); - + /* Debugging (before modification) */ printDescriptorRegionLocations(descriptorStruct, "Original"); - + /* * ------------------------------------------------------------------ * Modify the descriptor region, ready to go in the modified factory.rom @@ -100,7 +100,7 @@ int main() // Disable the ME/TPM: descriptorStruct = descriptorDisableMe(descriptorStruct); descriptorStruct = descriptorDisableTpm(descriptorStruct); - + /* Host/CPU is allowed to read/write all regions. */ descriptorStruct = descriptorHostRegionsUnlocked(descriptorStruct); /* The ME is disallowed read-write access to all regions @@ -120,7 +120,7 @@ int main() if (notCreated4kDescriptorFile(descriptorStruct, descriptorFilename)) { return 1; } - + /* * ------------------------------------------------------------------ * Generate ich9gen data (C code that will recreate the deactivatedME descriptor from scratch) @@ -134,7 +134,7 @@ int main() if (notCreatedCFileFromDescriptorStruct(descriptorStruct, "mkdescriptor.c", "mkdescriptor.h")) { return 1; } - + printf("The modified descriptor region has also been dumped as src files: mkdescriptor.c, mkdescriptor.h\n\n"); return 0; diff --git a/projects/ich9gen/sources/src/demefactory.h b/projects/ich9gen/sources/src/demefactory.h index 7226886b..3478cef5 100644 --- a/projects/ich9gen/sources/src/demefactory.h +++ b/projects/ich9gen/sources/src/demefactory.h @@ -14,9 +14,9 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + /* Header file for demefactory.c */ - + #ifndef DEMEFACTORY_H #define DEMEFACTORY_H diff --git a/projects/ich9gen/sources/src/descriptor/descriptor.c b/projects/ich9gen/sources/src/descriptor/descriptor.c index 18e4e17a..61ced67e 100644 --- a/projects/ich9gen/sources/src/descriptor/descriptor.c +++ b/projects/ich9gen/sources/src/descriptor/descriptor.c @@ -1,9 +1,9 @@ /* * descriptor/descriptor.c * This file is part of the ich9deblob utility from the libreboot project - * + * * Copyright (C) 2014, 2015 Leah Rowe - * Copyright (C) 2014 Steve Shenton + * Copyright (C) 2014 Steve Shenton * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,7 +32,7 @@ * --------------------------------------------------------------------- */ -/* Set the Host CPU / BIOS region to have read-write access on all regions */ +/* Set the Host CPU / BIOS region to have read-write access on all regions */ struct DESCRIPTORREGIONRECORD descriptorHostRegionsUnlocked(struct DESCRIPTORREGIONRECORD descriptorStruct) { descriptorStruct.masterAccessSection.flMstr1.fdRegionReadAccess = 0x1; @@ -80,7 +80,7 @@ struct DESCRIPTORREGIONRECORD descriptorPlatformRegionRemoved(struct DESCRIPTORR { descriptorStruct.regionSection.flReg4.BASE = 0x1FFF; descriptorStruct.regionSection.flReg4.LIMIT = 0; - + return descriptorStruct; } @@ -89,7 +89,7 @@ struct DESCRIPTORREGIONRECORD descriptorDisableMe(struct DESCRIPTORREGIONRECORD { descriptorStruct.ichStraps.ichStrap0.meDisable = 1; descriptorStruct.mchStraps.mchStrap0.meDisable = 1; - + return descriptorStruct; } @@ -97,7 +97,7 @@ struct DESCRIPTORREGIONRECORD descriptorDisableMe(struct DESCRIPTORREGIONRECORD struct DESCRIPTORREGIONRECORD descriptorDisableTpm(struct DESCRIPTORREGIONRECORD descriptorStruct) { descriptorStruct.mchStraps.mchStrap0.tpmDisable = 1; - + return descriptorStruct; } @@ -106,7 +106,7 @@ struct DESCRIPTORREGIONRECORD descriptorMoveGbeToStart(struct DESCRIPTORREGIONRE { descriptorStruct.regionSection.flReg3.BASE = DESCRIPTORREGIONSIZE >> FLREGIONBITSHIFT; descriptorStruct.regionSection.flReg3.LIMIT = GBEREGIONSIZE_8K >> FLREGIONBITSHIFT; - + return descriptorStruct; } @@ -115,7 +115,7 @@ struct DESCRIPTORREGIONRECORD descriptorGbeRegionRemoved(struct DESCRIPTORREGION { descriptorStruct.regionSection.flReg3.BASE = 0x1FFF; descriptorStruct.regionSection.flReg3.LIMIT = 0; - + return descriptorStruct; } @@ -124,7 +124,7 @@ struct DESCRIPTORREGIONRECORD descriptorBiosRegionFillImageAfterGbe(struct DESCR { descriptorStruct.regionSection.flReg1.BASE = (DESCRIPTORREGIONSIZE + GBEREGIONSIZE_8K) >> FLREGIONBITSHIFT; descriptorStruct.regionSection.flReg1.LIMIT = (romSize >> FLREGIONBITSHIFT) - 1; - + return descriptorStruct; } @@ -133,7 +133,7 @@ struct DESCRIPTORREGIONRECORD descriptorBiosRegionFillImageAfterDescriptor(struc { descriptorStruct.regionSection.flReg1.BASE = DESCRIPTORREGIONSIZE >> FLREGIONBITSHIFT; descriptorStruct.regionSection.flReg1.LIMIT = (romSize >> FLREGIONBITSHIFT) - 1; - + return descriptorStruct; } @@ -150,7 +150,7 @@ struct DESCRIPTORREGIONRECORD descriptorOemString(struct DESCRIPTORREGIONRECORD descriptorStruct.oemSection.magicString[7] = 0x45; return descriptorStruct; -} +} /* Check whether a GbE region is defined by this descriptor. * Not thorough, but should work in most cases */ @@ -178,7 +178,7 @@ struct DESCRIPTORREGIONRECORD librebootSetGbeBiosDescriptorRegions(struct DESCRI { if (descriptorDefinesGbeRegion(descriptorStruct)) { - /* + /* * set number of regions from 4 -> 2 (0 based, so 4 means 5 and 2 * means 3. We want 3 regions: descriptor, gbe and bios, in that order) */ @@ -193,7 +193,7 @@ struct DESCRIPTORREGIONRECORD librebootSetGbeBiosDescriptorRegions(struct DESCRI descriptorStruct.ichStraps.ichStrap0.lanPhy = 0x1; } else { - /* + /* * set number of regions from 4 -> 2 (0 based, so 4 means 5 and 1 * means 2. We want 2 regions: descriptor and bios, in that order) */ @@ -237,12 +237,12 @@ struct DESCRIPTORREGIONRECORD librebootDescriptorStructFromFactory(struct DESCRI descriptorStruct = descriptorMeRegionRemoved(descriptorStruct); /* Disable the ME/TPM and remove the ME/Platform regions: */ descriptorStruct = descriptorPlatformRegionRemoved(descriptorStruct); - + /* Disable the ME itself, so that it doesn't try to start when this descriptor is in use */ descriptorStruct = descriptorDisableMe(descriptorStruct); /* Also disable the TPM, by default */ descriptorStruct = descriptorDisableTpm(descriptorStruct); - + return descriptorStruct; } @@ -254,64 +254,64 @@ struct DESCRIPTORREGIONRECORD librebootDescriptorStructFromFactory(struct DESCRI /* * Generate a C (.h) header file for the C source file made by notCreatedCFileFromDescriptorStruct() - * + * * Output it to a file. */ -int notCreatedHFileForDescriptorCFile(char* outFileName, char* cFileName) -{ +int notCreatedHFileForDescriptorCFile(char* outFileName, char* cFileName) +{ remove(outFileName); /* Remove the old file before continuing */ - + /* Open the file that will be written to */ FILE* fp = fopen(outFileName, "w+"); /* ------------------------------ */ - + fprintf(fp, "/* %s: generated C code from ich9deblob */\n", outFileName); fprintf(fp, "/* .h header file for the descriptor-generating C code (%s) */\n\n", cFileName); - + fprintf(fp, "#ifndef ICH9GEN_MKDESCRIPTOR_H\n"); fprintf(fp, "#define ICH9GEN_MKDESCRIPTOR_H\n\n"); - + fprintf(fp, "#include \n"); fprintf(fp, "#include \n"); fprintf(fp, "#include \"../descriptor/descriptor.h\"\n\n"); - + fprintf(fp, "struct DESCRIPTORREGIONRECORD generatedDescriptorStruct(unsigned int romSize, int hasGbe);\n"); - + fprintf(fp, "#endif\n"); - + /* ------------------------------ */ - + fclose(fp); /* Always close the file when done. */ - + return 0; } /* * Generate a C source file that initializes the same data from a given * 4KiB Descriptor data structure. - * + * * Output it to a file. */ int notCreatedCFileFromDescriptorStruct(struct DESCRIPTORREGIONRECORD descriptorStruct, char* outFileName, char* headerFileName) { int i, j; - + remove(outFileName); /* Remove the old file before continuing */ - + /* Open the file that will be written to */ FILE* fp = fopen(outFileName, "w+"); /* ------------------------------ */ - + fprintf(fp, "/* %s: generated C code from ich9deblob */\n", outFileName); fprintf(fp, "/* .c source file for the descriptor-generating C code */\n\n"); - + fprintf(fp, "#include \"%s\"\n\n", headerFileName); - + fprintf(fp, "/* Generate a 4KiB Descriptor struct, with default values. */\n"); fprintf(fp, "/* Read ../descriptor/descriptor.h for an explanation of the default values used here */\n\n"); - + fprintf(fp, "struct DESCRIPTORREGIONRECORD generatedDescriptorStruct(unsigned int romSize, int hasGbe)\n"); fprintf(fp, "{\n"); fprintf(fp, " int i;\n"); @@ -600,11 +600,11 @@ int notCreatedCFileFromDescriptorStruct(struct DESCRIPTORREGIONRECORD descriptor fprintf(fp, "\n"); fprintf(fp, " return descriptorStruct;\n"); fprintf(fp, "}\n\n"); - + /* ------------------------------ */ - + fclose(fp); /* Always close the file when done. */ - + return 0; } @@ -620,7 +620,7 @@ int notCreatedCFileFromDescriptorStruct(struct DESCRIPTORREGIONRECORD descriptor void printDescriptorRegionLocations(struct DESCRIPTORREGIONRECORD descriptorStruct, char* romName) { printf("\n"); - + /* Descriptor region */ printf( "%s: Descriptor start block: %08x ; Descriptor end block: %08x\n", @@ -628,23 +628,23 @@ void printDescriptorRegionLocations(struct DESCRIPTORREGIONRECORD descriptorStru descriptorStruct.regionSection.flReg0.BASE << FLREGIONBITSHIFT, descriptorStruct.regionSection.flReg0.LIMIT << FLREGIONBITSHIFT ); - + /* BIOS region */ printf( - "%s: BIOS start block: %08x ; BIOS end block: %08x\n", + "%s: BIOS start block: %08x ; BIOS end block: %08x\n", romName, - descriptorStruct.regionSection.flReg1.BASE << FLREGIONBITSHIFT, + descriptorStruct.regionSection.flReg1.BASE << FLREGIONBITSHIFT, descriptorStruct.regionSection.flReg1.LIMIT << FLREGIONBITSHIFT ); - + /* ME region */ printf( - "%s: ME start block: %08x ; ME end block: %08x\n", + "%s: ME start block: %08x ; ME end block: %08x\n", romName, - descriptorStruct.regionSection.flReg2.BASE << FLREGIONBITSHIFT, + descriptorStruct.regionSection.flReg2.BASE << FLREGIONBITSHIFT, descriptorStruct.regionSection.flReg2.LIMIT << FLREGIONBITSHIFT ); - + /* GBe region */ printf( "%s: GBe start block: %08x ; GBe end block: %08x\n", @@ -652,7 +652,7 @@ void printDescriptorRegionLocations(struct DESCRIPTORREGIONRECORD descriptorStru descriptorStruct.regionSection.flReg3.BASE << FLREGIONBITSHIFT, descriptorStruct.regionSection.flReg3.LIMIT << FLREGIONBITSHIFT ); - + /* Platform region */ printf( "%s: Platform start block: %08x ; Platform end block: %08x\n", @@ -660,6 +660,6 @@ void printDescriptorRegionLocations(struct DESCRIPTORREGIONRECORD descriptorStru descriptorStruct.regionSection.flReg4.BASE << FLREGIONBITSHIFT, descriptorStruct.regionSection.flReg4.LIMIT << FLREGIONBITSHIFT ); - + return; } diff --git a/projects/ich9gen/sources/src/descriptor/descriptor.h b/projects/ich9gen/sources/src/descriptor/descriptor.h index 7fb5c257..c81d451f 100644 --- a/projects/ich9gen/sources/src/descriptor/descriptor.h +++ b/projects/ich9gen/sources/src/descriptor/descriptor.h @@ -18,7 +18,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + /* * Purpose: provide struct representing descriptor region. * Map actual buffers of this regions, directly to instances of these @@ -27,10 +27,10 @@ * bit fields used, corresponding to datasheet. See links to datasheets * and documentation in ich9deblob.c */ - + /* * See docs/hardware/x200_remove_me.html for info plus links to datasheet (also linked below) - * + * * Info about flash descriptor (read page 845 onwards): * http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datasheet.pdf */ @@ -54,7 +54,7 @@ #define ROMSIZE_8MB 0x800000 #define ROMSIZE_16MB 0x1000000 -/* +/* * Related to the flash descriptor * bits 12(0xC)-24(0x18) are represented for words found in the flash descriptor * To manipulate these easily in C, we shift them by FLREGIONBITSHIFT and then shift them back when done @@ -72,7 +72,7 @@ struct FLVALSIG { /* - * 4 bytes. + * 4 bytes. * descriptor mode = 0FF0A55A (hex, big endian). Note: stored in ROM in little endian order. * Anything else is considered invalid and will put the system in non-descriptor mode. */ @@ -92,7 +92,7 @@ struct FLMAP0 /* most significant bits. */ }; -struct FLMAP1 +struct FLMAP1 { /* least significant bits */ uint8_t FMBA : 8; @@ -103,7 +103,7 @@ struct FLMAP1 /* most significant bits */ }; -struct FLMAP2 +struct FLMAP2 { /* least significant bits */ uint8_t FMSBA : 8; @@ -113,7 +113,7 @@ struct FLMAP2 }; /* Flash Map Registers */ -struct FLMAPS +struct FLMAPS { struct FLMAP0 flMap0; struct FLMAP1 flMap1; @@ -121,7 +121,7 @@ struct FLMAPS }; /* Flash Components Register */ -struct FLCOMP +struct FLCOMP { /* least significant bits */ uint8_t component1Density : 3; @@ -138,7 +138,7 @@ struct FLCOMP /* most significant bits */ }; -struct COMPONENTSECTIONRECORD +struct COMPONENTSECTIONRECORD { struct FLCOMP flcomp; uint32_t flill; @@ -146,7 +146,7 @@ struct COMPONENTSECTIONRECORD uint8_t padding[36]; }; -struct FLREG +struct FLREG { /* least significant bits */ uint16_t BASE : 13; @@ -161,7 +161,7 @@ struct FLREG * Defines where all the regions begin/end. * This is very important for disabling ME/AMT */ -struct REGIONSECTIONRECORD +struct REGIONSECTIONRECORD { struct FLREG flReg0; /* Descriptor */ struct FLREG flReg1; /* BIOS */ @@ -171,7 +171,7 @@ struct REGIONSECTIONRECORD uint8_t padding[12]; }; -struct FLMSTR +struct FLMSTR { /* least significant bits */ uint16_t requesterId : 16; @@ -199,7 +199,7 @@ struct MASTERACCESSSECTIONRECORD uint8_t padding[148]; }; -struct ICHSTRAP0 +struct ICHSTRAP0 { /* least significant bits */ /* todo: add MeSmBus2Sel (boring setting) */ @@ -218,7 +218,7 @@ struct ICHSTRAP0 /* most significant bits */ }; -struct ICHSTRAP1 +struct ICHSTRAP1 { /* least significant bits */ uint8_t northMlink : 1; /* North MLink Dynamic Clock Gate Disable : Sets the default value for the South MLink Dynamic Clock Gate Enable registers. */ @@ -233,14 +233,14 @@ struct ICHSTRAP1 }; /* ICH straps */ -struct ICHSTRAPSRECORD +struct ICHSTRAPSRECORD { struct ICHSTRAP0 ichStrap0; struct ICHSTRAP1 ichStrap1; uint8_t padding[248]; }; -struct MCHSTRAP0 +struct MCHSTRAP0 { /* least significant bits */ uint8_t meDisable : 1; /* If true, ME is disabled. */ @@ -255,14 +255,14 @@ struct MCHSTRAP0 }; /* MCH straps */ -struct MCHSTRAPSRECORD +struct MCHSTRAPSRECORD { struct MCHSTRAP0 mchStrap0; uint8_t padding[3292]; }; /* ME VSCC Table */ -struct MEVSCCTABLERECORD +struct MEVSCCTABLERECORD { uint32_t jid0; uint32_t vscc0; @@ -284,14 +284,14 @@ struct DESCRIPTORMAP2RECORD }; /* OEM section */ -struct OEMSECTIONRECORD +struct OEMSECTIONRECORD { uint8_t magicString[8]; uint8_t padding[248]; }; /* 4KiB descriptor region, goes at the beginning of the ROM image */ -struct DESCRIPTORREGIONRECORD +struct DESCRIPTORREGIONRECORD { struct FLVALSIG flValSig; /* Flash Valid Signature Register */ struct FLMAPS flMaps; /* Flash Map Registers */ @@ -310,7 +310,7 @@ struct DESCRIPTORREGIONRECORD * Function declarations (keep gcc/make happy. check them in descriptor.c) * --------------------------------------------------------------------- */ - + struct DESCRIPTORREGIONRECORD descriptorHostRegionsUnlocked(struct DESCRIPTORREGIONRECORD descriptorStruct); struct DESCRIPTORREGIONRECORD descriptorMeRegionsForbidden(struct DESCRIPTORREGIONRECORD descriptorStruct); struct DESCRIPTORREGIONRECORD descriptorMeRegionRemoved(struct DESCRIPTORREGIONRECORD descriptorStruct); diff --git a/projects/ich9gen/sources/src/gbe/gbe.c b/projects/ich9gen/sources/src/gbe/gbe.c index d04b8f2a..6bd41549 100644 --- a/projects/ich9gen/sources/src/gbe/gbe.c +++ b/projects/ich9gen/sources/src/gbe/gbe.c @@ -18,7 +18,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + /* * Provide gbe related functions. */ @@ -40,7 +40,7 @@ uint16_t gbeGetChecksumFrom4kBuffer(uint16_t* gbeWord, uint16_t desiredValue, in for (wordOffset = 0; wordOffset < 0x3F; wordOffset++) total += gbeWord[wordOffset + (gbeRegionBase>>1)]; - + return desiredValue - total; } @@ -51,25 +51,25 @@ uint16_t gbeGetChecksumFrom4kStruct(struct GBEREGIONRECORD_4K gbeStruct4k, uint1 } /* modify the gbe region extracted from a factory.rom dump */ -struct GBEREGIONRECORD_8K deblobbedGbeStructFromFactory(struct GBEREGIONRECORD_8K gbeStruct8k) -{ +struct GBEREGIONRECORD_8K deblobbedGbeStructFromFactory(struct GBEREGIONRECORD_8K gbeStruct8k) +{ unsigned int i; - + /* * http://www.intel.co.uk/content/dam/doc/application-note/82573-nvm-map-appl-note.pdf - * That is a datasheet for a later chipset. Word 40H-53H seems (as per this datasheet) to be for AMT. + * That is a datasheet for a later chipset. Word 40H-53H seems (as per this datasheet) to be for AMT. * Writing over it doesn't seem to cause any harm, since the ME/AMT is already removed in libreboot. */ for(i = 0; i < sizeof(gbeStruct8k.backup.padding); i++) { gbeStruct8k.backup.padding[i] = 0xFF; /* FF is correct. In the struct, this is a char buffer. */ } /* We really only need to do this for words 40h-53h, but let's just nuke the whole lot. It's all 0xFF anyway. */ - + /* Fix the checksum */ gbeStruct8k.backup.checkSum = gbeGetChecksumFrom4kStruct(gbeStruct8k.backup, GBECHECKSUMTOTAL); - + /* Main Gbe region on X200 (as shipped by Lenovo) is broken. Fix it by over-writing it with the contents of the backup */ memcpy(&gbeStruct8k.main, &gbeStruct8k.backup, GBEREGIONSIZE_4K); - + return gbeStruct8k; } @@ -81,46 +81,46 @@ struct GBEREGIONRECORD_8K deblobbedGbeStructFromFactory(struct GBEREGIONRECORD_8 /* * Generate a C (.h) header file for the C source file made by notCreatedCFileFromGbeStruct4k() - * + * * Output it to a file. */ -int notCreatedHFileForGbeCFile(char* outFileName, char* cFileName) -{ +int notCreatedHFileForGbeCFile(char* outFileName, char* cFileName) +{ remove(outFileName); /* Remove the old file before continuing */ - + /* Open the file that will be written to */ FILE* fp = fopen(outFileName, "w+"); /* ------------------------------ */ - + fprintf(fp, "/* %s: generated C code from ich9deblob */\n", outFileName); fprintf(fp, "/* .h header file for the gbe-generating C code (%s) */\n\n", cFileName); - + fprintf(fp, "#ifndef ICH9GEN_MKGBE_H\n"); fprintf(fp, "#define ICH9GEN_MKGBE_H\n\n"); - + fprintf(fp, "#include \n"); fprintf(fp, "#include \n"); fprintf(fp, "#include \"../gbe/gbe.h\"\n\n"); - + fprintf(fp, "struct GBEREGIONRECORD_4K generatedGbeStruct4k();\n"); fprintf(fp, "struct GBEREGIONRECORD_8K generatedGbeStruct8k();\n\n"); - + fprintf(fp, "#endif\n"); - + /* ------------------------------ */ - + fclose(fp); /* Always close the file when done. */ - + return 0; } /* * Generate a C source file that initializes the same data from a given * 4KiB Gbe data structure. - * + * * It will simply copy the 4KiB struct at the end to make a full 8KiB struct. * So just pass a working 4KiB Gbe struct here and you're good to go. - * + * * Output it to a file. */ int notCreatedCFileFromGbeStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* outFileName, char* headerFileName) @@ -128,22 +128,22 @@ int notCreatedCFileFromGbeStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* int i; int paddingSize; int paddingIdentical; - + remove(outFileName); /* Remove the old file before continuing */ - + /* Open the file that will be written to */ FILE* fp = fopen(outFileName, "w+"); /* ------------------------------ */ - + fprintf(fp, "/* %s: generated C code from ich9deblob */\n", outFileName); fprintf(fp, "/* .c source file for the gbe-generating C code */\n\n"); - + fprintf(fp, "#include \"%s\"\n\n", headerFileName); - + fprintf(fp, "/* Generate a 4KiB Gbe struct, with default values. */\n"); fprintf(fp, "/* Read ../gbe/gbe.h for an explanation of the default values used here */\n\n"); - + fprintf(fp, "struct GBEREGIONRECORD_4K generatedGbeStruct4k()\n"); fprintf(fp, "{\n"); fprintf(fp, " int i;\n"); @@ -402,7 +402,7 @@ int notCreatedCFileFromGbeStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* fprintf(fp, "\n"); fprintf(fp, " return gbeStruct4k;\n"); fprintf(fp, "}\n\n"); - + fprintf(fp, "struct GBEREGIONRECORD_8K generatedGbeStruct8k()\n"); fprintf(fp, "{\n"); fprintf(fp, " struct GBEREGIONRECORD_8K gbeStruct8k;\n"); @@ -410,11 +410,11 @@ int notCreatedCFileFromGbeStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* fprintf(fp, " memcpy(&gbeStruct8k.backup, &gbeStruct8k.main, GBEREGIONSIZE_4K);\n"); fprintf(fp, " return gbeStruct8k;\n"); fprintf(fp, "}\n\n"); - + /* ------------------------------ */ - + fclose(fp); /* Always close the file when done. */ - + return 0; } @@ -431,24 +431,24 @@ int notCreatedCFileFromGbeStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* void printGbeChecksumDataFromStruct4k(struct GBEREGIONRECORD_4K gbeStruct4k, char* romName, char* regionName) { printf( - "%s Gbe (%s): calculated Gbe checksum: 0x%hx and actual GBe checksum: 0x%hx\n", + "%s Gbe (%s): calculated Gbe checksum: 0x%hx and actual GBe checksum: 0x%hx\n", romName, regionName, - gbeGetChecksumFrom4kStruct(gbeStruct4k, GBECHECKSUMTOTAL), + gbeGetChecksumFrom4kStruct(gbeStruct4k, GBECHECKSUMTOTAL), gbeStruct4k.checkSum ); - + return; } /* - * show debugging info: show calculated (correct) gbe checksum and what + * show debugging info: show calculated (correct) gbe checksum and what * is actually stored, in a 8K gbe struct. Do so for main and backup regions. */ void printGbeChecksumDataFromStruct8k(struct GBEREGIONRECORD_8K gbeStruct8k, char* romName) -{ +{ printGbeChecksumDataFromStruct4k(gbeStruct8k.main, romName, "main"); printGbeChecksumDataFromStruct4k(gbeStruct8k.backup, romName, "backup"); - + return; } diff --git a/projects/ich9gen/sources/src/gbe/gbe.h b/projects/ich9gen/sources/src/gbe/gbe.h index a1350fdd..14548e71 100644 --- a/projects/ich9gen/sources/src/gbe/gbe.h +++ b/projects/ich9gen/sources/src/gbe/gbe.h @@ -18,21 +18,21 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + /* * Purpose: provide struct representing gbe region. * Map actual buffers of this regions, directly to instances of these * structs. This makes working with gbe really easy. */ - + /* * bit fields used, corresponding to datasheet. See links to datasheets * and documentation in ich9deblob.c */ - + /* * See docs/hardware/x200_remove_me.html for info plus links to datasheet (also linked below) - * + * * Info about Gbe region (read whole datasheet): * http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf * https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums @@ -49,14 +49,14 @@ /* Size of the full gbe region in bytes */ #define GBEREGIONSIZE_8K 0x2000 /* - * Size of each sub-region in gbe. + * Size of each sub-region in gbe. * gbe contains two regions which * can be identical: main and backup. * These are each half the size of the full region */ #define GBEREGIONSIZE_4K 0x1000 -/* +/* * When adding up the first 0x3F 16-bit words * in a 4KiB GBE region, it should be equal * to 0xBABA @@ -74,7 +74,7 @@ * --------------------------------------------------------------------- * Gbe struct representing the data: * --------------------------------------------------------------------- - */ + */ struct GBE_RESERVED_WORD_03H { /* least significant bits */ @@ -147,17 +147,17 @@ struct GBE_EXTENDED_CONFIGURATION_CONTROL_WORD_2 { /* * Word 17h: LED 1 Configuration and Power Management - * + * * Default values for LEDCTL register fields controlling LED1 (LINK_1000) * output behaviours and OEM fields that define PHY power management * parameters loaded to the PHY_CTRL register. */ struct LED_CTL_1 { /* least significant bits */ - + /* See page 16 in the datasheet to show the different modes. deblobbed_descriptor.bin has "ACTIVITY" mode set */ uint8_t led1Mode : 4; /* Default value 0111 (bin) 7 (hex) says datasheet. 1011 (bin) B (hex) according to deblobbed_descriptor.bin */ - + uint8_t reserved1 : 1; /* Reserved. Should be 0 according to datasheet and deblobbed_descriptor.bin */ uint8_t led1BlinkMode : 1; /* 0 = slow blink, 1 = fast blink. should be identical to led0 blink mode. Default is 0 according to datasheet and deblobbed_descriptor.bin */ /* By setting this and led0 blink mode (see word 18h) to 1, you could enable a faster blinking on the LED's where the ethernet cable goes @@ -175,26 +175,26 @@ struct LED_CTL_1 { /* most significant bits */ }; -/* +/* * Word 18: LED 0 and 2 Configuration Defaults - * + * * Hardware defaults for LEDCTL register fields controlling LED0 (LINK/ACTIVITY) * and LED2 (LINK_100) output behaviours. */ struct LED_CTL_02 { /* least significant bits */ - + /* see page 16 in datasheet to show the different modes. deblobbed_descriptor has "LINK-UP" mode set */ uint8_t led0Mode : 4; /* default value 0100 (bin) or 4 (hex) according to datasheet. It's 0010 (bin) or 2 (hex) according to deblobbed_descriptor.bin */ - + uint8_t reserved1 : 1; /* Reserved. Should be set to 0 according to datasheet and deblobbed_descriptor.bin */ uint8_t led0BlinkMode : 1; /* This should be the same as led1BlinkMode (see word 17h). Default is 0 according to datasheet and deblobbed_descriptor.bin */ uint8_t led0Invert : 1; /* initial value of LED0_IVRT field. 0 = led0 has active low output, 1 is high active output. Default is 0 according to datasheet and deblobbed_descriptor.bin */ uint8_t led0Blink : 1; /* LED0_BLINK field. Should be 0 according to datasheet and deblobbed_descriptor.bin */ - + /* see page 16 in datasheet to shew the different modes. deblobbed_descriptor has "LINK_100" mode set */ uint8_t led2Mode : 4; /* default value 0110 (bin) or 6 (hex) according to datasheet and deblobbed_descriptor.bin */ - + uint8_t reserved2 : 1; /* Reserved. Should be 0 according to datasheet and deblobbed_descriptor.bin */ uint8_t led2BlinkMode : 1; /* 0 = slow blink. 1 = fast. default 0 according to datasheet and deblobbed_descriptor.bin */ uint8_t led2Invert : 1; /* LED2_IVRT field. Should be 0 according to datasheet and deblobbed_descriptor.bin */ @@ -218,7 +218,7 @@ struct GBE_PXE_BOOT_AGENT_MAIN_SETUP_OPTIONS { uint8_t efiPresence : 1; /* 1 means that an EFI image is present (0 means not present). deblobbed_descriptor.bin says 0. if 1, eeprom word 33h (efi version) becomes valid. if pxePresent is 1, that means EFI and PXE are both present.*/ uint8_t pxePresence : 1; /* 0 means that a PXE image is present. 1 means to pxe present. deblobbed_descriptor.bin says 0. if 0, then word 32h (PXE version) in eeprom becomes valid */ /* most significant bits */ - + /* This whole data structure is pointless, since libreboot doesn't (read: won't) * include the proprietary intel boot agent. Struct exists here simply for documentations sake. */ }; @@ -232,18 +232,18 @@ struct GBE_PXE_BOOT_AGENT_CONFIGURATION_CUSTOMIZATION_OPTIONS_31H { uint8_t disableLegacyWakeupSupport : 1; /* 1 means no changes in legacy wakeup support menu is allowed. default is 0, and deblobbed_descriptor.bin says 0 */ uint8_t disableFlashUpdate : 1; /* 1 means no changes to flash image using PROset is allowed. default is 0, and deblobbed_descriptor.bin says 0 */ uint8_t reserved1 : 2; /* Reserved. Datasheet says these must be 0, and deblobbed_descriptor.bin sets them to 0. */ - + /* * deblobbed_descriptor says 000 * 000 = normal behaviour * see datasheet (page 21) for other modes. */ uint8_t ibaBootOrderSetupMode : 3; - + uint8_t reserved2 : 3; /* Reserved. Datasheet says these must be set to 0, and deblobbed_descriptor.bin sets them to 0. */ uint8_t signature : 2; /* Must be set to 01 to indicate that this whole word has been configured by the agent or other software. deblobbed_descriptor.bin says 01. */ /* most significant bits */ - + /* This whole data structure is pointless, since libreboot doesn't (read: won't) * include the proprietary intel boot agent. Struct exists here simply for documentations sake. */ }; @@ -254,7 +254,7 @@ struct GBE_PXE_BOOT_AGENT_CONFIGURATION_CUSTOMIZATION_OPTIONS_32H { uint8_t minorVersionNumber : 4; /* PXE boot agent minor number. default is 2 (hex). deblobbed_descriptor.bin says 3 (hex) */ uint8_t majorVersionNumber : 4; /* PXE boot agent major number. default is F (hex). deblobbed_descriptor.bin says 1 (hex) */ /* most significant bits */ - + /* This whole data structure is pointless, since libreboot doesn't (read: won't) * include the proprietary intel boot agent. Struct exists here simply for documentations sake. */ }; @@ -269,7 +269,7 @@ struct GBE_PXE_IBA_CAPABILITIES { uint8_t reserved2_1 : 6; /* ^ part of reserved2_0. split this way so that the bitfields align */ uint8_t signature : 2; /* must be 01 to indicate that the word is configured by the agent or other software. deblobbed_descriptor.bin says 01 */ /* most significant bits */ - + /* This whole data structure is pointless, since libreboot doesn't (read: won't) * include the proprietary intel boot agent. Struct exists here simply for documentations sake. */ }; @@ -279,14 +279,14 @@ struct GBE_PXE_SOFTWARE_REGION { struct GBE_PXE_BOOT_AGENT_CONFIGURATION_CUSTOMIZATION_OPTIONS_31H bootAgentConfigurationCustomizationOptions31h; /* Word 31h */ struct GBE_PXE_BOOT_AGENT_CONFIGURATION_CUSTOMIZATION_OPTIONS_32H bootAgentConfigurationCustomizationOptions32h; /* Word 32h */ struct GBE_PXE_IBA_CAPABILITIES ibaCapabilities; /* Word 33h */ - + /* Words 34h to 3Eh (padding). Set these to 0xFFFF (according to deblobbed_descriptor.bin) */ uint16_t paddingWords34hTo3Eh[11]; - + /* * the pxe software region is practically useless in libreboot, since - * libreboot does not include the intel boot agent (it's proprietary software). - * + * libreboot does not include the intel boot agent (it's proprietary software). + * * Having this struct in place is simply for documentations sake. It is completely * irrelevant what you put here. filling it with 0xFFFF would probably be fine. */ @@ -301,90 +301,90 @@ struct GBEREGIONRECORD_4K { /* * Word 08 and 09 (pba low and pba high): - * + * * Both of these should be set to 0xFFFF by default, according to the datasheet. * "nine digit printed board assembly (PBA) number" for intel cards to be stored - * in a 4 byte (read: 2 word) field. - * + * in a 4 byte (read: 2 word) field. + * * Example: if pba number is 123456-003, then word 08 should be 1234h and word 09 becomes 5603. * Note: 1234 and 5603 above are big endian. In the image it would actually be 34 12 and 0356 - * + * * Example: in mine it was (in the image): 08 10 FF FF. That becomes 1008h and FFFFh, or * basically: 1008FF-0FF. The same was observed in another. - * + * * Setting it to FF FF FF FF should be fine, according to the datasheet. */ uint16_t pbaLow; /* Word 08. Set it to 0x1008 (according to deblobbed_descriptor.bin). */ uint16_t pbaHigh; /* Word 09. Set it to 0xFFFF (according to deblobbed_descriptor.bin). */ - + /* Word 0A */ struct GBE_PCI_INITIALIZATION_CONTROL_WORD pciInitializationControlWord; - - /* + + /* * Word 0B; subsystem ID - * + * * If load subsystem ID bit of word 0A (pci init control word) is * set to 1 (read: it is. in my deblobbed_descriptor.bin), store * the subsystem id here. Datasheet says that the default value is * 0000h, but you should set this to 20EEh (little endian: EE 20) */ uint16_t subsystemId; /* Set this to 0x20EE */ - + /* * Word 0C; subsystem vendor ID - * + * * If load subsystem vendor ID bit of word 0A (pci init control word) * is set to 1 (read: it is. in my deblobbed_descriptor.bin), store - * the subsystem vendor id here. Datasheet says that the default + * the subsystem vendor id here. Datasheet says that the default * value is 8086h, but you should set this to 17AAh (lendian: AA 17). */ uint16_t subsystemVendorId; /* Set this to 0x17AA */ - - /* + + /* * Word 0D: device ID - * + * * If load vendor/device ID in word 0A (pci init control word) is 1 * (it is) then this word is used to init device id using word 21h, * 1Eh or 1Fh. In my case, deviceId is 0x10F5. Word 21h is set to * 0x10CB, word 1Eh is 0x10F5 and 1Fh is 0x10BF - * + * * The datasheet says that 10F5 is for Intel 82567LM gigabit ethernet * controller; 10BF is for Intel 82567LF and 10CB is for Intel 82567V. - * + * * Based on this, the X200 is shown to have the Intel 82567LM ethernet * controller. */ uint16_t deviceId; /* Set this to 0x10F5. */ /* It is important that this is correct, for the linux kernel driver */ - - /* + + /* * Word 0E: vendor ID - * + * * If load vendor/device ID in word 0A (pci init control) is 1 (it is), * then this word used read to initialize the PCI vendor ID. Default - * value is 8086 according to datasheets, and deblobbed_descriptor.bin. - * + * value is 8086 according to datasheets, and deblobbed_descriptor.bin. + * * Intel is often 8086 as a PCI vendor ID. Because 8086. As in the CPU architecture. */ uint16_t vendorId; - + uint16_t deviceRevId; /* Word 0F: reserved bits. Set all bits to 0. */ struct GBE_LAN_POWER_CONSUMPTION lanPowerConsumption; /* Word 10: LAN Power Consumption (see struct definition) */ uint16_t reservedWords11h12h[2]; /* Words 11-12: Reserved. Set both of them to 0x0000 (according to datasheet). */ - + /* Word 13: Shared Initialization Control Word */ struct GBE_SHARED_INITIALIZATION_CONTROL_WORD sharedInitializationControlWord; - + /* Word 14: Extended Configuration Control Word 1 */ struct GBE_EXTENDED_CONFIGURATION_CONTROL_WORD_1 extendedConfigurationControlWord1; - + /* Word 15: Extended Configuration Control Word 2 */ struct GBE_EXTENDED_CONFIGURATION_CONTROL_WORD_2 extendedConfigurationControlWord2; - + /* Word 16: Extended Configuration Control Word 3 */ /* All bits reserved. Datasheet and deblobbed_descriptor.bin say to set it to zero */ uint16_t extendedConfigurationControlWord3; - + struct LED_CTL_1 ledCtl1; /* Word 17: LED 1 Configuration and Power Management */ struct LED_CTL_02 ledCtl02; /* Word 18: LED 0 and 2 Configuration Defaults */ uint16_t reservedWord19h; /* Word 19: Reserved. Default is 0x2B00 according to datasheet, but in deblobbed_descriptor.bin it is 0x2B40 */ @@ -401,16 +401,16 @@ struct GBEREGIONRECORD_4K { uint16_t reservedWords24to2Fh[12]; /* Words 24-2F: Reserved. These should all be 0x0000 according to datasheet and deblobbed_descriptor.bin */ struct GBE_PXE_SOFTWARE_REGION pxeSoftwareRegion; /* Words 30-3E: PXE Software Region */ uint16_t checkSum; /* when added to the sum of all words above, this should match GBECHECKSUMTOTAL */ - + /* set all bytes in here to 0xFF */ uint8_t padding[3968]; }; -/* main and backup region in gbe */ +/* main and backup region in gbe */ struct GBEREGIONRECORD_8K { struct GBEREGIONRECORD_4K main; struct GBEREGIONRECORD_4K backup; - /* + /* * Backup region: * This is actually "main" on X200, since the real main has a bad checksum * and other errors. You should do what you need on this one (if modifying @@ -423,7 +423,7 @@ struct GBEREGIONRECORD_8K { * Function declarations (keep gcc/make happy. check them in gbe.c) * --------------------------------------------------------------------- */ - + uint16_t gbeGetChecksumFrom4kBuffer(uint16_t* gbeWord, uint16_t desiredValue, int gbeRegionBase); uint16_t gbeGetChecksumFrom4kStruct(struct GBEREGIONRECORD_4K gbeStruct4k, uint16_t desiredValue); struct GBEREGIONRECORD_8K deblobbedGbeStructFromFactory(struct GBEREGIONRECORD_8K factoryGbeStruct8k); diff --git a/projects/ich9gen/sources/src/ich9deblob.c b/projects/ich9gen/sources/src/ich9deblob.c index d79a3a89..b9153ed6 100644 --- a/projects/ich9gen/sources/src/ich9deblob.c +++ b/projects/ich9gen/sources/src/ich9deblob.c @@ -1,7 +1,7 @@ /* * ich9deblob.c * This file is part of the ich9deblob utility from the libreboot project - * + * * Purpose: disable and remove the ME from ich9m/gm45 systems in coreboot. * * Copyright (C) 2014 Steve Shenton @@ -20,26 +20,26 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + /* Initially based on proof of concept by Steve Shenton. */ /* Original utility can be found at https://gitorious.org/ich9descriptortool */ - + /* - * Read a factory.rom dump (ich9m/gm45 systems) and + * Read a factory.rom dump (ich9m/gm45 systems) and * modify the flash descriptor to remove all regions except descriptor, * Gbe and BIOS. Set BIOS region to full size of the ROM image (after * the flash descriptor and gbe). Basically, deblob the descriptor. - * + * * This will will generate a concatenated descriptor+gbe dump suitable * for use in libreboot. Currently tested: ThinkPad X200 (coreboot/libreboot) */ - + /* * See docs/hardware/x200_remove_me.html for info plus links to datasheet (also linked below) - * + * * Info about flash descriptor (read page 845 onwards): * http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datasheet.pdf - * + * * Info about Gbe region (read whole datasheet): * http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf * https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums @@ -51,18 +51,18 @@ int main() { struct DESCRIPTORREGIONRECORD descriptorStruct; uint8_t* descriptorBuffer = (uint8_t*)&descriptorStruct; - + struct GBEREGIONRECORD_8K gbeStruct8k; uint8_t* gbeBuffer8k = (uint8_t*)&gbeStruct8k; uint32_t gbeRegionStart; - + char* romFilename = "factory.rom"; char* descriptorGbeFilename = "deblobbed_descriptor.bin"; char* descriptorNoGbeFilename = "deblobbed_4kdescriptor.bin"; - + unsigned int bufferLength; unsigned int romSize; - + /* * ------------------------------------------------------------------ * Compatibility checks. This version of ich9deblob is not yet portable. @@ -71,7 +71,7 @@ int main() if (systemOrCompilerIncompatible(descriptorStruct, gbeStruct8k)) return 1; /* If true, fail with error message */ - + /* * ------------------------------------------------------------------ * Extract the descriptor and gbe regions from the factory.rom dump @@ -86,20 +86,20 @@ int main() return 1; } printf("\n%s opened successfully\n", romFilename); - - /* + + /* * Get the descriptor region dump from the factory.rom * (goes in factoryDescriptorBuffer variable) */ bufferLength = fread(descriptorBuffer, 1, DESCRIPTORREGIONSIZE, fp); - if (DESCRIPTORREGIONSIZE != bufferLength) // + if (DESCRIPTORREGIONSIZE != bufferLength) // { printf("\nerror: could not read descriptor from %s (%i) bytes read\n", romFilename, bufferLength); fclose(fp); return 1; } printf("\ndescriptor region read successfully\n"); - + if (descriptorDefinesGbeRegion(descriptorStruct)) { gbeRegionStart = descriptorStruct.regionSection.flReg3.BASE << FLREGIONBITSHIFT; @@ -125,13 +125,13 @@ int main() printf("\n%s size: [%i] bytes\n", romFilename, romSize); fclose(fp); - + /* Debugging (before modification) */ printDescriptorRegionLocations(descriptorStruct, "Original"); - if (descriptorDefinesGbeRegion(descriptorStruct)) + if (descriptorDefinesGbeRegion(descriptorStruct)) printGbeChecksumDataFromStruct8k(gbeStruct8k, "Original"); else printf("NO GBE REGION\n"); - + /* * ------------------------------------------------------------------ * Modify the descriptor and gbe regions, ready to go in libreboot.rom @@ -179,7 +179,7 @@ int main() return 1; } } - + /* * ------------------------------------------------------------------ * Generate ich9gen data (C code that will recreate the deblobbed descriptor+gbe from scratch) @@ -205,7 +205,7 @@ int main() return 1; } } - + if (descriptorDefinesGbeRegion(descriptorStruct)) { printf("The modified descriptor and gbe regions have also been dumped as src files: mkdescriptor.c, mkdescriptor.h, mkgbe.c, mkgbe.h\n"); diff --git a/projects/ich9gen/sources/src/ich9deblob.h b/projects/ich9gen/sources/src/ich9deblob.h index c11ea290..e00b2c66 100644 --- a/projects/ich9gen/sources/src/ich9deblob.h +++ b/projects/ich9gen/sources/src/ich9deblob.h @@ -1,7 +1,7 @@ /* * ich9deblob.h * This file is part of the ich9deblob utility from the libreboot project - * + * * Purpose: header file for ich9deblob.c * * Copyright (C) 2014 Steve Shenton @@ -20,7 +20,7 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + #ifndef ICH9DEBLOB_H #define ICH9DEBLOB_H diff --git a/projects/ich9gen/sources/src/ich9gen.c b/projects/ich9gen/sources/src/ich9gen.c index b3a2c9f1..4d1e767e 100644 --- a/projects/ich9gen/sources/src/ich9gen.c +++ b/projects/ich9gen/sources/src/ich9gen.c @@ -15,16 +15,16 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + /* Generate deblobbed descriptor and gbe 12KiB file from scratch * without relying on a factory.rom dump */ - + #include "ich9gen.h" -int main(int argc, char *argv[]) +int main(int argc, char *argv[]) { int i, j; - + struct GBEREGIONRECORD_8K gbeStruct8k = generatedGbeStruct8k(); struct DESCRIPTORREGIONRECORD descriptorStruct4M = generatedDescriptorStruct(ROMSIZE_4MB, WITHGBE); struct DESCRIPTORREGIONRECORD descriptorStruct8M = generatedDescriptorStruct(ROMSIZE_8MB, WITHGBE); @@ -32,11 +32,11 @@ int main(int argc, char *argv[]) struct DESCRIPTORREGIONRECORD descriptorStructNoGbe4M = generatedDescriptorStruct(ROMSIZE_4MB, WITHOUTGBE); struct DESCRIPTORREGIONRECORD descriptorStructNoGbe8M = generatedDescriptorStruct(ROMSIZE_8MB, WITHOUTGBE); struct DESCRIPTORREGIONRECORD descriptorStructNoGbe16M = generatedDescriptorStruct(ROMSIZE_16MB, WITHOUTGBE); - + /* Only for the compatibility checks */ struct DESCRIPTORREGIONRECORD dummyDescriptorStruct; struct GBEREGIONRECORD_8K dummyGbeStruct8k; - + /* * ------------------------------------------------------------------ * Compatibility checks. This version of ich9deblob is not yet portable. @@ -45,19 +45,19 @@ int main(int argc, char *argv[]) if (systemOrCompilerIncompatible(dummyDescriptorStruct, dummyGbeStruct8k)) return 1; /* If true, fail with error message */ - + /* * ------------------------------------------------------------------ * Arguments given on the terminal * ------------------------------------------------------------------ */ - + if(argc==3) { - + /* If user provides their own MAC address, it will be used. - * Otherwise, ich9gen will simply use the default one. - * + * Otherwise, ich9gen will simply use the default one. + * * However, if the user provides an invalid MAC address, then ich9gen * will exit. */ if(0==strcmp(argv[1],"--macaddress")) { @@ -74,7 +74,7 @@ int main(int argc, char *argv[]) } for(i=0; i<6; i++) { gbeStruct8k.main.macAddress[i] = 0; - + /* Go through each nibble of the byte */ for(j=0; j<2; j++) { if(argv[2][(i*3)+j]>='a' && argv[2][(i*3)+j]<='f') @@ -92,7 +92,7 @@ int main(int argc, char *argv[]) gbeStruct8k.main.checkSum = gbeGetChecksumFrom4kStruct(gbeStruct8k.main, GBECHECKSUMTOTAL); /* Fix the checksum */ memcpy(&gbeStruct8k.backup, &gbeStruct8k.main, GBEREGIONSIZE_4K); /* Copy to the backup */ - + /* Generate ich9gen data (C code for Gbe region): */ /* mkgbe.h */ @@ -102,29 +102,29 @@ int main(int argc, char *argv[]) if (notCreatedCFileFromGbeStruct4k(gbeStruct8k.backup, "mkgbe.c", "mkgbe.h")) { return 1; } - + printf("You selected to change the MAC address in the Gbe section. This has been done.\n\n"); - + printf("The modified gbe region has also been dumped as src files: mkgbe.c, mkgbe.h\n"); printf("To use these in ich9gen, place them in src/ich9gen/ and re-build ich9gen.\n\n"); } - + } - + /* * ------------------------------------------------------------------ * Generate the 12KiB files, ready to be used in a libreboot image * ------------------------------------------------------------------ */ - + if (notCreatedDescriptorGbeFile(descriptorStruct4M, gbeStruct8k, "ich9fdgbe_4m.bin")) { return 1; } - + if (notCreatedDescriptorGbeFile(descriptorStruct8M, gbeStruct8k, "ich9fdgbe_8m.bin")) { return 1; } - + if (notCreatedDescriptorGbeFile(descriptorStruct16M, gbeStruct8k, "ich9fdgbe_16m.bin")) { return 1; } @@ -134,15 +134,15 @@ int main(int argc, char *argv[]) * In these descriptors, the onboard Intel GbE NIC is disabled; a discrete one is used instead * ------------------------------------------------------------------ */ - + if (notCreated4kDescriptorFile(descriptorStructNoGbe4M, "ich9fdnogbe_4m.bin")) { return 1; } - + if (notCreated4kDescriptorFile(descriptorStructNoGbe8M, "ich9fdnogbe_8m.bin")) { return 1; } - + if (notCreated4kDescriptorFile(descriptorStructNoGbe16M, "ich9fdnogbe_16m.bin")) { return 1; } diff --git a/projects/ich9gen/sources/src/ich9gen.h b/projects/ich9gen/sources/src/ich9gen.h index 6b346b06..c558e04a 100644 --- a/projects/ich9gen/sources/src/ich9gen.h +++ b/projects/ich9gen/sources/src/ich9gen.h @@ -14,9 +14,9 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see . */ - + /* Header file for ich9gen.c */ - + #ifndef ICH9GEN_H #define ICH9GEN_H diff --git a/projects/ich9gen/sources/src/ich9gen/mkdescriptor.c b/projects/ich9gen/sources/src/ich9gen/mkdescriptor.c index 3b97a97b..09669ccf 100644 --- a/projects/ich9gen/sources/src/ich9gen/mkdescriptor.c +++ b/projects/ich9gen/sources/src/ich9gen/mkdescriptor.c @@ -226,4 +226,3 @@ struct DESCRIPTORREGIONRECORD generatedDescriptorStruct(unsigned int romSize, in return descriptorStruct; } - diff --git a/projects/ich9gen/sources/src/ich9gen/mkgbe.c b/projects/ich9gen/sources/src/ich9gen/mkgbe.c index d6865823..099ab5b7 100644 --- a/projects/ich9gen/sources/src/ich9gen/mkgbe.c +++ b/projects/ich9gen/sources/src/ich9gen/mkgbe.c @@ -254,4 +254,3 @@ struct GBEREGIONRECORD_8K generatedGbeStruct8k() memcpy(&gbeStruct8k.backup, &gbeStruct8k.main, GBEREGIONSIZE_4K); return gbeStruct8k; } - -- cgit v1.2.3-70-g09d2 From e1947a9aa497c4b4bc45b7a6cd5878d06aa6eb90 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Mon, 15 Jan 2018 21:49:26 -0500 Subject: Make 'all', 'clean' phony targets in ich9gen Makefile --- projects/ich9gen/sources/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/projects/ich9gen/sources/Makefile b/projects/ich9gen/sources/Makefile index e16b63f0..ba4e53f9 100644 --- a/projects/ich9gen/sources/Makefile +++ b/projects/ich9gen/sources/Makefile @@ -22,6 +22,8 @@ FORCEC99=-std=c99 CFLAGS=-I. -Wall -Wextra -g $(FORCEC99) NOLINKER=-c +.PHONY: all clean + all: ich9deblob ich9gen demefactory ich9deblob: obj/ich9deblob.o obj/common/descriptor_gbe.o \ -- cgit v1.2.3-70-g09d2 From 2b3d79217ea2fe6068adb0453eadde107ea42822 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Mon, 15 Jan 2018 21:50:21 -0500 Subject: Add project ich9gen action scripts --- projects/ich9gen/ich9gen | 107 ++++++++++++++++++++++++++++++++++++++++ projects/ich9gen/ich9gen-helper | 22 +++++++++ 2 files changed, 129 insertions(+) create mode 100755 projects/ich9gen/ich9gen create mode 100755 projects/ich9gen/ich9gen-helper diff --git a/projects/ich9gen/ich9gen b/projects/ich9gen/ich9gen new file mode 100755 index 00000000..71567329 --- /dev/null +++ b/projects/ich9gen/ich9gen @@ -0,0 +1,107 @@ +#!/usr/bin/env bash + +# Copyright (C) 2016 Paul Kocialkowski +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +arguments() { + project_arguments_targets "$project" "$@" +} + +usage() { + project_usage_actions "$project" + project_usage_arguments "$project" "$@" +} + +extract() { + local repository="$project" + + project_extract "$project" "$@" +} + +extract_check() { + local repository="$project" + + project_extract_check "$project" "$@" +} + +update() { + local repository="$project" + + project_update_git "$project" "$repository" "$@" +} + +update_check() { + local repository="$project" + + project_update_check_git "$project" "$repository" "$@" +} + +build() { + local repository="$project" + + project_sources_directory_missing_empty_error "$project" "$repository" "$@" + + if git_project_check "$repository"; then + git_project_checkout "$project" "$repository" "$@" + fi + + local sources_path="$(project_sources_path "$project" "$repository" "$@")" + + local build_path="$(project_build_path "$project" "$@")" + + mkdir -p "$build_path" + make -C "$sources_path" -j"$TASKS" ich9gen + + ( + local macaddress="$(ich9gen_macaddress)" + + cd "$build_path" + + if [[ -n $macaddress ]]; then + "$sources_path"/ich9gen --macaddress "$macaddress" + else + "$sources_path"/ich9gen + fi + ) + + cp "$sources_path/ich9gen" "$build_path" + make -C "$sources_path" clean +} + +build_check() { + project_build_check "$project" "$@" +} + +install() { + project_install "$project" "$@" +} + +install_check() { + project_install_check "$project" "$@" +} + +release() { + project_release_install_archive "$project" "$TOOLS" "$@" + project_release_sources_archive_create "$project" "$@" +} + +release_check() { + project_release_install_archive_check "$project" "$TOOLS" "$@" + project_release_sources_archive_exists_check "$project" "$@" +} + +clean() { + project_clean "$project" "$@" +} diff --git a/projects/ich9gen/ich9gen-helper b/projects/ich9gen/ich9gen-helper new file mode 100755 index 00000000..d97af0af --- /dev/null +++ b/projects/ich9gen/ich9gen-helper @@ -0,0 +1,22 @@ +#!/usr/bin/env bash + +# Copyright (C) 2018 Andrew Robbins +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +MACADDRESS='macaddress' + +ich9gen_macaddress() { + project_file_contents "$project" "$CONFIGS" "$MACADDRESS" "$@" +} -- cgit v1.2.3-70-g09d2 From b278ccc7fe3a82124e50f7aad62cbd5099602a3a Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Tue, 16 Jan 2018 16:21:05 -0500 Subject: Add project ich9gen install, macaddress files The file 'macaddress' is expected to contain a correctly formed MAC address to be compiled into the descriptor binary generated by ich9gen. The file is optional and poses no issue if not present, however, as ich9gen will simply insert its own default in that case. --- projects/ich9gen/configs/install | 9 +++++++++ projects/ich9gen/configs/macaddress | 1 + 2 files changed, 10 insertions(+) create mode 100644 projects/ich9gen/configs/install create mode 100644 projects/ich9gen/configs/macaddress diff --git a/projects/ich9gen/configs/install b/projects/ich9gen/configs/install new file mode 100644 index 00000000..ef6e0b0e --- /dev/null +++ b/projects/ich9gen/configs/install @@ -0,0 +1,9 @@ +ich9fdgbe_4m.bin:ich9fdgbe_4m.bin +ich9fdgbe_8m.bin:ich9fdgbe_8m.bin +ich9fdgbe_16m.bin:ich9fdgbe_16m.bin +ich9fdnogbe_4m.bin:ich9fdnogbe_4m.bin +ich9fdnogbe_8m.bin:ich9fdnogbe_8m.bin +ich9fdnogbe_16m.bin:ich9fdnogbe_16m.bin +ich9gen:ich9gen +mkgbe.c:mkgbe.c +mkgbe.h:mkgbe.h diff --git a/projects/ich9gen/configs/macaddress b/projects/ich9gen/configs/macaddress new file mode 100644 index 00000000..ed828f94 --- /dev/null +++ b/projects/ich9gen/configs/macaddress @@ -0,0 +1 @@ +00:f5:f0:40:71:fe -- cgit v1.2.3-70-g09d2 From c41a8105bca5d1e0b793ef85624ddad1d229782d Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Tue, 16 Jan 2018 16:25:54 -0500 Subject: Change default Libreboot MAC address This only affects the GM45-based systems (e.g., X200, T400, etcetera) and GA-G41M-ES2L board as they require an MAC address hardcoded into the ROM for their integrated NIC to function. The new default MAC address is now '00:4c:69:62:72:65' (Libre). Credit goes to specing from the #libreboot IRC channel for coming up with it. --- projects/coreboot/configs/seabios/ga-g41m-es2l/config | 2 +- projects/ich9gen/configs/macaddress | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/coreboot/configs/seabios/ga-g41m-es2l/config b/projects/coreboot/configs/seabios/ga-g41m-es2l/config index ba81aa1d..3393ce2a 100644 --- a/projects/coreboot/configs/seabios/ga-g41m-es2l/config +++ b/projects/coreboot/configs/seabios/ga-g41m-es2l/config @@ -426,7 +426,7 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_DRIVERS_LENOVO_WACOM is not set # CONFIG_CACHE_MRC_SETTINGS is not set CONFIG_REALTEK_8168_RESET=y -CONFIG_REALTEK_8168_MACADDRESS="00:f5:f0:40:71:fe" +CONFIG_REALTEK_8168_MACADDRESS="00:4c:69:62:72:65" # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set CONFIG_SPI_FLASH=y diff --git a/projects/ich9gen/configs/macaddress b/projects/ich9gen/configs/macaddress index ed828f94..2ca03841 100644 --- a/projects/ich9gen/configs/macaddress +++ b/projects/ich9gen/configs/macaddress @@ -1 +1 @@ -00:f5:f0:40:71:fe +00:4c:69:62:72:65 -- cgit v1.2.3-70-g09d2 From f3aaf856cc37521d272666927a0d855ff862efd5 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 18 Jan 2018 17:49:06 -0500 Subject: Don't bother checking for git repo in bucts source bucts' sources are kept in its project directory which means we can skip checking for a git repository and instead skip straight to creating the sources archive when releasing images/sources. i.e., project_release_sources_git() called git_project_check() with 'bucts' as an argument, wasting time and resources looking in $root/$SOURCES/bucts (which doesn't exist) and ultimately concluding that the assumed location of bucts' sources isn't a git repository (which is true). We can avoid that circumlocution by simply calling project_release_sources_archive_create() instead of project_release_sources_git() within the release() and release_check() actions. --- projects/bucts/bucts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/bucts/bucts b/projects/bucts/bucts index 4b5d81bb..4eea684a 100644 --- a/projects/bucts/bucts +++ b/projects/bucts/bucts @@ -83,14 +83,14 @@ release() { local repository="$project" project_release_install_archive "$project" "$TOOLS" "$@" - project_release_sources_git "$project" "$repository" "$@" + project_release_sources_archive_create "$project" "$@" } release_check() { local repository="bucts" project_release_install_archive_check "$project" "$TOOLS" "$@" - project_release_check_sources_git "$project" "$repository" "$@" + project_release_sources_archive_exists_check "$project" "$@" } clean() { -- cgit v1.2.3-70-g09d2 From d91ed38eb8b1fed0b20e1a8d89bf57b7ab8f5ec9 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 18 Jan 2018 17:54:19 -0500 Subject: Remove unnecessary bucts targets file There's no difference between the 'generic' and 'lenovobios' bucts and simply wastes time compiling another bucts binary for no gain. If in the future such a distinction makes sense, the targets file can be re-added. --- projects/bucts/configs/targets | 2 -- 1 file changed, 2 deletions(-) delete mode 100644 projects/bucts/configs/targets diff --git a/projects/bucts/configs/targets b/projects/bucts/configs/targets deleted file mode 100644 index 915652d5..00000000 --- a/projects/bucts/configs/targets +++ /dev/null @@ -1,2 +0,0 @@ -generic -lenovobios -- cgit v1.2.3-70-g09d2 From 6699fa40dbae37246e22e384749cfac52e9a9e81 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 18 Jan 2018 18:18:11 -0500 Subject: Bump memtest86plus revision to pull in test #7 fix --- projects/memtest86plus/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/memtest86plus/configs/revision b/projects/memtest86plus/configs/revision index 8b866a4f..9f2728ba 100644 --- a/projects/memtest86plus/configs/revision +++ b/projects/memtest86plus/configs/revision @@ -1 +1 @@ -686a6739e5e0020262b45ad6e45795e7b1b7b67c +5ca4eb9544e51254254d09ae6e70f93403469ec3 -- cgit v1.2.3-70-g09d2 From b5e4d86fee0193ff24f39eee7a52b594040194cf Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 18 Jan 2018 18:30:48 -0500 Subject: Bump Coreboot revision to pull in X200 dock patch --- projects/coreboot/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/revision b/projects/coreboot/configs/revision index 6f2c9f24..24940261 100644 --- a/projects/coreboot/configs/revision +++ b/projects/coreboot/configs/revision @@ -1 +1 @@ -ceeafa45cae26ab857687082e02eae40d9621291 +a17796e6012041e2d8ebe16b0bde0b99809ee87c -- cgit v1.2.3-70-g09d2 From c1eb3cc6170226b6ef73a5191fe7707607276d40 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 18 Jan 2018 19:58:06 -0500 Subject: Update Coreboot config for board d510mo This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/d510mo/config | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/coreboot/configs/seabios/d510mo/config b/projects/coreboot/configs/seabios/d510mo/config index 1000508c..cf8d27f6 100644 --- a/projects/coreboot/configs/seabios/d510mo/config +++ b/projects/coreboot/configs/seabios/d510mo/config @@ -141,6 +141,7 @@ CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_BOARD_INTEL_D510MO=y # CONFIG_BOARD_INTEL_D810E2CB is not set # CONFIG_BOARD_INTEL_D945GCLF is not set +# CONFIG_BOARD_INTEL_DCP847SKE is not set # CONFIG_BOARD_INTEL_DG43GT is not set # CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set @@ -162,6 +163,7 @@ CONFIG_BOARD_INTEL_D510MO=y # CONFIG_BOARD_INTEL_TRUXTON is not set # CONFIG_BOARD_INTEL_WTM2 is not set CONFIG_DRIVERS_UART_8250IO=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO" # CONFIG_BOARD_INTEL_BASEBOARD_GLKRVP is not set CONFIG_CPU_ADDR_BITS=32 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 @@ -437,7 +439,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set CONFIG_SPI_FLASH=y @@ -580,7 +581,6 @@ CONFIG_COMMON_FADT=y # CONFIG_GENERATE_MP_TABLE is not set # CONFIG_GENERATE_PIRQ_TABLE is not set CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO" # # Payload -- cgit v1.2.3-70-g09d2 From cb743c7f5f550383af562355c8e0f28b69e2f1da Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 18 Jan 2018 20:00:02 -0500 Subject: Update Coreboot config for board d945gclf This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/d945gclf/config | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/coreboot/configs/seabios/d945gclf/config b/projects/coreboot/configs/seabios/d945gclf/config index b009e240..1f2d39b7 100644 --- a/projects/coreboot/configs/seabios/d945gclf/config +++ b/projects/coreboot/configs/seabios/d945gclf/config @@ -145,6 +145,7 @@ CONFIG_TTYS0_LCS=3 # CONFIG_BOARD_INTEL_D510MO is not set # CONFIG_BOARD_INTEL_D810E2CB is not set CONFIG_BOARD_INTEL_D945GCLF=y +# CONFIG_BOARD_INTEL_DCP847SKE is not set # CONFIG_BOARD_INTEL_DG43GT is not set # CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set @@ -166,6 +167,7 @@ CONFIG_BOARD_INTEL_D945GCLF=y # CONFIG_BOARD_INTEL_TRUXTON is not set # CONFIG_BOARD_INTEL_WTM2 is not set CONFIG_DRIVERS_UART_8250IO=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF" # CONFIG_BOARD_INTEL_BASEBOARD_GLKRVP is not set CONFIG_CPU_ADDR_BITS=32 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 @@ -449,7 +451,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set CONFIG_SPI_FLASH=y @@ -608,7 +609,6 @@ CONFIG_COMMON_FADT=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF" # # Payload -- cgit v1.2.3-70-g09d2 From 44bfbfc0d35a2582b3a5c0df340facbc056810c4 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 18 Jan 2018 20:00:54 -0500 Subject: Update Coreboot config for board ga-g41m-es2l This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/ga-g41m-es2l/config | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/projects/coreboot/configs/seabios/ga-g41m-es2l/config b/projects/coreboot/configs/seabios/ga-g41m-es2l/config index 3393ce2a..237f6daa 100644 --- a/projects/coreboot/configs/seabios/ga-g41m-es2l/config +++ b/projects/coreboot/configs/seabios/ga-g41m-es2l/config @@ -142,6 +142,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 CONFIG_FMDFILE="" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="GA-G41M-ES2L" CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set @@ -424,7 +425,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set CONFIG_REALTEK_8168_RESET=y CONFIG_REALTEK_8168_MACADDRESS="00:4c:69:62:72:65" # CONFIG_RT8168_GET_MAC_FROM_VPD is not set @@ -568,7 +568,6 @@ CONFIG_COMMON_FADT=y # CONFIG_GENERATE_MP_TABLE is not set # CONFIG_GENERATE_PIRQ_TABLE is not set CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="GA-G41M-ES2L" # # Payload -- cgit v1.2.3-70-g09d2 From 079e38184ecb7ffa79d56de0d3ff72ef621dd953 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 18 Jan 2018 20:02:09 -0500 Subject: Update Coreboot config for board kcma-d8 This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/kcma-d8/config | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/coreboot/configs/seabios/kcma-d8/config b/projects/coreboot/configs/seabios/kcma-d8/config index 3e851573..8b78ab25 100644 --- a/projects/coreboot/configs/seabios/kcma-d8/config +++ b/projects/coreboot/configs/seabios/kcma-d8/config @@ -130,6 +130,7 @@ CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" # CONFIG_BOARD_ASUS_A8N_SLI is not set # CONFIG_BOARD_ASUS_A8V_E_DELUXE is not set # CONFIG_BOARD_ASUS_A8V_E_SE is not set +# CONFIG_BOARD_ASUS_AM1I_A is not set # CONFIG_BOARD_ASUS_DSBF is not set # CONFIG_BOARD_ASUS_F2A85_M is not set # CONFIG_BOARD_ASUS_F2A85_M_PRO is not set @@ -171,6 +172,7 @@ CONFIG_FMDFILE="" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KCMA-D8" CONFIG_CPU_ADDR_BITS=48 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set @@ -471,7 +473,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set CONFIG_SPI_FLASH=y @@ -613,7 +614,6 @@ CONFIG_HAVE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KCMA-D8" # # Payload -- cgit v1.2.3-70-g09d2 From e99a3334c93adbd006def23f05d93e1b667ead31 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 18 Jan 2018 20:03:13 -0500 Subject: Update Coreboot config for board kfsn4-dre This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/kfsn4-dre/config | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/coreboot/configs/seabios/kfsn4-dre/config b/projects/coreboot/configs/seabios/kfsn4-dre/config index f85275f7..e4435801 100644 --- a/projects/coreboot/configs/seabios/kfsn4-dre/config +++ b/projects/coreboot/configs/seabios/kfsn4-dre/config @@ -131,6 +131,7 @@ CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" # CONFIG_BOARD_ASUS_A8N_SLI is not set # CONFIG_BOARD_ASUS_A8V_E_DELUXE is not set # CONFIG_BOARD_ASUS_A8V_E_SE is not set +# CONFIG_BOARD_ASUS_AM1I_A is not set # CONFIG_BOARD_ASUS_DSBF is not set # CONFIG_BOARD_ASUS_F2A85_M is not set # CONFIG_BOARD_ASUS_F2A85_M_PRO is not set @@ -174,6 +175,7 @@ CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_TTYS0_LCS=3 CONFIG_DRIVERS_UART_8250IO=y CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KFSN4-DRE" CONFIG_CPU_ADDR_BITS=48 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 CONFIG_USBDEBUG=y @@ -480,7 +482,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set @@ -632,7 +633,6 @@ CONFIG_HAVE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KFSN4-DRE" # # Payload -- cgit v1.2.3-70-g09d2 From a4366c827c6c46bb49075529687a81e15992dc35 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 18 Jan 2018 20:04:15 -0500 Subject: Update Coreboot config for board kgpe-d16 This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/kgpe-d16/config | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/projects/coreboot/configs/seabios/kgpe-d16/config b/projects/coreboot/configs/seabios/kgpe-d16/config index 5bc73835..7a2eca9c 100644 --- a/projects/coreboot/configs/seabios/kgpe-d16/config +++ b/projects/coreboot/configs/seabios/kgpe-d16/config @@ -131,6 +131,7 @@ CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" # CONFIG_BOARD_ASUS_A8N_SLI is not set # CONFIG_BOARD_ASUS_A8V_E_DELUXE is not set # CONFIG_BOARD_ASUS_A8V_E_SE is not set +# CONFIG_BOARD_ASUS_AM1I_A is not set # CONFIG_BOARD_ASUS_DSBF is not set # CONFIG_BOARD_ASUS_F2A85_M is not set # CONFIG_BOARD_ASUS_F2A85_M_PRO is not set @@ -172,6 +173,7 @@ CONFIG_FMDFILE="" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KGPE-D16" CONFIG_CPU_ADDR_BITS=48 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set @@ -472,7 +474,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set CONFIG_SPI_FLASH=y @@ -615,7 +616,6 @@ CONFIG_HAVE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KGPE-D16" # # Payload -- cgit v1.2.3-70-g09d2 From 95e2ec1b7c441a2f3ad1dfc73832400c6c8c2166 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 18 Jan 2018 20:04:59 -0500 Subject: Update Coreboot config for board macbook2,1 This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/macbook21/config | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/projects/coreboot/configs/seabios/macbook21/config b/projects/coreboot/configs/seabios/macbook21/config index 133db9d0..2fcf83ea 100644 --- a/projects/coreboot/configs/seabios/macbook21/config +++ b/projects/coreboot/configs/seabios/macbook21/config @@ -135,6 +135,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 CONFIG_FMDFILE="" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1" CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set @@ -418,7 +419,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set CONFIG_SPI_FLASH=y @@ -561,7 +561,6 @@ CONFIG_COMMON_FADT=y CONFIG_GENERATE_MP_TABLE=y # CONFIG_GENERATE_PIRQ_TABLE is not set CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1" # # Payload -- cgit v1.2.3-70-g09d2 From d994434dddd96d56dbb1100c69dfe669127eb7a8 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 18 Jan 2018 20:06:03 -0500 Subject: Update Coreboot config for board qemu_i440fx_piix4 This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/qemu_i440fx_piix4/config | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/projects/coreboot/configs/seabios/qemu_i440fx_piix4/config b/projects/coreboot/configs/seabios/qemu_i440fx_piix4/config index d648f094..a6110151 100644 --- a/projects/coreboot/configs/seabios/qemu_i440fx_piix4/config +++ b/projects/coreboot/configs/seabios/qemu_i440fx_piix4/config @@ -135,6 +135,7 @@ CONFIG_POST_DEVICE=y CONFIG_FMDFILE="" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="QEMU x86 i440fx/piix4" CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 CONFIG_MAINBOARD_VERSION="1.0" @@ -390,7 +391,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set @@ -517,7 +517,6 @@ CONFIG_HAVE_PIRQ_TABLE=y # CONFIG_GENERATE_MP_TABLE is not set CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="QEMU x86 i440fx/piix4" # # Payload -- cgit v1.2.3-70-g09d2 From 6fa53e8cd29c009fdd904ec564cc36863f9b1135 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 18 Jan 2018 20:06:39 -0500 Subject: Update Coreboot config for board qemu_q35_ich9 This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/qemu_q35_ich9/config | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/projects/coreboot/configs/seabios/qemu_q35_ich9/config b/projects/coreboot/configs/seabios/qemu_q35_ich9/config index aeee9cc9..7c3a47cf 100644 --- a/projects/coreboot/configs/seabios/qemu_q35_ich9/config +++ b/projects/coreboot/configs/seabios/qemu_q35_ich9/config @@ -117,14 +117,11 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" CONFIG_DCACHE_RAM_BASE=0xd0000 CONFIG_DCACHE_RAM_SIZE=0x10000 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Emulation" -CONFIG_HAVE_IFD_BIN=y -# CONFIG_HAVE_ME_BIN is not set CONFIG_MMCONF_BASE_ADDRESS=0xb0000000 CONFIG_POST_IO=y CONFIG_DEVICETREE="devicetree.cb" CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/emulation/qemu-q35/bootblock.c" CONFIG_MAX_REBOOT_CNT=3 -# CONFIG_HAVE_GBE_BIN is not set CONFIG_ID_SECTION_OFFSET=0x80 # CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set # CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set @@ -138,7 +135,7 @@ CONFIG_POST_DEVICE=y CONFIG_FMDFILE="" CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 CONFIG_DRIVERS_UART_8250IO=y -CONFIG_IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="QEMU x86 q35/ich9" CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 # CONFIG_USBDEBUG is not set @@ -273,7 +270,6 @@ CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y # CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set # CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y -# CONFIG_LOCK_MANAGEMENT_ENGINE is not set # # Super I/O @@ -283,13 +279,6 @@ CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y # # Embedded Controllers # -CONFIG_HAVE_INTEL_FIRMWARE=y - -# -# Intel Firmware -# -# CONFIG_EM100 is not set -# CONFIG_HAVE_EC_BIN is not set # CONFIG_MAINBOARD_HAS_CHROMEOS is not set # CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set # CONFIG_UEFI_2_4_BINDING is not set @@ -403,7 +392,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set @@ -529,7 +517,6 @@ CONFIG_HAVE_ACPI_TABLES=y # CONFIG_GENERATE_MP_TABLE is not set # CONFIG_GENERATE_PIRQ_TABLE is not set CONFIG_GENERATE_SMBIOS_TABLES=y -CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="QEMU x86 q35/ich9" # # Payload -- cgit v1.2.3-70-g09d2 From 661bba9d8bfa6a2b960b1e72ba966075cfc03f07 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:20:28 -0500 Subject: Update Coreboot config for board r400_16mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/r400_16mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/r400_16mb/config b/projects/coreboot/configs/seabios/r400_16mb/config index 5e18135a..be8209a7 100644 --- a/projects/coreboot/configs/seabios/r400_16mb/config +++ b/projects/coreboot/configs/seabios/r400_16mb/config @@ -315,6 +315,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From 9ac2fdc554777d5bde1508349087b09060b637f4 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:21:31 -0500 Subject: Update Coreboot config for board r400_4mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/r400_4mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/r400_4mb/config b/projects/coreboot/configs/seabios/r400_4mb/config index becebc06..d838e8a7 100644 --- a/projects/coreboot/configs/seabios/r400_4mb/config +++ b/projects/coreboot/configs/seabios/r400_4mb/config @@ -315,6 +315,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From d9f7e7a6cd77070ac0d81faa5a7fa8aea4eb6dac Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:22:09 -0500 Subject: Update Coreboot config for board r400_8mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/r400_8mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/r400_8mb/config b/projects/coreboot/configs/seabios/r400_8mb/config index 14eb5497..197e906c 100644 --- a/projects/coreboot/configs/seabios/r400_8mb/config +++ b/projects/coreboot/configs/seabios/r400_8mb/config @@ -315,6 +315,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From 86077cbbda3b24c1a4f0a23d87bccdd8d422fe48 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:22:45 -0500 Subject: Update Coreboot config for board t400_16mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/t400_16mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/t400_16mb/config b/projects/coreboot/configs/seabios/t400_16mb/config index 9368d339..cdda414b 100644 --- a/projects/coreboot/configs/seabios/t400_16mb/config +++ b/projects/coreboot/configs/seabios/t400_16mb/config @@ -315,6 +315,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From 18fa4ad26dde6b17c85704d42b8d8fec6b3d7b9f Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:24:11 -0500 Subject: Update Coreboot config for board t400_4mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/t400_4mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/t400_4mb/config b/projects/coreboot/configs/seabios/t400_4mb/config index cc66b4bb..62c1f941 100644 --- a/projects/coreboot/configs/seabios/t400_4mb/config +++ b/projects/coreboot/configs/seabios/t400_4mb/config @@ -315,6 +315,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From ab8f169691ddabcf393c664ae0de7391567e01f2 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:24:40 -0500 Subject: Update Coreboot config for board t400_8mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/t400_8mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/t400_8mb/config b/projects/coreboot/configs/seabios/t400_8mb/config index cf20d266..045c9d37 100644 --- a/projects/coreboot/configs/seabios/t400_8mb/config +++ b/projects/coreboot/configs/seabios/t400_8mb/config @@ -315,6 +315,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From f54466aca0398a875e9c6e84c2f2803a7b009d6c Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:25:15 -0500 Subject: Update Coreboot config for board t500_16mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/t500_16mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/t500_16mb/config b/projects/coreboot/configs/seabios/t500_16mb/config index 4a691bb4..99dab812 100644 --- a/projects/coreboot/configs/seabios/t500_16mb/config +++ b/projects/coreboot/configs/seabios/t500_16mb/config @@ -315,6 +315,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From f6a73a95eb570d3a0e01df5461b8efc412fa2776 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:26:08 -0500 Subject: Update Coreboot config for board t500_4mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/t500_4mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/t500_4mb/config b/projects/coreboot/configs/seabios/t500_4mb/config index ee8b1527..99908d32 100644 --- a/projects/coreboot/configs/seabios/t500_4mb/config +++ b/projects/coreboot/configs/seabios/t500_4mb/config @@ -315,6 +315,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From cdb64adc2e06af33d389cffa00e990208eb7050a Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:27:02 -0500 Subject: Update Coreboot config for board t500_8mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/t500_8mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/t500_8mb/config b/projects/coreboot/configs/seabios/t500_8mb/config index d20cb720..94541069 100644 --- a/projects/coreboot/configs/seabios/t500_8mb/config +++ b/projects/coreboot/configs/seabios/t500_8mb/config @@ -315,6 +315,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From 3eeb8eb0664a75c8450064f9bad24325ac00da99 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:27:59 -0500 Subject: Update Coreboot config for board t60 This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/t60/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/t60/config b/projects/coreboot/configs/seabios/t60/config index 8ccbacd1..04512207 100644 --- a/projects/coreboot/configs/seabios/t60/config +++ b/projects/coreboot/configs/seabios/t60/config @@ -320,6 +320,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y # CONFIG_MAINBOARD_HAS_CHROMEOS is not set @@ -441,7 +442,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set CONFIG_SPI_FLASH=y -- cgit v1.2.3-70-g09d2 From 873ee2e73f98645e5d1d7c03b9cf3a1ffcc10959 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:28:42 -0500 Subject: Update Coreboot config for board w500_16mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/w500_16mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/w500_16mb/config b/projects/coreboot/configs/seabios/w500_16mb/config index 4a691bb4..99dab812 100644 --- a/projects/coreboot/configs/seabios/w500_16mb/config +++ b/projects/coreboot/configs/seabios/w500_16mb/config @@ -315,6 +315,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From 5c674f93fed0d5ee83480a69febaf0520482de33 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:29:04 -0500 Subject: Update Coreboot config for board w500_4mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/w500_4mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/w500_4mb/config b/projects/coreboot/configs/seabios/w500_4mb/config index ee8b1527..99908d32 100644 --- a/projects/coreboot/configs/seabios/w500_4mb/config +++ b/projects/coreboot/configs/seabios/w500_4mb/config @@ -315,6 +315,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From 46297e1f623d1ef3bdacf00e6bc0314b26edcc95 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:29:23 -0500 Subject: Update Coreboot config for board w500_8mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/w500_8mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/w500_8mb/config b/projects/coreboot/configs/seabios/w500_8mb/config index d20cb720..94541069 100644 --- a/projects/coreboot/configs/seabios/w500_8mb/config +++ b/projects/coreboot/configs/seabios/w500_8mb/config @@ -315,6 +315,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # CONFIG_GIC is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From 493e8ed5d31205df22d2e69c5ac5f69dbf3d0ac1 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:29:45 -0500 Subject: Update Coreboot config for board x200_16mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/x200_16mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/x200_16mb/config b/projects/coreboot/configs/seabios/x200_16mb/config index 87e0d4ed..abf25d09 100644 --- a/projects/coreboot/configs/seabios/x200_16mb/config +++ b/projects/coreboot/configs/seabios/x200_16mb/config @@ -313,6 +313,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_DRIVERS_LENOVO_WACOM=y # CONFIG_DIGITIZER_AUTODETECT is not set CONFIG_DIGITIZER_PRESENT=y # CONFIG_DIGITIZER_ABSENT is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From 7a54024bab6659a2940babf1a8f5f93905af9438 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:30:08 -0500 Subject: Update Coreboot config for board x200_4mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/x200_4mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/x200_4mb/config b/projects/coreboot/configs/seabios/x200_4mb/config index 214128a1..33b2d886 100644 --- a/projects/coreboot/configs/seabios/x200_4mb/config +++ b/projects/coreboot/configs/seabios/x200_4mb/config @@ -313,6 +313,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_DRIVERS_LENOVO_WACOM=y # CONFIG_DIGITIZER_AUTODETECT is not set CONFIG_DIGITIZER_PRESENT=y # CONFIG_DIGITIZER_ABSENT is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From f7881688884c91ce772e1cfb1f8ba23ae3bc99e6 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:30:26 -0500 Subject: Update Coreboot config for board x200_8mb This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/x200_8mb/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/x200_8mb/config b/projects/coreboot/configs/seabios/x200_8mb/config index 4d9ef0b0..8e2be019 100644 --- a/projects/coreboot/configs/seabios/x200_8mb/config +++ b/projects/coreboot/configs/seabios/x200_8mb/config @@ -313,6 +313,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_EC_LENOVO_PMH7=y CONFIG_HAVE_INTEL_FIRMWARE=y @@ -443,7 +444,6 @@ CONFIG_DRIVERS_LENOVO_WACOM=y # CONFIG_DIGITIZER_AUTODETECT is not set CONFIG_DIGITIZER_PRESENT=y # CONFIG_DIGITIZER_ABSENT is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set # CONFIG_SPI_FLASH is not set -- cgit v1.2.3-70-g09d2 From 9966070cda2eea14770d3bbe869045d03014e47e Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 20 Jan 2018 21:30:48 -0500 Subject: Update Coreboot config for board x60 This config was updated using Coreboot's 'oldconfig' make target. --- projects/coreboot/configs/seabios/x60/config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/coreboot/configs/seabios/x60/config b/projects/coreboot/configs/seabios/x60/config index 952be764..8257be82 100644 --- a/projects/coreboot/configs/seabios/x60/config +++ b/projects/coreboot/configs/seabios/x60/config @@ -321,6 +321,7 @@ CONFIG_EC_ACPI=y CONFIG_EC_LENOVO_H8=y CONFIG_H8_BEEP_ON_DEATH=y CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set CONFIG_H8_DOCK_EARLY_INIT=y CONFIG_EC_LENOVO_PMH7=y # CONFIG_MAINBOARD_HAS_CHROMEOS is not set @@ -445,7 +446,6 @@ CONFIG_DRIVERS_LENOVO_WACOM=y # CONFIG_DIGITIZER_AUTODETECT is not set CONFIG_DIGITIZER_PRESENT=y # CONFIG_DIGITIZER_ABSENT is not set -# CONFIG_CACHE_MRC_SETTINGS is not set # CONFIG_RT8168_GET_MAC_FROM_VPD is not set # CONFIG_RT8168_SET_LED_MODE is not set CONFIG_SPI_FLASH=y -- cgit v1.2.3-70-g09d2 From d4bcd2bad83138f2494313b3adb75b519890b3ea Mon Sep 17 00:00:00 2001 From: Roman Rakhmatullin Date: Thu, 25 Jan 2018 21:20:01 +0000 Subject: Fixed a typo --- docs/hardware/d945gclf.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/hardware/d945gclf.md b/docs/hardware/d945gclf.md index c3f4754a..f464e4bd 100644 --- a/docs/hardware/d945gclf.md +++ b/docs/hardware/d945gclf.md @@ -30,7 +30,7 @@ Remarks about vendor bios: -------------------------- - Without coreboot/libreboot this board is utery useless, since the - vendor bios is very bad. It cannot boot from any HDD wether it is + vendor bios is very bad. It cannot boot from any HDD whether it is connected to the SATA port or USB. With libreboot it works just fine. -- cgit v1.2.3-70-g09d2 From 35934432a6257126f1dc444ee1b2864c8e741082 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 25 Jan 2018 16:42:39 -0500 Subject: Remove unnecessary memtest86plus targets file --- projects/memtest86plus/configs/targets | 2 -- 1 file changed, 2 deletions(-) delete mode 100644 projects/memtest86plus/configs/targets diff --git a/projects/memtest86plus/configs/targets b/projects/memtest86plus/configs/targets deleted file mode 100644 index f2cba0e5..00000000 --- a/projects/memtest86plus/configs/targets +++ /dev/null @@ -1,2 +0,0 @@ -grub -seabios -- cgit v1.2.3-70-g09d2 From 85e1a4604c6e416c5c736d10da9234069143267e Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 25 Jan 2018 16:45:15 -0500 Subject: Add memtest86plus floppy image to install file To retain options, it would be a good idea to keep the floppy image since SeaBIOS can boot floppy images directly from CBFS. --- projects/memtest86plus/configs/install | 1 + 1 file changed, 1 insertion(+) diff --git a/projects/memtest86plus/configs/install b/projects/memtest86plus/configs/install index 4092a417..6d1d72a2 100644 --- a/projects/memtest86plus/configs/install +++ b/projects/memtest86plus/configs/install @@ -1 +1,2 @@ memtest:memtest.elf +memtest.bin:memtest.img -- cgit v1.2.3-70-g09d2 From d870ebb62617b6a2c0bb4a7cab1f97a2299a6086 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 25 Jan 2018 16:56:05 -0500 Subject: Copy all memtest86plus binaries to the build path --- projects/memtest86plus/memtest86plus | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/memtest86plus/memtest86plus b/projects/memtest86plus/memtest86plus index 1aadbf6c..c64f66a7 100755 --- a/projects/memtest86plus/memtest86plus +++ b/projects/memtest86plus/memtest86plus @@ -75,7 +75,7 @@ build() { mkdir -p "$build_path" make -C "$sources_path" -j"$TASKS" - cp "$sources_path/memtest" "$build_path" + cp "$sources_path"/{memtest,memtest.bin} "$build_path" make -C "$sources_path" 'clean' } -- cgit v1.2.3-70-g09d2 From 4fec5369967e37866158aa28e7a28978eafd5727 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 25 Jan 2018 17:37:31 -0500 Subject: Update Coreboot patch for removing git submodules Simply updated to apply to the newer revision of Coreboot that's being used. Paul Kocialkowski is still retained as the author of the patch. --- .../patches/0001-Avoid-using-git-submodules-for-3rdparty.patch | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/projects/coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch b/projects/coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch index 6fd53217..24964bb4 100644 --- a/projects/coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch +++ b/projects/coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch @@ -1,6 +1,6 @@ -From c47f1f9e3b5d1a77b5261ad7cb7538c384828487 Mon Sep 17 00:00:00 2001 +From b403ddd709578d11f1e6d32abfc94701f57cae16 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski -Date: Thu, 21 Dec 2017 18:05:33 -0500 +Date: Thu, 25 Jan 2018 17:31:55 -0500 Subject: [PATCH] Avoid using git submodules for 3rdparty This gets rid of git submodules entirely, to avoid the nuisance caused @@ -59,11 +59,11 @@ index b118723..0000000 -Subproject commit b1187232fdf819586ba8c8ece4a27a7515cbdc6d diff --git a/3rdparty/blobs b/3rdparty/blobs deleted file mode 160000 -index d2e558a..0000000 +index 8eb92ba..0000000 --- a/3rdparty/blobs +++ /dev/null @@ -1 +0,0 @@ --Subproject commit d2e558a81f95f7b9149bea6b8362bb43ade82584 +-Subproject commit 8eb92ba947e171df11b3c62f5f257ce69b9e2d55 diff --git a/3rdparty/chromeec b/3rdparty/chromeec deleted file mode 160000 index 9fb1038..0000000 -- cgit v1.2.3-70-g09d2 From 0d7eb3b9096f082e38cb4b56639da498f0e16f12 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 27 Jan 2018 23:12:56 -0500 Subject: Delete obsolete flashrom patches These patches are in the process of being upstreamed. --- ...-whitelisted-ThinkPad-R400-and-ThinkPad-T.patch | 28 ---------------------- ...02-Add-whitelist-for-Taurinus-X200-laptop.patch | 24 ------------------- .../patches/0004-Whitelist-ThinkPad-W500.patch | 24 ------------------- 3 files changed, 76 deletions(-) delete mode 100644 projects/flashrom/patches/0001-New-laptops-whitelisted-ThinkPad-R400-and-ThinkPad-T.patch delete mode 100644 projects/flashrom/patches/0002-Add-whitelist-for-Taurinus-X200-laptop.patch delete mode 100644 projects/flashrom/patches/0004-Whitelist-ThinkPad-W500.patch diff --git a/projects/flashrom/patches/0001-New-laptops-whitelisted-ThinkPad-R400-and-ThinkPad-T.patch b/projects/flashrom/patches/0001-New-laptops-whitelisted-ThinkPad-R400-and-ThinkPad-T.patch deleted file mode 100644 index f9d51806..00000000 --- a/projects/flashrom/patches/0001-New-laptops-whitelisted-ThinkPad-R400-and-ThinkPad-T.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 52a0b55c77635dc026793e66d516e3aed335706a Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Fri, 11 Mar 2016 06:35:03 +0000 -Subject: [PATCH 1/1] New laptops whitelisted: ThinkPad R400 and ThinkPad T500 - -Support for these laptops was merged in coreboot a while ago, so it makes sense -for flashrom to whitelist them. ---- - board_enable.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/board_enable.c b/board_enable.c -index 7b152d1..1d56203 100644 ---- a/board_enable.c -+++ b/board_enable.c -@@ -2427,7 +2427,9 @@ const struct board_match board_matches[] = { - {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^SE440BX-2$", NULL, NULL, P3, "Intel", "SE440BX-2", 0, NT, intel_piix4_gpo27_lower}, - {0x1022, 0x7468, 0, 0, 0x1022, 0x7460, 0, 0, NULL, "iwill", "dk8_htx", P3, "IWILL", "DK8-HTX", 0, OK, w83627hf_gpio24_raise_2e}, - {0x8086, 0x27A0, 0x8086, 0x27a0, 0x8086, 0x27b8, 0x8086, 0x27b8, NULL, "kontron", "986lcd-m", P3, "Kontron", "986LCD-M", 0, OK, board_kontron_986lcd_m}, -+ {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad R400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad R400", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T400", 0, OK, p2_whitelist_laptop}, -+ {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T500", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T500", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x1E22, 0x17AA, 0x21F6, 0x8086, 0x1E55, 0x17AA, 0x21F6, "^ThinkPad T530", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T530", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60(s)", 0, OK, p2_whitelist_laptop}, --- -1.9.1 - diff --git a/projects/flashrom/patches/0002-Add-whitelist-for-Taurinus-X200-laptop.patch b/projects/flashrom/patches/0002-Add-whitelist-for-Taurinus-X200-laptop.patch deleted file mode 100644 index 0aa0701b..00000000 --- a/projects/flashrom/patches/0002-Add-whitelist-for-Taurinus-X200-laptop.patch +++ /dev/null @@ -1,24 +0,0 @@ -From b1828512abf58911cfb829cb6a98d4e8dbefadc2 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Fri, 11 Mar 2016 06:38:39 +0000 -Subject: [PATCH 1/1] Add whitelist for Taurinus X200 laptop - ---- - board_enable.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/board_enable.c b/board_enable.c -index 1d56203..a71061c 100644 ---- a/board_enable.c -+++ b/board_enable.c -@@ -2437,6 +2437,7 @@ const struct board_match board_matches[] = { - {0x8086, 0x3B07, 0x17AA, 0x2166, 0x8086, 0x3B30, 0x17AA, 0x2167, "^Lenovo X201", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X201", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x1E22, 0x17AA, 0x21FA, 0x8086, 0x1E55, 0x17AA, 0x21FA, "^ThinkPad X230", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X230", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x27A0, 0x17AA, 0x2017, 0x8086, 0x27B9, 0x17AA, 0x2009, "^ThinkPad X60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad X60(s)", 0, OK, p2_whitelist_laptop}, -+ {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^Taurinus X200", "Libiquity", "Taurinus X200", P2, "Libiquity", "ThinkPad X200", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x2411, 0x8086, 0x2411, 0x8086, 0x7125, 0x0e11, 0xb165, NULL, NULL, NULL, P3, "Mitac", "6513WU", 0, OK, board_mitac_6513wu}, - {0x8086, 0x8186, 0x8086, 0x8186, 0x8086, 0x8800, 0, 0, "^MSC Vertriebs GmbH$", NULL, NULL, P2, "MSC", "Q7-TCTC", 0, OK, p2_not_a_laptop}, - {0x8086, 0x7190, 0, 0, 0x8086, 0x7110, 0, 0, "^MS-6163 (i440BX)$", NULL, NULL, P3, "MSI", "MS-6163 (MS-6163 Pro)", 0, OK, intel_piix4_gpo14_raise}, --- -1.9.1 - diff --git a/projects/flashrom/patches/0004-Whitelist-ThinkPad-W500.patch b/projects/flashrom/patches/0004-Whitelist-ThinkPad-W500.patch deleted file mode 100644 index bb1c2bc3..00000000 --- a/projects/flashrom/patches/0004-Whitelist-ThinkPad-W500.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 8c970dcf19661bc3d128a10e3ca79c24b4479186 Mon Sep 17 00:00:00 2001 -From: Gauvain Roussel-Tarbouriech -Date: Sat, 29 Apr 2017 19:01:11 +0200 -Subject: [PATCH 1/1] Whitelist ThinkPad W500 - ---- - board_enable.c | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/board_enable.c b/board_enable.c -index fc99615..a418e4f 100644 ---- a/board_enable.c -+++ b/board_enable.c -@@ -2430,6 +2430,7 @@ const struct board_match board_matches[] = { - {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad R400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad R400", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T400", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T500", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T500", 0, OK, p2_whitelist_laptop}, -+ {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad W500", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad W500", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x1E22, 0x17AA, 0x21F6, 0x8086, 0x1E55, 0x17AA, 0x21F6, "^ThinkPad T530", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T530", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60", 0, OK, p2_whitelist_laptop}, - {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60(s)", 0, OK, p2_whitelist_laptop}, --- -2.12.2 - -- cgit v1.2.3-70-g09d2 From 5eb42d3bf11276700780f658b1de15ca6625a677 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 10 Feb 2018 22:05:55 -0500 Subject: Update Depthcharge revision to latest release --- projects/depthcharge/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/depthcharge/configs/revision b/projects/depthcharge/configs/revision index ec6fe7d9..6ce6b84b 100644 --- a/projects/depthcharge/configs/revision +++ b/projects/depthcharge/configs/revision @@ -1 +1 @@ -origin/release-R63-10032.B +origin/release-R65-10323.B -- cgit v1.2.3-70-g09d2 From 9f47421e4a5e07300c9a4e9ef42634049345dfc7 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 10 Feb 2018 22:08:12 -0500 Subject: Update flashmap revision to latest release --- projects/flashmap/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/flashmap/configs/revision b/projects/flashmap/configs/revision index ec6fe7d9..6ce6b84b 100644 --- a/projects/flashmap/configs/revision +++ b/projects/flashmap/configs/revision @@ -1 +1 @@ -origin/release-R63-10032.B +origin/release-R65-10323.B -- cgit v1.2.3-70-g09d2 From 3bd2108e2c52226d30211b484b696392a167e535 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 10 Feb 2018 22:09:30 -0500 Subject: Update flashrom-cros revision to latest release --- projects/flashrom-cros/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/flashrom-cros/configs/revision b/projects/flashrom-cros/configs/revision index ec6fe7d9..6ce6b84b 100644 --- a/projects/flashrom-cros/configs/revision +++ b/projects/flashrom-cros/configs/revision @@ -1 +1 @@ -origin/release-R63-10032.B +origin/release-R65-10323.B -- cgit v1.2.3-70-g09d2 From eebffd4ec5ce4b92c4933d77bb6f6eff46e05f90 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 10 Feb 2018 22:10:28 -0500 Subject: Update hdctools revision to latest release --- projects/hdctools/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/hdctools/configs/revision b/projects/hdctools/configs/revision index ec6fe7d9..6ce6b84b 100644 --- a/projects/hdctools/configs/revision +++ b/projects/hdctools/configs/revision @@ -1 +1 @@ -origin/release-R63-10032.B +origin/release-R65-10323.B -- cgit v1.2.3-70-g09d2 From cdbea528b3074095764927e7f69ddb17a5900a94 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 10 Feb 2018 22:11:16 -0500 Subject: Update mosys revision to latest release --- projects/mosys/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/mosys/configs/revision b/projects/mosys/configs/revision index ec6fe7d9..6ce6b84b 100644 --- a/projects/mosys/configs/revision +++ b/projects/mosys/configs/revision @@ -1 +1 @@ -origin/release-R63-10032.B +origin/release-R65-10323.B -- cgit v1.2.3-70-g09d2 From 0d7fbc4368b667739ab49c940d489bf400593555 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 10 Feb 2018 22:12:03 -0500 Subject: Update vboot revision to latest release --- projects/vboot/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/vboot/configs/revision b/projects/vboot/configs/revision index ec6fe7d9..6ce6b84b 100644 --- a/projects/vboot/configs/revision +++ b/projects/vboot/configs/revision @@ -1 +1 @@ -origin/release-R63-10032.B +origin/release-R65-10323.B -- cgit v1.2.3-70-g09d2 From e4c61ef90887aa426b757372c0875a9a0497f9c9 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 10 Feb 2018 22:12:50 -0500 Subject: Update vpd revision to latest release --- projects/vpd/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/vpd/configs/revision b/projects/vpd/configs/revision index ec6fe7d9..6ce6b84b 100644 --- a/projects/vpd/configs/revision +++ b/projects/vpd/configs/revision @@ -1 +1 @@ -origin/release-R63-10032.B +origin/release-R65-10323.B -- cgit v1.2.3-70-g09d2 From a558f81e04d9b570ca38cb13986c12cb153c23d0 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 10 Feb 2018 22:14:16 -0500 Subject: Update nyan CrOS-EC revision to latest release --- projects/cros-ec/configs/nyan/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/cros-ec/configs/nyan/revision b/projects/cros-ec/configs/nyan/revision index ec6fe7d9..6ce6b84b 100644 --- a/projects/cros-ec/configs/nyan/revision +++ b/projects/cros-ec/configs/nyan/revision @@ -1 +1 @@ -origin/release-R63-10032.B +origin/release-R65-10323.B -- cgit v1.2.3-70-g09d2 From 7b58195623d77b400a1739211c4f70b10532ebb2 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 10 Feb 2018 22:15:41 -0500 Subject: Update veyron CrOS-EC revision to latest release --- projects/cros-ec/configs/veyron/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/cros-ec/configs/veyron/revision b/projects/cros-ec/configs/veyron/revision index ec6fe7d9..6ce6b84b 100644 --- a/projects/cros-ec/configs/veyron/revision +++ b/projects/cros-ec/configs/veyron/revision @@ -1 +1 @@ -origin/release-R63-10032.B +origin/release-R65-10323.B -- cgit v1.2.3-70-g09d2 From ec03fccfefd689d4237b6e6dbba970029b1e1621 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Mon, 19 Feb 2018 13:23:34 +0000 Subject: update zanity.net mirror to new URL (no PR needed. just a URL change) the maintainer of the mirror contacted me privately, requesting the change --- www/download.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/www/download.md b/www/download.md index f88b20af..5edaa4f4 100644 --- a/www/download.md +++ b/www/download.md @@ -49,7 +49,8 @@ Project, USA) (elgrande74.net, France) - (zanity.net, New Zealand) + (nephelai.info, New Zealand) +(formerly nephelai.zanity.net/mirror/libreboot) (koddos.net, Netherlands) -- cgit v1.2.3-70-g09d2 From 9ee1680d164b610d6fc1bd57a7428ecfa98d562b Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Thu, 22 Feb 2018 19:18:20 +0100 Subject: Fix misguiding T60s to T60 variants --- docs/hardware/index.md | 2 +- docs/release.md | 18 +++++++++--------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/docs/hardware/index.md b/docs/hardware/index.md index 5fefdff3..01719ada 100644 --- a/docs/hardware/index.md +++ b/docs/hardware/index.md @@ -223,7 +223,7 @@ BIOS](https://en.wikipedia.org/wiki/Video_BIOS)' or 'VBIOS'). To find what LCD panel you have, see: [../misc/\#get\_edid\_panelname](../misc/#get_edid_panelname). -*Some T60s have ATI GPUs, and all T60P laptops have ATI GPUs These are +*Some T60 variants have ATI GPUs, and all T60p laptops have ATI GPUs These are incompatible! See [\#t60\_ati\_intel](#t60_ati_intel) for how to remedy this.* diff --git a/docs/release.md b/docs/release.md index 0cfdf8ef..f8300ac7 100644 --- a/docs/release.md +++ b/docs/release.md @@ -77,7 +77,7 @@ Machines supported in this release: - It is unknown whether a T61 can have it's mainboard replaced with a T60 motherboard. - See ***docs/future/\#t60\_cpu\_microcode***. - - T60P (and T60 laptops with ATI GPU) will likely never be + - T60p (and T60 laptops with ATI GPU) will likely never be supported: ***docs/hardware/\#t60\_ati\_intel*** - **ThinkPad X200** - X200S and X200 Tablet are also supported, conditionally; see @@ -228,7 +228,7 @@ Machines supported in this release: - It is unknown whether a T61 can have it's mainboard replaced with a T60 motherboard. - See ***docs/future/\#t60\_cpu\_microcode***. - - T60P (and T60 laptops with ATI GPU) will likely never be + - T60p (and T60 laptops with ATI GPU) will likely never be supported: ***docs/hardware/\#t60\_ati\_intel*** - **ThinkPad X200** - X200S and X200 Tablet are also supported, conditionally; see @@ -450,7 +450,7 @@ Machines supported in this release: - It is unknown whether a T61 can have it's mainboard replaced with a T60 motherboard. - See **future/\#t60\_cpu\_microcode**. - - T60P (and T60 laptops with ATI GPU) will likely never be + - T60p (and T60 laptops with ATI GPU) will likely never be supported: **hardware/\#t60\_ati\_intel** - **Lenovo ThinkPad X200** - X200S and X200 Tablet are also supported, conditionally; see @@ -658,7 +658,7 @@ Machines supported in this release: - It is unknown whether a T61 can have its mainboard replaced with a T60 motherboard. - See **future/\#t60\_cpu\_microcode**. - - T60P (and T60s with ATI GPU) will likely never be supported: + - T60p (and T60 variants with ATI GPU) will likely never be supported: **hardware/\#t60\_ati\_intel** - **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) - See **hardware/\#macbook11**. @@ -737,7 +737,7 @@ New systems supported in this release: **hardware/\#supported\_t60\_list** for known working LCD panels. - It is unknown whether a T61 can have its mainboard replaced with a T60 motherboard. - - T60P (and T60s with ATI GPU) will likely never be supported: + - T60p (and T60 variants with ATI GPU) will likely never be supported: **hardware/\#t60\_ati\_intel** - **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) - See **hardware/\#macbook11**. @@ -1088,7 +1088,7 @@ Revisions for r20140711 (1st beta) (11th July 2014) - Documentation: added a copy of Mono's Coreboot page (for macbook21) and linked it in main index. - T60: Copy CD option from the grub.cfg files for T60 \*serial\*.rom - images into the grub configs for non-serial images. (T60s have + images into the grub configs for non-serial images. (T60 laptops have CD/DVD drive on main laptop) - macbook21: remove options in build-macbook21 for \*serial\*.rom (there is no dock or serial port available for macbook21) @@ -1100,8 +1100,8 @@ Revisions for r20140711 (1st beta) (11th July 2014) - Documentation: Added info about getting LCD panel name based on EDID data. - Documentation: Added a link to this from the list of supported - T60s and LCD panels for T60 (so that the user can check what LCD - panel they have). + T60 laptopss and LCD panels for T60 (so that the user can check + what LCD panel they have). - X60/T60: Merged patches for 3D fix (from Paul Menzel) when using kernel 3.12 or higher (see ./resources/libreboot/patch/gitdiff and ./getcb) @@ -1237,7 +1237,7 @@ Revisions for r20140711 (1st beta) (11th July 2014) put in the coreboot configs - Documentation: In fact, document how the 'config' files in resources/libreboot/config/ were created -- Documentation: Added information about which ThinkPad T60s are +- Documentation: Added information about which ThinkPad T60 laptops are supported, and which are not. - Documentation: added information about LCD inverters (for upgrading the LCD panel on a T60 14.1' XGA or 15.1' XGA) -- cgit v1.2.3-70-g09d2 From 0135ce2a42af46a10666c36af40cfce6c2c184b3 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Mon, 26 Feb 2018 23:19:49 -0500 Subject: Update flashrom revision This pulls in the Thinkpad-related patches that Leah submitted upstream. --- projects/flashrom/configs/revision | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/flashrom/configs/revision b/projects/flashrom/configs/revision index 6b3126ce..0a38356a 100644 --- a/projects/flashrom/configs/revision +++ b/projects/flashrom/configs/revision @@ -1 +1 @@ -v1.0 +a72d5a98286272094dda06f5c69b48910f6a7451 -- cgit v1.2.3-70-g09d2 From 92ecdf75c6aba933c6e92328ade43a982d5b0430 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Fri, 2 Mar 2018 00:23:24 -0500 Subject: Update flashrom patch for redundant Macronix chips --- .../0001-Purge-redundant-Macronix-chips.patch | 91 ++++++ projects/flashrom/patches/0003-purged-chips.patch | 354 --------------------- 2 files changed, 91 insertions(+), 354 deletions(-) create mode 100644 projects/flashrom/patches/0001-Purge-redundant-Macronix-chips.patch delete mode 100644 projects/flashrom/patches/0003-purged-chips.patch diff --git a/projects/flashrom/patches/0001-Purge-redundant-Macronix-chips.patch b/projects/flashrom/patches/0001-Purge-redundant-Macronix-chips.patch new file mode 100644 index 00000000..e14bfe0c --- /dev/null +++ b/projects/flashrom/patches/0001-Purge-redundant-Macronix-chips.patch @@ -0,0 +1,91 @@ +From 4a262ea16a10a6067d48d70a2195151dea9292c6 Mon Sep 17 00:00:00 2001 +From: Andrew Robbins +Date: Fri, 2 Mar 2018 00:13:16 -0500 +Subject: [PATCH] Purge redundant Macronix chips + +Removing the redundant Macronix chips avoids the situation where X60 +owners have to specify their particular chip on the command line with +flashrom's '--chip' flag. +--- + flashchips.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/flashchips.c b/flashchips.c +index 1ab4986..7f85415 100644 +--- a/flashchips.c ++++ b/flashchips.c +@@ -7595,7 +7595,7 @@ const struct flashchip flashchips[] = { + .name = "MX25L1605A/MX25L1606E/MX25L1608E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, +- .model_id = MACRONIX_MX25L1605, ++ .model_id = 0xDEAD, + .total_size = 2048, + .page_size = 256, + /* OTP: 64B total; enter 0xB1, exit 0xC1 (MX25L1606E and MX25L1608E only) */ +@@ -7634,7 +7634,7 @@ const struct flashchip flashchips[] = { + .name = "MX25L1605D/MX25L1608D/MX25L1673E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, +- .model_id = MACRONIX_MX25L1605, ++ .model_id = 0xDEAD, + .total_size = 2048, + .page_size = 256, + .feature_bits = FEATURE_WRSR_WREN, +@@ -7776,7 +7776,7 @@ const struct flashchip flashchips[] = { + .name = "MX25L3205D/MX25L3208D", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, +- .model_id = MACRONIX_MX25L3205, ++ .model_id = 0xDEAD, + .total_size = 4096, + .page_size = 256, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ +@@ -7812,7 +7812,7 @@ const struct flashchip flashchips[] = { + .name = "MX25L3206E/MX25L3208E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, +- .model_id = MACRONIX_MX25L3205, ++ .model_id = 0xDEAD, + .total_size = 4096, + .page_size = 256, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ +@@ -7851,7 +7851,7 @@ const struct flashchip flashchips[] = { + .name = "MX25L3273E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, +- .model_id = MACRONIX_MX25L3205, ++ .model_id = 0xDEAD, + .total_size = 4096, + .page_size = 256, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ +@@ -7962,7 +7962,7 @@ const struct flashchip flashchips[] = { + .name = "MX25L6405D", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, +- .model_id = MACRONIX_MX25L6405, ++ .model_id = 0xDEAD, + .total_size = 8192, + .page_size = 256, + /* OTP: 64B total; enter 0xB1, exit 0xC1 */ +@@ -7998,7 +7998,7 @@ const struct flashchip flashchips[] = { + .name = "MX25L6406E/MX25L6408E", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, +- .model_id = MACRONIX_MX25L6405, ++ .model_id = 0xDEAD, + .total_size = 8192, + .page_size = 256, + /* MX25L6406E supports SFDP */ +@@ -8038,7 +8038,7 @@ const struct flashchip flashchips[] = { + .name = "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E/MX25L6473F", + .bustype = BUS_SPI, + .manufacture_id = MACRONIX_ID, +- .model_id = MACRONIX_MX25L6405, ++ .model_id = 0xDEAD, + .total_size = 8192, + .page_size = 256, + /* supports SFDP */ +-- +1.9.1 + diff --git a/projects/flashrom/patches/0003-purged-chips.patch b/projects/flashrom/patches/0003-purged-chips.patch deleted file mode 100644 index 0dc7e2bc..00000000 --- a/projects/flashrom/patches/0003-purged-chips.patch +++ /dev/null @@ -1,354 +0,0 @@ -From 260f0e096b385c9f53e9a28e79293131a11122a6 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Fri, 11 Mar 2016 06:50:50 +0000 -Subject: [PATCH 1/1] purged chips - ---- - flashchips.c | 303 ----------------------------------------------------------- - 1 file changed, 303 deletions(-) - -diff --git a/flashchips.c b/flashchips.c -index 0fc1b7a..5c94304 100644 ---- a/flashchips.c -+++ b/flashchips.c -@@ -7451,80 +7451,6 @@ const struct flashchip flashchips[] = { - - { - .vendor = "Macronix", -- .name = "MX25L1605", -- .bustype = BUS_SPI, -- .manufacture_id = MACRONIX_ID, -- .model_id = MACRONIX_MX25L1605, -- .total_size = 2048, -- .page_size = 256, -- .feature_bits = FEATURE_WRSR_WREN, -- .tested = TEST_OK_PREW, -- .probe = probe_spi_rdid, -- .probe_timing = TIMING_ZERO, -- .block_erasers = -- { -- { -- .eraseblocks = { {64 * 1024, 32} }, -- .block_erase = spi_block_erase_20, -- }, { -- .eraseblocks = { {64 * 1024, 32} }, -- .block_erase = spi_block_erase_d8, -- }, { -- .eraseblocks = { {2 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_60, -- }, { -- .eraseblocks = { {2 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_c7, -- }, -- }, -- .printlock = spi_prettyprint_status_register_bp2_srwd, /* bit6: error flag */ -- .unlock = spi_disable_blockprotect, -- .write = spi_chip_write_256, -- .read = spi_chip_read, /* Fast read (0x0B) supported */ -- .voltage = {2700, 3600}, -- }, -- -- { -- .vendor = "Macronix", -- .name = "MX25L1605A/MX25L1606E/MX25L1608E", -- .bustype = BUS_SPI, -- .manufacture_id = MACRONIX_ID, -- .model_id = MACRONIX_MX25L1605, -- .total_size = 2048, -- .page_size = 256, -- /* OTP: 64B total; enter 0xB1, exit 0xC1 (MX25L1606E and MX25L1608E only) */ -- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, -- .tested = TEST_OK_PREW, -- .probe = probe_spi_rdid, -- .probe_timing = TIMING_ZERO, -- .block_erasers = -- { -- { -- .eraseblocks = { {4 * 1024, 512} }, -- .block_erase = spi_block_erase_20, -- }, { -- .eraseblocks = { {64 * 1024, 32} }, -- .block_erase = spi_block_erase_52, -- }, { -- .eraseblocks = { {64 * 1024, 32} }, -- .block_erase = spi_block_erase_d8, -- }, { -- .eraseblocks = { {2 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_60, -- }, { -- .eraseblocks = { {2 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_c7, -- }, -- }, -- .printlock = spi_prettyprint_status_register_bp3_srwd, /* MX25L1605A bp2 only */ -- .unlock = spi_disable_blockprotect_bp3_srwd, -- .write = spi_chip_write_256, -- .read = spi_chip_read, /* Fast read (0x0B) supported (MX25L1608E supports dual-I/O read) */ -- .voltage = {2700, 3600}, -- }, -- -- { -- .vendor = "Macronix", - .name = "MX25L1605D/MX25L1608D/MX25L1673E", - .bustype = BUS_SPI, - .manufacture_id = MACRONIX_ID, -@@ -7632,41 +7558,6 @@ const struct flashchip flashchips[] = { - - { - .vendor = "Macronix", -- .name = "MX25L3205(A)", -- .bustype = BUS_SPI, -- .manufacture_id = MACRONIX_ID, -- .model_id = MACRONIX_MX25L3205, -- .total_size = 4096, -- .page_size = 256, -- .feature_bits = FEATURE_WRSR_WREN, -- .tested = TEST_OK_PREW, -- .probe = probe_spi_rdid, -- .probe_timing = TIMING_ZERO, -- .block_erasers = -- { -- { -- .eraseblocks = { {64 * 1024, 64} }, -- .block_erase = spi_block_erase_20, -- }, { -- .eraseblocks = { {64 * 1024, 64} }, -- .block_erase = spi_block_erase_d8, -- }, { -- .eraseblocks = { {4 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_60, -- }, { -- .eraseblocks = { {4 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_c7, -- }, -- }, -- .printlock = spi_prettyprint_status_register_bp2_srwd, /* bit6: error flag */ -- .unlock = spi_disable_blockprotect, -- .write = spi_chip_write_256, -- .read = spi_chip_read, /* Fast read (0x0B) supported */ -- .voltage = {2700, 3600}, -- }, -- -- { -- .vendor = "Macronix", - .name = "MX25L3205D/MX25L3208D", - .bustype = BUS_SPI, - .manufacture_id = MACRONIX_ID, -@@ -7703,84 +7594,6 @@ const struct flashchip flashchips[] = { - - { - .vendor = "Macronix", -- .name = "MX25L3206E/MX25L3208E", -- .bustype = BUS_SPI, -- .manufacture_id = MACRONIX_ID, -- .model_id = MACRONIX_MX25L3205, -- .total_size = 4096, -- .page_size = 256, -- /* OTP: 64B total; enter 0xB1, exit 0xC1 */ -- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, -- .tested = TEST_OK_PREW, -- .probe = probe_spi_rdid, -- .probe_timing = TIMING_ZERO, -- .block_erasers = -- { -- { -- .eraseblocks = { {4 * 1024, 1024} }, -- .block_erase = spi_block_erase_20, -- }, { -- .eraseblocks = { {64 * 1024, 64} }, -- .block_erase = spi_block_erase_d8, -- }, { -- .eraseblocks = { {64 * 1024, 64} }, -- .block_erase = spi_block_erase_52, -- }, { -- .eraseblocks = { {4 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_60, -- }, { -- .eraseblocks = { {4 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_c7, -- }, -- }, -- .printlock = spi_prettyprint_status_register_bp3_srwd, -- .unlock = spi_disable_blockprotect_bp3_srwd, -- .write = spi_chip_write_256, -- .read = spi_chip_read, /* Fast read (0x0B) and dual I/O supported */ -- .voltage = {2700, 3600}, -- }, -- -- { -- .vendor = "Macronix", -- .name = "MX25L3273E", -- .bustype = BUS_SPI, -- .manufacture_id = MACRONIX_ID, -- .model_id = MACRONIX_MX25L3205, -- .total_size = 4096, -- .page_size = 256, -- /* OTP: 64B total; enter 0xB1, exit 0xC1 */ -- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, -- .tested = TEST_OK_PREW, -- .probe = probe_spi_rdid, -- .probe_timing = TIMING_ZERO, -- .block_erasers = -- { -- { -- .eraseblocks = { {4 * 1024, 1024} }, -- .block_erase = spi_block_erase_20, -- }, { -- .eraseblocks = { {32 * 1024, 128} }, -- .block_erase = spi_block_erase_52, -- }, { -- .eraseblocks = { {64 * 1024, 64} }, -- .block_erase = spi_block_erase_d8, -- }, { -- .eraseblocks = { {4 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_60, -- }, { -- .eraseblocks = { {4 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_c7, -- }, -- }, -- .printlock = spi_prettyprint_status_register_bp3_srwd, -- .unlock = spi_disable_blockprotect_bp3_srwd, -- .write = spi_chip_write_256, -- .read = spi_chip_read, /* Fast read (0x0B) and dual I/O supported */ -- .voltage = {2700, 3600}, -- }, -- -- { -- .vendor = "Macronix", - .name = "MX25L3235D", - .bustype = BUS_SPI, - .manufacture_id = MACRONIX_ID, -@@ -7817,42 +7630,6 @@ const struct flashchip flashchips[] = { - - { - .vendor = "Macronix", -- .name = "MX25L6405", -- .bustype = BUS_SPI, -- .manufacture_id = MACRONIX_ID, -- .model_id = MACRONIX_MX25L6405, -- .total_size = 8192, -- .page_size = 256, -- /* Has an additional 512B EEPROM sector */ -- .feature_bits = FEATURE_WRSR_WREN, -- .tested = TEST_OK_PREW, -- .probe = probe_spi_rdid, -- .probe_timing = TIMING_ZERO, -- .block_erasers = -- { -- { -- .eraseblocks = { {64 * 1024, 128} }, -- .block_erase = spi_block_erase_20, -- }, { -- .eraseblocks = { {64 * 1024, 128} }, -- .block_erase = spi_block_erase_d8, -- }, { -- .eraseblocks = { {8 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_60, -- }, { -- .eraseblocks = { {8 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_c7, -- } -- }, -- .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6: error flag */ -- .unlock = spi_disable_blockprotect_bp3_srwd, -- .write = spi_chip_write_256, -- .read = spi_chip_read, /* Fast read (0x0B) supported */ -- .voltage = {2700, 3600}, -- }, -- -- { -- .vendor = "Macronix", - .name = "MX25L6405D", - .bustype = BUS_SPI, - .manufacture_id = MACRONIX_ID, -@@ -7889,86 +7666,6 @@ const struct flashchip flashchips[] = { - - { - .vendor = "Macronix", -- .name = "MX25L6406E/MX25L6408E", -- .bustype = BUS_SPI, -- .manufacture_id = MACRONIX_ID, -- .model_id = MACRONIX_MX25L6405, -- .total_size = 8192, -- .page_size = 256, -- /* MX25L6406E supports SFDP */ -- /* OTP: 06E 64B total; enter 0xB1, exit 0xC1 */ -- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, -- .tested = TEST_OK_PREW, -- .probe = probe_spi_rdid, -- .probe_timing = TIMING_ZERO, -- .block_erasers = -- { -- { -- .eraseblocks = { {4 * 1024, 2048} }, -- .block_erase = spi_block_erase_20, -- }, { -- .eraseblocks = { {64 * 1024, 128} }, -- .block_erase = spi_block_erase_52, -- }, { -- .eraseblocks = { {64 * 1024, 128} }, -- .block_erase = spi_block_erase_d8, -- }, { -- .eraseblocks = { {8 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_60, -- }, { -- .eraseblocks = { {8 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_c7, -- } -- }, -- .printlock = spi_prettyprint_status_register_bp3_srwd, -- .unlock = spi_disable_blockprotect_bp3_srwd, -- .write = spi_chip_write_256, -- .read = spi_chip_read, /* Fast read (0x0B), dual I/O read supported */ -- .voltage = {2700, 3600}, -- }, -- -- { -- .vendor = "Macronix", -- .name = "MX25L6436E/MX25L6445E/MX25L6465E/MX25L6473E", -- .bustype = BUS_SPI, -- .manufacture_id = MACRONIX_ID, -- .model_id = MACRONIX_MX25L6405, -- .total_size = 8192, -- .page_size = 256, -- /* supports SFDP */ -- /* OTP: 512B total; enter 0xB1, exit 0xC1 */ -- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, -- .tested = TEST_OK_PREW, -- .probe = probe_spi_rdid, -- .probe_timing = TIMING_ZERO, -- .block_erasers = -- { -- { -- .eraseblocks = { {4 * 1024, 2048} }, -- .block_erase = spi_block_erase_20, -- }, { -- .eraseblocks = { {32 * 1024, 256} }, -- .block_erase = spi_block_erase_52, -- }, { -- .eraseblocks = { {64 * 1024, 128} }, -- .block_erase = spi_block_erase_d8, -- }, { -- .eraseblocks = { {8 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_60, -- }, { -- .eraseblocks = { {8 * 1024 * 1024, 1} }, -- .block_erase = spi_block_erase_c7, -- } -- }, -- .printlock = spi_prettyprint_status_register_bp3_srwd, /* bit6 is quad enable */ -- .unlock = spi_disable_blockprotect_bp3_srwd, -- .write = spi_chip_write_256, -- .read = spi_chip_read, /* Fast read (0x0B) and multi I/O supported */ -- .voltage = {2700, 3600}, -- }, -- -- { -- .vendor = "Macronix", - .name = "MX25L12805D", - .bustype = BUS_SPI, - .manufacture_id = MACRONIX_ID, --- -1.9.1 - -- cgit v1.2.3-70-g09d2 From c8c92c141ed26210275efd5786eba2c1d3cd3ff7 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Fri, 2 Mar 2018 01:50:32 -0500 Subject: Update flashrom target 'lenovobios' patch This patch has simply been updated in order to apply to the flashrom revision currently being used. Leah Rowe has been duly retained as the author of the patch. --- ...bios-adaptation-for-Macronix-and-SST-chips.patch | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/projects/flashrom/patches/lenovobios/0001-Lenovobios-adaptation-for-Macronix-and-SST-chips.patch b/projects/flashrom/patches/lenovobios/0001-Lenovobios-adaptation-for-Macronix-and-SST-chips.patch index 1cb843c9..2a383fd1 100644 --- a/projects/flashrom/patches/lenovobios/0001-Lenovobios-adaptation-for-Macronix-and-SST-chips.patch +++ b/projects/flashrom/patches/lenovobios/0001-Lenovobios-adaptation-for-Macronix-and-SST-chips.patch @@ -1,22 +1,21 @@ -From aa2dd05f61f6ca91212d7f6d4055486af6e01436 Mon Sep 17 00:00:00 2001 -From: Leah Rowe -Date: Fri, 5 Aug 2016 22:40:49 +0200 +From 85eea125194414b6afc8053565bb333f06054421 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Fri, 2 Mar 2018 06:47:34 +0000 Subject: [PATCH] Lenovobios adaptation for Macronix and SST chips -Signed-off-by: Paul Kocialkowski --- flashchips.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/flashchips.c b/flashchips.c -index e5ea181..f3a017c 100644 +index 7f85415..16b166b 100644 --- a/flashchips.c +++ b/flashchips.c -@@ -7454,12 +7454,12 @@ const struct flashchip flashchips[] = { +@@ -7634,12 +7634,12 @@ const struct flashchip flashchips[] = { .name = "MX25L1605D/MX25L1608D/MX25L1673E", .bustype = BUS_SPI, .manufacture_id = MACRONIX_ID, -- .model_id = MACRONIX_MX25L1605, +- .model_id = 0xDEAD, + .model_id = 0x14, .total_size = 2048, .page_size = 256, @@ -27,7 +26,7 @@ index e5ea181..f3a017c 100644 .probe_timing = TIMING_ZERO, .block_erasers = { -@@ -9857,7 +9857,7 @@ const struct flashchip flashchips[] = { +@@ -10442,7 +10442,7 @@ const struct flashchip flashchips[] = { }, .printlock = spi_prettyprint_status_register_bp2_srwd, .unlock = spi_disable_blockprotect, @@ -36,7 +35,7 @@ index e5ea181..f3a017c 100644 .read = spi_chip_read, /* Fast read (0x0B), dual I/O supported */ .voltage = {2700, 3600}, }, -@@ -12150,12 +12150,12 @@ const struct flashchip flashchips[] = { +@@ -12735,12 +12735,12 @@ const struct flashchip flashchips[] = { .name = "SST25VF016B", .bustype = BUS_SPI, .manufacture_id = SST_ID, @@ -51,7 +50,7 @@ index e5ea181..f3a017c 100644 .probe_timing = TIMING_ZERO, .block_erasers = { -@@ -12178,7 +12178,7 @@ const struct flashchip flashchips[] = { +@@ -12763,7 +12763,7 @@ const struct flashchip flashchips[] = { }, .printlock = spi_prettyprint_status_register_sst25vf016, .unlock = spi_disable_blockprotect, @@ -61,5 +60,5 @@ index e5ea181..f3a017c 100644 .voltage = {2700, 3600}, }, -- -2.9.0 +1.9.1 -- cgit v1.2.3-70-g09d2 From a7de3dc83f7ed8f90a5fcc1c4610b58d7319dae9 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Fri, 2 Mar 2018 02:18:50 -0500 Subject: Update flashrom patch for reliable MX25 chip flash This patch has simply been updated in order to apply to the flashrom revision currently being used--with one minor alteration in usage (i.e., the '-m' flag). "consts" has been duly retained as the author of the patch. --- .../patches/0002-Workaround-for-MX25-chips.patch | 81 ++++++++++++++++++++++ .../0005-Workaround-MX25-reliable-operation.patch | 66 ------------------ 2 files changed, 81 insertions(+), 66 deletions(-) create mode 100644 projects/flashrom/patches/0002-Workaround-for-MX25-chips.patch delete mode 100644 projects/flashrom/patches/0005-Workaround-MX25-reliable-operation.patch diff --git a/projects/flashrom/patches/0002-Workaround-for-MX25-chips.patch b/projects/flashrom/patches/0002-Workaround-for-MX25-chips.patch new file mode 100644 index 00000000..de6272c0 --- /dev/null +++ b/projects/flashrom/patches/0002-Workaround-for-MX25-chips.patch @@ -0,0 +1,81 @@ +From 886f1db7edbfc9ef4c9727b4f564c1e7e35d6565 Mon Sep 17 00:00:00 2001 +From: consts +Date: Fri, 2 Mar 2018 07:03:37 +0000 +Subject: [PATCH] Workaround for MX25 chips + +https://notabug.org/libreboot/libreboot/issues/193 +--- + cli_classic.c | 5 +++++ + programmer.h | 1 + + spi.c | 9 +++++++++ + 3 files changed, 15 insertions(+) + +diff --git a/cli_classic.c b/cli_classic.c +index 31f7394..c60168c 100644 +--- a/cli_classic.c ++++ b/cli_classic.c +@@ -62,6 +62,7 @@ static void cli_classic_usage(const char *name) + " -o | --output log output to \n" + " --flash-contents assume flash contents to be \n" + " -L | --list-supported print supported devices\n" ++ " -m | --workaround-mx keep flash busy before sending command\n" + #if CONFIG_PRINT_WIKI == 1 + " -z | --list-supported-wiki print supported devices in wiki syntax\n" + #endif +@@ -136,6 +137,7 @@ int main(int argc, char *argv[]) + {"help", 0, NULL, 'h'}, + {"version", 0, NULL, 'R'}, + {"output", 1, NULL, 'o'}, ++ {"workaround-mx", 0, NULL, 'm'}, + {NULL, 0, NULL, 0}, + }; + +@@ -347,6 +349,9 @@ int main(int argc, char *argv[]) + } + #endif /* STANDALONE */ + break; ++ case 'm': /* --workaround-mx */ ++ workaround_mx = 1; ++ break; + default: + cli_classic_abort_usage(); + break; +diff --git a/programmer.h b/programmer.h +index 139f4fa..f54e690 100644 +--- a/programmer.h ++++ b/programmer.h +@@ -664,6 +664,7 @@ enum ich_chipset { + CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */ + CHIPSET_C620_SERIES_LEWISBURG, + }; ++extern int workaround_mx; /* workaround for MX25* chips, makes flash operations more reliable, less failures */ + + /* ichspi.c */ + #if CONFIG_INTERNAL == 1 +diff --git a/spi.c b/spi.c +index 56f1fdf..4e61d88 100644 +--- a/spi.c ++++ b/spi.c +@@ -30,10 +30,19 @@ + #include "programmer.h" + #include "spi.h" + ++int workaround_mx; /* Make operations with MX25* chips more reliable */ ++ + int spi_send_command(struct flashctx *flash, unsigned int writecnt, + unsigned int readcnt, const unsigned char *writearr, + unsigned char *readarr) + { ++ if (workaround_mx) { ++ const unsigned char cmd[JEDEC_READ_OUTSIZE] = {JEDEC_READ, 0, 0, 0}; ++ unsigned char buf[256]; ++ /* keep flash busy for some time, keep CS warm before sending actual command */ ++ flash->mst->spi.command(flash, sizeof(cmd), sizeof(buf), cmd, buf); ++ } ++ /* actual command */ + return flash->mst->spi.command(flash, writecnt, readcnt, writearr, + readarr); + } +-- +1.9.1 + diff --git a/projects/flashrom/patches/0005-Workaround-MX25-reliable-operation.patch b/projects/flashrom/patches/0005-Workaround-MX25-reliable-operation.patch deleted file mode 100644 index 472afd30..00000000 --- a/projects/flashrom/patches/0005-Workaround-MX25-reliable-operation.patch +++ /dev/null @@ -1,66 +0,0 @@ -diff --git a/cli_classic.c b/cli_classic.c -index 0a09cfd..9eeafe1 100644 ---- a/cli_classic.c -+++ b/cli_classic.c -@@ -61,6 +61,7 @@ static void cli_classic_usage(const char *name) - " -i | --image only flash image from flash layout\n" - " -o | --output log output to \n" - " -L | --list-supported print supported devices\n" -+ " | --workaround-mx keep flash busy before sending command\n" - #if CONFIG_PRINT_WIKI == 1 - " -z | --list-supported-wiki print supported devices in wiki syntax\n" - #endif -@@ -130,6 +131,7 @@ int main(int argc, char *argv[]) - {"help", 0, NULL, 'h'}, - {"version", 0, NULL, 'R'}, - {"output", 1, NULL, 'o'}, -+ {"workaround-mx", 0, NULL, 0x0101}, - {NULL, 0, NULL, 0}, - }; - -@@ -337,6 +339,9 @@ int main(int argc, char *argv[]) - } - #endif /* STANDALONE */ - break; -+ case 0x0101: /* --workaround-mx */ -+ workaround_mx = 1; -+ break; - default: - cli_classic_abort_usage(); - break; -diff --git a/programmer.h b/programmer.h -index 1a6216a..6f97cfc 100644 ---- a/programmer.h -+++ b/programmer.h -@@ -650,6 +650,7 @@ enum ich_chipset { - CHIPSET_8_SERIES_WELLSBURG, - CHIPSET_9_SERIES_WILDCAT_POINT, - }; -+extern int workaround_mx; /* workaround for MX25* chips, makes flash operations more reliable, less failures */ - - /* ichspi.c */ - #if CONFIG_INTERNAL == 1 -diff --git a/spi.c b/spi.c -index 894f73f..05aa5d0 100644 ---- a/spi.c -+++ b/spi.c -@@ -30,10 +30,19 @@ - #include "programmer.h" - #include "spi.h" - -+int workaround_mx; /* Make operations with MX25* chips more reliable */ -+ - int spi_send_command(struct flashctx *flash, unsigned int writecnt, - unsigned int readcnt, const unsigned char *writearr, - unsigned char *readarr) - { -+ if (workaround_mx) { -+ const unsigned char cmd[JEDEC_READ_OUTSIZE] = {JEDEC_READ, 0, 0, 0}; -+ unsigned char buf[256]; -+ /* keep flash busy for some time, keep CS warm before sending actual command */ -+ flash->mst->spi.command(flash, sizeof(cmd), sizeof(buf), cmd, buf); -+ } -+ /* actual command */ - return flash->mst->spi.command(flash, writecnt, readcnt, writearr, - readarr); - } -- cgit v1.2.3-70-g09d2 From 4606722c5818b0927c1521293176cee522969258 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 14 Mar 2018 01:14:45 +0000 Subject: Update download page to include the 16-digit GPG key (no pull request needed) This was brought to our attention by attila_lendvai on #libreboot IRC. Essentially, the previous instruction was vulnerable to potential collision attacks. With this new instruction, it should be a bit safer. Since this is urgent, no pull request was issued. This has been committed to the repository directly, with consent from and_who on IRC. --- www/download.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/www/download.md b/www/download.md index 5edaa4f4..245e1154 100644 --- a/www/download.md +++ b/www/download.md @@ -17,7 +17,9 @@ GPG signing key Releases are signed with GPG. - $ gpg --recv-keys 0x05E8C5B2 + gpg --recv-keys 0x969A979505E8C5B2 + +Full key fingerprint: CDC9 CAE3 2CB4 B7FC 84FD C804 969A 9795 05E8 C5B2 The GPG key can also be downloaded with this exported dump of the pubkey: [lbkey.asc](lbkey.asc). -- cgit v1.2.3-70-g09d2 From aa0819c63560f66261dc239cb41c1650bdaca2c4 Mon Sep 17 00:00:00 2001 From: Swift Geek Date: Wed, 14 Mar 2018 19:43:15 +0000 Subject: Rectify VBIOS section --- www/faq.md | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/www/faq.md b/www/faq.md index 610f8093..fca20e04 100644 --- a/www/faq.md +++ b/www/faq.md @@ -695,23 +695,23 @@ project. ### External GPUs -The Video BIOS is present on most video hardware. On all current -libreboot systems, this is implemented using free software. The Video -BIOS is responsible for initializing any sort of visual display; without -it, you'd have what's called a *headless* system. - -For integrated graphics, the VBIOS is usually embedded as an *option -ROM* in the main boot firmware. For external graphics, the VBIOS is +The Video BIOS is present on most video cards. For integrated graphics, +the VBIOS (special kind of OptionROM) is usually embedded +in the main boot firmware. For external graphics, the VBIOS is usually on the graphics card itself. This is usually proprietary; the -only difference is that SeaBIOS executes it (alternatively, you embed it +only difference is that SeaBIOS can execute it (alternatively, you embed it in a coreboot ROM image and have coreboot executes it, if you use a different payload, such as GRUB). -We're going to tentatively say no, they're not OK. Unless you're -actively working to replace the VBIOS, or find out how to get a visual -display without it (possible in some cases, if the kernel driver can be -modified to work without it, possibly only needing certain -non-executable data). +On current libreboot systems, instead of VBIOS, coreboot native GPU init is used, +which is currently only implemented for Intel GPUs. +Other cards with proper KMS drivers can be initialized once Linux boots, +but copy of VBIOS may be still needed to fetch proper VRAM frequency +and other similar parameters (without executing VBIOS code). + +In configurations where SeaBIOS and native GPU init are used together, +a special shim VBIOS is added that uses coreboot linear framebuffer. + ### EC (embedded controller) firmware -- cgit v1.2.3-70-g09d2 From 44475c78bef2e56de98191b385021343b99a6ac6 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Thu, 15 Mar 2018 17:37:09 -0400 Subject: Remove dead mirrors from mirror list --- www/download.md | 9 --------- 1 file changed, 9 deletions(-) diff --git a/www/download.md b/www/download.md index 245e1154..33116a1e 100644 --- a/www/download.md +++ b/www/download.md @@ -51,9 +51,6 @@ Project, USA) (elgrande74.net, France) - (nephelai.info, New Zealand) -(formerly nephelai.zanity.net/mirror/libreboot) - (koddos.net, Netherlands) RSYNC mirrors {#rsync} @@ -70,8 +67,6 @@ UK) (linux.ro, Romania) - - (koddos.net, Netherlands) Are you running a mirror? Contact the libreboot project, and the link will be @@ -92,8 +87,6 @@ if using HTTPS. (in-berlin.de, Germany) - (mirror.si, Slovenia) - (swordarmor.fr, France) FTP mirrors {#ftp} @@ -106,8 +99,6 @@ of Kent, UK) (linux.ro, Romania) - (mirror.si, Slovenia) - Statically linked ------------------ -- cgit v1.2.3-70-g09d2 From a965c22d9bad61a04898d4f2c7927763241ace48 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Fri, 16 Mar 2018 21:23:32 -0400 Subject: Use current mirror URI for swordarmor.fr --- www/download.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/www/download.md b/www/download.md index 33116a1e..4b24ec81 100644 --- a/www/download.md +++ b/www/download.md @@ -53,6 +53,8 @@ Project, USA) (koddos.net, Netherlands) + (swordarmor.fr, France) + RSYNC mirrors {#rsync} ------------- @@ -87,8 +89,6 @@ if using HTTPS. (in-berlin.de, Germany) - (swordarmor.fr, France) - FTP mirrors {#ftp} ----------- -- cgit v1.2.3-70-g09d2 From 7b3c11c99c955d1cdb00951ef47e5516bbf621a4 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 18 Mar 2018 14:33:58 +0000 Subject: update leah's irc nick on the site (no pull request needed for this) --- www/conduct.md | 2 +- www/management.md | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/www/conduct.md b/www/conduct.md index 313321c0..35f8bac4 100644 --- a/www/conduct.md +++ b/www/conduct.md @@ -84,7 +84,7 @@ reported by contacting one of the moderators privately via IRC private message * Andrew Robbins: **and\_who** on Freenode, email * Jason Self: **jxself** on Freenode -* Leah Rowe: **\_4of7** on Freenode, email +* Leah Rowe: **unoccupied** on Freenode, email * Paul Kocialkowski: **paulk-X** Freenode (X is variable, for this person, email check in the channel) diff --git a/www/management.md b/www/management.md index b05a1826..ce5eaf9e 100644 --- a/www/management.md +++ b/www/management.md @@ -32,7 +32,7 @@ In alphabetical order: - Paul Kocialkowski is a core developer. IRC nick **paulk-X** (**X** is variable, and changes over time), email - Leah Rowe is a core developer (and project founder). IRC nick - **\_4of7**, email + **unoccupied**, email - Swift Geek is a core developer. IRC nick **swiftgeek**, email -- cgit v1.2.3-70-g09d2 From 1a791d9519e50fdd52234c22f8b8593cf7947a2f Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 18 Mar 2018 14:41:50 +0000 Subject: fix format of email addresses on conduct and management pages --- www/conduct.md | 11 +++++++---- www/management.md | 9 +++++---- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/www/conduct.md b/www/conduct.md index 35f8bac4..10dac700 100644 --- a/www/conduct.md +++ b/www/conduct.md @@ -82,13 +82,16 @@ Instances of abusive, harassing, or otherwise unacceptable behavior may be reported by contacting one of the moderators privately via IRC private message (see list below): -* Andrew Robbins: **and\_who** on Freenode, email +* Andrew Robbins: **and\_who** on Freenode, email + [andrew@libreboot.org](mailto:andrew@libreboot.org) * Jason Self: **jxself** on Freenode -* Leah Rowe: **unoccupied** on Freenode, email +* Leah Rowe: **unoccupied** on Freenode, email + [leah@libreboot.org](mailto:leah@libreboot.org) * Paul Kocialkowski: **paulk-X** Freenode (X is variable, for this - person, email + person, email [paul@libreboot.org](mailto:paul@libreboot.org) check in the channel) -* Swift Geek: **swiftgeek** on Freenode, email +* Swift Geek: **swiftgeek** on Freenode, email + [swiftgeek@libreboot.org](mailto:swiftgeek@libreboot.org) If the complaint is for abuses on the Libreboot subreddit at [r/libreboot](https://www.reddit.com/r/libreboot/) then there are a separate diff --git a/www/management.md b/www/management.md index ce5eaf9e..cd990feb 100644 --- a/www/management.md +++ b/www/management.md @@ -28,13 +28,14 @@ List of members in the core management team In alphabetical order: - Andrew Robbins is a core developer. IRC nick **and\_who**, email - + [andrew@libreboot.org](mailto:andrew@libreboot.org) - Paul Kocialkowski is a core developer. IRC nick **paulk-X** - (**X** is variable, and changes over time), email + (**X** is variable, and changes over time), email + [paul@libreboot.org](mailto:paul@libreboot.org) - Leah Rowe is a core developer (and project founder). IRC nick - **unoccupied**, email + **unoccupied**, email [leah@libreboot.org](mailto:leah@libreboot.org) - Swift Geek is a core developer. IRC nick **swiftgeek**, email - + [swiftgeek@libreboot.org](mailto:swiftgeek@libreboot.org) Generally, the people on this list have these responsibilities: -- cgit v1.2.3-70-g09d2 From 25655d86cf10419633147d5803085d27c98333e8 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 18 Mar 2018 14:42:28 +0000 Subject: remove jxself from conduct/management pages - he quit the channel months ago --- www/conduct.md | 1 - www/management.md | 1 - 2 files changed, 2 deletions(-) diff --git a/www/conduct.md b/www/conduct.md index 10dac700..baaf45c9 100644 --- a/www/conduct.md +++ b/www/conduct.md @@ -84,7 +84,6 @@ reported by contacting one of the moderators privately via IRC private message * Andrew Robbins: **and\_who** on Freenode, email [andrew@libreboot.org](mailto:andrew@libreboot.org) -* Jason Self: **jxself** on Freenode * Leah Rowe: **unoccupied** on Freenode, email [leah@libreboot.org](mailto:leah@libreboot.org) * Paul Kocialkowski: **paulk-X** Freenode (X is variable, for this diff --git a/www/management.md b/www/management.md index cd990feb..b4850a6c 100644 --- a/www/management.md +++ b/www/management.md @@ -58,7 +58,6 @@ Other IRC channel moderators: - IRC nick **specing** on the Libreboot IRC channel. - IRC nick **pizzaiolo** on the Libreboot IRC channel. -- IRC nick **jxself** on the Libreboot IRC channel. Additionally, Libreboot has a separate set of operators on the subreddit r/libreboot. Check Reddit for more information. Actions taken by moderators -- cgit v1.2.3-70-g09d2 From 89580eeffcd0ce3bde66684a8c879a7cfa79d30a Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 18 Mar 2018 14:58:34 +0000 Subject: FAQ entry: note about 16-pin soic clip on 8-pin chip --- www/faq.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/www/faq.md b/www/faq.md index 610f8093..edcb649a 100644 --- a/www/faq.md +++ b/www/faq.md @@ -566,6 +566,9 @@ SPI flash chips can be programmed with the [BeagleBone Black](../docs/install/bbb_setup.md) or the [Raspberry Pi](../docs/install/rpi_setup.md). +It's possible to use a 16-pin SOIC test clip on an 8-pin SOIC chip, if you +align the pins properly. The connection is generally more sturdy. + How do I set a boot password? ------------------------------------------------------------------- -- cgit v1.2.3-70-g09d2 From a78cc7c3ff769202db8ad1455c32f2394b3bb2e3 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sun, 18 Mar 2018 14:52:21 +0000 Subject: management: remove another inactive irc contributor. also general clean-up --- www/conduct.md | 6 +----- www/management.md | 3 ++- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/www/conduct.md b/www/conduct.md index baaf45c9..69dc0ae8 100644 --- a/www/conduct.md +++ b/www/conduct.md @@ -95,11 +95,7 @@ reported by contacting one of the moderators privately via IRC private message If the complaint is for abuses on the Libreboot subreddit at [r/libreboot](https://www.reddit.com/r/libreboot/) then there are a separate group of moderators whom you can contact, via private message on the Reddit -website: - -* hexacat -* pizzaiolo\_ -* libreleah +website. The subreddit has a public list of moderators on it. If you deviate from these guidelines, make sure that it is with good reason. Treatment of each case will be handled pragmatically, on a case-by-case basis. diff --git a/www/management.md b/www/management.md index b4850a6c..f09ce9b7 100644 --- a/www/management.md +++ b/www/management.md @@ -57,7 +57,8 @@ These people are not part of core management, but still have influence. Other IRC channel moderators: - IRC nick **specing** on the Libreboot IRC channel. -- IRC nick **pizzaiolo** on the Libreboot IRC channel. + +specing occasionally provides assistance, and moderates the IRC channel. Additionally, Libreboot has a separate set of operators on the subreddit r/libreboot. Check Reddit for more information. Actions taken by moderators -- cgit v1.2.3-70-g09d2 From 81c76feaebe09c382e0fbfd42e358fc6710d47eb Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Tue, 20 Mar 2018 19:45:38 +0100 Subject: Remove explody bits from guide --- docs/install/rpi_setup.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/install/rpi_setup.md b/docs/install/rpi_setup.md index e74432d4..e46191e7 100644 --- a/docs/install/rpi_setup.md +++ b/docs/install/rpi_setup.md @@ -283,10 +283,10 @@ your PI. Power on your Pi, and run the following. Ensure you swap out "your\_chip\_name" with the proper name/model of your chip. Check that it can be read successfully. If you cannot read the chip and receive an -error similar to "no EEPROM Detected" or "0x0 Chip detected" then -you may want to try powering off your PI, and switching the two pins -which are connected to the IO ports. I.E. Connect pins (clip)8 to (pi)19 -and pins (clip)15 to (pi)21 +error similar to "no EEPROM Detected" then +you may want to make sure that MISO/MOSI are not swapped around, check +with multimeter whether voltage is right and that ground is connected +between "programmer" and target. pi# cd ~/flashrom -- cgit v1.2.3-70-g09d2 From 3310d42576cf6c24c0a62e83febb2b26481ff702 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 21 Mar 2018 11:46:28 +0000 Subject: News post about Libreboot installation workshop at FSF LibrePlanet 2018 --- www/news/MANIFEST | 1 + www/news/libreplanet2018-workshop.md | 96 ++++++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+) create mode 100644 www/news/libreplanet2018-workshop.md diff --git a/www/news/MANIFEST b/www/news/MANIFEST index 45bc9cae..4f588538 100644 --- a/www/news/MANIFEST +++ b/www/news/MANIFEST @@ -1,3 +1,4 @@ +news/libreplanet2018-workshop.md news/release-testing-20171221.md news/lenovo-recall.md news/alyssa-resignation.md diff --git a/www/news/libreplanet2018-workshop.md b/www/news/libreplanet2018-workshop.md new file mode 100644 index 00000000..88d338b5 --- /dev/null +++ b/www/news/libreplanet2018-workshop.md @@ -0,0 +1,96 @@ +% Libreboot installation workshop at FSF LibrePlanet 2018 conference +% Leah Rowe +% 21 March 2018 + +LibrePlanet is the annual conference held by the Free Software Foundation in +Boston, MA, USA. This year, it's being held at MIT university on March 24th +and 25th. More details about it are here: + + +The FSF isn't officially hosting a libreboot workshop at libreplanet +this year. At the 2015 and 2016 LibrePlanet conference, there were workshops +there run by myself and Patrick McDermott, a former member of the Libreboot +project. The FSF has confirmed that they don't have a dedicated room for it +this year, due to increasing number of conference goers. + +Therefore, an unofficial workshop is being set up. I've already issued a news +post about this on the libreplanet-discuss mailing list: + + +With John Sullivan's blessing: + + +If you, the reader, are attending LibrePlanet this year, and you would like to +get a libreboot system flashed for you, then take it with you to LibrePlanet. +There will be knowledgeable people there who can flash libreboot for you. + +Find one of the people on the list below (list will be updated if more people +volunteer to flash). If it's Kurt, they'll flash for you at the technoethical +booth. If it's someone else, they can take you into the speakers lounge - does +not matter if they're not a speaker. John Sullivan of FSF has approved this. +There are tables, chairs and power sockets in that room. +There are also tables and chairs outside the speakers lounge, in the common +area at the conference, but I highly recommend using the speakers lounge. +That's where I took people, on Libreplanet 2015 and 2016 :) +It's really comfy in there. + +John Sullivan of FSF has also confirmed that that there is a dedicated +*alcohol-free social and hacking time* at the FSF office on Saturday 24th +March, between 1900 to 2130 hours. You could also flash someones laptop for +them there, in the conference room at the FSF, or on a table outside. Or the +sysadmin room, if that's OK with them. + +I've been asking around. The following people have confirmed so far that they +will be providing Libreboot flashing services at the conference: + +- Kurt from Technoethical, an FSF-endorsed libreboot hardware seller. They will + also have their own samples. They'll be at the Technoethical booth there. + IRC nick sensiblemn\_ or sensiblemn on #libreboot IRC +- zyliwax from #libreboot IRC - has not committed fully, but is *very likely + to attend*, in their own words. +- Patrick McDermott (pehjota) of Libiquity. I've emailed them to ask, + though I'm not sure if they'll be there - they're usually there though, each + year. +- You could also find an FSF sysadmin and ask them to flash Libreboot for you. + +I would be grateful if anyone else would also be willing to provide flashing. +I myself am not attending the conference physically, unfortunately. + +See mailing list post for more info. If you would like to help Kurt and +zyliwax out, please either reply to that mailing list post on +libreplanet-discuss or email me directly: +[leah@libreboot.org](mailto:leah@libreboot.org) and I'll add your name in +the above list. + +Basically, all you need for flashing someones laptop at the conference is: + +- Portable SPI flasher (USB powered. SSH into it via your laptop, use the SPI + flasher's own 3v3, etc). Make sure to use the workaround-mx patch on + flashrom, so that you can use --workaround-mx on Macronix chips, if flashing + an X200, otherwise flashing will be unreliable (see mailing list post linked + above) - portability is important, in case you sit down with someone in + a place without power sockets. + See guides on libreboot.org for setting up SPI flashers, but ignore the notes + about external PSUs and instead just wire up the flasher's own 3v3 connection. + The workaround-mx patch is here: + + apply this on flashrom src and build with that. To use it, just pass the + --workaround-mx option in flashrom. +- Screwdrivers (phillips head 0 *and* 00 - sometimes labelled PH0 or PH00, + respectively) +- Thermal paste and thermal cleaning material, for T400 flashing + - arctic mx-4 paste recommended. For cleaning material, use anti-static cloth + and isopropyl alcohol - as pure as possible! ideally close to 100%! 70% + rubbing alcohol is common in USA, and not suitable for electronics +- Anti-ESD wrist/ankle strap, to protect against damage fro electrostatic + discharge when working with circuit boards. + +Optionally: + +- Bring DIP8 25xx SPI chips with libreboot, for ASUS KCMA-D8 or KGPE-D16, for the + conference goer to put in their D8/D16 when they get home. Also PLCC32 LPC + 1MB (or bigger, with padding at the beginning) chips for ASUS KFSN4-DRE +- Soldering equipment (knife tip, hot air, etc) for X200T flashing. NOTE: FSF has + soldering equipment in their offire, you could ask them to lend it to you + if you're flashing a laptop there at the FSF office. NOTE2: Kurt from Techno + is also bringing soldering equipment. -- cgit v1.2.3-70-g09d2 From 0d362962c8aaa0318a3d84f3fe40f4643da598b2 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 21 Mar 2018 17:16:49 +0000 Subject: fix typos in previous commit: offire changed to office. fro changed to from --- www/news/libreplanet2018-workshop.md | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/www/news/libreplanet2018-workshop.md b/www/news/libreplanet2018-workshop.md index 88d338b5..2ffc062e 100644 --- a/www/news/libreplanet2018-workshop.md +++ b/www/news/libreplanet2018-workshop.md @@ -7,7 +7,7 @@ Boston, MA, USA. This year, it's being held at MIT university on March 24th and 25th. More details about it are here: -The FSF isn't officially hosting a libreboot workshop at libreplanet +The FSF isn't officially hosting a Libreboot workshop at LibrePlanet this year. At the 2015 and 2016 LibrePlanet conference, there were workshops there run by myself and Patrick McDermott, a former member of the Libreboot project. The FSF has confirmed that they don't have a dedicated room for it @@ -21,29 +21,29 @@ With John Sullivan's blessing: If you, the reader, are attending LibrePlanet this year, and you would like to -get a libreboot system flashed for you, then take it with you to LibrePlanet. -There will be knowledgeable people there who can flash libreboot for you. +get a Libreboot system flashed for you, then take it with you to LibrePlanet. +There will be knowledgeable people there who can flash Libreboot for you. Find one of the people on the list below (list will be updated if more people -volunteer to flash). If it's Kurt, they'll flash for you at the technoethical -booth. If it's someone else, they can take you into the speakers lounge - does -not matter if they're not a speaker. John Sullivan of FSF has approved this. +volunteer to flash). If it's Kurt, they'll flash for you at the Technoethical +booth. If it's someone else, they can take you into the speakers' lounge (it does +not matter if they're not a speaker). John Sullivan of FSF has approved this. There are tables, chairs and power sockets in that room. -There are also tables and chairs outside the speakers lounge, in the common -area at the conference, but I highly recommend using the speakers lounge. +There are also tables and chairs outside the speakers' lounge, in the common +area at the conference, but I highly recommend using the speakers' lounge. That's where I took people, on Libreplanet 2015 and 2016 :) It's really comfy in there. John Sullivan of FSF has also confirmed that that there is a dedicated *alcohol-free social and hacking time* at the FSF office on Saturday 24th -March, between 1900 to 2130 hours. You could also flash someones laptop for +March, between 1900-2130 (7-9:30 PM). You could also flash someone's laptop for them there, in the conference room at the FSF, or on a table outside. Or the sysadmin room, if that's OK with them. I've been asking around. The following people have confirmed so far that they will be providing Libreboot flashing services at the conference: -- Kurt from Technoethical, an FSF-endorsed libreboot hardware seller. They will +- Kurt from Technoethical, an FSF-endorsed Libreboot hardware seller. They will also have their own samples. They'll be at the Technoethical booth there. IRC nick sensiblemn\_ or sensiblemn on #libreboot IRC - zyliwax from #libreboot IRC - has not committed fully, but is *very likely @@ -62,11 +62,11 @@ libreplanet-discuss or email me directly: [leah@libreboot.org](mailto:leah@libreboot.org) and I'll add your name in the above list. -Basically, all you need for flashing someones laptop at the conference is: +Basically, all you need for flashing someone's laptop at the conference is: - Portable SPI flasher (USB powered. SSH into it via your laptop, use the SPI flasher's own 3v3, etc). Make sure to use the workaround-mx patch on - flashrom, so that you can use --workaround-mx on Macronix chips, if flashing + flashrom, so that you can use `--workaround-mx` on Macronix chips, if flashing an X200, otherwise flashing will be unreliable (see mailing list post linked above) - portability is important, in case you sit down with someone in a place without power sockets. @@ -75,22 +75,22 @@ Basically, all you need for flashing someones laptop at the conference is: The workaround-mx patch is here: apply this on flashrom src and build with that. To use it, just pass the - --workaround-mx option in flashrom. + `--workaround-mx` option in flashrom. - Screwdrivers (phillips head 0 *and* 00 - sometimes labelled PH0 or PH00, respectively) - Thermal paste and thermal cleaning material, for T400 flashing - arctic mx-4 paste recommended. For cleaning material, use anti-static cloth and isopropyl alcohol - as pure as possible! ideally close to 100%! 70% rubbing alcohol is common in USA, and not suitable for electronics -- Anti-ESD wrist/ankle strap, to protect against damage fro electrostatic +- Anti-ESD wrist/ankle strap, to protect against damage from electrostatic discharge when working with circuit boards. Optionally: -- Bring DIP8 25xx SPI chips with libreboot, for ASUS KCMA-D8 or KGPE-D16, for the +- Bring DIP8 25xx SPI chips with Libreboot, for ASUS KCMA-D8 or KGPE-D16, for the conference goer to put in their D8/D16 when they get home. Also PLCC32 LPC 1MB (or bigger, with padding at the beginning) chips for ASUS KFSN4-DRE - Soldering equipment (knife tip, hot air, etc) for X200T flashing. NOTE: FSF has - soldering equipment in their offire, you could ask them to lend it to you - if you're flashing a laptop there at the FSF office. NOTE2: Kurt from Techno - is also bringing soldering equipment. + soldering equipment in their office, you could ask them to lend it to you + if you're flashing a laptop there at the FSF office. NOTE2: Kurt from + Technoethical is also bringing soldering equipment. -- cgit v1.2.3-70-g09d2 From 4b4e5388203999360aeddfa1c56cf75b79c8c5bb Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 21 Mar 2018 18:06:19 +0000 Subject: one more fix on news post: Libreplanet changed to LibrePlanet --- www/news/libreplanet2018-workshop.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/www/news/libreplanet2018-workshop.md b/www/news/libreplanet2018-workshop.md index 2ffc062e..7ea4f729 100644 --- a/www/news/libreplanet2018-workshop.md +++ b/www/news/libreplanet2018-workshop.md @@ -31,7 +31,7 @@ not matter if they're not a speaker). John Sullivan of FSF has approved this. There are tables, chairs and power sockets in that room. There are also tables and chairs outside the speakers' lounge, in the common area at the conference, but I highly recommend using the speakers' lounge. -That's where I took people, on Libreplanet 2015 and 2016 :) +That's where I took people, on LibrePlanet 2015 and 2016 :) It's really comfy in there. John Sullivan of FSF has also confirmed that that there is a dedicated -- cgit v1.2.3-70-g09d2 From 6311c732dd61a452020c7e8107f2cbb6230a4c9e Mon Sep 17 00:00:00 2001 From: zyliwax Date: Wed, 21 Mar 2018 14:32:41 -0400 Subject: Update FAQ to provide answers regarding activity and status of upcoming release. --- www/faq.md | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/www/faq.md b/www/faq.md index fca20e04..d32901d2 100644 --- a/www/faq.md +++ b/www/faq.md @@ -6,6 +6,74 @@ x-toc-enable: true Important issues ================ +Is the Libreboot project still active? +------------------------------------------- + +Yes! Please check out [the git +repository](https://notabug.org/libreboot/libreboot) for the extensive work +contributed to the project since the previous release. + +So when is the next version of Libreboot coming out? +------------------------------------------------------- + +Short answer: When it is ready. With your help, this will be sooner rather than +later! Read on to find out where help is most needed. + +Long answer: The new release will be ready when the build system has all +outstanding bugs fixed, allowing it to Libreboot ROM image files for all +supported platforms without reporting any major errors. Once these ROM files are +built, it must be possible to flash them onto every supported platform. All +platforms must then be able to initialize all essential hardware from the code +in the ROM files, then ultimately reach execution the included payload. + +The first obstacle to overcome in this setup is completing the code for the new +build system. Please check out [the git +repository](https://notabug.org/libreboot/libreboot), look over the code for the +build system, and attempt to run the build script for as many platforms as you +can. Document whatever problems you encounter while doing so on [the bug +tracker](https://notabug.org/libreboot/libreboot/issues). If you have strong +knowledge of shell scripting, look at the code yourself and attempt to resolve +whatever the problem may be. At the very least, you can use your investigation +of the code to provide information on your bug report that will help others +determine the proper fix. If you *don't* receive any errors, you should end up +with a Libreboot ROM file! The next paragraph will cover what to do next. + +Once the build system can produce ROM files for any given target, the next step +in preparing for release is testing the ROM files on actual hardware. First, +back up your existing firmware: doing so internally using `flashrom -p internal +-r backup.rom` is probably the most convenient method, though you are welcome to +do so externally as well by following the factory ROM backup procedure for your +platform. You will very likely need this backup since you are testing the new +release, which will have unknown bugs! You will want to have external flashing +equipment handy to flash your backup ROM back onto the device. + +Once you have the backup ready, follow [the on-site +instructions](https://libreboot.org/docs/install/) to flash the new ROM file to +its appropriate hardware platform, then (re)boot your computer. You should +expect to encounter problems! This is new software which needs your testing +support! Document those problems as clearly as possible on [the bug +tracker](https://notabug.org/libreboot/libreboot/issues) to inform the community +of their existence. If you have the technical know-how, try to fix whatever +problems you encounter and whatever other user-submitted bugs you think you can +find. + +You may also get lucky and reach your device payload, in which case: +congratulations! Please document your success on [the bug +tracker](https://notabug.org/libreboot/libreboot/issues) and proceed to test the +capabilities of your payload. When you are done testing, or if the new ROM file +renders your system unbootable, use your external flashing equipment to flash +your backup ROM back to your BIOS chip. + +Other areas where you can help prepare the next release include: porting other +boards from coreboot to Libreboot by removing their dependencies on non-free +components to boot and incorporating them into the build system, telling your +technically skilled friends about Libreboot to encourage their participation, +and offering your devices for testing once the build system reaches maturity. +You can list yourself as a volunteer along with the devices on + +With everyone's help, a new Libreboot release will come sooner rather than +later. + What version of libreboot do I have? ---------------------------------------------------------------- -- cgit v1.2.3-70-g09d2 From 07fbe40312c6827604986476e1566a95eec4af14 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 21 Mar 2018 19:18:16 +0000 Subject: Improvements on zyliwax's FAQ submission: re-write for further clarity --- www/faq.md | 109 +++++++++++++++++++++++++++---------------------------------- 1 file changed, 49 insertions(+), 60 deletions(-) diff --git a/www/faq.md b/www/faq.md index d32901d2..78f79016 100644 --- a/www/faq.md +++ b/www/faq.md @@ -9,70 +9,59 @@ Important issues Is the Libreboot project still active? ------------------------------------------- -Yes! Please check out [the git -repository](https://notabug.org/libreboot/libreboot) for the extensive work -contributed to the project since the previous release. +Yes! The [git repository](https://notabug.org/libreboot/libreboot) shows all of +the work that we're currently doing. Libreboot is quite active. So when is the next version of Libreboot coming out? ------------------------------------------------------- -Short answer: When it is ready. With your help, this will be sooner rather than -later! Read on to find out where help is most needed. - -Long answer: The new release will be ready when the build system has all -outstanding bugs fixed, allowing it to Libreboot ROM image files for all -supported platforms without reporting any major errors. Once these ROM files are -built, it must be possible to flash them onto every supported platform. All -platforms must then be able to initialize all essential hardware from the code -in the ROM files, then ultimately reach execution the included payload. - -The first obstacle to overcome in this setup is completing the code for the new -build system. Please check out [the git -repository](https://notabug.org/libreboot/libreboot), look over the code for the -build system, and attempt to run the build script for as many platforms as you -can. Document whatever problems you encounter while doing so on [the bug -tracker](https://notabug.org/libreboot/libreboot/issues). If you have strong -knowledge of shell scripting, look at the code yourself and attempt to resolve -whatever the problem may be. At the very least, you can use your investigation -of the code to provide information on your bug report that will help others -determine the proper fix. If you *don't* receive any errors, you should end up -with a Libreboot ROM file! The next paragraph will cover what to do next. - -Once the build system can produce ROM files for any given target, the next step -in preparing for release is testing the ROM files on actual hardware. First, -back up your existing firmware: doing so internally using `flashrom -p internal --r backup.rom` is probably the most convenient method, though you are welcome to -do so externally as well by following the factory ROM backup procedure for your -platform. You will very likely need this backup since you are testing the new -release, which will have unknown bugs! You will want to have external flashing -equipment handy to flash your backup ROM back onto the device. - -Once you have the backup ready, follow [the on-site -instructions](https://libreboot.org/docs/install/) to flash the new ROM file to -its appropriate hardware platform, then (re)boot your computer. You should -expect to encounter problems! This is new software which needs your testing -support! Document those problems as clearly as possible on [the bug -tracker](https://notabug.org/libreboot/libreboot/issues) to inform the community -of their existence. If you have the technical know-how, try to fix whatever -problems you encounter and whatever other user-submitted bugs you think you can -find. - -You may also get lucky and reach your device payload, in which case: -congratulations! Please document your success on [the bug -tracker](https://notabug.org/libreboot/libreboot/issues) and proceed to test the -capabilities of your payload. When you are done testing, or if the new ROM file -renders your system unbootable, use your external flashing equipment to flash -your backup ROM back to your BIOS chip. - -Other areas where you can help prepare the next release include: porting other -boards from coreboot to Libreboot by removing their dependencies on non-free -components to boot and incorporating them into the build system, telling your -technically skilled friends about Libreboot to encourage their participation, -and offering your devices for testing once the build system reaches maturity. -You can list yourself as a volunteer along with the devices on - -With everyone's help, a new Libreboot release will come sooner rather than -later. +Short answer: It's out when it's out. If you want to help out and submit +patches, refer to [the Git page](git.md). + +We don't issue ETAs. + +Long answer: + +We've been re-writing the entire Libreboot build system from scratch, since +the previous release. This has taken longer than we expected, but the new +build system is reaching maturity. We are polishing it. + +Once the new build system is stable, our next priority is ensuring that all +currently supported build targets build properly in Libreboot. + +After that, the priority is to make sure that all current boards in Libreboot +use the most up to date revision of coreboot, with all of the most recent fixes +and improvements. Testing those boards will then be a matter of peer review, +reaching out to the entire community via alpha/beta/RC releases. + +Generally, all major release-blocking issues must be addressed before a new +release can be issued. See: + + +The most important tasks now are as follows: + +- Study the build system of Libreboot (written in BASH), and make fixes to it. +- Work on new improvements and help with testing once ROMs build for all + boards, when the build system is stable. +- In particular, there are several new boards in coreboot that we can add to + Libreboot, as documented on the Libreboot bug tracker. These will also have + to be added, and fully tested. Instructions for setting up hardware-based + flashing tools can be found in + [the Libreboot installation guides](docs/install/) +- Bugs! Report bugs! +- A few new board ports will also come in handy ;) + If you've got the skills, we'd really appreciate that. Port them to coreboot + first, or make existing coreboot targets work without binary blobs. + +More generally: + +- Tell your friends about Libreboot! Libreboot wants to liberate as many people + as possible. +- If you have ways to improve the documentation, you can do that too. + Refer to [the Git page](git.md) for instructions on submitting patches to the + documentation. +- Encourage companies, or any persons with the skills/resources, to get + involved with Libreboot development. What version of libreboot do I have? ---------------------------------------------------------------- -- cgit v1.2.3-70-g09d2 From 7d1cd1c6b74b941563e7ab717bfdbfcad3ae3e45 Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Fri, 23 Mar 2018 07:08:34 +0100 Subject: Rectify wifi card info on C201PA --- docs/hardware/c201.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/hardware/c201.md b/docs/hardware/c201.md index f268e6f6..2fd9b973 100644 --- a/docs/hardware/c201.md +++ b/docs/hardware/c201.md @@ -92,8 +92,9 @@ well. Ask on IRC if you think you can contribute. Caution: WiFi requires a non-free blob, a USB dongle can be used instead. ========================================================================= -These laptops have non-removeable (soldered on) WiFi chips, which -require non-free firmware in the Linux kernel in order to work. +These laptops have non-removeable (soldered on) M.2 Type 1216 card +with WiFi+Bluetooth, which requires non-free firmware to be loaded by +the Linux kernel in order to work. The libreboot project recommends using an external USB wifi dongle that works with free software. See -- cgit v1.2.3-70-g09d2 From 689117d445dc31649d3f23bf181a410747d5b208 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 24 Mar 2018 11:10:59 +0000 Subject: update libreplanet news post to confirm that zyliwax is there --- www/news/libreplanet2018-workshop.md | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/www/news/libreplanet2018-workshop.md b/www/news/libreplanet2018-workshop.md index 7ea4f729..0de75670 100644 --- a/www/news/libreplanet2018-workshop.md +++ b/www/news/libreplanet2018-workshop.md @@ -46,11 +46,14 @@ will be providing Libreboot flashing services at the conference: - Kurt from Technoethical, an FSF-endorsed Libreboot hardware seller. They will also have their own samples. They'll be at the Technoethical booth there. IRC nick sensiblemn\_ or sensiblemn on #libreboot IRC -- zyliwax from #libreboot IRC - has not committed fully, but is *very likely - to attend*, in their own words. -- Patrick McDermott (pehjota) of Libiquity. I've emailed them to ask, - though I'm not sure if they'll be there - they're usually there though, each - year. +- zyliwax from #libreboot IRC - has confirmed that they will be there +- Patrick McDermott (pehjota) of Libiquity. Patrick is also present at + LibrePlanet, and has brought flashing equipment. What Patrick said on the + libreplanet-discuss mailing list: look for the person that is wearing a + grey Libiquity polo shirt. They posted this picture on the mailing list, + so you know how to find this person: + + - of note: Patrick is bringing CH341A-based programmer, and can flash D8/D16 - You could also find an FSF sysadmin and ask them to flash Libreboot for you. I would be grateful if anyone else would also be willing to provide flashing. -- cgit v1.2.3-70-g09d2 From b368eeaeb83f1c626bd9018500680e513faae5ab Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 24 Mar 2018 21:13:44 +0000 Subject: general cleanup on the homepage. also fix a few typos that were overlooked --- www/index.md | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/www/index.md b/www/index.md index 8fd886e1..9181a429 100644 --- a/www/index.md +++ b/www/index.md @@ -36,12 +36,11 @@ libreboot is fully free software, where anyone can contribute or inspect its code. Libreboot is faster, more secure and more reliable than most non-free -firmware, and can provide many advanced feature, like encrypted -/boot/, GPG signature checking before booting your kernel, ability to -load an OS *from the flash chip*, and more. +firmware. Libreboot provides many advanced features, like encrypted +/boot/, GPG signature checking before booting your kernel and more! Libreboot's main upstream provider is [coreboot](https://www.coreboot.org/), which we deblob. We upstream our custom patches to projects like coreboot, depthcharge, GRUB, and flashrom where possible. Together, we provide an -automated build and installation system with nontechnical documentation, -allowing Libreboot to be widely used. +automated build and installation system with non-technical documentation, +allowing Libreboot to be widely used. -- cgit v1.2.3-70-g09d2 From bf0737617a53efb13f1237fb2e74899c83f38c04 Mon Sep 17 00:00:00 2001 From: Swift Geek Date: Tue, 27 Mar 2018 08:48:48 +0000 Subject: Remove dead links and fix formatting --- docs/hardware/gm45_remove_me.md | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/docs/hardware/gm45_remove_me.md b/docs/hardware/gm45_remove_me.md index b2f8db8b..0ac2f49b 100644 --- a/docs/hardware/gm45_remove_me.md +++ b/docs/hardware/gm45_remove_me.md @@ -297,27 +297,21 @@ Early notes {#early_notes} Flash chips {#flashchips} ----------- +- X200 laptop (Mocha-1): + ICH9-M overrides ifd permissions with a strap connected to GPIO33 pin (see IRC notes below) -- Schematics for X200 laptop: - - **~~- Page 20 and page 9 refer to SDA\_HDO or SDA\_HDOUT~~** only on - series 6 or higher chipsets. ICH9-M (X200) does it with a strap - connected to GPIO33 pin (see IRC notes below) - - - According to page 29, the X200 can have any of the following flash + - The X200 can be found with any of the following flash chips: - - ATMEL AT26DF321-SU 72.26321.A01 - this is a 32Mb (4MiB) chip - - MXIC (Macronix?) MX25L3205DM2I-12G 72.25325.A01 - another 32Mb - (4MiB) chip - - MXIC (Macronix?) MX25L6405DMI-12G 41R0820AA - this is a 64Mb - (8MiB) chip - - Winbond W25X64VSFIG 41R0820BA - another 64Mb (8MiB) chip - - sgsit says that the X200s with the 64Mb flash chips are (probably) + - ATMEL AT26DF321-SU 72.26321.A01 - this is a 32Mb (4MiB) chip + - MXIC (Macronix?) MX25L3205DM2I-12G 72.25325.A01 - another 32Mb + (4MiB) chip + - MXIC (Macronix?) MX25L6405DMI-12G 41R0820AA - this is a 64Mb + (8MiB) chip + - Winbond W25X64VSFIG 41R0820BA - another 64Mb (8MiB) chip + + sgsit says that the X200s (Pecan-1) with the 64Mb flash chips are (probably) the ones with AMT (alongside the ME), whereas the 32Mb chips contain only the ME. -- Schematics for X200s laptop: - . Early development notes {#early_development_notes} ----------------------- -- cgit v1.2.3-70-g09d2 From 69c4b3cf270e1221c3f8799958fe01d975f86578 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Tue, 27 Mar 2018 19:04:46 +0100 Subject: Suppliers page: add Minifree chip flashing service for D8 and D16 --- www/suppliers.md | 1 + 1 file changed, 1 insertion(+) diff --git a/www/suppliers.md b/www/suppliers.md index 916804f2..2a38f6cd 100644 --- a/www/suppliers.md +++ b/www/suppliers.md @@ -28,6 +28,7 @@ Laptops: Services: - [Libreboot installation service](https://minifree.org/product/libreboot-installation-service/) +- [Libreboot chip flashing service for ASUS KGPE-D16 and KCMA-D8](https://minifree.org/product/d8-d16-chipflash/) Merchendise: -- cgit v1.2.3-70-g09d2 From 796d78c6a5041cd4a5adb451a08837a3e9a9858b Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Wed, 28 Mar 2018 04:17:28 +0200 Subject: Add disclaimer about BBB being example --- docs/install/bbb_setup.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/docs/install/bbb_setup.md b/docs/install/bbb_setup.md index 94cfdc0b..f2bb840b 100644 --- a/docs/install/bbb_setup.md +++ b/docs/install/bbb_setup.md @@ -8,6 +8,16 @@ flash chip with the BeagleBone Black, using the rev. C was used when creating this guide, but earlier revisions may also work. +***NOTE: Use of BeagleBone black is for example purposes only, +don't buy it unless you want _it_ specifically.*** *There are many ARM +Single Board Computers (SBC) that are capable of in system programming +(external flashing) and they perform similarly terrible at that task. +Common use of devicetrees on those devices allows for configuring them +in similar way, but not identical, so a bit of own research is required. +Lastly SBC is an example of self-contained device that is capable of flashing, +but it's possible to use smaller device like stm32 bluepill +with another computer to achieve similar result.* + *NOTE: this documentation may be outdated, and discusses configuring SPI flashing on the default Debian system that the BBB sometimes comes with. If you want an easier time, just use [BBB -- cgit v1.2.3-70-g09d2 From 0871a2b54400c5d57cac2d6256cf831a1d7a3e24 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 28 Mar 2018 11:50:56 +0100 Subject: re-add nephelai.info mirror to download page. the sysadmin brought it back --- www/download.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/www/download.md b/www/download.md index 4b24ec81..73713a87 100644 --- a/www/download.md +++ b/www/download.md @@ -47,6 +47,9 @@ university, USA) (Peers Community Project, USA) + (nephelai.info, New Zealand) +(formerly nephelai.zanity.net/mirror/libreboot) + (vimuser.org, Netherlands) (elgrande74.net, France) -- cgit v1.2.3-70-g09d2 From 657da40088c94f83a9967e34d38aa6360c82fde5 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 28 Mar 2018 12:03:54 +0100 Subject: update zanity mirror to link to sugol domain instead (per sysadmin's request) --- www/download.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/www/download.md b/www/download.md index 73713a87..242e39d3 100644 --- a/www/download.md +++ b/www/download.md @@ -47,7 +47,7 @@ university, USA) (Peers Community Project, USA) - (nephelai.info, New Zealand) + (sugol.org) (formerly nephelai.zanity.net/mirror/libreboot) (vimuser.org, Netherlands) -- cgit v1.2.3-70-g09d2 From d74a7811ca3d3b1f8abd1fb10e0349923be2f00b Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 28 Mar 2018 12:35:03 +0100 Subject: improve rsync mirroring instructions on the download page --- www/download.md | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/www/download.md b/www/download.md index 242e39d3..c12b8b07 100644 --- a/www/download.md +++ b/www/download.md @@ -30,8 +30,10 @@ pubkey: [lbkey.asc](lbkey.asc). Do you have a mirror? --------------------- -Let us know! We will add it here. Instructions for how to mirror -libreboot releases can be found [on the mirrors](#https). +Let us know! We will add it here. + +If you wish to create a new mirror of the Libreboot releases, you can use +*rsync*. See: [rsync mirror list](#rsync). HTTPS mirrors {#https} ------------- @@ -61,7 +63,14 @@ Project, USA) RSYNC mirrors {#rsync} ------------- -Useful for mirroring Libreboot's entire set of release archives. +Useful for mirroring Libreboot's entire set of release archives. You can put +an rsync command into crontab and pull the files into a directory on your +web server. + +*It is highly recommended that you use the libreboot.org mirror*, if you wish +to host an official mirror. Otherwise, if you simply want to create your own +local mirror, you should use one of the other mirrors, which sync from +libreboot.org. (Libreboot project official mirror) -- cgit v1.2.3-70-g09d2 From 44fa8cd358dd965ff5cbf783af549b14e96bae0b Mon Sep 17 00:00:00 2001 From: "John M. Harris, Jr" Date: Sat, 31 Mar 2018 11:36:48 -0400 Subject: Rewrite dead links on hardware page --- docs/hardware/index.md | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/docs/hardware/index.md b/docs/hardware/index.md index 01719ada..a6d112de 100644 --- a/docs/hardware/index.md +++ b/docs/hardware/index.md @@ -31,8 +31,8 @@ Libreboot supports the following systems in this release: ### Laptops (Intel, x86) -- [Lenovo ThinkPad X60/X60s](#list-of-supported-x60s) -- [Lenovo ThinkPad X60 Tablet](#list-of-supported-x60-tablets) +- [Lenovo ThinkPad X60/X60s](#list-of-supported-thinkpad-x60s) +- [Lenovo ThinkPad X60 Tablet](#list-of-supported-thinkpad-x60-tablets) - [Lenovo ThinkPad T60](#supported-t60-list) (some exceptions) - [Lenovo ThinkPad X200](x200.md) - [Lenovo ThinkPad R400](r400.md) @@ -224,7 +224,7 @@ To find what LCD panel you have, see: [../misc/\#get\_edid\_panelname](../misc/#get_edid_panelname). *Some T60 variants have ATI GPUs, and all T60p laptops have ATI GPUs These are -incompatible! See [\#t60\_ati\_intel](#t60_ati_intel) for how to remedy +incompatible! See [\#thinkpad-t60-ati-gpu-and-thinkpad-t60-intel-gpu-differences](#thinkpad-t60-ati-gpu-and-thinkpad-t60-intel-gpu-differences) for how to remedy this.* Tested LCD panels: (working) @@ -337,14 +337,14 @@ Information about the macbook1,1 There is an Apple laptop called the macbook1,1 from 2006 which uses the same i945 chipset as the ThinkPad X60/T60. A developer ported the -[MacBook2,1](#macbook21) to coreboot, the ROM images also work on the +[MacBook2,1](#information-about-the-macbook21) to coreboot, the ROM images also work on the macbook1,1. -You can refer to [\#macbook21](#macbook21) for most of this. Macbook2,1 -laptops come with Core 2 Duo processors which support 64-bit operating -systems (and 32-bit). The MacBook1,1 uses Core Duo processors (supports -32-bit OS but not 64-bit), and it is believed that this is the only -difference. +You can refer to [\#information-about-the-macbook21](#information-about-the-macbook21) +for most of this. Macbook2,1 laptops come with Core 2 Duo processors +which support 64-bit operating systems (and 32-bit). The MacBook1,1 +uses Core Duo processors (supports 32-bit OS but not 64-bit), and it is +believed that this is the only difference. It is believed that all models are compatible, listed here: @@ -363,9 +363,8 @@ Also of interest: Unbricking: [this page shows disassembly guides](https://www.ifixit.com/Device/MacBook_Core_2_Duo) and mono's -page (see [\#macbook21](#macbook21)) shows the location of the SPI flash -chip on the motherboard. [How to remove the -motherboard](https://www.ifixit.com/Guide/MacBook+Core+2+Duo+PRAM+Battery+Replacement/529). +page (see [\#information-about-the-macbook21](#information-about-the-macbook21)) +shows the location of the SPI flash chip on the motherboard. [How to remove the motherboard](https://www.ifixit.com/Guide/MacBook+Core+2+Duo+PRAM+Battery+Replacement/529). No method is yet known for flashing in GNU+Linux while the Apple firmware is running. You will need to disassemble the system and flash -- cgit v1.2.3-70-g09d2 From 1e9a5722d84d0ba05b24c240d0611ea463a1275f Mon Sep 17 00:00:00 2001 From: "John M. Harris, Jr" Date: Sat, 31 Mar 2018 11:37:13 -0400 Subject: Remove dead link to non-existent anchor --- docs/hardware/index.md | 3 --- 1 file changed, 3 deletions(-) diff --git a/docs/hardware/index.md b/docs/hardware/index.md index a6d112de..e1af93c0 100644 --- a/docs/hardware/index.md +++ b/docs/hardware/index.md @@ -358,9 +358,6 @@ Specifically (Order No. / Model No. / CPU): - MA254LL/A / A1181 (EMC 2092) / Core Duo T2400 *(tested - working)* - MA472LL/A / A1181 (EMC 2092) / Core Duo T2500 (untested) -Also of interest: -[../git/\#config\_macbook21](../git/#config_macbook21). - Unbricking: [this page shows disassembly guides](https://www.ifixit.com/Device/MacBook_Core_2_Duo) and mono's page (see [\#information-about-the-macbook21](#information-about-the-macbook21)) -- cgit v1.2.3-70-g09d2 From 31d9d64e1c64c3eb9f6a1d0286dbb40337108035 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 31 Mar 2018 17:29:50 +0100 Subject: FAQ: Add note for Fedora compatibility with Libreboot --- docs/gnulinux/index.md | 17 +++++++++++++++++ www/faq.md | 8 ++++++++ 2 files changed, 25 insertions(+) diff --git a/docs/gnulinux/index.md b/docs/gnulinux/index.md index a2a411ab..bc7a04f8 100644 --- a/docs/gnulinux/index.md +++ b/docs/gnulinux/index.md @@ -28,6 +28,23 @@ However, with Libreboot, GRUB is already included directly (as a payload), so ev - [How to Harden Your GRUB Configuration, for Security](grub_hardening.md) +Fedora won't boot? +------------------ + +This may also apply to CentOS or Redhat. + +When you use Libreboot's default GRUB config, and libreboot-grub uses fedora's +default grub.cfg (in /boot/grub2/grub.cfg), fedora by default makes use of the +`linux16` command, whereas it should be saying `linux` + +Do this in fedora: + +Open `/etc/grub.d/10_linux` + +Set the `sixteenbit` variable to an empty string, then do: + + grub2-mkconfig -o /boot/grub2/grub.cfg + Copyright © 2014, 2015 Leah Rowe Copyright © 2017 Elijah Smith diff --git a/www/faq.md b/www/faq.md index 78aee27b..9a3dca38 100644 --- a/www/faq.md +++ b/www/faq.md @@ -1012,6 +1012,14 @@ Absolutely! It is well-tested in libreboot, and highly recommended. See Any recent distribution should work, as long as it uses KMS (kernel mode setting) for the graphics. +Fedora won't boot? (may also be applicable to Redhat/CentOS) +----------------------------------------------------------- + +On Fedora, by default the grub.cfg tries to boot linux in 16-bit mode. You +just have to modify Fedora's GRUB configuration. +Refer to [the GNU+Linux page](docs/gnulinux/index.md#fedora-wont-boot). + + Can I use BSD? ---------------------------------- -- cgit v1.2.3-70-g09d2 From 621998ec3aac477e741014bc24aae59e2022a76a Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 31 Mar 2018 16:34:17 +0100 Subject: intel reg write util: add note about older command on older version of the util --- docs/misc/index.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/docs/misc/index.md b/docs/misc/index.md index 02e715d8..51c53c2c 100644 --- a/docs/misc/index.md +++ b/docs/misc/index.md @@ -130,6 +130,8 @@ You can set values: sudo intel_reg write 0x00061254 your_value_in_C_hex_format +NOTE: on older versions of this utility, use `intel_reg_write` instead. + The value set has the following structure: bits \[31:16\] is PWM divider. PWM / PWM\_divider = frequency bits \[15:0\] is the duty cycle and determines the portion of the backlight modulation frequency. A @@ -164,6 +166,8 @@ Next this value should be set at boot: either add intel_reg write 0x00061254 <your_ideal_value> +NOTE: on older versions of this utility, use `intel_reg_write` instead. + before exit 0 in /etc/rc.local or create a systemd service file /etc/systemd/system/backlight.service: [Unit] -- cgit v1.2.3-70-g09d2 From 457aee8e397709dab6257b9a8892ed285205a027 Mon Sep 17 00:00:00 2001 From: "John M. Harris, Jr" Date: Wed, 4 Apr 2018 00:24:57 -0400 Subject: Update links to FAQ item about EC firmware --- docs/hardware/index.md | 2 +- docs/hardware/r400.md | 2 +- docs/hardware/t400.md | 2 +- docs/hardware/t500.md | 2 +- docs/hardware/x200.md | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/docs/hardware/index.md b/docs/hardware/index.md index e1af93c0..00e99060 100644 --- a/docs/hardware/index.md +++ b/docs/hardware/index.md @@ -54,7 +54,7 @@ EC update on i945 (X60, T60) and GM45 (X200, T400, T500, R400, W500) ============================================================== It is recommended that you update to the latest EC firmware version. The -[EC firmware](../../faq.md#firmware-ec) is separate from +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from libreboot, so we don't actually provide that, but if you still have Lenovo BIOS then you can just run the Lenovo BIOS update utility, which will update both the BIOS and EC version. See: diff --git a/docs/hardware/r400.md b/docs/hardware/r400.md index 4e0a0b19..ae22c50f 100644 --- a/docs/hardware/r400.md +++ b/docs/hardware/r400.md @@ -23,7 +23,7 @@ EC update {#ecupdate} ========= It is recommended that you update to the latest EC firmware version. The -[EC firmware](../../faq.md#firmware-ec) is separate from +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from libreboot, so we don't actually provide that, but if you still have Lenovo BIOS then you can just run the Lenovo BIOS update utility, which will update both the BIOS and EC version. See: diff --git a/docs/hardware/t400.md b/docs/hardware/t400.md index 7464f682..df7f0082 100644 --- a/docs/hardware/t400.md +++ b/docs/hardware/t400.md @@ -23,7 +23,7 @@ EC update {#ecupdate} ========= It is recommended that you update to the latest EC firmware version. The -[EC firmware](../../faq.md#firmware-ec) is separate from +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from libreboot, so we don't actually provide that, but if you still have Lenovo BIOS then you can just run the Lenovo BIOS update utility, which will update both the BIOS and EC version. See: diff --git a/docs/hardware/t500.md b/docs/hardware/t500.md index fdbca0d1..3973346c 100644 --- a/docs/hardware/t500.md +++ b/docs/hardware/t500.md @@ -25,7 +25,7 @@ EC update {#ecupdate} ========= It is recommended that you update to the latest EC firmware version. The -[EC firmware](../../faq.md#firmware-ec) is separate from +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from libreboot, so we don't actually provide that, but if you still have Lenovo BIOS then you can just run the Lenovo BIOS update utility, which will update both the BIOS and EC version. See: diff --git a/docs/hardware/x200.md b/docs/hardware/x200.md index b7bb434b..10f5f621 100644 --- a/docs/hardware/x200.md +++ b/docs/hardware/x200.md @@ -25,7 +25,7 @@ EC update {#ecupdate} ========= It is recommended that you update to the latest EC firmware version. The -[EC firmware](../../faq.md#firmware-ec) is separate from +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from libreboot, so we don't actually provide that, but if you still have Lenovo BIOS then you can just run the Lenovo BIOS update utility, which will update both the BIOS and EC version. See: -- cgit v1.2.3-70-g09d2 From 995fab239730412a45476dc64099adc60167b10b Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Wed, 4 Apr 2018 07:19:18 +0200 Subject: Clarify EC and SuperIO --- www/faq.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/www/faq.md b/www/faq.md index fca20e04..0aa25819 100644 --- a/www/faq.md +++ b/www/faq.md @@ -737,8 +737,8 @@ libreboot. See: (not ready yet). Most (all?) chromebooks have free EC firmware. Libreboot is currently looking into supporting a few ARM-based chromebooks. -EC is only present on laptops. On desktop/server boards it is absent -(not required). +EC is present on nearly all laptops. Other devices use, depending on complexity, +either EC or variant with firmware in Mask ROM - SuperIO. ### HDD/SSD firmware -- cgit v1.2.3-70-g09d2 From d324927fd9c938b8005dcd9c90858e583514c3cd Mon Sep 17 00:00:00 2001 From: "John M. Harris, Jr" Date: Wed, 4 Apr 2018 02:06:49 -0400 Subject: Remove punctuation from T60 ATI/Intel GPU differences heading --- docs/hardware/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/hardware/index.md b/docs/hardware/index.md index 00e99060..259fc854 100644 --- a/docs/hardware/index.md +++ b/docs/hardware/index.md @@ -290,7 +290,7 @@ is very easily replaced; just remove the card and install another one *after* libreboot is installed. See [\#recommended\_wifi](#recommended_wifi) for replacements. -ThinkPad T60 (ATI GPU) and ThinkPad T60 (Intel GPU) differences. +ThinkPad T60 (ATI GPU) and ThinkPad T60 (Intel GPU) differences ---------------------------------------------------------------- If your T60 is a 14.1" or 15.1" model with an ATI GPU, it won't work -- cgit v1.2.3-70-g09d2 From 6519ab6ddccf6804efb16548bef4e47ece735015 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sun, 11 Mar 2018 22:48:17 -0400 Subject: Include modules from modules-minimal in GRUB image --- projects/grub/configs/bios/modules-minimal | 2 ++ projects/grub/configs/coreboot/modules-minimal | 2 ++ projects/grub/grub-helper | 10 ++++++++-- 3 files changed, 12 insertions(+), 2 deletions(-) diff --git a/projects/grub/configs/bios/modules-minimal b/projects/grub/configs/bios/modules-minimal index ea936115..ab41ba65 100644 --- a/projects/grub/configs/bios/modules-minimal +++ b/projects/grub/configs/bios/modules-minimal @@ -1,5 +1,7 @@ biosdisk +cbfs cbmemc +configfile ext2 halt part_bsd diff --git a/projects/grub/configs/coreboot/modules-minimal b/projects/grub/configs/coreboot/modules-minimal index 310aef86..bd3248fd 100644 --- a/projects/grub/configs/coreboot/modules-minimal +++ b/projects/grub/configs/coreboot/modules-minimal @@ -1,5 +1,7 @@ ahci +cbfs cbmemc +configfile ehci ext2 halt diff --git a/projects/grub/grub-helper b/projects/grub/grub-helper index dd069290..0ffa8e27 100755 --- a/projects/grub/grub-helper +++ b/projects/grub/grub-helper @@ -128,6 +128,9 @@ grub_build_bootable_image() { local format="$(grub_format "$target" "$@")" local prefix="$(grub_prefix "$target" "$@")" local config_path="$(grub_config_path "$target" "$@")" + local modmin_path="$(grub_modmin_path "$target" "$@")" + + local -a modmin=($(< "$modmin_path")) local grub_mkimage="$sources_path/grub-mkimage" local grub_module_dir="$sources_path/grub-core" @@ -142,7 +145,7 @@ grub_build_bootable_image() { --output="$grubimg" \ --format="$format" \ --prefix="$prefix" \ - cbfs configfile + "${modmin[@]}" cat "$grub_bootimg" "$grubimg" > "$grub_bootable_img" rm -f "$grubimg" @@ -192,6 +195,9 @@ grub_build_standalone_image() { local format="$(grub_format "$target" "$@")" local prefix="$(grub_prefix "$target" "$@")" local config_path="$(grub_config_path "$target" "$@")" + local modmin_path="$(grub_modmin_path "$target" "$@")" + + local -a modmin=($(< "$modmin_path")) local grubimg="$build_path/grub2" @@ -204,7 +210,7 @@ grub_build_standalone_image() { --fonts='' \ --themes='' \ --locales='' \ - --install-modules='cbfs configfile' \ + --install-modules="${modmin[*]}" \ --directory="$grub_module_dir" \ --format="$format" \ --output="$grubimg" \ -- cgit v1.2.3-70-g09d2 From 2d4f3a85878998f3c934adf3bc5daea78ba3d205 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sun, 11 Mar 2018 22:49:57 -0400 Subject: Be specific about size limit for floppy GRUB image --- projects/grub/grub-helper | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/projects/grub/grub-helper b/projects/grub/grub-helper index 0ffa8e27..596f7d96 100755 --- a/projects/grub/grub-helper +++ b/projects/grub/grub-helper @@ -184,7 +184,7 @@ grub_build_floppy_image() { mv "$tempfile" "$grubimg" else printf '\n%s' "Error: Image ${grubimg##*/} is too large; " 1>&2 - printf '%s\n\n' "it must be less than ${size}KiB in size" 1>&2 + printf '%s\n\n' "it must be less than ${floppy_size}KiB in size" 1>&2 return 1 fi -- cgit v1.2.3-70-g09d2 From 63132cde4d70d2b2fe69e19909c53f4d269de247 Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 7 Apr 2018 23:10:12 -0400 Subject: Add overlooked GRUB modules to modules-minimal --- projects/grub/configs/bios/modules-minimal | 4 ++++ projects/grub/configs/coreboot/modules-minimal | 1 + projects/grub/configs/uefi/modules-minimal | 3 +++ 3 files changed, 8 insertions(+) diff --git a/projects/grub/configs/bios/modules-minimal b/projects/grub/configs/bios/modules-minimal index ab41ba65..706aa529 100644 --- a/projects/grub/configs/bios/modules-minimal +++ b/projects/grub/configs/bios/modules-minimal @@ -1,10 +1,14 @@ +ahci biosdisk cbfs cbmemc configfile +ehci ext2 halt +loadenv part_bsd part_gpt +pata reboot verify diff --git a/projects/grub/configs/coreboot/modules-minimal b/projects/grub/configs/coreboot/modules-minimal index bd3248fd..0480a0d0 100644 --- a/projects/grub/configs/coreboot/modules-minimal +++ b/projects/grub/configs/coreboot/modules-minimal @@ -5,6 +5,7 @@ configfile ehci ext2 halt +loadenv part_bsd part_gpt pata diff --git a/projects/grub/configs/uefi/modules-minimal b/projects/grub/configs/uefi/modules-minimal index 310aef86..0480a0d0 100644 --- a/projects/grub/configs/uefi/modules-minimal +++ b/projects/grub/configs/uefi/modules-minimal @@ -1,8 +1,11 @@ ahci +cbfs cbmemc +configfile ehci ext2 halt +loadenv part_bsd part_gpt pata -- cgit v1.2.3-70-g09d2 From 101ce64808f235270f957b20ecb087874b35e168 Mon Sep 17 00:00:00 2001 From: Rahiel Kasim Date: Thu, 12 Apr 2018 12:46:55 +0200 Subject: typo: merchendise -> merchandise --- www/suppliers.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/www/suppliers.md b/www/suppliers.md index 2a38f6cd..d269d270 100644 --- a/www/suppliers.md +++ b/www/suppliers.md @@ -30,7 +30,7 @@ Services: - [Libreboot installation service](https://minifree.org/product/libreboot-installation-service/) - [Libreboot chip flashing service for ASUS KGPE-D16 and KCMA-D8](https://minifree.org/product/d8-d16-chipflash/) -Merchendise: +Merchandise: - [Libreboot T400 battery](https://minifree.org/product/libreboot-t400-battery/) - [Libreboot X200 battery](https://minifree.org/product/libreboot-x200-battery/) -- cgit v1.2.3-70-g09d2 From c931759ea7fa0ef0a48bca83e565385ecfa7d150 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 19 Apr 2018 14:37:28 +0100 Subject: add news post about Gender Reassignment Surgery fundraiser for Leah Rowe --- www/news/MANIFEST | 1 + www/news/leah-fundraiser.md | 45 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 www/news/leah-fundraiser.md diff --git a/www/news/MANIFEST b/www/news/MANIFEST index 4f588538..0e7cc034 100644 --- a/www/news/MANIFEST +++ b/www/news/MANIFEST @@ -1,3 +1,4 @@ +news/leah-fundraiser.md news/libreplanet2018-workshop.md news/release-testing-20171221.md news/lenovo-recall.md diff --git a/www/news/leah-fundraiser.md b/www/news/leah-fundraiser.md new file mode 100644 index 00000000..5a5b7b20 --- /dev/null +++ b/www/news/leah-fundraiser.md @@ -0,0 +1,45 @@ +% Help Leah, founder of Libreboot, get Gender Reassignment Surgery +% Leah Rowe +% 19 April 2017 + +I spoke with Andrew Robbins and Swift Geek on #libreboot IRC. These are two +other members of the core Libreboot community. This news post was submitted to +Pull Request, subject to their approval before publishing on libreboot.org. + +My name is Leah Rowe, and I'm the founder of the Libreboot project. I’m a 26 +year old British trans woman, living in the UK. After a lifetime of +repression and denial, I came out as transgender in June 2016; I +began living full-time as my true self for the first time. This was my coming +out message to the Libreboot community: + + +I need help from the community in order to to pay for my Gender Reassignment +Surgery. Here is my fundraiser: + + +I'm unable to pay for it myself. 2 years ago, I paid 90,000 USD to Raptor +Engineering to port the ASUS KGPE-D16 and KCMA-D8 to Libreboot as well as 4000 +AUD to Damien Zammit for the Gigabyte GA-G41M-ES2L and Intel D510MO ports. +Besides this, I've spent huge amounts of money in general on development of my +own and I've dedicated countless hours to this project. I love Libreboot +and I love working on it. For instance, I ported the ThinkPad X200 (later T400, +T500 etc) to Libreboot myself, working alongside Steve Shenton to free it from +the Intel ME firmware. Unfortunately, this has left me severely out of pocket +and, even now, I can't afford to pay for the things I need for myself such as +this. + +As a direct result of my contributions, the Free Software community is in a +much better state than it was. +The [Free Software Foundation](https://www.fsf.org/) now hosts fsf.org and +[gnu.org](https://www.gnu.org/), as well as +[GNU Savannah](https://savannah.gnu.org/) (used by many GNU projects, for code +hosting and collaboration) on ASUS KGPE-D16 +servers, running Libreboot. Additionally, both the Free Software Foundation and +[Software Freedom Conservancy](https://sfconservancy.org/) use Libreboot laptops +almost exclusively in their offices. Thousands of people now use Libreboot. +Projects inspired by Libreboot have also appeared such as the +[TALOS II workstation](https://www.raptorcs.com/TALOSII/). + +I greatly appreciate any help that the community can give me, no matter how +big or small. It will mean a great deal to me, and allow me to focus on my +passions, including Libreboot. -- cgit v1.2.3-70-g09d2 From 5decb978639d0a435fc83931005f1c25650bce86 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 25 Apr 2018 22:27:11 +0100 Subject: Add Minifree X200 Tablet to the suppliers page --- www/suppliers.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/www/suppliers.md b/www/suppliers.md index d269d270..78b56f9f 100644 --- a/www/suppliers.md +++ b/www/suppliers.md @@ -22,6 +22,7 @@ endorsement on a computer system, and invests money directly into Libreboot. Laptops: +- [Libreboot X200 Tablet laptop](https://minifree.org/product/libreboot-x200-tablet/) (FSF RYF certification pending) - [Libreboot X200 laptop](https://minifree.org/product/libreboot-x200/) (FSF RYF certified) - [Libreboot T400 laptop](https://minifree.org/product/libreboot-t400/) (FSF RYF certified) @@ -34,7 +35,8 @@ Merchandise: - [Libreboot T400 battery](https://minifree.org/product/libreboot-t400-battery/) - [Libreboot X200 battery](https://minifree.org/product/libreboot-x200-battery/) -- [Libreboot X200 docking station](https://minifree.org/product/docking-station-for-libreboot-x200/) +- [Libreboot X200 Tablet battery](https://minifree.org/product/libreboot-x200-tablet-battery/) +- [Libreboot X200/X200T docking station](https://minifree.org/product/docking-station-for-libreboot-x200/) - [Libreboot stickers](https://minifree.org/product/libreboot-stickers/) Phreedom 2600 -- cgit v1.2.3-70-g09d2 From 1744d698983ad47623b5904c83e0171d4f68cd04 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 28 Apr 2018 20:12:18 +0100 Subject: docs/gnulinux: fix the debian instructions (grub commands were b0rked) --- docs/gnulinux/grub_boot_installer.md | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/docs/gnulinux/grub_boot_installer.md b/docs/gnulinux/grub_boot_installer.md index 085ad34b..7086b71d 100644 --- a/docs/gnulinux/grub_boot_installer.md +++ b/docs/gnulinux/grub_boot_installer.md @@ -53,18 +53,23 @@ Make sure that the device isn't mounted, with `doas`; if it is, this command wil That's it! You should now be able to boot the installer from your USB drive (the instructions for doing so will be given later). ## Debian or Devuan net install -1. Download the Debian or Devuan net installer. You can download the Debian ISO from [the Debian homepage](https://www.debian.org/), or the Devuan ISO from [the Devuan homepage](https://www.devuan.org/). +Download the Debian or Devuan net installer. You can download the Debian ISO +from [the Debian homepage](https://www.debian.org/), or the Devuan ISO from +[the Devuan homepage](https://www.devuan.org/). -2. Create a bootable USB, using the commands in *Prepare the USB Drive in GNU+Linux*, above. +Secondly, create a bootable USB drive using the commands in +[#prepare-the-usb-drive-in-gnulinux](#prepare-the-usb-drive-in-gnulinux). -3. Boot the USB, and enter these commands in the GRUB terminal (for 64-bit Intel or AMD): +Thirdly, boot the USB and enter these commands in the GRUB terminal +(for 64-bit Intel or AMD): grub> set root='usb0' grub> linux /install.amd/vmlinuz grub> initrd /install.amd/initrd.gz grub> boot -4. If you are on a 32-bit system (e.g. some Thinkpad X60's), you will need to use these commands: +If you are on a 32-bit system (e.g. some Thinkpad X60's) then you will need to +use these commands instead: grub> set root='usb0' grub> linux /install.386/vmlinuz -- cgit v1.2.3-70-g09d2 From 911cacf2c2aaf780a15fd266c360c680a940dd3d Mon Sep 17 00:00:00 2001 From: ginny Date: Wed, 9 May 2018 20:44:28 +0300 Subject: Reformulated sentence so that people don't think it means model T4xx --- docs/hardware/t400.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/hardware/t400.md b/docs/hardware/t400.md index df7f0082..f7c4d437 100644 --- a/docs/hardware/t400.md +++ b/docs/hardware/t400.md @@ -2,7 +2,7 @@ title: ThinkPad T400 ... -It is believed that all or most T400 laptops are compatible. See notes +It is believed that all or most laptops of the model T400 are compatible. See notes about [CPU compatibility](../install/t400_external.html#cpu_compatibility) for potential incompatibilities. -- cgit v1.2.3-70-g09d2 From fdc116438fe0dfb98af483fd5ee7e1127b170def Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Wed, 9 May 2018 19:14:51 +0200 Subject: encrypted_parabola.md: prabola typofix --- docs/gnulinux/encrypted_parabola.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/gnulinux/encrypted_parabola.md b/docs/gnulinux/encrypted_parabola.md index b2e40a01..74c74fce 100644 --- a/docs/gnulinux/encrypted_parabola.md +++ b/docs/gnulinux/encrypted_parabola.md @@ -284,7 +284,7 @@ directory to the one you created in the previous steps, so that you can modify f and install software onto it, as if it were the host operating system. To `chroot` into your installation, follow the instructions [on the -Prabola beginner's guide](https://wiki.parabola.nu/Beginners%27_guide#Chroot_and_configure_the_base_system). +Parabola beginner's guide](https://wiki.parabola.nu/Beginners%27_guide#Chroot_and_configure_the_base_system). ### Setting up the Locale Locale refers to the language that your operating system will use, as well as some -- cgit v1.2.3-70-g09d2 From e87f326a7fe2f3493a28f4e25d207f4d05f7c050 Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Wed, 9 May 2018 19:20:15 +0200 Subject: c201.md: fix WP screw description It cannot be pulled low because that would enable #WP So I assume it's pulled up weakly on motherboard with some resistor --- docs/install/c201.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/install/c201.md b/docs/install/c201.md index 238c0734..3045b062 100644 --- a/docs/install/c201.md +++ b/docs/install/c201.md @@ -155,7 +155,7 @@ to be opened. The SPI flash is located next to the write protect screw. Its layout is indicated in the picture below. Note that it is not necessary to connect -`WP#` since removing the screw already connects it to ground. Before +`WP#` since after removing the screw it is pulled up weakly to 3v3. Before writing to the chip externally, the battery connector has to be detached. It is located under the heat spreader, that has to be unscrewed from the rest of the case. The battery connector is located on -- cgit v1.2.3-70-g09d2 From 90d88750f81e9c9badd40721fd6868170d51ae2e Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Wed, 9 May 2018 19:26:21 +0200 Subject: c201.md: change phrasing for detaching battery don't tell people to rip out the sockets from the motherboard, this ain't nokia 3310 --- docs/install/c201.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/docs/install/c201.md b/docs/install/c201.md index 3045b062..fb39196a 100644 --- a/docs/install/c201.md +++ b/docs/install/c201.md @@ -156,9 +156,9 @@ to be opened. The SPI flash is located next to the write protect screw. Its layout is indicated in the picture below. Note that it is not necessary to connect `WP#` since after removing the screw it is pulled up weakly to 3v3. Before -writing to the chip externally, the battery connector has to be -detached. It is located under the heat spreader, that has to be -unscrewed from the rest of the case. The battery connector is located on +writing to the chip externally, the battery has to be unplugged. +Battery connector is located under the heat spreader, that has to be +unscrewed from the rest of the case. It is located on the right and has colorful cables, as shown on the picture below. [![SPI flash -- cgit v1.2.3-70-g09d2 From e9aa96f3d2b482faddfa9a4d8ebe979692c2d5d4 Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Wed, 9 May 2018 19:30:43 +0200 Subject: bbb_setup.md: lost asterisk --- docs/install/bbb_setup.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/install/bbb_setup.md b/docs/install/bbb_setup.md index f2bb840b..5d684a7f 100644 --- a/docs/install/bbb_setup.md +++ b/docs/install/bbb_setup.md @@ -236,7 +236,7 @@ Output: Verify that the spidev device now exists: - # ls -al /dev/spid + # ls -al /dev/spid* Output: -- cgit v1.2.3-70-g09d2 From 32d8ab0b23cdf0e6280019e60559652a47f291f6 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Fri, 18 May 2018 22:05:39 +0100 Subject: Suppliers page: Add link to new TALOS II Lite --- www/suppliers.md | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/www/suppliers.md b/www/suppliers.md index 78b56f9f..d3667a9f 100644 --- a/www/suppliers.md +++ b/www/suppliers.md @@ -58,6 +58,12 @@ firmware and operating system preinstalled, *from the factory*. Website for pre-orders: +They have 2 systems available: + +- [TALOS II Lite](https://secure.raptorcs.com/content/TL1BC1/purchase.html) + (this is the cheaper version) +- [TALOS II](https://secure.raptorcs.com/content/TL2WK2/intro.html) + NOTE: this isn't technically Libreboot, but the boot firmware is entirely free. This is the same company that ported the ASUS KFSN4-DRE, KGPE-D16 and KCMA-D8 -- cgit v1.2.3-70-g09d2 From 9568db1eea3d771fd72a0ef54fda14ace954d4cd Mon Sep 17 00:00:00 2001 From: StewieFellows Date: Fri, 18 May 2018 22:49:55 +0000 Subject: Update 'docs/hardware/index.md' Adding Samsung LTN141XA-L01 to supported T60 LCD panels list. --- docs/hardware/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/hardware/index.md b/docs/hardware/index.md index 259fc854..12580cf8 100644 --- a/docs/hardware/index.md +++ b/docs/hardware/index.md @@ -242,11 +242,11 @@ Tested LCD panels: (working) works) - BOE-Hydis HV150UX1-100 (15.1" 1600x1200) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board) +- Samsung LTN141XA-L01 (14.1" 1024x768) Tested LCD panels: *not working yet (incompatible; see [../future/\#lcd\_i945\_incompatibility](../future/#lcd_i945_incompatibility))* -- Samsung LTN141XA-L01 (14.1" 1024x768) - LG-Philips LP150X09 (15.1" 1024x768) - Samsung LTN150XG (15.1" 1024x768) - LG-Philips LP150E06-A5K4 (15.1" 1400x1050) (also, not an official -- cgit v1.2.3-70-g09d2 From ff2b796271828a8e6271693e199f6d8fc7103458 Mon Sep 17 00:00:00 2001 From: mois Date: Mon, 21 May 2018 15:29:33 +0000 Subject: Update 'docs/gnulinux/grub_cbfs.md' corrected link in command --- docs/gnulinux/grub_cbfs.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/gnulinux/grub_cbfs.md b/docs/gnulinux/grub_cbfs.md index 5283b4fc..ce7acab9 100644 --- a/docs/gnulinux/grub_cbfs.md +++ b/docs/gnulinux/grub_cbfs.md @@ -164,7 +164,7 @@ using `flashrom`, making sure to save it in the `cbfstool` folder, inside **libr If you are told to specify the chip, add the option `-c {your chip}` to the command, like this: $ sudo flashrom -c MX25L6405 -p internal -r ~/Downloads/libreboot_util/\ - >cbfstool/x86_64/cbfstool/x86_64/libreboot.rom + >cbfstool/x86_64/libreboot.rom Now you are ready to extract the GRUB configuration files from the ROM, and modify them the way you want. -- cgit v1.2.3-70-g09d2 From d58414906e8106f01be0d18616dab41846c9d72e Mon Sep 17 00:00:00 2001 From: mois Date: Mon, 21 May 2018 15:35:25 +0000 Subject: Update 'docs/gnulinux/grub_cbfs.md' deleted duplicate strings in paths --- docs/gnulinux/grub_cbfs.md | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/docs/gnulinux/grub_cbfs.md b/docs/gnulinux/grub_cbfs.md index ce7acab9..b0d7b0e3 100644 --- a/docs/gnulinux/grub_cbfs.md +++ b/docs/gnulinux/grub_cbfs.md @@ -152,19 +152,17 @@ used by coreboot native graphics initialization. I'll choose **x200_8mb_usqwerty_vesafb.rom**; I'll copy the file (to the `cbfstool` directory), and rename it with one command: - $ mv "x200_8mb_usqwerty_vesafb.rom" ../cbfstool/x86_64/cbfstool/x86_64/libreboot.rom + $ mv "x200_8mb_usqwerty_vesafb.rom" ../cbfstool/x86_64/libreboot.rom #### 2. Create an Image from the Current ROM The simpler way to get a ROM image is to just create it from your current ROM, using `flashrom`, making sure to save it in the `cbfstool` folder, inside **libreboot\_util**: - $ sudo flashrom -p internal -r ~/Downloads/libreboot_util/cbfstool/\ - >x86_64/cbfstool/x86_64/libreboot.rom + $ sudo flashrom -p internal -r ~/Downloads/libreboot_util/cbfstool/x86_64/libreboot.rom If you are told to specify the chip, add the option `-c {your chip}` to the command, like this: - $ sudo flashrom -c MX25L6405 -p internal -r ~/Downloads/libreboot_util/\ - >cbfstool/x86_64/libreboot.rom + $ sudo flashrom -c MX25L6405 -p internal -r ~/Downloads/libreboot_util/cbfstool/x86_64/libreboot.rom Now you are ready to extract the GRUB configuration files from the ROM, and modify them the way you want. @@ -173,7 +171,7 @@ Now you are ready to extract the GRUB configuration files from the ROM, and modi You can check the contents of the ROM image, inside CBFS, using `cbfstool`. First, navigate to the cbfstool folder: - $ cd ~/Downloads/libreboot_util/cbfstool/x86_64/cbfstool/x86_64/ + $ cd ~/Downloads/libreboot_util/cbfstool/x86_64/ Then, run the `cbfstool` commmand, with the `print` option; this will display a list of all the files located in the ROM: @@ -243,8 +241,7 @@ the main storage for **/boot/grub/libreboot\_grub.cfg** or **/grub/libreboot\_gr Therefore, we need to either copy **libreboot\_grub.cfg** to **/grub**, or to **/boot/grub**: - $ sudo cp ~/Downloads/libreboot_util/cbfstool/x86_64/cbfstool/x86_64/grubtest.cfg \ - >/boot/grub # or /grub + $ sudo cp ~/Downloads/libreboot_util/cbfstool/x86_64/grubtest.cfg /boot/grub # or /grub Now, the next time we boot our computer, GRUB (in Libreboot) will automatically switch to this configuration file. *This means that you do not have to re-flash, @@ -354,7 +351,7 @@ of **grubtest.cfg**, called **grub.cfg**. First, go to the `cbfstool` directory: - $ cd ~/Downloads/libreboot_util/cbfstool/x86_64/cbfstool/x86_64/ + $ cd ~/Downloads/libreboot_util/cbfstool/x86_64/ Then, create a copy of **grubest.cfg**, named **grub.cfg**: -- cgit v1.2.3-70-g09d2 From 09f20baa6d60665e9c8b7a3aff34c06ba3c12d11 Mon Sep 17 00:00:00 2001 From: mois Date: Mon, 21 May 2018 15:55:34 +0000 Subject: Update 'docs/gnulinux/grub_cbfs.md' another typo --- docs/gnulinux/grub_cbfs.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/gnulinux/grub_cbfs.md b/docs/gnulinux/grub_cbfs.md index b0d7b0e3..4879d9cf 100644 --- a/docs/gnulinux/grub_cbfs.md +++ b/docs/gnulinux/grub_cbfs.md @@ -213,7 +213,7 @@ Or, replace it with this, if you are using a Debian-based distribution (e.g., Tr cryptomount -a set root='lvm/matrix-rootvol' - linux /vmlinuz root=/dev/mapper/matrix-rootvolcryptdevice=/dev/mapper/matrix-rootvol:root + linux /vmlinuz root=/dev/mapper/matrix-rootvol cryptdevice=/dev/mapper/matrix-rootvol:root initrd /initrd.img Remember, that these names come from the instructions to install GNU+Linux -- cgit v1.2.3-70-g09d2 From b8e0f0e74e3071a1cfe0f3f2310979820400996a Mon Sep 17 00:00:00 2001 From: "John M. Harris, Jr" Date: Tue, 22 May 2018 09:38:34 -0400 Subject: Fix bucts URI in oldbuild download script git.stuge.se is down, and has been for a while. --- resources/scripts/helpers/download/bucts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/resources/scripts/helpers/download/bucts b/resources/scripts/helpers/download/bucts index 7bea3e65..b57df1fd 100755 --- a/resources/scripts/helpers/download/bucts +++ b/resources/scripts/helpers/download/bucts @@ -37,7 +37,7 @@ rm -Rf "bucts/" # ------------------------------------------------------------------------------ # download it using git -git clone git://git.stuge.se/bucts.git +git clone https://notabug.org/libreboot/bucts.git # modifications are required cd "bucts/" -- cgit v1.2.3-70-g09d2 From 5c9c33854efe9285a79d510a90181b5c8eeb4864 Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Sun, 27 May 2018 12:20:52 +0200 Subject: Clarify image verification --- docs/install/x200_external.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/install/x200_external.md b/docs/install/x200_external.md index 3ff34501..5dd39877 100644 --- a/docs/install/x200_external.md +++ b/docs/install/x200_external.md @@ -163,7 +163,9 @@ Now compare the 3 images: # sha512sum factory*.rom -If the hashes match, then just copy one of them (the factory.rom) to a +If the hashes match and if hex editor (like `dhex`) shows that +they have valid contents (eg. it's not filled entirely with `0x00`/`0xFF`), +then just copy one of them (the factory.rom) to a safe place (on a drive connected to another system, not the BBB). This is useful for reverse engineering work, if there is a desirable behaviour in the original firmware that could be replicated in coreboot -- cgit v1.2.3-70-g09d2 From a117c5c29b4c8adc59ec9183d2f5373d41db952a Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Sun, 27 May 2018 12:22:38 +0200 Subject: Remove -V from flashrom command examples --- docs/install/x200_external.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/install/x200_external.md b/docs/install/x200_external.md index 5dd39877..83a5c23f 100644 --- a/docs/install/x200_external.md +++ b/docs/install/x200_external.md @@ -19,7 +19,7 @@ Flash chip size Run this command on x200 to find out flash chip model and its size: - # flashrom -p internal -V + # flashrom -p internal The X200S and X200 Tablet will use a WSON-8 flash chip, on the bottom of the motherboard (this requires removal of the motherboard). Not all X200S/X200T are @@ -180,7 +180,7 @@ address to one that is correct for your system. Now flash it: - # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w path/to/libreboot/rom/image.rom -V + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w path/to/libreboot/rom/image.rom ![](images/x200/disassembly/0015.jpg) -- cgit v1.2.3-70-g09d2 From 57b6b6f65110bb8a4f78ea88c6fb309eeecc7faf Mon Sep 17 00:00:00 2001 From: Fedja Beader Date: Sun, 27 May 2018 16:43:04 +0200 Subject: Add ahci1 (ultrabay SATA on T400) and similarly ata1 (presumably ultrabay on T60?) to FDE boot list and give them higher priority over HDD bay. Ditto for LUKS on partitions. --- resources/grub/config/menuentries/common.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/resources/grub/config/menuentries/common.cfg b/resources/grub/config/menuentries/common.cfg index d65f86fb..02376c50 100644 --- a/resources/grub/config/menuentries/common.cfg +++ b/resources/grub/config/menuentries/common.cfg @@ -64,11 +64,11 @@ menuentry 'Load Operating System (incl. fully encrypted disks) [o]' --hotkey='o # on raw crypto devices as well as inside LVM volumes this time. # The user will be prompted for a passphrase if a LUKS header was found. - for dev in ahci0 ata0 usb0 ${lvm}; do + for dev in ahci1 ahci0 ata1 ata0 usb0 ${lvm}; do cryptomount "(${dev})" done # 3) encrypted devices/partitions - for i in 0 1; do + for i in 1 0; do for part in 1 2 3 4 5; do for type in ahci ata; do cryptomount "(${type}${i},${part})" -- cgit v1.2.3-70-g09d2 From 030a9f52bfc97d73670223da8813f80fa0f8f129 Mon Sep 17 00:00:00 2001 From: Fedja Beader Date: Sun, 27 May 2018 16:50:09 +0200 Subject: Give USB storage devices priority over S?ATA ones. --- resources/grub/config/menuentries/common.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/resources/grub/config/menuentries/common.cfg b/resources/grub/config/menuentries/common.cfg index 02376c50..59e1e32e 100644 --- a/resources/grub/config/menuentries/common.cfg +++ b/resources/grub/config/menuentries/common.cfg @@ -64,13 +64,13 @@ menuentry 'Load Operating System (incl. fully encrypted disks) [o]' --hotkey='o # on raw crypto devices as well as inside LVM volumes this time. # The user will be prompted for a passphrase if a LUKS header was found. - for dev in ahci1 ahci0 ata1 ata0 usb0 ${lvm}; do + for dev usb1 usb0 ahci1 ahci0 ata1 ata0 ${lvm}; do cryptomount "(${dev})" done # 3) encrypted devices/partitions for i in 1 0; do for part in 1 2 3 4 5; do - for type in ahci ata; do + for type in usb ahci ata; do cryptomount "(${type}${i},${part})" done done -- cgit v1.2.3-70-g09d2 From ded3faf08665c3004d2d76db851c1c5c86d32150 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Thu, 31 May 2018 12:41:25 +0100 Subject: update suppliers page to say that Minifree X200T is RYF certified (no PR needed) no pull request needed. this is the most minor of minor changes --- www/suppliers.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/www/suppliers.md b/www/suppliers.md index d3667a9f..4432d86b 100644 --- a/www/suppliers.md +++ b/www/suppliers.md @@ -22,7 +22,7 @@ endorsement on a computer system, and invests money directly into Libreboot. Laptops: -- [Libreboot X200 Tablet laptop](https://minifree.org/product/libreboot-x200-tablet/) (FSF RYF certification pending) +- [Libreboot X200 Tablet laptop](https://minifree.org/product/libreboot-x200-tablet/) (FSF RYF certified) - [Libreboot X200 laptop](https://minifree.org/product/libreboot-x200/) (FSF RYF certified) - [Libreboot T400 laptop](https://minifree.org/product/libreboot-t400/) (FSF RYF certified) -- cgit v1.2.3-70-g09d2 From 7423bc922664b0ac074b8e33cdd3e85ebd8b5f2d Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Sat, 9 Jun 2018 15:13:18 +0100 Subject: git page: link to actual instructions for how to use git otherwise, how the hell does a user know what to do? we shouldn't just assume that everyone knows how to use git. some of our contributors might be people who just want to submit something to the documentation and they may never have used git before --- www/git.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/www/git.md b/www/git.md index 06aac3d0..375a9eda 100644 --- a/www/git.md +++ b/www/git.md @@ -13,6 +13,10 @@ You can submit your patches via Information about how the Libreboot project is governed is documented in our [general management guidelines](management.md). +Libreboot development is done using the Git version control system. +Refer to the [official Git documentation](https://git-scm.com/doc) if you don't +know how to use Git. + Editing the website and documentation, wiki-style ------------------------------------------------- -- cgit v1.2.3-70-g09d2 From 89961a3cb7d38575c09ef72c350b7bddadf01756 Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 13 Jun 2018 21:43:14 +0100 Subject: Fix/update/remove dead/broken links on the website and documentation Thanks go to skollrc for pointing out these dead links, on this thread: https://www.reddit.com/r/libreboot/comments/8pjjg5/some_dead_links_in_libreboot _website/ --- docs/gnulinux/configuring_parabola.md | 2 +- docs/gnulinux/encrypted_parabola.md | 4 ++-- docs/gnulinux/grub_boot_installer.md | 2 +- docs/hardware/gm45_remove_me.md | 2 +- docs/hardware/x200.md | 6 ------ docs/install/index.md | 2 +- docs/install/rpi_setup.md | 2 +- projects/ich9gen/sources/src/gbe/gbe.h | 2 +- projects/ich9gen/sources/src/ich9deblob.c | 2 +- resources/utilities/ich9deblob/src/gbe/gbe.h | 2 +- resources/utilities/ich9deblob/src/ich9deblob.c | 2 +- www/news/andrew-robbins-new-maintainer.md | 2 +- 12 files changed, 12 insertions(+), 18 deletions(-) diff --git a/docs/gnulinux/configuring_parabola.md b/docs/gnulinux/configuring_parabola.md index 1e525f59..935ff099 100644 --- a/docs/gnulinux/configuring_parabola.md +++ b/docs/gnulinux/configuring_parabola.md @@ -63,7 +63,7 @@ For more information related to `pacman`, review the following articles on the A * [Configuring pacman](https://wiki.parabolagnulinux.org/Installation_Guide#Configure_pacman) * [Using pacman](https://wiki.archlinux.org/index.php/Pacman) -* [Additional Repositories](https://wiki.parabolagnulinux.org/Official_Repositories>) +* [Additional Repositories](https://wiki.parabolagnulinux.org/Official_Repositories) ## Updating Parabola Parabola is kept up-to-date, using `pacman`. When you are updating Parabola, diff --git a/docs/gnulinux/encrypted_parabola.md b/docs/gnulinux/encrypted_parabola.md index 74c74fce..48ef5b76 100644 --- a/docs/gnulinux/encrypted_parabola.md +++ b/docs/gnulinux/encrypted_parabola.md @@ -102,7 +102,7 @@ You can either fill the header with zeroes, or with random data; again, I chose Also, if you're using an SSD, there are a two things you should keep in mind: - There are issues with TRIM; it's not enabled by default through LUKS, -and there are security issues, if you do enable it. See [this page](https://wiki.archlinux.org/index.php/Dm-cryptSpecialties#Discard.2FTRIM_support_for_solid_state_drives_.28SSD.29) for more info. +and there are security issues, if you do enable it. See [this page](https://wiki.archlinux.org/index.php/Dm-crypt#Specialties) for more info. - Make sure to read [this article](https://wiki.archlinux.org/index.php/Solid_State_Drives), for information on managing SSD's in Arch Linux (the information applies to Parabola, as well). @@ -381,7 +381,7 @@ for the LUKS passphrase, apply here as well. You will set this password with the ### Extra Security Tweaks There are some final changes that we can make to the installation, to make it -significantly more secure; these are based on the [Security](https://wiki.archlinux.org/index.php/Securit) section of the Arch wiki. +significantly more secure; these are based on the [Security](https://wiki.archlinux.org/index.php/Security) section of the Arch wiki. #### Key Strengthening We will want to open the configuration file for password settings, and increase diff --git a/docs/gnulinux/grub_boot_installer.md b/docs/gnulinux/grub_boot_installer.md index 7086b71d..7d4375e6 100644 --- a/docs/gnulinux/grub_boot_installer.md +++ b/docs/gnulinux/grub_boot_installer.md @@ -25,7 +25,7 @@ Overwrite the drive, writing your distro ISO to it with `dd`. For example, if we That's it! You should now be able to boot the installer from your USB drive (the instructions for doing so will be given later). ## Prepare the USB drive in NetBSD -[This page](https://wiki.netbsd.org/tutorials how_to_install_netbsd_from_an_usb_memory_stick/) on the NetBSD website shows how to create a NetBSD bootable USB drive, from within NetBSD itself. You should the `dd` method documented there. This will work with any GNU+Linux ISO image. +[This page](https://wiki.netbsd.org/tutorials/how_to_install_netbsd_from_an_usb_memory_stick/) on the NetBSD website shows how to create a NetBSD bootable USB drive, from within NetBSD itself. You should the `dd` method documented there. This will work with any GNU+Linux ISO image. ## Prepare the USB drive in FreeBSD [This page](https://www.freebsd.org/doc/handbook/bsdinstall-pre.html) on the FreeBSD website shows how to create a bootable USB drive for installing FreeBSD. Use the `dd` method documented. This will work with any GNU+Linux ISO image. diff --git a/docs/hardware/gm45_remove_me.md b/docs/hardware/gm45_remove_me.md index 0ac2f49b..26e5f9f6 100644 --- a/docs/hardware/gm45_remove_me.md +++ b/docs/hardware/gm45_remove_me.md @@ -418,7 +418,7 @@ region. According to the datasheet, it's supposed to add up to 0xBABA but can actually be others on the X200. - + *"One of those engineers loves classic rock music, so they selected 0xBABA"* diff --git a/docs/hardware/x200.md b/docs/hardware/x200.md index 10f5f621..fdf992d1 100644 --- a/docs/hardware/x200.md +++ b/docs/hardware/x200.md @@ -132,12 +132,6 @@ comparing it with X200 (factory BIOS) and X200 (gm45 raminit code in coreboot), to see what the differences are. Then tweak raminit code based on that. -Trouble undocking (button doesn't work) ----------------------------------------- - -This person seems to have a workaround: - - LCD compatibility list {#lcd_supported_list} ---------------------- diff --git a/docs/install/index.md b/docs/install/index.md index d4ac2f13..6cefad56 100644 --- a/docs/install/index.md +++ b/docs/install/index.md @@ -169,7 +169,7 @@ ASUS KCMA-D8? ------------- If you have the proprietary BIOS, you need to flash libreboot -externally. See [kcma-d8.md](kgpe-d8.md). +externally. See [kcma-d8.md](kcma-d8.md). If you already have coreboot or libreboot installed, without write protection on the flash chip, then you can do it in software (otherwise, diff --git a/docs/install/rpi_setup.md b/docs/install/rpi_setup.md index e46191e7..b083aac9 100644 --- a/docs/install/rpi_setup.md +++ b/docs/install/rpi_setup.md @@ -150,7 +150,7 @@ successfully. If not, just flash again. Pi](http://scruss.com/blog/2013/02/02/simple-adc-with-the-raspberry-pi/) - [Flashing coreboot on a T60 with a Raspberry Pi - the\_unconventional's - blog](https://blogs.fsfe.org/the_unconventional/2015/05/08/flashing-coreboot-on-a-t60-with-a-raspberry-pi/) + blog](https://web.archive.org/web/20150709043222/http://blogs.fsfe.org:80/the_unconventional/2015/05/08/coreboot-t60-raspberry-pi/) - *Pomona SOIC Clip flashing* - [Arch Linux Wiki - Installing Arch Linux on Chromebook](https://wiki.archlinux.org/index.php/Chromebook) diff --git a/projects/ich9gen/sources/src/gbe/gbe.h b/projects/ich9gen/sources/src/gbe/gbe.h index 14548e71..f28f4421 100644 --- a/projects/ich9gen/sources/src/gbe/gbe.h +++ b/projects/ich9gen/sources/src/gbe/gbe.h @@ -35,7 +35,7 @@ * * Info about Gbe region (read whole datasheet): * http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf - * https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums + * https://web.archive.org/web/20150912070329/https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums */ #ifndef GBESTRUCT_H diff --git a/projects/ich9gen/sources/src/ich9deblob.c b/projects/ich9gen/sources/src/ich9deblob.c index b9153ed6..d7a57c51 100644 --- a/projects/ich9gen/sources/src/ich9deblob.c +++ b/projects/ich9gen/sources/src/ich9deblob.c @@ -42,7 +42,7 @@ * * Info about Gbe region (read whole datasheet): * http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf - * https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums + * https://web.archive.org/web/20150912070329/https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums */ #include "ich9deblob.h" diff --git a/resources/utilities/ich9deblob/src/gbe/gbe.h b/resources/utilities/ich9deblob/src/gbe/gbe.h index a1350fdd..454ab2a2 100644 --- a/resources/utilities/ich9deblob/src/gbe/gbe.h +++ b/resources/utilities/ich9deblob/src/gbe/gbe.h @@ -35,7 +35,7 @@ * * Info about Gbe region (read whole datasheet): * http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf - * https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums + * https://web.archive.org/web/20150912070329/https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums */ #ifndef GBESTRUCT_H diff --git a/resources/utilities/ich9deblob/src/ich9deblob.c b/resources/utilities/ich9deblob/src/ich9deblob.c index d79a3a89..d0fc537a 100644 --- a/resources/utilities/ich9deblob/src/ich9deblob.c +++ b/resources/utilities/ich9deblob/src/ich9deblob.c @@ -42,7 +42,7 @@ * * Info about Gbe region (read whole datasheet): * http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf - * https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums + * https://web.archive.org/web/20150912070329/https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums */ #include "ich9deblob.h" diff --git a/www/news/andrew-robbins-new-maintainer.md b/www/news/andrew-robbins-new-maintainer.md index 50c43d3a..65fd8a3c 100644 --- a/www/news/andrew-robbins-new-maintainer.md +++ b/www/news/andrew-robbins-new-maintainer.md @@ -9,7 +9,7 @@ voted on by the maintainers with community input. These policies formalise our democratic standards. Today, we welcome Andrew Robbins (IRC nick `and_who` and -[NotABug](https://notabug.org) user [kragle](https://notabug.org/kragle)) as +[NotABug](https://notabug.org) user [and_who](https://notabug.org/and_who)) as our first new maintainer under the new policy. Going forward, Andrew will gain push access to Libreboot in order to review patches, as well as voting rights and IRC operator status. -- cgit v1.2.3-70-g09d2 From 23ca4041a92c5e9f54d60033b3a19f62f628734a Mon Sep 17 00:00:00 2001 From: nicorikken Date: Tue, 19 Jun 2018 06:13:44 +0000 Subject: Pending change for CMOS value naming 'switchable graphics' -> 'dual graphics' I proposed a naming patch for the T400 CMOS value in the Coreboot project: https://review.coreboot.org/#/c/coreboot/+/27158/ As this is the only manual referring to the name of the value, this commit updates the naming to reflect the upstream change. Merging this patch becomes relevant once the coreboot patch has made it's way into Libreboot. --- docs/install/r400_external.md | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/docs/install/r400_external.md b/docs/install/r400_external.md index 366896cb..4036c761 100644 --- a/docs/install/r400_external.md +++ b/docs/install/r400_external.md @@ -44,9 +44,10 @@ A note about GPUs ================= Some models have an Intel GPU, while others have both an ATI and an -Intel GPU; this is referred to as "switchable graphics". In the *BIOS -setup* program for lenovobios, you can specify that the system will use -one or the other (but not both). +Intel GPU; this is referred to as "Dual Graphics" (previously +"switchable graphics"). In the *BIOS setup* program for lenovobios, +you can specify that the system will use one or the other (but not +both). Libreboot is known to work on systems with only the Intel GPU, using native graphics initialization. On systems with switchable graphics, the @@ -365,6 +366,7 @@ You should see something like this: Now [install GNU+Linux](../gnulinux/). Copyright © 2014, 2015 Leah Rowe \ +Copyright © 2018 Nico Rikken \ Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License Version 1.3 or any later -- cgit v1.2.3-70-g09d2 From eb12d6466ce89f49480e1ea12e8236ed2c23c6bf Mon Sep 17 00:00:00 2001 From: Leah Rowe Date: Wed, 20 Jun 2018 13:13:12 +0100 Subject: Fix incorrect date on the most recent news entry --- www/news/leah-fundraiser.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/www/news/leah-fundraiser.md b/www/news/leah-fundraiser.md index 5a5b7b20..529547eb 100644 --- a/www/news/leah-fundraiser.md +++ b/www/news/leah-fundraiser.md @@ -1,6 +1,6 @@ % Help Leah, founder of Libreboot, get Gender Reassignment Surgery % Leah Rowe -% 19 April 2017 +% 19 April 2018 I spoke with Andrew Robbins and Swift Geek on #libreboot IRC. These are two other members of the core Libreboot community. This news post was submitted to -- cgit v1.2.3-70-g09d2 From 57965e5ea62232fe0f0e7123ddf0d2b563718c48 Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Sun, 24 Jun 2018 07:51:59 +0200 Subject: Missing -o in grub-mkconfig --- docs/gnulinux/encrypted_parabola.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/gnulinux/encrypted_parabola.md b/docs/gnulinux/encrypted_parabola.md index 74c74fce..d65d076e 100644 --- a/docs/gnulinux/encrypted_parabola.md +++ b/docs/gnulinux/encrypted_parabola.md @@ -422,7 +422,7 @@ Edit configuration in `/etc/default/grub`, remembering to use UUID when poitning Use `blkid` to get list of devices with their respective UUIDs. Next generate grub.cfg with - # grub-mkconfig /boot/grub/grub.cfg + # grub-mkconfig -o /boot/grub/grub.cfg If you have separate `/boot` partition, don't forget to add `boot` symlink inside that points to current directory -- cgit v1.2.3-70-g09d2 From 608c4e066dd3722269747fc61d238f1513e9237a Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Sun, 24 Jun 2018 08:04:36 +0200 Subject: Clarify memtest86+ section --- docs/install/index.md | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/docs/install/index.md b/docs/install/index.md index d4ac2f13..677fd244 100644 --- a/docs/install/index.md +++ b/docs/install/index.md @@ -62,10 +62,12 @@ they don't have to build anything from source on their own. The ROM images in each archive use the following at the end of the file name, if they are built with the GRUB payload: `*_*keymap*_*mode*.rom` -Available `modes`: `vesafb` or `txtmode`. The `vesafb` ROM images -are recommended, in most cases; `txtmode` ROM images come with -MemTest86+, which requires text-mode instead of the usual framebuffer -used by coreboot native graphics initialization. +Available modes: vesafb or txtmode. The vesafb ROM images are recommended +for regular use, but when flashing for the first time use txtmode version, +as it comes with Memtest86+, which requires text-mode instead of the usual +framebuffer used by coreboot native graphics initialization. +Machine should be tested with Memtest86+ after each reassembly or changing +from vendor bios to libreboot due to differences in raminit code. `keymap` can be one of several keymaps that keyboard supports (there are quite a few), which affects the keyboard layout configuration that is -- cgit v1.2.3-70-g09d2 From 6d182768a602fb6aaa56d4b5584356c9c17fe6ff Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Sun, 24 Jun 2018 08:13:13 +0200 Subject: FAQ entry for grub cryptomount errors --- www/faq.md | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/www/faq.md b/www/faq.md index 547fea6d..64958de8 100644 --- a/www/faq.md +++ b/www/faq.md @@ -140,6 +140,15 @@ around this by running the following command: You can find *cbfstool* in the \_util archive with the libreboot release that you are using. +What are the ata/ahci errors I see in libreboot's GRUB? +----------------------------------------------------------------------- + +You can safely ignore those errors, they exist because we can't quiet down +cryptomount command from `for` loop in libreboot's +[grub.cfg](https://notabug.org/libreboot/libreboot/src/r20160907/resources/grub/config/menuentries/common.cfg#L66) +It could be fixed in upstream grub by contributing patch that would add +quiet flag to it. + Hardware compatibility ====================== -- cgit v1.2.3-70-g09d2 From 0566efc6478aec54b9371c613afafae4b359fb0c Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Sun, 24 Jun 2018 08:49:38 +0200 Subject: Add FAQ entry for expanding knowledge about electronics --- www/faq.md | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/www/faq.md b/www/faq.md index 64958de8..ccbee214 100644 --- a/www/faq.md +++ b/www/faq.md @@ -145,7 +145,7 @@ What are the ata/ahci errors I see in libreboot's GRUB? You can safely ignore those errors, they exist because we can't quiet down cryptomount command from `for` loop in libreboot's -[grub.cfg](https://notabug.org/libreboot/libreboot/src/r20160907/resources/grub/config/menuentries/common.cfg#L66) +[grub.cfg](https://notabug.org/libreboot/libreboot/src/r20160907/resources/grub/config/menuentries/common.cfg#L66). It could be fixed in upstream grub by contributing patch that would add quiet flag to it. @@ -909,10 +909,8 @@ connect SATA HDDs via USB. Libreboot documents how to install several distributions with full disk encryption. You can adapt these for use with USB drives: -- [Full disk encryption with - Debian](../docs/gnulinux/encrypted_debian.md) -- [Full disk encryption with - Parabola](../docs/gnulinux/encrypted_parabola.md) +- [Full disk encryption with Debian](../docs/gnulinux/encrypted_debian.md) +- [Full disk encryption with Parabola](../docs/gnulinux/encrypted_parabola.md) The current theory (unproven) is that this will at least prevent malicious drives from wrongly manipulating data being read from or @@ -1043,3 +1041,32 @@ Are other operating systems compatible? Unknown. Probably not. +Where can I learn more about electronics +========================================== + +* Basics of soldering and rework by PACE + Both series of videos are mandatory regardless of your soldering skill. + * [Basic Soldering](https://www.youtube.com/watch?v=vIT4ra6Mo0s&list=PL926EC0F1F93C1837) + * [Rework and Repair](https://www.youtube.com/watch?v=HKX-GBe_lUI&list=PL958FF32927823D12) +* [edX course on basics of electronics](https://www.edx.org/course/circuits-electronics-1-basic-circuit-mitx-6-002-1x-0) + In most countries contents of this course is covered during + middle and high school. It will also serve well to refresh your memory + if you haven't used that knowledge ever since. +* Impedance intro + * [Similiarities of Wave Behavior](https://www.youtube.com/watch?v=DovunOxlY1k) + * [Reflections in tranmission line](https://www.youtube.com/watch?v=y8GMH7vMAsQ) + * Stubs: + * [Wikipedia article on stubs](https://en.wikipedia.org/wiki/Stub_(electronics)) + * [Polar Instruments article on stubs](http://www.polarinstruments.com/support/si/AP8166.html) + With external SPI flashing we only care about unintended PCB stubs +* Other YouTube channels with useful content about electronics + * [EEVblog](https://www.youtube.com/channel/UC2DjFE7Xf11URZqWBigcVOQ) + * [Louis Rossmann](https://www.youtube.com/channel/UCl2mFZoRqjw_ELax4Yisf6w) + * [mikeselectricstuff](https://www.youtube.com/channel/UCcs0ZkP_as4PpHDhFcmCHyA) + * [bigclive](https://www.youtube.com/channel/UCtM5z2gkrGRuWd0JQMx76qA) + * [ElectroBOOM](https://www.youtube.com/channel/UCJ0-OtVpF0wOKEqT2Z1HEtA) + * [Jeri Ellsworth](https://www.youtube.com/user/jeriellsworth/playlists) +* Boardview files can be open with [OpenBoardview](https://github.com/OpenBoardView/OpenBoardView), +which is free software under MIT license. + +Use of youtube-dl with mpv would be recommended for youtube links -- cgit v1.2.3-70-g09d2 From 2bac42b742a0217396dd68f4c77c40cf2360f04a Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Sun, 24 Jun 2018 15:09:56 +0200 Subject: Improve T500 sodimm notes --- docs/install/t500_external.md | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/install/t500_external.md b/docs/install/t500_external.md index c9b85a5d..9e114bca 100644 --- a/docs/install/t500_external.md +++ b/docs/install/t500_external.md @@ -362,11 +362,12 @@ Not to be confused with wifi (wifi is fine). Memory ====== -You need DDR3 SODIMM PC3-8500 RAM installed, in matching pairs -(speed/size). Non-matching pairs won't work. You can also install a +DDR3 SO-DIMM sticks will work at PC3-8500 clock and voltage, so make sure that +timings of sticks are matched while they operate at its frequency. +Non-matching pairs won't work. You can also install a single module (meaning, one of the slots will be empty) in slot 0. -Make sure that the RAM you buy is the 2Rx8 density. +Make sure that the RAM you buy has 2Rx8 arrangement when buying 4GiB modules. [This page](http://www.forum.thinkpads.com/viewtopic.php?p=760721) might be useful for RAM compatibility info (note: coreboot raminit is -- cgit v1.2.3-70-g09d2 From 817e68fee7c6ddd1852543326b77e2f0887fd6e2 Mon Sep 17 00:00:00 2001 From: "John M. Harris, Jr" Date: Sun, 24 Jun 2018 10:33:44 -0400 Subject: Clone seabios over HTTPS instead of git protocol --- resources/scripts/helpers/download/seabios | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/resources/scripts/helpers/download/seabios b/resources/scripts/helpers/download/seabios index 75299f2d..b773ec59 100755 --- a/resources/scripts/helpers/download/seabios +++ b/resources/scripts/helpers/download/seabios @@ -35,7 +35,7 @@ rm -rf "seabios/" # ------------------------------------------------------------------------------ # download it using git -git clone git://git.seabios.org/seabios.git seabios +git clone https://git.seabios.org/seabios.git seabios ( # modifications are required -- cgit v1.2.3-70-g09d2 From a8f882d78868970d2ca74a5638c791bd90c6b1f0 Mon Sep 17 00:00:00 2001 From: "John M. Harris, Jr" Date: Mon, 25 Jun 2018 02:58:49 -0400 Subject: Add reproducible build patches to GRUB --- ...e-add-argument-fixed-time-to-override-mti.patch | 73 ++++++++++++++++++++++ ...d-argument-fixed-time-to-get-reproducible.patch | 68 ++++++++++++++++++++ ...e-FIXED_TIMESTAMP-for-mkstandalone-if-set.patch | 30 +++++++++ resources/scripts/helpers/download/grub | 5 ++ 4 files changed, 176 insertions(+) create mode 100644 resources/grub/patch/reproducible/0001-mkstandalone-add-argument-fixed-time-to-override-mti.patch create mode 100644 resources/grub/patch/reproducible/0002-mkrescue-add-argument-fixed-time-to-get-reproducible.patch create mode 100644 resources/grub/patch/reproducible/0003-Makefile-use-FIXED_TIMESTAMP-for-mkstandalone-if-set.patch diff --git a/resources/grub/patch/reproducible/0001-mkstandalone-add-argument-fixed-time-to-override-mti.patch b/resources/grub/patch/reproducible/0001-mkstandalone-add-argument-fixed-time-to-override-mti.patch new file mode 100644 index 00000000..1d537e87 --- /dev/null +++ b/resources/grub/patch/reproducible/0001-mkstandalone-add-argument-fixed-time-to-override-mti.patch @@ -0,0 +1,73 @@ +From 8dde1d7be2dd321a375570b7ff7e22bb01293044 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Fri, 4 Dec 2015 17:10:42 +0100 +Subject: [PATCH 08/10] mkstandalone: add argument --fixed-time to override + mtime of files + +mkstandalone adds several files to an archive. Doing this it uses the +mtime to give these files a timestamp. +--fixed-time overrides these timestamps with a given. + +Replacing all timestamps with a specific one is required +to get reproducible builds. See source epoch specification of +reproducible-builds.org +--- + util/grub-mkstandalone.c | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/util/grub-mkstandalone.c b/util/grub-mkstandalone.c +index 4907d44..047f0cd 100644 +--- a/util/grub-mkstandalone.c ++++ b/util/grub-mkstandalone.c +@@ -30,6 +30,7 @@ + #pragma GCC diagnostic error "-Wmissing-prototypes" + #pragma GCC diagnostic error "-Wmissing-declarations" + ++static time_t fixed_time; + static char *output_image; + static char **files; + static int nfiles; +@@ -48,6 +49,7 @@ static struct argp_option options[] = { + 0, N_("save output in FILE [required]"), 2}, + {"format", 'O', N_("FILE"), 0, 0, 2}, + {"compression", 'C', "xz|none|auto", OPTION_HIDDEN, 0, 2}, ++ {"fixed-time", 't', N_("TIMEEPOCH"), 0, N_("Use a fixed timestamp to override mtime of all files. Time since epoch is used."), 2}, + {0, 0, 0, 0, 0, 0} + }; + +@@ -72,6 +74,7 @@ help_filter (int key, const char *text, void *input __attribute__ ((unused))) + static error_t + argp_parser (int key, char *arg, struct argp_state *state) + { ++ char *b; + if (key == 'C') + key = GRUB_INSTALL_OPTIONS_INSTALL_CORE_COMPRESS; + +@@ -80,6 +83,14 @@ argp_parser (int key, char *arg, struct argp_state *state) + + switch (key) + { ++ case 't': ++ fixed_time = strtoll (arg, &b, 10); ++ if (*b !='\0') { ++ printf (_("invalid fixed time number: %s\n"), arg); ++ argp_usage (state); ++ exit (1); ++ } ++ break; + + case 'o': + if (output_image) +@@ -192,7 +203,8 @@ add_tar_file (const char *from, + if (grub_util_is_special_file (from)) + return; + +- mtime = grub_util_get_mtime (from); ++ /* use fixed_time if given for mtime */ ++ mtime = fixed_time != -1 ? fixed_time : grub_util_get_mtime (from); + + optr = tcn = xmalloc (strlen (to) + 1); + for (iptr = to; *iptr == '/'; iptr++); +-- +1.9.1 + diff --git a/resources/grub/patch/reproducible/0002-mkrescue-add-argument-fixed-time-to-get-reproducible.patch b/resources/grub/patch/reproducible/0002-mkrescue-add-argument-fixed-time-to-get-reproducible.patch new file mode 100644 index 00000000..0612ade0 --- /dev/null +++ b/resources/grub/patch/reproducible/0002-mkrescue-add-argument-fixed-time-to-get-reproducible.patch @@ -0,0 +1,68 @@ +From 0f1e1a29d4d019e7b2b1a3ac3db7ca22c75e8d88 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Fri, 4 Dec 2015 17:10:43 +0100 +Subject: [PATCH 09/10] mkrescue: add argument --fixed-time to get reproducible + uuids + +The uuid generation is based on the time. +--- + util/grub-mkrescue.c | 15 ++++++++++++++- + 1 file changed, 14 insertions(+), 1 deletion(-) + +diff --git a/util/grub-mkrescue.c b/util/grub-mkrescue.c +index 238d484..a3e0155 100644 +--- a/util/grub-mkrescue.c ++++ b/util/grub-mkrescue.c +@@ -52,6 +52,7 @@ static int xorriso_arg_alloc; + static char **xorriso_argv; + static char *iso_uuid; + static char *iso9660_dir; ++static time_t fixed_time; + + static void + xorriso_push (const char *val) +@@ -110,6 +111,7 @@ static struct argp_option options[] = { + {"product-version", OPTION_PRODUCT_VERSION, N_("STRING"), 0, N_("use STRING as product version"), 2}, + {"sparc-boot", OPTION_SPARC_BOOT, 0, 0, N_("enable sparc boot. Disables HFS+, APM, ARCS and boot as disk image for i386-pc"), 2}, + {"arcs-boot", OPTION_ARCS_BOOT, 0, 0, N_("enable ARCS (big-endian mips machines, mostly SGI) boot. Disables HFS+, APM, sparc64 and boot as disk image for i386-pc"), 2}, ++ {"fixed-time", 't', N_("TIMEEPOCH"), 0, N_("use a fixed timestamp for uuid generation"), 2}, + {0, 0, 0, 0, 0, 0} + }; + +@@ -153,6 +155,8 @@ enum { + static error_t + argp_parser (int key, char *arg, struct argp_state *state) + { ++ char *b; ++ + if (grub_install_parse (key, arg)) + return 0; + switch (key) +@@ -212,6 +216,15 @@ argp_parser (int key, char *arg, struct argp_state *state) + xorriso = xstrdup (arg); + return 0; + ++ case 't': ++ fixed_time = strtoll (arg, &b, 10); ++ if (*b !='\0') { ++ printf (_("invalid fixed time number: %s\n"), arg); ++ argp_usage (state); ++ exit (1); ++ } ++ return 0; ++ + default: + return ARGP_ERR_UNKNOWN; + } +@@ -542,7 +555,7 @@ main (int argc, char *argv[]) + { + time_t tim; + struct tm *tmm; +- tim = time (NULL); ++ tim = fixed_time != -1 ? fixed_time : time (NULL); + tmm = gmtime (&tim); + iso_uuid = xmalloc (55); + grub_snprintf (iso_uuid, 50, +-- +1.9.1 + diff --git a/resources/grub/patch/reproducible/0003-Makefile-use-FIXED_TIMESTAMP-for-mkstandalone-if-set.patch b/resources/grub/patch/reproducible/0003-Makefile-use-FIXED_TIMESTAMP-for-mkstandalone-if-set.patch new file mode 100644 index 00000000..f06dbfb5 --- /dev/null +++ b/resources/grub/patch/reproducible/0003-Makefile-use-FIXED_TIMESTAMP-for-mkstandalone-if-set.patch @@ -0,0 +1,30 @@ +From 57174ed960905be4f9c229bbf3913b25745dbfd9 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Fri, 4 Dec 2015 17:10:44 +0100 +Subject: [PATCH 10/10] Makefile: use FIXED_TIMESTAMP for mkstandalone if set + +mkstandalone sets timestamps for files which can be overriden by a fixed_timestamp. +This makes it possible to build reproducible builds for coreboot. + +To build a reproducible build of grub for coreboot do: +make default_payload.elf FIXED_TIMESTAMP=1134242 +--- + Makefile.am | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/Makefile.am b/Makefile.am +index 00a9663..ed7f148 100644 +--- a/Makefile.am ++++ b/Makefile.am +@@ -411,7 +411,7 @@ bootcheck: $(BOOTCHECKS) + if COND_i386_coreboot + default_payload.elf: grub-mkstandalone grub-mkimage FORCE + test -f $@ && rm $@ || true +- pkgdatadir=. ./grub-mkstandalone --grub-mkimage=./grub-mkimage -O i386-coreboot -o $@ --modules='ahci pata ehci uhci ohci usb_keyboard usbms part_msdos ext2 fat at_keyboard part_gpt usbserial_usbdebug cbfs' --install-modules='ls linux search configfile normal cbtime cbls memrw iorw minicmd lsmmap lspci halt reboot hexdump pcidump regexp setpci lsacpi chain test serial multiboot cbmemc linux16 gzio echo help syslinuxcfg xnu $(shell cat grub-core/fs.lst) password_pbkdf2 $(EXTRA_PAYLOAD_MODULES)' --fonts= --themes= --locales= -d grub-core/ /boot/grub/grub.cfg=$(srcdir)/coreboot.cfg ++ pkgdatadir=. ./grub-mkstandalone --grub-mkimage=./grub-mkimage -O i386-coreboot -o $@ --modules='ahci pata ehci uhci ohci usb_keyboard usbms part_msdos ext2 fat at_keyboard part_gpt usbserial_usbdebug cbfs' --install-modules='ls linux search configfile normal cbtime cbls memrw iorw minicmd lsmmap lspci halt reboot hexdump pcidump regexp setpci lsacpi chain test serial multiboot cbmemc linux16 gzio echo help syslinuxcfg xnu $(shell cat grub-core/fs.lst) password_pbkdf2 $(EXTRA_PAYLOAD_MODULES)' --fonts= --themes= --locales= -d grub-core/ /boot/grub/grub.cfg=$(srcdir)/coreboot.cfg $(if $(FIXED_TIMESTAMP),-t $(FIXED_TIMESTAMP)) + endif + + endif +-- +1.9.1 + diff --git a/resources/scripts/helpers/download/grub b/resources/scripts/helpers/download/grub index c0a298cb..3ec8a8fb 100755 --- a/resources/scripts/helpers/download/grub +++ b/resources/scripts/helpers/download/grub @@ -49,6 +49,11 @@ git reset --hard e54c99aaff5e5f6f5d3b06028506c57e66d8ef77 # Replace "GNU GRUB version" in GRUB screen with "FREE AS IN FREEDOM" git am "../resources/grub/patch/0001-grub-core-normal-main.c-Display-FREE-AS-IN-FREEDOM-n.patch" +# Enable reproducible builds +git am "../resources/grub/patch/reproducible/0001-mkstandalone-add-argument-fixed-time-to-override-mti.patch" +git am "../resources/grub/patch/reproducible/0002-mkrescue-add-argument-fixed-time-to-get-reproducible.patch" +git am "../resources/grub/patch/reproducible/0003-Makefile-use-FIXED_TIMESTAMP-for-mkstandalone-if-set.patch" + cd "../" # Also download SeaBIOS, which we use with GRUB, to implement SeaGRUB -- cgit v1.2.3-70-g09d2 From 2373ddab15df2f7cb71993c5dafcb09cbb2f3ac0 Mon Sep 17 00:00:00 2001 From: "John M. Harris, Jr" Date: Mon, 25 Jun 2018 12:30:55 -0400 Subject: Move organized patches to project directory for newbuild The new build system just applies all patches in the directory, so we can't have a properly organized structure. --- ...e-add-argument-fixed-time-to-override-mti.patch | 73 ++++++++++++++++++++++ ...d-argument-fixed-time-to-get-reproducible.patch | 68 ++++++++++++++++++++ ...e-FIXED_TIMESTAMP-for-mkstandalone-if-set.patch | 30 +++++++++ 3 files changed, 171 insertions(+) create mode 100644 projects/grub/patches/0001-mkstandalone-add-argument-fixed-time-to-override-mti.patch create mode 100644 projects/grub/patches/0002-mkrescue-add-argument-fixed-time-to-get-reproducible.patch create mode 100644 projects/grub/patches/0003-Makefile-use-FIXED_TIMESTAMP-for-mkstandalone-if-set.patch diff --git a/projects/grub/patches/0001-mkstandalone-add-argument-fixed-time-to-override-mti.patch b/projects/grub/patches/0001-mkstandalone-add-argument-fixed-time-to-override-mti.patch new file mode 100644 index 00000000..1d537e87 --- /dev/null +++ b/projects/grub/patches/0001-mkstandalone-add-argument-fixed-time-to-override-mti.patch @@ -0,0 +1,73 @@ +From 8dde1d7be2dd321a375570b7ff7e22bb01293044 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Fri, 4 Dec 2015 17:10:42 +0100 +Subject: [PATCH 08/10] mkstandalone: add argument --fixed-time to override + mtime of files + +mkstandalone adds several files to an archive. Doing this it uses the +mtime to give these files a timestamp. +--fixed-time overrides these timestamps with a given. + +Replacing all timestamps with a specific one is required +to get reproducible builds. See source epoch specification of +reproducible-builds.org +--- + util/grub-mkstandalone.c | 14 +++++++++++++- + 1 file changed, 13 insertions(+), 1 deletion(-) + +diff --git a/util/grub-mkstandalone.c b/util/grub-mkstandalone.c +index 4907d44..047f0cd 100644 +--- a/util/grub-mkstandalone.c ++++ b/util/grub-mkstandalone.c +@@ -30,6 +30,7 @@ + #pragma GCC diagnostic error "-Wmissing-prototypes" + #pragma GCC diagnostic error "-Wmissing-declarations" + ++static time_t fixed_time; + static char *output_image; + static char **files; + static int nfiles; +@@ -48,6 +49,7 @@ static struct argp_option options[] = { + 0, N_("save output in FILE [required]"), 2}, + {"format", 'O', N_("FILE"), 0, 0, 2}, + {"compression", 'C', "xz|none|auto", OPTION_HIDDEN, 0, 2}, ++ {"fixed-time", 't', N_("TIMEEPOCH"), 0, N_("Use a fixed timestamp to override mtime of all files. Time since epoch is used."), 2}, + {0, 0, 0, 0, 0, 0} + }; + +@@ -72,6 +74,7 @@ help_filter (int key, const char *text, void *input __attribute__ ((unused))) + static error_t + argp_parser (int key, char *arg, struct argp_state *state) + { ++ char *b; + if (key == 'C') + key = GRUB_INSTALL_OPTIONS_INSTALL_CORE_COMPRESS; + +@@ -80,6 +83,14 @@ argp_parser (int key, char *arg, struct argp_state *state) + + switch (key) + { ++ case 't': ++ fixed_time = strtoll (arg, &b, 10); ++ if (*b !='\0') { ++ printf (_("invalid fixed time number: %s\n"), arg); ++ argp_usage (state); ++ exit (1); ++ } ++ break; + + case 'o': + if (output_image) +@@ -192,7 +203,8 @@ add_tar_file (const char *from, + if (grub_util_is_special_file (from)) + return; + +- mtime = grub_util_get_mtime (from); ++ /* use fixed_time if given for mtime */ ++ mtime = fixed_time != -1 ? fixed_time : grub_util_get_mtime (from); + + optr = tcn = xmalloc (strlen (to) + 1); + for (iptr = to; *iptr == '/'; iptr++); +-- +1.9.1 + diff --git a/projects/grub/patches/0002-mkrescue-add-argument-fixed-time-to-get-reproducible.patch b/projects/grub/patches/0002-mkrescue-add-argument-fixed-time-to-get-reproducible.patch new file mode 100644 index 00000000..0612ade0 --- /dev/null +++ b/projects/grub/patches/0002-mkrescue-add-argument-fixed-time-to-get-reproducible.patch @@ -0,0 +1,68 @@ +From 0f1e1a29d4d019e7b2b1a3ac3db7ca22c75e8d88 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Fri, 4 Dec 2015 17:10:43 +0100 +Subject: [PATCH 09/10] mkrescue: add argument --fixed-time to get reproducible + uuids + +The uuid generation is based on the time. +--- + util/grub-mkrescue.c | 15 ++++++++++++++- + 1 file changed, 14 insertions(+), 1 deletion(-) + +diff --git a/util/grub-mkrescue.c b/util/grub-mkrescue.c +index 238d484..a3e0155 100644 +--- a/util/grub-mkrescue.c ++++ b/util/grub-mkrescue.c +@@ -52,6 +52,7 @@ static int xorriso_arg_alloc; + static char **xorriso_argv; + static char *iso_uuid; + static char *iso9660_dir; ++static time_t fixed_time; + + static void + xorriso_push (const char *val) +@@ -110,6 +111,7 @@ static struct argp_option options[] = { + {"product-version", OPTION_PRODUCT_VERSION, N_("STRING"), 0, N_("use STRING as product version"), 2}, + {"sparc-boot", OPTION_SPARC_BOOT, 0, 0, N_("enable sparc boot. Disables HFS+, APM, ARCS and boot as disk image for i386-pc"), 2}, + {"arcs-boot", OPTION_ARCS_BOOT, 0, 0, N_("enable ARCS (big-endian mips machines, mostly SGI) boot. Disables HFS+, APM, sparc64 and boot as disk image for i386-pc"), 2}, ++ {"fixed-time", 't', N_("TIMEEPOCH"), 0, N_("use a fixed timestamp for uuid generation"), 2}, + {0, 0, 0, 0, 0, 0} + }; + +@@ -153,6 +155,8 @@ enum { + static error_t + argp_parser (int key, char *arg, struct argp_state *state) + { ++ char *b; ++ + if (grub_install_parse (key, arg)) + return 0; + switch (key) +@@ -212,6 +216,15 @@ argp_parser (int key, char *arg, struct argp_state *state) + xorriso = xstrdup (arg); + return 0; + ++ case 't': ++ fixed_time = strtoll (arg, &b, 10); ++ if (*b !='\0') { ++ printf (_("invalid fixed time number: %s\n"), arg); ++ argp_usage (state); ++ exit (1); ++ } ++ return 0; ++ + default: + return ARGP_ERR_UNKNOWN; + } +@@ -542,7 +555,7 @@ main (int argc, char *argv[]) + { + time_t tim; + struct tm *tmm; +- tim = time (NULL); ++ tim = fixed_time != -1 ? fixed_time : time (NULL); + tmm = gmtime (&tim); + iso_uuid = xmalloc (55); + grub_snprintf (iso_uuid, 50, +-- +1.9.1 + diff --git a/projects/grub/patches/0003-Makefile-use-FIXED_TIMESTAMP-for-mkstandalone-if-set.patch b/projects/grub/patches/0003-Makefile-use-FIXED_TIMESTAMP-for-mkstandalone-if-set.patch new file mode 100644 index 00000000..f06dbfb5 --- /dev/null +++ b/projects/grub/patches/0003-Makefile-use-FIXED_TIMESTAMP-for-mkstandalone-if-set.patch @@ -0,0 +1,30 @@ +From 57174ed960905be4f9c229bbf3913b25745dbfd9 Mon Sep 17 00:00:00 2001 +From: Alexander Couzens +Date: Fri, 4 Dec 2015 17:10:44 +0100 +Subject: [PATCH 10/10] Makefile: use FIXED_TIMESTAMP for mkstandalone if set + +mkstandalone sets timestamps for files which can be overriden by a fixed_timestamp. +This makes it possible to build reproducible builds for coreboot. + +To build a reproducible build of grub for coreboot do: +make default_payload.elf FIXED_TIMESTAMP=1134242 +--- + Makefile.am | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/Makefile.am b/Makefile.am +index 00a9663..ed7f148 100644 +--- a/Makefile.am ++++ b/Makefile.am +@@ -411,7 +411,7 @@ bootcheck: $(BOOTCHECKS) + if COND_i386_coreboot + default_payload.elf: grub-mkstandalone grub-mkimage FORCE + test -f $@ && rm $@ || true +- pkgdatadir=. ./grub-mkstandalone --grub-mkimage=./grub-mkimage -O i386-coreboot -o $@ --modules='ahci pata ehci uhci ohci usb_keyboard usbms part_msdos ext2 fat at_keyboard part_gpt usbserial_usbdebug cbfs' --install-modules='ls linux search configfile normal cbtime cbls memrw iorw minicmd lsmmap lspci halt reboot hexdump pcidump regexp setpci lsacpi chain test serial multiboot cbmemc linux16 gzio echo help syslinuxcfg xnu $(shell cat grub-core/fs.lst) password_pbkdf2 $(EXTRA_PAYLOAD_MODULES)' --fonts= --themes= --locales= -d grub-core/ /boot/grub/grub.cfg=$(srcdir)/coreboot.cfg ++ pkgdatadir=. ./grub-mkstandalone --grub-mkimage=./grub-mkimage -O i386-coreboot -o $@ --modules='ahci pata ehci uhci ohci usb_keyboard usbms part_msdos ext2 fat at_keyboard part_gpt usbserial_usbdebug cbfs' --install-modules='ls linux search configfile normal cbtime cbls memrw iorw minicmd lsmmap lspci halt reboot hexdump pcidump regexp setpci lsacpi chain test serial multiboot cbmemc linux16 gzio echo help syslinuxcfg xnu $(shell cat grub-core/fs.lst) password_pbkdf2 $(EXTRA_PAYLOAD_MODULES)' --fonts= --themes= --locales= -d grub-core/ /boot/grub/grub.cfg=$(srcdir)/coreboot.cfg $(if $(FIXED_TIMESTAMP),-t $(FIXED_TIMESTAMP)) + endif + + endif +-- +1.9.1 + -- cgit v1.2.3-70-g09d2 From b10bb838279c1fdd31fb832430b036940f457974 Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Tue, 26 Jun 2018 18:24:13 +0200 Subject: Change space to non-breaking space U+00A0 --- docs/install/index.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/install/index.md b/docs/install/index.md index d4ac2f13..c4ed5dc9 100644 --- a/docs/install/index.md +++ b/docs/install/index.md @@ -264,13 +264,13 @@ executables from the libreboot source code archives. How to update the flash chip contents: -`$ sudo ./flash update `[`yourrom.rom`](#rom) +`$ sudo ./flash update `[`yourrom.rom`](#rom) Ocassionally, coreboot changes the name of a given board. If flashrom complains about a board mismatch, but you are sure that you chose the correct ROM image, then run this alternative command: - `$ sudo ./flash forceupdate `[`yourrom.rom`](#rom) + `$ sudo ./flash forceupdate `[`yourrom.rom`](#rom) You should see `Verifying flash... VERIFIED.` written at the end of the flashrom output. *Shut down* after you see this, and then boot -- cgit v1.2.3-70-g09d2 From 1fb8dafbb9e59de5c48b976fe511c58175a731f8 Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Tue, 26 Jun 2018 18:58:59 +0200 Subject: Missed from previous nbsp commit --- docs/install/index.md | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/install/index.md b/docs/install/index.md index c4ed5dc9..7639c14d 100644 --- a/docs/install/index.md +++ b/docs/install/index.md @@ -305,7 +305,7 @@ the flashing script. do this: * The first half of the procedure is as follows: -`$ sudo ./flash i945lenovo_firstflash `[`yourrom.rom`](#rom) +`$ sudo ./flash i945lenovo_firstflash `[`yourrom.rom`](#rom) You should see within the output the following: @@ -332,11 +332,11 @@ needed (see below). When you have booted up again, you must also do this: -`$ sudo ./flash i945lenovo_secondflash `[`yourrom.rom`](#rom) +`$ sudo ./flash i945lenovo_secondflash `[`yourrom.rom`](#rom) If flashing fails at this stage, try the following: -`$ sudo ./flashrom/i686/flashrom -p internal:laptop=force_I_want_a_brick -w `[`yourrom.rom`](#rom) +`$ sudo ./flashrom/i686/flashrom -p internal:laptop=force_I_want_a_brick -w `[`yourrom.rom`](#rom) You should see within the output the following: @@ -372,7 +372,7 @@ with your device. Use this flashing script, to install libreboot: -`$ sudo ./flash i945apple_firstflash `[`yourrom.rom`](#rom) +`$ sudo ./flash i945apple_firstflash `[`yourrom.rom`](#rom) You should also see within the output the following: -- cgit v1.2.3-70-g09d2 From a5348fe90a197736a020a87905e3d5f27f0a988f Mon Sep 17 00:00:00 2001 From: Sebastian 'Swift Geek' Grzywna Date: Tue, 26 Jun 2018 19:04:01 +0200 Subject: install/index.md: Remove -V from flashrom command --- docs/install/index.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/install/index.md b/docs/install/index.md index 677fd244..67c5d722 100644 --- a/docs/install/index.md +++ b/docs/install/index.md @@ -246,7 +246,7 @@ Flash chip size Use this to find out: - # flashrom -p internal -V + # flashrom -p internal All good? --------- -- cgit v1.2.3-70-g09d2 From f1ed499c93eeb8f908ea685fe781759234f87a4d Mon Sep 17 00:00:00 2001 From: "John M. Harris, Jr" Date: Fri, 13 Jul 2018 14:22:26 -0400 Subject: Fix link to information about HDD/SSD firmware --- docs/gnulinux/grub_hardening.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/gnulinux/grub_hardening.md b/docs/gnulinux/grub_hardening.md index 9eb7237e..e1329f21 100644 --- a/docs/gnulinux/grub_hardening.md +++ b/docs/gnulinux/grub_hardening.md @@ -33,7 +33,7 @@ Helpful links: - [GRUB manual](https://www.gnu.org/software/grub/manual/html_node/Security.html#Security) - [GRUB info pages](http://git.savannah.gnu.org/cgit/grub.git/tree/docs/grub.texi) -- [SATA connected storage considered dangerous.](../../faq.md#firmware-hddssd) +- [SATA connected storage considered dangerous.](../../faq.md#hddssd-firmware) - [Coreboot GRUB security howto](https://www.coreboot.org/GRUB2#Security) GRUB Password -- cgit v1.2.3-70-g09d2 From ac86366fb364b41e69301db232021b33c5651af0 Mon Sep 17 00:00:00 2001 From: "John M. Harris, Jr" Date: Sat, 21 Jul 2018 20:30:28 -0400 Subject: Remove Peers Community mirror link "As of 2018-06-27, the mirrors have shutdown" --- www/download.md | 3 --- 1 file changed, 3 deletions(-) diff --git a/www/download.md b/www/download.md index c12b8b07..5dc046a8 100644 --- a/www/download.md +++ b/www/download.md @@ -46,9 +46,6 @@ of Kent, UK) (Princeton university, USA) - (Peers Community -Project, USA) - (sugol.org) (formerly nephelai.zanity.net/mirror/libreboot) -- cgit v1.2.3-70-g09d2