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ASUS Chromebook C201

- -

- This is a Chromebook, using the Rockchip RK3288 SoC. It uses - an ARM CPU, and has free EC firmware (unlike some other laptops). - More RK3288-based laptops will be added to libreboot at a later date. -

- Paul Kocialkowski, a Replicant developer, ported this laptop to libreboot. Thank you, Paul! -

- -

- More info will be added later, including build/installation instructions. - The board is supported in libreboot, however, and has been confirmed to work. -

- -

- Flashing instructions can be found at ../install/#flashrom -

- -

- Back to previous index. -

- -

Google's intent with CrOS devices
Considerations about ChromeOS and free operating systems
Caution: Video acceleration requires a non-free blob, software rendering can be used instead.
Caution: WiFi requires a non-free blob, a USB dongle can be used instead.
EC firmware is free software!
No microcode!
Depthcharge payload
Flash chip write protection: the screw

- -

Google's intent with CrOS devices

- CrOS (Chromium OS/Chrome OS) devices, such as Chromebooks, were not designed with the intent of bringing more freedom to users. - However, they run with a lot of free software at the boot software and embedded controller levels, - since free software gives Google enough flexibility to optimize various aspects such as boot time - and most importantly, to implement the CrOS security system, that involves various aspects of the software. - Google does hire a lot of Coreboot developers, who are generally friendly to the free software movement - and try to be good members of the free software community, by contributing code back. -

- CrOS devices are designed (from the factory) to actually coax the user into using - proprietary web services - (SaaSS) that invade the user's privacy (ChromeOS is literally just the Google Chrome browser when you boot up, itself proprietary - and comes with proprietary add-ons like flash. It's only intended for SaaSS, not actual, real computing). - Google is even a member of the PRISM program, as outlined - by Edward Snowden. See notes about ChromeOS below. The libreboot project recommends - that the user replace the default ChromeOS with a distribution that can be used in freedom, - without invading the user's privacy. -

- We also use a similar argument for the MacBook and the ThinkPads that are supported in libreboot. - Those laptops are supported, in spite of Apple and Lenovo, companies which are actually hostile - to the free software movement. -

- Back to top of page. -

- -

Considerations about ChromeOS and free operating systems

- This laptop comes preinstalled (from the factory) with Google ChromeOS. This is a GNU+Linux distribution, but it's not general purpose - and it comes with proprietary software. It's designed for SaaSS. Libreboot recommends that users of this laptop replace it with another distribution. -

- Use one of the distributions recommend by the libreboot project. - See ../distros/ -

Debian GNU+Linux

- https://wiki.debian.org/InstallingDebianOn/Asus/C201 - shows how to install Debian. -

- TODO: instructions for Devuan -

- Back to top of page. -

- -

Caution: Video acceleration requires a non-free blob, software rendering can be used instead.

- The Tamil driver source code for the onboard Mali T GPU is not released. The developer has so-far withheld it. Until that is released, the only way to use video (in freedom) on this laptop is to not have video acceleration, by making sure not to install the relevant blob. Most tasks can still be performed without video acceleration, without any noticeable performance penalty. -

- In practise, this means that certain things like games, blender and GNOME shell (or other fancy desktops) won't work well. - The libreboot project recommends a lightweight desktop which does not need video acceleration, such as XFCE or LXDE. -

- The Tamil developer wrote this blog post, which sheds light on the story: http://libv.livejournal.com/27461.html,http://libv.livejournal.com/27461.html. -

- Back to top of page. -

Caution: WiFi requires a non-free blob, a USB dongle can be used instead.

- These laptops have non-removeable (soldered on) WiFi chips, which require non-free firmware in the Linux kernel - in order to work. -

- The libreboot project recommends using an external USB wifi dongle that works - with free software. See #recommended_wifi. -

- There are 2 companies (endorsed by Creative Commons, under their Respects your Freedom - guidelines), that sell USB WiFi dongles guaranteed to work with free software (i.e. linux-libre kernel): -

ThinkPenguin sells them (company based in USA)
Tehnoetic sells them (company based in Europe)

- These wifi dongles use the AR9271 (atheros) chipset, supported by - the free ath9k_htc driver in the Linux kernel. They work in linux-libre too. -

- -

EC firmware is free software!

- It's free software. Google provides the source. Build scripts will be added later, with EC sources - provided in libreboot, and builds of the EC firmware. -

- This is unlike the other current libreboot laptops (Intel based). In practise, you can - (if you do without the video/wifi blobs, and replace ChromeOS with a distribution - that respects your freedom) be more free when using one of these laptops. -

- The libreboot FAQ briefly describes what an EC is: - http://libreboot.org/faq/#firmware-ec -

- -

No microcode!

- Unlike x86 (e.g. Intel/AMD) CPUs, ARM CPUs do not use microcode, not even built in. - On the Intel/AMD based libreboot systems, there is still microcode in the CPU - (not considered problematic by the FSF, provided that it is reasonably trusted - to not be malicious, since it's part of the hardware and read-only), but we - exclude microcode updates (volatile updates which are uploaded at boot time by the boot firmware, - if present), which are proprietary software. -

- On ARM CPUs, the instruction set is implemented in circuitry, without microcode. -

- Back to top of page. -

- -

Depthcharge payload

- These systems do not use the GRUB payload. Instead, they use a payload called depthcharge, - which is common on CrOS devices. This is free software, maintained by Google. -

- -

Flash chip write protection: the screw

- It's next to the flash chip. Unscrew it, and the flash chip is read-write. Screw it back in, and the flash chip is read-only. - It's called the screw. -

- The screw is accessible by removing other screws and gently prying off the upper shell, where the flash chip and the screw - are then directly accessible. User flashing from software is possible, without having to externally re-flash, but the flash chip - is SPI (SOIC-8 form factor) so you can also externally re-flash if you want to. In practise, you only need to externally re-flash - if you brick the laptop; read ../install/bbb_setup.html for an example of how to set up - an SPI programmer. -

- Write protection is useful, because it prevents the firmware from being re-flashed by any malicious software that - might become executed on your GNU+Linux system, as root. In other words, it can prevent a firmware-level evil maid attack. It's - possible to write protect on all current libreboot systems, but CrOS devices make it easy. The screw is such a stupidly - simple idea, which all designs should implement. -

- -

- Copyright © 2015 Leah Rowe <info@minifree.org>
- Permission is granted to copy, distribute and/or modify this document - under the terms of the Creative Commons Attribution-ShareAlike 4.0 International license - or any later version published by Creative Commons; - - A copy of the license can be found at ../cc-by-sa-4.0.txt -

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE - EXTENT POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS - AND AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF - ANY KIND CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, - IMPLIED, STATUTORY, OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, - WARRANTIES OF TITLE, MERCHANTABILITY, FITNESS FOR A PARTICULAR - PURPOSE, NON-INFRINGEMENT, ABSENCE OF LATENT OR OTHER DEFECTS, - ACCURACY, OR THE PRESENCE OR ABSENCE OF ERRORS, WHETHER OR NOT - KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF WARRANTIES ARE NOT - ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT APPLY TO YOU. -

- TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE - TO YOU ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, - NEGLIGENCE) OR OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, - INCIDENTAL, CONSEQUENTIAL, PUNITIVE, EXEMPLARY, OR OTHER LOSSES, - COSTS, EXPENSES, OR DAMAGES ARISING OUT OF THIS PUBLIC LICENSE OR - USE OF THE LICENSED MATERIAL, EVEN IF THE LICENSOR HAS BEEN - ADVISED OF THE POSSIBILITY OF SUCH LOSSES, COSTS, EXPENSES, OR - DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT ALLOWED IN FULL OR - IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. -

- The disclaimer of warranties and limitation of liability provided - above shall be interpreted in a manner that, to the extent - possible, most closely approximates an absolute disclaimer and - waiver of all liability. -

- -

- - - - diff --git a/docs/hcl/c201.md b/docs/hcl/c201.md new file mode 100644 index 00000000..5c92e5b5 --- /dev/null +++ b/docs/hcl/c201.md @@ -0,0 +1,267 @@ +

+ +ASUS Chromebook C201 {#pagetop} +==================== + +This is a Chromebook, using the Rockchip RK3288 SoC. It uses an ARM CPU, +and has free EC firmware (unlike some other laptops). More RK3288-based +laptops will be added to libreboot at a later date. + +Paul Kocialkowski, a [Replicant](http://www.replicant.us/) developer, +ported this laptop to libreboot. Thank you, Paul! + +**More info will be added later, including build/installation +instructions. The board is supported in libreboot, however, and has been +confirmed to work.** + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +[Back to previous index](./). + +

+ +

+ +- [Google\'s intent with CrOS devices](#googlesintent) +- [Considerations about ChromeOS and free operating systems](#os) +- [Caution: Video acceleration requires a non-free blob, software + rendering can be used instead.](#videoblobs) +- [Caution: WiFi requires a non-free blob, a USB dongle can be used + instead.](#wifiblobs) +- [EC firmware is free software!](#ec) +- [No microcode!](#microcode) +- [Depthcharge payload](#depthcharge) +- [Flash chip write protection: the screw](#thescrew) + +

+ +

+ +Google\'s intent with CrOS devices {#googlesintent} +================================== + +CrOS (Chromium OS/Chrome OS) devices, such as Chromebooks, were not +designed with the intent of bringing more freedom to users. However, +they run with a lot of free software at the boot software and embedded +controller levels, since free software gives Google enough flexibility +to optimize various aspects such as boot time and most importantly, to +implement the CrOS security system, that involves various aspects of the +software. Google does hire a lot of Coreboot developers, who are +generally friendly to the free software movement and try to be good +members of the free software community, by contributing code back. + +CrOS devices are designed (from the factory) to actually coax the user +into using proprietary web services (SaaSS) that invade the user\'s +privacy (ChromeOS is literally just the Google Chrome browser when you +boot up, itself proprietary and comes with proprietary add-ons like +flash. It\'s only intended for SaaSS, not actual, real computing). +Google is even a member of the *PRISM* program, as outlined by Edward +Snowden. See notes about ChromeOS below. The libreboot project +recommends that the user replace the default *ChromeOS* with a +distribution that can be used in freedom, without invading the user\'s +privacy. + +We also use a similar argument for the MacBook and the ThinkPads that +are supported in libreboot. Those laptops are supported, in spite of +Apple and Lenovo, companies which are actually *hostile* to the free +software movement. + +[Back to top of page](#pagetop). + +

+ +

+ +Considerations about ChromeOS and free operating systems {#os} +======================================================== + +This laptop comes preinstalled (from the factory) with Google ChromeOS. +This is a GNU+Linux distribution, but it\'s not general purpose and it +comes with proprietary software. It\'s designed for SaaSS. Libreboot +recommends that users of this laptop replace it with another +distribution. + +Use one of the distributions recommend by the libreboot project. See +[../distros/](../distros/) + +Debian GNU+Linux +---------------- + + shows how to +install Debian. + +TODO: instructions for Devuan + +[Back to top of page](#pagetop). + +

+ +

+ +Caution: Video acceleration requires a non-free blob, software rendering can be used instead. {#videoblobs} +============================================================================================= + +The Tamil driver source code for the onboard Mali T GPU is not released. +The developer has so-far withheld it. Until that is released, the only +way to use video (in freedom) on this laptop is to not have video +acceleration, by making sure not to install the relevant blob. Most +tasks can still be performed without video acceleration, without any +noticeable performance penalty. + +In practise, this means that certain things like games, blender and +GNOME shell (or other fancy desktops) won\'t work well. The libreboot +project recommends a lightweight desktop which does not need video +acceleration, such as *XFCE* or *LXDE*. + +The Tamil developer wrote this blog post, which sheds light on the +story: +[http://libv.livejournal.com/27461.html,http://libv.livejournal.com/27461.html](http://libv.livejournal.com/27461.html). + +[Back to top of page](#pagetop). + +

+ +

+ +Caution: WiFi requires a non-free blob, a USB dongle can be used instead. {#wifiblobs} +========================================================================= + +These laptops have non-removeable (soldered on) WiFi chips, which +require non-free firmware in the Linux kernel in order to work. + +The libreboot project recommends using an external USB wifi dongle that +works with free software. See +[\#recommended\_wifi](./#recommended_wifi). + +There are 2 companies (endorsed by Creative Commons, under their +*Respects your Freedom* guidelines), that sell USB WiFi dongles +guaranteed to work with free software (i.e. linux-libre kernel): + +- [ThinkPenguin sells + them](https://www.thinkpenguin.com/gnu-linux/penguin-wireless-n-usb-adapter-gnu-linux-tpe-n150usb) + (company based in USA) +- [Tehnoetic sells + them](https://tehnoetic.com/tehnoetic-wireless-adapter-gnu-linux-libre-tet-n150) + (company based in Europe) + +These wifi dongles use the AR9271 (atheros) chipset, supported by the +free *ath9k\_htc* driver in the Linux kernel. They work in *linux-libre* +too. + +

+ +

+ +EC firmware is free software! {#ec} +============================= + +It\'s free software. Google provides the source. Build scripts will be +added later, with EC sources provided in libreboot, and builds of the EC +firmware. + +This is unlike the other current libreboot laptops (Intel based). In +practise, you can (if you do without the video/wifi blobs, and replace +ChromeOS with a distribution that respects your freedom) be more free +when using one of these laptops. + +The libreboot FAQ briefly describes what an *EC* is: + + +

+ +

+ +No microcode! {#microcode} +============= + +Unlike x86 (e.g. Intel/AMD) CPUs, ARM CPUs do not use microcode, not +even built in. On the Intel/AMD based libreboot systems, there is still +microcode in the CPU (not considered problematic by the FSF, provided +that it is reasonably trusted to not be malicious, since it\'s part of +the hardware and read-only), but we exclude microcode updates (volatile +updates which are uploaded at boot time by the boot firmware, if +present), which are proprietary software. + +On ARM CPUs, the instruction set is implemented in circuitry, without +microcode. + +[Back to top of page](#pagetop). + +

+ +

+ +Depthcharge payload {#depthcharge} +=================== + +These systems do not use the GRUB payload. Instead, they use a payload +called depthcharge, which is common on CrOS devices. This is free +software, maintained by Google. + +

+ +

+ +Flash chip write protection: the screw {#thescrew} +====================================== + +It\'s next to the flash chip. Unscrew it, and the flash chip is +read-write. Screw it back in, and the flash chip is read-only. It\'s +called the screw. + +*The screw* is accessible by removing other screws and gently prying off +the upper shell, where the flash chip and the screw are then directly +accessible. User flashing from software is possible, without having to +externally re-flash, but the flash chip is SPI (SOIC-8 form factor) so +you can also externally re-flash if you want to. In practise, you only +need to externally re-flash if you brick the laptop; read +[../install/bbb\_setup.html](../install/bbb_setup.html) for an example +of how to set up an SPI programmer. + +Write protection is useful, because it prevents the firmware from being +re-flashed by any malicious software that might become executed on your +GNU+Linux system, as root. In other words, it can prevent a +firmware-level *evil maid* attack. It\'s possible to write protect on +all current libreboot systems, but CrOS devices make it easy. The screw +is such a stupidly simple idea, which all designs should implement. + +

+ +

+ +Copyright © 2015 Leah Rowe <info@minifree.org>\ +Permission is granted to copy, distribute and/or modify this document +under the terms of the Creative Commons Attribution-ShareAlike 4.0 +International license or any later version published by Creative +Commons; A copy of the license can be found at +[../cc-by-sa-4.0.txt](../cc-by-sa-4.0.txt) + +Updated versions of the license (when available) can be found at + + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT +POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND +AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND +CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, +OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, +ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE +OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF +WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT +APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU +ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR +OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, +PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES +ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN +IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, +COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT +ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above +shall be interpreted in a manner that, to the extent possible, most +closely approximates an absolute disclaimer and waiver of all liability. + +

diff --git a/docs/hcl/d510mo.html b/docs/hcl/d510mo.html deleted file mode 100644 index f11693cf..00000000 --- a/docs/hcl/d510mo.html +++ /dev/null @@ -1,82 +0,0 @@ - - - - - - - - - Intel D510MO desktop board - - - - -

Intel D510MO desktop board

- -

- This is a desktop board using intel hardware (circa ~2009, ICH7 southbridge, similar performance-wise to the Libreboot X200. It can make for quite a nifty desktop. Powered by libreboot. -

- NOTE: This board has a working framebuffer in Grub, but in GNU+Linux in native resolution the display is unusable due to some raminit issues. - This board can however be used for building a headless server. -

- Flashing instructions can be found at ../install/d510mo.html -

- -

- Copyright © 2016 Leah Rowe <info@minifree.org>
- Permission is granted to copy, distribute and/or modify this document - under the terms of the Creative Commons Attribution-ShareAlike 4.0 International license - or any later version published by Creative Commons; - - A copy of the license can be found at ../cc-by-sa-4.0.txt -

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- - - - diff --git a/docs/hcl/d510mo.md b/docs/hcl/d510mo.md new file mode 100644 index 00000000..522e34e8 --- /dev/null +++ b/docs/hcl/d510mo.md @@ -0,0 +1,55 @@ +

+ +Intel D510MO desktop board {#pagetop} +========================== + +This is a desktop board using intel hardware (circa \~2009, ICH7 +southbridge, similar performance-wise to the Libreboot X200. It can make +for quite a nifty desktop. Powered by libreboot. + +NOTE: This board has a working framebuffer in Grub, but in GNU+Linux in +native resolution the display is unusable due to some raminit issues. +This board can however be used for building a headless server. + +Flashing instructions can be found at +[../install/d510mo.html](../install/d510mo.html) + +

+ +

+ +Copyright © 2016 Leah Rowe <info@minifree.org>\ +Permission is granted to copy, distribute and/or modify this document +under the terms of the Creative Commons Attribution-ShareAlike 4.0 +International license or any later version published by Creative +Commons; A copy of the license can be found at +[../cc-by-sa-4.0.txt](../cc-by-sa-4.0.txt) + +Updated versions of the license (when available) can be found at + + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT +POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND +AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND +CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, +OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, +ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE +OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF +WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT +APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU +ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR +OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, +PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES +ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN +IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, +COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT +ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above +shall be interpreted in a manner that, to the extent possible, most +closely approximates an absolute disclaimer and waiver of all liability. + +

diff --git a/docs/hcl/d945gclf.html b/docs/hcl/d945gclf.html deleted file mode 100644 index f18d7c19..00000000 --- a/docs/hcl/d945gclf.html +++ /dev/null @@ -1,151 +0,0 @@ - - - - - - - - - Intel D945GCLF desktop board - - - - -

Intel D945GCLF desktop board

- -

- Back to previous index -

- -

- If you just want flashing instructions, go to - ../install/d945gclf.html -

- -

- This board is a mini-itx desktop board for 2008. It uses an atom -230, which is a singe core CPU but it is hyperthreaded so it appears to -have 2 thread to the OS. The flash chip is very small, 512KiB, so grub2 -does not fit, which is why libreboot has to use seabios on this target. -Full disk encryption like on other supported targets will not be -possible, so plan accordingly. -

- This board has a 945gc chipset which is the desktop equivalent of -945gm which can be found in the Lenovo x60/t60 or macbook2,1. This -chipset features an ICH7 southbridge. It has 1 DIMM slot that can -accommodate up to 2G of DDR2 RAM. -

- Connectivity-wise it has 1 PCI slot, a 10/100 ethernet port, 4 -usb slot and 4 usb ports, with one internal header and 2 SATA ports. -

- The D945GCLF2 is an upgraded version of this board. The -differences are: 1 more USB header, 10/100/1000 ethernet and a dual core - cpu (also hyperthreaded). Since the board is almost identical (and -coreboot code seem to indicate that it works, since MAX_CPU=4 is set), -it is believed that it should also work but this is untested. -

- Remarks about vendor bios: -

Without coreboot/libreboot this board is utery useless, since the -vendor bios is very bad. It cannot boot from any HDD wether it is -connected to the SATA port or USB. With libreboot it works just fine.
The vendor bios write protects the flash so it requires external -flashing to install libreboot on this device. Once libreboot is flashed -there is no problem to update the firmware internally

- Here is an image of the board:
-
- Here is an image of the D945GCLF2 board:
-
- And SPI SOIC8 flash chip
- -

- -

How to replace thermal paste and fan

- This board comes with very crappy disposable loud fan, that one has no bearings, -which can not be repaired or oiled properly, do not waste your time trying to fix it, just buy one chinese same size fan
- - -
- Make sure that new one has same wiring
-
- This is a new one, with bearing and maintenable
- -
- Now remove the both coolers rotating them a bit, slowly, then clean both silicons -and both coolers (removing cmos battery first is recommended)
-
- Put a little bit of non conductive thermal paste on both silicons (only cpu silicon iis shown on that image)
-
-

Before assembling new fan, some need new longer screws, make sure having these (on the left is original one, too short for new fan)
-
- After that, assemble your new fan into CPU cooler
-
- Finally assemle both coolers on both chips, do not forget put in the CPU fan connector back, and you are done. -

- -

- Copyright © 2016 Arthur Heymans <arthur@aheymans.xyz>
- Copyright © 2016 Vitaly Castaño Solana <vita_cell@hotmail.com>
- Permission is granted to copy, distribute and/or modify this document - under the terms of the Creative Commons Attribution-ShareAlike 4.0 International license - or any later version published by Creative Commons; - - A copy of the license can be found at ../cc-by-sa-4.0.txt -

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- - - - - diff --git a/docs/hcl/d945gclf.md b/docs/hcl/d945gclf.md new file mode 100644 index 00000000..2e19f527 --- /dev/null +++ b/docs/hcl/d945gclf.md @@ -0,0 +1,121 @@ +

+ +Intel D945GCLF desktop board {#pagetop} +============================ + +[Back to previous index](https://libreboot.org/docs/hcl/) + +If you just want flashing instructions, go to +[../install/d945gclf.html](https://libreboot.org/docs/install/d945gclf.html) + +This board is a mini-itx desktop board for 2008. It uses an atom 230, +which is a singe core CPU but it is hyperthreaded so it appears to have +2 thread to the OS. The flash chip is very small, 512KiB, so grub2 does +not fit, which is why libreboot has to use seabios on this target. Full +disk encryption like on other supported targets will not be possible, so +plan accordingly. + +This board has a 945gc chipset which is the desktop equivalent of 945gm +which can be found in the Lenovo x60/t60 or macbook2,1. This chipset +features an ICH7 southbridge. It has 1 DIMM slot that can accommodate up +to 2G of DDR2 RAM. + +Connectivity-wise it has 1 PCI slot, a 10/100 ethernet port, 4 usb slot +and 4 usb ports, with one internal header and 2 SATA ports. + +The D945GCLF2 is an upgraded version of this board. The differences are: +1 more USB header, 10/100/1000 ethernet and a dual core cpu (also +hyperthreaded). Since the board is almost identical (and coreboot code +seem to indicate that it works, since MAX\_CPU=4 is set), it is believed +that it should also work but this is untested. + +Remarks about vendor bios: +-------------------------- + +- Without coreboot/libreboot this board is utery useless, since the + vendor bios is very bad. It cannot boot from any HDD wether it is + connected to the SATA port or USB. With libreboot it works just + fine. +- The vendor bios write protects the flash so it requires external + flashing to install libreboot on this device. Once libreboot is + flashed there is no problem to update the firmware internally + +Here is an image of the board:\ +![](../images/d945gclf/d945gclf.jpg)\ +Here is an image of the D945GCLF2 board:\ +![](../images/d945gclf/20160923_141521.jpg){width="80%" height="80%"}\ +And SPI SOIC8 flash chip\ +![](../images/d945gclf/20160923_141550.jpg){width="50%" height="50%"} + +

+ +

+ +How to replace thermal paste and fan +------------------------------------ + +This board comes with very crappy disposable loud fan, that one has no +bearings, which can not be repaired or oiled properly, do not waste your +time trying to fix it, just buy one chinese same size fan\ +![](../images/d945gclf/20160923_141620.jpg){width="50%" height="50%"} +![](../images/d945gclf/20160923_141614.jpg){width="50%" height="50%"}\ +Make sure that new one has same wiring\ +![](../images/d945gclf/20160923_142618.jpg){width="50%" height="50%"}\ +This is a new one, with bearing and maintenable\ +![](../images/d945gclf/20160923_141738.jpg){width="50%" height="50%"} +![](../images/d945gclf/20160923_141814.jpg){width="50%" height="50%"}\ +Now remove the both coolers rotating them a bit, slowly, then clean both +silicons and both coolers (removing cmos battery first is recommended)\ +![](../images/d945gclf/20160923_141601.jpg){width="50%" height="50%"}\ +Put a little bit of non conductive thermal paste on both silicons (only +cpu silicon iis shown on that image)\ +![](../images/d945gclf/20160923_142031.jpg){width="50%" height="50%"}\ + +Before assembling new fan, some need new longer screws, make sure having +these (on the left is original one, too short for new fan)\ +![](../images/d945gclf/20160923_141659.jpg){width="50%" height="50%"}\ +After that, assemble your new fan into CPU cooler\ +![](../images/d945gclf/20160923_141635.jpg){width="50%" height="50%"}\ +Finally assemle both coolers on both chips, do not forget put in the CPU +fan connector back, and you are done. + +

+ +

+ +Copyright © 2016 Arthur Heymans <arthur@aheymans.xyz>\ +Copyright © 2016 Vitaly Castaño Solana <vita\_cell@hotmail.com>\ +Permission is granted to copy, distribute and/or modify this document +under the terms of the Creative Commons Attribution-ShareAlike 4.0 +International license or any later version published by Creative +Commons; A copy of the license can be found at +[../cc-by-sa-4.0.txt](https://libreboot.org/docs/cc-by-sa-4.0.txt) + +Updated versions of the license (when available) can be found at + + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT +POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND +AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND +CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, +OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, +ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE +OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF +WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT +APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU +ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR +OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, +PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES +ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN +IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, +COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT +ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above +shall be interpreted in a manner that, to the extent possible, most +closely approximates an absolute disclaimer and waiver of all liability. + +

diff --git a/docs/hcl/ga-g41m-es2l.html b/docs/hcl/ga-g41m-es2l.html deleted file mode 100644 index da009d67..00000000 --- a/docs/hcl/ga-g41m-es2l.html +++ /dev/null @@ -1,86 +0,0 @@ - - - - - - - - - Gigabyte GA-G41M-ES2L desktop board - - - - -

Gigabyte GA-G41M-ES2L desktop board

- -

- This is a desktop board using intel hardware (circa ~2009, ICH7 southbridge, similar performance-wise to the Libreboot X200. It can make for quite a nifty desktop. Powered by libreboot. -

- IDE on the board is untested, but it might be possible to use a SATA HDD using an IDE SATA adapter. The SATA ports do work. -

- You need to set a custom MAC address in GNU+Linux for the NIC to work. In /etc/network/interfaces on debian-based systems like Debian or Devuan, - this would be in the entry for your NIC:
- hwaddress ether macaddressgoeshere -

- Flashing instructions can be found at ../install/#flashrom -

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- - - - diff --git a/docs/hcl/ga-g41m-es2l.md b/docs/hcl/ga-g41m-es2l.md new file mode 100644 index 00000000..98912994 --- /dev/null +++ b/docs/hcl/ga-g41m-es2l.md @@ -0,0 +1,59 @@ +

+ +Gigabyte GA-G41M-ES2L desktop board {#pagetop} +=================================== + +This is a desktop board using intel hardware (circa \~2009, ICH7 +southbridge, similar performance-wise to the Libreboot X200. It can make +for quite a nifty desktop. Powered by libreboot. + +IDE on the board is untested, but it might be possible to use a SATA HDD +using an IDE SATA adapter. The SATA ports do work. + +You need to set a custom MAC address in GNU+Linux for the NIC to work. +In /etc/network/interfaces on debian-based systems like Debian or +Devuan, this would be in the entry for your NIC:\ +hwaddress ether macaddressgoeshere + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +

+ +

diff --git a/docs/hcl/gm45_remove_me.html b/docs/hcl/gm45_remove_me.html deleted file mode 100644 index 8e66ef7d..00000000 --- a/docs/hcl/gm45_remove_me.html +++ /dev/null @@ -1,693 +0,0 @@ - - - - - - - - - GM45 chipsets: remove the ME (manageability engine) - - - - -

- -

GM45 chipsets: remove the ME (manageability engine)

- This sections relates to disabling and removing the ME (Intel Management Engine) on - GM45. This was originally done on the ThinkPad X200, and later adapted for the ThinkPad R400/T400/T500. It can - in principle be done on any GM45 or GS45 system. -

- The ME is a blob that typically must be left inside the flash chip (in the ME region, as outlined - by the default descriptor). On GM45, it is possible to remove it without any ill effects. All - other parts of coreboot on GM45 systems (provided GMA MHD4500 / Intel graphics) can be blob-free, - so removing the ME was the last obstacle to - make GM45 a feasible target in libreboot (the systems can also work without the microcode blobs). -

- The ME is removed and disabled in libreboot by modifying the descriptor. More info about - this can be found in the ich9deblob/ich9gen source code in resources/utilities/ich9deblob/ - in libreboot, or more generally on this page. -

- More information about the ME can be found at - http://www.coreboot.org/Intel_Management_Engine - and http://me.bios.io/Main_Page. -

- Another project recently found: - http://io.smashthestack.org/me/ -

- Back to previous index. -

- -

ICH9 gen utility

- -

- It is no longer necessary to use ich9deblob to generate - a deblobbed descriptor+gbe image for GM45 targets. ich9gen is a small utility within - ich9deblob that can generate them from scratch, without a factory.bin dump. -

- -

- ich9gen executables can be found under ./ich9deblob/ statically compiled in - libreboot_util. If you are using src or git, build ich9gen from source with:
- $ ./oldbuild module ich9deblob
- The executable will appear under resources/utilities/ich9deblob/ -

- -

- Run:
- $ ./ich9gen -

- -

- Running ich9gen this way (without any arguments) generates - a default descriptor+gbe image with a generic MAC address. - You probably don't want to use the generic one; the ROM images - in libreboot contain a descriptor+gbe image by default (already - inserted) just to prevent or mitigate the risk of bricking - your laptop, but with the generic MAC address (the libreboot - project does not know what your real MAC address is). -

- -

- You can find out your MAC address from ip addr or ifconfig in GNU+Linux. - Alternatively, if you are running libreboot already (with the correct MAC address in your - ROM), dump it (flashrom -r) and read the first 6 bytes from position 0x1000 (or 0x2000) in a hex editor - (or, rename it to factory.rom and run it in ich9deblob: in the newly created mkgbe.c - will be the individual bytes of your MAC address). If you are currently running the stock firmware - and haven't installed libreboot yet, you can also run that through ich9deblob to get the mac address. -

- -

- An even simpler way to get the MAC address would be to read what's on the little sticker on - the bottom/base of the laptop. -

- -

- On GM45 laptops that use flash descriptors, the MAC address - or the onboard ethernet chipset is flashed (inside the ROM image). - You should generate a descriptor+gbe image with your own MAC address - inside (with the Gbe checksum updated to match). Run:
- $ ./ich9gen --macaddress XX:XX:XX:XX:XX:XX
- (replace the XX chars with the hexadecimal chars in the MAC address that you want) -

- -

- Two new files will be created: -

ich9fdgbe_4m.bin: this is for GM45 laptops with the 4MB flash chip.
ich9fdgbe_8m.bin: this is for GM45 laptops with the 8MB flash chip.
ich9fdgbe_16m.bin: this is for GM45 laptops with the 16MB flash chip.

- -

- Assuming that your libreboot image is named libreboot.rom, copy - the file to where libreboot.rom is located - and then insert the descriptor+gbe file into the ROM image.
- For 16MiB flash chips:
- $ dd if=ich9fdgbe_16m.bin of=libreboot.rom bs=1 count=12k conv=notrunc
- For 8MiB flash chips:
- $ dd if=ich9fdgbe_8m.bin of=libreboot.rom bs=1 count=12k conv=notrunc
- For 4MiB flash chips:
- $ dd if=ich9fdgbe_4m.bin of=libreboot.rom bs=1 count=12k conv=notrunc
-

- -

- Your libreboot.rom image is now ready to be flashed on the system. Refer back to - ../install/#flashrom - for how to flash it. -

- -

- Write-protecting the flash chip -

- Look in resources/utilities/ich9deblob/src/descriptor/descriptor.c - for the following lines in the descriptorHostRegionsUnlocked function: -

-   descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x1;
-   descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x1;
-   descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x1;
-   descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x1;
-   descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x1;
-

- Also look in resources/utilities/ich9deblob/src/ich9gen/mkdescriptor.c - for the following lines: -

-    descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */
-    descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */
-    descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */
-    descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */
-    descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */
-

- -

- NOTE: When you write-protect the flash chip, re-flashing is no longer possible unless you - use dedicated external equipment, which also means disassembling the laptop. The same equipment - can also be used to remove the write-protection later on, if you choose to do so. *Only* write-protect - the chip if you have the right equipment for external flashing later on; for example, see - ../install/bbb_setup.html. -

- -

- Change them all to 0x0, then re-compile ich9gen. After you have done that, - follow the notes in #ich9gen to generate a new - descriptor+gbe image and insert that into your ROM image, then flash it. - The next time you boot, the flash chip will be read-only in software - (hardware re-flashing will still work, which you will need for re-flashing - the chip after write-protecting it, to clear the write protection or - to flash yet another ROM image with write protection set in the descriptor). -

- Flashrom will tell you that you can still forcefully re-flash, using -p internal:ich_spi_force=yes but - this won't actually work; it'll just brick your laptop. -

- For external flashing guides, refer to ../install/. -

- -

ICH9 deblob utility

- -

- This is no longer strictly necessary. Libreboot ROM images for GM45 systems now - contain the 12KiB descriptor+gbe generated from ich9gen, by default. -

- -

- This was the tool originally used to disable the ME on X200 (later adapted for other systems that use the - GM45 chipset). ich9gen now supersedes it; - ich9gen is better because it does not rely on dumping the factory.rom image (whereas, ich9deblob does). -

- -

- This is what you will use to generate the deblobbed descriptor+gbe regions for your libreboot ROM image. -

- If you are working with libreboot_src (or git), you can find the source under resources/utilities/ich9deblob/ - and will already be compiled if you ran ./oldbuild module all or ./oldbuild module ich9deblob from the main directory (./), - otherwise you can build it like so:
- $ ./oldbuild module ich9deblob
- An executable file named ich9deblob will now appear under resources/utilities/ich9deblob/ -

- If you are working with libreboot_util release archive, you can find the utility included, statically compiled - (for i686 and x86_64 on GNU+Linux) under ./ich9deblob/. -

- -

- Place the factory.rom from your system - (can be obtained using the external flashing guides for GM45 targets linked ../install/) in - the directory where you have your ich9deblob executable, then run the tool:
- $ ./ich9deblob -

- A 12kiB file named deblobbed_descriptor.bin will now appear. Keep this and the factory.rom stored in a safe location! - The first 4KiB contains the descriptor data region for your system, and the next 8KiB contains the gbe region (config data for your - gigabit NIC). These 2 regions could actually be separate files, but they are joined into 1 file in this case. -

- A 4KiB file named deblobbed_4kdescriptor.bin will alternatively appear, if no GbE region was detected inside the ROM image. - This is usually the case, when a discrete NIC is used (eg Broadcom) instead of Intel. Only the Intel NICs need a GbE region in - the flash chip. -

- -

- Assuming that your libreboot image is named libreboot.rom, copy - the deblobbed_descriptor.bin file to where libreboot.rom is located - and then run:
- $ dd if=deblobbed_descriptor.bin of=libreboot.rom bs=1 count=12k conv=notrunc -

- Alternatively, if you got a the deblobbed_4kdescriptor.bin file (no GbE defined), - do this: - $ dd if=deblobbed_4kdescriptor.bin of=libreboot.rom bs=1 count=4k conv=notrunc -

- -

- The utility will also generate 4 additional files: -

mkdescriptor.c
mkdescriptor.h
mkgbe.c
mkgbe.h

- These are C source files that can re-generate the very same Gbe and Descriptor structs - (from ich9deblob/ich9gen). To use these, place them in src/ich9gen/ in ich9deblob, then re-build. - The newly built ich9gen executable will be able to re-create the very same 12KiB file from scratch, - based on the C structs, this time without the need for a factory.rom dump! -

- -

- You should now have a libreboot.rom image containing the correct 4K descriptor and 8K gbe regions, which - will then be safe to flash. Refer back to ../install/#flashrom - for how to flash it. -

- -

demefactory utility

- -

- This takes a factory.rom dump and disables the ME/TPM, but leaves the region intact. - It also sets all regions read-write. -

- -

- The ME interferes with flash read/write in flashrom, and the default descriptor - locks some regions. The idea is that doing this will remove all of those restrictions. -

- -

- Simply run (with factory.rom in the same directory):
- $ ./demefactory -

- -

- It will generate a 4KiB descriptor file (only the descriptor, no GbE). Insert that into - a factory.rom image (NOTE: do this on a copy of it. Keep the original factory.rom stored - safely somewhere):
- $ dd if=demefactory_4kdescriptor.bin of=factory_nome.rom bs=1 count=4k conv=notrunc -

- -

- TODO: test this.
- TODO: lenovobios (GM45 thinkpads) still write-protects parts of the flash. Modify the assembly code - inside. - Note: the factory.rom (BIOS region) from lenovobios is in a compressed format, which you have to extract. - bios_extract upstream won't work, but the following was said in #coreboot on freenode IRC: -

-<roxfan> vimuser: try bios_extract with ffv patch http://patchwork.coreboot.org/patch/3444/
-<roxfan> or https://github.com/coreboot/bios_extract/blob/master/phoenix_extract.py
-<roxfan> what are you looking for specifically, btw?
-
-0x74: 0x9fff03e0 PR0: Warning: 0x003e0000-0x01ffffff is read-only.
-0x84: 0x81ff81f8 PR4: Warning: 0x001f8000-0x001fffff is locked.
-

- -

- Use-case: a factory.rom image modified in this way would theoretically have no - flash protections whatsoever, making it easy to quickly switch between factory/libreboot - in software, without ever having to disassemble and re-flash externally unless you brick - the device. -

- -

- demefactory is part of the ich9deblob src, found at resources/utilities/ich9deblob/ -

- -

- The sections below are adapted from (mostly) IRC logs related to early development getting the ME removed on GM45. - They are useful for background information. This could not have been done without sgsit's help. -

- -

Early notes

- -

- http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-10-family-datasheet.pdf - page 230 mentions about descriptor and non-descriptor mode (which wipes out gbe and ME/AMT). -
- ~~See reference to HDA_SDO (disable descriptor security)~~ - strap connected GPIO33 pin is it on ICH9-M (X200). HDA_SDO applies to later chipsets (series 6 or higher). - Disabling descriptor security also disables the ethernet according to sgsit. sgsit's method - involves use of 'soft straps' (see IRC logs below) instead of disabling the descriptor. -
- and the location of GPIO33 on the x200s: (was an external link. Putting it here instead) - images/x200/gpio33_location.jpg - - it's above the number 7 on TP37 (which is above the big intel chip at the bottom) -
- The ME datasheet may not be for the mobile chipsets but it doesn't vary that much. - This one gives some detail and covers QM67 which is what the X201 uses: - http://www.intel.co.uk/content/dam/www/public/us/en/documents/datasheets/6-chipset-c200-chipset-datasheet.pdf -

- -

Flash chips

- -

- Schematics for X200 laptop: http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006075.pdf - ~~- Page 20 and page 9 refer to SDA_HDO or SDA_HDOUT~~ only on series 6 or higher chipsets. ICH9-M (X200) does it with a strap connected to GPIO33 pin (see IRC notes below)
- - According to page 29, the X200 can have any of the following flash chips: -
- ATMEL AT26DF321-SU 72.26321.A01 - this is a 32Mb (4MiB) chip
- MXIC (Macronix?) MX25L3205DM2I-12G 72.25325.A01 - another 32Mb (4MiB) chip
- MXIC (Macronix?) MX25L6405DMI-12G 41R0820AA - this is a 64Mb (8MiB) chip
- Winbond W25X64VSFIG 41R0820BA - another 64Mb (8MiB) chip
- sgsit says that the X200s with the 64Mb flash chips are (probably) the ones with AMT (alongside the ME), whereas - the 32Mb chips contain only the ME. -
- Schematics for X200s laptop: http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006104.pdf. -

- -

Early development notes

- -

-
-Start (hex)	End (hex)	Length (hex)	Area Name
------------	---------	------------	---------
-00000000	003FFFFF	00400000	Flash Image
-
-00000000	00000FFF	00001000	Descriptor Region
-00000004	0000000F	0000000C		Descriptor Map
-00000010	0000001B	0000000C		Component Section
-00000040	0000004F	00000010		Region Section
-00000060	0000006B	0000000C		Master Access Section
-00000060	00000063	00000004			CPU/BIOS
-00000064	00000067	00000004			Manageability Engine (ME)
-00000068	0000006B	00000004			GbE LAN
-00000100	00000103	00000004		ICH Strap 0
-00000104	00000107	00000004		ICH Strap 1
-00000200	00000203	00000004		MCH Strap 0
-00000EFC	00000EFF	00000004		Descriptor Map 2
-00000ED0	00000EF7	00000028		ME VSCC Table
-00000ED0	00000ED7	00000008			Flash device 1
-00000ED8	00000EDF	00000008			Flash device 2
-00000EE0	00000EE7	00000008			Flash device 3
-00000EE8	00000EEF	00000008			Flash device 4
-00000EF0	00000EF7	00000008			Flash device 5
-00000F00	00000FFF	00000100		OEM Section
-00001000	001F5FFF	001F5000	ME Region
-001F6000	001F7FFF	00002000	GbE Region
-001F8000	001FFFFF	00008000	PDR Region
-00200000	003FFFFF	00200000	BIOS Region
-
-Start (hex)	End (hex)	Length (hex)	Area Name
------------	---------	------------	---------
-00000000	003FFFFF	00400000	Flash Image
-
-00000000	00000FFF	00001000	Descriptor Region
-00000004	0000000F	0000000C		Descriptor Map
-00000010	0000001B	0000000C		Component Section
-00000040	0000004F	00000010		Region Section
-00000060	0000006B	0000000C		Master Access Section
-00000060	00000063	00000004			CPU/BIOS
-00000064	00000067	00000004			Manageability Engine (ME)
-00000068	0000006B	00000004			GbE LAN
-00000100	00000103	00000004		ICH Strap 0
-00000104	00000107	00000004		ICH Strap 1
-00000200	00000203	00000004		MCH Strap 0
-00000ED0	00000EF7	00000028		ME VSCC Table
-00000ED0	00000ED7	00000008			Flash device 1
-00000ED8	00000EDF	00000008			Flash device 2
-00000EE0	00000EE7	00000008			Flash device 3
-00000EE8	00000EEF	00000008			Flash device 4
-00000EF0	00000EF7	00000008			Flash device 5
-00000EFC	00000EFF	00000004		Descriptor Map 2
-00000F00	00000FFF	00000100		OEM Section
-00001000	00002FFF	00002000	GbE Region
-00003000	00202FFF	00200000	BIOS Region
-
-Build Settings
---------------
-Flash Erase Size = 0x1000
-
-
-

- -

- It's a utility called 'Flash Image Tool' for ME 4.x that was used for this. You drag a complete - image into in and the utility decomposes the various components, allowing you to set soft straps. -

- This tool is proprietary, for Windows only, but was used to deblob the X200. End justified means, and - the utility is no longer needed since the ich9deblob utility (documented on this page) can now be - used to create deblobbed descriptors. -

- -

- GBE (gigabit ethernet) region in SPI flash -

- -

- Of the 8K, about 95% is 0xFF. - The data is the gbe region is fully documented in this public datasheet: - http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf -

- -

- The only actual content found was: -

- -

-
-00  1F  1F  1F  1F  1F  00  08  FF  FF  83  10  FF  FF  FF  FF  
-08  10  FF  FF  C3  10  EE  20  AA  17  F5  10  86  80  00  00  
-01  0D  00  00  00  00  05  06  20  30  00  0A  00  00  8B  8D  
-02  06  40  2B  43  00  00  00  F5  10  AD  BA  F5  10  BF  10  
-AD  BA  CB  10  AD  BA  AD  BA  00  00  00  00  00  00  00  00  
-00  00  00  00  00  00  00  00  00  00  00  00  00  00  00  00  
-00  01  00  40  28  12  07  40  FF  FF  FF  FF  FF  FF  FF  FF  
-FF  FF  FF  FF  FF  FF  FF  FF  FF  FF  FF  FF  FF  FF  D9  F0  
-20  60  1F  00  02  00  13  00  00  80  1D  00  FF  00  16  00  
-DD  CC  18  00  11  20  17  00  DD  DD  18  00  12  20  17  00  
-00  80  1D  00  00  00  1F  
-
-

- -

- The first part is the MAC address set to all 0x1F. It's repeated haly way through - the 8K area, and the rest is all 0xFF. This is all documented in the datasheet. -

- -

- The GBe region starts at 0x20A000 bytes from the *end* of a factory image and is 0x2000 bytes long. - In libreboot (deblobbed) the descriptor is set to put gbe directly after the initial 4K flash descriptor. - So the first 4K of the ROM is the descriptor, and then the next 8K is the gbe region. -

- -

GBE region: change MAC address

- -

- According to the datasheet, it's supposed to add up to 0xBABA but can actually be others on the X200. - https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums -

- "One of those engineers loves classic rock music, so they selected 0xBABA" -

In honour of the song Baba O'Reilly by The Who apparently. We're not making this stuff up...

- -

- 0x3ABA, 0x34BA, 0x40BA and more have been observed in the main Gbe regions on the X200 factory.rom dumps. - The checksums of the backup regions match BABA, however. -

- -

- By default, the X200 (as shipped by Lenovo) actually has an invalid main gbe checksum. The backup gbe region is correct, - and is what these systems default to. Basically, you should do what you need on the *backup* gbe region, and - then correct the main one by copying from the backup. -

- -

- Look at resources/utilities/ich9deblob/ich9deblob.c. -

Add the first 0x3F 16bit numbers (unsigned) of the GBe descriptor together (this includes the checksum value) - and that has to add up to 0xBABA. In other words, the checksum is 0xBABA minus the total of the first - 0x3E 16bit numbers (unsigned), ignoring any overflow.

- -

Flash descriptor region

- -

- http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datasheet.pdf - from page 850 onwards. This explains everything that is in the flash descriptor, which can be used to understand what libreboot - is doing about modifying it. -

- -

- How to deblob: -

patch the number of regions present in the descriptor from 5 - 3
originally descriptor + bios + me + gbe + platform
modified = descriptor + bios + gbe
the next stage is to patch the part of the descriptor which defines the start and end point of each section
then cut out the gbe region and insert it just after the region
all this can be substantiated with public docs (ICH9 datasheet)
the final part is flipping 2 bits. Halting the ME via 1 MCH soft strap and 1 ICH soft strap
the part of the descriptor described there gives the base address and length of each region (bits 12:24 of each address)
to disable a region, you set the base address to 0xFFF and the length to 0
and you change the number of regions from 4 (zero based) to 2

- -

- There's an interesting parameter called 'ME Alternate disable', which allows the ME to only handle hardware errata in the southbridge, - but disables any other functionality. This is similar to the 'ignition' in the 5 series and higher but using the standard firmware - instead of a small 128K version. Useless for libreboot, though. -

- -

- To deblob GM45, you chop out the platform and ME regions and correct the addresses in flReg1-4. - Then you set meDisable to 1 in ICHSTRAP0 and MCHSTRAP0. -

- -

How to patch the descriptor from the factory.rom dump

map the first 4k into the struct (minus the gbe region)
set NR in FLMAP0 to 2 (from 4)
adjust BASE and LIMIT in flReg1,2,3,4 to reflect the new location of each region (or remove them in the case of Platform and ME)
set meDisable to 1/true in ICHSTRAP0 and MCHSTRAP0
extract the 8k GBe region and append that to the end of the 4k descriptor
output the 12k concatenated chunk
Then it can be dd'd into the first 12K part of a coreboot image.
the GBe region always starts 0x20A000 bytes from the end of the ROM

- -

- This means that libreboot's descriptor region will simply define the following regions: -

descriptor (4K)
gbe (8K)
bios (rest of flash chip. CBFS also set to occupy this whole size)

- -

- The data in the descriptor region is little endian, and it represents bits 24:12 of the address - (bits 12-24, written this way since bit 24 is nearer to left than bit 12 in the binary representation). -

- So, x << 12 = address -

- If it's in descriptor mode, then the first 4 bytes will be 5A A5 F0 0F. -

- -

- - -

- -

platform data partition in boot flash (factory.rom / lenovo bios)

- -

- Basically useless for libreboot, since it appears to be a blob. - Removing it didn't cause any issues in libreboot. -

- This is a 32K region from the factory image. It could be data - (non-functional) that the original Lenovo BIOS used, but we don't know. -

- -

- It has only a 448 byte fragment different from 0x00 or 0xFF. -

- -

- Copyright © 2014, 2015 Leah Rowe <info@minifree.org>
- Permission is granted to copy, distribute and/or modify this document - under the terms of the Creative Commons Attribution-ShareAlike 4.0 International license - or any later version published by Creative Commons; - - A copy of the license can be found at ../cc-by-sa-4.0.txt -

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- - - diff --git a/docs/hcl/gm45_remove_me.md b/docs/hcl/gm45_remove_me.md new file mode 100644 index 00000000..92ef4347 --- /dev/null +++ b/docs/hcl/gm45_remove_me.md @@ -0,0 +1,604 @@ +

+ +GM45 chipsets: remove the ME (manageability engine) {#pagetop} +=================================================== + +This sections relates to disabling and removing the ME (Intel +**M**anagement **E**ngine) on GM45. This was originally done on the +ThinkPad X200, and later adapted for the ThinkPad R400/T400/T500. It can +in principle be done on any GM45 or GS45 system. + +The ME is a blob that typically must be left inside the flash chip (in +the ME region, as outlined by the default descriptor). On GM45, it is +possible to remove it without any ill effects. All other parts of +coreboot on GM45 systems (provided GMA MHD4500 / Intel graphics) can be +blob-free, so removing the ME was the last obstacle to make GM45 a +feasible target in libreboot (the systems can also work without the +microcode blobs). + +The ME is removed and disabled in libreboot by modifying the descriptor. +More info about this can be found in the ich9deblob/ich9gen source code +in resources/utilities/ich9deblob/ in libreboot, or more generally on +this page. + +More information about the ME can be found at + and +. + +Another project recently found: + +[Back to previous index](./). + +

+ +

+ +ICH9 gen utility {#ich9gen} +================ + +It is no longer necessary to use [ich9deblob](#ich9deblob) to generate a +deblobbed descriptor+gbe image for GM45 targets. ich9gen is a small +utility within ich9deblob that can generate them from scratch, without a +factory.bin dump. + +ich9gen executables can be found under ./ich9deblob/ statically compiled +in libreboot\_util. If you are using src or git, build ich9gen from +source with:\ +\$ **./oldbuild module ich9deblob**\ +The executable will appear under resources/utilities/ich9deblob/ + +Run:\ +\$ **./ich9gen** + +Running ich9gen this way (without any arguments) generates a default +descriptor+gbe image with a generic MAC address. You probably don\'t +want to use the generic one; the ROM images in libreboot contain a +descriptor+gbe image by default (already inserted) just to prevent or +mitigate the risk of bricking your laptop, but with the generic MAC +address (the libreboot project does not know what your real MAC address +is). + +You can find out your MAC address from **ip addr** or **ifconfig** in +GNU+Linux. Alternatively, if you are running libreboot already (with the +correct MAC address in your ROM), dump it (flashrom -r) and read the +first 6 bytes from position 0x1000 (or 0x2000) in a hex editor (or, +rename it to factory.rom and run it in ich9deblob: in the newly created +mkgbe.c will be the individual bytes of your MAC address). If you are +currently running the stock firmware and haven\'t installed libreboot +yet, you can also run that through ich9deblob to get the mac address. + +An even simpler way to get the MAC address would be to read what\'s on +the little sticker on the bottom/base of the laptop. + +On GM45 laptops that use flash descriptors, the MAC address or the +onboard ethernet chipset is flashed (inside the ROM image). You should +generate a descriptor+gbe image with your own MAC address inside (with +the Gbe checksum updated to match). Run:\ +\$ **./ich9gen \--macaddress XX:XX:XX:XX:XX:XX**\ +(replace the XX chars with the hexadecimal chars in the MAC address that +you want) + +Two new files will be created: + +- **ich9fdgbe\_4m.bin**: this is for GM45 laptops with the 4MB flash + chip. +- **ich9fdgbe\_8m.bin**: this is for GM45 laptops with the 8MB flash + chip. +- **ich9fdgbe\_16m.bin**: this is for GM45 laptops with the 16MB flash + chip. + +Assuming that your libreboot image is named **libreboot.rom**, copy the +file to where **libreboot.rom** is located and then insert the +descriptor+gbe file into the ROM image.\ +For 16MiB flash chips:\ +\$ **dd if=ich9fdgbe\_16m.bin of=libreboot.rom bs=1 count=12k +conv=notrunc**\ +For 8MiB flash chips:\ +\$ **dd if=ich9fdgbe\_8m.bin of=libreboot.rom bs=1 count=12k +conv=notrunc**\ +For 4MiB flash chips:\ +\$ **dd if=ich9fdgbe\_4m.bin of=libreboot.rom bs=1 count=12k +conv=notrunc**\ + +Your libreboot.rom image is now ready to be flashed on the system. Refer +back to [../install/\#flashrom](../install/#flashrom) for how to flash +it. + +Write-protecting the flash chip +------------------------------- + +Look in *resources/utilities/ich9deblob/src/descriptor/descriptor.c* for +the following lines in the *descriptorHostRegionsUnlocked* function: + + descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x1; + +Also look in *resources/utilities/ich9deblob/src/ich9gen/mkdescriptor.c* +for the following lines: + + descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + +NOTE: When you write-protect the flash chip, re-flashing is no longer +possible unless you use dedicated external equipment, which also means +disassembling the laptop. The same equipment can also be used to remove +the write-protection later on, if you choose to do so. \*Only\* +write-protect the chip if you have the right equipment for external +flashing later on; for example, see +[../install/bbb\_setup.html](../install/bbb_setup.html). + +Change them all to 0x0, then re-compile ich9gen. After you have done +that, follow the notes in [\#ich9gen](#ich9gen) to generate a new +descriptor+gbe image and insert that into your ROM image, then flash it. +The next time you boot, the flash chip will be read-only in software +(hardware re-flashing will still work, which you will need for +re-flashing the chip after write-protecting it, to clear the write +protection or to flash yet another ROM image with write protection set +in the descriptor). + +Flashrom will tell you that you can still forcefully re-flash, using *-p +internal:ich\_spi\_force=yes* but this won\'t actually work; it\'ll just +brick your laptop. + +For external flashing guides, refer to [../install/](../install/). + +

+ +

+ +ICH9 deblob utility {#ich9deblob} +=================== + +**This is no longer strictly necessary. Libreboot ROM images for GM45 +systems now contain the 12KiB descriptor+gbe generated from ich9gen, by +default.** + +This was the tool originally used to disable the ME on X200 (later +adapted for other systems that use the GM45 chipset). +[ich9gen](#ich9gen) now supersedes it; ich9gen is better because it does +not rely on dumping the factory.rom image (whereas, ich9deblob does). + +This is what you will use to generate the deblobbed descriptor+gbe +regions for your libreboot ROM image. + +If you are working with libreboot\_src (or git), you can find the source +under resources/utilities/ich9deblob/ and will already be compiled if +you ran **./oldbuild module all** or **./oldbuild module ich9deblob** +from the main directory (./), otherwise you can build it like so:\ +\$ **./oldbuild module ich9deblob**\ +An executable file named **ich9deblob** will now appear under +resources/utilities/ich9deblob/ + +If you are working with libreboot\_util release archive, you can find +the utility included, statically compiled (for i686 and x86\_64 on +GNU+Linux) under ./ich9deblob/. + +Place the factory.rom from your system (can be obtained using the +external flashing guides for GM45 targets linked +[../install/](../install/)) in the directory where you have your +ich9deblob executable, then run the tool:\ +\$ **./ich9deblob** + +A 12kiB file named **deblobbed\_descriptor.bin** will now appear. **Keep +this and the factory.rom stored in a safe location!** The first 4KiB +contains the descriptor data region for your system, and the next 8KiB +contains the gbe region (config data for your gigabit NIC). These 2 +regions could actually be separate files, but they are joined into 1 +file in this case. + +A 4KiB file named **deblobbed\_4kdescriptor.bin** will alternatively +appear, if no GbE region was detected inside the ROM image. This is +usually the case, when a discrete NIC is used (eg Broadcom) instead of +Intel. Only the Intel NICs need a GbE region in the flash chip. + +Assuming that your libreboot image is named **libreboot.rom**, copy the +**deblobbed\_descriptor.bin** file to where **libreboot.rom** is located +and then run:\ +\$ **dd if=deblobbed\_descriptor.bin of=libreboot.rom bs=1 count=12k +conv=notrunc** + +Alternatively, if you got a the **deblobbed\_4kdescriptor.bin** file (no +GbE defined), do this: \$ **dd if=deblobbed\_4kdescriptor.bin +of=libreboot.rom bs=1 count=4k conv=notrunc** + +The utility will also generate 4 additional files: + +- mkdescriptor.c +- mkdescriptor.h +- mkgbe.c +- mkgbe.h + +These are C source files that can re-generate the very same Gbe and +Descriptor structs (from ich9deblob/ich9gen). To use these, place them +in src/ich9gen/ in ich9deblob, then re-build. The newly built +**ich9gen** executable will be able to re-create the very same 12KiB +file from scratch, based on the C structs, this time **without** the +need for a factory.rom dump! + +You should now have a **libreboot.rom** image containing the correct 4K +descriptor and 8K gbe regions, which will then be safe to flash. Refer +back to [../install/\#flashrom](../install/#flashrom) for how to flash +it. + +

+ +

+ +demefactory utility {#demefactory} +=================== + +This takes a factory.rom dump and disables the ME/TPM, but leaves the +region intact. It also sets all regions read-write. + +The ME interferes with flash read/write in flashrom, and the default +descriptor locks some regions. The idea is that doing this will remove +all of those restrictions. + +Simply run (with factory.rom in the same directory):\ +\$ **./demefactory** + +It will generate a 4KiB descriptor file (only the descriptor, no GbE). +Insert that into a factory.rom image (NOTE: do this on a copy of it. +Keep the original factory.rom stored safely somewhere):\ +\$ **dd if=demefactory\_4kdescriptor.bin of=factory\_nome.rom bs=1 +count=4k conv=notrunc** + +TODO: test this.\ +TODO: lenovobios (GM45 thinkpads) still write-protects parts of the +flash. Modify the assembly code inside. Note: the factory.rom (BIOS +region) from lenovobios is in a compressed format, which you have to +extract. bios\_extract upstream won\'t work, but the following was said +in \#coreboot on freenode IRC: + + vimuser: try bios_extract with ffv patch http://patchwork.coreboot.org/patch/3444/ + or https://github.com/coreboot/bios_extract/blob/master/phoenix_extract.py + what are you looking for specifically, btw? + + 0x74: 0x9fff03e0 PR0: Warning: 0x003e0000-0x01ffffff is read-only. + 0x84: 0x81ff81f8 PR4: Warning: 0x001f8000-0x001fffff is locked. + +Use-case: a factory.rom image modified in this way would theoretically +have no flash protections whatsoever, making it easy to quickly switch +between factory/libreboot in software, without ever having to +disassemble and re-flash externally unless you brick the device. + +demefactory is part of the ich9deblob src, found at +*resources/utilities/ich9deblob/* + +

+ +

+ +The sections below are adapted from (mostly) IRC logs related to early +development getting the ME removed on GM45. They are useful for +background information. This could not have been done without sgsit\'s +help. + +

+ +Early notes {#early_notes} +----------- + +- + page 230 mentions about descriptor and non-descriptor mode (which + wipes out gbe and ME/AMT). +- ~~**See reference to HDA\_SDO (disable descriptor security)**~~ + strap connected GPIO33 pin is it on ICH9-M (X200). HDA\_SDO applies + to later chipsets (series 6 or higher). Disabling descriptor + security also disables the ethernet according to sgsit. sgsit\'s + method involves use of \'soft straps\' (see IRC logs below) instead + of disabling the descriptor. +- **and the location of GPIO33 on the x200s: (was an external link. + Putting it here instead)** + [images/x200/gpio33\_location.jpg](images/x200/gpio33_location.jpg) - + it\'s above the number 7 on TP37 (which is above the big intel chip + at the bottom) +- The ME datasheet may not be for the mobile chipsets but it doesn\'t + vary that much. This one gives some detail and covers QM67 which is + what the X201 uses: + + +

+ +

+ +Flash chips {#flashchips} +----------- + +- Schematics for X200 laptop: + + **~~- Page 20 and page 9 refer to SDA\_HDO or SDA\_HDOUT~~** only on + series 6 or higher chipsets. ICH9-M (X200) does it with a strap + connected to GPIO33 pin (see IRC notes below)\ + - According to page 29, the X200 can have any of the following flash + chips: + - ATMEL AT26DF321-SU 72.26321.A01 - this is a 32Mb (4MiB) chip + - MXIC (Macronix?) MX25L3205DM2I-12G 72.25325.A01 - another 32Mb + (4MiB) chip + - MXIC (Macronix?) MX25L6405DMI-12G 41R0820AA - this is a 64Mb + (8MiB) chip + - Winbond W25X64VSFIG 41R0820BA - another 64Mb (8MiB) chip + + sgsit says that the X200s with the 64Mb flash chips are (probably) + the ones with AMT (alongside the ME), whereas the 32Mb chips contain + only the ME. +- Schematics for X200s laptop: + . + +

+ +

+ +Early development notes {#early_development_notes} +----------------------- + + + Start (hex) End (hex) Length (hex) Area Name + ----------- --------- ------------ --------- + 00000000 003FFFFF 00400000 Flash Image + + 00000000 00000FFF 00001000 Descriptor Region + 00000004 0000000F 0000000C Descriptor Map + 00000010 0000001B 0000000C Component Section + 00000040 0000004F 00000010 Region Section + 00000060 0000006B 0000000C Master Access Section + 00000060 00000063 00000004 CPU/BIOS + 00000064 00000067 00000004 Manageability Engine (ME) + 00000068 0000006B 00000004 GbE LAN + 00000100 00000103 00000004 ICH Strap 0 + 00000104 00000107 00000004 ICH Strap 1 + 00000200 00000203 00000004 MCH Strap 0 + 00000EFC 00000EFF 00000004 Descriptor Map 2 + 00000ED0 00000EF7 00000028 ME VSCC Table + 00000ED0 00000ED7 00000008 Flash device 1 + 00000ED8 00000EDF 00000008 Flash device 2 + 00000EE0 00000EE7 00000008 Flash device 3 + 00000EE8 00000EEF 00000008 Flash device 4 + 00000EF0 00000EF7 00000008 Flash device 5 + 00000F00 00000FFF 00000100 OEM Section + 00001000 001F5FFF 001F5000 ME Region + 001F6000 001F7FFF 00002000 GbE Region + 001F8000 001FFFFF 00008000 PDR Region + 00200000 003FFFFF 00200000 BIOS Region + + Start (hex) End (hex) Length (hex) Area Name + ----------- --------- ------------ --------- + 00000000 003FFFFF 00400000 Flash Image + + 00000000 00000FFF 00001000 Descriptor Region + 00000004 0000000F 0000000C Descriptor Map + 00000010 0000001B 0000000C Component Section + 00000040 0000004F 00000010 Region Section + 00000060 0000006B 0000000C Master Access Section + 00000060 00000063 00000004 CPU/BIOS + 00000064 00000067 00000004 Manageability Engine (ME) + 00000068 0000006B 00000004 GbE LAN + 00000100 00000103 00000004 ICH Strap 0 + 00000104 00000107 00000004 ICH Strap 1 + 00000200 00000203 00000004 MCH Strap 0 + 00000ED0 00000EF7 00000028 ME VSCC Table + 00000ED0 00000ED7 00000008 Flash device 1 + 00000ED8 00000EDF 00000008 Flash device 2 + 00000EE0 00000EE7 00000008 Flash device 3 + 00000EE8 00000EEF 00000008 Flash device 4 + 00000EF0 00000EF7 00000008 Flash device 5 + 00000EFC 00000EFF 00000004 Descriptor Map 2 + 00000F00 00000FFF 00000100 OEM Section + 00001000 00002FFF 00002000 GbE Region + 00003000 00202FFF 00200000 BIOS Region + + Build Settings + -------------- + Flash Erase Size = 0x1000 + +It\'s a utility called \'Flash Image Tool\' for ME 4.x that was used for +this. You drag a complete image into in and the utility decomposes the +various components, allowing you to set soft straps. + +This tool is proprietary, for Windows only, but was used to deblob the +X200. End justified means, and the utility is no longer needed since the +ich9deblob utility (documented on this page) can now be used to create +deblobbed descriptors. + +

+ +

+ +GBE (gigabit ethernet) region in SPI flash {#gbe_region} +------------------------------------------ + +Of the 8K, about 95% is 0xFF. The data is the gbe region is fully +documented in this public datasheet: + + +The only actual content found was: + + + 00 1F 1F 1F 1F 1F 00 08 FF FF 83 10 FF FF FF FF + 08 10 FF FF C3 10 EE 20 AA 17 F5 10 86 80 00 00 + 01 0D 00 00 00 00 05 06 20 30 00 0A 00 00 8B 8D + 02 06 40 2B 43 00 00 00 F5 10 AD BA F5 10 BF 10 + AD BA CB 10 AD BA AD BA 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 01 00 40 28 12 07 40 FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF FF FF FF D9 F0 + 20 60 1F 00 02 00 13 00 00 80 1D 00 FF 00 16 00 + DD CC 18 00 11 20 17 00 DD DD 18 00 12 20 17 00 + 00 80 1D 00 00 00 1F + +The first part is the MAC address set to all 0x1F. It\'s repeated haly +way through the 8K area, and the rest is all 0xFF. This is all +documented in the datasheet. + +The GBe region starts at 0x20A000 bytes from the \*end\* of a factory +image and is 0x2000 bytes long. In libreboot (deblobbed) the descriptor +is set to put gbe directly after the initial 4K flash descriptor. So the +first 4K of the ROM is the descriptor, and then the next 8K is the gbe +region. + +

+ +### GBE region: change MAC address {#gbe_region_changemacaddress} + +According to the datasheet, it\'s supposed to add up to 0xBABA but can +actually be others on the X200. + + +*\"One of those engineers loves classic rock music, so they selected +0xBABA\"* + +In honour of the song *Baba O\'Reilly* by *The Who* apparently. We\'re +not making this stuff up\... + +0x3ABA, 0x34BA, 0x40BA and more have been observed in the main Gbe +regions on the X200 factory.rom dumps. The checksums of the backup +regions match BABA, however. + +By default, the X200 (as shipped by Lenovo) actually has an invalid main +gbe checksum. The backup gbe region is correct, and is what these +systems default to. Basically, you should do what you need on the +\*backup\* gbe region, and then correct the main one by copying from the +backup. + +Look at resources/utilities/ich9deblob/ich9deblob.c. + +- Add the first 0x3F 16bit numbers (unsigned) of the GBe descriptor + together (this includes the checksum value) and that has to add up + to 0xBABA. In other words, the checksum is 0xBABA minus the total of + the first 0x3E 16bit numbers (unsigned), ignoring any overflow. + +

+ +

+ +Flash descriptor region {#flash_descriptor_region} +----------------------- + + +from page 850 onwards. This explains everything that is in the flash +descriptor, which can be used to understand what libreboot is doing +about modifying it. + +How to deblob: + +- patch the number of regions present in the descriptor from 5 - 3 +- originally descriptor + bios + me + gbe + platform +- modified = descriptor + bios + gbe +- the next stage is to patch the part of the descriptor which defines + the start and end point of each section +- then cut out the gbe region and insert it just after the region +- all this can be substantiated with public docs (ICH9 datasheet) +- the final part is flipping 2 bits. Halting the ME via 1 MCH soft + strap and 1 ICH soft strap +- the part of the descriptor described there gives the base address + and length of each region (bits 12:24 of each address) +- to disable a region, you set the base address to 0xFFF and the + length to 0 +- and you change the number of regions from 4 (zero based) to 2 + +There\'s an interesting parameter called \'ME Alternate disable\', which +allows the ME to only handle hardware errata in the southbridge, but +disables any other functionality. This is similar to the \'ignition\' in +the 5 series and higher but using the standard firmware instead of a +small 128K version. Useless for libreboot, though. + +To deblob GM45, you chop out the platform and ME regions and correct the +addresses in flReg1-4. Then you set meDisable to 1 in ICHSTRAP0 and +MCHSTRAP0. + +How to patch the descriptor from the factory.rom dump + +- map the first 4k into the struct (minus the gbe region) +- set NR in FLMAP0 to 2 (from 4) +- adjust BASE and LIMIT in flReg1,2,3,4 to reflect the new location of + each region (or remove them in the case of Platform and ME) +- set meDisable to 1/true in ICHSTRAP0 and MCHSTRAP0 +- extract the 8k GBe region and append that to the end of the 4k + descriptor +- output the 12k concatenated chunk +- Then it can be dd\'d into the first 12K part of a coreboot image. +- the GBe region always starts 0x20A000 bytes from the end of the ROM + +This means that libreboot\'s descriptor region will simply define the +following regions: + +- descriptor (4K) +- gbe (8K) +- bios (rest of flash chip. CBFS also set to occupy this whole size) + +The data in the descriptor region is little endian, and it represents +bits 24:12 of the address (bits 12-24, written this way since bit 24 is +nearer to left than bit 12 in the binary representation). + +So, *x << 12 = address* + +If it\'s in descriptor mode, then the first 4 bytes will be 5A A5 F0 0F. + +

+ +

+ +platform data partition in boot flash (factory.rom / lenovo bios) {#platform_data_region} +----------------------------------------------------------------- + +Basically useless for libreboot, since it appears to be a blob. Removing +it didn\'t cause any issues in libreboot. + +This is a 32K region from the factory image. It could be data +(non-functional) that the original Lenovo BIOS used, but we don\'t know. + +It has only a 448 byte fragment different from 0x00 or 0xFF. + +

+ +

+ +Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ +Permission is granted to copy, distribute and/or modify this document +under the terms of the Creative Commons Attribution-ShareAlike 4.0 +International license or any later version published by Creative +Commons; A copy of the license can be found at +[../cc-by-sa-4.0.txt](../cc-by-sa-4.0.txt) + +Updated versions of the license (when available) can be found at + + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT +POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND +AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND +CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, +OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, +ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE +OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF +WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT +APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU +ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR +OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, +PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES +ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN +IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, +COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT +ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above +shall be interpreted in a manner that, to the extent possible, most +closely approximates an absolute disclaimer and waiver of all liability. + +

diff --git a/docs/hcl/imac52.html b/docs/hcl/imac52.html deleted file mode 100644 index 0dad8992..00000000 --- a/docs/hcl/imac52.html +++ /dev/null @@ -1,76 +0,0 @@ - - - - - - - - - - Apple iMac 5,2 - - - - -

Apple iMac 5,2

- -

- Information to be written soon, but this board is merged in libreboot. -

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- - - - diff --git a/docs/hcl/imac52.md b/docs/hcl/imac52.md new file mode 100644 index 00000000..ea4d0394 --- /dev/null +++ b/docs/hcl/imac52.md @@ -0,0 +1,46 @@ +

+ +Apple iMac 5,2 {#pagetop} +============== + +Information to be written soon, but this board is merged in libreboot. + +

+ +

diff --git a/docs/hcl/index.html b/docs/hcl/index.html deleted file mode 100644 index 3c1dd403..00000000 --- a/docs/hcl/index.html +++ /dev/null @@ -1,736 +0,0 @@ - - - - - - - - - Hardware compatibility list - - - - -

Hardware compatibility list

- This sections relates to known hardware compatibility in libreboot. -

- List of supported hardware -
-
- NOTES: -
- Updating the EC firmware on i945 and GM45 (recommended)
- How to find what EC version you have (i945/GM45)
-
Recommended wifi chipsets

- Back to previous index. -

- -

List of supported hardware

- -

- Libreboot supports the following systems in this release: -

Desktops (AMD, Intel, x86)

Servers/workstations (AMD, x86)

Laptops (ARM)

ASUS Chromebook C201

Laptops (Intel, x86)

Lenovo ThinkPad X60/X60s
Lenovo ThinkPad X60 Tablet
Lenovo ThinkPad T60 (there are exceptions. see link)
Lenovo ThinkPad X200
Lenovo ThinkPad R400
Lenovo ThinkPad T400
Lenovo ThinkPad T500
Apple MacBook1,1
Apple MacBook2,1

- -

- 'Supported' means that the build scripts know how to build ROM images for these systems, - and that the systems have been tested (confirmed working). There may be exceptions; - in other words, this is a list of 'officially' supported systems. -

- -

- It is also possible to build ROM images (from source) for other systems (and virtual systems, e.g. QEMU). -

- -

- - -

- -

EC update on i945 (X60, T60) and GM45 (X200, T400, T500, R400)

- -

- It is recommended that you update to the latest EC firmware version. - The EC firmware - is separate from libreboot, so we don't actually provide that, but - if you still have Lenovo BIOS then you can just run the Lenovo BIOS - update utility, which will update both the BIOS and EC version. - See: -

- NOTE: this can only be done when you are using Lenovo BIOS. How to - update the EC firmware while running libreboot is unknown. - Libreboot only replaces the BIOS firmware, not EC. -

- Updated EC firmware has several advantages e.g. - bettery battery handling. -

- Back to top of page -

- -

How to find what EC version you have (i945/GM45)

- -

- In GNU+Linux, you can try this:
- grep 'at EC' /proc/asound/cards -

- Sample output:
- ThinkPad Console Audio Control at EC reg 0x30, fw 7WHT19WW-3.6 -

- 7WHT19WW is the version in different notation, use search engine to find out regular version - in this case it's a 1.06 for x200 tablet -

- Back to top of page -

- -

Recommended wifi chipsets

- The following are known to work well: -

mini PCI express cards using the Atheros AR9285 chipset (e.g. Atheros AR5B95) - 802.11n
USB dongles using the AR9271 chipset (e.g. Unex DNuA 93-F) - 802.11n
Any of the chipsets listed at https://h-node.org/wifi/catalogue/en/1/1/undef/undef/yes?

- The following was mentioned (on IRC), but it's unknown to the libreboot project if these work with linux-libre kernel (TODO: test): -

ar5bhb116 ar9382 ABGN
[0200]: Qualcomm Atheros AR242x / AR542x Wireless Network Adapter (PCI-Express) [168c:001c]

- -

List of supported ThinkPad X60s

- -

- Native gpu initialization ('native graphics') which replaces the proprietary VGA Option ROM - ('Video BIOS' or 'VBIOS'), - all known LCD panels are currently compatible: -

- -

- To find what LCD panel you have, see: ../misc/#get_edid_panelname. -

- -

TMD-Toshiba LTD121ECHB: #
CMO N121X5-L06: #
Samsung LTN121XJ-L07: #
BOE-Hydis HT121X01-101: #

- -

- You can remove an X61/X61s motherboard from the chassis and install an X60/X60s motherboard in it's place (for flashing libreboot). The chassis is mostly identical - and the motherboards are the same shape/size. -

- -

- The X60 typically comes with an Intel wifi chipset which does not work at all without proprietary firmware, and while Lenovo BIOS is running - the system will refuse to boot if you replace the card. Fortunately it is very easily replaced; - just remove the card and install another one after libreboot is installed. See #recommended_wifi for replacements. -

- -

List of supported ThinkPad X60 Tablets

- -

- Native gpu initialization ('native graphics') which replaces the proprietary VGA Option ROM - ('Video BIOS' or 'VBIOS'). -

- -

- To find what LCD panel you have, see: ../misc/#get_edid_panelname. -

- -

- There are 5 known LCD panels for the X60 Tablet: -

- X60T XGA (1024x768): -
- BOE-Hydis HV121X03-100 (works)
- Samsung LTN121XP01 (does not work. blank screen)
- BOE-Hydis HT12X21-351 (does not work. blank screen)
-
- X60T SXGA+ (1400x1050): -
- BOE-Hydis HV121P01-100 (works)
- BOE-Hydis HV121P01-101 (works)
-

- -

- Most X60Ts only have digitizer (pen), but some have finger (touch) aswell as pen; finger/multitouch doesn't work, only digitizer (pen) does. -

- -

- You can remove an X61/X61s motherboard from the chassis and install an X60/X60s motherboard in its place (for flashing libreboot). The chassis is mostly identical - and the motherboards are the same shape/size. It is unknown if the same applies between the X60 Tablet and the X61 Tablet. -

- -

- The X60 Tablet typically comes with an Intel wifi chipset which does not work at all without proprietary firmware, and while Lenovo BIOS is running - the system will refuse to boot if you replace the card. Fortunately it is very easily replaced; - just remove the card and install another one after libreboot is installed. See #recommended_wifi for replacements. -

- -

- A user with a X60T that has digitizer+finger support, reported that they could get finger input working. They - used linuxwacom at git tag 0.25.99.2 and had the following in their xorg.conf: -

- -

-# Now, for some reason (probably a bug in linuxwacom),
-# the 'Touch=on' directive gets reset to 'off'.
-# So you'll need to do
-# $ xsetwacom --set WTouch Touch on
-#
-# tested with linuxwacom git 42a42b2a8636abc9e105559e5dea467163499de7
-
-Section "Monitor"
-	 Identifier             "<default monitor>"
-	 DisplaySize     245 184
-EndSection
-
-Section "Screen"
-	 Identifier "Default Screen Section"
-	 Monitor    "<default monitor<"
-EndSection
-
-Section "InputDevice"
-	 Identifier  "WTouch"
-	 Driver      "wacom"
-	 Option      "Device" "/dev/ttyS0"
-#    Option      "DebugLevel" "12"
-	 Option      "BaudRate" "38400"
-	 Option      "Type" "touch"
-	 Option      "Touch" "on"
-	 Option      "Gesture" "on"
-	 Option      "ForceDevice" "ISDV4"
-#    Option      "KeepShape" "on"
-	 Option      "Mode" "Absolute"
-	 Option      "RawSample" "2"
-#    Option      "TPCButton" "off"
-	 Option      "TopX" "17"
-	 Option      "TopY" "53"
-	 Option      "BottomX" "961"
-	 Option      "BottomY" "985"
-EndSection
-
-Section "ServerLayout"
-  Identifier    "Default Layout"
-  Screen        "Default Screen Section"
-  InputDevice   "WTouch" "SendCoreEvents"
-EndSection
-
-

- -

Supported T60 list

- -

- Native gpu initialization ('native graphics') which replaces the proprietary VGA Option ROM - ('Video BIOS' or 'VBIOS'). -

- -

- To find what LCD panel you have, see: ../misc/#get_edid_panelname. -

- -

- - Some T60s have ATI GPUs, and all T60P laptops have ATI GPUs These are incompatible! See #t60_ati_intel for how to remedy this. - -

- -

- Tested LCD panels: working(compatible) -

TMD-Toshiba LTD141EN9B (14.1" 1400x1050) (FRU P/N 41W1478 recommended for the inverter board)
Samsung LTN141P4-L02 (14.1" 1400x1050) (FRU P/N 41W1478 recommended for the inverter board)
LG-Philips LP150E05-A2K1 (15.1" 1400x1050) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)
Samsung LTN150P4-L01 (15.1" 1400x1050) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board) (not a T60 screen afaik, but it works)
BOE-Hydis HV150UX1-100 (15.1" 1600x1200) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)

- -

- Tested LCD panels: not working yet (incompatible; see ../future/#lcd_i945_incompatibility) -

Samsung LTN141XA-L01 (14.1" 1024x768)
LG-Philips LP150X09 (15.1" 1024x768)
Samsung LTN150XG (15.1" 1024x768)
LG-Philips LP150E06-A5K4 (15.1" 1400x1050) (also, not an official T60 screen)
Samsung LTN154X3-L0A (15.4" 1280x800)
IDtech IAQX10N (15.1" 2048x1536) (no display in GRUB, display in GNU+Linux is temperamental) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)
IDtech N150U3-L01 (15.1" 1600x1200) (no display in GRUB, display in GNU+Linux works) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)

- -

- The following LCD panels are UNTESTED. If you have one of these panels - then please submit a report!: -

CMO(IDtech?) N141XC (14.1" 1024x768)
BOE-Hydis HT14X14 (14.1" 1024x768)
TMD-Toshiba LTD141ECMB (14.1" 1024x768)
Boe-Hydis HT14P12 (14.1" 1400x1050) (FRU P/N 41W1478 recommended for the inverter board)
CMO (IDtech?) 13N7068 (15.1" 1024x768)
CMO (IDtech?) 13N7069 (15.1" 1024x768)
BOE-Hydis HV150P01-100 (15.1" 1400x1050) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)
BOE-Hydis HV150UX1-102 (15.1" 1600x1200) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)
IDtech IAQX10S (15.1" 2048x1536) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended for the inverter board)
Samsung LTN154P2-L05 (42X4641 42T0329) (15.4" 1680x1050)
LG-Philips LP154W02-TL10 (13N7020 42T0423) (15.4" 1680x1050)
LG-Philips LP154WU1-TLB1 (42T0361) (15.4" 1920x1200) (for T61p but it might work in T60. Unknown!)
Samsung LTN154U2-L05 (42T0408 42T0574) (15.4" 1920x1200) (for T61p but it might work in T60. Unknown!)

- -

- It is unknown whether the 1680x1050 (15.4") and 1920x1200 (15.4") panels use a different inverter board than the 1280x800 panels. -

- -

- The T60 typically comes with an Intel wifi chipset which does not work at all without proprietary firmware, and while Lenovo BIOS is running - the system will refuse to boot if you replace the card. Fortunately it is very easily replaced; - just remove the card and install another one after libreboot is installed. See #recommended_wifi for replacements. -

- -

ThinkPad T60 (ATI GPU) and ThinkPad T60 (Intel GPU) differences.

- -

- If your T60 is a 14.1" or 15.1" model with an ATI GPU, it won't work with libreboot by default but - you can replace the motherboard with another T60 motherboard that has an Intel GPU, and then libreboot should work. -

- -

- As far as I know, 14.1" (Intel GPU) and 15.1" (Intel GPU) T60 motherboards are the same, where - 'spacers' are used on the 15.1" T60. In any case, it makes sense to find one that is guaranteed to fit in your chassis. -

- -

- There is also a 15.4" T60 with Intel GPU. -

- -

- Note: the T60p laptops all have ATI graphics. - The T60p laptops cannot be used with libreboot under any circumstances. -

- -

- The following T60 motherboard (see area highlighted in white) shows an empty space where the ATI GPU would be (this particular motherboard has an Intel GPU):

- -

- -

- The reason that the ATI GPU on T60 is unsupported is due to the VBIOS (Video BIOS) which is non-free. - The VBIOS for the Intel GPU on X60/T60 has been reverse engineered, and replaced with Free Software and - so will work in libreboot. -

- -

- The 'Video BIOS' is what initializes graphics. -

- -

- See: https://en.wikipedia.org/wiki/Video_BIOS.
- In fact, lack of free VBIOS in general is a big problem in coreboot, and is one reason (among others) why many ports for coreboot are - unsuitable for libreboot's purpose. -

- -

- Theoretically, the ThinkPad T60 with ATI GPU can work with libreboot and have ROM images compiled for it, however - in practise it would not be usable as a laptop because there would be no visual display at all. That being said, - such a configuration is acceptable for use in a 'headless' server setup (with serial and/or ssh console as the display). -

- -

Information about the macbook1,1

- -

- There is an Apple laptop called the macbook1,1 from 2006 which uses the same i945 chipset as the ThinkPad X60/T60. - A developer ported the MacBook2,1 to coreboot, the ROM images also work on the macbook1,1. -

- -

- You can refer to #macbook21 for most of this. Macbook2,1 laptops come with Core 2 Duo processors - which support 64-bit operating systems (and 32-bit). The MacBook1,1 uses Core Duo processors (supports 32-bit OS but not 64-bit), - and it is believed that this is the only difference. -

- -

- It is believed that all models are compatible, listed here: -

http://www.everymac.com/ultimate-mac-lookup/?search_keywords=MacBook1,1

- -

- Compatible models -

- Specifically (Order No. / Model No. / CPU): -

MA255LL/A / A1181 (EMC 2092) / Core Duo T2500 (tested - working)
MA254LL/A / A1181 (EMC 2092) / Core Duo T2400 (tested - working)
MA472LL/A / A1181 (EMC 2092) / Core Duo T2500 (untested)

- -

- Also of interest: ../git/#config_macbook21. -

- -

- Unbricking: this page shows disassembly guides and mono's page (see #macbook21) - shows the location of the SPI flash chip on the motherboard. How to remove the motherboard. -

- -

- No method is yet known for flashing in GNU+Linux while the Apple firmware is running. You will need to disassemble the system and flash externally. - Reading from flash seems to work. For external flashing, refer to ../install/bbb_setup.html. -

- -

Information about the macbook2,1

- -

- There is an Apple laptop called the macbook2,1 from late 2006 or early 2007 that uses the same i945 chipset - as the ThinkPad X60 and ThinkPad T60. A developer ported coreboot to their macbook2,1, and now libreboot can run on it. -

- Mono Moosbart is the person who wrote the port for macbook2,1. Referenced below are copies (up to date at the time of writing, 20140630) - of the pages that this person wrote when porting coreboot to the macbook2,1. They are included here in case the main site goes down for - whatever reason, since they include a lot of useful information. -

- Backups created using wget:
- $ wget -m -p -E -k -K -np http://macbook.donderklumpen.de/
- $ wget -m -p -E -k -K -np http://macbook.donderklumpen.de/coreboot/
- Use -e robots=off if using this trick for other sites and the site restricts using robots.txt -

- -

- Links to wget backups (and the backups themselves) of Mono's pages (see above) removed temporarily. Mono has given me permission to distribute them, but I need to ask - this person to tell me what license these works fall under first. Otherwise, the above URLs should be fine. NOTE TO SELF: REMOVE THIS WHEN DONE -

- -

- Installing GNU+Linux distributions (on Apple EFI firmware) -

Parabola GNU+Linux installation on a macbook2,1 with Apple EFI firmware (this is a copy of Mono's page, see above)

- How to boot an ISO: burn it to a CD (like you would normally) and hold down the Alt/Control key while booting. - The bootloader will detect the GNU+Linux CD as 'Windows' (because Apple doesn't think GNU+Linux exists). Install it like you normally would. - When you boot up again, hold Alt/Control once more. The installation (on the HDD) will once again be seen as 'Windows'. (it's not actually Windows, - but Apple likes to think that Apple and Microsoft are all that exist.) - Now to install libreboot, follow ../install/#flashrom_macbook21. -

- -

- Information about coreboot -

Coreboot on the macbook2,1 (this is a copy of Mono's page, see above)

- -

- coreboot wiki page -

https://www.coreboot.org/Board:apple/macbook21

- -

- Compatible models -

- It is believed that all models are compatible, listed here: -

http://www.everymac.com/ultimate-mac-lookup/?search_keywords=MacBook2,1

- Specifically (Order No. / Model No. / CPU): -

MA699LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T5600 (tested - working)
MA701LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T7200 (tested - working)
MB061LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7200 (untested)
MA700LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T7200 (tested - working)
MB063LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7400 (works)
MB062LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7400 (tested - working)

- -

- Also of interest: ../git/#config_macbook21. -

- -

- Unbricking: this page shows disassembly guides and mono's page (see above) - shows the location of the SPI flash chip on the motherboard. How to remove the motherboard. -

- -

- For external flashing, refer to ../install/bbb_setup.html. -

- -

- You need to replace OS X with GNU+Linux before flashing libreboot. (OSX won't run at all in libreboot). -

- -

- There are some issues with this system (compared to other computers that libreboot supports): -

- -

- This is an apple laptop, so it comes with OS X: it has an Apple keyboard, which means that certain keys are missing: - insert, del, home, end, pgup, pgdown. There is also one mouse button only. Battery life is poor compared to X60/T60 (for now). - It also has other issues: for example, the Apple logo on the back is a hole, exposing the backlight, which means that it glows. You should cover it up. -

- -

- The system does get a bit hotter compared to when running the original firmware. It is certainly hotter - than an X60/T60. The heat issues have been partially fixed by the following patch (now merged in libreboot): - https://review.coreboot.org/#/c/7923/. -

- -

- - The MacBook2,1 comes with a webcam, which does not work without proprietary software. Also, webcams are a security risk; cover it up! Or remove it. - -

- -

- A user reported that they could get better response from the touchpad with the following in their xorg.conf: -

- -

-Section "InputClass"
- Identifier "Synaptics Touchpad"
- Driver "synaptics"
- MatchIsTouchpad "on"
- MatchDevicePath "/dev/input/event*"
- Driver "synaptics"
-# The next two values determine how much pressure one needs
-# for tapping, moving the cursor and other events.
- Option "FingerLow" "10"
- Option "FingerHigh" "15"
-# Do not emulate mouse buttons in the touchpad corners.
- Option "RTCornerButton" "0"
- Option "RBCornerButton" "0"
- Option "LTCornerButton" "0"
- Option "LBCornerButton" "0"
-# One finger tap = left-click
- Option "TapButton1" "1"
-# Two fingers tap = right-click
- Option "TapButton2" "3"
-# Three fingers tap = middle-mouse
- Option "TapButton3" "2"
-# Try to not count the palm of the hand landing on the touchpad
-# as a tap. Not sure if helps.
- Option "PalmDetect" "1"
-# The following modifies how long and how fast scrolling continues
-# after lifting the finger when scrolling
- Option "CoastingSpeed" "20"
- Option "CoastingFriction" "200"
-# Smaller number means that the finger has to travel less distance
-# for it to count as cursor movement. Larger number prevents cursor
-# shaking.
- Option "HorizHysteresis" "10"
- Option "VertHysteresis" "10"
-# Prevent two-finger scrolling. Very jerky movement
- Option "HorizTwoFingerScroll" "0"
- Option "VertTwoFingerScroll" "0"
-# Use edge scrolling
- Option "HorizEdgeScroll" "1"
- Option "VertEdgeScroll" "1"
-EndSection
-

- A user reported that the above is only for linux kernel 3.15 or lower. For newer kernels, - the touchpad works fine out of the box, except middle tapping. -

- -

- A user submitted a utility to enable 3-finger tap on this laptop. It's - available at resources/utilities/macbook21-three-finger-tap in - the libreboot git repository. -

- -

- Copyright © 2014, 2015, 2016 Leah Rowe <info@minifree.org>
- Permission is granted to copy, distribute and/or modify this document - under the terms of the Creative Commons Attribution-ShareAlike 4.0 International license - or any later version published by Creative Commons; - - A copy of the license can be found at ../cc-by-sa-4.0.txt -

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- - - diff --git a/docs/hcl/index.md b/docs/hcl/index.md new file mode 100644 index 00000000..dd8d7e9f --- /dev/null +++ b/docs/hcl/index.md @@ -0,0 +1,666 @@ +

+ +Hardware compatibility list {#pagetop} +=========================== + +This sections relates to known hardware compatibility in libreboot. + +- [List of supported hardware](#supported_list) + - [Desktops (x86, AMD and Intel)](#supported_desktops_x86amdintel) + - [Servers/workstations](#supported_workstations_x86amd) + - [Laptops (ARM)](#supported_laptops_arm) + - [Laptops (Intel, x86)](#supported_laptops_x86intel) +- NOTES: + - [Updating the EC firmware on i945 and GM45 + (recommended)](#ecupdate) + - [How to find what EC version you have (i945/GM45)](#ecversion) +- [Recommended wifi chipsets](#recommended_wifi) + +[Back to previous index](../). + +

+ +

+ +List of supported hardware {#supported_list} +-------------------------- + +Libreboot supports the following systems in this release: + +### Desktops (AMD, Intel, x86) {#supported_desktops_x86amdintel} + +- [Gigabyte GA-G41M-ES2L motherboard](ga-g41m-es2l.html) +- [Intel D510MO motherboard](d510mo.html) +- [ASUS KCMA-D8 motherboard](kcma-d8.html) +- [Intel D945GCLF](d945gclf.html) +- [Apple iMac 5,2](imac52.html) + +### Servers/workstations (AMD, x86) {#supported_workstations_x86amd} + +- [ASUS KFSN4-DRE motherboard](kfsn4-dre.html) +- [ASUS KGPE-D16 motherboard](kgpe-d16.html) + +### Laptops (ARM) {#supported_laptops_arm} + +- [ASUS Chromebook C201](c201.html) + +### Laptops (Intel, x86) {#supported_laptops_x86intel} + +- [Lenovo ThinkPad X60/X60s](#supported_x60_list) +- [Lenovo ThinkPad X60 Tablet](#supported_x60t_list) +- [Lenovo ThinkPad T60](#supported_t60_list) (there are exceptions. + see link) +- [Lenovo ThinkPad X200](x200.html) +- [Lenovo ThinkPad R400](r400.html) +- [Lenovo ThinkPad T400](t400.html) +- [Lenovo ThinkPad T500](t500.html) +- [Apple MacBook1,1](#macbook11) +- [Apple MacBook2,1](#macbook21) + +\'Supported\' means that the build scripts know how to build ROM images +for these systems, and that the systems have been tested (confirmed +working). There may be exceptions; in other words, this is a list of +\'officially\' supported systems. + +It is also possible to build ROM images (from source) for other systems +(and virtual systems, e.g. QEMU). + +[Back to top of page](#pagetop) + +

+ +

+ +EC update on i945 (X60, T60) and GM45 (X200, T400, T500, R400) {#ecupdate} +============================================================== + +It is recommended that you update to the latest EC firmware version. The +[EC firmware](https://libreboot.org/faq/#firmware-ec) is separate from +libreboot, so we don\'t actually provide that, but if you still have +Lenovo BIOS then you can just run the Lenovo BIOS update utility, which +will update both the BIOS and EC version. See: + +- +- + +NOTE: this can only be done when you are using Lenovo BIOS. How to +update the EC firmware while running libreboot is unknown. Libreboot +only replaces the BIOS firmware, not EC. + +Updated EC firmware has several advantages e.g. bettery battery +handling. + +[Back to top of page](#pagetop) + +

+ +

+ +How to find what EC version you have (i945/GM45) {#ecversion} +================================================ + +In GNU+Linux, you can try this:\ +**grep \'at EC\' /proc/asound/cards** + +Sample output:\ +**ThinkPad Console Audio Control at EC reg 0x30, fw 7WHT19WW-3.6** + +7WHT19WW is the version in different notation, use search engine to find +out regular version - in this case it\'s a 1.06 for x200 tablet + +[Back to top of page](#pagetop) + +

+ +

+ +Recommended wifi chipsets {#recommended_wifi} +------------------------- + +The following are known to work well: + +- mini PCI express cards using the Atheros AR9285 chipset (e.g. + Atheros AR5B95) - 802.11n +- USB dongles using the AR9271 chipset (e.g. Unex DNuA 93-F) - 802.11n +- Any of the chipsets listed at + + +The following was mentioned (on IRC), but it\'s unknown to the libreboot +project if these work with linux-libre kernel (TODO: test): + +- ar5bhb116 ar9382 ABGN +- \[0200\]: Qualcomm Atheros AR242x / AR542x Wireless Network Adapter + (PCI-Express) \[168c:001c\] + +[Back to top of page](#pagetop) + +

+ +

+ +List of supported ThinkPad X60s {#supported_x60_list} +------------------------------- + +Native gpu initialization (\'native graphics\') which replaces the +proprietary VGA Option ROM (\'[Video +BIOS](https://en.wikipedia.org/wiki/Video_BIOS)\' or \'VBIOS\'), all +known LCD panels are currently compatible: + +To find what LCD panel you have, see: +[../misc/\#get\_edid\_panelname](../misc/#get_edid_panelname). + +- TMD-Toshiba LTD121ECHB: \# +- CMO N121X5-L06: \# +- Samsung LTN121XJ-L07: \# +- BOE-Hydis HT121X01-101: \# + +You can remove an X61/X61s motherboard from the chassis and install an +X60/X60s motherboard in it\'s place (for flashing libreboot). The +chassis is mostly identical and the motherboards are the same +shape/size. + +The X60 typically comes with an Intel wifi chipset which does not work +at all without proprietary firmware, and while Lenovo BIOS is running +the system will refuse to boot if you replace the card. Fortunately it +is very easily replaced; just remove the card and install another one +**after** libreboot is installed. See +[\#recommended\_wifi](#recommended_wifi) for replacements. + +[Back to top of page.](#pagetop) + +

+ +

+ +List of supported ThinkPad X60 Tablets {#supported_x60t_list} +-------------------------------------- + +Native gpu initialization (\'native graphics\') which replaces the +proprietary VGA Option ROM (\'[Video +BIOS](https://en.wikipedia.org/wiki/Video_BIOS)\' or \'VBIOS\'). + +To find what LCD panel you have, see: +[../misc/\#get\_edid\_panelname](../misc/#get_edid_panelname). + +There are 5 known LCD panels for the X60 Tablet: + +- **X60T XGA (1024x768):** + - BOE-Hydis HV121X03-100 (works) + - Samsung LTN121XP01 (does not work. blank screen) + - BOE-Hydis HT12X21-351 (does not work. blank screen) +- **X60T SXGA+ (1400x1050):** + - BOE-Hydis HV121P01-100 (works) + - BOE-Hydis HV121P01-101 (works) + +Most X60Ts only have digitizer (pen), but some have finger (touch) +aswell as pen; finger/multitouch doesn\'t work, only digitizer (pen) +does. + +You can remove an X61/X61s motherboard from the chassis and install an +X60/X60s motherboard in its place (for flashing libreboot). The chassis +is mostly identical and the motherboards are the same shape/size. **It +is unknown if the same applies between the X60 Tablet and the X61 +Tablet**. + +The X60 Tablet typically comes with an Intel wifi chipset which does not +work at all without proprietary firmware, and while Lenovo BIOS is +running the system will refuse to boot if you replace the card. +Fortunately it is very easily replaced; just remove the card and install +another one **after** libreboot is installed. See +[\#recommended\_wifi](#recommended_wifi) for replacements. + +A user with a X60T that has digitizer+finger support, reported that they +could get finger input working. They used linuxwacom at git tag +0.25.99.2 and had the following in their xorg.conf: + + # Now, for some reason (probably a bug in linuxwacom), + # the 'Touch=on' directive gets reset to 'off'. + # So you'll need to do + # $ xsetwacom --set WTouch Touch on + # + # tested with linuxwacom git 42a42b2a8636abc9e105559e5dea467163499de7 + + Section "Monitor" + Identifier "" + DisplaySize 245 184 + EndSection + + Section "Screen" + Identifier "Default Screen Section" + Monitor " + +

+ +Supported T60 list {#supported_t60_list} +------------------ + +Native gpu initialization (\'native graphics\') which replaces the +proprietary VGA Option ROM (\'[Video +BIOS](https://en.wikipedia.org/wiki/Video_BIOS)\' or \'VBIOS\'). + +To find what LCD panel you have, see: +[../misc/\#get\_edid\_panelname](../misc/#get_edid_panelname). + +**Some T60s have ATI GPUs, and all T60P laptops have ATI GPUs These are +incompatible! See [\#t60\_ati\_intel](#t60_ati_intel) for how to remedy +this.** + +Tested LCD panels: **working(compatible)** + +- TMD-Toshiba LTD141EN9B (14.1\" 1400x1050) (FRU P/N 41W1478 + recommended for the inverter board) +- Samsung LTN141P4-L02 (14.1\" 1400x1050) (FRU P/N 41W1478 recommended + for the inverter board) +- LG-Philips LP150E05-A2K1 (15.1\" 1400x1050) (P/N 42T0078 FRU 42T0079 + or P/N 41W1338 recommended for the inverter board) +- Samsung LTN150P4-L01 (15.1\" 1400x1050) (P/N 42T0078 FRU 42T0079 or + P/N 41W1338 recommended for the inverter board) (not a T60 screen + afaik, but it works) +- BOE-Hydis HV150UX1-100 (15.1\" 1600x1200) (P/N 42T0078 FRU 42T0079 + or P/N 41W1338 recommended for the inverter board) + +

+ +Tested LCD panels: **not working yet (incompatible; see +[../future/\#lcd\_i945\_incompatibility](../future/#lcd_i945_incompatibility))** + +- Samsung LTN141XA-L01 (14.1\" 1024x768) +- LG-Philips LP150X09 (15.1\" 1024x768) +- Samsung LTN150XG (15.1\" 1024x768) +- LG-Philips LP150E06-A5K4 (15.1\" 1400x1050) (also, not an official + T60 screen) +- Samsung LTN154X3-L0A (15.4\" 1280x800) +- IDtech IAQX10N (15.1\" 2048x1536) (no display in GRUB, display in + GNU+Linux is temperamental) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 + recommended for the inverter board) +- IDtech N150U3-L01 (15.1\" 1600x1200) (no display in GRUB, display in + GNU+Linux works) (P/N 42T0078 FRU 42T0079 or P/N 41W1338 recommended + for the inverter board) + +

+ +

+ +*The following LCD panels are **UNTESTED**. If you have one of these +panels then please submit a report!*: + +- CMO(IDtech?) N141XC (14.1\" 1024x768) +- BOE-Hydis HT14X14 (14.1\" 1024x768) +- TMD-Toshiba LTD141ECMB (14.1\" 1024x768) +- Boe-Hydis HT14P12 (14.1\" 1400x1050) (FRU P/N 41W1478 recommended + for the inverter board) +- CMO (IDtech?) 13N7068 (15.1\" 1024x768) +- CMO (IDtech?) 13N7069 (15.1\" 1024x768) +- BOE-Hydis HV150P01-100 (15.1\" 1400x1050) (P/N 42T0078 FRU 42T0079 + or P/N 41W1338 recommended for the inverter board) +- BOE-Hydis HV150UX1-102 (15.1\" 1600x1200) (P/N 42T0078 FRU 42T0079 + or P/N 41W1338 recommended for the inverter board) +- IDtech IAQX10S (15.1\" 2048x1536) (P/N 42T0078 FRU 42T0079 or P/N + 41W1338 recommended for the inverter board) +- Samsung LTN154P2-L05 (42X4641 42T0329) (15.4\" 1680x1050) +- LG-Philips LP154W02-TL10 (13N7020 42T0423) (15.4\" 1680x1050) +- LG-Philips LP154WU1-TLB1 (42T0361) (15.4\" 1920x1200) **(for T61p + but it might work in T60. Unknown!)** +- Samsung LTN154U2-L05 (42T0408 42T0574) (15.4\" 1920x1200) **(for + T61p but it might work in T60. Unknown!)** + +It is unknown whether the 1680x1050 (15.4\") and 1920x1200 (15.4\") +panels use a different inverter board than the 1280x800 panels. + +The T60 typically comes with an Intel wifi chipset which does not work +at all without proprietary firmware, and while Lenovo BIOS is running +the system will refuse to boot if you replace the card. Fortunately it +is very easily replaced; just remove the card and install another one +**after** libreboot is installed. See +[\#recommended\_wifi](#recommended_wifi) for replacements. + +

+ +[Back to top of page.](#pagetop) + +

+ +

+ +ThinkPad T60 (ATI GPU) and ThinkPad T60 (Intel GPU) differences. {#t60_ati_intel} +---------------------------------------------------------------- + +If your T60 is a 14.1\" or 15.1\" model with an ATI GPU, it won\'t work +with libreboot by default but you can replace the motherboard with +another T60 motherboard that has an Intel GPU, and then libreboot should +work. + +As far as I know, 14.1\" (Intel GPU) and 15.1\" (Intel GPU) T60 +motherboards are the same, where \'spacers\' are used on the 15.1\" T60. +In any case, it makes sense to find one that is guaranteed to fit in +your chassis. + +There is also a 15.4\" T60 with Intel GPU. + +Note: the T60**p** laptops all have ATI graphics. The T60p laptops +cannot be used with libreboot under any circumstances. + +The following T60 motherboard (see area highlighted in white) shows an +empty space where the ATI GPU would be (this particular motherboard has +an Intel GPU):\ +\ +![](../images/t60_dev/t60_unbrick.jpg) + +The reason that the ATI GPU on T60 is unsupported is due to the VBIOS +(Video BIOS) which is non-free. The VBIOS for the Intel GPU on X60/T60 +has been reverse engineered, and replaced with Free Software and so will +work in libreboot. + +The \'Video BIOS\' is what initializes graphics. + +See: .\ +In fact, lack of free VBIOS in general is a big problem in coreboot, and +is one reason (among others) why many ports for coreboot are unsuitable +for libreboot\'s purpose. + +Theoretically, the ThinkPad T60 with ATI GPU can work with libreboot and +have ROM images compiled for it, however in practise it would not be +usable as a laptop because there would be no visual display at all. That +being said, such a configuration is acceptable for use in a \'headless\' +server setup (with serial and/or ssh console as the display). + +[Back to top of page.](#pagetop) + +

+ +

+ +Information about the macbook1,1 {#macbook11} +-------------------------------- + +There is an Apple laptop called the macbook1,1 from 2006 which uses the +same i945 chipset as the ThinkPad X60/T60. A developer ported the +[MacBook2,1](#macbook21) to coreboot, the ROM images also work on the +macbook1,1. + +You can refer to [\#macbook21](#macbook21) for most of this. Macbook2,1 +laptops come with Core 2 Duo processors which support 64-bit operating +systems (and 32-bit). The MacBook1,1 uses Core Duo processors (supports +32-bit OS but not 64-bit), and it is believed that this is the only +difference. + +It is believed that all models are compatible, listed here: + +- + +

+ +### Compatible models + +Specifically (Order No. / Model No. / CPU): + +- MA255LL/A / A1181 (EMC 2092) / Core Duo T2500 **(tested - working)** +- MA254LL/A / A1181 (EMC 2092) / Core Duo T2400 **(tested - working)** +- MA472LL/A / A1181 (EMC 2092) / Core Duo T2500 (untested) + +

+ +

+ +Information about the macbook2,1 {#macbook21} +-------------------------------- + +There is an Apple laptop called the macbook2,1 from late 2006 or early +2007 that uses the same i945 chipset as the ThinkPad X60 and ThinkPad +T60. A developer ported coreboot to their macbook2,1, and now libreboot +can run on it. + +Mono Moosbart is the person who wrote the port for macbook2,1. +Referenced below are copies (up to date at the time of writing, +20140630) of the pages that this person wrote when porting coreboot to +the macbook2,1. They are included here in case the main site goes down +for whatever reason, since they include a lot of useful information. + +Backups created using wget:\ +**\$ wget -m -p -E -k -K -np http://macbook.donderklumpen.de/**\ +**\$ wget -m -p -E -k -K -np +http://macbook.donderklumpen.de/coreboot/**\ +Use **-e robots=off** if using this trick for other sites and the site +restricts using robots.txt + +**Links to wget backups (and the backups themselves) of Mono\'s pages +(see above) removed temporarily. Mono has given me permission to +distribute them, but I need to ask this person to tell me what license +these works fall under first. Otherwise, the above URLs should be fine. +NOTE TO SELF: REMOVE THIS WHEN DONE** + +

+ +### Installing GNU+Linux distributions (on Apple EFI firmware) + +- [Parabola GNU+Linux installation on a macbook2,1 with Apple EFI + firmware](#) (this is a copy of Mono\'s page, see above) + +How to boot an ISO: burn it to a CD (like you would normally) and hold +down the Alt/Control key while booting. The bootloader will detect the +GNU+Linux CD as \'Windows\' (because Apple doesn\'t think GNU+Linux +exists). Install it like you normally would. When you boot up again, +hold Alt/Control once more. The installation (on the HDD) will once +again be seen as \'Windows\'. (it\'s not actually Windows, but Apple +likes to think that Apple and Microsoft are all that exist.) Now to +install libreboot, follow +[../install/\#flashrom\_macbook21](../install/#flashrom_macbook21). + +

+ +

+ +### Information about coreboot + +- [Coreboot on the macbook2,1](#) (this is a copy of Mono\'s page, see + above) + +

+ +

+ +### coreboot wiki page + +- + +

+ +

+ +### Compatible models + +It is believed that all models are compatible, listed here: + +- + +Specifically (Order No. / Model No. / CPU): + +- MA699LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T5600 **(tested - + working)** +- MA701LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T7200 **(tested - + working)** +- MB061LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7200 (untested) +- MA700LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T7200 **(tested - + working)** +- MB063LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7400 (works) +- MB062LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7400 **(tested - + working)** + +

+ +Also of interest: +[../git/\#config\_macbook21](../git/#config_macbook21). + +Unbricking: [this page shows disassembly +guides](https://www.ifixit.com/Device/MacBook_Core_2_Duo) and mono\'s +page (see above) shows the location of the SPI flash chip on the +motherboard. [How to remove the +motherboard](https://www.ifixit.com/Guide/MacBook+Core+2+Duo+PRAM+Battery+Replacement/529). + +For external flashing, refer to +[../install/bbb\_setup.html](../install/bbb_setup.html). + +You need to replace OS X with GNU+Linux before flashing libreboot. (OSX +won\'t run at all in libreboot). + +There are some issues with this system (compared to other computers that +libreboot supports): + +This is an apple laptop, so it comes with OS X: it has an Apple +keyboard, which means that certain keys are missing: insert, del, home, +end, pgup, pgdown. There is also one mouse button only. Battery life is +poor compared to X60/T60 (for now). It also has other issues: for +example, the Apple logo on the back is a hole, exposing the backlight, +which means that it glows. You should cover it up. + +The system does get a bit hotter compared to when running the original +firmware. It is certainly hotter than an X60/T60. The heat issues have +been partially fixed by the following patch (now merged in libreboot): +. + +**The MacBook2,1 comes with a webcam, which does not work without +proprietary software. Also, webcams are a security risk; cover it up! Or +remove it.** + +A user reported that they could get better response from the touchpad +with the following in their xorg.conf: + + Section "InputClass" + Identifier "Synaptics Touchpad" + Driver "synaptics" + MatchIsTouchpad "on" + MatchDevicePath "/dev/input/event*" + Driver "synaptics" + # The next two values determine how much pressure one needs + # for tapping, moving the cursor and other events. + Option "FingerLow" "10" + Option "FingerHigh" "15" + # Do not emulate mouse buttons in the touchpad corners. + Option "RTCornerButton" "0" + Option "RBCornerButton" "0" + Option "LTCornerButton" "0" + Option "LBCornerButton" "0" + # One finger tap = left-click + Option "TapButton1" "1" + # Two fingers tap = right-click + Option "TapButton2" "3" + # Three fingers tap = middle-mouse + Option "TapButton3" "2" + # Try to not count the palm of the hand landing on the touchpad + # as a tap. Not sure if helps. + Option "PalmDetect" "1" + # The following modifies how long and how fast scrolling continues + # after lifting the finger when scrolling + Option "CoastingSpeed" "20" + Option "CoastingFriction" "200" + # Smaller number means that the finger has to travel less distance + # for it to count as cursor movement. Larger number prevents cursor + # shaking. + Option "HorizHysteresis" "10" + Option "VertHysteresis" "10" + # Prevent two-finger scrolling. Very jerky movement + Option "HorizTwoFingerScroll" "0" + Option "VertTwoFingerScroll" "0" + # Use edge scrolling + Option "HorizEdgeScroll" "1" + Option "VertEdgeScroll" "1" + EndSection + +A user reported that the above is only for linux kernel 3.15 or lower. +For newer kernels, the touchpad works fine out of the box, except middle +tapping. + +A user submitted a utility to enable 3-finger tap on this laptop. It\'s +available at *resources/utilities/macbook21-three-finger-tap* in the +libreboot git repository. + +[Back to top of page.](#pagetop) + +

+ +

+ +Copyright © 2014, 2015, 2016 Leah Rowe <info@minifree.org>\ +Permission is granted to copy, distribute and/or modify this document +under the terms of the Creative Commons Attribution-ShareAlike 4.0 +International license or any later version published by Creative +Commons; A copy of the license can be found at +[../cc-by-sa-4.0.txt](../cc-by-sa-4.0.txt) + +Updated versions of the license (when available) can be found at + + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT +POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND +AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND +CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, +OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, +ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE +OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF +WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT +APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU +ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR +OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, +PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES +ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN +IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, +COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT +ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above +shall be interpreted in a manner that, to the extent possible, most +closely approximates an absolute disclaimer and waiver of all liability. + +

diff --git a/docs/hcl/kcma-d8.html b/docs/hcl/kcma-d8.html deleted file mode 100644 index 05b42ce9..00000000 --- a/docs/hcl/kcma-d8.html +++ /dev/null @@ -1,186 +0,0 @@ - - - - - - - - - ASUS KCMA-D8 desktop/workstation board - - - - -

ASUS KCMA-D8 desktop/workstation board

- -

- This is a desktop board using AMD hardware (Fam10h and Fam15h CPUs available). It can also be used - for building a high-powered workstation. Powered by libreboot. The coreboot port was done by - Timothy Pearson of Raptor Engineering Inc. and, - working with them, merged into libreboot. -

- -

- Memory initialization is still problematic, for some modules. We recommend avoiding Kingston modules. -

- -

- Flashing instructions can be found at ../install/#flashrom - - note that external flashing is required (e.g. BBB), if the proprietary (ASUS) firmware is currently installed. - If you already have libreboot, by default it is possible to re-flash using software running in GNU+Linux - on the kcma-d8, without using external hardware. -

- -

- Back to previous index. -

- -

CPU compatibility

- Use Opteron 4200 series (works without microcode updates, including hw virt). - 4300 series needs microcode updates, so avoid those CPUs. 4100 series is too old, and mostly untested. -

- -

Board status (compatibility)

- See https://raptorengineeringinc.com/coreboot/kcma-d8-status.php. -

- -

Form factor

- These boards use the SSI EEB 3.61 form factor; make sure - that your case supports this. This form factor is similar - to E-ATX in that the size is identical, but the position of - the screws are different. -

- -

IPMI iKVM module add-on

- Don't use it. It uses proprietary firmware and adds a backdoor (remote out-of-band management chip, - similar to the Intel Management Engine. Fortunately, - the firmware is unsigned (possibly to replace) and physically separate from the mainboard since it's - on the add-on module, which you don't have to install. -

- -

Flash chips

- 2MiB flash chips are included by default, on these boards. It's on a P-DIP 8 slot (SPI chip). - The flash chip can be upgraded to higher sizes: 4MiB, 8MiB or 16MiB. With at least 8MiB, - you could feasibly fit a compressed linux+initramfs image (BusyBox+Linux system) into CBFS - and boot that, loading it into memory. -

- Libreboot has configs for 2, 4, 8 and 16 MiB flash chip sizes (default flash chip is 2MiB). -

- - DO NOT hot-swap the chip with your bare hands. Use a P-DIP 8 - chip extractor. These can be found online. - See http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools - -

- -

Native graphics initialization

- Only text-mode is known to work, but linux(kernel) can initialize - the framebuffer display (if it has KMS - kernel mode setting). -

- -

Current issues

LRDIMM memory modules are currently incompatible
- SAS (via PIKE 2008 module) requires non-free option ROM (and SeaBIOS) to boot from it - (theoretically possible to replace, but you can put a kernel in CBFS or on SATA - and use that to boot GNU, which can be on a SAS drive. The linux kernel can use - those SAS drives (via PIKE module) without an option ROM). -
- IPMI iKVM module (optional add-on card) uses proprietary firmware. Since it's for - remote out-of-band management, it's theoretically a backdoor similar to the Intel - Management Engine. Fortunately, unlike the ME, this firmware is unsigned which - means that a free replacement is theoretically possible. For now, the libreboot project - recommends not installing the module. This project - might be interesting to derive from, for those who want to work on a free replacement. - In practise, out-of-band management isn't very useful anyway (or at the very least, - it's not a major inconvenience to not have it). -
Graphics: only text-mode works. See #graphics

- -

Hardware specifications

- Check the ASUS website. -

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- - - - diff --git a/docs/hcl/kcma-d8.md b/docs/hcl/kcma-d8.md new file mode 100644 index 00000000..0e57a659 --- /dev/null +++ b/docs/hcl/kcma-d8.md @@ -0,0 +1,170 @@ +

+ +ASUS KCMA-D8 desktop/workstation board {#pagetop} +====================================== + +This is a desktop board using AMD hardware (Fam10h **and Fam15h** CPUs +available). It can also be used for building a high-powered workstation. +Powered by libreboot. The coreboot port was done by Timothy Pearson of +Raptor Engineering Inc. and, working with them, merged into libreboot. + +**Memory initialization is still problematic, for some modules. We +recommend avoiding Kingston modules.** + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) - note that external +flashing is required (e.g. BBB), if the proprietary (ASUS) firmware is +currently installed. If you already have libreboot, by default it is +possible to re-flash using software running in GNU+Linux on the kcma-d8, +without using external hardware. + +[Back to previous index](./). + +

+ +

+ +CPU compatibility +================= + +**Use Opteron 4200 series (works without microcode updates, including hw +virt).** 4300 series needs microcode updates, so avoid those CPUs. 4100 +series is too old, and mostly untested. + +

+ +

+ +Board status (compatibility) {#boardstatus} +============================ + +See . + +

+ +

+ +Form factor {#formfactor} +=========== + +These boards use the SSI EEB 3.61 form factor; make sure that your case +supports this. This form factor is similar to E-ATX in that the size is +identical, but the position of the screws are different. + +

+ +

+ +IPMI iKVM module add-on {#ipmi} +======================= + +Don\'t use it. It uses proprietary firmware and adds a backdoor (remote +out-of-band management chip, similar to the [Intel Management +Engine](http://libreboot.org/faq/#intelme). Fortunately, the firmware is +unsigned (possibly to replace) and physically separate from the +mainboard since it\'s on the add-on module, which you don\'t have to +install. + +

+ +

+ +Flash chips {#flashchips} +=========== + +2MiB flash chips are included by default, on these boards. It\'s on a +P-DIP 8 slot (SPI chip). The flash chip can be upgraded to higher sizes: +4MiB, 8MiB or 16MiB. With at least 8MiB, you could feasibly fit a +compressed linux+initramfs image (BusyBox+Linux system) into CBFS and +boot that, loading it into memory. + +Libreboot has configs for 2, 4, 8 and 16 MiB flash chip sizes (default +flash chip is 2MiB). + +**DO NOT hot-swap the chip with your bare hands. Use a P-DIP 8 chip +extractor. These can be found online. See +** + +

+ +

+ +Native graphics initialization {#graphics} +============================== + +Only text-mode is known to work, but linux(kernel) can initialize the +framebuffer display (if it has KMS - kernel mode setting). + +

+ +

+ +Current issues {#issues} +============== + +- LRDIMM memory modules are currently incompatible +- SAS (via PIKE 2008 module) requires non-free option ROM (and + SeaBIOS) to boot from it (theoretically possible to replace, but you + can put a kernel in CBFS or on SATA and use that to boot GNU, which + can be on a SAS drive. The linux kernel can use those SAS drives + (via PIKE module) without an option ROM). +- IPMI iKVM module (optional add-on card) uses proprietary firmware. + Since it\'s for remote out-of-band management, it\'s theoretically a + backdoor similar to the Intel Management Engine. Fortunately, unlike + the ME, this firmware is unsigned which means that a free + replacement is theoretically possible. For now, the libreboot + project recommends not installing the module. [This + project](https://github.com/facebook/openbmc) might be interesting + to derive from, for those who want to work on a free replacement. In + practise, out-of-band management isn\'t very useful anyway (or at + the very least, it\'s not a major inconvenience to not have it). +- Graphics: only text-mode works. See [\#graphics](#graphics) + +

+ +

+ +Hardware specifications {#specifications} +----------------------- + +Check the ASUS website. + +

+ +

diff --git a/docs/hcl/kfsn4-dre.html b/docs/hcl/kfsn4-dre.html deleted file mode 100644 index 17ad8d31..00000000 --- a/docs/hcl/kfsn4-dre.html +++ /dev/null @@ -1,164 +0,0 @@ - - - - - - - - - ASUS KFSN4-DRE server/workstation board - - - - -

ASUS KFSN4-DRE server/workstation board

- -

- This is a server board using AMD hardware (Fam10h). It can also be used - for building a high-powered workstation. Powered by libreboot. -

- -

- Flashing instructions can be found at ../install/#flashrom -

- -

- Back to previous index. -

- -

Form factor

- -

Flash chips

- These boards use LPC flash (not SPI), in a PLCC socket. The default flash size - 1MiB (8Mbits), and can be upgraded to 2MiB (16Mbits). - SST49LF080A is the default that the board uses. - SST49LF016C is an example of a 2MiB (16Mbits) chip, which might work. - It is believed that 2MiB (16Mbits) is the maximum size available for the flash chip. -

- - DO NOT hot-swap the chip with your bare hands. Use a PLCC - chip extractor. These can be found online. - See http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools - -

- -

Native graphics initialization

- Native graphics initialization exists (XGI Z9s) for this board. - Framebuffer- and text-mode both work. A serial port is also - available. -

- -

Memory

- DDR2 533/667 Registered ECC. 16 slots. Total capacity up to 64GiB. -

- -

Hex-core CPUs

- PCB revision 1.05G is the best version of this board (the - revision number will be printed on the board), because it - can use dual hex-core CPUs (Opteron 2400/8400 series). Other - revisions are believed to only support dual quad-core CPUs. -

- -

Current issues

- There seems to be a 30 second bootblock delay (observed by tpearson); - the system otherwise boots and works as expected. - See text/kfsn4-dre/bootlog.txt - - this uses the 'simple' bootblock, while tpearson uses the 'normal' - bootblock, which tpearson suspects may be a possible cause. - This person says that they will look into it. - This config doesn't have the issue. -
- Text-mode is a bit jittery (but still usable). (the jitter disappears - if using KMS, once the kernel starts. The jitter will remain, if - booting the kernel in text-mode). -

- -

Other information

- specifications -

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- - - - diff --git a/docs/hcl/kfsn4-dre.md b/docs/hcl/kfsn4-dre.md new file mode 100644 index 00000000..5f195ac9 --- /dev/null +++ b/docs/hcl/kfsn4-dre.md @@ -0,0 +1,139 @@ +

+ +ASUS KFSN4-DRE server/workstation board {#pagetop} +======================================= + +This is a server board using AMD hardware (Fam10h). It can also be used +for building a high-powered workstation. Powered by libreboot. + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +[Back to previous index](./). + +

+ +

+ +Flash chips {#flashchips} +=========== + +These boards use LPC flash (not SPI), in a PLCC socket. The default +flash size 1MiB (8Mbits), and can be upgraded to 2MiB (16Mbits). +SST49LF080A is the default that the board uses. SST49LF016C is an +example of a 2MiB (16Mbits) chip, which might work. It is believed that +2MiB (16Mbits) is the maximum size available for the flash chip. + +**DO NOT hot-swap the chip with your bare hands. Use a PLCC chip +extractor. These can be found online. See +** + +

+ +

+ +Native graphics initialization {#graphics} +============================== + +Native graphics initialization exists (XGI Z9s) for this board. +Framebuffer- and text-mode both work. A serial port is also available. + +

+ +

+ +Memory +====== + +DDR2 533/667 Registered ECC. 16 slots. Total capacity up to 64GiB. + +

+ +

+ +Hex-core CPUs {#hexcore} +============= + +PCB revision 1.05G is the best version of this board (the revision +number will be printed on the board), because it can use dual hex-core +CPUs (Opteron 2400/8400 series). Other revisions are believed to only +support dual quad-core CPUs. + +

+ +

+ +Current issues {#issues} +============== + +- There seems to be a 30 second bootblock delay (observed by + tpearson); the system otherwise boots and works as expected. See + [text/kfsn4-dre/bootlog.txt](text/kfsn4-dre/bootlog.txt) - this uses + the \'simple\' bootblock, while tpearson uses the \'normal\' + bootblock, which tpearson suspects may be a possible cause. This + person says that they will look into it. [This + config](http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asus/kfsn4-dre/4.0-10101-g039edeb/2015-06-27T03:59:16Z/config.txt;h=4742905c185a93fbda8eb14322dd82c70641aef0;hb=055f5df4e000a97453dfad6c91c2d06ea22b8545) + doesn\'t have the issue. +- Text-mode is a bit jittery (but still usable). (the jitter + disappears if using KMS, once the kernel starts. The jitter will + remain, if booting the kernel in text-mode). + +

+ +

+ +Other information +================= + +[specifications](ftp://ftp.sgi.com/public/Technical%20Support/Pdf%20files/Asus/kfsn4-dre.pdf) + +

+ +

diff --git a/docs/hcl/kgpe-d16.html b/docs/hcl/kgpe-d16.html deleted file mode 100644 index a1fdac40..00000000 --- a/docs/hcl/kgpe-d16.html +++ /dev/null @@ -1,310 +0,0 @@ - - - - - - - - - ASUS KGPE-D16 server/workstation board - - - - -

ASUS KGPE-D16 server/workstation board

- -

- This is a server board using AMD hardware (Fam10h and Fam15h CPUs available). It can also be used - for building a high-powered workstation. Powered by libreboot. The coreboot port was done by - Timothy Pearson of Raptor Engineering Inc. and, - working with them (and sponsoring the work), merged into libreboot. -

- - -

- Memory initialization is still problematic, for some modules. We recommend avoiding Kingston modules. -

- -

- Back to previous index. -

- -

CPU compatibility

- Use Opteron 6200 series (works without microcode updates, including hw virt). - 6300 series needs microcode updates, so avoid those CPUs. 6100 series is too old, and mostly untested. -

- -

Board status (compatibility)

- See https://raptorengineeringinc.com/coreboot/kgpe-d16-status.php. -

- -

Form factor

- -

IPMI iKVM module add-on

- -

Flash chips

- Libreboot has configs for 2, 4, 8 and 16 MiB flash chip sizes (default flash chip is 2MiB). -

- - DO NOT hot-swap the chip with your bare hands. Use a P-DIP 8 - chip extractor. These can be found online. - See http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools - -

- -

Native graphics initialization

- Only text-mode is known to work, but linux(kernel) can initialize - the framebuffer display (if it has KMS - kernel mode setting). -

- -

Current issues

LRDIMM memory modules are currently incompatible
- SAS (via PIKE 2008 module) requires non-free option ROM (and SeaBIOS) to boot from it - (theoretically possible to replace, but you can put a kernel in CBFS or on SATA - and use that to boot GNU, which can be on a SAS drive. The linux kernel can use - those SAS drives (via PIKE module) without an option ROM). -
- IPMI iKVM module (optional add-on card) uses proprietary firmware. Since it's for - remote out-of-band management, it's theoretically a backdoor similar to the Intel - Management Engine. Fortunately, unlike the ME, this firmware is unsigned which - means that a free replacement is theoretically possible. For now, the libreboot project - recommends not installing the module. This project - might be interesting to derive from, for those who want to work on a free replacement. - In practise, out-of-band management isn't very useful anyway (or at the very least, - it's not a major inconvenience to not have it). -
Graphics: only text-mode works. See #graphics

- -

Hardware specifications

- The information here is adapted, from the ASUS website. -

Processor / system bus

2 CPU sockets (G34 compatible)
HyperTransport™ Technology 3.0
- CPUs supported: -
- AMD Opteron 6100 series (Fam10h. No IOMMU support. Not recommended - old. View errata datasheet here: http://support.amd.com/TechDocs/41322_10h_Rev_Gd.pdf)
- AMD Opteron 6200 series (Fam15h, with full IOMMU support in libreboot - highly recommended - fast, and works well without microcode updates, including virtualization)
- AMD Opteron 6300 series (Fam15h, with full IOMMU support in libreboot. AVOID LIKE THE PLAGUE - virtualization is broken without microcode updates.
- - NOTE: 6300 series CPUs have buggy microcode built-in, and libreboot recommends avoiding the updates. The 6200 series CPUs have more reliable microcode. - Look at this errata datasheet: http://support.amd.com/TechDocs/48063_15h_Mod_00h-0Fh_Rev_Guide.pdf - (see Errata 734 - this is what kills the 6300 series) -
-
6.4 GT/s per link (triple link)

Core logic

AMD SR5690
AMD SP5100

Memory compatibility (with libreboot)

Total Slots: 16 (4-channel per CPU, 8 DIMM per CPU), ECC
Capacity: Maximum up to 256GB RDIMM
- Memory Type that is compatible: -
- DDR3 1600/1333/1066/800 UDIMM*
- DDR3 1600/1333/1066/800 RDIMM*
-
- Compatible sizes per memory module: -
- 16GB, 8GB, 4GB, 3GB, 2GB, 1GB RDIMM
- 8GB, 4GB, 2GB, 1GB UDIMM
-

Expansion slots

Total slot: 6
Slot Location 1: PCI 32bit/33MHz
Slot Location 2: PCI-E x16 (Gen2 X8 Link)
Slot Location 3: PCI-E x16 (Gen2 X16 Link), Auto switch to x8 link if slot 2 is occupied
Slot Location 4: PCI-E x8 (Gen2 X4 Link)
Slot Location 5: PCI-E x16 (Gen2 X16 Link)
Slot Location 6: PCI-E x16 (Gen2 X16 Link), Auto turn off if slot 5 is occupied, For 1U FH/FL Card, MIO supported
Additional Slot 1: PIKE slot (for SAS drives. See notes above)
Follow SSI Location#

Form factor

SSI EEB 3.61 (12"x13")

ASUS features

Fan Speed Control
Rack Ready (Rack and Pedestal dual use)

Storage

- SATA controller: -
- AMD SP5100
- 6 x SATA2 300MB/s
-
- SAS/SATA Controller: -
- ASUS PIKE2008 3Gbps 8-port SAS card included
-

Networking

2 x Intel® 82574L + 1 x Mgmt LAN

Graphics

Aspeed AST2050 with 8MB VRAM

On board I/O

1 x PSU Power Connector (24-pin SSI power connector + 8-pin SSI 12V + 8-pin SSI 12V power connector)
1 x Management Connector , Onboard socket for management card
3 x USB pin header , Up to 6 Devices
1 x Internal A Type USB Port
8 x Fan Header , 4pin (3pin/4pin fan dual support)
2 x SMBus
1 x Serial Port Header
1 x TPM header
1 x PS/2 KB/MS port

Back I/O ports

1 x External Serial Port
2 x External USB Port
1 x VGA Port
2 x RJ-45
1 x PS/2 KB/Mouse

Environment

Operation temperature: 10C ~ 35C
Non operation temperature: -40C ~ 70C
Non operation humidity: 20% ~ 90% ( Non condensing)

Monitoring

CPU temperatures
Fan speed (RPM)

Note:

* DDR3 1600 can only be supported with AMD Opteron 6300/6200 series processor

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- - - - diff --git a/docs/hcl/kgpe-d16.md b/docs/hcl/kgpe-d16.md new file mode 100644 index 00000000..1764026c --- /dev/null +++ b/docs/hcl/kgpe-d16.md @@ -0,0 +1,284 @@ +

+ +ASUS KGPE-D16 server/workstation board {#pagetop} +====================================== + +This is a server board using AMD hardware (Fam10h **and Fam15h** CPUs +available). It can also be used for building a high-powered workstation. +Powered by libreboot. The coreboot port was done by Timothy Pearson of +Raptor Engineering Inc. and, working with them (and sponsoring the +work), merged into libreboot. + +**Memory initialization is still problematic, for some modules. We +recommend avoiding Kingston modules.** + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) - note that external +flashing is required (e.g. BBB), if the proprietary (ASUS) firmware is +currently installed. If you already have libreboot, by default it is +possible to re-flash using software running in GNU+Linux on the +KGPE-D16, without using external hardware. + +[Back to previous index](./). + +

+ +

+ +CPU compatibility +================= + +**Use Opteron 6200 series (works without microcode updates, including hw +virt).** 6300 series needs microcode updates, so avoid those CPUs. 6100 +series is too old, and mostly untested. + +

+ +

+ +Board status (compatibility) {#boardstatus} +============================ + +See . + +

+ +

+ +Hardware specifications {#specifications} +----------------------- + +The information here is adapted, from the ASUS website. + +### Processor / system bus + +- 2 CPU sockets (G34 compatible) +- HyperTransport™ Technology 3.0 +- CPUs supported: + - AMD Opteron 6100 series (Fam10h. No IOMMU support. **Not** + recommended - old. View errata datasheet here: + ) + - AMD Opteron 6200 series (Fam15h, with full IOMMU support in + libreboot - **highly recommended - fast, and works well without + microcode updates, including virtualization**) + - AMD Opteron 6300 series (Fam15h, with full IOMMU support in + libreboot. **AVOID LIKE THE PLAGUE - virtualization is broken + without microcode updates.** + - NOTE: 6300 series CPUs have buggy microcode built-in, and + libreboot recommends avoiding the updates. The 6200 series CPUs + have more reliable microcode. Look at this errata datasheet: + + (see Errata 734 - this is what kills the 6300 series) +- 6.4 GT/s per link (triple link) + +### Core logic + +- AMD SR5690 +- AMD SP5100 + +### Memory compatibility (with libreboot) + +- **Total Slots:** 16 (4-channel per CPU, 8 DIMM per CPU), ECC +- **Capacity:** Maximum up to 256GB RDIMM +- **Memory Type that is compatible:** + - DDR3 1600/1333/1066/800 UDIMM\* + - DDR3 1600/1333/1066/800 RDIMM\* +- **Compatible sizes per memory module:** + - 16GB, 8GB, 4GB, 3GB, 2GB, 1GB RDIMM + - 8GB, 4GB, 2GB, 1GB UDIMM + +### Expansion slots + +- **Total slot:** 6 +- **Slot Location 1:** PCI 32bit/33MHz +- **Slot Location 2:** PCI-E x16 (Gen2 X8 Link) +- **Slot Location 3:** PCI-E x16 (Gen2 X16 Link), Auto switch to x8 + link if slot 2 is occupied +- **Slot Location 4:** PCI-E x8 (Gen2 X4 Link) +- **Slot Location 5:** PCI-E x16 (Gen2 X16 Link) +- **Slot Location 6:** PCI-E x16 (Gen2 X16 Link), Auto turn off if + slot 5 is occupied, For 1U FH/FL Card, MIO supported +- **Additional Slot 1:** PIKE slot (for SAS drives. See notes above) +- Follow SSI Location\# + +### Form factor {#form-factor} + +- SSI EEB 3.61 (12\"x13\") + +### ASUS features + +- Fan Speed Control +- Rack Ready (Rack and Pedestal dual use) + +### Storage + +- **SATA controller:** + - AMD SP5100 + - 6 x SATA2 300MB/s +- **SAS/SATA Controller:** + - ASUS PIKE2008 3Gbps 8-port SAS card included + +### Networking + +- 2 x Intel® 82574L + 1 x Mgmt LAN + +### Graphics + +- Aspeed AST2050 with 8MB VRAM + +### On board I/O + +- 1 x PSU Power Connector (24-pin SSI power connector + 8-pin SSI + 12V + 8-pin SSI 12V power connector) +- 1 x Management Connector , Onboard socket for management card +- 3 x USB pin header , Up to 6 Devices +- 1 x Internal A Type USB Port +- 8 x Fan Header , 4pin (3pin/4pin fan dual support) +- 2 x SMBus +- 1 x Serial Port Header +- 1 x TPM header +- 1 x PS/2 KB/MS port + +### Back I/O ports + +- 1 x External Serial Port +- 2 x External USB Port +- 1 x VGA Port +- 2 x RJ-45 +- 1 x PS/2 KB/Mouse + +### Environment + +- **Operation temperature:** 10C \~ 35C +- **Non operation temperature:** -40C \~ 70C +- **Non operation humidity:** 20% \~ 90% ( Non condensing) + +### Monitoring + +- CPU temperatures +- Fan speed (RPM) + +### Note: + +- \* DDR3 1600 can only be supported with AMD Opteron 6300/6200 series + processor + +

+ +

diff --git a/docs/hcl/r400.html b/docs/hcl/r400.html deleted file mode 100644 index cf948209..00000000 --- a/docs/hcl/r400.html +++ /dev/null @@ -1,158 +0,0 @@ - - - - - - - - - ThinkPad R400 - - - - -

ThinkPad R400

- -

- It is believed that all or most R400 laptops are compatible. - See notes about CPU compatibility for - potential incompatibilities. -

- -

- There are two possible flash chip sizes for the R400: 4MiB (32Mbit) or 8MiB (64Mbit). - This can be identified by the type of flash chip below the palmrest: 4MiB is SOIC-8, 8MiB - is SOIC-16. -

- -

- The R400 laptops come with the ME (and sometimes AMT in addition) before flashing libreboot. Libreboot disables and removes it - by using a modified descriptor: see gm45_remove_me.html (contains notes, plus - instructions) -

- -

- Flashing instructions can be found at ../install/#flashrom -

- -

- Back to previous index. -

- -

EC update

- -

- NOTE: this can only be done when you are using Lenovo BIOS. How to - update the EC firmware while running libreboot is unknown. - Libreboot only replaces the BIOS firmware, not EC. -

- Updated EC firmware has several advantages e.g. - bettery battery handling. -

- -

Compatibility (without blobs)

- -

Hardware virtualization (vt-x)

- The R400, when run without CPU microcode updates in coreboot, currently kernel panics - if running QEMU with vt-x enabled on 2 cores for the guest. With a single core enabled - for the guest, the guest panics (but the host is fine). Working around this in QEMU - might be possible; if not, software virtualization should work fine (it's just slower). -

- On GM45 hardware (with libreboot), make sure that the kvm and kvm_intel kernel modules - are not loaded, when using QEMU. -

- The following errata datasheet from Intel might help with investigation: - http://download.intel.com/design/mobile/specupdt/320121.pdf -

- -

- The R400 is almost identical to the X200, code-wise. See x200.html. -

- -

- TODO: put hardware register logs here like on the X200 and T400 page. -

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- - - diff --git a/docs/hcl/r400.md b/docs/hcl/r400.md new file mode 100644 index 00000000..51afdfdc --- /dev/null +++ b/docs/hcl/r400.md @@ -0,0 +1,121 @@ +

+ +ThinkPad R400 {#pagetop} +============= + +It is believed that all or most R400 laptops are compatible. See notes +about [CPU +compatibility](../install/r400_external.html#cpu_compatibility) for +potential incompatibilities. + +There are two possible flash chip sizes for the R400: 4MiB (32Mbit) or +8MiB (64Mbit). This can be identified by the type of flash chip below +the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. + +**The R400 laptops come with the ME (and sometimes AMT in addition) +before flashing libreboot. Libreboot disables and removes it by using a +modified descriptor: see [gm45\_remove\_me.html](gm45_remove_me.html)** +(contains notes, plus instructions) + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +[Back to previous index](./). + +

+ +

+ +EC update {#ecupdate} +========= + +It is recommended that you update to the latest EC firmware version. The +[EC firmware](https://libreboot.org/faq/#firmware-ec) is separate from +libreboot, so we don\'t actually provide that, but if you still have +Lenovo BIOS then you can just run the Lenovo BIOS update utility, which +will update both the BIOS and EC version. See: + +- +- + +NOTE: this can only be done when you are using Lenovo BIOS. How to +update the EC firmware while running libreboot is unknown. Libreboot +only replaces the BIOS firmware, not EC. + +Updated EC firmware has several advantages e.g. bettery battery +handling. + +

+ +

+ +Compatibility (without blobs) {#compatibility_noblobs} +----------------------------- + +

+ +### Hardware virtualization (vt-x) {#hwvirt} + +The R400, when run without CPU microcode updates in coreboot, currently +kernel panics if running QEMU with vt-x enabled on 2 cores for the +guest. With a single core enabled for the guest, the guest panics (but +the host is fine). Working around this in QEMU might be possible; if +not, software virtualization should work fine (it\'s just slower). + +On GM45 hardware (with libreboot), make sure that the *kvm* and +*kvm\_intel* kernel modules are not loaded, when using QEMU. + +The following errata datasheet from Intel might help with investigation: + + +

+ +

+ +The R400 is almost identical to the X200, code-wise. See +[x200.html](x200.html). + +TODO: put hardware register logs here like on the [X200](x200.html) and +[T400](t400.html) page. + +

+ +

diff --git a/docs/hcl/t400.html b/docs/hcl/t400.html deleted file mode 100644 index 56dfea24..00000000 --- a/docs/hcl/t400.html +++ /dev/null @@ -1,179 +0,0 @@ - - - - - - - - - ThinkPad T400 - - - - -

ThinkPad T400

- -

- It is believed that all or most T400 laptops are compatible. - See notes about CPU compatibility - for potential incompatibilities. -

- -

- There are two possible flash chip sizes for the T400: 4MiB (32Mbit) or 8MiB (64Mbit). - This can be identified by the type of flash chip below the palmrest: 4MiB is SOIC-8, 8MiB - is SOIC-16. -

- -

- The T400 laptops come with the ME (and sometimes AMT in addition) before flashing libreboot. Libreboot disables and removes it - by using a modified descriptor: see gm45_remove_me.html (contains notes, plus - instructions) -

- -

- Flashing instructions can be found at ../install/#flashrom -

- -

- Back to previous index. -

- -

EC update

- -

- NOTE: this can only be done when you are using Lenovo BIOS. How to - update the EC firmware while running libreboot is unknown. - Libreboot only replaces the BIOS firmware, not EC. -

- Updated EC firmware has several advantages e.g. - bettery battery handling. -

- -

Compatibility (without blobs)

- -

Hardware virtualization (vt-x)

- The T400, when run without CPU microcode updates in coreboot, currently kernel panics - if running QEMU with vt-x enabled on 2 cores for the guest. With a single core enabled - for the guest, the guest panics (but the host is fine). Working around this in QEMU - might be possible; if not, software virtualization should work fine (it's just slower). -

- On GM45 hardware (with libreboot), make sure that the kvm and kvm_intel kernel modules - are not loaded, when using QEMU. -

- The following errata datasheet from Intel might help with investigation: - http://download.intel.com/design/mobile/specupdt/320121.pdf -

- -

- The T400 is almost identical to the X200, code-wise. See x200.html. -

- -

Hardware register dumps

- -

- The coreboot wiki shows - how to collect various logs useful in porting to new - boards. Following are outputs from the T400: -

- -

- T400 with Winbond W25X64 flash chip (8MiB, SOIC-16) - and Lenovo BIOS 2.02 (EC firmware 1.01): -
- ../future/dumps/logs-t400-bios2.02-ec1.01/
-
- Version of flashrom used for the external flashing/reading logs is the one that libreboot git revision c164960 uses. -

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- - - diff --git a/docs/hcl/t400.md b/docs/hcl/t400.md new file mode 100644 index 00000000..ab1523f8 --- /dev/null +++ b/docs/hcl/t400.md @@ -0,0 +1,136 @@ +

+ +ThinkPad T400 {#pagetop} +============= + +It is believed that all or most T400 laptops are compatible. See notes +about [CPU +compatibility](../install/t400_external.html#cpu_compatibility) for +potential incompatibilities. + +There are two possible flash chip sizes for the T400: 4MiB (32Mbit) or +8MiB (64Mbit). This can be identified by the type of flash chip below +the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. + +**The T400 laptops come with the ME (and sometimes AMT in addition) +before flashing libreboot. Libreboot disables and removes it by using a +modified descriptor: see [gm45\_remove\_me.html](gm45_remove_me.html)** +(contains notes, plus instructions) + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +[Back to previous index](./). + +

+ +

+ +Compatibility (without blobs) {#compatibility_noblobs} +----------------------------- + +

+ +### Hardware virtualization (vt-x) {#hwvirt} + +The T400, when run without CPU microcode updates in coreboot, currently +kernel panics if running QEMU with vt-x enabled on 2 cores for the +guest. With a single core enabled for the guest, the guest panics (but +the host is fine). Working around this in QEMU might be possible; if +not, software virtualization should work fine (it\'s just slower). + +On GM45 hardware (with libreboot), make sure that the *kvm* and +*kvm\_intel* kernel modules are not loaded, when using QEMU. + +The following errata datasheet from Intel might help with investigation: + + +

+ +

+ +The T400 is almost identical to the X200, code-wise. See +[x200.html](x200.html). + +

+ +

+ +Hardware register dumps {#regdumps} +----------------------- + +The coreboot wiki +[shows](http://www.coreboot.org/Motherboard_Porting_Guide) how to +collect various logs useful in porting to new boards. Following are +outputs from the T400: + +- T400 with **Winbond W25X64** flash chip (8MiB, SOIC-16) and Lenovo + BIOS 2.02 (EC firmware 1.01): + - [../future/dumps/logs-t400-bios2.02-ec1.01/](../future/dumps/logs-t400-bios2.02-ec1.01/) +- Version of flashrom used for the external flashing/reading logs is + the one that libreboot git revision c164960 uses. + +

+ +

diff --git a/docs/hcl/t500.html b/docs/hcl/t500.html deleted file mode 100644 index b8d451eb..00000000 --- a/docs/hcl/t500.html +++ /dev/null @@ -1,209 +0,0 @@ - - - - - - - - - ThinkPad T500 - - - - -

ThinkPad T500

- -

- It is believed that all or most T500 laptops are compatible. - See notes about CPU compatibility - for potential incompatibilities. -

- -

- There are two possible flash chip sizes for the T500: 4MiB (32Mbit) or 8MiB (64Mbit). - This can be identified by the type of flash chip below the palmrest: 4MiB is SOIC-8, 8MiB - is SOIC-16. -

- -

- The T500 laptops come with the ME (and sometimes AMT in addition) before flashing libreboot. Libreboot disables and removes it - by using a modified descriptor: see gm45_remove_me.html (contains notes, plus - instructions) -

- -

- Flashing instructions can be found at ../install/#flashrom -

- -

- Back to previous index. -

- -

EC update

- -

- NOTE: this can only be done when you are using Lenovo BIOS. How to - update the EC firmware while running libreboot is unknown. - Libreboot only replaces the BIOS firmware, not EC. -

- Updated EC firmware has several advantages e.g. - bettery battery handling. -

- -

Compatibility (without blobs)

- -

Hardware virtualization (vt-x)

- The T500, when run without CPU microcode updates in coreboot, currently kernel panics - if running QEMU with vt-x enabled on 2 cores for the guest. With a single core enabled - for the guest, the guest panics (but the host is fine). Working around this in QEMU - might be possible; if not, software virtualization should work fine (it's just slower). -

- On GM45 hardware (with libreboot), make sure that the kvm and kvm_intel kernel modules - are not loaded, when using QEMU. -

- The following errata datasheet from Intel might help with investigation: - http://download.intel.com/design/mobile/specupdt/320121.pdf -

- -

- The T500 is almost identical to the X200, code-wise. See x200.html. -

- -

- Descriptor and Gbe differences -

- -

- See - ../future/dumps/t500_x200_descriptor/descriptor_diff_t500_x200.txt - and - ../future/dumps/t500_x200_descriptor/gbe_diff_t500_x200.txt -

- -

- The patches above are based on the output from ich9deblob on a factory.rom image dumped from the T500 - with a SOIC-8 4MiB flash chip. The patch re-creates the X200 descriptor/gbe source, so the commands were - something like:
- $ diff -u t500gbe x200gbe
- $ diff -u t500descriptor x200descriptor -

- -

- ME VSCC table is in a different place and a different size on the T500. Libreboot disables and removes the ME - anyway, so it doesn't matter. -

- -

- The very same descriptor/gbe used on the X200 (generated by ich9gen) - was re-used on the T500, and it still worked. -

- -

Hardware register dumps

- -

- The coreboot wiki shows - how to collect various logs useful in porting to new - boards. Following are outputs from the T500: -

- -

- T500 with Macronix MX25L3205D flash chip (4MiB, SOIC-8) - and Lenovo BIOS 3.13 7VET83WW (EC firmware 1.06): -
- ../future/dumps/t500log/
-

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- - - diff --git a/docs/hcl/t500.md b/docs/hcl/t500.md new file mode 100644 index 00000000..eebeccb1 --- /dev/null +++ b/docs/hcl/t500.md @@ -0,0 +1,160 @@ +

+ +ThinkPad T500 {#pagetop} +============= + +It is believed that all or most T500 laptops are compatible. See notes +about [CPU +compatibility](../install/t500_external.html#cpu_compatibility) for +potential incompatibilities. + +There are two possible flash chip sizes for the T500: 4MiB (32Mbit) or +8MiB (64Mbit). This can be identified by the type of flash chip below +the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. + +**The T500 laptops come with the ME (and sometimes AMT in addition) +before flashing libreboot. Libreboot disables and removes it by using a +modified descriptor: see [gm45\_remove\_me.html](gm45_remove_me.html)** +(contains notes, plus instructions) + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +[Back to previous index](./). + +

+ +

+ +Compatibility (without blobs) {#compatibility_noblobs} +----------------------------- + +

+ +### Hardware virtualization (vt-x) {#hwvirt} + +The T500, when run without CPU microcode updates in coreboot, currently +kernel panics if running QEMU with vt-x enabled on 2 cores for the +guest. With a single core enabled for the guest, the guest panics (but +the host is fine). Working around this in QEMU might be possible; if +not, software virtualization should work fine (it\'s just slower). + +On GM45 hardware (with libreboot), make sure that the *kvm* and +*kvm\_intel* kernel modules are not loaded, when using QEMU. + +The following errata datasheet from Intel might help with investigation: + + +

+ +

+ +The T500 is almost identical to the X200, code-wise. See +[x200.html](x200.html). + +

+ +

+ +Descriptor and Gbe differences {#descriptor_difference} +------------------------------ + +See +[../future/dumps/t500\_x200\_descriptor/descriptor\_diff\_t500\_x200.txt](../future/dumps/t500_x200_descriptor/descriptor_diff_t500_x200.txt) +and +[../future/dumps/t500\_x200\_descriptor/gbe\_diff\_t500\_x200.txt](../future/dumps/t500_x200_descriptor/gbe_diff_t500_x200.txt) + +The patches above are based on the output from ich9deblob on a +factory.rom image dumped from the T500 with a SOIC-8 4MiB flash chip. +The patch re-creates the X200 descriptor/gbe source, so the commands +were something like:\ +\$ **diff -u t500gbe x200gbe**\ +\$ **diff -u t500descriptor x200descriptor** + +ME VSCC table is in a different place and a different size on the T500. +Libreboot disables and removes the ME anyway, so it doesn\'t matter. + +The very same descriptor/gbe used on the X200 (generated by +[ich9gen](gm45_remove_me.html#ich9gen)) was re-used on the T500, and it +still worked. + +

+ +

+ +Hardware register dumps {#regdumps} +----------------------- + +The coreboot wiki +[shows](http://www.coreboot.org/Motherboard_Porting_Guide) how to +collect various logs useful in porting to new boards. Following are +outputs from the T500: + +- T500 with **Macronix MX25L3205D** flash chip (4MiB, SOIC-8) and + Lenovo BIOS 3.13 7VET83WW (EC firmware 1.06): + - [../future/dumps/t500log/](../future/dumps/t500log/) + +

+ +

diff --git a/docs/hcl/x200.html b/docs/hcl/x200.html deleted file mode 100644 index d5c8f528..00000000 --- a/docs/hcl/x200.html +++ /dev/null @@ -1,423 +0,0 @@ - - - - - - - - - ThinkPad X200 - - - - -

ThinkPad X200

- -

- It is believed that all X200 laptops are compatible. X200S and X200 Tablet will - also work, depending on the configuration. -

- It *might* be possible to put an X200 motherboard in an X201 chassis, though this is currently untested - by the libreboot project. The same may also apply between X200S and X201S; again, this is untested. - It's most likely true. -

- -

- There are two possible flash chip sizes for the X200: 4MiB (32Mbit) or 8MiB (64Mbit). - This can be identified by the type of flash chip below the palmrest: 4MiB is SOIC-8, 8MiB - is SOIC-16. -

- -

- The X200 laptops come with the ME (and sometimes AMT in addition) before flashing libreboot. Libreboot disables and removes it - by using a modified descriptor: see gm45_remove_me.html (contains notes, plus - instructions) -

- -

- Flashing instructions can be found at ../install/#flashrom -

- -

- Back to previous index. -

- -

EC update

- -

- NOTE: this can only be done when you are using Lenovo BIOS. How to - update the EC firmware while running libreboot is unknown. - Libreboot only replaces the BIOS firmware, not EC. -

- Updated EC firmware has several advantages e.g. - bettery battery handling. -

- -

Compatibility (without blobs)

- -

Hardware virtualization (vt-x)

- The X200, when run without CPU microcode updates in coreboot, currently kernel panics - if running QEMU with vt-x enabled on 2 cores for the guest. With a single core enabled - for the guest, the guest panics (but the host is fine). Working around this in QEMU - might be possible; if not, software virtualization should work fine (it's just slower). -

- On GM45 hardware (with libreboot), make sure that the kvm and kvm_intel kernel modules - are not loaded, when using QEMU. -

- The following errata datasheet from Intel might help with investigation: - http://download.intel.com/design/mobile/specupdt/320121.pdf -

- Anecdotal reports from at least 1 user suggests that some models with CPU microcode 1067a (on the CPU itself) might work with vt-x in libreboot. -

- -

X200S and X200 Tablet.

- -

- X200S and X200 Tablet have raminit issues at the time of writing - (GS45 chipset. X200 uses GM45). -

- -

- X200S and X200 Tablet are known to work, but only with certain CPU+RAM configurations. - The current stumbling block is RCOMP and SFF, mentioned in - https://www.cs.cmu.edu/~410/doc/minimal_boot.pdf. -

- The issues mostly relate to raminit (memory initialization). With an - unpatched coreboot, you get the following: text/x200s/cblog00.txt. - No SODIMM combination that was tested would work. At first glance, it looks - like GS45 (chipset that X200S uses. X200 uses GM45) is unsupported, but - there is a workaround that can be used to make certain models of the X200S - work, depending on the RAM. -

- The datasheet for GS45 describes two modes: low-performance and - high-performance. Low performance uses the SU range of ultra-low - voltage procesors (SU9400, for example), and high-performance uses the - SL range of processors (SL9400, for example). According to datasheets, - GS45 behaves very similarly to GM45 when operating in high-performance - mode. -

- The theory then was that you could simply remove - the checks in coreboot and make it pass GS45 off as GM45; the idea is - that, with a high-performance mode CPU (SL9400, for example) it would - just boot up and work. -

- This suspicion was confirmed with the following log: - text/x200s/cblog01.txt. - The memory modules in this case are 2x4GB. ~~However, not all - configurations work: text/x200s/cblog02.txt (2x2GB) - and text/x200s/cblog03.txt (1x2GB) - show a failed bootup.~~ False alarm. The modules were mixed (non-matching). X200S - with high-performance mode CPU will work so long as you use matching memory modules - (doesn't matter what size). -

- This was then pushed as a patch for coreboot, which can be found at - http://review.coreboot.org/#/c/7786/ - (libreboot merges this patch in coreboot-libre now. Check the 'getcb' script in - src or git). -

- -

Proper GS45 raminit

- A new northbridge gs45 should be added to coreboot, based on gm45, - and a new port x200st (X200S and X200T) should be added based on - the x200 port. -

- This port would have proper raminit. Alternatively, gs45 (if - raminit is taken to be the only issue with it) can be part of - gm45 northbridge support (and X200S/Tablet being part of the X200 - port) with conditional checks in the raminit that make raminit - work differently (as required) for GS45. nico_h and pgeorgi/patrickg - in the coreboot IRC channel should know more about raminit on gm45 - and likely gs45. -

- pgeorgi recommends to run SerialICE on the factory BIOS (for X200S), - comparing it with X200 (factory BIOS) and X200 (gm45 raminit code - in coreboot), to see what the differences are. Then tweak raminit - code based on that. -

- -

Trouble undocking (button doesn't work)

- -

- This person seems to have a workaround: - https://github.com/the-unconventional/libreboot-undock -

- -

LCD compatibility list

- -

- LCD panel list (X200 panels listed there): - http://www.thinkwiki.org/wiki/TFT_display -

- -

- All LCD panels for the X200, X200S and X200 Tablet are known to work. -

- -

- Back to top of page. -

- -

- AFFS/IPS panels -

X200

- Adapted from https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-X200 -

- Look at wikipedia for difference between TN and IPS panels. IPS have much better colour/contrast than - a regular TN, and will typically have good viewing angles. -

- These seem to be from the X200 tablet. You need to find one without the glass touchscreen protection on it - (might be able to remove it, though). It also must not have a digitizer on it (again, might be possible to - just simply remove the digitizer). -

BOE-Hydis HV121WX4-120, HV121WX4-110 or HV121WX4-100 - cheap-ish, might be hard to find
Samsung LTN121AP02-001 - common to find, cheap

- If your X200 has an LED backlit panel in it, then you also need to get an inverter and harness cable - that is compatible with the CCFL panels. To see which panel type you have, see - #led_howtotell. If you need the inverter/cable, here are part numbers: - 44C9909 for CCFL LVDS cable with bluetooth and camera connections, and 42W8009 or 42W8010 for the - inverter. -

- There are glossy and matte versions of these. Matte means anti-glare, which is what you want (in this authors opinion). -

- Refer to the HMM (hardware maintenance manual) for how to replace the screen. -

Sources:

X200S

- http://forum.thinkpads.com/viewtopic.php?p=618928#p618928 - explains that the X200S screens/assemblies are thinner. You need to replace the whole lid with one from a normal X200/X201. -

- -

- Back to top of page. -

- -

How to tell if it has an LED or CCFL?

- -

- Some X200s have a CCFL backlight and some have an LED backlight, in their LCD panel. This - also means that the inverters will vary, so you must be careful if ever replacing either - the panel and/or inverter. (a CCFL inverter is high-voltage and will destroy an LED backlit panel). -

- CCFLs contain mercury. An X200 with a CCFL backlight will (unless it has been changed to an LED, - with the correct inverter. Check with your supplier!) the following: "This product - contains Lithium Ion Battery, Lithium Battery and a lamp which contains mercury; dispose according to - local, state or federal laws" (one with an LED backlit panel will say something different). -

- Back to top of page. -

- -

Hardware register dumps

- -

- The coreboot wiki shows - how to collect various logs useful in porting to new - boards. Following are outputs from the X200: -

- -

- BIOS 3.15, EC 1.06 -
- hwdumps/x200/
-

- -

RAM, S3 and microcode updates

- -

- Not all memory modules work. Most of the default ones do, but you have to be careful - when upgrading to 8GiB; some modules work, some don't. -

- -

- Someone on reddit also did their own research on RAM compatibility: - on this post -

- -

- This page might be useful for RAM compatibility info - (note: coreboot raminit is different, so this page might be BS) -

- -

- pehjota started collecting some steppings for different CPUs on several X200 laptops. - You can get the CPUID by running:
- $ dmesg | sed -n 's/^.* microcode: CPU0 sig=0x$[^,]*$,.*$/\1/p' -

- -

- What pehjota wrote: - The laptops that have issues resuming from suspend, as well as a laptop that (as I mentioned earlier in #libreboot) won't boot with any Samsung DIMMs, all have CPUID 0x10676 (stepping M0). -

- -

- What pehjota wrote: - Laptops with CPUID 0x167A (stepping R0) resume properly every time and work with Samsung DIMMs. I'll - need to do more testing on more units to better confirm these trends, but it looks like the M0 microcode - is very buggy. That would also explain why I didn't have issues with Samsung DIMMs with the Lenovo BIOS - (which would have microcode updates). I wonder if VT-x works on R0. -

- -

- What pehjota wrote: - As I said, 10676 is M0 and 1067A is R0; those are the two CPUIDs and steppings for Intel Core 2 Duo P8xxx CPUs with factory microcode. (1067 is the family and model, and 6 or A is the stepping ID.) -

- -

- - TODO: check the CPUIDs and test S3 resume and/or KVM on any C2D systems (including non-P8xxx ones, which I don't have here) you have available. I'd be curious if you could confirm these results. - - It might not be coreboot that's buggy with raminit/S3; it might just be down to the microcode updates. -

- -

Unsorted notes

- -

-<sgsit> do you know if it's possible to flash thinkpads over the LPC debug connector at the front edge?
-<sgsit> that would make life much easier for systems like this
-<sgsit> all the Wistron manufactured systems have this thing called a "golden finger", normally at the front edge of the board
-<sgsit> you can plug a board in which gives diagnostic codes but i'm wondering whether it is capable of more
-<sgsit> http://www.endeer.cz/bios.tools/bios.html
-

- -

- Copyright © 2014, 2015 Leah Rowe <info@minifree.org>
- Copyright © 2015 Patrick "P. J." McDermott <pj@pehjota.net>
- Permission is granted to copy, distribute and/or modify this document - under the terms of the Creative Commons Attribution-ShareAlike 4.0 International license - or any later version published by Creative Commons; - - A copy of the license can be found at ../cc-by-sa-4.0.txt -

- -

- Updated versions of the license (when available) can be found at - https://creativecommons.org/licenses/by-sa/4.0/legalcode -

- -

- - - diff --git a/docs/hcl/x200.md b/docs/hcl/x200.md new file mode 100644 index 00000000..c559d275 --- /dev/null +++ b/docs/hcl/x200.md @@ -0,0 +1,363 @@ +

+ +ThinkPad X200 {#pagetop} +============= + +It is believed that all X200 laptops are compatible. X200S and X200 +Tablet will also work, [depending on the configuration](#x200s). + +It \*might\* be possible to put an X200 motherboard in an X201 chassis, +though this is currently untested by the libreboot project. The same may +also apply between X200S and X201S; again, this is untested. **It\'s +most likely true.** + +There are two possible flash chip sizes for the X200: 4MiB (32Mbit) or +8MiB (64Mbit). This can be identified by the type of flash chip below +the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. + +**The X200 laptops come with the ME (and sometimes AMT in addition) +before flashing libreboot. Libreboot disables and removes it by using a +modified descriptor: see [gm45\_remove\_me.html](gm45_remove_me.html)** +(contains notes, plus instructions) + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +[Back to previous index](./). + +

+ +

+ +Compatibility (without blobs) {#compatibility_noblobs} +----------------------------- + +

+ +### Hardware virtualization (vt-x) {#hwvirt} + +The X200, when run without CPU microcode updates in coreboot, currently +kernel panics if running QEMU with vt-x enabled on 2 cores for the +guest. With a single core enabled for the guest, the guest panics (but +the host is fine). Working around this in QEMU might be possible; if +not, software virtualization should work fine (it\'s just slower). + +On GM45 hardware (with libreboot), make sure that the *kvm* and +*kvm\_intel* kernel modules are not loaded, when using QEMU. + +The following errata datasheet from Intel might help with investigation: + + +Anecdotal reports from at least 1 user suggests that some models with +CPU microcode 1067a (on the CPU itself) might work with vt-x in +libreboot. + +

+ +

+ +X200S and X200 Tablet. {#x200s} +---------------------- + +X200S and X200 Tablet have raminit issues at the time of writing (GS45 +chipset. X200 uses GM45). + +X200S and X200 Tablet are known to work, but only with certain CPU+RAM +configurations. The current stumbling block is RCOMP and SFF, mentioned +in . + +The issues mostly relate to raminit (memory initialization). With an +unpatched coreboot, you get the following: +[text/x200s/cblog00.txt](text/x200s/cblog00.txt). No SODIMM combination +that was tested would work. At first glance, it looks like GS45 (chipset +that X200S uses. X200 uses GM45) is unsupported, but there is a +workaround that can be used to make certain models of the X200S work, +depending on the RAM. + +The datasheet for GS45 describes two modes: low-performance and +high-performance. Low performance uses the SU range of ultra-low voltage +procesors (SU9400, for example), and high-performance uses the SL range +of processors (SL9400, for example). According to datasheets, GS45 +behaves very similarly to GM45 when operating in high-performance mode. + +The theory then was that you could simply remove the checks in coreboot +and make it pass GS45 off as GM45; the idea is that, with a +high-performance mode CPU (SL9400, for example) it would just boot up +and work. + +This suspicion was confirmed with the following log: +[text/x200s/cblog01.txt](text/x200s/cblog01.txt). The memory modules in +this case are 2x4GB. ~~**However, not all configurations work: +[text/x200s/cblog02.txt](text/x200s/cblog02.txt) (2x2GB) and +[text/x200s/cblog03.txt](text/x200s/cblog03.txt) (1x2GB) show a failed +bootup.**~~ *False alarm. The modules were mixed (non-matching). X200S +with high-performance mode CPU will work so long as you use matching +memory modules (doesn\'t matter what size).* + +This was then pushed as a patch for coreboot, which can be found at + (libreboot merges this patch in +coreboot-libre now. Check the \'getcb\' script in src or git). + +

+ +### Proper GS45 raminit {#x200s_raminit} + +A new northbridge gs45 should be added to coreboot, based on gm45, and a +new port x200st (X200S and X200T) should be added based on the x200 +port. + +This port would have proper raminit. Alternatively, gs45 (if raminit is +taken to be the only issue with it) can be part of gm45 northbridge +support (and X200S/Tablet being part of the X200 port) with conditional +checks in the raminit that make raminit work differently (as required) +for GS45. nico\_h and pgeorgi/patrickg in the coreboot IRC channel +should know more about raminit on gm45 and likely gs45. + +pgeorgi recommends to run SerialICE on the factory BIOS (for X200S), +comparing it with X200 (factory BIOS) and X200 (gm45 raminit code in +coreboot), to see what the differences are. Then tweak raminit code +based on that. + +

+ +

+ +Trouble undocking (button doesn\'t work) +---------------------------------------- + +This person seems to have a workaround: + + +

+ +

+ +LCD compatibility list {#lcd_supported_list} +---------------------- + +LCD panel list (X200 panels listed there): + + +All LCD panels for the X200, X200S and X200 Tablet are known to work. + +[Back to top of page.](#pagetop) + +

+ +### AFFS/IPS panels {#ips} + +#### X200 + +Adapted from + + +Look at wikipedia for difference between TN and IPS panels. IPS have +much better colour/contrast than a regular TN, and will typically have +good viewing angles. + +These seem to be from the X200 tablet. You need to find one without the +glass touchscreen protection on it (might be able to remove it, though). +It also must not have a digitizer on it (again, might be possible to +just simply remove the digitizer). + +- BOE-Hydis HV121WX4-120, HV121WX4-110 or HV121WX4-100 - cheap-ish, + might be hard to find +- Samsung LTN121AP02-001 - common to find, cheap + +**If your X200 has an LED backlit panel in it, then you also need to get +an inverter and harness cable that is compatible with the CCFL panels. +To see which panel type you have, see +[\#led\_howtotell](#led_howtotell). If you need the inverter/cable, here +are part numbers: 44C9909 for CCFL LVDS cable with bluetooth and camera +connections, and 42W8009 or 42W8010 for the inverter.** + +There are glossy and matte versions of these. Matte means anti-glare, +which is what you want (in this authors opinion). + +Refer to the HMM (hardware maintenance manual) for how to replace the +screen. + +Sources: + +- [ThinkPad Forums - Matte AFFS Panel on + X200](http://forum.thinkpads.com/viewtopic.php?f=2&t=84941) +- [ThinkPad Forums - Parts for X200 AFFS + Mod](http://forum.thinkpads.com/viewtopic.php?p=660662#p660662) +- [ThinkWiki.de - X200 + Displayumbau](http://thinkwiki.de/X200_Displayumbau) + +

+ +

+ +### X200S + + explains +that the X200S screens/assemblies are thinner. You need to replace the +whole lid with one from a normal X200/X201. + +

+ +[Back to top of page.](#pagetop) + +

+ +

+ +How to tell if it has an LED or CCFL? {#led_howtotell} +------------------------------------- + +Some X200s have a CCFL backlight and some have an LED backlight, in +their LCD panel. This also means that the inverters will vary, so you +must be careful if ever replacing either the panel and/or inverter. (a +CCFL inverter is high-voltage and will destroy an LED backlit panel). + +CCFLs contain mercury. An X200 with a CCFL backlight will (****unless it +has been changed to an LED, with the correct inverter. Check with your +supplier!) the following: *\"This product contains Lithium Ion Battery, +Lithium Battery and a lamp which contains mercury; dispose according to +local, state or federal laws\"* (one with an LED backlit panel will say +something different). + +[Back to top of page.](#pagetop) + +

+ +

+ +RAM, S3 and microcode updates {#ram_s3_microcode} +============================= + +Not all memory modules work. Most of the default ones do, but you have +to be careful when upgrading to 8GiB; some modules work, some don\'t. + +Someone on reddit also did their own research on RAM compatibility: [on +this +post](https://www.reddit.com/r/libreboot/comments/5ax17e/liberated_x200_is_really_picky_with_memory/) + +[This page](http://www.forum.thinkpads.com/viewtopic.php?p=760721) might +be useful for RAM compatibility info (note: coreboot raminit is +different, so this page might be BS) + +pehjota started collecting some steppings for different CPUs on several +X200 laptops. You can get the CPUID by running:\ +\$ **dmesg | sed -n \'s/\^.\* microcode: CPU0 +sig=0x\$\[\^,\]\*\$,.\*\$/\\1/p\'** + +What pehjota wrote: The laptops that have issues resuming from suspend, +as well as a laptop that (as I mentioned earlier in \#libreboot) won\'t +boot with any Samsung DIMMs, all have CPUID 0x10676 (stepping M0). + +What pehjota wrote: Laptops with CPUID 0x167A (stepping R0) resume +properly every time and work with Samsung DIMMs. I\'ll need to do more +testing on more units to better confirm these trends, but it looks like +the M0 microcode is very buggy. That would also explain why I didn\'t +have issues with Samsung DIMMs with the Lenovo BIOS (which would have +microcode updates). I wonder if VT-x works on R0. + +What pehjota wrote: As I said, 10676 is M0 and 1067A is R0; those are +the two CPUIDs and steppings for Intel Core 2 Duo P8xxx CPUs with +factory microcode. (1067 is the family and model, and 6 or A is the +stepping ID.) + +**TODO: check the CPUIDs and test S3 resume and/or KVM on any C2D +systems (including non-P8xxx ones, which I don\'t have here) you have +available. I\'d be curious if you could confirm these results.** It +might not be coreboot that\'s buggy with raminit/S3; it might just be +down to the microcode updates. + +

+ +

+ +Unsorted notes {#unsorted} +-------------- + + do you know if it's possible to flash thinkpads over the LPC debug connector at the front edge? + that would make life much easier for systems like this + all the Wistron manufactured systems have this thing called a "golden finger", normally at the front edge of the board + you can plug a board in which gives diagnostic codes but i'm wondering whether it is capable of more + http://www.endeer.cz/bios.tools/bios.html + +

+ +

+ +Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ +Copyright © 2015 Patrick \"P. J.\" McDermott <pj@pehjota.net>\ +Permission is granted to copy, distribute and/or modify this document +under the terms of the Creative Commons Attribution-ShareAlike 4.0 +International license or any later version published by Creative +Commons; A copy of the license can be found at +[../cc-by-sa-4.0.txt](../cc-by-sa-4.0.txt) + +Updated versions of the license (when available) can be found at + + +UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT +POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND +AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND +CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, +OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, +ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE +OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF +WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT +APPLY TO YOU. + +TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU +ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR +OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, +PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES +ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN +IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, +COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT +ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. + +The disclaimer of warranties and limitation of liability provided above +shall be interpreted in a manner that, to the extent possible, most +closely approximates an absolute disclaimer and waiver of all liability. + +

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