From 0f6ea1c9e0a25a9b7546f96f27cef8841f0d09b5 Mon Sep 17 00:00:00 2001 From: Libreboot Contributor Date: Wed, 18 Mar 2020 17:20:14 +0100 Subject: Creation of i18n folder containing translations of the libreboot project. Added french one, not finished. --- i18n/fr_FR/BUILD_HOWTO.md | 103 + i18n/fr_FR/COPYING | 674 ++ i18n/fr_FR/README.md | 32 + i18n/fr_FR/RELEASE | 92 + i18n/fr_FR/docs/$ | 1438 ++++ i18n/fr_FR/docs/bsd/freebsd.md | 150 + i18n/fr_FR/docs/bsd/index.md | 20 + i18n/fr_FR/docs/bsd/netbsd.md | 165 + i18n/fr_FR/docs/bsd/openbsd.md | 197 + i18n/fr_FR/docs/cc-by-sa-4.0.txt | 215 + i18n/fr_FR/docs/depthcharge/index.md | 176 + i18n/fr_FR/docs/fdl-1.3.md | 171 + .../docs/future/coreboot_native_3.12_bug.tar.gz | Bin 0 -> 583842 bytes .../docs/future/donotusethis_macbook_acpi.diff | 28 + i18n/fr_FR/docs/future/dumps/5320_7c0000_gma.c | 519 ++ i18n/fr_FR/docs/future/dumps/5885_logs.tar.gz | Bin 0 -> 111526 bytes i18n/fr_FR/docs/future/dumps/5885_logs_2.tar.gz | Bin 0 -> 105775 bytes i18n/fr_FR/docs/future/dumps/5927_2.tar.gz | Bin 0 -> 804125 bytes i18n/fr_FR/docs/future/dumps/5927_3.tar.gz | Bin 0 -> 287569 bytes i18n/fr_FR/docs/future/dumps/5927_5.tar.gz | Bin 0 -> 94223 bytes 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.../projects/coreboot/configs/nyan/dependencies | 2 + i18n/fr_FR/projects/coreboot/configs/nyan/ec | 1 + i18n/fr_FR/projects/coreboot/configs/nyan/targets | 2 + .../configs/qemu_i440fx_piix4/16MiB/config | 5 + .../qemu_i440fx_piix4/16MiB/corebootfb/config | 5 + .../qemu_i440fx_piix4/16MiB/corebootfb/grub/config | 1 + .../16MiB/corebootfb/grub/dependencies | 1 + .../16MiB/corebootfb/seabios/config | 1 + .../16MiB/corebootfb/seabios/dependencies | 1 + .../qemu_i440fx_piix4/16MiB/corebootfb/targets | 2 + .../configs/qemu_i440fx_piix4/16MiB/targets | 2 + .../qemu_i440fx_piix4/16MiB/textmode/config | 1 + .../qemu_i440fx_piix4/16MiB/textmode/grub/config | 1 + .../16MiB/textmode/grub/dependencies | 1 + .../16MiB/textmode/seabios/config | 1 + .../16MiB/textmode/seabios/dependencies | 1 + .../qemu_i440fx_piix4/16MiB/textmode/targets | 2 + .../coreboot/configs/qemu_i440fx_piix4/8MiB/config | 4 + .../qemu_i440fx_piix4/8MiB/corebootfb/config | 5 + .../qemu_i440fx_piix4/8MiB/corebootfb/grub/config | 1 + .../8MiB/corebootfb/grub/dependencies | 1 + .../8MiB/corebootfb/seabios/config | 1 + .../8MiB/corebootfb/seabios/dependencies | 1 + .../qemu_i440fx_piix4/8MiB/corebootfb/targets | 2 + .../configs/qemu_i440fx_piix4/8MiB/targets | 2 + .../configs/qemu_i440fx_piix4/8MiB/textmode/config | 1 + .../qemu_i440fx_piix4/8MiB/textmode/grub/config | 1 + .../8MiB/textmode/grub/dependencies | 1 + .../qemu_i440fx_piix4/8MiB/textmode/seabios/config | 1 + .../8MiB/textmode/seabios/dependencies | 1 + .../qemu_i440fx_piix4/8MiB/textmode/targets | 2 + .../coreboot/configs/qemu_i440fx_piix4/arch | 1 + .../coreboot/configs/qemu_i440fx_piix4/config | 585 ++ .../configs/qemu_i440fx_piix4/dependencies | 1 + .../coreboot/configs/qemu_i440fx_piix4/targets | 2 + .../coreboot/configs/qemu_q35_ich9/16MiB/config | 5 + .../configs/qemu_q35_ich9/16MiB/corebootfb/config | 5 + .../qemu_q35_ich9/16MiB/corebootfb/grub/config | 1 + .../16MiB/corebootfb/grub/dependencies | 1 + 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i18n/fr_FR/projects/coreboot/configs/t60/arch | 1 + i18n/fr_FR/projects/coreboot/configs/t60/config | 647 ++ .../projects/coreboot/configs/t60/dependencies | 1 + i18n/fr_FR/projects/coreboot/configs/t60/targets | 2 + i18n/fr_FR/projects/coreboot/configs/targets | 20 + i18n/fr_FR/projects/coreboot/configs/veyron/arch | 1 + .../projects/coreboot/configs/veyron/dependencies | 2 + .../coreboot/configs/veyron/jerry/16MiB/config | 5 + .../jerry/16MiB/corebootfb/depthcharge/config | 1 + .../16MiB/corebootfb/depthcharge/dependencies | 1 + .../configs/veyron/jerry/16MiB/corebootfb/targets | 1 + .../coreboot/configs/veyron/jerry/16MiB/targets | 1 + .../coreboot/configs/veyron/jerry/4MiB/config | 4 + .../jerry/4MiB/corebootfb/depthcharge/config | 1 + .../jerry/4MiB/corebootfb/depthcharge/dependencies | 1 + .../configs/veyron/jerry/4MiB/corebootfb/targets | 1 + .../coreboot/configs/veyron/jerry/4MiB/targets | 1 + .../projects/coreboot/configs/veyron/jerry/config | 732 ++ .../projects/coreboot/configs/veyron/jerry/ec | 1 + .../projects/coreboot/configs/veyron/jerry/targets | 2 + .../coreboot/configs/veyron/mickey/4MiB/config | 4 + .../mickey/4MiB/corebootfb/depthcharge/config | 1 + .../4MiB/corebootfb/depthcharge/dependencies | 1 + .../configs/veyron/mickey/4MiB/corebootfb/targets | 1 + .../coreboot/configs/veyron/mickey/4MiB/targets | 1 + .../projects/coreboot/configs/veyron/mickey/config | 715 ++ .../coreboot/configs/veyron/mickey/targets | 1 + .../coreboot/configs/veyron/minnie/16MiB/config | 5 + .../minnie/16MiB/corebootfb/depthcharge/config | 1 + .../16MiB/corebootfb/depthcharge/dependencies | 1 + .../configs/veyron/minnie/16MiB/corebootfb/targets | 1 + .../coreboot/configs/veyron/minnie/16MiB/targets | 1 + .../coreboot/configs/veyron/minnie/4MiB/config | 4 + .../minnie/4MiB/corebootfb/depthcharge/config | 1 + .../4MiB/corebootfb/depthcharge/dependencies | 1 + .../configs/veyron/minnie/4MiB/corebootfb/targets | 1 + .../coreboot/configs/veyron/minnie/4MiB/targets | 1 + .../projects/coreboot/configs/veyron/minnie/config | 732 ++ .../projects/coreboot/configs/veyron/minnie/ec | 1 + .../coreboot/configs/veyron/minnie/targets | 2 + .../coreboot/configs/veyron/speedy/16MiB/config | 5 + .../speedy/16MiB/corebootfb/depthcharge/config | 1 + .../16MiB/corebootfb/depthcharge/dependencies | 1 + .../configs/veyron/speedy/16MiB/corebootfb/targets | 1 + .../coreboot/configs/veyron/speedy/16MiB/targets | 1 + .../coreboot/configs/veyron/speedy/4MiB/config | 4 + .../speedy/4MiB/corebootfb/depthcharge/config | 1 + .../4MiB/corebootfb/depthcharge/dependencies | 1 + .../configs/veyron/speedy/4MiB/corebootfb/targets | 1 + .../coreboot/configs/veyron/speedy/4MiB/targets | 1 + .../projects/coreboot/configs/veyron/speedy/config | 732 ++ .../projects/coreboot/configs/veyron/speedy/ec | 1 + .../coreboot/configs/veyron/speedy/targets | 2 + .../fr_FR/projects/coreboot/configs/veyron/targets | 4 + i18n/fr_FR/projects/coreboot/configs/w500 | 1 + .../projects/coreboot/configs/x200/16MiB/config | 6 + .../coreboot/configs/x200/16MiB/corebootfb/config | 3 + .../configs/x200/16MiB/corebootfb/grub/config | 1 + .../x200/16MiB/corebootfb/grub/dependencies | 1 + .../configs/x200/16MiB/corebootfb/seabios/config | 1 + .../x200/16MiB/corebootfb/seabios/dependencies | 1 + .../coreboot/configs/x200/16MiB/corebootfb/targets | 2 + .../projects/coreboot/configs/x200/16MiB/targets | 2 + .../coreboot/configs/x200/16MiB/textmode/config | 1 + .../configs/x200/16MiB/textmode/grub/config | 1 + .../configs/x200/16MiB/textmode/grub/dependencies | 1 + .../configs/x200/16MiB/textmode/seabios/config | 1 + .../x200/16MiB/textmode/seabios/dependencies | 1 + .../coreboot/configs/x200/16MiB/textmode/targets | 2 + .../projects/coreboot/configs/x200/4MiB/config | 6 + .../coreboot/configs/x200/4MiB/corebootfb/config | 3 + .../configs/x200/4MiB/corebootfb/grub/config | 1 + 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i18n/fr_FR/projects/cros-ec/configs/tools/revision | 1 + i18n/fr_FR/projects/cros-ec/configs/veyron/install | 2 + .../projects/cros-ec/configs/veyron/jerry/config | 1 + .../cros-ec/configs/veyron/jerry/dependencies | 1 + .../projects/cros-ec/configs/veyron/minnie/config | 1 + .../cros-ec/configs/veyron/minnie/dependencies | 1 + .../fr_FR/projects/cros-ec/configs/veyron/revision | 1 + .../projects/cros-ec/configs/veyron/speedy/config | 1 + .../cros-ec/configs/veyron/speedy/dependencies | 1 + i18n/fr_FR/projects/cros-ec/configs/veyron/targets | 3 + i18n/fr_FR/projects/cros-ec/cros-ec | 138 + i18n/fr_FR/projects/cros-ec/cros-ec-helper | 22 + .../0001-use-_DEFAULT_SOURCE-for-newer-glibc.patch | 53 + ...nforce-compilation-without-system-headers.patch | 27 + ...re-functions-inline-that-aren-t-always-de.patch | 28 + ...e-assembly-exception-handler-and-routine-.patch | 230 + ...-a-clang-warning-by-use-a-unused-variable.patch | 38 + .../0002-use-_DEFAULT_SOURCE-for-newer-glibc.patch | 53 + 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i18n/fr_FR/www/logo/stickers/libreboot-simple-bold-5.08cmx5.72cm-diecut.svg create mode 100644 i18n/fr_FR/www/management.md create mode 100644 i18n/fr_FR/www/news-list.md create mode 100644 i18n/fr_FR/www/news/.unity.md.swp create mode 100644 i18n/fr_FR/www/news/MANIFEST create mode 100644 i18n/fr_FR/www/news/alyssa-resignation.md create mode 100644 i18n/fr_FR/www/news/andrew-robbins-new-maintainer.md create mode 100644 i18n/fr_FR/www/news/formalised-structure.md create mode 100644 i18n/fr_FR/www/news/freenode2018-workshop.md create mode 100644 i18n/fr_FR/www/news/leah-fundraiser.md create mode 100644 i18n/fr_FR/www/news/lenovo-recall.md create mode 100644 i18n/fr_FR/www/news/libreplanet2018-workshop.md create mode 100644 i18n/fr_FR/www/news/libreplanet2019-workshop.md create mode 100644 i18n/fr_FR/www/news/new-mailing-lists.md create mode 100644 i18n/fr_FR/www/news/proposal-rejoin-gnu.md create mode 100644 i18n/fr_FR/www/news/release-testing-20171221.md create mode 100644 i18n/fr_FR/www/news/talos.md create mode 100644 i18n/fr_FR/www/news/unity.md create mode 100644 i18n/fr_FR/www/publish.sh create mode 100644 i18n/fr_FR/www/robots.txt create mode 100644 i18n/fr_FR/www/suppliers.md (limited to 'i18n') diff --git a/i18n/fr_FR/BUILD_HOWTO.md b/i18n/fr_FR/BUILD_HOWTO.md new file mode 100644 index 00000000..73d0cbde --- /dev/null +++ b/i18n/fr_FR/BUILD_HOWTO.md @@ -0,0 +1,103 @@ +# Système de build de Libreboot + + +## Point d'entrée + +Le point d'entrée du système de build de Libreboot est le script s'appelant "libreboot" dans le dossier racine . + +Éxecuter ce script sans arguments montrera comment l'utiliser de façon générale. + + +## Configuration + +Le système de build peut être configuré avec un fichier s'appelant "libreboot.conf" placé dans le dossier racine. + +L'usage typique de ce fichier est l'initialisation des variables d'environnements dont une liste est disponible dans la description de l'usage du point d'entrée. + +Puisque le système de build se sert de ce fichier après que les bibliothèques sont chargées, il peut être utilisé pour remplacer n'importe quelle de leurs fonctions ou variables. + + +## Projets et outils cibles + +Le système de build marche autour de concepts de projets et d'outils, qui défini les composants spécifiques qui peuvent être utilisé pour produire : +* des fichiers sources +* des systèmes +* des images +* des outils + +De nombreuses actions sont disponibles pour chaque projet et outil cibles, beaucoup d'entre elles figurant dans l'aide du script principal. ? . Ces actions sont exécutés de façon récursives quand aucune cible est spécifiée. + +Chaque projet et outil cible à son propre dossier (soit dans [projets](https://git.miquellionel.ovh/lili/libreboot_fr/src/branch/master/projects) ou [tools](https://git.miquellionel.ovh/lili/libreboot_fr/src/branch/master/tools) ) contenant un script nommé après la cible et si possible un script d'aide ( nom du script+"-helper". +Le script d'aide est automatiquement inclus dans le système de build. +Le nom des fonctions dans le script d'aide sont généralement précédées du nom de la cible, les trait d'union étant rémplacé par "_". + +Chaque action d'un projet et outil cible sont les functions définis dans le script spécifique de la cible, avec des noms correspondant aux actions de la cible. + + +## Méta-cibles + +Les méta-cibles sont des outils et projets cible qui applique l'action demandée sur des cibles individuelles, permettant d'éxecuter une action sur plusiers cibles à la fois. Par example, une méta-cible nommée après le système de build avec un suffixe "-all" appelerait d'autre cibles, prefixé avec "-images", "-tools", etc qui performeront l'action demandée sur toutes les cibles sous-jacentes. + + +## Actions de projets + +De nombres actions génériques permettent la préparation de projets, à travers une série d'étapes : +* télécharger, extraire où mettre à jour la source du projet. +* construire le projet dans un dossier de construction +* installer le projet dans un dossier d'installation +* produire une version du projet dans un dossier de versions +* nettoyer les dossiers d'installation, de construction et de version + +Les actions peuvent être vérifiées par une fonction correspondante spécifique au projet, nommé après la fonction à vérifier avec le suffixe "_check" pour déterminer s'il est nécessaire ou non de les lancer de nouveau pour suivre les étapes. +Une variable d'environnement peut forcer les actions à être éxecutée, en spécifiant une liste de projets espacée : +PROJECTS_FORCE + + +## Configuration du projet et patchs + +La configuration pour chaque projet est stockée dans leur propre dossier. +Les cibles pour chaque projet sont définis par un fichier "targets" dans le dossier "configs". Les cibles sont lues de façon récursive, suivant les noms des sous dossiers pour les cibles du projet. + +Chaque dossier de configuration d'un projet peut être utilisé pour garder des informations et configurations propre la à la cible. + +Un fichier "install" dans chaque sous dossier indique quel fichier prendre depuis le fichier de build et où installer dans le dossier d'installation. + + +## Sources des projets + +Chaque projet peut soit télécharger des sources spécifiques ou soit utiliser les sources d'autres projets, apportant possiblement ses propres patchs et révisions. + +Les sources sont téléchargées avec l'action "download" ou peuvent être extraite depuis des sources versionnées ( après avoir placé les sources dans un dossier "source" ) avec l'action "extract". + +Les projets peuvent aussi garder leurs sources dans leur propre dossier de projet, dans un dossier nommé "sources". + + +## Installation des projets + +Les projets sont installés depuis des fichiers nommés "install" situés dans le dossier du projet, copiant les fichiers construits sélectionnés dans le dossier d'installation portant le nom du projet, avec la liste des cibles séparées par des trait d'union. +Ces fichiers d'installation sont lus récursivement, suivant les noms des sous-dossiers pour trouver les cibles du projet. + +Les fichiers supplémentaires à installer sont spécifiés dans le dossier "install" et décrits dans un fichier du même nom, suivant les noms des sous-dossiers pour trouver les cibles du projet. + + +## Version des projets + +Les projets sont versionnés dans un dossier de version, nommé après le projet avec la liste des cibles séparé par un trait d'union. +Chaque fichiers d'installation d'un projet sont empaquetés dans une tarball reposant dans le dossier de version correspondant. +Une somme de contrôle et une signature GPG détâchée (si la variable d'environnement RELEASE_KEY est initialisée) sont aussi générés. + +Les tarballs sont reproduisables grâce à une liste de fichiers donnée par le fichier ".tarfiles". Elle peuvent aussi contenir le fichier ".epoch" et les fichiers git ".revision" et ".version". + + +## Actions des outils + +Les outils sont utilisés pour maintenir le système de build et effectuer des tâches routinières automatisables. Ils peuvent avoir des actions spécifiques et n'implémenter aucune des actions génériques. + +Les actions peuvent être vérifiées par un fonction correspondant à un outil spécifique, nommée après la fonction à vérifier et avec le suffixe "_check", pour déterminer si oui ou non il est nécesssaire de les éxecuter à nouveau pour suivre les étapes. +Une variable d'environnement peut forcer certaines actions à être éxecutée en spécifiant une liste espacée de tâches : TASKS_FORCE. + + +## Source des outils + +Les outils peuvent garder leur sources dans un dossier "sources" dans leur propre dossier. Ces sources peuvent être mise à jour avec l'action update. + diff --git a/i18n/fr_FR/COPYING b/i18n/fr_FR/COPYING new file mode 100644 index 00000000..94a9ed02 --- /dev/null +++ b/i18n/fr_FR/COPYING @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. 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If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/i18n/fr_FR/README.md b/i18n/fr_FR/README.md new file mode 100644 index 00000000..f54fabf8 --- /dev/null +++ b/i18n/fr_FR/README.md @@ -0,0 +1,32 @@ +# Présentation du projet Libreboot + +La documentation de Libreboot est dans le dossier [docs/](https://git.miquellionel.ovh/lili/libreboot_fr/src/branch/master/docs). +Les termes de la licence peuvent être trouvé dans [COPYING](https://git.miquellionel.ovh/lili/libreboot_fr/src/branch/master/COPYING). + +Libreboot est destiné à être un remplacement libre du BIOS ou UEFI; un micrologiciel libre initialisant le matériel et démarrant le chargeur d'amorçage (bootloader) pour votre système d'exploitation. C'est aussi un BIOS open source, mais l'open source échoue à promouvoir la liberté; définissez libreboot en tant qu'un logiciel libre, merci. + +## Pourquoi utiliser Libreboot ? + +Beaucoup de personnes utilisent un micrologiciel non libre, même s'ils utilisent GNU/Linux. Les micrologiciels +BIOS/UEFI non libre contiennent souvent des portes dérobées, peuvent être lent et avoir de grave bugs, +vous laissant démuni et à la merci des développeurs; vous n'avez pas de libertés sur votre usage de l'informatique. + + +Par contraste,libreboot est en train de construire un monde où tout le monde peut utiliser, étudier, adapter et partager des logiciels, avec un vrai contrôle et une vraie appropriation de leur technologie. +. + +Bref, vous devriez l'utiliser pour le bien de votre liberté ! + +Libreboot est plus rapide, plus sécurisé et plus stable que la plupart des micrologiciels non-libre, et peut apporter d'autres fonctionnalités avancées (tel que le chiffrement du /boot/, vérification de la signature GPG avant de démarrer votre kernel, possibilité de charger un OS depuis la puce flash (flash chip), et plus encore). + +Les fournisseurs principaux de Libreboot en amont sont Coreboot (que nous "déblobons", pour l'initialisation matérielle), depthcharge (chargeur d'amorçage, et charge utile de Libreboot par défaut sur l'architecture ARM), et GRUB (chargeur d'amorçage, et charge utile de Libreboot par défaut sur l'architecture x86). + + +Nous intégrons par ailleurs flashrom (pour installer Libreboot), ainsi que quelques un de nos utilitaires, scripts et fichier de configuration. + +Tout celà est intégré dans un seul paquetage cohérent et facile à utiliser. Nous ajoutons nos propres patchs aux nombreuses sources utilisées en amont, et quand celà est faisable nous essayons de fusionner en amont autant que possible. + +Le système de contruction de Libreboot et sa documentation sont disponibles ici dans le but de rendre le micrologiciel libre accessible à tous. + + +Ce LISEZMOI est sous la licence [Creative Commons Zero 1.0](https://creativecommons.org/publicdomain/zero/1.0/) diff --git a/i18n/fr_FR/RELEASE b/i18n/fr_FR/RELEASE new file mode 100644 index 00000000..134a65c8 --- /dev/null +++ b/i18n/fr_FR/RELEASE @@ -0,0 +1,92 @@ +Libreboot 20160907 + +Pour les cartes existantes, il n'y a pas de nouveaux changements spécifiques à celles-ci. + +Cette version ajoute une nouvelle carte mère à libreboot: +* Intel D945GCLF carte mère d'ordinateur de bureau (grâce à Arthur Heymans) + +Autres résolutions de bogues: +* nombreuses améliorations de la documentation. +* réajout de "unset superusers" dans le grub.cfg, qui était nécessaire pour certains utilisateurs selon la distributions qu'ils utilisaient. + +Libreboot 20160902 + +C'est une version de fixage de bogue, basé sur la 20160818. Elle ne contient pas de changement sur les nouvelles cartes. +La version précédente 20160818 avait des erreurs de build dans l'archive _src, et l'archive +_util était seulement du code source. + +Changement comparé à 20160818: +* Résolution d'un bug où la commande ./build module coreboot retourné un statut toujours différent de 0. +* Résolution du symlink manquant de crossgcc lors de la build depuis _src (merci Arthur +Heymans) +* Résolution de la build avec le payload depthcharge (ASUS C201) +* Le changelog est désormais plus correct au lieu d'un simple copier coller du git log +* L'Util archive est de nouveau un fichier binaire (le code source est dans l'archive _src) +* La documentation est maintenant au format HTML. + +Libreboot 20160818 + +NOUVELLES CARTES MÈRES AJOUTÉES: +* ASUS Chromebook C201 (ordi portable ARM) (grâce à Paul Kocialkowski) +* Gigabyte GA-G41M-ES2L carte mère (bureau) (grâce à Damien Zammit) +* Intel D510MO carte mère (bureau) (grâce à Damien Zammit) +* ASUS KCMA-D8 carte mère (bureau) (grâce à Timothy Pearson) +* ASUS KFSN4-DRE carte mère (serveur) (grâce à Timothy Pearson) +* ASUS KGPE-D16 carte mère (serveur) (grâce à Timothy Pearson) + +Pour les cartes précedemment supportées, de nombreuses corrections venant d'amont ont été fusionnées. + +Autre changements (par rapport à la version libreboot 20150518): +(ceci est un résumé. Pour une liste plus détaillée des changements, veuillez vous référer au git log). + +256Mo VRAM alloué sur la GM45 (X200, T400, T500, R400) au lieu de 32Mo. +C'est une amélioration par rapport au BIOS Lenovo et Libreboot 20150518, permettant le décodage vidéo à 1080p d'être plus fluide. (merci Arthur Heymans). Pour clarifier, la performance vidéo GM45 dans libreboot 20160818 est meilleure que le BIOS originel et la précédente version. + +64Mo VRAM sur i945 (X60, T60, MacBook2,1) maintenant supporté dans coreboot-libre, et utilisé par défaut (dans les précédentes versions, il y avait 8Mo alloué). Merci à Arthur Heymans. + +Une meilleure durée de vie de la batterie sur la GM45 (X200, T400, T500, R400) dû au niveau plus haut de cstates maitenant supportés.(merci Arthur Heymans). États de puissances C4 maintenant supportés. + +Le mode texte de la GM45 (X200, T400, T500, R400) marche maitenant, permettant d'utiliser MemText86+ comfortablement. (grâce à Nick High de coreboot) + +Les affichages LVDS à double canaux sur la GM45 (T400, T500) sont maintenant automatiquement détecté coreboot-libre. (merci Vladimir Serbinenko de coreboot) + +Résolution partielle dans coreboot-libre par rapport à l'affichage du GRUB sur la GM45, résolution plus haute pour les écrans LCD pour les affichages LVDS à double canaux (T400, T500). (merci Arthur Heymans) + +Améliorations massive de la configuration du GRUB, rendant plus facile le démarrage automatique +de nombreux systèmes d'exploitations chiffré, et généralement un menu plus utile pour démarrer (les remerciements grâce à Klemens Nanni du projet autoboot). +Libreboot utilise maintenant automatiquement le grub.cfg fourni par la distribution +GNU+Linux installée, si présente, passant sur cette configuration. Celà est fait à travers de multiples partitions où libreboot cherche activement pour un fichier de configuration +(notamment sur les volumes chiffrés et LVM). Celà devrait rendre Libreboot plus facile +à utiliser pour les utilisateurs non techniques, sans avoir à modifier la +configuration GRUB utilisée dans libreboot. + +Les archives des utilitaires sont maitenant en mode source seulement . Vous aurez besoin de compiler les paquets +dedans (scripts de builds sont compris, et un script pour installer les dépendances du build). (les archives de fichiers binaires sont de nouveau prévues dans une nouvelle version où le nouveau système de build sera fusionné). + +SeaGRUB est maintenant le payload par défaut des cartes x86. (SeaBIOS configuré pour immédiatement charger un payload GRUB depuis CBFS sans fournir une interface dans SeaBIOS. De cette façon, GRUB est encore utilisé mais maintenant les services du BIOS sont disponibles, vous obtenez donc le meilleur des deux mondes). Les remerciements reviennent à Timothy Pearson +de coreboot pour cette idée. + +crossgcc est maintenant téléchargé et construit en tant que module séparé de coreboot-libre, +avec une révision universelle utilisée pour build toutes les cartes. + +Les cartes mères spécifiques ont leur propre patchs et modification de coreboot, indépendantes des autres autres. Celà rend la maintenance plus facile. + +Mise à jour de tous les utilitaires et modules (coreboot, GRUB, etc) vers des versions plus récentes, +avec de nombreuses correction de bogues et améliorations en amont. + +Le problème de l'octect "siècle" de l'Horloge Temps Réél (RTC/HTR) est mainteant corrigé sur la GM45 dans coreboot-libre, donc la date devrait maitenant s'afficher +correctement lors de l'utilisation du dernier kernel linux, au lieu de voir 1970-01-01 au démarrage (grâce à Alexander Couzens de coreboot) + +Le système de build utilise maintenant plusieurs coeurs d'un CPU, accélérant le build pour certaine personnes. +La spécification manuelle du nombre de coeurs a utiliser est possible pour ceux qui utilise le système de build dans un environnement chrooté (les remerciements vont à +Timothy Pearson de coreboot). + +Dans le système de build (répo git), https:// est maitenant utilisée lors du clonage de coreboot. +http:// est utilisé en tant qu'alternative pour GRUB si git:// échoue + +Nouveau chargeur d'amorçage, depthcharge (libre et maintenu par Google) +prêt à l'utilisation sur l'ASUS Chromebook C201. (les remerciements vont à Paul Kocialkowski) + + +Nombreuses corrections à l'utilitaire ich9gen (p.e maintenant la densité du composant flash est correctement mise dans la description, les descriptions gbe-less sont maintenant supportées.) + diff --git a/i18n/fr_FR/docs/$ b/i18n/fr_FR/docs/$ new file mode 100644 index 00000000..7cadf22b --- /dev/null +++ b/i18n/fr_FR/docs/$ @@ -0,0 +1,1438 @@ +--- +title: Listes de changements par version stable. +x-toc-enable: true +... + +Les versions mises à jour de libreboot peuvent être trouvée sur [libreboot.org](/). +Les annoncements de publication de nouvelles versions de Libreboot peuvent être trouvée dans la [section des actualités](../news/) sur le site web. + +Libreboot 20160907 {#release20160907} +================== + +Date de publication : 7 Septembre 2016 + +Pour les cartes mères existantes, il n'y pas de nouveaux changements spécifiques. + +Cette version ajoute une nouvelle carte mère à libreboot: + +- Carte mère de bureau Intel D945GCLF (merci à Arthur Heymans) + +Autres correction de bogue : + +- Nombreuses améliorations de la documentation +- Réajout de "unset superusers" au grub.cfg, qui était nécessaire pour quelques utilisateurs en fonction de la distribution qu'ils utilisaient. + + +Libreboot 20160902 {#release20160922} +================== + +Date de publication: 2 Septembre 2016. + +Cela corrige des problèmes dans la version précédente 20160818. +Regardez le journal des changements pour des détails. + + +Libreboot 20160818 {#release20160818} +================== + +Date de publication: 18 Août 2016. + +Les instructions d'installation peuvent être trouvée dans `docs/install`. +Les instructions de constructions (pour le code source) peuvent être trouvé dans `docs/git/\#build`. + + +Machines supportées dans cette version: +----------------------------------- + +- **ASUS Chromebook C201** + - Regardez les notes dans ***docs/hardware/c201.html*** +- **Gigabyte GA-G41M-ES2L desktop motherboard** + - Regardez les notes dans ***docs/hardware/ga-g41m-es2l.html*** +- **Intel D510MO desktop motherboard** + - Regardez les notes dans ***docs/hardware/d510mo.html*** +- **Intel D945GCLF desktop motherboard** + - Regardez les notes dans ***docs/hardware/d945gclf.html*** +- **Apple iMac 5,2** + - Regardez les notes dans ***docs/hardware/imac52.html*** +- **ASUS KFSN4-DRE server board** + - PCB revision 1.05G is the best version (can use 6-core CPUs) + - Regardez les notes dans ***docs/hardware/kfsn4-dre.html*** +- **ASUS KGPE-D16 server board** + - Regardez les notes dans ***docs/hardware/kgpe-d16.html*** +- **ASUS KCMA-D8 desktop/workstation board** + - Regardez les notes dans ***docs/hardware/kcma-d8.html*** +- **ThinkPad X60/X60s** + - Vous pouvez aussi enlever la carte mère d'un X61/X61s et la remplacer avec une carte mère X60/X60s. Une carte d'une X60 Tablet rentrera aussi dans l'intérieur d'un X60/X60s. + +- **ThinkPad X60 Tablet** (résolution 1024x768 et 1400x1050) avec support pour scanneur + + + - ***docs/hardware/\#supported\_x6Ot\_list*** pour la lste d'écrans LCD supportés. + - C'est inconnu s'il se peut qu'une X61 Tablet ait sa carte mère remplacée par une carté mère d'une X60 Tablet. + + +- **ThinkPad T60** (Intel GPU) (il y a des problèmes; regardez en dessous): + + - Regardez les notes ci-dessous pour les exceptions et + ***docs/hardware/\#supported\_t60\_list*** pour une liste connue d'écrans LCD fonctionnels. + + - C'est inconnu s'il se peut qu'un T61 ait sa carte mère remplacée par une carté mère d'un T60. + - Regardez **docs/future/\#t60\_cpu\_microcode***. + - T60p (et ordinateurs portables avec carte graphiques ATI) ne sera surêment jamais supporté : ***docs/hardware/\#t60\_ati\_intel***. + + +- **ThinkPad X200** + - **ME/AMT**: libreboot enlève ceci, permanemment. + ***docs/hardware/gm45\_remove\_me.html*** + +- **ThinkPad R400** + - Regardez **docs/hardware/r400.html** + - **ME/AMT**: libreboot enlève ceci, permanemment. + ***docs/hardware/gm45\_remove\_me.html*** + +- **ThinkPad T400** + - Regardez ***docs/hardware/t400.html*** + - **ME/AMT**: libreboot enlève ceci, permanemment. + ***docs/hardware/gm45\_remove\_me.html*** + +- **ThinkPad T500**: + - Regardez ***docs/hardware/t500.html*** + - **ME/AMT**: libreboot enlève ceci, permanemment. + ***docs/hardware/gm45\_remove\_me.html*** + +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - Regardez ***docs/hardware/\#macbook11***. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - Regardez ***docs/hardware/\#macbook21***. + + +Changements pour cette version, relatif à r20150518 (les changements les plus tôt en dernier, les changements récents en premier) +--------------------------------------------------------------------------------------------- + +Libreboot 20160818 + +- NOUVELLES CARTES MÈRES AJOUTÉES: + - ASUS Chromebook C201 (ordi portable ARM) (grâce à Paul Kocialkowski) + - Gigabyte GA-G41M-ES2L carte mère (bureau) (grâce à Damien Zammit) + - Intel D510MO carte mère (bureau) (grâce à Damien Zammit) + - ASUS KCMA-D8 carte mère (bureau) (grâce à Timothy Pearson) + - ASUS KFSN4-DRE carte mère (serveur) (grâce à Timothy Pearson) + - ASUS KGPE-D16 carte mère (serveur) (grâce à Timothy Pearson) + +Pour les cartes précedemment supportées, de nombreuses corrections venant d'amont ont été fusionnées. + +Autre changements (par rapport à la version libreboot 20150518): +(ceci est un résumé. Pour une liste plus détaillée des changements, veuillez vous référer au git log). + +256Mo VRAM alloué sur la GM45 (X200, T400, T500, R400) au lieu de 32Mo. +C'est une amélioration par rapport au BIOS Lenovo et Libreboot 20150518, permettant le décodage vidéo à 1080p d'être plus fluide. (merci Arthur Heymans). Pour clarifier, la performance vidéo GM45 dans libreboot 20160818 est meilleure que le BIOS originel et la précédente version. + +64Mo VRAM sur i945 (X60, T60, MacBook2,1) maintenant supporté dans coreboot-libre, et utilisé par défaut (dans les précédentes versions, il y avait 8Mo alloué). Merci à Arthur Heymans. + +Une meilleure durée de vie de la batterie sur la GM45 (X200, T400, T500, R400) dû au niveau plus haut de cstates maitenant supportés.(merci Arthur Heymans). États de puissances C4 maintenant supportés. + +Le mode texte de la GM45 (X200, T400, T500, R400) marche maitenant, permettant d'utiliser MemText86+ comfortablement. (grâce à Nick High de coreboot) + +Les affichages LVDS à double canaux sur la GM45 (T400, T500) sont maintenant automatiquement détecté coreboot-libre. (merci Vladimir Serbinenko de coreboot) + +Résolution partielle dans coreboot-libre par rapport à l'affichage du GRUB sur la GM45, résolution plus haute pour les écrans LCD pour les affichages LVDS à double canaux (T400, T500). (merci Arthur Heymans) + +Améliorations massive de la configuration du GRUB, rendant plus facile le démarrage automatique +de nombreux systèmes d'exploitations chiffré, et généralement un menu plus utile pour démarrer (les remerciements grâce à Klemens Nanni du projet autoboot). +Libreboot utilise maintenant automatiquement le grub.cfg fourni par la distribution +GNU+Linux installée, si présente, passant sur cette configuration. Celà est fait à travers de multiples partitions où libreboot cherche activement pour un fichier de configuration +(notamment sur les volumes chiffrés et LVM). Celà devrait rendre Libreboot plus facile +à utiliser pour les utilisateurs non techniques, sans avoir à modifier la +configuration GRUB utilisée dans libreboot. + +Les archives des utilitaires sont maitenant en mode source seulement . Vous aurez besoin de compiler les paquets +dedans (scripts de builds sont compris, et un script pour installer les dépendances du build). (les archives de fichiers binaires sont de nouveau prévues dans une nouvelle version où le nouveau système de build sera fusionné). + +SeaGRUB est maintenant le payload par défaut des cartes x86. (SeaBIOS configuré pour immédiatement charger un payload GRUB depuis CBFS sans fournir une interface dans SeaBIOS. De cette façon, GRUB est encore utilisé mais maintenant les services du BIOS sont disponibles, vous obtenez donc le meilleur des deux mondes). Les remerciements reviennent à Timothy Pearson +de coreboot pour cette idée. + +crossgcc est maintenant téléchargé et construit en tant que module séparé de coreboot-libre, +avec une révision universelle utilisée pour build toutes les cartes. + +Les cartes mères spécifiques ont leur propre patchs et modification de coreboot, indépendantes des autres autres. Celà rend la maintenance plus facile. + +Mise à jour de tous les utilitaires et modules (coreboot, GRUB, etc) vers des versions plus récentes, +avec de nombreuses correction de bogues et améliorations en amont. + +Le problème de l'octect "siècle" de l'Horloge Temps Réél (RTC/HTR) est mainteant corrigé sur la GM45 dans coreboot-libre, donc la date devrait maitenant s'afficher +correctement lors de l'utilisation du dernier kernel linux, au lieu de voir 1970-01-01 au démarrage (grâce à Alexander Couzens de coreboot) + +Le système de build utilise maintenant plusieurs coeurs d'un CPU, accélérant le build pour certaine personnes. +La spécification manuelle du nombre de coeurs a utiliser est possible pour ceux qui utilise le système de build dans un environnement chrooté (les remerciements vont à +Timothy Pearson de coreboot). + +Dans le système de build (répo git), https:// est maitenant utilisée lors du clonage de coreboot. +http:// est utilisé en tant qu'alternative pour GRUB si git:// échoue + +Nouveau chargeur d'amorçage, depthcharge (libre et maintenu par Google) +prêt à l'utilisation sur l'ASUS Chromebook C201. (les remerciements vont à Paul Kocialkowski) + + +Nombreuses corrections à l'utilitaire ich9gen (p.e maintenant la densité du composant flash est correctement mise dans la description, les descriptions gbe-less sont maintenant supportées.) + + +Version 20150518 {#release20150518} +================ + +Date de publication : 18 May 2015. + +Instructions d'installation peuvent être trouvé à ***docs/install/*** +Instructions de constructions (pour le code source) peuvent être trouvée dans ***docs/git/\#build***. + + +Machines supportés dans cette version: +----------------------------------- + +- **ThinkPad X60/X60s** + - Vous pouvez aussi enlever la carte mère d'un X61/X61s et la remplacer avec une carte mère d'un X60/X60s. Une carte mère d'une X60 Tablet rentrera aussi à l'intérieur d'une X60/X60s +- **ThinkPad X60 Tablet** (1024x768 et 1400x1050) avec support pour scanneur + - Regardez ***docs/hardware/\#supported\_x60t\_list*** pour une liste des écrans LCD supportés + - C'est inconnu s'il se peut qu'un X61 Tablet peut avoir sa carte mère remplacée par une carte mère d'une X60 Tablet. +- **ThinkPad T60** (Carte graphique Intel) (il y a des problèmes; regardez ci-dessous): + - Regardez les notes ci-dessous pour des exceptions, et ***docs/hardware/\#supported\_t60\_list*** pour les écrans LCDs connus pour marcher. + - C'est inconnu s'il se peut qu'un T61 peut avoir sa carte mère remplacée par une carte mère d'un T60. + - Regardez ***docs/future/\#t60\_ati\_intel*** +- **ThinkPad X200** + - X200S et X200 Tablet sont aussi supportés, conditionnellement; regardez + ***docs/hardware/x200.html\#x200s*** + - **ME/AMT**: libreboot enlève ceci, définitevement. + ***docs/hardware/gm45\_remove\_me.html*** +- **ThinkPad R400** + - Regardez ***docs/hardware/r400.html*** + - **ME/AMT**: libreboot enlève ceci, définitevement. + ***docs/hardware/gm45\_remove\_me.html*** +- **ThinkPad T400** + - Regardez ***docs/hardware/t400.html*** + - **ME/AMT**: libreboot enlève ceci, définitevement. + ***docs/hardware/gm45\_remove\_me.html*** +- **ThinkPad T500** + - Regardez ***docs/hardware/t500.html*** + - **ME/AMT**: libreboot enlève ceci, définitevement. + ***docs/hardware/gm45\_remove\_me.html*** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - Regardez ***docs/hardware/\#macbook11***. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - Regardez ***docs/hardware/\#macbook21***. + +Changements pour cette version, relatif à r20150518 (les changements les plus tôt en dernier, les changements récents en premier) +--------------------------------------------------------------------------------------------- + +- Ajoute une donnée de liste blanche dans board\_enable.c dans la flashrom, pour le ThinkPad R400, T400 et T500 +- Flashrom mis à jour (à la révision SVN 1889) + - Patch de la liste blanche pour le X200 enlevé (fusionné depuis l'amont) + - Liste blanche X200 modifiée pour inclure le X200S et le X200 Tablet +- libreboot\_util: n'inclut pas les fichiers d'agencement du cmos (ne sont plus nécessaires) +- **coreboot_libre: Patchs rétroactifs pour le support du scanneur pour les X200 Tablet** +- build/release/archives: créé un fichier manifeste de somme SHA512 des archives de version. +- build/release/archives: séparation de crossgcc dans une nouvelle archive +- désactivé la génération d'images ROM txtmode pour maintenant ( elles seront de retour de nouveau encore dans une prochaine version) +- coreboot-libre: supprimer le code inutilisé (réduit la taille de l'archive src) +- Guides de flashage: rendus plus amicaux pour les personnes daltonienne. +- docs/gnulinux/encrypted\_\*.html: suppression de la mention de la longueur du mot de passe - c'était arbitraire et sans intérêt. +- docs/maintain/: Finir le guide +- scripts/download/coreboot: utilise les diffs incluses dans libreboot, pas quelques bon bouts du gerrit extérieur - review.coreboot.org (gerrit) étant hors service ne tue plus libreboot (des mirroirs de sauvegardes du répertoire maître existent). +- docs/install/bbb\_setup.html: ajout d'infos à propos de wp/hold et pinouts +- docs/: améliore la description de libreboot +- docs/hardware/gm45\_remove\_me.html: notes à propos de l'utilitaire demefactory. +- docs/install/bbb\_setup.html: débug EHCI : recommander linux-libre. +- docs/install/bbb\_setup.html: Guide de mise en place des fichiers journaux de débug de l'EHCI. +- docs/hardware/t500.html: ajout du rapport de compatibilité des écrans (ÀFAIRE: corriger les écrans incompatibles) +- Met à jour coreboot(encore) + fusionne les patchs de carte graphiques hybride GM45 - celà signifie que la mise en place d'un T400/T500 avec GPU hybride ATI+Intel marchera (ATI désactivé, Intel activé définitivement). L'option power\_on\_after\_fail de la nvram ajoutée à toutes les cartes mères GM45, par défaut sur Non, comme ça la brancher sur secteur ne démarre pas le système contre la volonté de l'utilisateur. Net20DC est maintenant le boîtier de déboguage par défaut sur toutes les cartes mères (compatibles avec BBB). +- demefactory (nouvel utilitaire): créée la factory.rom sans la ME +- ich9deblob: re-façonnage des fonctions de descriptor.c +- docs/hardware/t500.html: ajout des journaux matériels +- docs/gnulinux/encrypted\_\*.html: pas de mot de passe pour la saisie par défaut +- docs/git/: Ajout de plus détails à propos de BUC.TS +- grub.cfg: Scanne aussi pour grub2/grub.cfg, pas juste grub/grub.cfg +- docs/maintain/ (nouvelle section. Travail en cours !): Faire la maintenance de libreboot +- docs/gnulinux/grub\_boot\_installer.html: Correction d'une instruction hasardeuse +- docs/tasks.html: meilleure catégorisation entre intel/amd/arm +- docs/install/bbb\_setup.html: notes à propos de la stabilité de l'utilitaire de flashage SPI. +- docs/install/bbb\_setup.html: plus de noms pour les cables de 0.1 pouce. +- docs/install/\*\_external.html: ajout d'un avis de non responsabilité à propos de la pâte thermique. +- docs/install/bbb\_setup.html: Correction des liens cassés +- docs/install/bbb\_setup.html: notes préliminaires à propos du déboguage EHCI. +- docs/hardware/gm45\_remove\_me.html: lien vers les sites webs parlant de la ME. +- docs/install/{t400,t500,r400}\_external.html: notes à propos de la compatibilité des processeurs (CPU). +- Supprime le script ich9macchange. Il est inutile et embrouille les gens. +- docs/hardware/gm45\_remove\_me.html: prioritisation du chemin d'éxecutable d'ich9gen. +- docs/hardware/gm45\_remove\_me.html: prioritisation du changement d'adresse MAC. +- docs/hardware/gm45\_remove\_me.html: notes moins embrouillantes à propos d'ich9gen +- build/dependencies/parabola: Ajout de dépendances pour l'architecture x86_64. +- scripts/dependencies/paraboladependencies: dépendances de constructions (pour 32-bit Parabola). +- **Nouvelle carte mère**: ThinkPad T500 +- Ajout des diffs pour les différences de descripteurs/gbe entre le T500 et X200 +- coreboot-libre: fournit une meilleure catégorisation des blobs. +- docs/hardware/gm45\_remove\_me.html: ajout de notes à propos de la protection d'écriture flash. +- **Nouvelle carte mère**: ThinkPad T400 +- GRUB: ajout d'un support partial de vesamenu.c32 (corrige la fin du menu ISOLINUX) +- Mise à jour du GRUB (à la révision fa07d919d1ff868b18d8a42276d094b63a58e299). +- Mise à jour de coreboot (à la révsion 83b05eb0a85d7b7ac0837cece67afabbdb46ea65) + - Le microcode du CPU Intel (la majorité de) n'est plus supprimé désormais, parce que c'était supprimé en amont (bougé dans un répertoire tierce partie). + - Le patch du cstate pour Macbook2,1 n'est plus choisi sur le volet (fusionné de l'amont). + - Le patch pour désactiver l'utilisation de l'horodatage dans coreboot n'est plus inclus (fusionné de l'amont) +- coreboot-libre: ne pas lister le micrologiciel kbd vortex86ex en tant que microcode +- coreboot-libre: ajout de la license GPLv3 aux scripts findblobs. +- coreboot-libreboot: ne supprime pas raminit\_tables (nahelem/sandybridge) (ils ne sont pas des blobs) +- coreboot-libre: ne supprime pas les fichiers .spd.hex (ils ne sont pas des blobs). +- build/release/archives: ne met pas rmodtool dans libreboot\_util +- docs/install/x200\_external.html: recommande l'installation de GNU+Linux à la fin. +- docs/install/x200\_external.html: ajoute plus de photos, améliore les instructions +- build/clean/grub: utilise distclean au lieu de clean +- grub-assemble: Ajoute les modules *bsd* et *part\_bsd* +- build/roms/withgrub: n'éxecute seulement ich9gen si les images de gm45/gs45 existe +- docs/git/: ajout de notes à propos de la compilation pour certaines cartes mères spécifiques. +- build/roms/withgrub: permet la compilation pour une portée customisée de cartes mères. +- grub-assemble: désactive la sortie verbeuse. +- Ajoute de la documentation sur comment déverouiller le système de fichiers chiffré avec clé dans initramfs dans Parabola Linux +- docs/gnulinux/grub\_cbfs.html: amélioration de la structure (plus facile à utiliser) +- grub.cfg: Désactive le beep au démarrage. +- docs/install/bbb\_setup.html: rend le guide plus facile à utiliser +- docs/gnulinux/grub\_cbfs: supprime les instructions redondantes +- docs/install/x200\_external.html: met des punaises dans les images. +- docs/install/bbb\_setup.html: remplace la photo PSU 3.3V avec ATX PSU +- docs/hardware/x200.html: ajout de décharges du X200 4Mo avec BIOS Lenovo v3.22 +- docs/hardware/x200.html: ajout de décharges du X200 4Mo avec BIOS Lenovo v3.18 +- grub.cfg: ajout d'une entrée de menu syslinux\_configfile pour ahci0 +- grub.cfg: ajout de plus de chemins pour syslinux\_configfile + +- Add documentation on how to unlock root encrypted fs with key in + initramfs in Parabola Linux +- docs/gnulinux/grub\_cbfs.html: Improve structure (easier to use) +- grub.cfg: Disable the beep on startup +- docs/install/bbb\_setup.html: Make the guide easier to use +- docs/gnulinux/grub\_cbfs.html: Remove redundant instructions +- docs/install/x200\_external.html: Mark pins in the images +- docs/install/bbb\_setup.html: Replace 3.3V PSU photo with ATX PSU +- docs/hardware/x200.html: Add dumps from 4-MiB X200 with Lenovo BIOS 3.22 +- docs/hardware/x200.html: Add dumps from 4-MiB X200 with Lenovo BIOS 3.18 +- grub.cfg: add syslinux\_configfile menuentry for ahci0 +- grub.cfg: Add more paths for syslinux\_configfile +- docs/future.html: T60: Add EDID dump from LG-Philips LP150E05-A2K1 +- docs/install/bbb\_setup.html: Further clarify which clip is needed +- bash scripts: Make script output more user-friendly in general +- bash scripts: Only enable verbose output if DEBUG= is used +- build: Support multiple extra options - now possible to build + multiple images for arbitrary boards (configs), but without building + the entire collection. +- Deleted the signing archive key - the finger print and ID is given + instead, so that the user can download it from a key server +- scripts/helpers/build/release: Move docs to separate archive - + reduces the size of the other archives considerably +- Move DEBLOB to resources/utilities/coreboot-libre/deblob +- scripts/helpers/build/release: Delete DEBLOB from libreboot\_src/ - + not needed in libreboot\_src (release archive) because it contains a + coreboot revision that has already been deblobbed. +- flash (script): Use *build* instead of *DEBLOB* to know if in src +- docs/install/r400\_external.html: Show images, don't link. +- docs/install/x200\_external.html: Show images, don't link. +- docs/install/bbb\_setup.html: Show images, instead of linking +- Documentation: optimize all images (reduce file sizes) +- Remove download links from the release page (and the archive page) - + release archives are hosted differently following this release, + which means that the old methods are no longer viable. +- Moved ich9macchange to resources/scripts/misc/ich9macchange +- ich9macchange: assume that the script is being run from \_util (act + only on one ROM image, defined by a user-provided path) +- Move grub-background to resources/scripts/misc/grub-background +- grub-background: assume that it is being run from libreboot\_util +- grub-background: change only one ROM image, specified by path +- build (release archives): Add the commitid file to release/ +- build-release: Move the release archives to release/ +- Merge all build scripts into a single generic script, with helpers + in resources/scripts/helpers/build/ +- Replace *getall* with *download*, which takes as input an argument + specifying which program the user wants to download. +- Moved the get scripts to resources/scripts/helpers/download/ +- build-release: Remove the powertop entries +- Documentation: general improvements to the flashing instructions +- Merged all flashing scripts into a single script +- Updated GRUB +- bucts: Make it build without git +- Moved dejavu-fonts-ttf-2.34/AUTHORS to resources/grub/font/ +- Deleted GRUB Invaders from libreboot +- Deleted SeaBIOS from libreboot +- build-release: optimize use of tar (reduced file sizes) +- grub.cfg: add another SYSLINUX config location + (/syslinux/syslinux.cfg) +- build-release: remove the bin/ directory from libreboot\_util +- cleandeps: delete the bin/ directory +- buildrom-withgrub: create the bin directory if it does not exist +- coreboot-libre: don't use git for version timestamp +- i945-pwm: add clean command to Makefile +- i945-pwm: add -lz to Makefile +- docs/install/x200\_external: Mention GPIO33 non-descriptor mode +- docs/hardware/: Remove redundant links +- ich9macchange: Add R400 +- build-release: Separate ROM images into individual archives +- build-release: rename libreboot\_bin to libreboot\_util +- **New board:** ThinkPad R400 support added to libreboot. +- bbb\_setup.html: tell user to use libreboot's own flashrom + +Release 20150124, 20150126 and 20150208 {#release20150124} +======================================= + +Date de publication: 24th January 2015. + +Machines supported in this release: +----------------------------------- + +- **Lenovo ThinkPad X60/X60s** + - You can also remove the motherboard from an X61/X61s and replace + it with an X60/X60s motherboard. An X60 Tablet motherboard will + also fit inside an X60/X60s. +- **Lenovo ThinkPad X60 Tablet** (1024x768 and 1400x1050) with + digitizer support + - See **hardware/\#supported\_x60t\_list** for list of supported LCD + panels + - It is unknown whether an X61 Tablet can have it's mainboard + replaced with an X60 Tablet motherboard. +- **Lenovo ThinkPad T60** (Intel GPU) (there are + issuesinstall/x200\_external.html; see below): + - See notes below for exceptions, and + **hardware/\#supported\_t60\_list** for known working LCD panels. + - It is unknown whether a T61 can have it's mainboard replaced + with a T60 motherboard. + - See **future/\#t60\_cpu\_microcode**. + - T60p (and T60 laptops with ATI GPU) will likely never be + supported: **hardware/\#t60\_ati\_intel** +- **Lenovo ThinkPad X200** + - X200S and X200 Tablet are also supported, conditionally; see + **hardware/x200.html\#x200s** + - **ME/AMT**: libreboot enlève ceci, définitevement. + **hardware/gm45\_remove\_me.html** +- **Lenovo ThinkPad R400** (r20150208 and later, only) + - **ME/AMT**: libreboot enlève ceci, définitevement. + **hardware/gm45\_remove\_me.html** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - See **hardware/\#macbook11**. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - See **hardware/\#macbook21**. + +Revisions for r20150208 (relative to r20150126) +----------------------------------------------- + +This is a maintenance release (polishing) based on r20150126. Users who +installed r20150126 don't really need to update to this release. + +- buildrom-withgrub: use gnulove.jpg background on 16:10 laptops + (MacBook2,1 and X200) +- build-release: include grub-background script in libreboot\_bin +- grub-background (new): lets user change GRUB background image +- grub-assemble: Add link to original utility. +- buildrom-withgrub: Put background.jpg in CBFS, not GRUB memdisk +- grub-assemble: merge scripts into a single script gen.sh +- Documentation: implement theme, drastically improve readability +- docs/hardware/: update list of compatible T60 LCD panels +- docs/: more clarification of libreboot's stated purpose. +- build-release: include the commitid file in the release archives +- docs/: Further emphasize the GNU+Linux requirement. +- lenovobios\_firstflash: fix BASH errors +- lenovobios\_secondflash: fix BASH errors +- docs/install/x200\_external.html: Tell user to switch MAC address. +- docs/git/: Add to the list of x86\_64 compatible hosts. +- docs/install/: Remove old (obsolete) information. +- docs/git/: Say that the build dependencies are for src (and not + nedeed for libreboot\_bin) +- build: re-factor the descriptor/gbe generating loop for GM45/ICH9M +- X60, X60S and X60 Tablet now the same ROM images. +- Add QEMU (q35/ich9) support to libreboot. +- Add QEMU (i440fx/piix4) support to libreboot +- docs/: Re-write the description of what libreboot is. +- docs/release.html: Add notes about how to use GPG. +- build-release: delete the commitid file from release archives +- build-release: create file named commitid after build-release + +Revisions for r20150126 (relative to r20150124) +----------------------------------------------- + +This is a bug fix release based on r20150124. It contains a few small +changes: + +- grub.cfg: hardcode the list of partitions to search (speeds up + booting considerably. GRUB regexp isn't very well optimized) +- Docs (x200.html hcl): Remove incorrect information +- Documentation (bbb\_setup.md): Fix typos +- build-release: delete ich9fdgbe\_{4m,8m}.bin files from ich9gen + - These were accidentically included in the r20150124 release. + They are generated from ich9gen so it's ok, but they don't + need to be in the archive. +- Documentation (grub\_cbfs.md): Looping in libreboot\_grub.cfg (Add + notes about it if the user copied from grub.cfg in CBFS.) + +Changes for this release (latest changes first, earliest changes last) +---------------------------------------------------------------------- + +- grub.cfg: Added (ahci1) to list of devices for ISOLINUX parser + (CD/DVD) (this is needed for the X200 docking station). +- grub.cfg: ISOLINUX parsing is now done on all USB partitions. +- grub.cfg: Automatically switched to /boot/grub/libreboot\_grub.cfg + on a partition, if it exists. +- libreboot\_bin: added static ARM binaries for flashrom, cbfstool, + ich9gen and ich9deblob (tested on beaglebone black). +- Flashrom: removed redundant Macronix flashchip definitions (for X200 + owners). +- Flashrom: added whitelist for ThinkPad X200. +- X200: fixed uneven backlight (at low levels) +- ich9macchange (new script, uses ich9gen): for changing the default + MAC address on X200 ROM images. +- ich9gen: added capability to change the default MAC address (and + update the checksum) +- ich9deblob: added new utility ich9gen: this can generate a + descriptor+gbe image without a factory.rom dump present. +- Modified ich9deblob to use a struct for Gbe, documenting everything. +- Massively updated the ich9deblob utility: re-factored everything + completely. +- Enabled cstates 1 and 2 on macbook21. This reduces idle heat / power + consumption. +- buildrom-withgrub: disabled creation of \*txtmode\*.rom for X200 + (only framebuffer graphics work) +- Updated SeaBIOS (again) +- docs/install/\#flashrom\_x200: improve instructions +- Updated flashrom (again) - patches updated +- Updated GRUB (again) +- Updated coreboot (again) +- build-release: not all files were copied to libreboot\_src. fix + that. +- build-release: include cbmem (statically compiled) in libreboot\_bin +- Documentation (X200): added software-based flashing instructions +- Documentation: remove all references to the bus pirate (replaced + with BBB flashing tutorials) +- **New board:** ThinkPad X200S and X200 Tablet support added to + libreboot +- build: automatically find board names (configs) to build for +- **New board:** ThinkPad X200 support added to libreboot +- coreboot-libre config (all boards): enable USB dongle log output + (for BeagleBone Black) +- cleandeps: actually clean grubinvaders +- .gitignore: add powertop directory +- cleandeps: clean i945-pwm utility +- scripts (all): fix typos +- Documentation: general cleanup. +- builddeps-flashrom: reduce build commands to a single for loop +- scripts (all): replace unnecessary rm -Rf with rm -f +- docs/release.html: add lenovo g505s to the list of candidates +- .gitignore: add libreboot\_bin.tar.xz and libreboot\_src.tar.xz +- libreboot\_bin.tar.xz: Include utils as statically linked binaries + - This means that the user does not have to install build + dependency or build from source anymore. +- deps-parabola (removed) Remove Parabola dependencies script. Will + re-add later (properly tested) +- grub.cfg: Add more path checks to isolinux parser (more ISOs should + work now) +- Update SeaBIOS +- x60flashfrom5 (new), for X60 users upgrading from 5th/early release +- Update flashrom +- Update GRUB +- Updated coreboot-libre + - i945: permanently set tft\_brightness to 0xff (fixes bug on X60 + where turning up brightness at max would make it loop back to + low brightness) +- getcb: Revert X60/T60 to legacy backlight controls + - The ACPI brightness patches were abandoned and obsolete. +- grub.cfg: Only load initrd.img if it exists. Add rw to linux line + (for ProteanOS) +- build: Only generate the GRUB configurations once (re-use on all + images) +- Only build 2 GRUB payload executables, re-use on all boards. +- resources/utilities/grub-assemble/gen.txtmode.sh: Use GNU BASH\ + resources/utilities/grub-assemble/gen.vesafb.sh: Use GNU BASH +- scripts (error handling): Replace exit with exit 1 (make debugging + easier) +- Move most files in CBFS to GRUB memdisk, except grub.cfg and + grubtest.cfg +- docs/release.html Add DMP vortex86ex to list of candidates. +- docs/release.html Add ThinkPad X201 to list of candidates. +- New links added to docs/security/x60\_security and + docs/security/t60\_security +- lenovobios\_secondflash: Warn if BUCTS is not present. (not a + dealbreaker. Can just pull out nvram battery/coin). +- lenovobios\_firstflash: Fail if BUCTS fails. (anti-bricking + precaution) +- Removed obnoxious warnings from flashing scripts, improved + documentation instead. +- scripts (all): add proper error checking (fail fast, fail early. Do + not continue if there are errors) +- buildrom-withgrub: rename image to boardname\_layout\_romtype.rom +- buildrom-withgrub: don't move cbfstool, execute directly +- resources/utilities/grub-assemble: add French Dvorak (BEPO) keyboard + layout. +- Documentation: add docs/hardware/x60\_keyboard.html (show how to + replace keyboard on X60/X60T) +- Documentation: major cleanup (better structure, easier to find + things) +- docs/release.html: Remove Acer CB5 from list of future candidates. + - Too many issues. Chromebooks are crippled (soldered + RAM/storage/wifi) and have too many usability issues for the + libreboot project. +- docs/gnulinux/grub\_cbfs.html Major cleanup. Usability improvements. +- flash (flashrom script): remove boardmismatch=force + - This was put there before for users upgrading from libreboot r5 + to r6, but also allows the user to flash the wrong image. For + example, the user could flash a T60 image on an X60, thus + bricking the system. It's almost certain that most people have + upgraded by now, so remove this potentially dangerous option. +- Documentation: update compatibility list for X60T LCD panels. +- docs/release.html: add note about X60 Tablet board in X60/X60s +- docs/howtos/grub\_boot\_installer.html: small corrections +- docs/howtos/grub\_boot\_installer.html: improved readability, fixed + html errors +- Documentation (macbook21 related): clean up + +Release 20141015 {#release20141015} +================ + +Machines supported in this release: +----------------------------------- + +- **Lenovo ThinkPad X60/X60s** + - You can also remove the motherboard from an X61/X61s and replace + it with an X60/X60s motherboard. An X60 Tablet motherboard will + also fit inside an X60/X60s. +- **Lenovo ThinkPad X60 Tablet** (1024x768 and 1400x1050) with + digitizer support + - See **hardware/\#supported\_x60t\_list** for list of supported LCD + panels + - It is unknown whether an X61 Tablet can have its mainboard + replaced with an X60 Tablet motherboard. +- **Lenovo ThinkPad T60** (Intel GPU) (there are issues; see below): + - See notes below for exceptions, and + **hardware/\#supported\_t60\_list** for known working LCD panels. + - It is unknown whether a T61 can have its mainboard replaced with + a T60 motherboard. + - See **future/\#t60\_cpu\_microcode**. + - T60p (and T60 variants with ATI GPU) will likely never be supported: + **hardware/\#t60\_ati\_intel** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - See **hardware/\#macbook11**. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - See **hardware/\#macbook21**. + +Changes for this release (latest changes first, earliest changes last) +---------------------------------------------------------------------- + +- Updated coreboot (git commit + 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e), the latest at the time of + writing. +- Updated SeaBIOS (git commit + 67d1fbef0f630e1e823f137d1bae7fa5790bcf4e), the latest at the time of + writing. +- Updated Flashrom (svn revision 1850), the latest at the time of + writing. +- Updated GRUB (git commit 9a67e1ac8e92cd0b7521c75a734fcaf2e58523ad), + the latest at the time of writing. +- Cleaned up the documentation, removed unneeded files. +- ec/lenovo/h8 (x60/x60s/x60t/t60): Enable + wifi/bluetooth/wwan/touchpad/trackpoint by default. +- Documentation: Updated list of T60 LCDs (Samsung LTN150XG 15" XGA + listed as non-working). +- builddeps-coreboot: Don't build libpayload (not needed. This was + leftover by mistake, when trying out the TINT payload). +- Replaced most diff files (patches) for coreboot with gerrit + checkouts (cherry-pick). +- Documentation: x60\_security.html and t60\_security.html: added + links to info about the ethernet controller (Intel 82573). +- Documentation: x60\_security.html and t60\_security.html: added + notes about DMA and the docking station. +- Documentation: configuring\_parabola.html: basic post-install steps + for Parabola GNU+Linux (helpful, since libreboot development is + being moved to Parabola at the time of writing). +- builddeps-coreboot: use 'make crossgcc-i386' instead of 'make + crossgcc'. Libreboot only targets x86 at the time of writing. +- ROM images no longer include SeaBIOS. Instead, the user adds it + afterwards. Documentation and scripts updated. +- docs/images/encrypted\_parabola.html: Notes about linux-libre-grsec +- Documentation: encrypted\_parabola.html: add tutorial for encrypted + Parabola GNU+Linux installation. +- Documentation: added more info about wifi chipsets + +6th release (pre-release, 7th beta) {#release20140911} +=================================== + +- Released 11th July 2014 (pre-release) 1st beta +- Revised (pre-release, 2nd beta) 16th July 2014 +- Revised (pre-release, 3rd beta) 20th July 2014 +- Revised (pre-release, 4th beta) 29th July 2014 +- Revised (pre-release, 5th beta) 11th August 2014 (corrected 11th + August 2014) +- Revised (pre-release, 6th beta) 3rd September 2014 +- Revised (pre-release, 7th beta) 11th September 2014 + +Machines still supported (compared to previous release): +-------------------------------------------------------- + +- **Lenovo ThinkPad X60/X60s** + - You can also remove the motherboard from an X61/X61s and replace + it with an X60/X60s motherboard. + +New systems supported in this release: +-------------------------------------- + +- **Lenovo ThinkPad X60 Tablet** (1024x768 and 1400x1050) with + digitizer support + - See **hardware/\#supported\_x60t\_list** for list of supported LCD + panels + - It is unknown whether an X61 Tablet can have its mainboard + replaced with an X60 Tablet motherboard. +- **Lenovo ThinkPad T60** (Intel GPU) (there are issues; see below) + - See notes below for exceptions, and + **hardware/\#supported\_t60\_list** for known working LCD panels. + - It is unknown whether a T61 can have its mainboard replaced with + a T60 motherboard. + - T60p (and T60 variants with ATI GPU) will likely never be supported: + **hardware/\#t60\_ati\_intel** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - See **hardware/\#macbook11**. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - See **hardware/\#macbook21**. + +Machines no longer supported (compared to previous release): +------------------------------------------------------------ + +- **All previous systems still supported!** + +Revisions for r20140911 (7th beta) (11th September 2014) +-------------------------------------------------------- + +- The changes below were made in a git repository, unlike in previous + releases. Descriptions below are copied from 'git log'. +- Update .gitignore for new dependencies. +- Use a submodule for i945-pwm. +- Don't clean packages that fail or don't need cleaning. +- Don't clean i945-pwm, it's not needed. +- Regression fix: Parabola live ISO boot issues +- Re-enable background images in ISOLINUX/SYSLINUX GRUB parser menus +- Regression fix: Re-add CD-ROM (ata0) in GRUB +- Documentation: add notes about performance penalty when using + ecryptfs. +- Documentation: Fixed spelling and grammatical errors. +- Documentation: macbook21: add new system as tested +- Documentation: macbook21: add info about improving touchpad + sensitivity +- Documentation: X60 Tablet: add more information about finger input +- Documentation: release.html: Add information about recently merged + commit in coreboot + +Revisions for r20140903 (6th beta) (3rd September 2014) +------------------------------------------------------- + +- Added modified builddeb\* scripts for Parabola GNU+Linux-libre: + buildpac, buildpac-flashrom, buildpac-bucts (courtesy of Noah + Vesely) +- Documentation: updated all relevant areas to mention use of + buildpac\* scripts for Parabola users. +- Documentation: added information showing how to enable or disable + bluetooth on the X60 +- MacBook1,1 tested! See **hardware/\#macbook11** +- Documentation: fixed typo in \#get\_edid\_panelname (get-edit + changed to get-edid) +- Documentation: added images/x60\_lcd\_change/ (pics only for now) +- Added gcry\_serpent and gcry\_whirlpool to the GRUB module list in + the 'build' script (for luks users) +- **Libreboot is now based on a new coreboot version from August 23rd, + 2014:\ + Merged commits (relates to boards that were already supported in + libreboot):** + - + - (merged already) + - (merged already) + - (merged already) + - (merged already) + - ** (merged already)** + - (merged already) + - (merged already) + - (merged already) + (text-mode patch, might enable memtest. macbook21) + - (MERGED) (remove useless + ps/2 keyboard delay from macbook21. already merged) +- These were also merged in coreboot (relates to boards that libreboot + already supported): + - (merged) + - (merged) + - (merged) + - (merged) + - (merged) + - (merged) +- Documentation: removed the section about tft\_brightness on X60 (new + code makes it obsolete) +- Removed all patches from resources/libreboot/patch/ and added new + patch: 0000\_t60\_textmode.git.diff +- Updated getcb script and DEBLOB script. +- Updated configuration files under resources/libreboot/config/ to + accomodate new coreboot version. +- Removed grub\_serial\*.cfg and libreboot\_serial\*.rom, all + configs/rom files are now unified (containing same configuration as + serial rom files from before). + - Documentation: updated \#rom to reflect the above. +- Updated GRUB to new version from August 14th, 2014. +- Unified all grub configurations for all systems to a single grub.cfg + under resources/grub/config/ +- Updated flashrom to new version from August 20th, 2014 +- Added getseabios and builddeps-seabios (builddeps and getall were + also updated) + - Added instructions to 'buildrom-withgrub' to include + bios.bin.elf and vgaroms/vgabios.bin from SeaBIOS inside the + ROM. +- Added seabios (and sgavgabios) to grub as payload option in menu +- Disabled serial output in Memtest86+ (no longer needed) to speed up + tests. + - MemTest86+ now works properly, it can output on the laptop + screen (no serial port needed anymore). +- Added getgrubinvaders, builddeps-grubinvaders scripts. Added these + to getall and builddeps. + - Added [GRUB Invaders](http://www.coreboot.org/GRUB_invaders) + menu entry in resources/grub/config/grub.cfg +- Added rules to builddeps-coreboot to build libpayload with + TinyCurses. (added appropriate instructions to cleandeps script). +- Commented out lines in resources/grub/config/grub.cfg for loading + font/background (not useful anymore, now that GRUB is in text-mode). +- Commented out lines in buildrom-withgrub that included + backgrounds/fonts (not useful anymore, now that GRUB is in + text-mode). +- Added resources/utilities/i945-pwm/ (from + git://git.mtjm.eu/i945-pwm), for debugging acpi brightness on i945 + systems. + - Added instructions for it in builddeps, builddeps-i945pwm, + builddeb and cleandeps +- 'build' script: removed the parts that generated sha512sum + manifests (not needed, since release tarballs are GPG-signed) +- 'build' script: removed the parts that generated libreboot\_meta + directory (not needed anymore, since \_meta will be hosted in git) + - Updated \#build\_meta (and other parts of documentation) to + accomodate this change. +- Documentation: simplified (refactored) the notes in \#rom +- 'build' script: removed the parts that generated libreboot\_bin + and added them to a new script: 'build-release' + - Documentation: \#build updated to reflect the above. +- ~~Added all gcry\_\* modules to grub (luks/cryptomount): + gcry\_arcfour gcry\_camellia gcry\_crc gcry\_dsa gcry\_md4 + gcry\_rfc2268 gcry\_rmd160 gcry\_seed gcry\_sha1 gcry\_sha512 + gcry\_twofish gcry\_blowfish gcry\_cast5 gcry\_des gcry\_idea + gcry\_md5 gcry\_rijndael gcry\_rsa gcry\_serpent gcry\_sha256 + gcry\_tiger gcry\_whirlpool~~ +- Added GNUtoo's list of GRUB modules (includes all of the gcry\_\* + modules above), cryptomount should be working now. +- Removed builddeb-bucts and builddeb-flashrom, merged them with + builddeb ( updated accordingly) +- Removed buildpac-bucts and buildpac-flashrom, merged them with + buildpac ( updated accordingly) +- Renamed buildpac to deps-parabola ( updated accordingly) +- Documentation: removed all parts talking about build dependencies, + replaced them with links to \#build\_dependencies +- Documentation: emphasized more strongly on the documentation, the + need to re-build bucts and/or flashrom before flashing a ROM image. +- build-release: flashrom, nvramtool, cbfstool and bucts are no longer + provided pre-compiled in binary archives, and are now in source form + only. (to maximize distro compatibility). +- 'build' script: replaced grub.elf assembly instructons, it is now + handled by a utility added under resources/utilities/grub-assemble +- Moved resources/grub/keymap to + resources/utilities/grub-assemble/keymap, and updated that utility + to use it +- Documentation: removed useless links to pictures of keyboard layouts + and unmodified layouts. +- Removed all unused fonts from dejavu-fonts-ttf-2.34/ directory +- 'buildrom-withgrub' script: updated it to create 2 sets of ROMs + for each system: one with text-mode, one with coreboot framebuffer. +- Documentation: updated \#rom to reflect the above +- Deleted unused README and COPYING file from main directory +- Removed some rm -Rf .git\* instructions from the get\* scripts and + moved them to build-release script +- Split up default grub.cfg into 6 parts: + extra/{common.cfg,txtmode.cfg,vesafb.cfg} and + menuentries/{common.cfg,txtmode.cfg,vesafb.cfg} + - buildrom-withgrub script uses these to generate the correct + grub.cfg for each type of configuration. +- grub\_memdisk.cfg (used inside grub.elf) now only loads grub.cfg + from cbfs. It no longer enables serial output or sets prefix. + (menuentries/common.cfg does instead) +- resources/grub/config/extra/common.cfg, added: + - insmod instructions to load those modules: nativedisk, ehci, + ohci, uhci, usb, usbserial\_pl2303, usbserial\_ftdi, + usbserial\_usbdebug + - set prefix=(memdisk)/boot/grub + - For native graphics (recommended by coreboot wiki):\ + gfxpayload=keep\ + terminal\_output \--append gfxterm + - Play a beep on startup:\ + play 480 440 1 +- Documentation: updated gnulinux/grub\_cbfs.html to make it safer + (and easier) to follow. + +Corrections to r20140811 (5th beta) (11th August 2014) +------------------------------------------------------ + +- Fixed typo where revision list for 5th beta was listed as March 11th + 2014, when in fact it was August 11th 2014 +- Fixed incorrect grub.cfg that was actually placed in + resources/grub/config/x60/grub\_usqwerty.cfg which broke the default + GRUB menu entry on X60 + +Revisions for r20140811 (5th beta) (11th August 2014) +----------------------------------------------------- + +- build: added 'luks', 'lvm', 'cmosdump' and 'cmostest' to the + list of modules for grub.elf +- Documentation: added pics showing T60 unbricking (still need to + write a tutorial) +- build: include cmos.layout + (coreboot/src/mainboard/manufacturer/model/cmos.layout) files in + libreboot\_bin +- Documentation: added **install/x60tablet\_unbrick.html** +- Documentation: added **install/t60\_unbrick.html** +- Documentation: added **install/t60\_lcd\_15.html** +- Documentation: added **install/t60\_security.html** +- Documentation: added **install/t60\_heatsink.html** +- Documentation: Renamed RELEASE.html to release.html +- Documentation: removed pcmcia reference in x60\_security.html (it's + cardbus) +- Documentation: added preliminary information about randomized seal + (for physical intrusion detection) in x60\_security.html and + t60\_security.html +- Documentation: added preliminary information about + preventing/mitigating cold-boot attack in x60\_security.html and + t60\_security.html +- Documentation: added info to \#macbook21 warning about issues with + macbook21 +- Documentation: X60/T60: added information about checking custom ROMs + using dd to see whether or not the top 64K region is duplicated + below top or not. Advise caution about this in the tutorial that + deals with flashing on top of Lenovo BIOS, citing the correct dd + commands necessary if it is confirmed that the ROM has not been + applied with dd yet. (in the case that the user compiled their own + ROMs from libreboot, without using the build scripts, or if they + forgot to use dd, etc). +- Split resources/libreboot/patch/gitdiff into separate patch files + (getcb script updated to accomodate this change). +- Re-added .git files to bucts +- Fixed the oversight where macbook21\_firstflash wasn't included in + binary archives +- Release archives are now compressed using .tar.xz for better + compression + +Revisions for r20140729 (4th beta) (29th July 2014) +--------------------------------------------------- + +- Documentation: improved (more explanations, background info) in + docs/security/x60\_security.html (courtesy of Denis Carikli) +- MacBook2,1 tested (confirmed) +- macbook21: Added script 'macbook21\_firstflash' for flashing + libreboot while Apple EFI firmware is running. +- Documentation: macbook21: added software-based flashing instructions + for flashing libreboot while Apple EFI firmware is running. +- Reduced size of libreboot\_src.tar.gz: + - Removed .git and .gitignore from grub directory + (libreboot\_src); not needed. Removing them reduces the size of + the archive (by a lot). GRUB development should be upstream. + - Removed .git and .gitignore from bucts directory + (libreboot\_src); not needed. Removing them reduces the size of + the archive. bucts development should be upstream. + - Removed .svn from flashrom directory (libreboot\_src); not + needed. Removing it reduces the size of the archive. flashrom + development should be upstream. +- Added ROMs with Qwerty (Italian) layout in GRUB + (libreboot\*itqwerty.rom) +- Added resources/utilities/i945gpu/intel-regs.py for debugging issues + related to LCD panel compatibility on X60 Tablet and T60. (courtesy + of [Michał Masłowski](http://mtjm.eu)) + +Revisions for r20140720 (3rd beta) (20th July 2014) +--------------------------------------------------- + +- Fixed typo that existed in 2nd beta where the release date of the + 2nd beta was listed as being in year 2016, when in actual fact it + was 2014. +- Documentation: added (preliminary) details about (rare) buggy CPUs + on the ThinkPad T60 that were found to fail (instability, kernel + panics, etc) without the microcode updates. +- Documentation: added docs/hardware/x60\_heatsink.html for showing + how to change the heatsink on the Thinkpad X60 +- Added ROM images for Azerty (French) keyboard layout in GRUB + (courtesy of Olivier Mondoloni) +- Tidied up some scripts: + - ~~Re-factored those scripts (made easier to read/maintain): + build-x60, build-x60t, build-t60, build-macbook21~~ + - ~~Reduced the number of grub configs to 2 (or 1, for macbook21), + the build scripts now generate the other configs at build + time.~~ + - Deleted build-x60, build-x60t, build-t60, build-macbook21 and + replaced with intelligent (generic) buildrom-withgrub script + - Updated build to use buildrom-withgrub script for building the + ROM images. + - coreboot.rom and coreboot\_serial.rom renamed to + coreboot\_usqwerty.rom and coreboot\_serial\_usqwerty.rom + - coreboot\_dvorak and coreboot\_serial\_dvorak.rom renamed to + coreboot\_usdvorak.rom and coreboot\_serial\_usdvorak.rom + - Renamed coreboot\*rom to libreboot\*rom + - Made flash, lenovobios\_firstflash and lenovobios\_secondflash + scripts fail if the specified file does not exist. + - Updated all relevant parts of the documentation to reflect the + above. +- Replaced background.png with background.jpg. added gnulove.jpg. + (resources/grub/background/) +- Updated buildrom-withgrub to use background.jpg instead of + background.png +- Updated buildrom-withgrub to use gnulove.jpg aswell +- Updated resources/grub/config/macbook21/grub\*cfg to use gnulove.jpg + background. +- Updated resources/grub/config/{x60,t60,x60t}/grub\*cfg to use + background.jpg background. +- Documentation: updated docs/\#grub\_custom\_keyboard to be more + generally useful. +- nvramtool: + - Updated builddeps-coreboot script to build it + - Updated build script to include it in libreboot\_bin +- Documentation: added docs/security/x60\_security.html (security + hardening for X60) + +Revisions for r20140716 (2nd beta) (16th July 2014) +--------------------------------------------------- + +- Deleted all git-related files from the coreboot directory. This was + necessary because with those it is possible to run 'git diff' + which shows the changes made in the form of a patch (diff format); + this includes the blobs that were deleted during deblobbing. + +Revisions for r20140711 (1st beta) (11th July 2014) +--------------------------------------------------- + +- Initial release (new coreboot base, dated 1st June 2014. See + 'getcb' script for reference) +- DEBLOBBED coreboot +- Removed the part from memtest86+ 'make' where it tried to connect + to some scp server while compiling. (commented out line 24 in the + Makefile) +- X60 now uses a single .config (for coreboot) +- X60 now uses a single grub.cfg (for grub memdisk) +- X60 now uses a single grub.elf (payload) +- Added new native graphics code for X60 (replaces the old 'replay' + code) from Vladimir Serbinenko: 5320/9 from review.coreboot.org +- T60 is now supported, with native graphics. (5345/4 from + review.coreboot.org, cherry-picked on top of 5320/9 checkout) +- Added macbook2,1 support (from Mono Moosbart and Vladimir + Serbinenko) from review.coreboot.org (see 'getcb' script to know + how that was done) + - Documentation: added information linking to correct page and + talking about which models are supported. + - Added resources/libreboot/config/macbook21config + - macbook21: Added 'build-macbook21' script and linked to it in + 'build' (ROMs included under bin/macbook21/) + - macbook21: Removed dd instructions from build-macbook21 script + (macbook21 does not need bucts when flashing libreboot while + Apple EFI firmware is running) + - Documentation: Added macbook21 ROMs to the list of ROMs in + docs/\#rom + - Documentation: Write documentation linking to Mono Moosbart's + macbook21 and parabola page (and include a copy) +- Documentation: added a copy of Mono's Parabola install guide (for + macbook21 with Apple EFI firmware) and linked in in main index. +- Documentation: added a copy of Mono's Coreboot page (for macbook21) + and linked it in main index. +- T60: Copy CD option from the grub.cfg files for T60 \*serial\*.rom + images into the grub configs for non-serial images. (T60 laptops have + CD/DVD drive on main laptop) +- macbook21: remove options in build-macbook21 for \*serial\*.rom + (there is no dock or serial port available for macbook21) +- Added patches for backlight controls on X60 and T60 with help from + Denis Carikli (see ./resources/libreboot/patch/gitdiff and ./getcb + and docs/i945\_backlight.md) + - Documentation: added docs/i945\_backlight.html showing how + backlight controls were made to work on X60/T60 +- Documentation: Added info about getting LCD panel name based on EDID + data. + - Documentation: Added a link to this from the list of supported + T60 laptopss and LCD panels for T60 (so that the user can check + what LCD panel they have). +- X60/T60: Merged patches for 3D fix (from Paul Menzel) when using + kernel 3.12 or higher (see ./resources/libreboot/patch/gitdiff and + ./getcb) + - based on 5927/11 and 5932/5 from review.coreboot.org +- Improved thinkpad\_acpi support (from coreboot ): xsensors shows + more information. + - From 4650/29 in review.coreboot.org (merged in coreboot + 'master' on June 1st 2014) +- Merged changes for digitizer (X60 Tablet) and IR (X60 and T60) based + on 5243/17, 5242/17 and 5239/19 from review.coreboot.org + - (see ./resources/libreboot/patch/gitdiff and ./getcb) +- Documentation: added information about building flashrom using + 'builddeps-flashrom' script. +- Re-created resources/libreboot/config/x60config +- Re-created resources/libreboot/config/t60config +- Added 'x60tconfig' in resources/libreboot/config (because X60 + Tablet has different information about serial/model/version in + 'dmidecode') + - Added 'build-x60t' script + - Updated 'build' script to use 'build-x60t' + - Documentation: added to \#config section the section + \#config\_x60t (libreboot configuration and dmidecode info) + - Documentation: added x60t ROMs to the list of ROMs +- Tidied up the 'builddeps' script (easier to read) +- Tidied up the 'cleandeps' script (easier to read) +- Annotated the 'buildall' script +- Added 'getcb' script for getting coreboot revision used from git, + and patching it. +- Added 'getgrub' script for getting the GRUB revision used from + git, and patching it. +- Added 'getmt86' script for getting the memtest86+ version used, + and patching it. +- Added 'getbucts' script for getting the bucts version used. +- Added 'getflashrom' script for getting the flashrom version used, + and patching it +- Added 'getall' script which runs all of the other 'get' scripts. +- Add instructions to the 'build' script to prepare + libreboot\_meta.tar.gz + - New archive: libreboot\_meta.tar.gz - minimal archive, using the + 'get' scripts to download all the dependencies (coreboot, + memtest, grub and so on). +- Documentation: added information about where 'build' script + prepares the libreboot\_meta.tar.gz archive. +- Documentation: added information about how to use the 'get' + scripts in libreboot\_meta.tar.gz (to generate + libreboot\_src.tar.gz) + - Documentation: mention that meta doesn't create libreboot\_src/ + directory, but that libreboot\_meta itself becomes the same. + - Documentation: advise to rename libreboot\_meta to + libreboot\_src after running 'getall'. +- Annotated the 'builddeb' script, to say what each set of + dependencies are for. +- Separated bucts/flashrom builddeb sections into separate scripts: + builddeb-flashrom, builddeb-bucts. +- Documentation: Updated relevant parts based on the above. +- Added instructions to 'build' script for including builddeb-bucts + and builddeb-flashrom in libreboot\_bin +- Updated flashrom checkout (r1822 2014-06-16) from SVN + (http://flashrom.org/Downloads). + - Updated flashing instructions in docs/ for new commands needed + (Macronix chip on X60/T60) + - For X60/T60 (flashrom): Patched + flashchips.c\_lenovobios\_macronix and + flashchips.c\_lenovobios\_sst executables for SST/macronix + (included in resources/flashrom/patch) + - Updated builddeps to build flashrom\_lenovobios\_sst and + flashrom\_lenovobios\_macronix, for X60/T60 users with Lenovo + BIOS + - moved the flashrom build instructions from 'builddeps' and put + them in 'builddeps-flashrom', excecuting that from + 'builddeps'. + - Added builddeps-flashrom to libreboot\_bin.tar.gz +- flashrom: added patched flashchips.c to resources/flashrom/patch + (automatically use correct macronix chip on libreboot, without using + '-c' switch) + - removed 'MX25L1605' and 'MX25L1605A/MX25L1606E' entries in + flashchips.c for the patched version of flashchips.c + - added instructions to 'builddeps-flashrom' to automatically + use this modified flashchips.c in the default build +- Added builddeb to libreboot\_bin.tar.gz +- Moved 'bucts' build instructions from builddeps to builddeps-bucts + - builddeps now runs 'builddeps-bucts' instead + - Added 'builddeps-bucts' to libreboot\_bin.tar.gz + - Documentation: Added information about using 'builddep-bucts' + to build the BUC.TS utility. +- Added 'lenovobios\_firstflash' and 'lenovobios\_secondflash' + scripts + - Added instructions to 'build' script for including those files + in libreboot\_bin + - Documentation: Add tutorial for flashing while Lenovo BIOS is + running (on X60/T60) +- Added 'flash' script (make sure to run builddeps-flashrom first) + which (while libreboot is already running) can use flashrom to flash + a ROM + - eg: "sudo ./flash bin/x60/coreboot\_serial\_ukdvorak.rom" + equivalent to "sudo ./flashrom/flashrom -p internal -w + bin/x60/coreboot\_uk\_dvorak.rom" + - updated 'build' script to include the 'flash' script in + libreboot\_bin.tar.gz +- Documentation: replaced default flashrom tutorial to recommend the + 'flash' script instead. +- Re-add cbfstool source code back into libreboot\_bin.tar.gz, as + cbfstool\_standalone + - Patched that version to work (able to be built and used) without + requiring the entire coreboot source code. + - Created patched version of the relevant source files and added + it into resources/cbfstool/patch + - see coreboot/util/cbfstool/rmodule.c and then the patched + version in resources/cbfstool/patch/rmodule.c + - see coreboot/src/include/rmodule-defs.h and the rule in + 'build' for including this in + ../libreboot\_bin/cbfstool\_standalone + - Added instructions to 'build' script for applying this patch + to the cbfstool\_standalone source in libreboot\_bin + - Added instructions to 'build' script for then re-compiling + cbfstool\_standalone in libreboot\_bin after applying the patch + - Added a 'builddeps-cbfstool' script (in src, but only used in + bin and put in bin by 'build') that compiles + cbfstool\_standalone in libreboot\_bin (make), moves the + cbfstool and rmodtool binaries into libreboot\_bin/ and then + does 'make clean' in libreboot\_bin/cbfstool\_standalone + - Updated the 'build' script to put 'builddeps-cbfstool' in + libreboot\_bin + - Updated the 'build' script in the cbfstool (standalone) part + to accomodate the above. + - Documentation: added notes about cbfstool (standalone) in + libreboot\_bin +- Documentation: made docs/gnulinux/grub\_cbfs.html slightly easier to + follow. +- Annotate the 'build\*' scripts with 'echo' commands, to help the + user understand what it actually happening during the build process. +- Documentation: added information about how 'dmidecode' data was + put in the coreboot configs + - Documentation: In fact, document how the 'config' files in + resources/libreboot/config/ were created +- Documentation: Added information about which ThinkPad T60 laptops are + supported, and which are not. +- Documentation: added information about LCD inverters (for upgrading + the LCD panel on a T60 14.1' XGA or 15.1' XGA) + - it's FRU P/N 41W1478 (on T60 14.1") so this was added to the + docs. + - it's P/N 42T0078 FRU 42T0079 or P/N 41W1338 (on T60 15.1") so + this was added to the docs. +- Documentation: added information about names of LCD panels for T60 + to the relevant parts of the documentation. +- Documentation: added information (with pictures) about the + differences between T60 with Intel GPU and T60 with ATI GPU. +- Documentation: added pictures of keyboard layouts (US/UK + Qwerty/Dvorak) to the ROM list, to let the user compare with their + own keyboard. +- Move the coreboot build instructions in 'builddeps' into + 'builddeps-coreboot' and link it in 'builddeps' + - Link to 'builddeps-coreboot' in final stage of 'getcb' +- Move GRUB build instructions from 'builddeps' into + 'builddeps-grub', link from 'builddeps' + - Link to 'builddeps-grub' in final stage of 'getgrub' +- Move MemTest86+ build instructions from 'builddeps' into + 'builddeps-memtest86', link from 'builddeps' + - Link to 'builddeps-memtest86' in final stage of 'getmt86' +- made 'build' script put resources/ directory in libreboot\_bin, to + make builddeps-flashrom work in libreboot\_bin +- Removed instructions for building source code in the 'get' script + (they don't really belong there) +- Added libfuse-dev and liblzma-dev to the list of GRUB dependencies + in 'builddeb' script. +- Converted the 'RELEASE' file to 'docs/RELEASE.html' +- Added those dependencies to builddeb script (for GRUB part): gawk + libdevmapper-dev libtool libfreetype6-dev +- Added to build script the instruction at the end to create a + sha512sum.txt with a file manifest plus checksums. +- Deleted the RELEASE and BACKPORT files (no longer needed) +- Documentation: added information about X60/T60 dock (ultrabase x6 + and advanced mini dock) to relevant sections. + - Added to docs/\#serial + +Release 20140622 (5th release) {#release20140622} +============================== + +- 7th March 2014 +- revised 22nd June 2014 + +Officially supported +-------------------- + +- ThinkPad X60 +- ThinkPad X60s + +Revision (22nd June 2014 - extra) +--------------------------------- + +- Documentation: added X60 Unbricking tutorial +- Documentation: added info about enabling or disabling wifi +- Documentation: added info about enabling or disabling trackpoint + +Revision (22nd June 2014 - extra) +--------------------------------- + +- Documentation: Improved the instructions for using flashrom +- Documentation: Improved the instructions for using cbfstool (to + change the default GRUB menu) +- Documentation: Numerous small fixes. + +Revision notes (22nd June 2014) +------------------------------- + +- updated GRUB (git 4b8b9135f1676924a8458da528d264bbc7bbb301, 20th + April 2014) +- Made "DeJavu Sans Mono" the default font in GRUB (fixes border + corruption). +- re-added background image in GRUB (meditating GNU) +- added 6 more images: + - coreboot\_ukqwerty.rom (UK Qwerty keyboard layout in GRUB) + - coreboot\_serial\_ukqwerty.rom (UK Qwerty keyboard layout in + GRUB) + - coreboot\_dvorak.rom (US Dvorak keyboard layout in GRUB) + - coreboot\_serial\_dvorak.rom (US Dvorak keyboard layout in GRUB) + - coreboot\_ukdvorak.rom (UK Dvorak keyboard layout in GRUB) + - coreboot\_serial\_ukdvorak.rom (UK Dvorak keyboard layout in + GRUB) + - (coreboot.rom and coreboot\_serial.rom have US Qwerty keyboard + layout in GRUB, as usual) +- improved the documentation: + - removed FLASH\_INSTRUCTION and README.powertop and merged them + with README + - removed obsolete info from README and tidied it up + - deleted README (replaced with docs/) +- tidied up the menu entries in GRUB +- tidied up the root directory of X60\_source/, sorted more files into + subdirectories +- improved the commenting inside the 'build' script (should make + modifying it easier) +- Renamed X60\_binary.tar.gz and X60\_source.tar.gz to + libreboot\_bin.tar.gz and libreboot\_src.tar.gz, respectively. +- Replaced "GNU GRUB version" with "FREE AS IN FREEDOM" on GNU + GRUB start screen. +- Added sha512.txt files in libreboot\_src and libreboot\_bin. (inside + the archives) +- Added libreboot\_bin.tar.gz.sha512.txt and + libreboot\_src.tar.gz.sha512.txt files (outside of the archives) + +Revision notes (11th June 2014): +-------------------------------- + +- removed 'CD' boot option from coreboot.rom (not needed) +- removed 'processor.max\_cstate=2' and 'idle=halt' options (see + README.powertop file) + +Revision notes (5th June 2014): +------------------------------- + +- added backlight support (Fn+Home and Fn+End) on X60 +- fixed broken/unstable 3D when using kernel 3.12 or higher +- (see 'BACKPORT' file) + +Revision notes (9th March 2015): +-------------------------------- + +- recreated coreboot config from scratch +- GRUB loads even faster now (less than 2 seconds). +- Total boot time reduced by further \~5 seconds. +- Added crypto and cryptodisk modules to GRUB +- cbfstool now included in the binary archives + +Development notes +----------------- + +- Binary archive now have 2 images: + - With serial output enabled and memtest86+ included (debug level + 8 in coreboot) + - With serial output disabled and memtest86+ excluded (faster boot + speeds) (debugging disabled) +- Reduced impact on battery life: + - 'processor.max\_cstate=2' instead of 'idle=halt' for booting + default kernel +- coreboot.rom (faster boot speeds, debugging disabled): + - Disabled coreboot serial output (Console-> in "make + menuconfig") + - Set coreboot debug level to 0 instead of 8 (Console-> in + "make menuconfig") + - Changed GRUB timeout to 1 second instead of 2 (in grub.cfg + - Removed background image in GRUB. + - Removed memtest86+ payload (since it relies on serial output) +- coreboot\_serial.rom (slower boot speeds, debugging enabled): + - Boot time still reduced, but only by \~2 seconds + - has the memtest86+ payload included in the ROM + - has serial port enabled. How this is achieved (from + X60\_source): Turn on debugging level to 8, and enable serial + output +- (in Console-> in coreboot "make menuconfig") +- (and build with grub\_serial.cfg and grub\_memdisk\_serial.cfg) + +Release 20140221 (4th release) {#release20140221} +============================== + +- 21st February 2014 + +Officially supported +-------------------- + +- ThinkPad X60 +- ThinkPad X60s + +Development notes +----------------- + +- Removed SeaBIOS (redundant) +- New GRUB version (2.02\~beta2) + - Fixes some USB issues + - Includes ISOLINUX/SYSLINUX parser +- New grub.cfg +- Removed useless options: + - options for booting sda 2/3/4 + - seabios boot option +- Added new menu entries: + - Parse ISOLINUX config (USB) + - Parse ISOLINUX config (CD) + - Added 'cat' module for use on GRUB command line. +- "set pager=1" is set in grub.cfg, for less-like functionality + +The "Parse" options read ./isolinux/isolinux.cfg on a CD or USB, and +automatically converts it to a grub config and switches to the boot menu +of that distro. This makes booting ISOs \*much\* easier than before. + +r20131214 (3rd release) {#release20131214} +======================= + +- 14th December 2013 + +Supported: +---------- + +- ThinkPad X60 +- ThinkPad X60s + +Development notes +----------------- + +- Added SeaBIOS payload to GRUB2 (for booting USB drives) +- new grub.cfg + +r20131213 (2nd release) {#release20131213} +======================= + +- 13th December 2013 + +Supported: +---------- + +- ThinkPad X60 +- ThinkPad X60s + +Development notes +----------------- + +- added background image to GRUB2 +- added memtest86+ payload to grub2 +- improvements to the documentation +- new grub.cfg + +r20131212 (1st release) {#release20131212} +======================= + +- 12th December 2013 + +Supported: +---------- + +- ThinkPad X60 +- ThinkPad X60s + +Development notes +----------------- + +- initial release +- source code deblobbed + +Copyright © 2014, 2015, 2016 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [fdl-1.3.md](fdl-1.3.md) diff --git a/i18n/fr_FR/docs/bsd/freebsd.md b/i18n/fr_FR/docs/bsd/freebsd.md new file mode 100644 index 00000000..ef7163fd --- /dev/null +++ b/i18n/fr_FR/docs/bsd/freebsd.md @@ -0,0 +1,150 @@ +--- +title: Comment installer FreeBSD sur un système Libreboot +x-toc-enable: true +... + +Cette section se rapporte à la préparation, au démarrage et à l'installation +de FreeBSD sur votre système libreboot, en utilisant rien de plus qu'une clef +USB (et *dd*). Ça a été seulement testé sur un Lenovo ThinkPad x200. + +C'est attendu que vous utilisiez le mode texte dans libreboot (txtmode images), pour +le début du processus de démarrage dans FreeBSD. *Démarrer l'installateur résulte en +un affichage rouge clignotant, et ne démarre pas.* + +Les remerciements vont à ioxcide dans [ce billet Reddit](https://www.reddit.com/r/BSD/comments/53jt70/libreboot_and_bsds/) +pour les instructions initiales. + +À FAIRE: tester FreeBSD de manière plus extensive, et s'assurer qu'il est fonctionnel (et corriger +celà le cas échéant). Les instructions sont données ici pour démarrer et installer FreeBSD, mais +nous ne sommes par sûr si oui ou non c'est en ce moment complétement compatible avec libreboot. + +* Cette section est seulement pour la charge utile GRUB. Pour depthcharge (utilisée sur +les appareils CrOs dans libreboot), les instructions attendent d'être écrite.* + +freebsd.img est l'image d'installation pour FreeBSD. Adaptez concordément +le nom de fichier, pour n'importe quelle version de FreeBSD que vous utilisez. + + +Préparer la clef USB (dans FreeBSD) +---------------------------------- + +[Cette page](https://www.freebsd.org/doc/handbook/bsdinstall-pre.html) sur le +site web de FreeBSD montre comment créer une clef USB démarrable pour installer +FreeBSD. Utilisez le *dd* sur cette page. + +Préparer la clef USB (dans NetBSD) +--------------------------------- + +[Cette page](https://wiki.netbsd.org/tutorials/how_to_install_netbsd_from_an_usb_memory_stick/) +sur le site web de NetBSD montre comment créer une clef USB NetBSD démarrable, depuis NetBSD même. +Vous devriez utilisé la méthode *dd* documentée sur cette page; vous pouvez utiliser celle-ci avec +n'importe quelle ISO (image disque), incluant FreeBSD. + +Préparer la clef USB (sur LibertyBSD ou OpenBSD) +------------------------------------------------ + +Si vous avez téléchargé votre ISO sur un système LibertyBSD ou OpenBSD, voici +comment créer une clef USB FreeBSD démarrable: + +Connectez la clef USB. Regardez la sortie de dmesg: + + $ dmesg | tail + +Vérifiez et confirmer de quel USB il s'agit si vous pensez par exemple que c'est sd3: + + $ disklabel sd3 + +Vérifiez qu'elle n'a pas été montée automatiquement. Sinon, on l'éjecte. Par exemple : + + $ doas umount /dev/sd3i + +dmesg vous a dit quel appareil/bloc c'était, donc on peut maintenant écrire par dessus +l'installateur FreeBSD grâce à dd. Par exemple : + + $ doas dd if=freebsd.img of=/dev/rsdXc bs=1M; sync + +Vous devriez être maintenant capable de démarrer l'installeur depuis votre clef USB. +Continuez à lire pour apprendre comme faire ceci. + +Préparer la clef USB (dans GNU+Linux) +------------------------------------ + +Si vous avez téléchargé votre ISO sur système GNU+Linux, voici comment créer la +clef USB NetBSD démarrable: + +Connectez la clef USB. Vérifiez la sortie de dmesg: + + $ dmesg + +Jetez un coup d'oeil à lsblk pour voir de quel disque il s'agit: + + $ lsblk + +Vérifiez qu'il n'a pas été monté automatiquement et si c'était le cas, démontez-le. Par example: + + $ sudo umount /dev/sdX\* + # umount /dev/sdX\* + +dmesg vous a dit de quel appareil il s'agit. Écraser en écriture le disque en écrivant l'ISO de la distrib dessus grâce à dd. Par example: + + $ sudo dd if=freebsd.img of=/dev/sdX bs=8M; sync + # dd if=freebsd.img of=/dev/sdX bs=8M; sync + +Vous devriez être maintenant capable de démarrer l'installateur depuis votre clef USB. +Continuez à lire pour des informations sur comment faire celà. + + +Installer FreeBSD sans le chiffrement de tout le disque +----------------------------------------------- + +Tapez sur C pour avoir accès à la console GRUB. + + grub> kfreebsd (usb0,gpt3)/boot/kernel/kernel + grub> set FreeBSD.vfs.mountfrom=ufs:/dev/da1p3\ + grub> boot + +Ça fera démarrer dans l'installateur FreeBSD. Suivez la procédure d'installation +normale pour FreeBSD. + +Installer FreeBSD avec le chiffrement de tout le disque +-------------------------------------------- + +TODO + +Démarrer +------- + +TODO + +Configurer Grub +---------------- + +TODO + +Dépannage +=============== + +La majorité de ces problèmes arrivent lors de l'utilisation de libreboot avec le 'text mode' +de coreboot au lieu du framebuffer de coreboot. Ce mode est utile pour démarrer +des charges +utiles comme memtest86+ qui s'attendent au mode texte, mais pour NetBSD celà peut être +problématique car il essaye d'alterner sur un framebuffer qui n'existe pas. + +Dans la plupart des cas, vous devriez utiliser les images ROM vesafb. Exemple du nom de fichier: +libreoot\_ukdvorak\_vesafb.rom. + +Ne démarrera pas... quelque chose à propos d'un fichier non trouvé +--------------------------------------------- + +Vos noms d'appareils (p.e usb0, usb1, sd0, sd1, wd0, ahci0, hd0, etc) et nombre +peuvent +différer. Utilisez l'autocomplétion de TAB. + +Copyright © 2016 Leah Rowe \ +Copyright © 2016 Scott Bonds \ + +Permission est donnée de copier, distribuer et/ou modifier ce document +sous les termes de la Licence de documentation libre GNU version 1.3 ou +quelconque autre versions publiées plus tard par la Free Software Foundation +sans Sections Invariantes, Textes de Page de Garde, et Textes de Dernière de Couverture. +Une copie de cette license peut être trouvé dans [fdl-1.3.md](fdl-1.3.md). diff --git a/i18n/fr_FR/docs/bsd/index.md b/i18n/fr_FR/docs/bsd/index.md new file mode 100644 index 00000000..8864b5a1 --- /dev/null +++ b/i18n/fr_FR/docs/bsd/index.md @@ -0,0 +1,20 @@ +--- +title: Projets BSD +... + +Cette section se rapporte sur le 'comment' des projets BSD: préparer des USBs démarrables, changer +le menu par défaut de GRUB et ainsi de suite. + +* Cette section est seulement pour la charge utile GRUB. Pour depthcharge, +les instructions attendent d'être écrite.* + +- [Comment installer NetBSD sur un système libreboot](netbsd.msd) +- [Comment installer LibertyBSD ou OpenBSD sur un système libreboot](openbsd.md) +- [Comment installer FreeBSD sur un système libreboot](freebsd.md) + +Copyright © 2016 Scott Bonds \ +Permission est donnée de copier, distribuer et/ou modifier ce document +sous les termes de la Licence de documentation libre GNU version 1.3 ou +quelconque autre versions publiées plus tard par la Free Software Foundation +sans Sections Invariantes, Textes de Page de Garde, et Textes de Dernière de Couverture. +Une copie de cette license peut être trouvé dans [fdl-1.3.md](fdl-1.3.md). diff --git a/i18n/fr_FR/docs/bsd/netbsd.md b/i18n/fr_FR/docs/bsd/netbsd.md new file mode 100644 index 00000000..b7354f1f --- /dev/null +++ b/i18n/fr_FR/docs/bsd/netbsd.md @@ -0,0 +1,165 @@ +--- +title: Comment installer NetBSD sur un système Libreboot ? +x-toc-enable: true +... + +Cette section concernent la préparation, le démarrage et l'installation de +NetBSD sur votre système Libreboot en utilisant rien de plus qu'une clef USB (et *dd*). +Ça a seulement été testé sur un ThinkPad X60 librebooté. + +C'est attendu que vous utilisiez le mode texte dans libreboot (txtmode images), pour +le début du processus de démarrage dans NetBSD.*La veille/hibernation est dysfonctionnelle +d'après au moins un utilisateur.* + +Grâce à ioxcide dans [ce post Reddit](https://www.reddit.com/r/BSD/comments/53jt70/libreboot_and_bsds/) +pour les instructions initiales. + +*Cette section est seulement pour la charge utile GRUB. Pour depthcharge (utilisé sur les appareils +ChromeOS dans libreboot) des instructions attendent encore d'être écrites dans la documentation de libreboot.* + +netbsd.iso est l'image d'installation pour NetBSD. Adaptez le nom de fichier +en accordance selon votre version de NetBSD. + +Préparer la clef USB (dans NetBSD) +--------------------------------- + +[Cette page](https://wiki.netbsd.org/tutorials/how_to_install_netbsd_from_an_usb_memory_stick/) +sur le site web de NetBSD montre comment créer une clef USB NetBSD démarrable +depuis NetBSD même. Vous devriez utiliser la méthode *dd* documentée là-bas. + +Préparer la clef USB (dans FreeBSD) +---------------------------------- +[Cette page](https://www.freebsd.org/doc/handbook/bsdinstall-pre.html) sur le +site web FreeBSD montre comment créer une clef USB démarrable pour installer FreeBSD. +Utilisez le *dd* sur cette page. Vous pouvez aussi utiliser les mêmes instructions avec une +image ISO de NetBSD. + +Préparer la clef USB (sur LibertyBSD ou OpenBSD) +------------------------------------------------ + +Si vous avez téléchargé votre ISO sur un système LibertyBSD ou OpenBSD, voici +comment créer une clef USB NetBSD démarrable: + +Connectez la clef USB. Regardez la sortie de dmesg: + + $ dmesg | tail + +Vérifiez et confirmer de quel USB il s'agit si vous pensez par exemple que c'est sd3: + + $ disklabel sd3 + +Vérifiez qu'elle n'a pas été montée automatiquement. Sinon, on l'éjecte. Par exemple : + + $ doas umount /dev/sd3i + +dmesg vous a dit quel appareil/bloc c'était, donc on peut maintenant écrire par dessus +l'installateur FreeBSD grâce à dd. Par exemple : + + $ doas dd if=freebsd.img of=/dev/rsdXc bs=1M; sync + +Vous devriez être maintenant capable de démarrer l'installeur depuis votre clef USB. +Continuez à lire pour apprendre comment faire celà. + +Préparer la clef USB (dans GNU+Linux) +------------------------------------ + +Si vous avez téléchargé votre ISO sur système GNU+Linux, voici comment créer la clef USB NetBSD démarrable: + +Connectez la clef USB. Vérifiez la sortie de dmesg: + + $ dmesg + +Jetez un coup d'oeil à lsblk pour voir de quel disque il s'agit: + + $ lsblk + +Vérifiez qu'il n'a pas été monté automatiquement et si c'était le cas, démontez le. Par +example: + + $ sudo umount /dev/sdX\* + # umount /dev/sdX\* + +dmesg vous a dit de quel appareil il s'agit. Écraser en écriture le disque en écrivant +l'ISO de la distrib dessus grâce à dd. Par example: + + $ sudo dd if=install60.fs of=/dev/sdX bs=8M; sync + # dd if=netbsd.iso of=/dev/sdX bs=8M; sync + +Vous devriez être maintenant capable de démarrer l'installateur depuis votre clef USB. +Continuez à lire pour des informations sur comment faire celà. + +Installer NetBSD sans le chiffrement de tout le disque +---------------------------------------------- + +Vous allez peut-être avoir besoin d'un clavier USB externe durant l'installation. +Tapez sur C pour avoir accès à la console GRUB. + + grub> knetbsd -r sd0a (usb0,netbsd1)/netbsd + grub> boot + +Ça fera démarrer dans l'installateur NetBSD. Suivez la procédure d'installation normale +pour NetBSD. + +Installer NetBSD avec le chiffrement de tout le disque +------------------------------------------- + +TODO + +Démarrer +------- + +Tapez sur C dans grub pour avoir accès à la ligne de commande. + + grub> knetbsd -r wd0a (ahci0,netbsd1)/netbsd + grub> boot + +NetBSD commencera à démarrer. Youpi ! + +Configurer GRUB +---------------- + +Si vous ne voulez pas allez dans la ligne de commande GRUB et taper +une commande pour démarrer NetBSD à chaque fois, vous pouvez créer un +fichierde configuration GRUB qui sera au courant de votre installation +NetBSD et qui sera utilisé automatiquement par libreboot. + +Sur votre partition racine NetBSD, créez le répertoire /grub et ajoutez-y le +fichier `libreboot_grub_cfg`. Rajoutez-y ces lignes : + + default=0 + timeout=3 + + menuentry "NetBSD" { + knetbsd -r wd0a (ahci0,netbsd1)/netbsd + } + +La prochaine fois que vous démarreriez, vous verrez le vieux menu GRUB pour quelque +secondes, puis vous allez voir un nouveau menu avec seulement NetBSD dans la liste. Après +3 secondes NetBSD démarrera ou vous pouvez presser Entrée pour démarrer. + +Dépannage +=============== + +La majorité de ces problèmes arrivent lors de l'utilisation de libreboot avec le 'text mode' +de coreboot au lieu du framebuffer de coreboot. Ce mode est utile pour démarrer des charges +utiles comme memtest86+ qui s'attendent au mode texte, mais pour NetBSD celà peut être +problématique car il essaye d'alterner sur un framebuffer qui n'existe pas. + +Dans la plupart des cas, vous devriez utiliser les images ROM vesafb. Exemple du nom de fichier: +libreoot\_ukdvorak\_vesafb.rom. + +Ne démarrera pas... quelque chose à propos d'un fichier non trouvé +--------------------------------------------- + +Vos noms d'appareils (p.e usb0, usb1, sd0, sd1, wd0, ahci0, hd0, etc) et nombre peuvent +différer. Utilisez l'autocomplétion de TAB. + +Copyright © 2016 Leah Rowe \ +Copyright © 2016 Scott Bonds \ + + +Permission est donnée de copier, distribuer et/ou modifier ce document +sous les termes de la Licence de documentation libre GNU version 1.3 ou +quelconque autre versions publiées plus tard par la Free Software Foundation +sans Sections Invariantes, Textes de Page de Garde, et Textes de Dernière de Couverture. +Une copie de cette license peut être trouvé dans [fdl-1.3.md](fdl-1.3.md). diff --git a/i18n/fr_FR/docs/bsd/openbsd.md b/i18n/fr_FR/docs/bsd/openbsd.md new file mode 100644 index 00000000..20937e32 --- /dev/null +++ b/i18n/fr_FR/docs/bsd/openbsd.md @@ -0,0 +1,197 @@ +--- +title: How to install LibertyBSD or OpenBSD on a libreboot system +x-toc-enable: true +... + +NOTE: Ce guide a été écrit pour OpenBSD par la personne qui y a contribué, mais +le projet libreboot recommande LibertyBSD. LibertyBSD est une version d'OpenBSD +sans logiciel propriétaire dans les dépôts logiciels (OpenBSD distribue des blobs de micrologiciels +pour des périphériques dans son kernel). Allez sur le [site web de LibertyBSD](http://libertybsd.net/) +-- À FAIRE: tester sur LibertyBSD et donner la priorité aux explications dans ce guide. + +Cette section concerne la préparation, le démarrage et l'installation d'OpenBSD +sur votre système libreboot en utilisant rien de plus qu'un clef USB (et `dd`). +Ça a seulement été testé sur un ThinkPad X200 de chez Lenovo. + +*Cette section est seulement pour la charge utile GRUB. Pour depthcharge (utilisé +sur les appareils CrOS dans libreboot), des instructions ont encore à être écrite +dans la documentation libreboot.* + +install61.fs est l'image d'installation pour OpenBSD 6.1. Adaptez le nom du +fichier en concordance avec ce que vous avez, que ce soit pour une version +différente d'OpenBSD ou LibertyBSD. + +Préparer la clef USB (sur LibertyBSD ou OpenBSD) +------------------------------------------------ + +Si vous avez téléchargé votre ISO sur un système LibertyBSD ou OpenBSD, voici +comment créer une clef USB FreeBSD démarrable: + +Connectez la clef USB. Regardez la sortie de dmesg: + + $ dmesg | tail + +Vérifiez et confirmer de quel USB il s'agit si vous pensez par exemple que c'est sd3: + + $ disklabel sd3 + +Vérifiez qu'elle n'a pas été montée automatiquement. Sinon, on l'éjecte. Par exemple : + + $ doas umount /dev/sd3i + +dmesg vous a dit quel appareil/bloc c'était, donc on peut maintenant écrire par dessus +l'installateur FreeBSD grâce à dd. Par exemple : + + $ doas dd if=freebsd.img of=/dev/rsdXc bs=1M; sync + +Vous devriez être maintenant capable de démarrer l'installeur depuis votre clef USB. +Continuez à lire pour apprendre comme faire ceci. + +Continuez à lire pour des informations sur comment faire celà. + + +Préparer la clef USB (dans NetBSD) +--------------------------------- + +[Cette page](https://wiki.netbsd.org/tutorials/how_to_install_netbsd_from_an_usb_memory_stick/) +sur le site web de NetBSD montre comment créer une clef USB NetBSD démarrable, depuis NetBSD même. +Vous devriez utilisé la méthode *dd* documentée sur cette page; vous pouvez utiliser celle-ci avec +n'importe quelle ISO (image disque), incluant FreeBSD. + + +Préparer la clef USB (dans FreeBSD) +---------------------------------- + +[Cette page](https://www.freebsd.org/doc/handbook/bsdinstall-pre.html) sur le +site web de FreeBSD montre comment créer une clef USB démarrable pour installer +FreeBSD. Utilisez le *dd* sur cette page. + + +Préparer la clef USB (dans GNU+Linux) +------------------------------------ + +Si vous avez téléchargé votre ISO sur système GNU+Linux, voici comment créer la +clef USB NetBSD démarrable: + +Connectez la clef USB. Vérifiez la sortie de dmesg: + + $ dmesg + +Jetez un coup d'oeil à lsblk pour voir de quel disque il s'agit: + + $ lsblk + +Vérifiez qu'il n'a pas été monté automatiquement et si c'était le cas, démontez-le. Par example: + + $ sudo umount /dev/sdX\* + # umount /dev/sdX\* + +dmesg vous a dit de quel appareil il s'agit. Écraser en écriture le disque en écrivant l'ISO de la distrib dessus grâce à dd. Par example: + + $ sudo dd if=freebsd.img of=/dev/sdX bs=8M; sync + # dd if=freebsd.img of=/dev/sdX bs=8M; sync + +Vous devriez être maintenant capable de démarrer l'installateur depuis votre clef USB. + +Installer OpenBSD sans le chiffrement de tout le disque +----------------------------------------------- + +Pressez C dans GRUB pour avoir accés à la ligne de commande: + + grub> kopenbsd (usb0,openbsd1)/6.1/amd64/bsd.rd + grub> boot + +Ça commencera le démarrage sur l'installateur d'OpenBSD. Suivez la +procédure normale pour installer OpenBSD. + +Installer OpenBSD avec le chiffrement de tout le disque +-------------------------------------------- + +Ne marche pas. Vous pouvez modifier la procédure ci-dessus (installation +sans chiffrement pour installer OpenBSD avec le chiffrement de tout le disque, et +ça semble marcher mais il n'est pas encore très clair de savoir comment *démarrer* +une installation OpenBSD+CDE(Chiffrement du Disque en Entier) en utilisant libreboot+GRUB2. +Si vous réusissez à le faire marcher, merci de nous le faire savoir. + +Si vous démarrez en mode texte (le mode tampon d'image, aussi appelé framebuffer, peut +aussi marcher), il serait possible de chainload le chargeur d'amorçage d'OpenBSD ou LibertyBSD +depuis la section MBR sur le périphérique de stockage interne. De cette façon, il serait possible +de démarrer avec une installation OpenBSD ou LibertyBSD chiffrée. Merci de nous le faire savoir +(les informations de contact sont sur la page d'accueil de libreboot) si vous arrivez à le faire +marcher de cette façon. + +Alternativement, il serait bon de porter OpenBSD soit nativement en tant qu'une charge +utile coreboot, ou de le porter dans libpayload (bibliothèque de charge utile dans coreboot; +elle a une bibliothèque C basique et quelques fonctions pour certaines opérations p.e. texte/bitmap). +*Celà serait ideal parce qu'alors il serait possible de démarrer de vraiment +démarrer une installation OpenBSD ou LibertyBSD entièrement chiffrée, en mettant +tout dans la puce de flashage.* + +Alternativement, modifier GRUB pour supporter le démarrage d'installations +OpenBSD entièrement chiffrées serait possible, mais probablement pas faisable; +c'est une base de code totalement étrangère au projet OpenBSD, pas étroitement +intégrée et le chargeur d'amorçage d'OpenBSD marche déjà. + +Démarrer +------- + +Tapez C dans GRUB pour accéder à la ligne de commande : + + grub> kopenbsd -r sd0a (ahci0,openbsd1)/bsd + grub> boot + +Et OpenBSD démarrera. Hourra ! + +Configurer Grub +---------------- + +Si vous ne voulez pas rentrer dans la console GRUB et taper +une commande pour démarrer OpenBSD à chaque fois, vous pouvez créer un +fichier de configuration GRUB qui sera au courant de votre installation +OpenBSD et qui sera utilisé automatiquement par libreboot. + +Sur votre partition racine NetBSD, créez le répertoire `/grub` et ajoutez-y le +fichier `libreboot_grub_cfg`. Rajoutez-y ces lignes : + + default=0 + timeout=3 + + menuentry "OpenBSD" { + kopenbsd -r wd0a (ahci0,openbsd1)/openbsd + } + +Si votre installation OpenBSD utilise une table de partition GPT, utilisez la +partition `gpt4` à la place de `openbsd1`. + +La prochaine fois que vous démarreriez, vous verrez le vieux menu GRUB pour quelque +secondes, puis vous allez voir un nouveau menu avec seulement OpenBSD dans la liste. Après +3 secondes OpenBSD démarrera ou vous pouvez presser Entrée pour démarrer. + +Dépannage +=============== + +La majorité de ces problèmes arrivent lors de l'utilisation de libreboot avec le 'text mode' +de coreboot au lieu du framebuffer de coreboot. Ce mode est utile pour démarrer +des charges +utiles comme memtest86+ qui s'attendent au mode texte, mais pour OpenBSD celà peut être +problématique car il essaye d'alterner sur un framebuffer qui n'existe pas. + +Dans la plupart des cas, vous devriez utiliser les images ROM vesafb. Exemple du nom de fichier: +libreoot\_ukdvorak\_vesafb.rom. + +Ne démarrera pas... quelque chose à propos d'un fichier non trouvé +--------------------------------------------- + +Vos noms d'appareils (p.e usb0, usb1, sd0, sd1, wd0, ahci0, hd0, etc) et nombre +peuvent +différer. Utilisez l'autocomplétion de TAB. + +Copyright © 2016 Leah Rowe \ +Copyright © 2016 Scott Bonds \ + + +Permission est donnée de copier, distribuer et/ou modifier ce document +sous les termes de la Licence de documentation libre GNU version 1.3 ou +quelconque autre versions publiées plus tard par la Free Software Foundation +sans Sections Invariantes, Textes de Page de Garde, et Textes de Dernière de Couverture. +Une copie de cette license peut être trouvé dans [fdl-1.3.md](fdl-1.3.md). diff --git a/i18n/fr_FR/docs/cc-by-sa-4.0.txt b/i18n/fr_FR/docs/cc-by-sa-4.0.txt new file mode 100644 index 00000000..5421306d --- /dev/null +++ b/i18n/fr_FR/docs/cc-by-sa-4.0.txt @@ -0,0 +1,215 @@ +Attribution-ShareAlike 4.0 International + +======================================================================= + +Creative Commons Corporation (« Creative Commons ») +n'est pas un cabinet d'avocats et ne donne ni services +ni conseils juridiques. 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Donneur de licence signifie un individu ou une entité octroyant la présente Licence publique et les droits accordés par elle. + + k. Partager signifie mettre une œuvre à la disposition du public par tout moyen ou procédé qui requiert l’autorisation découlant des Droits accordés par la licence, tels que les droits de reproduction, de représentation au public, de distribution, de diffusion, de communication ou d’importation, y compris de manière à ce que chacun puisse y avoir accès de l’endroit et au moment qu’il choisit individuellement. + + l. Droit sui generis des producteurs de bases de données signifie droits distincts du droit d'auteur résultant de la Directive 96/9/CE du Parlement européen et du Conseil du 11 mars 1996 sur la protection juridique des bases de données, ainsi que tout autre droit de nature équivalente dans le monde. + + m. Vous (preneur de licence) se rapporte à tout individu ou entité exerçant les Droits accordés par la licence. Votre et Vos renvoient également au preneur de licence. + + + +Article 2 - Champ d’application de la présente Licence publique. + + a. Octroi de la licence. + + 1. Sous réserve du respect des termes et conditions d'utilisation de la présente Licence publique, le Donneur de licence Vous autorise à exercer pour le monde entier, à titre gratuit, non sous-licenciable, non exclusif, irrévocable, les Droits accordés par la licence afin de : + + A. reproduire et Partager l’Œuvre sous licence, en tout ou partie ; et + B. produire, reproduire et Partager l’Œuvre dérivée. + + 2. Exceptions et limitations. Afin de lever toute ambiguïté, lorsque les Exceptions et limitations s’appliquent à Votre utilisation, la présente Licence publique ne s’applique pas et Vous n’avez pas à Vous conformer à ses termes et conditions. + + 3. Durée. La durée de la présente Licence publique est définie à l’Article 6(a). + + 4. Supports et formats : modifications techniques autorisées. Le Donneur de licence Vous autorise à exercer les Droits accordés par la licence sur tous les supports et formats connus ou encore inconnus à ce jour, et à apporter toutes les modifications techniques que ceux-ci requièrent. Le Donneur de licence renonce et/ou accepte de ne pas exercer ses droits qui pourraient être susceptibles de Vous empêcher d’apporter les modifications techniques nécessaires pour exercer les Droits accordés par la licence, y compris celles nécessaires au contournement des Mesures techniques efficaces. Dans le cadre de la présente Licence publique, le fait de ne procéder qu’à de simples modifications techniques autorisées selon les termes du présent Article 2(a)(4) n’est jamais de nature à créer une Œuvre dérivée. + + 5. Utilisateurs en aval. + + A. Offre du Donneur de licence – Œuvre sous licence. Chaque utilisateur de l’Œuvre sous licence reçoit automatiquement une offre de la part du Donneur de licence lui permettant d’exercer les Droits accordés par la licence selon les termes et conditions de la présente Licence publique. + + B. Offre additionnelle du Donneur de licence – Œuvre dérivée. Chaque utilisateur d’une Œuvre dérivée reçoit automatiquement une offre du Donneur de licence lui permettant d’exercer les Droits accordés par la licence sur l’Œuvre dérivée selon les termes et conditions de la Licence d’Œuvre dérivée que Vous appliquez. + + C. Pas de restrictions en aval pour les utilisateurs suivants. Vous ne pouvez proposer ou imposer des termes et conditions supplémentaires ou différents, ou appliquer quelque Mesure technique efficace que ce soit à l’Œuvre sous licence si ceux(celles)-ci sont de nature à restreindre l’exercice des Droits accordés par la licence aux utilisateurs de l’Œuvre sous licence. + + 6. Non approbation. Aucun élément de la présente Licence publique ne peut être interprété comme laissant supposer que le preneur de licence ou que l’utilisation qu’il fait de l’Œuvre sous licence est lié à, parrainé, approuvé, ou doté d'un statut officiel par le Donneur de licence ou par toute autre personne à qui revient l’attribution de l’Œuvre sous licence, comme indiqué à l’Article 3(a)(1)(A)(i). + + + b. Autres droits. + + 1. Les droits moraux, tel que le droit à l’intégrité de l’œuvre, ne sont pas accordés par la présente Licence publique, ni le droit à l’image, ni le droit au respect de la vie privée, ni aucun autre droit de la personnalité ou apparenté ; cependant, dans la mesure du possible, le Donneur de licence renonce et/ou accepte de ne pas faire valoir les droits qu’il détient de manière à Vous permettre d’exercer les Droits accordés par la licence. + 2. Le droit des brevets et le droit des marques ne sont pas concernés par la présente Licence publique. + + 3. Dans la mesure du possible, le Donneur de licence renonce au droit de collecter des redevances auprès de Vous pour l’exercice des Droits accordés par la licence, directement ou indirectement dans le cadre d’un régime de gestion collective facultative ou obligatoire assorti de possibilités de renonciation quel que soit le type d’accord ou de licence. Dans tous les autres cas, le Donneur de licence se réserve expressément le droit de collecter de telles redevances. + + + +Article 3 – Conditions d'utilisation de la présente Licence publique. + +L’exercice des Droits accordés par la licence est expressément soumis aux conditions suivantes. + + a. Attribution. + + 1. Si Vous partagez l’Œuvre sous licence (y compris sous une forme modifiée), Vous devez : + + A. conserver les informations suivantes lorsqu’elles sont fournies par le Donneur de licence avec l’Œuvre sous licence : + i. identification du(des) auteur(s) de l’Œuvre sous licence et de toute personne à qui revient l’attribution de l’Œuvre sous licence, dans la mesure du possible, conformément à la demande du Donneur de licence (y compris sous la forme d’un pseudonyme s’il est indiqué) ; + ii. l’indication de l’existence d’un droit d’auteur ; + iii. une notice faisant référence à la présente Licence publique ; + iv. une notice faisant référence aux limitations de garantie et exclusions de responsabilité ; + v. un URI ou un hyperlien vers l’Œuvre sous licence dans la mesure du possible ; + + B. Indiquer si Vous avez modifié l’Œuvre sous licence et conserver un suivi des modifications précédentes ; et + + C. Indiquer si l’Œuvre sous licence est mise à disposition en vertu de la présente Licence publique en incluant le texte, l’URI ou l’hyperlien correspondant à la présente Licence publique. + + 2. Vous pouvez satisfaire aux conditions de l’Article 3(a)(1) dans toute la mesure du possible, en fonction des supports, moyens et contextes dans lesquels Vous Partagez l’Œuvre sous licence. Par exemple, Vous pouvez satisfaire aux conditions susmentionnées en fournissant l’URI ou l’hyperlien vers la ressource incluant les informations requises. + + 3. Bien que requises aux termes de l’Article 3(a)(1)(A), certaines informations devront être retirées, dans la mesure du possible, si le Donneur de licence en fait la demande. + + + b. Partage dans les mêmes conditions. + +Outre les conditions indiquées à l’Article 3(a), si Vous Partagez une Œuvre dérivée que Vous avez réalisée, les conditions suivantes s’appliquent aussi. + + 1. La Licence d’Œuvre dérivée que Vous appliquez doit être une licence Creative Commons avec les mêmes Eléments de licence, qu’il s’agisse de cette version ou d’une version ultérieure, ou une Licence compatible BY-SA. + + 2. Vous devez inclure le texte, l’URI ou l’hyperlien correspondant à la Licence d’Œuvre dérivée que Vous appliquez. Ces conditions peuvent être satisfaites dans la mesure du raisonnable suivant les supports, moyens et contextes via lesquels Vous Partagez l’Œuvre dérivée. + + 3. Vous ne pouvez pas proposer ou imposer des termes ou des conditions supplémentaires ou différents ou appliquer des Mesures techniques efficaces à l’Œuvre dérivée qui seraient de nature à restreindre l’exercice des Droits accordés par la Licence d’Œuvre dérivée que Vous appliquez. + + + +Article 4 – Le Droit sui generis des producteurs de bases de données. + +Lorsque les Droits accordés par la licence incluent le Droit sui generis des producteurs de bases de données applicable à Votre utilisation de l’Œuvre sous licence : + + a. afin de lever toute ambiguïté, l’Article 2(a)(1) Vous accorde le droit d’extraire, réutiliser, reproduire et Partager la totalité ou une partie substantielle du contenu de la base de données ; + b. si Vous incluez la totalité ou une partie substantielle du contenu de la base de données dans une base de données pour laquelle Vous détenez un Droit sui generis de producteur de bases de données, la base de données sur laquelle Vous détenez un tel droit (mais pas ses contenus individuels) sera alors considérée comme une Œuvre dérivée, y compris pour l’application de l’Article 3(b) ; et + c. Vous devez respecter les conditions de l’Article 3(a) si Vous Partagez la totalité ou une partie substantielle du contenu des bases de données. + +Afin de lever toute ambiguïté, le présent Article 4 complète mais ne remplace pas Vos obligations découlant des termes de la présente Licence publique lorsque les Droits accordés par la licence incluent d’autres Droit d’auteur et droits connexes. + + + +Article 5 – Limitations de garantie et exclusions de responsabilité. + + a. Sauf indication contraire et dans la mesure du possible, le Donneur de licence met à disposition l’Œuvre sous licence telle quelle, et n’offre aucune garantie de quelque sorte que ce soit, notamment expresse, implicite, statutaire ou autre la concernant. Cela inclut, notamment, les garanties liées au titre, à la valeur marchande, à la compatibilité de certaines utilisations particulières, à l’absence de violation, à l’absence de vices cachés ou autres défauts, à l’exactitude, à la présence ou à l’absence d’erreurs connues ou non ou susceptibles d’être découvertes dans l’Œuvre sous licence. Lorsqu’une limitation de garantie n’est pas autorisée en tout ou partie, cette clause peut ne pas Vous être applicable. + + b. Dans la mesure du possible, le Donneur de licence ne saurait voir sa responsabilité engagée vis-à-vis de Vous, quel qu’en soit le fondement juridique (y compris, notamment, la négligence), pour tout préjudice direct, spécial, indirect, incident, conséquentiel, punitif, exemplaire, ou pour toutes pertes, coûts, dépenses ou tout dommage découlant de l’utilisation de la présente Licence publique ou de l’utilisation de l’Œuvre sous licence, même si le Donneur de licence avait connaissance de l’éventualité de telles pertes, coûts, dépenses ou dommages. Lorsqu’une exclusion de responsabilité n’est pas autorisée en tout ou partie, cette clause peut ne pas Vous être applicable. + + c.Les limitations de garantie et exclusions de responsabilité ci-dessus doivent être interprétées, dans la mesure du possible, comme des limitations et renonciations totales de toute responsabilité. + + + +Article 6 – Durée et fin. + + a. La présente Licence publique s’applique pendant toute la durée de validité des Droits accordés par la licence. Cependant, si Vous manquez à Vos obligations prévues par la présente Licence publique, Vos droits accordés par la présente Licence publique seront automatiquement révoqués. +Lorsque les Droits accordés par la licence ont été révoqués selon les termes de l’Article 6(a), ils seront rétablis : + + 1. automatiquement, à compter du jour où la violation aura cessé, à condition que Vous y remédiiez dans les 30 jours suivant la date à laquelle Vous aurez eu connaissance de la violation ; ou + + 2.à condition que le Donneur de licence l’autorise expressément. + + +Afin de lever toute ambiguïté, le présent Article 6(b) n’affecte pas le droit du Donneur de licence de demander réparation dans les cas de violation de la présente Licence publique. + + c. Afin de lever toute ambiguïté, le Donneur de licence peut également proposer l’Œuvre sous licence selon d’autres termes et conditions et peut cesser la mise à disposition de l’Œuvre sous licence à tout moment ; une telle cessation n’entraîne pas la fin de la présente Licence publique. + + d. Les Articles 1, 5, 6, 7, et 8 continueront à s’appliquer même après la résiliation de la présente Licence publique. + + + +Article 7 – Autres termes et conditions. + + a. Sauf accord exprès, le Donneur de licence n’est lié par aucune modification des termes de Votre part. + + b. Tous arrangements, ententes ou accords relatifs à l’Œuvre sous licence non mentionnés dans la présente Licence publique sont séparés et indépendants des termes et conditions de la présente Licence publique. + + + +Article 8 – Interprétation. + + a. Afin de lever toute ambiguïté, la présente Licence publique ne doit en aucun cas être interprétée comme ayant pour effet de réduire, limiter, restreindre ou imposer des conditions plus contraignantes que celles qui sont prévues par les dispositions légales applicables. + + b. Dans la mesure du possible, si une clause de la présente Licence publique est déclarée inapplicable, elle sera automatiquement modifiée a minima afin de la rendre applicable. Dans le cas où la clause ne peut être modifiée, elle sera écartée de la présente Licence publique sans préjudice de l’applicabilité des termes et conditions restants. + + c. Aucun terme ni aucune condition de la présente Licence publique ne sera écarté(e) et aucune violation ne sera admise sans l’accord exprès du Donneur de licence. + + d. Aucun terme ni aucune condition de la présente Licence publique ne constitue ou ne peut être interprété(e) comme une limitation ou une renonciation à un quelconque privilège ou à une immunité s’appliquant au Donneur de licence ou à Vous, y compris lorsque celles-ci émanent d’une procédure légale, quel(le) qu’en soit le système juridique concerné ou l’autorité compétente. + + +Creative Commons n’est pas partie prenante de ses licences publiques. Néanmoins, Creative Commons se réserve le droit d'utiliser une de ses licences publiques pour les œuvres qu’elle publie, et dans ce cas sera considérée comme « Donneur de licence ». Le texte des licences publiques Creative Commons est versé au domaine public en vertu de CC0 Domaine Public. A l’exception des seuls cas où il est indiqué que l’œuvre est mise à disposition sous licence publique Creative Commons et ceux autorisés par les statuts de Creative Commons disponibles sur creativecommons.org/policies, Creative Commons n’autorise l’utilisation par aucune partie de la marque "Creative Commons" ou de toute autre marque ou logo de Creative Commons sans le consentement écrit préalable de Creative Commons. Cette restriction relative à l'utilisation des marques ne constitue pas une partie de nos licences publiques. + +Vous pouvez joindre Creative Commons via creativecommons.org. diff --git a/i18n/fr_FR/docs/depthcharge/index.md b/i18n/fr_FR/docs/depthcharge/index.md new file mode 100644 index 00000000..ffb525f5 --- /dev/null +++ b/i18n/fr_FR/docs/depthcharge/index.md @@ -0,0 +1,176 @@ +--- +title: Depthcharge payload +x-toc-enable: true +... + +This section relates to the depthcharge payload used in libreboot. + +CrOS security model +=================== + +CrOS (Chromium OS/Chrome OS) devices such as Chromebooks implement a strict +security model to ensure that these devices do not become compromised, that is +implemented as the verified boot (vboot) reference, most of which is executed +within depthcharge. A detailed overview of the CrOS security model is available +on the dedicated page. + +In spite of the CrOS security model, depthcharge won't allow booting kernels +without verifying their signature and booting from external media or legacy +payload unless explicitly allowed: see [configuring verified boot +parameters](#configuring_verified_boot_parameters). + +Developer mode screen +===================== + +The developer mode screen can be accessed in depthcharge when developer mode is +enabled. Developer mode can be enabled from the recovery mode screen. + +It allows booting normally, booting from internal storage, booting from +external media (when enabled), booting from legacy payload (when enabled), +showing information about the device and disabling developer mode. + +Holding the developer mode screen +--------------------------------- + +As instructed on the developer mode screen, the screen can be held by pressing +*Ctrl + H* in the first 3 seconds after the screen is shown. After that delay, +depthcharge will resume booting normally. + +Booting normally +---------------- + +As instructed on the developer mode screen, a regular boot will happen after *3 +seconds* (if developer mode screen is not held). + +The default boot medium (internal storage, external media, legacy payload) is +shown on screen. + +Booting from different mediums +------------------------------ + +Depthcharge allows booting from different mediums, when they are allowed (see +[configuring verified boot parameters](#configuring_verified_boot_parameters) +to enable or disable boot mediums). + +As instructed on the developer mode screen, booting from various mediums can be +triggered by pressing various key combinations: + +- Internal storage: *Ctrl + D* +- External media: *Ctrl + U* (when enabled) +- Legacy payload: *Ctrl + L* (when enabled) + +Showing device information +-------------------------- + +As instructed on the developer mode screen, showing device information can be +triggered by pressing *Ctrl + I* or *Tab*. Various information is shown, +including vboot non-volatile data, TPM status, GBB flags and key hashes. + +Warnings +-------- + +The developer mode screen will show warnings when: + +- Booting kernels without verifying their signature is enabled +- Booting from external media is enabled +- Booting legacy payloads is enabled + +Recovery mode screen +==================== + +The recovery mode screen can be accessed in depthcharge, by pressing *Escape + +Refresh + Power* when the device is off. + +It allows recovering the device from a bad state by booting from a trusted +recovery media. When accessed with the device in a good state, it also allows +enabling developer mode. + +Recovering from a bad state +--------------------------- + +When the device fails to verify the signature of a piece of the boot software +or when an error occurs, it is considered to be in a bad state and will +instruct the user to reboot to recovery mode. + +Recovery mode boots using only software located in write-protected memory, that +is considered to be trusted and safe. + +Recovery mode then allows recovering the device by booting from a trusted +recovery media, that is automatically detected when recovery mode starts. When +no external media is found or when the recovery media is invalid, instructions +are shown on screen. + +Trusted recovery media are external media (USB drives, SD cards, etc) that hold +a kernel signed with the recovery key. + +Google provides images of such recovery media for Chrome OS (which are not +advised to users as they contain proprietary software). + +They are signed with Google's recovery keys, that are pre-installed on the +device when it ships. + +When replacing the full flash of the device, the pre-installed keys are +replaced. When the recovery private key is available (e.g. when using +self-generated keys), it can be used to sign a kernel for recovery purposes. + +Enabling developer mode +----------------------- + +As instructed on the recovery mode screen, developer mode can be enabled by +pressing *Ctrl + D*. Instructions to confirm enabling developer mode are then +shown on screen. + +Configuring verified boot parameters +==================================== + +Depthcharge's behavior relies on the verified boot (vboot) reference +implementation, that can be configured with parameters stored in the verified +boot non-volatile storage. + +These parameters can be modified with the `crossystem` tool, that requires +sufficient privileges to access the verified boot non-volatile storage. + +`crossystem` relies on `mosys`, that is used to access the verified boot +non-volatile storage on some devices. `crossystem` and `mosys` are both free +software and their source code is made available by Google: +[crossystem](https://chromium.googlesource.com/chromiumos/platform/vboot_reference/). +[mosys](https://chromium.googlesource.com/chromiumos/platform/mosys/). + +These tools are not distributed along with Libreboot yet. However, they are +preinstalled on the device, with ChromeOS. + +Some of these parameters have the potential of *weakening the security of the +device*. In particular, disabling kernels signature verification, external +media boot and legacy payload boot can weaken the security of the device. + +The following parameters can be configured: + +Kernels signature verification: + + # crossystem dev_boot_signed_only=1 # enable + # crossystem dev_boot_signed_only=0 # disable + +External media boot: + + # crossystem dev_boot_usb=1 # enable + # crossystem dev_boot_usb=0 # disable + +Legacy payload boot: + + # crossystem dev_boot_legacy=1 # enable + # crossystem dev_boot_legacy=0 # disable + +Default boot medium: + + # crossystem dev_default_boot=disk # internal storage + # crossystem dev_default_boot=usb # external media + # crossystem dev_default_boot=legacy # legacy payload + + +Copyright © 2015 Paul Kocialkowski \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/fdl-1.3.md b/i18n/fr_FR/docs/fdl-1.3.md new file mode 100644 index 00000000..5a971aec --- /dev/null +++ b/i18n/fr_FR/docs/fdl-1.3.md @@ -0,0 +1,171 @@ +--- +title: Licence de documentation libre GNU +... +This is an unofficial translation of the GNU Free Documentation License into French. It was not published by the Free Software Foundation, and does not legally state the distribution terms for documents that uses the GNU FDL—only the original English text of the GNU FDL does that. However, we hope that this translation will help French speakers understand the GNU FDL better. + +Ceci est une traduction non officielle de la GNU FDL (licence GNU de documentation libre) en français. Elle n'a pas été publiée par la Free Software Foundation, et n'établit pas juridiquement les termes de distribution des documents qui utilisent la GNU FDL – seul le texte anglais original de la GNU FDL le fait. Cependant, nous espérons que cette traduction aidera les francophones à mieux comprendre la GNU FDL. + +Copyright © 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. + +Cette page peut être utilisée suivant les conditions de la licence Creative Commons attribution de paternité, pas de modification, 3.0 France (CC BY-ND 3.0 FR). + +Le texte qui est placé sur cette page après la présente phrase n'a pas vocation à produire un quelconque effet juridique. + +Début de la traduction : + +Licence GNU de documentation libre + +Version 1.3, 3 novembre 2008 + +Droits d'auteur © 2000, 2001, 2002, 2007, 2008 Fondation pour le logiciel libre + +Tout le monde est autorisé à copier et redistribuer à l'identique le texte de cette licence, mais le modifier n'est pas autorisé. + +## 0. PRÉAMBULE + +Le but de cette Licence est de rendre un manuel, un livre, ou un autre document fonctionnel et utile "libre" : d'assurer à tout le monde la liberté effective de le copier et de le redistribuer, en le modifiant ou non, commercialement ou bénévolement. Accessoirement, cette Licence donne la possibilité à l'auteur et à l'éditeur d'être crédités de leur travail, sans être considérés comme responsables des modifications faites par d'autres. + +Cette Licence est une sorte de "gauche d'auteur" ("copyleft"), ce qui signifie que les œuvres dérivées du document doivent elles aussi être libres. Elle est le complément de la licence publique générale GNU, qui est une licence de type gauche d'auteur conçue pour les logiciels libres. + +Nous avons conçu cette Licence pour l'utiliser dans les manuels de logiciel libre, parce que les logiciels libres nécessitent de la documentation libre : un programme libre doit être fourni avec des manuels assurant des libertés identiques à celles qu'assure le logiciel. Mais cette Licence n'est pas limitée aux manuels de logiciels ; elle peut être utilisée pour n'importe quelle œuvre textuelle, quel que soit le sujet traité, que cette œuvre soit publiée en tant que livre imprimé, ou non. Nous recommandons cette Licence principalement pour les œuvres à but éducatif ou pour les manuels de référence. + +## 1. APPLICABILITÉ ET DÉFINITIONS + +Cette Licence s'applique à tout manuel ou autre œuvre, sur n'importe quel support, qui contient une mention, placée par le détenteur des droits d'auteur, disant que le manuel ou l'œuvre peut être distribuée selon les termes de cette Licence. Une telle mention accorde une autorisation valable dans le monde entier, gratuite, sans limite de durée, d'utiliser l'œuvre selon les conditions établies ici. Le terme "Document", utilisé ci-après désigne tout manuel ou œuvre contenant une telle mention. Tout membre du public est un licencié, et est désigné par "vous". Vous acceptez la licence si vous copiez, modifiez ou distribuez l'œuvre d'une façon qui requiert une permission selon la loi sur le droit d'auteur. + +Une "Version Modifiée" du Document désigne toute œuvre contenant le Document ou une portion du Document, copié à l'identique, ou copié avec des modifications ou traduit dans une autre langue. + +Une "Section Secondaire" est une annexe portant un nom spécifique ou une section préliminaire du Document qui traite exclusivement de la relation des éditeurs ou des auteurs du Document au thème général du Document (ou à des thèmes liés) et ne contient rien qui pourrait relever directement de ce thème général. (Ainsi, si le Document est en partie un manuel de mathématiques, une Section Secondaire ne peut donner aucune explication en mathématiques.) La relation peut être une connexion historique avec le sujet ou avec des sujets liés, ou elle peut être un point de vue juridique, commercial, philosophique, éthique ou politique sur ces sujets. + +Les "Sections Invariantes" sont certaines Sections Secondaires, dont les titres sont désignés comme étant des Sections Invariantes dans la mention disant que le Document est publié selon les termes de cette Licence. Si une section ne correspond pas à la définition de Section Secondaire établie ci-dessus, alors il n'est pas permis de la désigner comme Invariante. Le Document peut contenir zéro Section Invariante. Si le Document n'identifie aucune Section Invariante, alors il n'y en a aucune. + +Les "Textes De Couverture" sont certains courts passages de texte qui sont mentionnés comme Textes De Première De Couverture ou Textes De Quatrième De Couverture dans la mention disant que le Document est publié selon les termes de cette Licence. Un Texte De Première De Couverture peut contenir 5 mots au maximum, et un Texte De Quatrième De Couverture peut contenir 25 mots au maximum. + +Une copie "Transparente" du Document désigne une copie lisible par une machine, représentée dans un format dont les spécifications sont disponibles pour le grand public, qui permet de corriger facilement le document avec des éditeurs de texte génériques ou (pour les images composées de pixels) avec des éditeurs d'image génériques ou (pour les dessins) avec des éditeurs de dessin largement disponibles, et qui est approprié pour servir de données d'entrée aux formateurs de texte ou pour être traduit automatiquement dans une variété de formats appropriés pour servir de données d'entrée aux formateurs de texte. Une copie faite dans un format de fichier par ailleurs Transparent, mais dont le marquage, ou l'absence de marquage, a été conçu de façon à empêcher ou décourager les lecteurs de faire des modifications ultérieurement n'est pas Transparente. Un format d'image n'est pas Transparent s'il est utilisé pour afficher toute quantité substantielle de texte. Une copie qui n'est pas "Transparente" est appelée "Opaque". + +Voici des exemples de formats appropriés pour faire des copies Transparentes : du texte brut ASCII sans marquage ; le format d'entrée de Texinfo ; le format d'entrée de LaTeX ; le format SGML ou XML en utilisant une DTD disponible publiquement ; du HTML simple et conforme aux standards ; du PostScript ou du PDF conçu pour être modifié par des humains. Voici des exemple de formats d'image transparents : PNG, XCF et JPG. Voici des exemples de formats opaques : les formats privateurs qui ne peuvent être lus et modifiés que par des logiciels de traitement de texte privateurs ; du SGML ou du XML dont la DTD ou les outils de traitement ne sont pas largement disponibles ; le HTML généré par une machine ; du PostScript ou du PDF produit par un logiciel de traitement de texte dans un but d'affichage seulement. + +La "Page De Titre" désigne, pour un livre imprimé, la page de titre elle-même, plus les pages suivantes nécessaires pour contenir, lisiblement, les mentions que cette Licence oblige à inscrire dans la page de titre. Pour les œuvres dont le format ne possède pas de page de titre en tant que telle, "Page De Titre" désigne le texte placé à côté de l'inscription la plus en vue du titre de l'œuvre, qui précède le début du corps du texte. + +L' "éditeur" désigne toute personne ou entité qui distribue des copies du Document au public. + +Une section "Intitulée XYZ" désigne soit une sous-unité du Document dont le titre est exactement XYZ, soit une sous-unité du Document dont le titre contient XYZ entre parenthèses après le texte traduisant XYZ dans une autre langue. (Ici XYZ représente un nom de section spécifique mentionné ci-après, tel que "Acknowledgements" [Remerciements], "Dedications" [Dédicaces], "Endorsements" [Approbations], ou "History" [Historique]). "Conserver le Titre" d'une telle section, quand vous modifiez le Document, signifie que cette section reste une section "Intitulée XYZ" selon la présente définition. + +Le Document peut inclure des Mentions De Limitation De Garantie à côté de la mention indiquant que cette Licence s'applique au Document. Ces Mentions De Limitation De Garantie sont considérées comme incluses par référence dans cette Licence, mais elles ne peuvent que limiter des garanties : toute autre implication que ces Mentions De Limitation De Garantie pourraient avoir est nulle et n'a aucun effet sur la signification de cette Licence. + +## 2. COPIE À L'IDENTIQUE + +Vous pouvez copier et distribuer le Document sur tout support, commercialement ou bénévolement, à condition que cette Licence, les mentions de droit d'auteur, et la mention disant que cette Licence s'applique au Document soient reproduites dans toutes les copies, et que vous n'ajoutiez absolument aucune autre condition aux conditions de cette Licence. Vous ne pouvez pas utiliser de mesures techniques pour entraver ou contrôler la lecture ou la copie des copies que vous faites ou distribuez. Toutefois, vous pouvez accepter une rémunération en échange de copies. Si vous distribuez un nombre de copies suffisamment important, vous devez aussi vous conformer aux conditions de la section 3. + +Vous pouvez aussi prêter des copies, selon les mêmes conditions que ci-dessus, et vous pouvez afficher publiquement des copies. + +## 3. COPIE EN GRANDE QUANTITÉ + +Si vous publiez plus de 100 copies imprimées (ou 100 copies dans un média qui a communément une couverture imprimée) du Document, et que la mention de licence du Document indique qu'il y a des Textes De Couverture, vous devez insérer chaque copie dans une couverture qui porte, clairement et lisiblement, tous ces Textes De Couverture : les Textes De Première De Couverture sur la première de couverture, et les Textes De Quatrième De Couverture sur la quatrième de couverture. Ces deux pages de couvertures doivent aussi vous identifier clairement et lisiblement comme l'éditeur de ces copies. La première de couverture doit présenter le titre complet, et tous les mots du titre doivent avoir la même importance et la même visibilité. Vous pouvez ajouter d'autres choses en supplément sur la couverture. Faire des copies avec des changements uniquement sur la couverture, tant que les copies conservent le titre du Document et satisfont ces conditions, est considéré comme faire des copies à l'identique. + +Si les textes requis pour l'une ou l'autre des pages de couverture sont trop volumineux pour y figurer lisiblement, vous devez mettre les premiers de la liste (autant qu'il est possible d'en mettre de façon lisible) sur la page de couverture elle-même, et mettre le reste sur les pages adjacentes. + +Si vous publiez ou distribuez plus de 100 copies Opaques du Document, vous devez soit inclure une copie Transparente et lisible par une machine avec chaque copie Opaque, soit indiquer dans chaque copie Opaque (ou dans une notice accompagnant chaque copie opaque) un emplacement sur le réseau informatique à partir duquel le grand public utilisant le réseau peut accéder au téléchargement, en utilisant des protocoles réseau publics et standards, d'une copie complète et Transparente du Document, sans aucun ajout. Si vous utilisez cette dernière option, vous devez prendre des précautions raisonnablement prudentes, quand vous commencez la distribution de copies Opaques en grande quantité, pour garantir que cette copie Transparente restera accessible par les moyens et à l'emplacement indiqués pendant au moins un an après la dernière distribution de copie Opaque (directement ou par l'intermédiaire de vos agents ou de vos revendeurs au détail) de cette édition au public. + +Il est demandé, sans que cela soit une obligation, que vous contactiez les auteurs du Document bien avant de redistribuer tout nombre important de copies, pour leur donner une chance de vous fournir une version mise à jour du Document. + +## 4. MODIFICATIONS + +Vous pouvez copier et distribuer une Version Modifiée du Document selon les conditions des sections 2 et 3 ci-dessus, à condition que vous accordiez le droit à tous ceux à qui vous distribuez la Version Modifiée de copier et de distribuer la Version Modifiée selon les termes de cette Licence, avec la Version Modifiée jouant le rôle du Document, autorisant ainsi la distribution et la modification de la Version Modifiée à toute personne qui en possède une copie. De plus, vous devez faire les choses suivantes dans la Version Modifiée : + +A. Utiliser dans la Page De Titre (et sur la couverture, s'il y en a) un titre distinct de celui du Document et de ceux des précédentes versions (qui devraient, s'il y en a, être énumérées dans la section History de ce Document). Vous pouvez utiliser le même titre que celui d'une version précédente si l'éditeur original de cette version vous en donne la permission. +B. Citer sur la Page De Titre, en tant qu'auteurs, une ou plusieurs personnes ou entités responsables des modifications faites dans la Version Modifiée, ainsi qu'au moins cinq des auteurs principaux du Document (tous les auteurs principaux, s'il y en a moins de cinq), sauf s'ils vous dispensent de cette obligation. +C. Spécifier sur la Page de titre le nom de l'éditeur de la Version Modifiée, en précisant que c'est lui l'éditeur. +D. Conserver toutes les mentions de droit d'auteur du Document. +E. Ajouter une mention appropriée indiquant vos droits d'auteur pour les modifications que vous avez faites ; cette mention doit être adjacente aux autres mentions de droit d'auteur. +F. Inclure, immédiatement après les mentions de droit d'auteur, une mention de licence donnant la permission au public d'utiliser la Version Modifiée selon les termes de cette Licence, en respectant la forme indiquée dans la section Addendum ci-dessous. +G. Conserver dans cette mention de licence les listes complètes des Sections Invariantes et des Textes De Couverture inscrites dans la mention de licence du Document. +H. Inclure une copie non modifiée de cette Licence. +I. Conserver la section Intitulée "History", Conserver son Titre, et ajouter à cette section un paragraphe indiquant au minimum le titre, l'année, les nouveaux auteurs, et l'éditeur de la Version Modifiée comme cela est fait sur la Page De Titre. S'il n'y a pas de section Intitulée "History" dans le Document, en créer une qui indique le titre, l'année, les auteurs, et l'éditeur du Document comme cela est fait sur la Page De Titre, et ensuite ajouter un paragraphe décrivant la Version Modifiée comme indiqué dans la phrase précédente. +J. Conserver l'indication d'emplacement sur le réseau, s'il y en a une, donnée dans le Document pour l'accès public à une copie Transparente du Document, et Conserver de la même manière les indications d'emplacement sur le réseau données dans le Document pour les versions précédentes sur lesquelles il est basé. Celles-ci peuvent être placées dans la section "History". Vous pouvez omettre une indication d'emplacement sur le réseau pour une œuvre qui a été publiée au moins quatre ans avant le Document lui-même, ou si l'éditeur original de la version à laquelle elle réfère vous en donne la permission. +K. Pour toute section Intitulée "Acknowledgements" ou "Dedications", Conserver le Titre de la section et, à l'intérieur de la section, toute la substance et le ton de chacun des remerciements aux contributeurs ou de chacune des dédicaces qui y figure. +L. Conserver toutes les Sections Invariantes du Document, non modifiées dans leurs textes et dans leurs titres. Les numéros de sections ou leurs équivalents ne sont pas considérés comme faisant partie des titres de section. +M. Supprimer toute section Intitulée "Endorsements". Une telle section ne peut pas être incluse dans la Version Modifiée. +N. Ne pas modifier le titre d'une section existante en lui donnant le titre "Endorsements" ou en lui donnant un titre qui entre en conflit avec le titre d'une Section Invariante. +O. Conserver toute Mention De Limitation De Garantie. +Si la Version Modifiée inclut de nouvelles sections préliminaires ou de nouvelles annexes qui répondent à la définition de Sections Secondaires et ne contiennent rien qui soit copié du Document, vous pouvez si vous le souhaitez désigner certaines ou toutes ces sections comme invariantes. Pour faire cela, ajoutez leurs titres à la liste des Sections Invariantes dans la mention de licence de la Version Modifiée. Ces titres doivent être distincts de tout autre titre de section. + +Vous pouvez ajouter une section Intitulée "Endorsements", à condition qu'elle ne contienne que des marques de soutien pour votre Version Modifiée faites par d'autres parties—par exemple, des déclarations d'évaluation par les pairs ou des déclarations stipulant que votre texte a été approuvé par une organisation comme définition officielle d'un standard. + +Vous pouvez ajouter un passage de cinq mots au maximum comme Texte De Première De Couverture, et un passage de 25 mots au maximum comme Texte De Quatrième De Couverture, à la fin de la liste des Textes De Couverture dans la Version Modifiée. Un seul passage de Texte De Première De Couverture et un seul passage de Texte De Quatrième De Couverture peut être ajouté par (ou par l'intermédiaire d'arrangements faits par) une même entité. Si le Document inclut déjà un texte pour la même page de couverture, précédemment ajouté par vous ou par arrangement fait par la même entité que celle au nom de laquelle vous agissez, vous ne pouvez pas en ajouter d'autre ; mais vous pouvez remplacer l'ancien à condition que l'éditeur précédent ayant placé l'ancien texte vous en donne la permission explicite. + +Par cette Licence, l'auteur (ou les auteurs) et l'éditeur (ou les éditeurs) du Document ne donnent pas la permission d'utiliser leurs noms pour un usage publicitaire ou pour exprimer explicitement ou implicitement leur soutien à une Version Modifiée. + +## 5. COMBINAISON DE DOCUMENTS + +Vous pouvez combiner le Document avec d'autres documents publiés selon les termes de cette Licence, à condition de respecter les termes définis dans la section 4 ci-dessus pour les Versions Modifiées, et à condition que vous incluiez dans la combinaison toutes les Sections Invariantes de tous les documents originaux, non modifiées, et que vous les énumériez toutes comme Sections Invariantes de votre œuvre combinée dans sa mention de licence, et que de plus vous conserviez toutes les Mentions De Limitation De Garantie de tous les documents originaux. + +L'œuvre combinée n'a besoin de contenir qu'une seule copie de cette Licence, et de multiples Sections Invariantes identiques peuvent être remplacées par une seule d'entre elles. S'il y a plusieurs Sections Invariantes avec le même nom mais avec des contenus différents, rendez unique le titre de chaque section en question en ajoutant à la fin de celui-ci, entre parenthèses, le nom de l'auteur ou de l'éditeur original de cette section s'il est connu, ou, à défaut, un nombre unique. Faites le même ajustement aux titres de section dans la liste des Sections Invariantes figurant dans la mention de licence de l'œuvre combinée. + +Dans la combinaison, vous devez combiner toutes les sections Intitulées "History" de tous les documents originaux, en formant une unique section Intitulée "History" ; de la même manière, combinez toutes les sections Intitulées "Acknowledgements", puis toutes les sections Intitulées "Dedications". Vous devez supprimer toutes les sections Intitulées "Endorsements". + +## 6. COLLECTIONS DE DOCUMENTS + +Vous pouvez faire une collection composée du Document et d'autres documents publiés selon les termes de cette Licence, et remplacer les copies individuelles de cette Licence dans les divers documents par une unique copie incluse dans la collection, à condition qu'à tous les autres égards et pour chacun des documents vous vous conformiez aux règles de cette Licence régissant la copie à l'identique. + +Vous pouvez extraire un document d'une telle collection, et le distribuer individuellement selon les termes de cette Licence, à condition que vous insériez une copie de cette Licence dans le document extrait, et que vous vous conformiez à cette Licence à tous les autres égards, en ce qui concerne la copie du document extrait. + +## 7. AGRÉGATION AVEC DES ŒUVRES INDÉPENDANTES + +Une compilation du Document ou de ses dérivés avec d'autres documents ou œuvres séparés et indépendants, dans une unité de stockage ou sur un support de distribution, est appelée "agrégat" si le droit d'auteur résultant de la compilation n'est pas utilisé pour limiter les droits légaux des utilisateurs de la compilation au-delà de ce que les œuvres individuelles permettent. Quand le Document est inclus dans un agrégat, cette Licence ne s'applique pas aux autres œuvres de l'agrégat qui ne sont pas elles-mêmes des œuvres dérivées du Document. + +Si l'obligation de Texte De Couverture de la section 3 est applicable à ces copies du Document, alors si le Document correspond à moins de la moitié de l'agrégat entier, les Textes De Couverture du Document peuvent être placés sur la couverture qui contient le Document à l'intérieur de l'agrégat, ou l'équivalent électronique de cette couverture si le Document est sous forme électronique. Dans le cas contraire, elles doivent apparaître sur la couverture imprimée qui contient l'agrégat entier. + +## 8. TRADUCTION + +La traduction est considérée comme un genre de modification, ainsi vous pouvez distribuer des traductions du Document selon les termes de la section 4. Remplacer des Sections Invariantes par des traductions requiert des permissions spéciales de la part des détenteurs du droit d'auteur, mais vous pouvez inclure des traductions de certaines ou de toutes les Sections Invariantes en plus des versions originales de ces Sections Invariantes. Vous pouvez inclure une traduction de cette Licence, et de toutes les mentions du Document, et de n'importe quelle Mention De Limitation De Garantie, à condition que vous incluiez aussi la version anglaise originale de cette Licence et les versions originales de ces mentions. En cas de divergence entre la traduction et la version originale de cette Licence ou d'une mention, la version originale prévaudra. + +Si une section du Document est Intitulée "Acknowledgements", "Dedications", ou "History", l'obligation (section 4) de Conserver son Titre (section 1) nécessitera typiquement un ajustement du titre traduit. + +## 9. EXPIRATION + +Vous ne pouvez pas copier, modifier, sous-licencier, ou distribuer le Document sauf aux conditions expressément prévues par la présente Licence. Toute tentative de le copier, le modifier, le sous-licencier ou le distribuer d'une autre manière est nulle, et entrainera automatiquement l'expiration des droits qui vous ont été conférés par cette Licence. + +Toutefois, si vous cessez toute violation de cette Licence, alors la licence qui vous a été octroyée par un détenteur particulier des droits d'auteur est rétablie (a) provisoirement, sauf si et jusqu'à ce que le détenteur des droits d'auteur annule votre licence de manière explicite et définitive, et (b) définitivement, si le détenteur des droits d'auteur ne parvient pas à vous notifier la violation par des moyens raisonnables dans un délai de 60 jours après la cessation de la violation. + +De plus, la licence qui vous a été octroyée par un détenteur particulier des droits d'auteur est rétablie définitivement si ce détenteur des droits d'auteur vous notifie de la violation par des moyens raisonnables, si c'est la première fois que vous avez reçu une notification de violation de cette Licence (pour toute œuvre) de la part de ce même détenteur des droits d'auteur, et si vous remédiez à la violation dans un délai de 30 jours après avoir reçu la notification. + +L'expiration de vos droits engendrée par cette section n'entraine pas l'expiration des licences des parties auxquelles vous avez envoyé des copies en les autorisant à utiliser les copies selon les termes de cette Licence. Si vos droits ont expirés et n'ont pas été rétablis définitivement, le fait de recevoir une copie de la même œuvre ou une copie d'une partie de la même œuvre ne vous donne aucun droit de l'utiliser. + +## 10. RÉVISIONS FUTURES DE CETTE LICENCE + +Il se peut que de temps en temps la Fondation pour le logiciel libre publie une nouvelle version, révisée, de la licence GNU de documentation libre. Ces nouvelles versions seront dans le même esprit, mais elles pourront différer dans les détails, pour répondre à de nouveaux problèmes ou inquiétudes. Référez-vous à http://www.gnu.org/copyleft/. + +Chaque version de la Licence possède un numéro de version distinct. Si le Document spécifie qu'il peut être utilisé selon les termes d'une version numérotée particulière de cette Licence "ou toute version ultérieure", vous avez le choix de vous conformer aux termes et aux conditions de la version spécifiée ou de toute version ultérieure qui a été publiée (pas en tant que brouillon) par la Fondation pour le logiciel libre. Si le Document ne spécifie pas de numéro de version, vous pouvez choisir n'importe quelle version publiée (pas en tant que brouillon) par la Fondation pour le logiciel libre. Si le Document spécifie qu'un serveur mandataire peut décider quelles versions futures de cette Licence peuvent être utilisées, la déclaration publique d'acceptation d'une version de la part de ce serveur mandataire vous autorise de manière permanente à choisir cette version pour utiliser le Document. + +## 11. RELICENCIER + +"Site de Collaboration Massive Multi-auteur" (ou "Site CMM") désigne tout serveur du World Wide Web qui publie des œuvres auxquelles le droit d'auteur est applicable et qui fournit aussi une infrastructure conséquente permettant à n'importe qui de modifier ces œuvres. Un wiki public que tout le monde peut modifier est un exemple d'un tel serveur. Une "Collaboration Massive Multi-auteur" (ou "CMM") contenue dans ce site désigne tout ensemble d'œuvres concernées par le droit d'auteur ainsi publiées sur le site CMM. + +"CC-BY-SA" désigne la licence Creative Commons attribution de paternité, partage à l'identique, 3.0, publiée par l'organisation Creative Commons, une organisation à but non lucratif basée à San Francisco, en Californie, ainsi que toute version future de type gauche d'auteur de cette licence, publiée par la même organisation. + +"Incorporer" signifie publier ou republier un Document, en entier ou en partie, comme partie d'un autre Document. + +Une CMM est "éligible pour relicencier" si elle est licenciée sous cette Licence, et si toutes les œuvres qui ont été publiées antérieurement sous cette Licence ailleurs que sur cette CMM, et incorporées ensuite en totalité ou en partie dans la CMM, (1) n'ont pas de textes de couverture ou de sections invariantes, et (2) ont été ainsi incorporées avant le premier novembre 2008. + +L'opérateur d'un Site CMM peut republier une CMM contenue dans le site sous licence CC-BY-SA sur le même site, à n'importe quelle date avant le premier août 2009, à condition que la CMM soit éligible pour relicencier. + +## ADDENDUM : Comment utiliser cette Licence dans vos documents + +Pour utiliser cette Licence dans un document que vous avez écrit, incluez une copie de cette Licence dans le document et inscrivez les mentions de droit d'auteur et de licence suivantes juste après la page de titre : + + Copyright (C) ANNÉE VOTRE NOM. + Vous avez la permission de copier, distribuer ou modifier ce document selon + les termes de la licence GNU de documentation libre, dans sa version 1.3 ou + dans toute version ultérieure publiée par la Free Software Foundation ; + sans Section Invariante, sans Texte De Première De Couverture, et sans + Texte De Quatrième De Couverture. Une copie de cette licence est incluse + dans la section intitulée "Licence GNU de documentation libre". +Si vous avez des Sections Invariantes, des Textes De Première de Couverture et des Textes De Quatrième De Couverture, remplacez les lignes "sans Texte …" par : + + avec les Sections Invariantes suivantes : LISTE DE LEURS TITRES ; avec + les Textes De Première De Couverture suivants : LISTE ; et avec les Textes + De Quatrième De Couverture suivants : LISTE. +Si vous avez des Sections Invariantes mais pas de Texte De Couverture, ou une autre combinaison des trois, fusionner les deux possibilités pour que cela convienne à la situation. + +Si votre document contient des exemples non triviaux de code source de logiciel, nous recommandons de publier ces exemples en parallèle sous une licence de logiciel libre de votre choix, telle que la licence publique générale GNU, pour permettre leur utilisation dans des logiciels libres. diff --git a/i18n/fr_FR/docs/future/coreboot_native_3.12_bug.tar.gz b/i18n/fr_FR/docs/future/coreboot_native_3.12_bug.tar.gz new file mode 100644 index 00000000..3564198a Binary files /dev/null and b/i18n/fr_FR/docs/future/coreboot_native_3.12_bug.tar.gz differ diff --git a/i18n/fr_FR/docs/future/donotusethis_macbook_acpi.diff b/i18n/fr_FR/docs/future/donotusethis_macbook_acpi.diff new file mode 100644 index 00000000..61a55c64 --- /dev/null +++ b/i18n/fr_FR/docs/future/donotusethis_macbook_acpi.diff @@ -0,0 +1,28 @@ +diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c +index 9a025dd..a2adb76 100644 +--- a/src/mainboard/apple/macbook21/mainboard.c ++++ b/src/mainboard/apple/macbook21/mainboard.c +@@ -40,6 +40,12 @@ + extern const u32 *cim_verb_data; + extern u32 cim_verb_data_size; + ++static acpi_cstate_t cst_entries[] = { ++ { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, ++ { 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } }, ++ { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } }, ++}; ++ + #if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE + static int int15_handler(void) + { +@@ -73,7 +79,8 @@ static int int15_handler(void) + + int get_cst_entries(acpi_cstate_t **entries) + { +- return 0; ++ *entries = cst_entries; ++ return ARRAY_SIZE(cst_entries); + } + + static void mainboard_init(device_t dev) + diff --git a/i18n/fr_FR/docs/future/dumps/5320_7c0000_gma.c b/i18n/fr_FR/docs/future/dumps/5320_7c0000_gma.c new file mode 100644 index 00000000..04a70dca --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/5320_7c0000_gma.c @@ -0,0 +1,519 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include "i945.h" +#include "chip.h" +#include +#include +#include +#include + +#define GDRST 0xc0 + +#define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) +#define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) +#define LVDS_CLOCK_BOTH_POWERUP_ALL (3 << 2) +#define DISPPLANE_BGRX888 (0x6<<26) +#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ + +#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14) + +#define PGETBL_CTL 0x2020 +#define PGETBL_ENABLED 0x00000001 + +#define BASE_FREQUENCY 120000 + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + +static int gtt_setup(unsigned int mmiobase) +{ + unsigned long PGETBL_save; + + PGETBL_save = read32(mmiobase + PGETBL_CTL) & ~PGETBL_ENABLED; + PGETBL_save |= PGETBL_ENABLED; + + PGETBL_save |= pci_read_config32(dev_find_slot(0, PCI_DEVFN(2,0)), 0x5c) & 0xfffff000; + PGETBL_save |= 2; /* set GTT to 256kb */ + + // hack!!! + PGETBL_save += 0x7c0000; // ugly hack. from 5927/3. Must calculate it properly! + /// hack!!! + + write32(mmiobase + GFX_FLSH_CNTL, 0); + + write32(mmiobase + PGETBL_CTL, PGETBL_save); + + /* verify */ +/* // old + if (read32(mmiobase + PGETBL_CTL) & PGETBL_ENABLED) { + printk(BIOS_DEBUG, "gtt_setup is enabled.\n"); +*/ + // Hack. Must do properly later: + PGETBL_save = read32(mmiobase + PGETBL_CTL); + if (PGETBL_save & PGETBL_ENABLED) { + printk(BIOS_DEBUG, "gtt_setup is enabled: GTT PGETLB_CTL register: 0x%lx\n", PGETBL_save); + // end hack + } else { + printk(BIOS_DEBUG, "gtt_setup failed!!!\n"); + return 1; + } + write32(mmiobase + GFX_FLSH_CNTL, 0); + + return 0; +} + +static int intel_gma_init(struct northbridge_intel_i945_config *conf, + unsigned int pphysbase, unsigned int piobase, + unsigned int pmmio, unsigned int pgfx) +{ + struct edid edid; + u8 edid_data[128]; + unsigned long temp; + int hpolarity, vpolarity; + u32 candp1, candn; + u32 best_delta = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; + u32 hactive, vactive, right_border, bottom_border; + u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; + u32 i, j; + + pphysbase += 0x20000; + + printk(BIOS_SPEW, + "i915lightup: graphics %p mmio %08x addrport %04x physbase %08x\n", + (void *)pgfx, pmmio, piobase, pphysbase); + + intel_gmbus_read_edid(pmmio + GMBUS0, 3, 0x50, edid_data, 128); + decode_edid(edid_data, sizeof(edid_data), &edid); + + hpolarity = (edid.phsync == '-'); + vpolarity = (edid.pvsync == '-'); + hactive = edid.x_resolution; + vactive = edid.y_resolution; + right_border = edid.hborder; + bottom_border = edid.vborder; + vblank = edid.vbl; + hblank = edid.hbl; + vsync = edid.vspw; + hsync = edid.hspw; + hfront_porch = edid.hso; + vfront_porch = edid.vso; + + for (i = 0; i < 2; i++) + for (j = 0; j < 0x100; j++) + /* R=j, G=j, B=j. */ + write32(pmmio + PALETTE(i) + 4 * j, 0x10101 * j); + + write32(pmmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PCH_PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + + write32(pmmio + MI_ARB_STATE, MI_ARB_C3_LP_WRITE_ENABLE | (1 << 27)); + /* Clean registers. */ + for (i = 0; i < 0x20; i += 4) + write32(pmmio + RENDER_RING_BASE + i, 0); + for (i = 0; i < 0x20; i += 4) + write32(pmmio + FENCE_REG_965_0 + i, 0); + write32(pmmio + PP_ON_DELAYS, 0); + write32(pmmio + PP_OFF_DELAYS, 0); + + /* Disable VGA. */ + write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); + + /* Disable pipes. */ + write32(pmmio + PIPECONF(0), 0); + write32(pmmio + PIPECONF(1), 0); + + /* Init PRB0. */ + write32(pmmio + HWS_PGA, 0x352d2000); + write32(pmmio + PRB0_CTL, 0); + write32(pmmio + PRB0_HEAD, 0); + write32(pmmio + PRB0_TAIL, 0); + write32(pmmio + PRB0_START, 0); + write32(pmmio + PRB0_CTL, 0x0001f001); + + write32(pmmio + D_STATE, DSTATE_PLL_D3_OFF + | DSTATE_GFX_CLOCK_GATING | DSTATE_DOT_CLOCK_GATING); + write32(pmmio + ECOSKPD, 0x00010000); + write32(pmmio + HWSTAM, 0xeffe); + write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); + write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); + + target_frequency = conf->gpu_lvds_is_dual_channel ? edid.pixel_clock + : (2 * edid.pixel_clock); + + /* Find suitable divisors. */ + for (candp1 = 1; candp1 <= 8; candp1++) { + for (candn = 5; candn <= 10; candn++) { + u32 cur_frequency; + u32 m; /* 77 - 131. */ + u32 denom; /* 35 - 560. */ + u32 current_delta; + + denom = candn * candp1 * 7; + /* Doesnt overflow for up to + 5000000 kHz = 5 GHz. */ + m = (target_frequency * denom + + BASE_FREQUENCY / 2) / BASE_FREQUENCY; + + if (m < 77 || m > 131) + continue; + + cur_frequency = (BASE_FREQUENCY * m) / denom; + if (target_frequency > cur_frequency) + current_delta = target_frequency - cur_frequency; + else + current_delta = cur_frequency - target_frequency; + + if (best_delta > current_delta) { + best_delta = current_delta; + pixel_n = candn; + pixel_p1 = candp1; + pixel_m2 = ((m + 3) % 5) + 7; + pixel_m1 = (m - pixel_m2) / 5; + } + } + } + + if (best_delta == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } + + printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", + hactive, vactive); + printk(BIOS_DEBUG, "Borders %d x %d\n", right_border, bottom_border); + printk(BIOS_DEBUG, "Blank %d x %d\n", hblank, vblank); + printk(BIOS_DEBUG, "Sync %d x %d\n", hsync, vsync); + printk(BIOS_DEBUG, "Front porch %d x %d\n", hfront_porch, vfront_porch); + printk(BIOS_DEBUG, (conf->gpu_lvds_use_spread_spectrum_clock + ? "Spread spectrum clock\n" + : "DREF clock\n")); + printk(BIOS_DEBUG, (conf->gpu_lvds_is_dual_channel + ? "Dual channel\n" + : "Single channel\n")); + printk(BIOS_DEBUG, "Polarities %d, %d\n", + hpolarity, vpolarity); + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", + BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n + / (pixel_p1 * 7)); + + write32(pmmio + DSPCNTR(0), DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(1), + ((pixel_n - 2) << 16) + | ((pixel_m1 - 2) << 8) | pixel_m2); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (conf->gpu_lvds_use_spread_spectrum_clock + ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV + : 0) + | (pixel_p1 << 16) + | (pixel_p1)); + mdelay(1); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS + | (conf->gpu_lvds_is_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) + | (pixel_p1 << 16) + | (pixel_p1)); + mdelay(1); + write32(pmmio + HTOTAL(1), + ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(pmmio + HBLANK(1), + ((hactive + right_border + hblank - 1) << 16) + | (hactive + right_border - 1)); + write32(pmmio + HSYNC(1), + ((hactive + right_border + hfront_porch + hsync - 1) << 16) + | (hactive + right_border + hfront_porch - 1)); + + write32(pmmio + VTOTAL(1), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); + write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(pmmio + VSYNC(1), + (vactive + bottom_border + vfront_porch + vsync - 1) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(pmmio + PIPESRC(1), ((hactive - 1) << 16) | (vactive - 1)); + + /* Disable panel fitter (we're in native resolution). */ + write32(pmmio + PF_CTL(0), 0); + write32(pmmio + PF_WIN_SZ(0), 0); + write32(pmmio + PF_WIN_POS(0), 0); + write32(pmmio + PFIT_PGM_RATIOS, 0); + write32(pmmio + PFIT_CONTROL, 0); + + mdelay(1); + + write32(pmmio + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); + write32(pmmio + DSPPOS(0), 0); + + /* Backlight init. */ + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + FW_BLC, 0x011d011a); + write32(pmmio + FW_BLC2, 0x00000102); + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + FW_BLC_SELF, 0x0001003f); + write32(pmmio + FW_BLC, 0x011d0109); + write32(pmmio + FW_BLC2, 0x00000102); + write32(pmmio + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); + write32(pmmio + BLC_PWM_CTL, conf->gpu_backlight); + + edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; + write32(pmmio + DSPADDR(0), 0); + write32(pmmio + DSPSURF(0), 0); + write32(pmmio + DSPSTRIDE(0), edid.bytes_per_line); + write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888 + | DISPPLANE_SEL_PIPE_B | DISPPLANE_GAMMA_ENABLE); + mdelay(1); + + write32(pmmio + PIPECONF(1), PIPECONF_ENABLE); + write32(pmmio + LVDS, LVDS_ON + | (hpolarity << 20) | (vpolarity << 21) + | (conf->gpu_lvds_is_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) + | LVDS_CLOCK_A_POWERUP_ALL + | LVDS_PIPE(1)); + + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_OFF); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS | PANEL_POWER_RESET); + mdelay(1); + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | PANEL_POWER_ON | PANEL_POWER_RESET); + + printk (BIOS_DEBUG, "waiting for panel powerup\n"); + while (1) { + u32 reg32; + reg32 = read32(pmmio + PP_STATUS); + if ((reg32 & PP_SEQUENCE_MASK) == PP_SEQUENCE_NONE) + break; + } + printk (BIOS_DEBUG, "panel powered up\n"); + + write32(pmmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + + /* Clear interrupts. */ + write32(pmmio + DEIIR, 0xffffffff); + write32(pmmio + SDEIIR, 0xffffffff); + write32(pmmio + IIR, 0xffffffff); + write32(pmmio + IMR, 0xffffffff); + write32(pmmio + EIR, 0xffffffff); + + /* GTT is the Global Translation Table for the graphics pipeline. + * It is used to translate graphics addresses to physical + * memory addresses. As in the CPU, GTTs map 4K pages. + * There are 32 bits per pixel, or 4 bytes, + * which means 1024 pixels per page. + * There are 4250 GTTs on Link: + * 2650 (X) * 1700 (Y) pixels / 1024 pixels per page. + * The setgtt function adds a further bit of flexibility: + * it allows you to set a range (the first two parameters) to point + * to a physical address (third parameter);the physical address is + * incremented by a count (fourth parameter) for each GTT in the + * range. + * Why do it this way? For ultrafast startup, + * we can point all the GTT entries to point to one page, + * and set that page to 0s: + * memset(physbase, 0, 4096); + * setgtt(0, 4250, physbase, 0); + * this takes about 2 ms, and is a win because zeroing + * the page takes a up to 200 ms. We will be exploiting this + * trick in a later rev of this code. + * This call sets the GTT to point to a linear range of pages + * starting at physbase. + */ + + if (gtt_setup(pmmio)) { + printk(BIOS_ERR, "ERROR: GTT Setup Failed!!!\n"); + return 0; + } + + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(pphysbase + (i << 12) + 1, piobase + 4); + } + + temp = read32(pmmio + PGETBL_CTL); + printk(BIOS_INFO, "GTT PGETBL_CTL register: 0x%lx\n", temp); + + if (temp & 1) + printk(BIOS_INFO, "GTT Enabled\n"); + else + printk(BIOS_ERR, "ERROR: GTT is still Disabled!!!\n"); + + printk(BIOS_SPEW, "memset %p to 0x00 for %d bytes\n", + (void *)pgfx, hactive * vactive * 4); + memset((void *)pgfx, 0x00, hactive * vactive * 4); + + set_vbe_mode_info_valid(&edid, pgfx); + + return 0; +} +#endif + +static void gma_func0_init(struct device *dev) +{ + u32 reg32; + + /* Unconditionally reset graphics */ + pci_write_config8(dev, GDRST, 1); + udelay(50); + pci_write_config8(dev, GDRST, 0); + /* wait for device to finish */ + while (pci_read_config8(dev, GDRST) & 1) { }; + + /* IGD needs to be Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER + | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + +#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); +#endif + + +#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + /* This should probably run before post VBIOS init. */ + printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); + u32 iobase, mmiobase, graphics_base; + struct northbridge_intel_i945_config *conf = dev->chip_info; + + iobase = dev->resource_list[1].base; + mmiobase = dev->resource_list[0].base; + graphics_base = dev->resource_list[2].base; + + printk(BIOS_SPEW, "GMADR=0x%08x GTTADR=0x%08x\n", + pci_read_config32(dev, 0x18), + pci_read_config32(dev, 0x1c) + ); + + int err; + err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, + iobase, mmiobase, graphics_base); + if (err == 0) + gfx_set_init_done(1); +#endif +} + +/* This doesn't reclaim stolen UMA memory, but IGD could still + be reenabled later. */ +static void gma_func0_disable(struct device *dev) +{ + struct device *dev_host = dev_find_slot(0, PCI_DEVFN(0x0, 0)); + + pci_write_config16(dev, GCFC, 0xa00); + pci_write_config16(dev_host, GGC, (1 << 1)); + + unsigned int reg32 = pci_read_config32(dev_host, DEVEN); + reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); + pci_write_config32(dev_host, DEVEN, reg32); + + dev->enabled = 0; +} + +static void gma_func1_init(struct device *dev) +{ + u32 reg32; + u8 val; + + /* IGD needs to be Bus Master, also enable IO accesss */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + pci_write_config32(dev, PCI_COMMAND, reg32 | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + + if (get_option(&val, "tft_brightness") == CB_SUCCESS) + pci_write_config8(dev, 0xf4, val); + else + pci_write_config8(dev, 0xf4, 0xff); +} + +static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } +} + +static struct pci_operations gma_pci_ops = { + .set_subsystem = gma_set_subsystem, +}; + +static struct device_operations gma_func0_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func0_init, + .scan_bus = 0, + .enable = 0, + .disable = gma_func0_disable, + .ops_pci = &gma_pci_ops, +}; + + +static struct device_operations gma_func1_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = gma_func1_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = &gma_pci_ops, +}; + +static const struct pci_driver i945_gma_func0_driver __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27a2, +}; + +static const struct pci_driver i945_gma_func1_driver __pci_driver = { + .ops = &gma_func1_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x27a6, +}; diff --git a/i18n/fr_FR/docs/future/dumps/5885_logs.tar.gz b/i18n/fr_FR/docs/future/dumps/5885_logs.tar.gz new file mode 100644 index 00000000..599445e7 Binary files /dev/null and b/i18n/fr_FR/docs/future/dumps/5885_logs.tar.gz differ diff --git a/i18n/fr_FR/docs/future/dumps/5885_logs_2.tar.gz b/i18n/fr_FR/docs/future/dumps/5885_logs_2.tar.gz new file mode 100644 index 00000000..a3381b4c Binary files /dev/null and b/i18n/fr_FR/docs/future/dumps/5885_logs_2.tar.gz differ diff --git a/i18n/fr_FR/docs/future/dumps/5927_2.tar.gz b/i18n/fr_FR/docs/future/dumps/5927_2.tar.gz new file mode 100644 index 00000000..39a794b4 Binary files /dev/null and b/i18n/fr_FR/docs/future/dumps/5927_2.tar.gz differ diff --git a/i18n/fr_FR/docs/future/dumps/5927_3.tar.gz b/i18n/fr_FR/docs/future/dumps/5927_3.tar.gz new file mode 100644 index 00000000..484acc60 Binary files /dev/null and b/i18n/fr_FR/docs/future/dumps/5927_3.tar.gz differ diff --git a/i18n/fr_FR/docs/future/dumps/5927_5.tar.gz b/i18n/fr_FR/docs/future/dumps/5927_5.tar.gz new file mode 100644 index 00000000..31ba59f7 Binary files /dev/null and b/i18n/fr_FR/docs/future/dumps/5927_5.tar.gz differ diff --git a/i18n/fr_FR/docs/future/dumps/5927_6.tar.gz b/i18n/fr_FR/docs/future/dumps/5927_6.tar.gz new file mode 100644 index 00000000..09810f05 Binary files /dev/null and b/i18n/fr_FR/docs/future/dumps/5927_6.tar.gz differ diff --git a/i18n/fr_FR/docs/future/dumps/5927_7.tar.gz b/i18n/fr_FR/docs/future/dumps/5927_7.tar.gz new file mode 100644 index 00000000..85435470 Binary files /dev/null and b/i18n/fr_FR/docs/future/dumps/5927_7.tar.gz differ diff --git a/i18n/fr_FR/docs/future/dumps/5927_cbmemc b/i18n/fr_FR/docs/future/dumps/5927_cbmemc new file mode 100644 index 00000000..1ef5139c --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/5927_cbmemc @@ -0,0 +1,1442 @@ + + +coreboot-4.0-6196-g1aa8cbd-7BETC7WW (2.08 ) Tue Jun 3 22:16:33 BST 2014 starting... + +Mobile Intel(R) 82945GM/GME Express Chipset +(G)MCH capable of up to FSB 800 MHz +(G)MCH capable of up to DDR2-667 +Setting up static southbridge registers... GPIOS... done. +Disabling Watchdog reboot... done. +Setting up static northbridge registers... done. +Waiting for MCHBAR to come up...ok +PM1_CNT: 00001c00 +SMBus controller enabled. +Setting up RAM controller. +This mainboard supports Dual Channel Operation. +DDR II Channel 0 Socket 0: x16DS +DDR II Channel 1 Socket 0: x8DDS +Memory will be driven at 667MHz with CAS=5 clocks +tRAS = 15 cycles +tRP = 5 cycles +tRCD = 5 cycles +Refresh: 7.8us +tWR = 5 cycles +DIMM 0 side 0 = 512 MB +DIMM 0 side 1 = 512 MB +DIMM 2 side 0 = 1024 MB +DIMM 2 side 1 = 1024 MB +tRFC = 43 cycles +Setting Graphics Frequency... +FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz +Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, ok +Setting mode of operation for memory channels...Dual Channel Assymetric. +Programming Clock Crossing...MEM=667 FSB=667... ok +Setting RAM size... +C0DRB = 0x20202010 +C1DRB = 0x60606040 +TOLUD = 0x00c0 +Setting row attributes... +C0DRA = 0x0033 +C1DRA = 0x0033 +DIMM0 has 8 banks. +DIMM2 has 8 banks. +one dimm per channel config.. +Initializing System Memory IO... +Programming Dual Channel RCOMP +Table Index: 3 +Programming DLL Timings... +Enabling System Memory IO... +jedec enable sequence: bank 0 +jedec enable sequence: bank 1 +bankaddr from bank size of rank 0 +jedec enable sequence: bank 4 +bankaddr from bank size of rank 1 +jedec enable sequence: bank 5 +bankaddr from bank size of rank 4 +receive_enable_autoconfig() for channel 0 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=f3 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=73 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +receive_enable_autoconfig() for channel 1 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=c5 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=45 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +RAM initialization finished. +Setting up Egress Port RCRB +Loading p + +*** Log truncated, 497 characters dropped. *** + +Adding CBMEM entry as no. 3 +Trying CBFS ramstage loader. +CBFS: loading stage fallback/ramstage @ 0x100000 (417848 bytes), entry @ 0x100000 +coreboot-4.0-6196-g1aa8cbd-7BETC7WW (2.08 ) Tue Jun 3 22:16:33 BST 2014 booting... +BS: Entering BS_PRE_DEVICE state. +BS: Exiting BS_PRE_DEVICE state. +BS: BS_PRE_DEVICE times (us): entry 0 run 2975 exit 0 +BS: Entering BS_DEV_INIT_CHIPS state. +BS: Exiting BS_DEV_INIT_CHIPS state. +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3324 exit 0 +BS: Entering BS_DEV_ENUMERATE state. +Enumerating buses... +Show all devs...Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 00:69: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:5c: enabled 1 +I2C: 00:5d: enabled 1 +I2C: 00:5e: enabled 1 +I2C: 00:5f: enabled 1 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + DOMAIN: 0000: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:1b.0: enabled 1 + PCI: 00:1c.0: enabled 1 + PCI: 00:1c.1: enabled 1 + PCI: 00:1d.0: enabled 1 + PCI: 00:1d.1: enabled 1 + PCI: 00:1d.2: enabled 1 + PCI: 00:1d.3: enabled 1 + PCI: 00:1d.7: enabled 1 + PCI: 00:1f.0: enabled 1 + PNP: 00ff.1: enabled 1 + PNP: 00ff.2: enabled 1 + PNP: 164e.2: enabled 1 + PNP: 164e.3: enabled 0 + PNP: 164e.7: enabled 1 + PNP: 164e.19: enabled 1 + PNP: 002e.0: enabled 0 + PNP: 002e.1: enabled 1 + PNP: 002e.2: enabled 0 + PNP: 002e.3: enabled 1 + PNP: 002e.7: enabled 1 + PNP: 002e.a: enabled 0 + PCI: 00:1f.1: enabled 1 + PCI: 00:1f.2: enabled 1 + PCI: 00:1f.3: enabled 1 + I2C: 00:69: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:5c: enabled 1 + I2C: 00:5d: enabled 1 + I2C: 00:5e: enabled 1 + I2C: 00:5f: enabled 1 +scan_static_bus for Root Device +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/27a0] ops +PCI: 00:00.0 [8086/27a0] enabled +PCI: 00:02.0 [8086/27a2] ops +PCI: 00:02.0 [8086/27a2] enabled +PCI: 00:02.1 [8086/27a6] ops +PCI: 00:02.1 [8086/27a6] enabled +PCI: 00:1b.0 [8086/27d8] ops +PCI: 00:1b.0 [8086/27d8] enabled +PCI: 00:1c.0 [8086/0000] bus ops +PCI: 00:1c.0 [8086/27d0] enabled +PCI: 00:1c.1 [8086/0000] bus ops +PCI: 00:1c.1 [8086/27d2] enabled +PCI: 00:1c.2 [8086/0000] bus ops +PCI: 00:1c.2 [8086/27d4] enabled +PCI: 00:1c.3 [8086/0000] bus ops +PCI: 00:1c.3 [8086/27d6] enabled +PCI: 00:1d.0 [8086/27c8] ops +PCI: 00:1d.0 [8086/27c8] enabled +PCI: 00:1d.1 [8086/27c9] ops +PCI: 00:1d.1 [8086/27c9] enabled +PCI: 00:1d.2 [8086/27ca] ops +PCI: 00:1d.2 [8086/27ca] enabled +PCI: 00:1d.3 [8086/27cb] ops +PCI: 00:1d.3 [8086/27cb] enabled +PCI: 00:1d.7 [8086/27cc] ops +PCI: 00:1d.7 [8086/27cc] enabled +PCI: 00:1e.0 [8086/2448] bus ops +PCI: 00:1e.0 [8086/2448] enabled +PCI: 00:1f.0 [8086/27b9] bus ops +PCI: 00:1f.0 [8086/27b9] enabled +PCI: 00:1f.1 [8086/27df] ops +PCI: 00:1f.1 [8086/27df] enabled +PCI: 00:1f.2 [8086/0000] ops +PCI: 00:1f.2 [8086/27c4] enabled +PCI: 00:1f.3 [8086/27da] bus ops +PCI: 00:1f.3 [8086/27da] enabled +do_pci_scan_bridge for PCI: 00:1c.0 +PCI: pci_scan_bus for bus 01 +PCI: 01:00.0 [8086/109a] enabled +PCI: pci_scan_bus returning with max=001 +do_pci_scan_bridge returns max 1 +do_pci_scan_bridge for PCI: 00:1c.1 +PCI: pci_scan_bus for bus 02 +PCI: 02:00.0 [168c/002b] enabled +PCI: pci_scan_bus returning with max=002 +do_pci_scan_bridge returns max 2 +do_pci_scan_bridge for PCI: 00:1c.2 +PCI: pci_scan_bus for bus 03 +PCI: pci_scan_bus returning with max=003 +do_pci_scan_bridge returns max 3 +do_pci_scan_bridge for PCI: 00:1c.3 +PCI: pci_scan_bus for bus 04 +PCI: pci_scan_bus returning with max=004 +do_pci_scan_bridge returns max 4 +do_pci_scan_bridge for PCI: 00:1e.0 +PCI: pci_scan_bus for bus 05 +PCI: 05:00.0 [1180/0476] bus ops +PCI: 05:00.0 [1180/0476] enabled +PCI: 05:00.1 [1180/0552] enabled +PCI: 05:00.2 [1180/0822] enabled +PCI: 05:00.3 [1180/0843] enabled +do_pci_scan_bridge for PCI: 05:00.0 +PCI: pci_scan_bus for bus 06 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +scan_static_bus for PCI: 00:1f.0 +WARNING: No CMOS option 'touchpad'. +PNP: 00ff.1 enabled +recv_ec_data: 0x37 +recv_ec_data: 0x42 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x33 +recv_ec_data: 0x37 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x04 +recv_ec_data: 0x03 +recv_ec_data: 0x00 +recv_ec_data: 0x11 +EC Firmware ID 7BHT37WW-3.4, Version 0.01B +recv_ec_data: 0x00 +recv_ec_data: 0x10 +recv_ec_data: 0x20 +recv_ec_data: 0x30 +recv_ec_data: 0x00 +recv_ec_data: 0xa6 +recv_ec_data: 0x01 +recv_ec_data: 0x30 +PNP: 00ff.2 enabled +PNP: 164e.2 enabled +PNP: 164e.3 disabled +PNP: 164e.7 enabled +PNP: 164e.19 enabled +PNP: 002e.0 disabled +PNP: 002e.1 enabled +PNP: 002e.2 disabled +PNP: 002e.3 enabled +PNP: 002e.7 enabled +PNP: 002e.a disabled +scan_static_bus for PCI: 00:1f.0 done +scan_static_bus for PCI: 00:1f.3 +smbus: PCI: 00:1f.3[0]->I2C: 01:69 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled +scan_static_bus for PCI: 00:1f.3 done +PCI: pci_scan_bus returning with max=006 +scan_static_bus for Root Device done +done +BS: Exiting BS_DEV_ENUMERATE state. +BS: BS_DEV_ENUMERATE times (us): entry 0 run 529332 exit 0 +BS: Entering BS_DEV_RESOURCES state. +found VGA at PCI: 00:02.0 +Setting up VGA for PCI: 00:02.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. +PCI: 00:1c.0 read_resources bus 1 link: 0 +PCI: 00:1c.0 read_resources bus 1 link: 0 done +PCI: 00:1c.1 read_resources bus 2 link: 0 +PCI: 00:1c.1 read_resources bus 2 link: 0 done +PCI: 00:1c.2 read_resources bus 3 link: 0 +PCI: 00:1c.2 read_resources bus 3 link: 0 done +PCI: 00:1c.3 read_resources bus 4 link: 0 +PCI: 00:1c.3 read_resources bus 4 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 done +PCI: 00:1f.0 read_resources bus 0 link: 0 +PNP: 00ff.1 missing read_resources +PNP: 00ff.2 missing read_resources +PCI: 00:1f.0 read_resources bus 0 link: 0 done +PCI: 00:1f.3 read_resources bus 1 link: 0 +PCI: 00:1f.3 read_resources bus 1 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 + PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18 + PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 + PCI: 01:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 2c + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 34 + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags c0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags c0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags c0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags c0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 01:00.0 18 * [0x0 - 0x1f] io +PCI: 00:1c.0 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 05:00.0 2c * [0x0 - 0xfff] io +PCI: 05:00.0 34 * [0x1000 - 0x1fff] io +PCI: 00:1e.0 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 1c * [0x0 - 0x1fff] io +PCI: 00:1c.0 1c * [0x2000 - 0x2fff] io +PCI: 00:1d.0 20 * [0x3000 - 0x301f] io +PCI: 00:1d.1 20 * [0x3020 - 0x303f] io +PCI: 00:1d.2 20 * [0x3040 - 0x305f] io +PCI: 00:1d.3 20 * [0x3060 - 0x307f] io +PCI: 00:1f.1 20 * [0x3080 - 0x308f] io +PCI: 00:1f.2 20 * [0x3090 - 0x309f] io +PCI: 00:02.0 14 * [0x30a0 - 0x30a7] io +PCI: 00:1f.1 10 * [0x30a8 - 0x30af] io +PCI: 00:1f.1 18 * [0x30b0 - 0x30b7] io +PCI: 00:1f.2 10 * [0x30b8 - 0x30bf] io +PCI: 00:1f.2 18 * [0x30c0 - 0x30c7] io +PCI: 00:1f.1 14 * [0x30c8 - 0x30cb] io +PCI: 00:1f.1 1c * [0x30cc - 0x30cf] io +PCI: 00:1f.2 14 * [0x30d0 - 0x30d3] io +PCI: 00:1f.2 1c * [0x30d4 - 0x30d7] io +DOMAIN: 0000 compute_resources_io: base: 30d8 size: 30d8 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:00.0 10 * [0x0 - 0x1ffff] mem +PCI: 00:1c.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 02:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:1c.1 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 05:00.0 1c * [0x0 - 0x1ffffff] prefmem +PCI: 00:1e.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 05:00.0 24 * [0x0 - 0x1ffffff] mem +PCI: 05:00.0 10 * [0x2000000 - 0x2000fff] mem +PCI: 05:00.1 10 * [0x2001000 - 0x20017ff] mem +PCI: 05:00.2 10 * [0x2001800 - 0x20018ff] mem +PCI: 05:00.3 10 * [0x2001900 - 0x20019ff] mem +PCI: 00:1e.0 compute_resources_mem: base: 2001a00 size: 2100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem +PCI: 00:1e.0 20 * [0x10000000 - 0x120fffff] mem +PCI: 00:1e.0 24 * [0x12100000 - 0x140fffff] prefmem +PCI: 00:1c.0 20 * [0x14100000 - 0x141fffff] mem +PCI: 00:1c.1 20 * [0x14200000 - 0x142fffff] mem +PCI: 00:02.0 10 * [0x14300000 - 0x1437ffff] mem +PCI: 00:02.1 10 * [0x14380000 - 0x143fffff] mem +PCI: 00:02.0 1c * [0x14400000 - 0x1443ffff] mem +PCI: 00:1b.0 10 * [0x14440000 - 0x14443fff] mem +PCI: 00:1d.7 10 * [0x14444000 - 0x144443ff] mem +PCI: 00:1f.2 24 * [0x14444400 - 0x144447ff] mem +DOMAIN: 0000 compute_resources_mem: base: 14444800 size: 14444800 align: 28 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:02.0 +constrain_resources: PCI: 00:02.1 +constrain_resources: PCI: 00:1b.0 +constrain_resources: PCI: 00:1c.0 +constrain_resources: PCI: 01:00.0 +constrain_resources: PCI: 00:1c.1 +constrain_resources: PCI: 02:00.0 +constrain_resources: PCI: 00:1c.2 +constrain_resources: PCI: 00:1c.3 +constrain_resources: PCI: 00:1d.0 +constrain_resources: PCI: 00:1d.1 +constrain_resources: PCI: 00:1d.2 +constrain_resources: PCI: 00:1d.3 +constrain_resources: PCI: 00:1d.7 +constrain_resources: PCI: 00:1e.0 +constrain_resources: PCI: 05:00.0 +constrain_resources: PCI: 05:00.1 +constrain_resources: PCI: 05:00.2 +constrain_resources: PCI: 05:00.3 +constrain_resources: PCI: 00:1f.0 +constrain_resources: PNP: 00ff.1 +constrain_resources: PNP: 00ff.2 +skipping PNP: 00ff.2@60 fixed resource, size=0! +skipping PNP: 00ff.2@62 fixed resource, size=0! +skipping PNP: 00ff.2@64 fixed resource, size=0! +skipping PNP: 00ff.2@66 fixed resource, size=0! +constrain_resources: PNP: 164e.2 +constrain_resources: PNP: 164e.7 +constrain_resources: PNP: 164e.19 +constrain_resources: PNP: 002e.1 +constrain_resources: PNP: 002e.3 +constrain_resources: PNP: 002e.7 +constrain_resources: PCI: 00:1f.1 +constrain_resources: PCI: 00:1f.2 +constrain_resources: PCI: 00:1f.3 +constrain_resources: I2C: 01:69 +constrain_resources: I2C: 01:54 +constrain_resources: I2C: 01:55 +constrain_resources: I2C: 01:56 +constrain_resources: I2C: 01:57 +constrain_resources: I2C: 01:5c +constrain_resources: I2C: 01:5d +constrain_resources: I2C: 01:5e +constrain_resources: I2C: 01:5f +avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff + lim->base 00001690 lim->limit 0000ffff +avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff + lim->base 00000000 lim->limit efffffff +Setting resources... +DOMAIN: 0000 allocate_resources_io: base:1690 size:30d8 align:12 gran:0 limit:ffff +Assigned: PCI: 00:1e.0 1c * [0x2000 - 0x3fff] io +Assigned: PCI: 00:1c.0 1c * [0x4000 - 0x4fff] io +Assigned: PCI: 00:1d.0 20 * [0x5000 - 0x501f] io +Assigned: PCI: 00:1d.1 20 * [0x5020 - 0x503f] io +Assigned: PCI: 00:1d.2 20 * [0x5040 - 0x505f] io +Assigned: PCI: 00:1d.3 20 * [0x5060 - 0x507f] io +Assigned: PCI: 00:1f.1 20 * [0x5080 - 0x508f] io +Assigned: PCI: 00:1f.2 20 * [0x5090 - 0x509f] io +Assigned: PCI: 00:02.0 14 * [0x50a0 - 0x50a7] io +Assigned: PCI: 00:1f.1 10 * [0x50a8 - 0x50af] io +Assigned: PCI: 00:1f.1 18 * [0x50b0 - 0x50b7] io +Assigned: PCI: 00:1f.2 10 * [0x50b8 - 0x50bf] io +Assigned: PCI: 00:1f.2 18 * [0x50c0 - 0x50c7] io +Assigned: PCI: 00:1f.1 14 * [0x50c8 - 0x50cb] io +Assigned: PCI: 00:1f.1 1c * [0x50cc - 0x50cf] io +Assigned: PCI: 00:1f.2 14 * [0x50d0 - 0x50d3] io +Assigned: PCI: 00:1f.2 1c * [0x50d4 - 0x50d7] io +DOMAIN: 0000 allocate_resources_io: next_base: 50d8 size: 30d8 align: 12 gran: 0 done +PCI: 00:1c.0 allocate_resources_io: base:4000 size:1000 align:12 gran:12 limit:ffff +Assigned: PCI: 01:00.0 18 * [0x4000 - 0x401f] io +PCI: 00:1c.0 allocate_resources_io: next_base: 4020 size: 1000 align: 12 gran: 12 done +PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1e.0 allocate_resources_io: base:2000 size:2000 align:12 gran:12 limit:ffff +Assigned: PCI: 05:00.0 2c * [0x2000 - 0x2fff] io +Assigned: PCI: 05:00.0 34 * [0x3000 - 0x3fff] io +PCI: 00:1e.0 allocate_resources_io: next_base: 4000 size: 2000 align: 12 gran: 12 done +DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:14444800 align:28 gran:0 limit:efffffff +Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem +Assigned: PCI: 00:1e.0 20 * [0xe0000000 - 0xe20fffff] mem +Assigned: PCI: 00:1e.0 24 * [0xe2100000 - 0xe40fffff] prefmem +Assigned: PCI: 00:1c.0 20 * [0xe4100000 - 0xe41fffff] mem +Assigned: PCI: 00:1c.1 20 * [0xe4200000 - 0xe42fffff] mem +Assigned: PCI: 00:02.0 10 * [0xe4300000 - 0xe437ffff] mem +Assigned: PCI: 00:02.1 10 * [0xe4380000 - 0xe43fffff] mem +Assigned: PCI: 00:02.0 1c * [0xe4400000 - 0xe443ffff] mem +Assigned: PCI: 00:1b.0 10 * [0xe4440000 - 0xe4443fff] mem +Assigned: PCI: 00:1d.7 10 * [0xe4444000 - 0xe44443ff] mem +Assigned: PCI: 00:1f.2 24 * [0xe4444400 - 0xe44447ff] mem +DOMAIN: 0000 allocate_resources_mem: next_base: e4444800 size: 14444800 align: 28 gran: 0 done +PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 allocate_resources_mem: base:e4100000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 01:00.0 10 * [0xe4100000 - 0xe411ffff] mem +PCI: 00:1c.0 allocate_resources_mem: next_base: e4120000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_mem: base:e4200000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 02:00.0 10 * [0xe4200000 - 0xe420ffff] mem +PCI: 00:1c.1 allocate_resources_mem: next_base: e4210000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_prefmem: base:e2100000 size:2000000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 1c * [0xe2100000 - 0xe40fffff] prefmem +PCI: 00:1e.0 allocate_resources_prefmem: next_base: e4100000 size: 2000000 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_mem: base:e0000000 size:2100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 24 * [0xe0000000 - 0xe1ffffff] mem +Assigned: PCI: 05:00.0 10 * [0xe2000000 - 0xe2000fff] mem +Assigned: PCI: 05:00.1 10 * [0xe2001000 - 0xe20017ff] mem +Assigned: PCI: 05:00.2 10 * [0xe2001800 - 0xe20018ff] mem +Assigned: PCI: 05:00.3 10 * [0xe2001900 - 0xe20019ff] mem +PCI: 00:1e.0 allocate_resources_mem: next_base: e2001a00 size: 2100000 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +pci_tolm: 0xd0000000 +Base of stolen memory: 0xbf800000 +Top of Low Used DRAM: 0xc0000000 +IGD decoded, subtracting 8M UMA +Available memory: 3137536K (3064M) +Adding PCIe config bar +DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem +PCI: 00:02.0 10 <- [0x00e4300000 - 0x00e437ffff] size 0x00080000 gran 0x13 mem +PCI: 00:02.0 14 <- [0x00000050a0 - 0x00000050a7] size 0x00000008 gran 0x03 io +PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem +PCI: 00:02.0 1c <- [0x00e4400000 - 0x00e443ffff] size 0x00040000 gran 0x12 mem +PCI: 00:02.1 10 <- [0x00e4380000 - 0x00e43fffff] size 0x00080000 gran 0x13 mem +PCI: 00:1b.0 10 <- [0x00e4440000 - 0x00e4443fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem +PCI: 00:1c.0 20 <- [0x00e4100000 - 0x00e41fffff] size 0x00100000 gran 0x14 bus 01 mem +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 01:00.0 10 <- [0x00e4100000 - 0x00e411ffff] size 0x00020000 gran 0x11 mem +PCI: 01:00.0 18 <- [0x0000004000 - 0x000000401f] size 0x00000020 gran 0x05 io +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.1 20 <- [0x00e4200000 - 0x00e42fffff] size 0x00100000 gran 0x14 bus 02 mem +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 02:00.0 10 <- [0x00e4200000 - 0x00e420ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem +PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io +PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem +PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem +PCI: 00:1d.0 20 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io +PCI: 00:1d.1 20 <- [0x0000005020 - 0x000000503f] size 0x00000020 gran 0x05 io +PCI: 00:1d.2 20 <- [0x0000005040 - 0x000000505f] size 0x00000020 gran 0x05 io +PCI: 00:1d.3 20 <- [0x0000005060 - 0x000000507f] size 0x00000020 gran 0x05 io +PCI: 00:1d.7 10 <- [0x00e4444000 - 0x00e44443ff] size 0x00000400 gran 0x0a mem +PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 05 io +PCI: 00:1e.0 24 <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x14 bus 05 prefmem +PCI: 00:1e.0 20 <- [0x00e0000000 - 0x00e20fffff] size 0x02100000 gran 0x14 bus 05 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 05:00.0 In set resources +PCI: 05:00.0 10 <- [0x00e2000000 - 0x00e2000fff] size 0x00001000 gran 0x0c mem +PCI: 05:00.0 2c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 34 <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 1c <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x0c prefmem +PCI: 05:00.0 24 <- [0x00e0000000 - 0x00e1ffffff] size 0x02000000 gran 0x0c mem +PCI: 05:00.1 10 <- [0x00e2001000 - 0x00e20017ff] size 0x00000800 gran 0x0b mem +PCI: 05:00.2 10 <- [0x00e2001800 - 0x00e20018ff] size 0x00000100 gran 0x08 mem +PCI: 05:00.3 10 <- [0x00e2001900 - 0x00e20019ff] size 0x00000100 gran 0x08 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PNP: 00ff.1 missing set_resources +PNP: 00ff.2 missing set_resources +PNP: 164e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io +ERROR: PNP: 164e.2 70 irq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 74 drq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 75 drq size: 0x0000000001 not assigned +PNP: 164e.7 60 <- [0x0000001680 - 0x000000168f] size 0x00000010 gran 0x04 io +ERROR: PNP: 164e.7 70 irq size: 0x0000000001 not assigned +PNP: 164e.19 60 <- [0x000000164c - 0x000000164d] size 0x00000002 gran 0x01 io +ERROR: PNP: 164e.19 70 irq size: 0x0000000001 not assigned +PNP: 002e.1 60 <- [0x00000003bc - 0x00000007bb] size 0x00000400 gran 0x0a io +PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq +ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned +PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io +PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq +PNP: 002e.7 60 <- [0x0000001620 - 0x0000001627] size 0x00000008 gran 0x03 io +ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PCI: 00:1f.1 10 <- [0x00000050a8 - 0x00000050af] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 14 <- [0x00000050c8 - 0x00000050cb] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 18 <- [0x00000050b0 - 0x00000050b7] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 1c <- [0x00000050cc - 0x00000050cf] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 20 <- [0x0000005080 - 0x000000508f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 10 <- [0x00000050b8 - 0x00000050bf] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x00000050d0 - 0x00000050d3] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x00000050c0 - 0x00000050c7] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x00000050d4 - 0x00000050d7] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x0000005090 - 0x000000509f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 24 <- [0x00e4444400 - 0x00e44447ff] size 0x00000400 gran 0x0a mem +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +CBMEM region bf6d0000-bf7fffff (cbmem_late_set_table) +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 1690 size 30d8 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base d0000000 size 14444800 align 28 gran 0 limit efffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base bf800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base e4300000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:02.0 resource base 50a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 14 + PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001200 index 18 + PCI: 00:02.0 resource base e4400000 size 40000 align 18 gran 18 limit efffffff flags 60000200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base e4380000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base e4440000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 4000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.0 resource base e4100000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base e4100000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10 + PCI: 01:00.0 resource base 4000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.1 resource base e4200000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base e4200000 size 10000 align 16 gran 16 limit efffffff flags 60000201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 5000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 5020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 5040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 5060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base e4444000 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 2000 size 2000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1e.0 resource base e2100000 size 2000000 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1e.0 resource base e0000000 size 2100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base e2000000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 10 + PCI: 05:00.0 resource base 2000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 2c + PCI: 05:00.0 resource base 3000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 34 + PCI: 05:00.0 resource base e2100000 size 2000000 align 12 gran 12 limit efffffff flags 60001200 index 1c + PCI: 05:00.0 resource base e0000000 size 2000000 align 12 gran 12 limit efffffff flags 60000200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base e2001000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base e2001800 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base e2001900 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags e0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags e0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags e0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags e0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 50a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.1 resource base 50c8 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.1 resource base 50b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.1 resource base 50cc size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.1 resource base 5080 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 50b8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.2 resource base 50d0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.2 resource base 50c0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.2 resource base 50d4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.2 resource base 5090 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 resource base e4444400 size 400 align 10 gran 10 limit efffffff flags 60000200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +Done allocating resources. +BS: Exiting BS_DEV_RESOURCES state. +BS: BS_DEV_RESOURCES times (us): entry 0 run 3353806 exit 0 +BS: Entering BS_DEV_ENABLE state. +Enabling resources... +PCI: 00:00.0 subsystem <- 17aa/2017 +PCI: 00:00.0 cmd <- 06 +PCI: 00:02.0 subsystem <- 17aa/201a +PCI: 00:02.0 cmd <- 03 +PCI: 00:02.1 subsystem <- 17aa/201a +PCI: 00:02.1 cmd <- 02 +PCI: 00:1b.0 subsystem <- 17aa/2010 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 0000/0000 +PCI: 00:1c.0 cmd <- 107 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 0000/0000 +PCI: 00:1c.1 cmd <- 106 +PCI: 00:1c.2 bridge ctrl <- 0003 +PCI: 00:1c.2 cmd <- 00 +PCI: 00:1c.3 bridge ctrl <- 0003 +PCI: 00:1c.3 cmd <- 00 +PCI: 00:1d.0 subsystem <- 17aa/200a +PCI: 00:1d.0 cmd <- 01 +PCI: 00:1d.1 subsystem <- 17aa/200a +PCI: 00:1d.1 cmd <- 01 +PCI: 00:1d.2 subsystem <- 17aa/200a +PCI: 00:1d.2 cmd <- 01 +PCI: 00:1d.3 subsystem <- 17aa/200a +PCI: 00:1d.3 cmd <- 01 +PCI: 00:1d.7 subsystem <- 17aa/200b +PCI: 00:1d.7 cmd <- 102 +PCI: 00:1e.0 bridge ctrl <- 0003 +PCI: 00:1e.0 cmd <- 07 (NOT WRITTEN!) +PCI: 00:1f.0 subsystem <- 17aa/2009 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.1 subsystem <- 17aa/200c +PCI: 00:1f.1 cmd <- 01 +PCI: 00:1f.2 subsystem <- 17aa/200d +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 17aa/200f +PCI: 00:1f.3 cmd <- 101 +PCI: 01:00.0 cmd <- 03 +PCI: 02:00.0 cmd <- 02 +PCI: 05:00.0 bridge ctrl <- 0503 +PCI: 05:00.0 cmd <- 03 +PCI: 05:00.1 cmd <- 02 +PCI: 05:00.2 cmd <- 06 +PCI: 05:00.3 cmd <- 06 +done. +BS: Exiting BS_DEV_ENABLE state. +BS: BS_DEV_ENABLE times (us): entry 0 run 124473 exit 0 +BS: Entering BS_DEV_INIT state. +Initializing devices... +Root Device init +recv_ec_data: 0x11 +recv_ec_data: 0x11 +Root Device init 5804 usecs +CPU_CLUSTER: 0 init +start_eip=0x00001000, code_size=0x00000031 +Initializing SMM handler... ... pmbase = 0x0500 + +SMI_STS: MCSMI PM1 +PM1_STS: WAK PWRBTN TMROF +GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 +ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI12 GPI11 GPI10 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 +TCO_STS: INTRD_DET + ... raise SMI# +Initializing CPU #0 +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000bf800000 size 0xbf740000 type 6 +0x00000000bf800000 - 0x00000000d0000000 size 0x10800000 type 0 +0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 +0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 +MTRR addr 0x0-0x10 set to 6 type @ 0 +MTRR addr 0x10-0x20 set to 6 type @ 1 +MTRR addr 0x20-0x30 set to 6 type @ 2 +MTRR addr 0x30-0x40 set to 6 type @ 3 +MTRR addr 0x40-0x50 set to 6 type @ 4 +MTRR addr 0x50-0x60 set to 6 type @ 5 +MTRR addr 0x60-0x70 set to 6 type @ 6 +MTRR addr 0x70-0x80 set to 6 type @ 7 +MTRR addr 0x80-0x84 set to 6 type @ 8 +MTRR addr 0x84-0x88 set to 6 type @ 9 +MTRR addr 0x88-0x8c set to 6 type @ 10 +MTRR addr 0x8c-0x90 set to 6 type @ 11 +MTRR addr 0x90-0x94 set to 6 type @ 12 +MTRR addr 0x94-0x98 set to 6 type @ 13 +MTRR addr 0x98-0x9c set to 6 type @ 14 +MTRR addr 0x9c-0xa0 set to 6 type @ 15 +MTRR addr 0xa0-0xa4 set to 0 type @ 16 +MTRR addr 0xa4-0xa8 set to 0 type @ 17 +MTRR addr 0xa8-0xac set to 0 type @ 18 +MTRR addr 0xac-0xb0 set to 0 type @ 19 +MTRR addr 0xb0-0xb4 set to 0 type @ 20 +MTRR addr 0xb4-0xb8 set to 0 type @ 21 +MTRR addr 0xb8-0xbc set to 0 type @ 22 +MTRR addr 0xbc-0xc0 set to 0 type @ 23 +MTRR addr 0xc0-0xc1 set to 6 type @ 24 +MTRR addr 0xc1-0xc2 set to 6 type @ 25 +MTRR addr 0xc2-0xc3 set to 6 type @ 26 +MTRR addr 0xc3-0xc4 set to 6 type @ 27 +MTRR addr 0xc4-0xc5 set to 6 type @ 28 +MTRR addr 0xc5-0xc6 set to 6 type @ 29 +MTRR addr 0xc6-0xc7 set to 6 type @ 30 +MTRR addr 0xc7-0xc8 set to 6 type @ 31 +MTRR addr 0xc8-0xc9 set to 6 type @ 32 +MTRR addr 0xc9-0xca set to 6 type @ 33 +MTRR addr 0xca-0xcb set to 6 type @ 34 +MTRR addr 0xcb-0xcc set to 6 type @ 35 +MTRR addr 0xcc-0xcd set to 6 type @ 36 +MTRR addr 0xcd-0xce set to 6 type @ 37 +MTRR addr 0xce-0xcf set to 6 type @ 38 +MTRR addr 0xcf-0xd0 set to 6 type @ 39 +MTRR addr 0xd0-0xd1 set to 6 type @ 40 +MTRR addr 0xd1-0xd2 set to 6 type @ 41 +MTRR addr 0xd2-0xd3 set to 6 type @ 42 +MTRR addr 0xd3-0xd4 set to 6 type @ 43 +MTRR addr 0xd4-0xd5 set to 6 type @ 44 +MTRR addr 0xd5-0xd6 set to 6 type @ 45 +MTRR addr 0xd6-0xd7 set to 6 type @ 46 +MTRR addr 0xd7-0xd8 set to 6 type @ 47 +MTRR addr 0xd8-0xd9 set to 6 type @ 48 +MTRR addr 0xd9-0xda set to 6 type @ 49 +MTRR addr 0xda-0xdb set to 6 type @ 50 +MTRR addr 0xdb-0xdc set to 6 type @ 51 +MTRR addr 0xdc-0xdd set to 6 type @ 52 +MTRR addr 0xdd-0xde set to 6 type @ 53 +MTRR addr 0xde-0xdf set to 6 type @ 54 +MTRR addr 0xdf-0xe0 set to 6 type @ 55 +MTRR addr 0xe0-0xe1 set to 6 type @ 56 +MTRR addr 0xe1-0xe2 set to 6 type @ 57 +MTRR addr 0xe2-0xe3 set to 6 type @ 58 +MTRR addr 0xe3-0xe4 set to 6 type @ 59 +MTRR addr 0xe4-0xe5 set to 6 type @ 60 +MTRR addr 0xe5-0xe6 set to 6 type @ 61 +MTRR addr 0xe6-0xe7 set to 6 type @ 62 +MTRR addr 0xe7-0xe8 set to 6 type @ 63 +MTRR addr 0xe8-0xe9 set to 6 type @ 64 +MTRR addr 0xe9-0xea set to 6 type @ 65 +MTRR addr 0xea-0xeb set to 6 type @ 66 +MTRR addr 0xeb-0xec set to 6 type @ 67 +MTRR addr 0xec-0xed set to 6 type @ 68 +MTRR addr 0xed-0xee set to 6 type @ 69 +MTRR addr 0xee-0xef set to 6 type @ 70 +MTRR addr 0xef-0xf0 set to 6 type @ 71 +MTRR addr 0xf0-0xf1 set to 6 type @ 72 +MTRR addr 0xf1-0xf2 set to 6 type @ 73 +MTRR addr 0xf2-0xf3 set to 6 type @ 74 +MTRR addr 0xf3-0xf4 set to 6 type @ 75 +MTRR addr 0xf4-0xf5 set to 6 type @ 76 +MTRR addr 0xf5-0xf6 set to 6 type @ 77 +MTRR addr 0xf6-0xf7 set to 6 type @ 78 +MTRR addr 0xf7-0xf8 set to 6 type @ 79 +MTRR addr 0xf8-0xf9 set to 6 type @ 80 +MTRR addr 0xf9-0xfa set to 6 type @ 81 +MTRR addr 0xfa-0xfb set to 6 type @ 82 +MTRR addr 0xfb-0xfc set to 6 type @ 83 +MTRR addr 0xfc-0xfd set to 6 type @ 84 +MTRR addr 0xfd-0xfe set to 6 type @ 85 +MTRR addr 0xfe-0xff set to 6 type @ 86 +MTRR addr 0xff-0x100 set to 6 type @ 87 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: default type WB/UC MTRR counts: 4/4. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x00 done. +CPU: 0 2 siblings +CPU: 0 has sibling 1 +CPU #0 initialized +CPU1: stack_base 00160000, stack_end 00160ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++Sending STARTUP #2 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #1 +Waiting for 1 CPUS to stop +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x01 done. +CPU: 1 2 siblings +CPU #1 initialized +CPU 1 going down... +All AP CPUs stopped (11641 loops) +CPU1: stack: 00160000 - 00161000, lowest used address 00160c68, stack used: 920 bytes +CPU_CLUSTER: 0 init 687708 usecs +PCI: 00:00.0 init +Normal boot. +PCI: 00:00.0 init 2905 usecs +PCI: 00:02.0 init +Initializing VGA without OPROM. +GMADR=0xd0000008 GTTADR=0xe4400000 +i915lightup: graphics d0020000 mmio e4300000 addrport 50a0 physbase bf800000 +Extracted contents: +header: 00 ff ff ff ff ff ff 00 +serial number: 30 ae 00 40 00 00 00 00 00 0f +version: 01 03 +basic params: 80 19 12 78 ea +chroma info: ed 75 91 57 4f 8b 26 21 50 54 +established: 21 08 00 +standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 +descriptor 1: 28 15 00 40 41 00 26 30 18 88 36 00 f6 b9 00 00 00 18 +descriptor 2: ed 10 00 40 41 00 26 30 18 88 36 00 f6 b9 00 00 00 18 +descriptor 3: 00 00 00 0f 00 61 43 32 61 43 28 0f 01 00 4c a3 58 4a +descriptor 4: 00 00 00 fe 00 4c 54 4e 31 32 31 58 4a 2d 4c 30 37 0a +extensions: 00 +checksum: 00 + +Manufacturer: LEN Model 4000 Serial Number 0 +EDID version: 1.3 +Digital display +Maximum image size: 25 cm x 18 cm +Gamma: 220% +Check DPMS levels +DPMS levels: Standby Suspend Off +Supported color formats: RGB 4:4:4, YCrCb 4:2:2 +First detailed timing is preferred timing +Established timings supported: + 640x480@60Hz + 800x600@60Hz + 1024x768@60Hz +Standard timings supported: +Detailed timings +Hex of detail: 281500404100263018883600f6b900000018 +Did detailed timing +Detailed mode (IN HEX): Clock 54160 KHz, f6 mm x b9 mm + 0400 0418 04a0 0540 hborder 0 + 0300 0303 0309 0326 vborder 0 + -hsync -vsync +Hex of detail: ed1000404100263018883600f6b900000018 +Detailed mode (IN HEX): Clock 54160 KHz, f6 mm x b9 mm + 0400 0418 04a0 0540 hborder 0 + 0300 0303 0309 0326 vborder 0 + -hsync -vsync +Hex of detail: 0000000f006143326143280f01004ca3584a +Manufacturer-specified data, tag 15 +Hex of detail: 000000fe004c544e313231584a2d4c30370a +ASCII string: LTN121XJ +Checksum +Checksum: 0x0 (valid) + +Unknown extension block + +EDID block does NOT conform to EDID 1.3! + Missing name descriptor + Missing monitor ranges + Detailed block string not properly terminated +EDID block does not conform at all! + Bad year of manufacture + Detailed blocks filled with garbage +I915_WRITE(HTOTAL(pipe), 053f03ff) +I915_WRITE(HBLANK(pipe),0x053f03ff) +I915_WRITE(HSYNC(pipe),0x049f0417) +I915_WRITE(VTOTAL(pipe), 032502ff) +I915_WRITE(VBLANK(pipe),0x032502ff) +I915_WRITE(VSYNC(pipe),0x03080302) +Table has 2247 elements +Change verbosity to 0 +run: return 2246 +Run returns 2247 +gtt_setup: GTT PGETLB_CTL register: 0x0 +gtt_setup: GTT PGETLB_CTL register: 0x1 +gtt_setup: GTT PGETLB_CTL register: 0xbf800001 +gtt_setup: GTT PGETLB_CTL register: 0xbf800003 +gtt_setup is enabled: GTT PGETLB_CTL register: 0x1 +setgtt(0,1600,0xbf800000,4096); +GTT PGETLB_CTL register: 0xbf800001 +GTT Enabled +memset d0020000 to 0x00 for 3145728 bytes +229929 microseconds +PCI: 00:02.0 init 265041 usecs +PCI: 00:02.1 init +PCI: 00:02.1 init 2382 usecs +PCI: 00:1b.0 init +Azalia: codec type: Azalia +Azalia: base = e4440000 +Azalia: codec_mask = 03 +Azalia: Initializing codec #1 +Azalia: codec viddid: 14f12bfa +Azalia: No verb! +Azalia: Initializing codec #0 +Azalia: codec viddid: 11d41981 +Azalia: No verb! +PCI: 00:1b.0 init 25808 usecs +PCI: 00:1c.0 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.0 init 4490 usecs +PCI: 00:1c.1 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.1 init 4490 usecs +PCI: 00:1c.2 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.2 init 4491 usecs +PCI: 00:1c.3 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.3 init 4489 usecs +PCI: 00:1d.0 init +UHCI: Setting up controller.. done. +PCI: 00:1d.0 init 4925 usecs +PCI: 00:1d.1 init +UHCI: Setting up controller.. done. +PCI: 00:1d.1 init 4926 usecs +PCI: 00:1d.2 init +UHCI: Setting up controller.. done. +PCI: 00:1d.2 init 4924 usecs +PCI: 00:1d.3 init +UHCI: Setting up controller.. done. +PCI: 00:1d.3 init 4925 usecs +PCI: 00:1d.7 init +EHCI: Setting up controller.. done. +PCI: 00:1d.7 init 4933 usecs +PCI: 00:1e.0 init +PCI: 00:1e.0 init 1683 usecs +PCI: 00:1f.0 init +i82801gx: lpc_init +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +IOAPIC: Dumping registers + reg 0x0000: 0x02000000 + reg 0x0001: 0x00170020 + reg 0x0002: 0x00170020 +WARNING: No CMOS option 'power_on_after_fail'. +Set power on after power failure. +NMI sources enabled. +rtc_failed = 0x0 +RTC Init +i8259_configure_irq_trigger: current interrupts are 0x0 +i8259_configure_irq_trigger: try to set interrupts 0x200 +Disabling ACPI via APMC: +done. +Locking SMM. +PCI: 00:1f.0 init 50455 usecs +PCI: 00:1f.1 init +i82801gx_ide: initializing... IDE0 +PCI: 00:1f.1 init 4942 usecs +PCI: 00:1f.2 init +i82801gx_sata: initializing... +SATA controller in AHCI mode. +PCI: 00:1f.2 init 7210 usecs +PCI: 01:00.0 init +PCI: 01:00.0 init 1669 usecs +PCI: 02:00.0 init +PCI: 02:00.0 init 1668 usecs +PCI: 05:00.0 init +Ricoh RL5c476: Initializing. +CF Base = 0 +CF boot not enabled. +PCI: 05:00.0 init 7377 usecs +PCI: 05:00.1 init +PCI: 05:00.1 init 1670 usecs +PCI: 05:00.2 init +PCI: 05:00.2 init 1670 usecs +PCI: 05:00.3 init +PCI: 05:00.3 init 1670 usecs +PNP: 164e.2 init +PNP: 164e.2 init 1582 usecs +PNP: 164e.7 init +PNP: 164e.7 init 1584 usecs +PNP: 164e.19 init +PNP: 164e.19 init 1670 usecs +PNP: 002e.1 init +PNP: 002e.1 init 1582 usecs +PNP: 002e.3 init +PNP: 002e.3 init 1584 usecs +PNP: 002e.7 init +PNP: 002e.7 init 1582 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:69 init +I2C: 01:69 init 16205 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:54 init +I2C: 01:54 init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:55 init +I2C: 01:55 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:56 init +I2C: 01:56 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:57 init +I2C: 01:57 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5c init +Locking EEPROM RFID +init EEPROM done +I2C: 01:5c init 28615 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5d init +I2C: 01:5d init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5e init +I2C: 01:5e init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5f init +I2C: 01:5f init 3593 usecs +Devices initialized +Show all devs...After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 01:69: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:5c: enabled 1 +I2C: 01:5d: enabled 1 +I2C: 01:5e: enabled 1 +I2C: 01:5f: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 01:00.0: enabled 1 +PCI: 02:00.0: enabled 1 +PCI: 05:00.0: enabled 1 +PCI: 05:00.1: enabled 1 +PCI: 05:00.2: enabled 1 +PCI: 05:00.3: enabled 1 +APIC: 01: enabled 1 +BS: Exiting BS_DEV_INIT state. +BS: BS_DEV_INIT times (us): entry 0 run 1411225 exit 0 +BS: Entering BS_POST_DEVICE state. +CBMEM region bf6d0000-bf7fffff (cbmem_check_toc) +Adding CBMEM entry as no. 4 +Moving GDT to bf6e0600...ok +Finalize devices... +Devices finalized +BS: Exiting BS_POST_DEVICE state. +BS: BS_POST_DEVICE times (us): entry 9470 run 6558 exit 0 +BS: Entering BS_OS_RESUME_CHECK state. +BS: Exiting BS_OS_RESUME_CHECK state. +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3401 exit 0 +BS: Entering BS_WRITE_TABLES state. +Copying Interrupt Routing Table to 0x000f0000... done. +Adding CBMEM entry as no. 5 +Copying Interrupt Routing Table to 0xbf6e0800... done. +PIRQ table: 272 bytes. +Wrote the mp table end at: 000f0410 - 000f05cc +Adding CBMEM entry as no. 6 +Wrote the mp tabl +6653 bytes lost diff --git a/i18n/fr_FR/docs/future/dumps/5927_config b/i18n/fr_FR/docs/future/dumps/5927_config new file mode 100644 index 00000000..045ca300 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/5927_config @@ -0,0 +1,441 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_EXPERT=y +CONFIG_LOCALVERSION="7BETC7WW (2.08 )" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_BROKEN_CAR_MIGRATE is not set +# CONFIG_DYNAMIC_CBMEM is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_ADVANTECH is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_ARIMA is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASI is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AXUS is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_EAGLELION is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NEWISYS is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_TECHNOLOGIC is not set +# CONFIG_VENDOR_TELEVIDEO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x60" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60 / X60s" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="Lenovo" +CONFIG_MAX_CPUS=2 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_VGA_BIOS_ID="8086,27a2" +CONFIG_DRIVERS_PS2_KEYBOARD=y +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +# CONFIG_UDELAY_IO is not set +CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_ACPI_SSDTX_NUM=0 +# CONFIG_PCI_64BIT_PREF_MEM is not set +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_STACK_SIZE=0x1000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x200000 +CONFIG_BOARD_LENOVO_X60=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_MAINBOARD_VERSION="ThinkPad X60" +CONFIG_CPU_ADDR_BITS=32 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_MAINBOARD_SERIAL_NUMBER="L3AZ921" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="1703WMF" +CONFIG_ARCH_X86=y +# CONFIG_ARCH_ARMV7 is not set +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_AP_IN_SIPI_WAIT=y +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_ROMCC is not set +CONFIG_PC80_SYSTEM=y +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_HPET_ADDRESS=0xfed00000 +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_UPDATE_IMAGE is not set + +# +# Chipset +# + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_CPU_TI_AM335X is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0 +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SMM_TSEG_SIZE=0 +CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_MODULES is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_EHCI_BAR=0xfef00000 +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87392=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_DOCK_EARLY_INIT=y +CONFIG_EC_LENOVO_PMH7=y + +# +# SoC +# + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_ON_DEVICE_ROM_RUN is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_AGP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCI_BUS_SEGN_BITS=0 +# CONFIG_EARLY_PCI_BRIDGE is not set + +# +# VGA BIOS +# + +# +# Display +# + +# +# PXE ROM +# +# CONFIG_PXE_ROM is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 + +# +# Generic Drivers +# +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_TPM is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +CONFIG_DRIVERS_UART=y +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_POST_IO is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_HAVE_ACPI_SLIC is not set +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +# CONFIG_VGA is not set +# CONFIG_GFXUMA is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_HAVE_REFCODE_BLOB is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y + +# +# System tables +# +CONFIG_GENERATE_ACPI_TABLES=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_PAYLOAD_FILE="grub.elf" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +CONFIG_MAX_REBOOT_CNT=3 diff --git a/i18n/fr_FR/docs/future/dumps/5927_crashdump b/i18n/fr_FR/docs/future/dumps/5927_crashdump new file mode 100644 index 00000000..3e09cd59 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/5927_crashdump @@ -0,0 +1,77 @@ +Time: 1401830541 s 274954 us +Kernel: 3.14.4-gnuowen +PCI ID: 0x27a2 +EIR: 0x00000010 +IER: 0x00028053 +PGTBL_ER: 0x00000013 +FORCEWAKE: 0x00000000 +DERRMR: 0x00000000 +CCID: 0x00000000 +Missed interrupts: 0x00000000 + fence[0] = 00000000 + fence[1] = 00000000 + fence[2] = 00000000 + fence[3] = 00000000 + fence[4] = 00000000 + fence[5] = 00000000 + fence[6] = 00000000 + fence[7] = 00000000 + fence[8] = 00000000 + fence[9] = 00000000 + fence[10] = 00000000 + fence[11] = 00000000 + fence[12] = 00000000 + fence[13] = 00000000 + fence[14] = 00000000 + fence[15] = 00000000 + INSTDONE_0: 0x7fffffc0 + INSTDONE_1: 0x00000000 + INSTDONE_2: 0x00000000 + INSTDONE_3: 0x00000000 +Active [0]: +Pinned [0]: +Num Pipes: 2 +Pipe [0]: + Power: off + SRC: 00000000 +Plane [0]: + CNTR: 00000000 + STRIDE: 00000000 + SIZE: 00000000 + POS: 00000000 + ADDR: 00000000 +Cursor [0]: + CNTR: 00000000 + POS: 00000000 + BASE: 00000000 +Pipe [1]: + Power: off + SRC: 00000000 +Plane [1]: + CNTR: 00000000 + STRIDE: 00000000 + SIZE: 00000000 + POS: 00000000 + ADDR: 00000000 +Cursor [1]: + CNTR: 00000000 + POS: 00000000 + BASE: 00000000 +CPU transcoder: A + Power: off + CONF: 00000000 + HTOTAL: 00000000 + HBLANK: 00000000 + HSYNC: 00000000 + VTOTAL: 00000000 + VBLANK: 00000000 + VSYNC: 00000000 +CPU transcoder: A + Power: off + CONF: 00000000 + HTOTAL: 00000000 + HBLANK: 00000000 + HSYNC: 00000000 + VTOTAL: 00000000 + VBLANK: 00000000 + VSYNC: 00000000 diff --git a/i18n/fr_FR/docs/future/dumps/coreboot_5296_oprom_grub_cbmemc b/i18n/fr_FR/docs/future/dumps/coreboot_5296_oprom_grub_cbmemc new file mode 100644 index 00000000..c769d1a0 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/coreboot_5296_oprom_grub_cbmemc @@ -0,0 +1,1436 @@ + + +coreboot-4.0-6195-g3b7c130-7BETC7WW (2.08 ) Tue Jun 3 16:36:44 BST 2014 starting... + +Mobile Intel(R) 82945GM/GME Express Chipset +(G)MCH capable of up to FSB 800 MHz +(G)MCH capable of up to DDR2-667 +Setting up static southbridge registers... GPIOS... done. +Disabling Watchdog reboot... done. +Setting up static northbridge registers... done. +Waiting for MCHBAR to come up...ok +PM1_CNT: 00001c00 +SMBus controller enabled. +Setting up RAM controller. +This mainboard supports Dual Channel Operation. +DDR II Channel 0 Socket 0: x16DS +DDR II Channel 1 Socket 0: x8DDS +Memory will be driven at 667MHz with CAS=5 clocks +tRAS = 15 cycles +tRP = 5 cycles +tRCD = 5 cycles +Refresh: 7.8us +tWR = 5 cycles +DIMM 0 side 0 = 512 MB +DIMM 0 side 1 = 512 MB +DIMM 2 side 0 = 1024 MB +DIMM 2 side 1 = 1024 MB +tRFC = 43 cycles +Setting Graphics Frequency... +FSB: 667 MHz Voltage: 1.05V Render: 250Mhz Display: 200MHz +Setting Memory Frequency... CLKCFG=0x00010023, CLKCFG=0x00010043, ok +Setting mode of operation for memory channels...Dual Channel Assymetric. +Programming Clock Crossing...MEM=667 FSB=667... ok +Setting RAM size... +C0DRB = 0x20202010 +C1DRB = 0x60606040 +TOLUD = 0x00c0 +Setting row attributes... +C0DRA = 0x0033 +C1DRA = 0x0033 +DIMM0 has 8 banks. +DIMM2 has 8 banks. +one dimm per channel config.. +Initializing System Memory IO... +Programming Dual Channel RCOMP +Table Index: 3 +Programming DLL Timings... +Enabling System Memory IO... +jedec enable sequence: bank 0 +jedec enable sequence: bank 1 +bankaddr from bank size of rank 0 +jedec enable sequence: bank 4 +bankaddr from bank size of rank 1 +jedec enable sequence: bank 5 +bankaddr from bank size of rank 4 +receive_enable_autoconfig() for channel 0 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=f3 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=73 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +receive_enable_autoconfig() for channel 1 + find_strobes_low() + set_receive_enable() medium=0x3, coarse=0x5 + set_receive_enable() medium=0x1, coarse=0x5 + find_strobes_edge() + set_receive_enable() medium=0x1, coarse=0x5 + add_quarter_clock() mediumcoarse=15 fine=c5 + set_receive_enable() medium=0x3, coarse=0x5 + find_preamble() + set_receive_enable() medium=0x3, coarse=0x4 + set_receive_enable() medium=0x3, coarse=0x3 + add_quarter_clock() mediumcoarse=0f fine=45 + normalize() + set_receive_enable() medium=0x0, coarse=0x4 +RAM initialization finished. +Setting up Egress Port RCRB +Loading p + +*** Log truncated, 497 characters dropped. *** + +Adding CBMEM entry as no. 3 +Trying CBFS ramstage loader. +CBFS: loading stage fallback/ramstage @ 0x100000 (327736 bytes), entry @ 0x100000 +coreboot-4.0-6195-g3b7c130-7BETC7WW (2.08 ) Tue Jun 3 16:36:44 BST 2014 booting... +BS: Entering BS_PRE_DEVICE state. +BS: Exiting BS_PRE_DEVICE state. +BS: BS_PRE_DEVICE times (us): entry 0 run 2976 exit 0 +BS: Entering BS_DEV_INIT_CHIPS state. +BS: Exiting BS_DEV_INIT_CHIPS state. +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3323 exit 0 +BS: Entering BS_DEV_ENUMERATE state. +Enumerating buses... +Show all devs...Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 00:69: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:5c: enabled 1 +I2C: 00:5d: enabled 1 +I2C: 00:5e: enabled 1 +I2C: 00:5f: enabled 1 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + DOMAIN: 0000: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:1b.0: enabled 1 + PCI: 00:1c.0: enabled 1 + PCI: 00:1c.1: enabled 1 + PCI: 00:1d.0: enabled 1 + PCI: 00:1d.1: enabled 1 + PCI: 00:1d.2: enabled 1 + PCI: 00:1d.3: enabled 1 + PCI: 00:1d.7: enabled 1 + PCI: 00:1f.0: enabled 1 + PNP: 00ff.1: enabled 1 + PNP: 00ff.2: enabled 1 + PNP: 164e.2: enabled 1 + PNP: 164e.3: enabled 0 + PNP: 164e.7: enabled 1 + PNP: 164e.19: enabled 1 + PNP: 002e.0: enabled 0 + PNP: 002e.1: enabled 1 + PNP: 002e.2: enabled 0 + PNP: 002e.3: enabled 1 + PNP: 002e.7: enabled 1 + PNP: 002e.a: enabled 0 + PCI: 00:1f.1: enabled 1 + PCI: 00:1f.2: enabled 1 + PCI: 00:1f.3: enabled 1 + I2C: 00:69: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:5c: enabled 1 + I2C: 00:5d: enabled 1 + I2C: 00:5e: enabled 1 + I2C: 00:5f: enabled 1 +scan_static_bus for Root Device +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/27a0] ops +PCI: 00:00.0 [8086/27a0] enabled +PCI: 00:02.0 [8086/27a2] ops +PCI: 00:02.0 [8086/27a2] enabled +PCI: 00:02.1 [8086/27a6] ops +PCI: 00:02.1 [8086/27a6] enabled +PCI: 00:1b.0 [8086/27d8] ops +PCI: 00:1b.0 [8086/27d8] enabled +PCI: 00:1c.0 [8086/0000] bus ops +PCI: 00:1c.0 [8086/27d0] enabled +PCI: 00:1c.1 [8086/0000] bus ops +PCI: 00:1c.1 [8086/27d2] enabled +PCI: 00:1c.2 [8086/0000] bus ops +PCI: 00:1c.2 [8086/27d4] enabled +PCI: 00:1c.3 [8086/0000] bus ops +PCI: 00:1c.3 [8086/27d6] enabled +PCI: 00:1d.0 [8086/27c8] ops +PCI: 00:1d.0 [8086/27c8] enabled +PCI: 00:1d.1 [8086/27c9] ops +PCI: 00:1d.1 [8086/27c9] enabled +PCI: 00:1d.2 [8086/27ca] ops +PCI: 00:1d.2 [8086/27ca] enabled +PCI: 00:1d.3 [8086/27cb] ops +PCI: 00:1d.3 [8086/27cb] enabled +PCI: 00:1d.7 [8086/27cc] ops +PCI: 00:1d.7 [8086/27cc] enabled +PCI: 00:1e.0 [8086/2448] bus ops +PCI: 00:1e.0 [8086/2448] enabled +PCI: 00:1f.0 [8086/27b9] bus ops +PCI: 00:1f.0 [8086/27b9] enabled +PCI: 00:1f.1 [8086/27df] ops +PCI: 00:1f.1 [8086/27df] enabled +PCI: 00:1f.2 [8086/0000] ops +PCI: 00:1f.2 [8086/27c4] enabled +PCI: 00:1f.3 [8086/27da] bus ops +PCI: 00:1f.3 [8086/27da] enabled +do_pci_scan_bridge for PCI: 00:1c.0 +PCI: pci_scan_bus for bus 01 +PCI: 01:00.0 [8086/109a] enabled +PCI: pci_scan_bus returning with max=001 +do_pci_scan_bridge returns max 1 +do_pci_scan_bridge for PCI: 00:1c.1 +PCI: pci_scan_bus for bus 02 +PCI: 02:00.0 [168c/002b] enabled +PCI: pci_scan_bus returning with max=002 +do_pci_scan_bridge returns max 2 +do_pci_scan_bridge for PCI: 00:1c.2 +PCI: pci_scan_bus for bus 03 +PCI: pci_scan_bus returning with max=003 +do_pci_scan_bridge returns max 3 +do_pci_scan_bridge for PCI: 00:1c.3 +PCI: pci_scan_bus for bus 04 +PCI: pci_scan_bus returning with max=004 +do_pci_scan_bridge returns max 4 +do_pci_scan_bridge for PCI: 00:1e.0 +PCI: pci_scan_bus for bus 05 +PCI: 05:00.0 [1180/0476] bus ops +PCI: 05:00.0 [1180/0476] enabled +PCI: 05:00.1 [1180/0552] enabled +PCI: 05:00.2 [1180/0822] enabled +PCI: 05:00.3 [1180/0843] enabled +do_pci_scan_bridge for PCI: 05:00.0 +PCI: pci_scan_bus for bus 06 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +PCI: pci_scan_bus returning with max=006 +do_pci_scan_bridge returns max 6 +scan_static_bus for PCI: 00:1f.0 +WARNING: No CMOS option 'touchpad'. +PNP: 00ff.1 enabled +recv_ec_data: 0x37 +recv_ec_data: 0x42 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x33 +recv_ec_data: 0x37 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x04 +recv_ec_data: 0x03 +recv_ec_data: 0x00 +recv_ec_data: 0x11 +EC Firmware ID 7BHT37WW-3.4, Version 0.01B +recv_ec_data: 0x00 +recv_ec_data: 0x10 +recv_ec_data: 0x20 +recv_ec_data: 0x30 +recv_ec_data: 0x00 +recv_ec_data: 0xa6 +recv_ec_data: 0x01 +recv_ec_data: 0x30 +PNP: 00ff.2 enabled +PNP: 164e.2 enabled +PNP: 164e.3 disabled +PNP: 164e.7 enabled +PNP: 164e.19 enabled +PNP: 002e.0 disabled +PNP: 002e.1 enabled +PNP: 002e.2 disabled +PNP: 002e.3 enabled +PNP: 002e.7 enabled +PNP: 002e.a disabled +scan_static_bus for PCI: 00:1f.0 done +scan_static_bus for PCI: 00:1f.3 +smbus: PCI: 00:1f.3[0]->I2C: 01:69 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled +scan_static_bus for PCI: 00:1f.3 done +PCI: pci_scan_bus returning with max=006 +scan_static_bus for Root Device done +done +BS: Exiting BS_DEV_ENUMERATE state. +BS: BS_DEV_ENUMERATE times (us): entry 0 run 529959 exit 0 +BS: Entering BS_DEV_RESOURCES state. +found VGA at PCI: 00:02.0 +Setting up VGA for PCI: 00:02.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. +PCI: 00:1c.0 read_resources bus 1 link: 0 +PCI: 00:1c.0 read_resources bus 1 link: 0 done +PCI: 00:1c.1 read_resources bus 2 link: 0 +PCI: 00:1c.1 read_resources bus 2 link: 0 done +PCI: 00:1c.2 read_resources bus 3 link: 0 +PCI: 00:1c.2 read_resources bus 3 link: 0 done +PCI: 00:1c.3 read_resources bus 4 link: 0 +PCI: 00:1c.3 read_resources bus 4 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 done +PCI: 00:1f.0 read_resources bus 0 link: 0 +PNP: 00ff.1 missing read_resources +PNP: 00ff.2 missing read_resources +PCI: 00:1f.0 read_resources bus 0 link: 0 done +PCI: 00:1f.3 read_resources bus 1 link: 0 +PCI: 00:1f.3 read_resources bus 1 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 + PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18 + PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 + PCI: 01:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 2c + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 34 + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags c0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags c0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags c0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags c0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 01:00.0 18 * [0x0 - 0x1f] io +PCI: 00:1c.0 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 05:00.0 2c * [0x0 - 0xfff] io +PCI: 05:00.0 34 * [0x1000 - 0x1fff] io +PCI: 00:1e.0 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 1c * [0x0 - 0x1fff] io +PCI: 00:1c.0 1c * [0x2000 - 0x2fff] io +PCI: 00:1d.0 20 * [0x3000 - 0x301f] io +PCI: 00:1d.1 20 * [0x3020 - 0x303f] io +PCI: 00:1d.2 20 * [0x3040 - 0x305f] io +PCI: 00:1d.3 20 * [0x3060 - 0x307f] io +PCI: 00:1f.1 20 * [0x3080 - 0x308f] io +PCI: 00:1f.2 20 * [0x3090 - 0x309f] io +PCI: 00:02.0 14 * [0x30a0 - 0x30a7] io +PCI: 00:1f.1 10 * [0x30a8 - 0x30af] io +PCI: 00:1f.1 18 * [0x30b0 - 0x30b7] io +PCI: 00:1f.2 10 * [0x30b8 - 0x30bf] io +PCI: 00:1f.2 18 * [0x30c0 - 0x30c7] io +PCI: 00:1f.1 14 * [0x30c8 - 0x30cb] io +PCI: 00:1f.1 1c * [0x30cc - 0x30cf] io +PCI: 00:1f.2 14 * [0x30d0 - 0x30d3] io +PCI: 00:1f.2 1c * [0x30d4 - 0x30d7] io +DOMAIN: 0000 compute_resources_io: base: 30d8 size: 30d8 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:00.0 10 * [0x0 - 0x1ffff] mem +PCI: 00:1c.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 02:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:1c.1 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 05:00.0 1c * [0x0 - 0x1ffffff] prefmem +PCI: 00:1e.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 05:00.0 24 * [0x0 - 0x1ffffff] mem +PCI: 05:00.0 10 * [0x2000000 - 0x2000fff] mem +PCI: 05:00.1 10 * [0x2001000 - 0x20017ff] mem +PCI: 05:00.2 10 * [0x2001800 - 0x20018ff] mem +PCI: 05:00.3 10 * [0x2001900 - 0x20019ff] mem +PCI: 00:1e.0 compute_resources_mem: base: 2001a00 size: 2100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem +PCI: 00:1e.0 20 * [0x10000000 - 0x120fffff] mem +PCI: 00:1e.0 24 * [0x12100000 - 0x140fffff] prefmem +PCI: 00:1c.0 20 * [0x14100000 - 0x141fffff] mem +PCI: 00:1c.1 20 * [0x14200000 - 0x142fffff] mem +PCI: 00:02.0 10 * [0x14300000 - 0x1437ffff] mem +PCI: 00:02.1 10 * [0x14380000 - 0x143fffff] mem +PCI: 00:02.0 1c * [0x14400000 - 0x1443ffff] mem +PCI: 00:1b.0 10 * [0x14440000 - 0x14443fff] mem +PCI: 00:1d.7 10 * [0x14444000 - 0x144443ff] mem +PCI: 00:1f.2 24 * [0x14444400 - 0x144447ff] mem +DOMAIN: 0000 compute_resources_mem: base: 14444800 size: 14444800 align: 28 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:02.0 +constrain_resources: PCI: 00:02.1 +constrain_resources: PCI: 00:1b.0 +constrain_resources: PCI: 00:1c.0 +constrain_resources: PCI: 01:00.0 +constrain_resources: PCI: 00:1c.1 +constrain_resources: PCI: 02:00.0 +constrain_resources: PCI: 00:1c.2 +constrain_resources: PCI: 00:1c.3 +constrain_resources: PCI: 00:1d.0 +constrain_resources: PCI: 00:1d.1 +constrain_resources: PCI: 00:1d.2 +constrain_resources: PCI: 00:1d.3 +constrain_resources: PCI: 00:1d.7 +constrain_resources: PCI: 00:1e.0 +constrain_resources: PCI: 05:00.0 +constrain_resources: PCI: 05:00.1 +constrain_resources: PCI: 05:00.2 +constrain_resources: PCI: 05:00.3 +constrain_resources: PCI: 00:1f.0 +constrain_resources: PNP: 00ff.1 +constrain_resources: PNP: 00ff.2 +skipping PNP: 00ff.2@60 fixed resource, size=0! +skipping PNP: 00ff.2@62 fixed resource, size=0! +skipping PNP: 00ff.2@64 fixed resource, size=0! +skipping PNP: 00ff.2@66 fixed resource, size=0! +constrain_resources: PNP: 164e.2 +constrain_resources: PNP: 164e.7 +constrain_resources: PNP: 164e.19 +constrain_resources: PNP: 002e.1 +constrain_resources: PNP: 002e.3 +constrain_resources: PNP: 002e.7 +constrain_resources: PCI: 00:1f.1 +constrain_resources: PCI: 00:1f.2 +constrain_resources: PCI: 00:1f.3 +constrain_resources: I2C: 01:69 +constrain_resources: I2C: 01:54 +constrain_resources: I2C: 01:55 +constrain_resources: I2C: 01:56 +constrain_resources: I2C: 01:57 +constrain_resources: I2C: 01:5c +constrain_resources: I2C: 01:5d +constrain_resources: I2C: 01:5e +constrain_resources: I2C: 01:5f +avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff + lim->base 00001690 lim->limit 0000ffff +avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff + lim->base 00000000 lim->limit efffffff +Setting resources... +DOMAIN: 0000 allocate_resources_io: base:1690 size:30d8 align:12 gran:0 limit:ffff +Assigned: PCI: 00:1e.0 1c * [0x2000 - 0x3fff] io +Assigned: PCI: 00:1c.0 1c * [0x4000 - 0x4fff] io +Assigned: PCI: 00:1d.0 20 * [0x5000 - 0x501f] io +Assigned: PCI: 00:1d.1 20 * [0x5020 - 0x503f] io +Assigned: PCI: 00:1d.2 20 * [0x5040 - 0x505f] io +Assigned: PCI: 00:1d.3 20 * [0x5060 - 0x507f] io +Assigned: PCI: 00:1f.1 20 * [0x5080 - 0x508f] io +Assigned: PCI: 00:1f.2 20 * [0x5090 - 0x509f] io +Assigned: PCI: 00:02.0 14 * [0x50a0 - 0x50a7] io +Assigned: PCI: 00:1f.1 10 * [0x50a8 - 0x50af] io +Assigned: PCI: 00:1f.1 18 * [0x50b0 - 0x50b7] io +Assigned: PCI: 00:1f.2 10 * [0x50b8 - 0x50bf] io +Assigned: PCI: 00:1f.2 18 * [0x50c0 - 0x50c7] io +Assigned: PCI: 00:1f.1 14 * [0x50c8 - 0x50cb] io +Assigned: PCI: 00:1f.1 1c * [0x50cc - 0x50cf] io +Assigned: PCI: 00:1f.2 14 * [0x50d0 - 0x50d3] io +Assigned: PCI: 00:1f.2 1c * [0x50d4 - 0x50d7] io +DOMAIN: 0000 allocate_resources_io: next_base: 50d8 size: 30d8 align: 12 gran: 0 done +PCI: 00:1c.0 allocate_resources_io: base:4000 size:1000 align:12 gran:12 limit:ffff +Assigned: PCI: 01:00.0 18 * [0x4000 - 0x401f] io +PCI: 00:1c.0 allocate_resources_io: next_base: 4020 size: 1000 align: 12 gran: 12 done +PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1e.0 allocate_resources_io: base:2000 size:2000 align:12 gran:12 limit:ffff +Assigned: PCI: 05:00.0 2c * [0x2000 - 0x2fff] io +Assigned: PCI: 05:00.0 34 * [0x3000 - 0x3fff] io +PCI: 00:1e.0 allocate_resources_io: next_base: 4000 size: 2000 align: 12 gran: 12 done +DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:14444800 align:28 gran:0 limit:efffffff +Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem +Assigned: PCI: 00:1e.0 20 * [0xe0000000 - 0xe20fffff] mem +Assigned: PCI: 00:1e.0 24 * [0xe2100000 - 0xe40fffff] prefmem +Assigned: PCI: 00:1c.0 20 * [0xe4100000 - 0xe41fffff] mem +Assigned: PCI: 00:1c.1 20 * [0xe4200000 - 0xe42fffff] mem +Assigned: PCI: 00:02.0 10 * [0xe4300000 - 0xe437ffff] mem +Assigned: PCI: 00:02.1 10 * [0xe4380000 - 0xe43fffff] mem +Assigned: PCI: 00:02.0 1c * [0xe4400000 - 0xe443ffff] mem +Assigned: PCI: 00:1b.0 10 * [0xe4440000 - 0xe4443fff] mem +Assigned: PCI: 00:1d.7 10 * [0xe4444000 - 0xe44443ff] mem +Assigned: PCI: 00:1f.2 24 * [0xe4444400 - 0xe44447ff] mem +DOMAIN: 0000 allocate_resources_mem: next_base: e4444800 size: 14444800 align: 28 gran: 0 done +PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 allocate_resources_mem: base:e4100000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 01:00.0 10 * [0xe4100000 - 0xe411ffff] mem +PCI: 00:1c.0 allocate_resources_mem: next_base: e4120000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_mem: base:e4200000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 02:00.0 10 * [0xe4200000 - 0xe420ffff] mem +PCI: 00:1c.1 allocate_resources_mem: next_base: e4210000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_prefmem: base:e2100000 size:2000000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 1c * [0xe2100000 - 0xe40fffff] prefmem +PCI: 00:1e.0 allocate_resources_prefmem: next_base: e4100000 size: 2000000 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_mem: base:e0000000 size:2100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 24 * [0xe0000000 - 0xe1ffffff] mem +Assigned: PCI: 05:00.0 10 * [0xe2000000 - 0xe2000fff] mem +Assigned: PCI: 05:00.1 10 * [0xe2001000 - 0xe20017ff] mem +Assigned: PCI: 05:00.2 10 * [0xe2001800 - 0xe20018ff] mem +Assigned: PCI: 05:00.3 10 * [0xe2001900 - 0xe20019ff] mem +PCI: 00:1e.0 allocate_resources_mem: next_base: e2001a00 size: 2100000 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +pci_tolm: 0xd0000000 +Base of stolen memory: 0xbf800000 +Top of Low Used DRAM: 0xc0000000 +IGD decoded, subtracting 8M UMA +Available memory: 3137536K (3064M) +Adding PCIe config bar +DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem +PCI: 00:02.0 10 <- [0x00e4300000 - 0x00e437ffff] size 0x00080000 gran 0x13 mem +PCI: 00:02.0 14 <- [0x00000050a0 - 0x00000050a7] size 0x00000008 gran 0x03 io +PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem +PCI: 00:02.0 1c <- [0x00e4400000 - 0x00e443ffff] size 0x00040000 gran 0x12 mem +PCI: 00:02.1 10 <- [0x00e4380000 - 0x00e43fffff] size 0x00080000 gran 0x13 mem +PCI: 00:1b.0 10 <- [0x00e4440000 - 0x00e4443fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem +PCI: 00:1c.0 20 <- [0x00e4100000 - 0x00e41fffff] size 0x00100000 gran 0x14 bus 01 mem +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 01:00.0 10 <- [0x00e4100000 - 0x00e411ffff] size 0x00020000 gran 0x11 mem +PCI: 01:00.0 18 <- [0x0000004000 - 0x000000401f] size 0x00000020 gran 0x05 io +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.1 20 <- [0x00e4200000 - 0x00e42fffff] size 0x00100000 gran 0x14 bus 02 mem +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 02:00.0 10 <- [0x00e4200000 - 0x00e420ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem +PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io +PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem +PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem +PCI: 00:1d.0 20 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io +PCI: 00:1d.1 20 <- [0x0000005020 - 0x000000503f] size 0x00000020 gran 0x05 io +PCI: 00:1d.2 20 <- [0x0000005040 - 0x000000505f] size 0x00000020 gran 0x05 io +PCI: 00:1d.3 20 <- [0x0000005060 - 0x000000507f] size 0x00000020 gran 0x05 io +PCI: 00:1d.7 10 <- [0x00e4444000 - 0x00e44443ff] size 0x00000400 gran 0x0a mem +PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 05 io +PCI: 00:1e.0 24 <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x14 bus 05 prefmem +PCI: 00:1e.0 20 <- [0x00e0000000 - 0x00e20fffff] size 0x02100000 gran 0x14 bus 05 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 05:00.0 In set resources +PCI: 05:00.0 10 <- [0x00e2000000 - 0x00e2000fff] size 0x00001000 gran 0x0c mem +PCI: 05:00.0 2c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 34 <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 1c <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x0c prefmem +PCI: 05:00.0 24 <- [0x00e0000000 - 0x00e1ffffff] size 0x02000000 gran 0x0c mem +PCI: 05:00.1 10 <- [0x00e2001000 - 0x00e20017ff] size 0x00000800 gran 0x0b mem +PCI: 05:00.2 10 <- [0x00e2001800 - 0x00e20018ff] size 0x00000100 gran 0x08 mem +PCI: 05:00.3 10 <- [0x00e2001900 - 0x00e20019ff] size 0x00000100 gran 0x08 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PNP: 00ff.1 missing set_resources +PNP: 00ff.2 missing set_resources +PNP: 164e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io +ERROR: PNP: 164e.2 70 irq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 74 drq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 75 drq size: 0x0000000001 not assigned +PNP: 164e.7 60 <- [0x0000001680 - 0x000000168f] size 0x00000010 gran 0x04 io +ERROR: PNP: 164e.7 70 irq size: 0x0000000001 not assigned +PNP: 164e.19 60 <- [0x000000164c - 0x000000164d] size 0x00000002 gran 0x01 io +ERROR: PNP: 164e.19 70 irq size: 0x0000000001 not assigned +PNP: 002e.1 60 <- [0x00000003bc - 0x00000007bb] size 0x00000400 gran 0x0a io +PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq +ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned +PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io +PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq +PNP: 002e.7 60 <- [0x0000001620 - 0x0000001627] size 0x00000008 gran 0x03 io +ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PCI: 00:1f.1 10 <- [0x00000050a8 - 0x00000050af] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 14 <- [0x00000050c8 - 0x00000050cb] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 18 <- [0x00000050b0 - 0x00000050b7] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 1c <- [0x00000050cc - 0x00000050cf] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 20 <- [0x0000005080 - 0x000000508f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 10 <- [0x00000050b8 - 0x00000050bf] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x00000050d0 - 0x00000050d3] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x00000050c0 - 0x00000050c7] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x00000050d4 - 0x00000050d7] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x0000005090 - 0x000000509f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 24 <- [0x00e4444400 - 0x00e44447ff] size 0x00000400 gran 0x0a mem +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +CBMEM region bf6d0000-bf7fffff (cbmem_late_set_table) +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 1690 size 30d8 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base d0000000 size 14444800 align 28 gran 0 limit efffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base bf800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base e4300000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:02.0 resource base 50a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 14 + PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001200 index 18 + PCI: 00:02.0 resource base e4400000 size 40000 align 18 gran 18 limit efffffff flags 60000200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base e4380000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base e4440000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 4000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.0 resource base e4100000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base e4100000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10 + PCI: 01:00.0 resource base 4000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.1 resource base e4200000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base e4200000 size 10000 align 16 gran 16 limit efffffff flags 60000201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 5000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 5020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 5040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 5060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base e4444000 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 2000 size 2000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1e.0 resource base e2100000 size 2000000 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1e.0 resource base e0000000 size 2100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base e2000000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 10 + PCI: 05:00.0 resource base 2000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 2c + PCI: 05:00.0 resource base 3000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 34 + PCI: 05:00.0 resource base e2100000 size 2000000 align 12 gran 12 limit efffffff flags 60001200 index 1c + PCI: 05:00.0 resource base e0000000 size 2000000 align 12 gran 12 limit efffffff flags 60000200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base e2001000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base e2001800 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base e2001900 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags e0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags e0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags e0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags e0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 50a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.1 resource base 50c8 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.1 resource base 50b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.1 resource base 50cc size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.1 resource base 5080 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 50b8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.2 resource base 50d0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.2 resource base 50c0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.2 resource base 50d4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.2 resource base 5090 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 resource base e4444400 size 400 align 10 gran 10 limit efffffff flags 60000200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +Done allocating resources. +BS: Exiting BS_DEV_RESOURCES state. +BS: BS_DEV_RESOURCES times (us): entry 0 run 3353777 exit 0 +BS: Entering BS_DEV_ENABLE state. +Enabling resources... +PCI: 00:00.0 subsystem <- 17aa/2017 +PCI: 00:00.0 cmd <- 06 +PCI: 00:02.0 subsystem <- 17aa/201a +PCI: 00:02.0 cmd <- 03 +PCI: 00:02.1 subsystem <- 17aa/201a +PCI: 00:02.1 cmd <- 02 +PCI: 00:1b.0 subsystem <- 17aa/2010 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 0000/0000 +PCI: 00:1c.0 cmd <- 107 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 0000/0000 +PCI: 00:1c.1 cmd <- 106 +PCI: 00:1c.2 bridge ctrl <- 0003 +PCI: 00:1c.2 cmd <- 00 +PCI: 00:1c.3 bridge ctrl <- 0003 +PCI: 00:1c.3 cmd <- 00 +PCI: 00:1d.0 subsystem <- 17aa/200a +PCI: 00:1d.0 cmd <- 01 +PCI: 00:1d.1 subsystem <- 17aa/200a +PCI: 00:1d.1 cmd <- 01 +PCI: 00:1d.2 subsystem <- 17aa/200a +PCI: 00:1d.2 cmd <- 01 +PCI: 00:1d.3 subsystem <- 17aa/200a +PCI: 00:1d.3 cmd <- 01 +PCI: 00:1d.7 subsystem <- 17aa/200b +PCI: 00:1d.7 cmd <- 102 +PCI: 00:1e.0 bridge ctrl <- 0003 +PCI: 00:1e.0 cmd <- 07 (NOT WRITTEN!) +PCI: 00:1f.0 subsystem <- 17aa/2009 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.1 subsystem <- 17aa/200c +PCI: 00:1f.1 cmd <- 01 +PCI: 00:1f.2 subsystem <- 17aa/200d +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 17aa/200f +PCI: 00:1f.3 cmd <- 101 +PCI: 01:00.0 cmd <- 03 +PCI: 02:00.0 cmd <- 02 +PCI: 05:00.0 bridge ctrl <- 0503 +PCI: 05:00.0 cmd <- 03 +PCI: 05:00.1 cmd <- 02 +PCI: 05:00.2 cmd <- 06 +PCI: 05:00.3 cmd <- 06 +done. +BS: Exiting BS_DEV_ENABLE state. +BS: BS_DEV_ENABLE times (us): entry 0 run 124466 exit 0 +BS: Entering BS_DEV_INIT state. +Initializing devices... +Root Device init +recv_ec_data: 0x11 +recv_ec_data: 0x11 +Root Device init 5771 usecs +CPU_CLUSTER: 0 init +start_eip=0x00001000, code_size=0x00000031 +Initializing SMM handler... ... pmbase = 0x0500 + +SMI_STS: MCSMI PM1 +PM1_STS: WAK PWRBTN TMROF +GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 +ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI12 GPI11 GPI10 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 +TCO_STS: INTRD_DET + ... raise SMI# +Initializing CPU #0 +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000bf800000 size 0xbf740000 type 6 +0x00000000bf800000 - 0x00000000d0000000 size 0x10800000 type 0 +0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 +0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 +MTRR addr 0x0-0x10 set to 6 type @ 0 +MTRR addr 0x10-0x20 set to 6 type @ 1 +MTRR addr 0x20-0x30 set to 6 type @ 2 +MTRR addr 0x30-0x40 set to 6 type @ 3 +MTRR addr 0x40-0x50 set to 6 type @ 4 +MTRR addr 0x50-0x60 set to 6 type @ 5 +MTRR addr 0x60-0x70 set to 6 type @ 6 +MTRR addr 0x70-0x80 set to 6 type @ 7 +MTRR addr 0x80-0x84 set to 6 type @ 8 +MTRR addr 0x84-0x88 set to 6 type @ 9 +MTRR addr 0x88-0x8c set to 6 type @ 10 +MTRR addr 0x8c-0x90 set to 6 type @ 11 +MTRR addr 0x90-0x94 set to 6 type @ 12 +MTRR addr 0x94-0x98 set to 6 type @ 13 +MTRR addr 0x98-0x9c set to 6 type @ 14 +MTRR addr 0x9c-0xa0 set to 6 type @ 15 +MTRR addr 0xa0-0xa4 set to 0 type @ 16 +MTRR addr 0xa4-0xa8 set to 0 type @ 17 +MTRR addr 0xa8-0xac set to 0 type @ 18 +MTRR addr 0xac-0xb0 set to 0 type @ 19 +MTRR addr 0xb0-0xb4 set to 0 type @ 20 +MTRR addr 0xb4-0xb8 set to 0 type @ 21 +MTRR addr 0xb8-0xbc set to 0 type @ 22 +MTRR addr 0xbc-0xc0 set to 0 type @ 23 +MTRR addr 0xc0-0xc1 set to 6 type @ 24 +MTRR addr 0xc1-0xc2 set to 6 type @ 25 +MTRR addr 0xc2-0xc3 set to 6 type @ 26 +MTRR addr 0xc3-0xc4 set to 6 type @ 27 +MTRR addr 0xc4-0xc5 set to 6 type @ 28 +MTRR addr 0xc5-0xc6 set to 6 type @ 29 +MTRR addr 0xc6-0xc7 set to 6 type @ 30 +MTRR addr 0xc7-0xc8 set to 6 type @ 31 +MTRR addr 0xc8-0xc9 set to 6 type @ 32 +MTRR addr 0xc9-0xca set to 6 type @ 33 +MTRR addr 0xca-0xcb set to 6 type @ 34 +MTRR addr 0xcb-0xcc set to 6 type @ 35 +MTRR addr 0xcc-0xcd set to 6 type @ 36 +MTRR addr 0xcd-0xce set to 6 type @ 37 +MTRR addr 0xce-0xcf set to 6 type @ 38 +MTRR addr 0xcf-0xd0 set to 6 type @ 39 +MTRR addr 0xd0-0xd1 set to 6 type @ 40 +MTRR addr 0xd1-0xd2 set to 6 type @ 41 +MTRR addr 0xd2-0xd3 set to 6 type @ 42 +MTRR addr 0xd3-0xd4 set to 6 type @ 43 +MTRR addr 0xd4-0xd5 set to 6 type @ 44 +MTRR addr 0xd5-0xd6 set to 6 type @ 45 +MTRR addr 0xd6-0xd7 set to 6 type @ 46 +MTRR addr 0xd7-0xd8 set to 6 type @ 47 +MTRR addr 0xd8-0xd9 set to 6 type @ 48 +MTRR addr 0xd9-0xda set to 6 type @ 49 +MTRR addr 0xda-0xdb set to 6 type @ 50 +MTRR addr 0xdb-0xdc set to 6 type @ 51 +MTRR addr 0xdc-0xdd set to 6 type @ 52 +MTRR addr 0xdd-0xde set to 6 type @ 53 +MTRR addr 0xde-0xdf set to 6 type @ 54 +MTRR addr 0xdf-0xe0 set to 6 type @ 55 +MTRR addr 0xe0-0xe1 set to 6 type @ 56 +MTRR addr 0xe1-0xe2 set to 6 type @ 57 +MTRR addr 0xe2-0xe3 set to 6 type @ 58 +MTRR addr 0xe3-0xe4 set to 6 type @ 59 +MTRR addr 0xe4-0xe5 set to 6 type @ 60 +MTRR addr 0xe5-0xe6 set to 6 type @ 61 +MTRR addr 0xe6-0xe7 set to 6 type @ 62 +MTRR addr 0xe7-0xe8 set to 6 type @ 63 +MTRR addr 0xe8-0xe9 set to 6 type @ 64 +MTRR addr 0xe9-0xea set to 6 type @ 65 +MTRR addr 0xea-0xeb set to 6 type @ 66 +MTRR addr 0xeb-0xec set to 6 type @ 67 +MTRR addr 0xec-0xed set to 6 type @ 68 +MTRR addr 0xed-0xee set to 6 type @ 69 +MTRR addr 0xee-0xef set to 6 type @ 70 +MTRR addr 0xef-0xf0 set to 6 type @ 71 +MTRR addr 0xf0-0xf1 set to 6 type @ 72 +MTRR addr 0xf1-0xf2 set to 6 type @ 73 +MTRR addr 0xf2-0xf3 set to 6 type @ 74 +MTRR addr 0xf3-0xf4 set to 6 type @ 75 +MTRR addr 0xf4-0xf5 set to 6 type @ 76 +MTRR addr 0xf5-0xf6 set to 6 type @ 77 +MTRR addr 0xf6-0xf7 set to 6 type @ 78 +MTRR addr 0xf7-0xf8 set to 6 type @ 79 +MTRR addr 0xf8-0xf9 set to 6 type @ 80 +MTRR addr 0xf9-0xfa set to 6 type @ 81 +MTRR addr 0xfa-0xfb set to 6 type @ 82 +MTRR addr 0xfb-0xfc set to 6 type @ 83 +MTRR addr 0xfc-0xfd set to 6 type @ 84 +MTRR addr 0xfd-0xfe set to 6 type @ 85 +MTRR addr 0xfe-0xff set to 6 type @ 86 +MTRR addr 0xff-0x100 set to 6 type @ 87 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: default type WB/UC MTRR counts: 4/4. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x00 done. +CPU: 0 2 siblings +CPU: 0 has sibling 1 +CPU #0 initialized +CPU1: stack_base 0014a000, stack_end 0014aff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++Sending STARTUP #2 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #1 +Waiting for 1 CPUS to stop +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x01 done. +CPU: 1 2 siblings +CPU #1 initialized +CPU 1 going down... +All AP CPUs stopped (11642 loops) +CPU1: stack: 0014a000 - 0014b000, lowest used address 0014ac68, stack used: 920 bytes +CPU_CLUSTER: 0 init 687602 usecs +PCI: 00:00.0 init +Normal boot. +PCI: 00:00.0 init 2905 usecs +PCI: 00:02.0 init +In CBFS, ROM address for PCI: 00:02.0 = ffe007b8 +PCI expansion ROM, signature 0xaa55, INIT size 0x10000, data ptr 0x0040 +PCI ROM image, vendor ID 8086, device ID 27a2, +PCI ROM image, Class Code 030000, Code Type 00 +Copying VGA ROM Image from ffe007b8 to 0xc0000, 0x10000 bytes +Real mode stub @00000600: 867 bytes +Calling Option ROM... +int15_handler: AX=5f40 BX=d103 CX=0055 DX=0002 +DISPLAY=3 +int15_handler: AX=5f34 BX=078f CX=0002 DX=0002 +Unknown INT15 function 5f34! +int15 call returned error. +int15_handler: AX=5f35 BX=078f CX=0002 DX=00c0 +... Option ROM returned. +VGA Option ROM was run +gma_func0_init: After VBIOS/native init: GMADR=0xd0000008 GTTADR=0xe4400000 +PCI: 00:02.0 init 175395 usecs +PCI: 00:02.1 init +PCI: 00:02.1 init 2383 usecs +PCI: 00:1b.0 init +Azalia: codec type: Azalia +Azalia: base = e4440000 +Azalia: codec_mask = 03 +Azalia: Initializing codec #1 +Azalia: codec viddid: 14f12bfa +Azalia: No verb! +Azalia: Initializing codec #0 +Azalia: codec viddid: 11d41981 +Azalia: No verb! +PCI: 00:1b.0 init 25808 usecs +PCI: 00:1c.0 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.0 init 4491 usecs +PCI: 00:1c.1 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.1 init 4490 usecs +PCI: 00:1c.2 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.2 init 4491 usecs +PCI: 00:1c.3 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.3 init 4491 usecs +PCI: 00:1d.0 init +UHCI: Setting up controller.. done. +PCI: 00:1d.0 init 4923 usecs +PCI: 00:1d.1 init +UHCI: Setting up controller.. done. +PCI: 00:1d.1 init 4924 usecs +PCI: 00:1d.2 init +UHCI: Setting up controller.. done. +PCI: 00:1d.2 init 4924 usecs +PCI: 00:1d.3 init +UHCI: Setting up controller.. done. +PCI: 00:1d.3 init 4925 usecs +PCI: 00:1d.7 init +EHCI: Setting up controller.. done. +PCI: 00:1d.7 init 4933 usecs +PCI: 00:1e.0 init +PCI: 00:1e.0 init 1681 usecs +PCI: 00:1f.0 init +i82801gx: lpc_init +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +IOAPIC: Dumping registers + reg 0x0000: 0x02000000 + reg 0x0001: 0x00170020 + reg 0x0002: 0x00170020 +WARNING: No CMOS option 'power_on_after_fail'. +Set power on after power failure. +NMI sources enabled. +rtc_failed = 0x0 +RTC Init +i8259_configure_irq_trigger: current interrupts are 0x0 +i8259_configure_irq_trigger: try to set interrupts 0x200 +Disabling ACPI via APMC: +done. +Locking SMM. +PCI: 00:1f.0 init 50464 usecs +PCI: 00:1f.1 init +i82801gx_ide: initializing... IDE0 +PCI: 00:1f.1 init 4941 usecs +PCI: 00:1f.2 init +i82801gx_sata: initializing... +SATA controller in AHCI mode. +PCI: 00:1f.2 init 7211 usecs +PCI: 01:00.0 init +PCI: 01:00.0 init 1668 usecs +PCI: 02:00.0 init +PCI: 02:00.0 init 1670 usecs +PCI: 05:00.0 init +Ricoh RL5c476: Initializing. +CF Base = 0 +CF boot not enabled. +PCI: 05:00.0 init 7378 usecs +PCI: 05:00.1 init +PCI: 05:00.1 init 1669 usecs +PCI: 05:00.2 init +PCI: 05:00.2 init 1671 usecs +PCI: 05:00.3 init +PCI: 05:00.3 init 1671 usecs +PNP: 164e.2 init +PNP: 164e.2 init 1584 usecs +PNP: 164e.7 init +PNP: 164e.7 init 1583 usecs +PNP: 164e.19 init +PNP: 164e.19 init 1670 usecs +PNP: 002e.1 init +PNP: 002e.1 init 1582 usecs +PNP: 002e.3 init +PNP: 002e.3 init 1583 usecs +PNP: 002e.7 init +PNP: 002e.7 init 1582 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:69 init +I2C: 01:69 init 16211 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:54 init +I2C: 01:54 init 3591 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:55 init +I2C: 01:55 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:56 init +I2C: 01:56 init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:57 init +I2C: 01:57 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5c init +Locking EEPROM RFID +init EEPROM done +I2C: 01:5c init 28615 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5d init +I2C: 01:5d init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5e init +I2C: 01:5e init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5f init +I2C: 01:5f init 3592 usecs +Devices initialized +Show all devs...After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 01:69: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:5c: enabled 1 +I2C: 01:5d: enabled 1 +I2C: 01:5e: enabled 1 +I2C: 01:5f: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 01:00.0: enabled 1 +PCI: 02:00.0: enabled 1 +PCI: 05:00.0: enabled 1 +PCI: 05:00.1: enabled 1 +PCI: 05:00.2: enabled 1 +PCI: 05:00.3: enabled 1 +APIC: 01: enabled 1 +BS: Exiting BS_DEV_INIT state. +BS: BS_DEV_INIT times (us): entry 0 run 1321463 exit 0 +BS: Entering BS_POST_DEVICE state. +CBMEM region bf6d0000-bf7fffff (cbmem_check_toc) +Adding CBMEM entry as no. 4 +Moving GDT to bf6e0600...ok +Finalize devices... +Devices finalized +BS: Exiting BS_POST_DEVICE state. +BS: BS_POST_DEVICE times (us): entry 9470 run 6558 exit 0 +BS: Entering BS_OS_RESUME_CHECK state. +BS: Exiting BS_OS_RESUME_CHECK state. +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3401 exit 0 +BS: Entering BS_WRITE_TABLES state. +Copying Interrupt Routing Table to 0x000f0000... done. +Adding CBMEM entry as no. 5 +Copying Interrupt Routing Table to 0xbf6e0800... done. +PIRQ table: 272 bytes. +Wrote the mp table end at: 000f0410 - 000f05cc +Adding CBMEM entry as no. 6 +Wrote the mp table end at: bf6e1810 - bf6e19cc +MP table: 460 bytes. +Adding CBMEM entry as no. 7 +ACPI: Writing ACPI tables at bf6e2800. +ACPI: * HPET +ACPI: added table 1/32, length now 40 +ACPI: * MADT +ACPI: added table 2/32, length now 44 +ACPI: * MCFG +ACPI: added table 3/32, length now 48 +ACPI: * FACS +ACPI: Patching up global NVS in DSDT at offset 0x0263 -> 0xbf6e5c10 +ACPI: * DSDT @ bf6e2b40 Length 30ca +ACPI: * FADT +ACPI: added table 4/32, length now 52 +ACPI: * SSDT +Found 1 CPU(s) with 2 core(s) each. +clocks between 1000 and 1666 MHz. +adding 3 P-States between busratio 6 and a, incl. P0 +PSS: 1666MHz power 31000 control 0xa1e status 0xa1e +PSS: 1333MHz power 22050 control 0x818 status 0x818 +PSS: 1000MHz power 13100 control 0x613 status 0x613 +clocks between 1000 and 1666 MHz. +adding 3 P-States between busratio 6 and a, incl. P0 +PSS: 1666MHz power 31000 control 0xa1e status 0xa1e +PSS: 1333MHz power 22050 control 0x818 status 0x818 +PSS: 1000MHz power 13100 control 0x613 status 0x613 +ACPI: added table 5/32, length now 56 +current = bf6e6110 +ACPI: done. +Laptop handling... +ACPI tables: 14608 bytes. +Adding CBMEM entry as no. 8 +smbios_write_tables: bf6edc00 +Root Device (Lenovo ThinkPad X60 / X60s) +recv_ec_data: 0x37 +recv_ec_data: 0x42 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x33 +recv_ec_data: 0x37 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x04 +recv_ec_data: 0x03 +CPU_CLUSTER: 0 (Intel i945 Northbridge) +APIC: 00 (Socket mFCPGA478 CPU) +DOMAIN: 0000 (Intel i945 Northbridge) +PCI: 00:00.0 (Intel i945 Northbridge) +PCI: 00:02.0 (Intel i945 Northbridge) +PCI: 00:02.1 (Intel i945 Northbridge) +PCI: 00:1b.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1c.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1c.1 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.0 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.1 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.2 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.3 (Intel ICH7/ICH7-M (82801Gx) Series Southbridge) +PCI: 00:1d.7 (Intel ICH7/I +4509 bytes lost diff --git a/i18n/fr_FR/docs/future/dumps/coreboot_5926_oprom_grub_config b/i18n/fr_FR/docs/future/dumps/coreboot_5926_oprom_grub_config new file mode 100644 index 00000000..dedf3ae6 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/coreboot_5926_oprom_grub_config @@ -0,0 +1,449 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_EXPERT=y +CONFIG_LOCALVERSION="7BETC7WW (2.08 )" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_BROKEN_CAR_MIGRATE is not set +# CONFIG_DYNAMIC_CBMEM is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_ADVANTECH is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_ARIMA is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASI is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AXUS is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_EAGLELION is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NEWISYS is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_TECHNOLOGIC is not set +# CONFIG_VENDOR_TELEVIDEO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x60" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60 / X60s" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="Lenovo" +CONFIG_MAX_CPUS=2 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_VGA_BIOS_ID="8086,27a2" +CONFIG_DRIVERS_PS2_KEYBOARD=y +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_VGA_BIOS=y +# CONFIG_UDELAY_IO is not set +CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_ACPI_SSDTX_NUM=0 +CONFIG_VGA_BIOS_FILE="vgabios.bin" +# CONFIG_PCI_64BIT_PREF_MEM is not set +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_STACK_SIZE=0x1000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x200000 +CONFIG_BOARD_LENOVO_X60=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_MAINBOARD_VERSION="ThinkPad X60" +CONFIG_CPU_ADDR_BITS=32 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_MAINBOARD_SERIAL_NUMBER="L3AZ921" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="1703WMF" +CONFIG_ARCH_X86=y +# CONFIG_ARCH_ARMV7 is not set +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +CONFIG_AP_IN_SIPI_WAIT=y +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_ROMCC is not set +CONFIG_PC80_SYSTEM=y +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_HPET_ADDRESS=0xfed00000 +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_UPDATE_IMAGE is not set + +# +# Chipset +# + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_CPU_TI_AM335X is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0 +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_SMM_TSEG_SIZE=0 +CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_MODULES is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y +CONFIG_CPU_MICROCODE_CBFS_GENERATE=y +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set +# CONFIG_CPU_MICROCODE_CBFS_NONE is not set + +# +# Northbridge +# +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +CONFIG_S3_VGA_ROM_RUN=y +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_EHCI_BAR=0xfef00000 +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87392=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_DOCK_EARLY_INIT=y +CONFIG_EC_LENOVO_PMH7=y + +# +# SoC +# + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set +# CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is not set +CONFIG_VGA_ROM_RUN=y +# CONFIG_ALWAYS_LOAD_OPROM is not set +CONFIG_ON_DEVICE_ROM_RUN=y +CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y +# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_AGP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCI_BUS_SEGN_BITS=0 +# CONFIG_EARLY_PCI_BRIDGE is not set + +# +# VGA BIOS +# + +# +# Display +# +# CONFIG_FRAMEBUFFER_SET_VESA_MODE is not set +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# PXE ROM +# +# CONFIG_PXE_ROM is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 + +# +# Generic Drivers +# +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_TPM is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +CONFIG_DRIVERS_UART=y +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000 +CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_POST_IO is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_HAVE_ACPI_SLIC is not set +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +# CONFIG_VGA is not set +# CONFIG_GFXUMA is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_HAVE_REFCODE_BLOB is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y + +# +# System tables +# +CONFIG_GENERATE_ACPI_TABLES=y +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_PAYLOAD_FILE="grub.elf" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_REALMODE_DEBUG is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +CONFIG_REG_SCRIPT=y +CONFIG_MAX_REBOOT_CNT=3 diff --git a/i18n/fr_FR/docs/future/dumps/grub.cfg b/i18n/fr_FR/docs/future/dumps/grub.cfg new file mode 100644 index 00000000..c3a9d073 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/grub.cfg @@ -0,0 +1,38 @@ +set default="0" +set timeout=1 +set pager=1 + +menuentry 'GNU+Linux with linux-libre 3.14.4' { + linux (ahci0,1)/boot/vmlinuz-3.14.4-gnuowen root=/dev/sda1 processor.max_cstate=2 drm.debug=0x06 console=tty0 console=ttyS0,115200n8 + initrd (ahci0,1)/boot/initrd.img-3.14.4-gnuowen +} +menuentry 'Parse ISOLINUX menu (USB)' { + set root='usb0' + syslinux_configfile -i (usb0)/isolinux/isolinux.cfg +} +menuentry 'Parse ISOLINUX menu (CD)' { + set root='ata0' + syslinux_configfile -i (ata0)/isolinux/isolinux.cfg +} +menuentry 'Scan for GRUB configurations on the internal HDD (Permits to load other OS or distributions)' { + insmod regexp + insmod ahci + insmod part_msdos + for x in (ahci0,*) ; do + if [ -f "$x/grub/grub.cfg" ] ; then + submenu "Load Config from $x" $x { + root=$2 + source /grub/grub.cfg + unset superusers + } + fi + if [ -f "$x/boot/grub/grub.cfg" ] ; then + submenu "Load Config from $x" $x { + root=$2 + source /boot/grub/grub.cfg + unset superusers + } + fi + done +} + diff --git a/i18n/fr_FR/docs/future/dumps/grub_memdisk_serial.cfg b/i18n/fr_FR/docs/future/dumps/grub_memdisk_serial.cfg new file mode 100644 index 00000000..92009107 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/grub_memdisk_serial.cfg @@ -0,0 +1,10 @@ +#Serial and keyboard configuration, very important. +serial --speed=115200 --unit=0 --word=8 --parity=no --stop=1 +terminal_input --append serial +terminal_output --append serial +terminal_input --append at_keyboard #add keyboard support. + +set prefix=(memdisk)/boot/grub + +set root='cbfsdisk' +source (cbfsdisk)/grub.cfg diff --git a/i18n/fr_FR/docs/future/dumps/kernel312_irc b/i18n/fr_FR/docs/future/dumps/kernel312_irc new file mode 100644 index 00000000..81ff687c --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/kernel312_irc @@ -0,0 +1,1589 @@ +
+ +

Coreboot 5926 test for Paul Menzel

+

+ Coreboot log when running Video BIOS (grub payload) and http://review.coreboot.org/5926. +

+

+ Result (ThinkPad X60): cbmem -c output
+ Config used on the X60 (grub payload and vbios): .config +

+ + + + + + + + + + + +

Coreboot 5893 test for Paul Menzel

+

+ With VBIOS
+ With native graphics (replay code). +

+

+ Here is a crash dump from running native graphics (): /sys/class/drm/card0/error. +

+ +
+ +

early attempt: i945 stolen memory fix (for kernel 3.12/later) (this attempt failed)

+

+Back then we had no idea that GTT address was incorrect, and we had no idea what was causing the issue. + +

+Note: see this fix for the initial fix that was found.
+
+not working yet
+http://review.coreboot.org/#/c/5885/
+
+untested. will test this.
+checkout 5320. cherry pick 5345 on top.
+mannually apply changes from 5884/1 and 5885/3
+make backlight changes as in #x60_native_notes and #t60_native_notes
+test this on X60 and T60.
+
+If it works, manually apply 5885 to 5320 alone and then push with 5320 as dependency.
+Rebase that new change ID, and rebase 5345 (pushing it as new change ID).
+Manually merge the rebased 5345 into the new patch, and then push that.
+
+Boot with grub (obviosly!) and kernel 3.14.4 as before (with 17fec8a left untouched!).
+
+Note: tidy these notes! (so others can follow)
+
+get those logs:
+Make a copy of these files:
+ * /var/log/dmesg
+ * /var/log/kern.log
+ * /var/log/Xorg.0.log
+ * /var/log/Xorg.0.log.old (If you have to restart gdm)
+ * /proc/ioports
+ * /proc/iomem
+Record these outputs:
+ * sudo intel_reg_dumper
+ * uname -r
+ * lspci -vvnn
+Do this first: $ sudo modprobe msr (then do as below):
+ * sudo inteltool -a       --> in coreboot/src/util/inteltool
+Make a copy of:
+ * coreboot serial output log.
+ --> Get it from serial port, or get it like that:
+ --> ./cbmem -c (under coreboot/util/cbmem)
+Output from source tree:
+$ git log -p | head -150       (localhost/x60gitlog)
+$ git diff								(localhost/x60gitdiff)
+Make a copy of the .config from coreboot source tree
+ ^										(localhost/x60config)
+3D acceleration test (test if 3.12+/stolenmem issue is fixed):
+ - Run openarena (1024x768 res), say if it works. (note: Press tilde, do /cg_drawfps 1)
+ - Run tuxcart (1024x768 res), say if it works.
+ - Run neverball (1024x768 res), say if it works.
+ - Run glxgears, report what you see.
+
+Some results on the X60 (3D still doesn't work, openarena and tuxkart were slow): 
+5885_logs.tar.gz
+git diff: http://paste.debian.net/102618/
+
+In src/northbridge/intel/i945/raminit.c
+PaulePanter: vimuser: In your next step could you please add
+PaulePanter: printk(BIOS_DEBUG, "BSM = 0x%08x\n", pci_read_config32(PCI_DEV(0,2,0), BSM));
+PaulePanter: before
+PaulePanter: pci_write_config32(PCI_DEV(0,2,0), BSM, (tolud * MiB - 64 * MiB) & 0xfff00000);
+done
+Also removing the #if statement around those 2 lines above.
+Also adding it after that line aswell, per advice from PaulePanter
+
+Some new results on the X60 after doing the above (3D still doesn't work, openarena and tuxkart were slow): 
+5885_logs_2.tar.gz
+
+PaulePanter: vimuser: No idea if you can write with `devmem2`. Never used it.
+PaulePanter: vimuser: It would indeed be interesting to know what value the BSM has with the vendor BIOS.
+Note to self: do that.
+
+PaulePanter said: I have `& 0xfff00000` and phcoder uses `& 0xfffff000`, so it looks like I have the ordering incorrect.
+
+
+Look at that discussion:
+http://lists.freedesktop.org/archives/intel-gfx/2014-May/046309.html
+http://lists.freedesktop.org/archives/intel-gfx/2014-May/046310.html
+--> if BSM register is read-only, then is there something els ethat we might have missed?
+
+
+

+ + + + + + + + + + +

kernel 3.12+ bugs (X60/T60 native init)Back to top of page

+

+ Some further notes to refer to later (WARNING: long! These are collected IRC logs for later reference. Most of the + logs are not useful or relevant, and will be deleted later): + +

+Note: see this fix for the initial fix that was found.
+
+see: http://www.coreboot.org/Board:lenovo/x60#Problems_in_native_graphics_code_exposed_by_recent_kernels
+see: http://www.coreboot.org/Lenovo_x60x_vgainit_todos
+
+Non-coreboot (not even i945) platforms also have issues with 3.12+
+see: https://bugs.freedesktop.org/show_bug.cgi?id=76520
+
+Is this relevant?: http://lists.freedesktop.org/archives/intel-gfx/2014-February/040771.html
+
+
+
+note: read below.
+and note: on later kernels they also can't seem to init the GPU properly without vbios or native gfx, whereas older kernels could.
+
+PaulePanter: damo22: There is also a Linux and coreboot native graphics incompatibility documented in the Wiki (by samnob).
+PaulePanter: http://www.coreboot.org/Board:lenovo/x60#Problems_in_native_graphics_code_exposed_by_recent_kernels
+vimuser: PaulePanter, that only exists with kernel 3.12 and above. 
+PaulePanter: vimuser: Do you have time to report it to the Freedesktop Bugzilla?
+funfunctor:  patrickg: I think its related to recent changes we had done to toolchain.in
+vimuser: Yes. What info do you need ?
+PaulePanter: vimuser: It’s a regressions and these are normally not allowed with Linux’ no regression policy.
+vimuser: What do you think would happen then, after I made that report?
+PaulePanter: vimuser: https://01.org/linuxgraphics/documentation/how-report-bugs
+vimuser: You can look at it 2 ways: kernel broke, or kernel fixed a bug which broke coreboot.
+PaulePanter: vimuser: Hopefully they’ll fix it.
+vimuser: so: either coreboot is broken, or kernel is broken. 
+vimuser: PaulePanter, kernel 3.12+ should work just fine on lenovo bios, so my opinion is that the native gfx in coreboot is what's buggy.
+PaulePanter: vimuser: You can also check with the developers in #intel-gfx. But first report the bug so you can reference it.
+vimuser: Do you think I should just copy what's in the coreboot wiki already?
+PaulePanter: vimuser: Does not matter. If it worked before 3.12, it should work afterward.
+vimuser: It seems pretty complete (as far as reporting it is concerned).
+vimuser: PaulePanter, my basic point is that I'm on the fence as to whether this is linux's problem, coreboot's problem, or both.
+PaulePanter: vimuser: That would probably help. If they need other information, the Intel folks will ask you for it. Daniel Vetter and the other Intel folks are very responsive in my experience.
+vimuser: So you think then that there would be a patch specifically for i915 + coreboot_native_init
+PaulePanter: vimuser: I do not know. They hopefully figure it out.
+vimuser: PaulePanter, I will do it.
+PaulePanter: vimuser: And as I wrote, it is a regression. As far as I understood it, even if the firmware/hardware is broken, Linux should not introduce regressions.
+vimuser: PaulePanter: at the very least, it might offer a new perspective. this whole issue has been very one-sided so far: it has only been coreboot community that talks about it. It has probably gone unobserved in kernel/intel community.
+vimuser: The intel/kernel people might even be able to (easily) spot a fix for coreboot.
+vimuser: I hadn't even considered this possibility before, I thought it was only a coreboot problem. Talking to those other people definitely makes sense.
+
+PaulePanter of #coreboot made the initial report to Freedesktop tracker:
+
+PaulePanter: vimuser: Hi. Did you report the Linux regression to the Freedesktop bug tracker?
+PaulePanter: vimuser: Understood. Do you have an account for the Freedesktop bug tracker?
+vimuser: PaulePanter: I do not have an account for Freedesktop bug tracker, but I think I could get one?
+PaulePanter: vimuser: Yes, it is easy to register.
+vimuser: PaulePanter, there's reporting and there's reporting properly; I want to compile my report first, before I make it. 
+PaulePanter: vimuser: As you do not know what they need, I think it is the wrong approach.
+vimuser: Since the people that I am reporting to will be unfamiliar with the issue, and might not even know about coreboot, or only vaguely know.
+PaulePanter: vimuser: I’ll report the issue and give you the URL. You can then add to it.
+vimuser: PaulePanter: Good point. I can make it brief describing it as best I can, and then I can answer any specific questions.
+vimuser: PaulePanter, you can use my notes at http://libreboot.org/howto.html#kernel312bugs if you like, it's a collection of insights plus links to those pages on the coreboot wiki that talk about the issue.
+vimuser: (in case there is anything in the notes that might be helpful)
+vimuser: PaulePanter, are the intel i915 devs of freedesktop also the ones working on the i915 code in kernel.org? (I'm slightly confused about this)
+
+THE REPORT:
+
+PaulePanter: vimuser: The Wiki talks about crashes.
+PaulePanter: vimuser: https://bugs.freedesktop.org/show_bug.cgi?id=79038
+
+PaulePanter: vimuser: The Wiki talks about crashes.
+PaulePanter: vimuser: https://bugs.freedesktop.org/show_bug.cgi?id=79038
+vimuser: PaulePanter, thanks. I'll add to it and help any way I can.
+PaulePanter: vimuser: Add `drm.debug=0x06` to the Linux command line (probably configuring in GRUB) and please add `/var/log/dmesg` to the bug report. (Or the output of `dmesg`.)
+PaulePanter: vimuser: They also need `/var/log/Xorg.0.log` and your distribution and exact Linux kernel version `uname -r`.
+vimuser: PaulePanter: there are basically 2 versions of native init: 3998 (based on replay, only works on X60 with XGA screen - also what libreboot currently uses) and 5320 (much better, works on more screens, 5345 can use it to enable T60 - not yet in libreboot)
+vimuser: PaulePanter: should I do this test on both versions? (libreboot and coreboot+5320+5345)
+
+vimuser: PaulePanter: should I do this test on both versions? (libreboot and coreboot+5320+5345)
+vimuser: PaulePanter: nonetheless, I will do both, and make that report for you now.
+vimuser: Do I do this on pre-3.12 kernel or 3.12+ ?
+PaulePanter: vimuser: I’d say Linux 3.12+.
+PaulePanter: vimuser: Do you know which coreboot patches samnob used?
+
+vimuser: PaulePanter: very well. http://jxself.org/linux-libre has latest kernels
+vimuser: I will install that.
+vimuser: I do not know what coreboot patches samnob used. Probably 3998 (this was a long time ago).
+vimuser: Definitely change ID 3998 (review.coreboot.org gerrit): http://review.coreboot.org/#/c/3998/
+
+
+vimuser: PaulePanter: here is the information that you requested: http://libreboot.org/logs/3998_Xorg.0.log http://libreboot.org/logs/3998_dmesg http://libreboot.org/logs/3998_uname
+vimuser: PaulePanter: that bug in the report doesn't happen with the above -- it's an older kernel. 
+vimuser: Do they want me to try 3.12+ instead?
+vimuser: PaulePanter: you should also give them these links to the lastest code for native graphics:
+vimuser: http://review.coreboot.org/#/c/5320/
+
+PaulePanter: vimuser: Thank you for getting the logs. Please register and upload the files yourself.
+vimuser: Yes, ok. I will also get the same logs again for a kernel that is broken (3.12+)
+vimuser: I will repeat both processes again for coreboot+5320+5345, as currently I am getting these on libreboot. 
+vimuser: More logs can't hurt, the worst that can happen is they will ignore the ones they don't need. I want to make sure they have everything they need.
+
+samnob: vimuser: samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnuowen_1_i386.deb and http://samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnu-stolenmem-owen_1_i386.deb latest linux-libre without and with 17fec8a reverted.
+PaulePanter: vimuser: Thanks.
+
+vimuser: samnob, thanks.
+vimuser: but we are trying to get kernel 3.12+ to work without users having to patch it
+vimuser: either by fixing coreboot, or patching around coreboot in the kernel
+vimuser: eventually both
+samnob: Yes, just providing you kernels for the bug.
+vimuser: ah right. 
+vimuser: with and without. that is useful. i was going to use jxself kernels. that is useful.
+vimuser: I'll use yours then ;)
+vimuser: dpkg -i ?
+
+samnob: Though based on the devs comment in the bug I think you're hope of the driver working around it is unlikely.
+vimuser: can't hurt to try
+samnob: dpkg -i will work fine.
+samnob: (though gdebi is more fun.)
+samnob: there's a version symlink_hook in that same folder that is handy for grub2 payload users too.
+vimuser: samnob we think it might be classed under linux "no regression" policy
+vimuser: PaulePanter's idea
+samnob: can't hurt to try :)
+
+Here is the debugging results then: coreboot_native_3.12_bug.tar.gz
+
+---
+
+http://undeadly.org/cgi?action=article&sid=20131120060004 was suggested
+(also refer back te the datasheet)
+
+----
+
+I have since been alerted to this bug report, which is unrelated to us
+but shows that 3.12 also breaks later systems on Lenovo BIOS (as far as I can tell):
+
+https://bugzilla.kernel.org/show_bug.cgi?id=71391
+
+--
+
+PaulePanter:  vimuser: If you run the Lenovo X60 right now, could you just paste it now. It should not change between all your tests.
+PaulePanter:  vimuser: It would really be helpful to have it now.
+vimuser: My workstation X60 is running coreboot+5320 (and modification for backlight control support)
+vimuser: Shall I take iomem output from that?
+vimuser: kernel 3.2 is in use
+PaulePanter:  vimuser: Yes. Please.
+vimuser: For you record:
+vimuser: $ uname -r
+vimuser: 3.2.0-56-generic-pae
+vimuser: PaulePanter: http://paste.debian.net/101404/
+
+PaulePanter linked to this:
+http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-desktop-vol-2-datasheet.pdf
+---------------
+
+PaulePanter: patrickg: As the resident i945 export, do you know where the register GBSM (Graphics Base of Stolen Memory) should be set?
+PaulePanter: patrickg: Is the VGA Option ROM responsible for that?
+PaulePanter: damo22: You do not see any problems with the VGA Option ROM, right?
+damo22: PaulePanter: i am running vga rom with updated kernel (after the patch) and experience no problems with video
+PaulePanter: damo22: Thank you for the confirmation.
+PaulePanter: src/northbridge/intel/i945/northbridge.c:       printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
+patrickg:  PaulePanter: what's that, 0x5c?
+patrickg:  h, no
+PaulePanter: + /* Almost universally we can find the Graphics Base of Stolen Memory
+PaulePanter: + * at offset 0x5c in the igfx configuration space. On a few (desktop)patrickg:  PaulePanter: I think we never configured that but left it to vgabios
+patrickg:  PaulePanter: we only configured the RAM side
+PaulePanter: patrickg: Thanks. So with native VGA init, coreboot needs to do that too.
+damo22: we just need to write the gfxstolen base to gma config space at 0x5c
+damo22: that should fix it
+damo22: because then the kernel will try to read that
+damo22: hmm but if the generation of the gma is not >=3 it will assume it is above top of memory
+patrickg:  well, it is
+damo22: patrickg: do you happen to know if the x60 gma is generation 2 or 3? how do i find out
+PaulePanter: damo22: lspci ?
+damo22: (rev 0x)?
+PaulePanter: lspci -nn
+damo22: never mind i will ctags the kernel tree
+patrickg:  but bbl
+patrickg:  damo22: code.metager.de applies openGrok on tons of open source projects. probably to linux, too
+damo22: thanks patrickg
+damo22: okay, i945g/gm is generation 3
+damo22: its nothing to do with the lscpi revision
+PaulePanter: damo22: How did you check that?
+PaulePanter: … it is 3rd gen?
+damo22: PaulePanter: its in the i915_drv.c in the kernel
+damo22: eg, i965g/gm is generation 4
+PaulePanter: Ok.
+damo22: its also NOT valleyview
+* pl4nkton is now known as pl4nkton`away
+PaulePanter: damo22: ?
+PaulePanter: Who said that?
+damo22: im trying to figure out which path the kernel takes before and after the patch
+damo22: it must be different
+PaulePanter: damo22: https://bugs.freedesktop.org/show_bug.cgi?id=79038#c12
+PaulePanter: damo22: Before they calculate it manually and afterward they read out that register, which the firmware should program, right?
+PaulePanter: src/northbridge/intel/i945/i945.h:#define TOLUD         0x9c    /* Top of Low Used Memory */
+PaulePanter: Off topic, how do I make Vim and Ctags jump to the correct header definition. If I Ctrl + click on `TOLUD` in `src/northbridge/intel/i945/raminit.c` it jumps into the header of `intel/fsp_sandybridge/northbridge.h` instead of `src/northbridge/intel/i945/i945.h`.
+PaulePanter: ?
+damo22: i have the same problem, there is a way to configure it to pop up a list of matches so you can select the right one but i dont know how
+PaulePanter: damo22: Ok. Good to know I am not the only one.
+
+damo22: okay, so for gen 3 i915, (i945/m) we can do what i said above and it should work
+PaulePanter: Is “graphics datastolen memory size (PCI Device 0 offset 52 bits 7:4)” configurable and programmed by the firmware or is it fixed if the IGP is enabled and can just be read?
+PaulePanter: damo22: Yes.
+damo22: its just a matter of setting the base address in the register
+damo22: i think the only difference is that in the kernel it is assumed that it is aligned to 0x100000
+damo22: kernel does this: base &= ~((1<<20) - 1);
+damo22: but coreboot does this: pci_read_config32(dev, 0x5c) & ~0xf,
+damo22: possibly a one liner
+damo22: change ~0xf to ~0xfffff lol
+samnob: vimuser: samnoble.org/thinkpad/kernel/linux-image-3.14.4-gnu-stolenmem-owen_2_i386.deb and linux-image-3.14.4-gnuowen_2_i386.deb with CONFIG_STRICT_DEVMEM unset. No PAE as always.
+samnob: damo22: thanks for looking into this.
+
+vimuser: damo22: you are the most awesome person ever. I'm stilll preparing my dev/debugging environment and you speculate this already. I will try it soon.
+vimuser: samnob: thank you for confirming.
+vimuser: samnob: ok, /dev/mem support and non-PAE. excellent! 
+samnob: vimuser: don't overlook that revision 2 those, are new debs with STRICT_DEVMEM unset
+damo22: vimuser: its much quicker to read and compare code than to compile kernels and flash firmware
+PaulePanter: vimuser: I think your testing is not needed until you get a patch.
+PaulePanter: damo22: TOLUD (PCI Device 0 offset BCh bits 31:20)
+vimuser: PaulePanter ?
+vimuser: Yes I understand that. I was about to debug, but now we will test damo22's advice first.
+damo22: PaulePanter: i think intel_gma_init is being called with unaligned physical address for graphics mem
+
+PaulePanter: vimuser: BDSM—Base Data of Stolen Memory Register
+PaulePanter: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-desktop-vol-2-datasheet.pdf
+
+PaulePanter: vimuser: The methods you try just read it out and never set it.
+PaulePanter: This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BCh bits 31:20).
+damo22: PaulePanter: im pretty sure BDSM is only present in core iX cpus
+vimuser: PaulePanter, yes my method was to go about to be sure where it is set, and then try to set it properly in 5320. 
+PaulePanter: vimuser: The problem is already present with native graphics in coreboot master, isn’t it?
+vimuser: damo22 took a shorter method to get the same result (hopefully. like you, i wait for him to confirm or deny success)
+vimuser: PaulePanter, yes the 3.12+ glitches exist in 5320 changeset aswell as 3998 (the old replay version, which 5320 is a re-write of)
+PaulePanter: vimuser: Sorry, I claim your tests would have never gotten any solution for the problem.
+* martinr (~martin@8.36.227.227) has joined #coreboot
+vimuser: PaulePanter, that is quite possible, but it was a test anyway. 
+PaulePanter: damo22: Chris Wilson and the Linux commit say that the BDSM is present, don’t they?
+PaulePanter: + if (INTEL_INFO(dev)->gen >= 3) {
+PaulePanter: + /* Read Graphics Base of Stolen Memory directly */
+vimuser: I actually did find where the stolen memory address was set, in /var/log/kern.log after using drm.debug=0x06 in those previous results i uploaded to freedesktop.org, but that was on coreboot/5320 with the address set incorrectly.
+vimuser: just search for the word "stolen" in the log and you'll find it on one of the lines.
+
+PaulePanter: vimuser: It’s not *set* it is *read* in there.
+vimuser: Oh right.
+vimuser: But I thought when reading it, it has to know the address. So the address I saw must have been what was set?
+vimuser: What am I missing?
+damo22: okay so there is something to clarify, i915 driver is the same for all intel gpus even some that are physically located in cpu
+
+PaulePanter: vimuser: As it is not explicitely set beforehand it contains some incorrect value, which is then read.
+PaulePanter: vimuser: That is the whole problem.
+vimuser: I see.
+vimuser: So,
+vimuser: my tests would have been useless, then.
+
+damo22: it didnt work
+(note: can still try to make other changes: see testing notes below)
+
+damo22: oh wait, X just didnt detect the LVDS
+damo22: in fact nothing did
+damo22: but there were no errors
+damo22: ok so when i plug external monitor X freezes and gives errors
+damo22: and internal display isnt active
+damo22: wierd, when i rebooted i got vga fine
+damo22: i think linux kernel i915 is trying to do something with vgarom because it says "invalid rom contents" as first boot line
+damo22: no i need to find out if the kernel is doing something bad without rom present
+damo22: and then figure out how to enable lvds, because vga is working
+vimuser: drivers/pci/rom.c:   dev_err(&pdev->dev, "Invalid ROM contents\n");
+vimuser: in that: size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size)
+vimuser:                 /* Standard PCI ROMs start out with these bytes 55 AA */
+vimuser:                 if (readb(image) != 0x55) {
+vimuser:                         dev_err(&pdev->dev, "Invalid ROM contents\n");
+vimuser:                         break;
+vimuser:                 }
+damo22: i guess i should focus on the fact that coreboot did not initialise the gfx at grub screen
+damo22: i mean seabios
+damo22: its difficult because linux does some reinitialisation of gfx
+damo22: i thought i had this one in the bag
+CareBear\: damo22 : it does complete reinit
+damo22: i flicked throught the kernel i915 driver and it looks like it reads VBT tables from romheaders or something
+damo22: if we are using native gfx init, those are not present right?
+samnob:  damo22: I think you need to be using grub2 to test native gfx init, seabios needs at least a stub of a vgarom.
+CareBear\: damo22 : correct
+CareBear\: samnob damo22 : if you want to use SeaBIOS you can use the SeaVGABIOS which will pick up a native framebuffer initialized by coreboot
+damo22: does SeaVGABIOS install VBT stuff in the vgarom area?
+CareBear\: damo22 : probably not the kind the framebuffer driver looks for
+damo22: then it will fail with linux
+CareBear\: damo22 : yes
+damo22: CareBear\: can we write a vgabios stub that passes the signature tests and also has native VBT tables, but executes nothing?
+damo22: otherwise we need to patch the linux kernel to ignore certain models that have no vgabios
+CareBear\: damo22 : let's first find out what information is used in those tables
+damo22: i have the code in front of me
+damo22: drivers/gpu/drm/i915/intel_bios.c (kernel)
+damo22: vimuser: no, i am trawling through linux driver code
+vimuser: damo22: are you aware that certain kernels can initialize the GPU on X60 without the native gfx or oprom? (you don't see payloads, but kernel/X11 shows display
+damo22: i have a feeling the linux kernel currently tries to load the vgarom regardless of PCH existance
+
+damo22: i think there are two problems with native gfx init, one problem is that the lvds isnt coming up (coreboot issue), the other is is with the linux kernel i915 driver that tries to read the vgarom that isnt there
+
+vimuser: damo22, what hardware are you testing your changes on?
+vimuser: Did you try 5320 without your changes?
+vimuser: (hardware: X60 or T60)
+
+Peter on 5320 talks about vga pipe not being enabled: this means that payload doesn't appear
+on vga (only on lvds). OS can output on vga or lvds. so we need to get 5320 to output (during payload) on vga
+
+damo22: i just slept on it, and i think i know what the problem is
+
+         * LVDS discovery:
+         * 1) check for EDID on DDC
+         * 2) check for VBT data
+         * 3) check to see if LVDS is already on
+         *    if none of the above, no panel
+
+
+1) it cant find the EDID because the i2c is failing to read with NAK
+2) there is no VBT data because there is no vga option rom
+3) coreboot is still not doing native init properly so the panel is still off
+
+Therefore linux assumes there is no LVDS.
+
+damo22: how do i enable cbmem console? i enabled it in menuconfig, do i need cbmem dynamically growing?
+damo22: [*] Send console output to a CBMEM buffer\
+damo22: but i got nothing
+
+Guest-FR: Hi
+Guest-FR: would you please check
+Guest-FR: src/northbridge/intel/i945/gma.c
+Guest-FR: function gma_func0_disable
+Guest-FR: pci_write_config16(dev, GCFC, 0xa00) , sound wrong isn't it?
+
+damo22: Guest-FR: what do you think is wrong about it?
+Guest-FR: per the datasheet (intel, so probably it is also wrong!) , the value should be "0x1b"
+Guest-FR: page 74
+damo22: Guest-FR: can you link me to the datasheet
+Guest-FR: damo22: congig16 is expecting 0x && 4 digits isn't it?
+Guest-FR: damo22: e.i.: 0x1234
+damo22: Guest-FR: 0xa00 === 0x0a00
+damo22: same thing
+Guest-FR: ok
+
+Guest-FR: here is the link for tha datasheet http://www.intel.com/Assets/PDF/datasheet/307502.pdf
+
+damo22: ty
+damo22: Guest-FR: i am also working on this gma
+damo22: Guest-FR: i am trying to figure out why native gfx init is not working on my X60 tablet
+
+Guest-FR: per gma.h, GCFC is  0xf0    /* Graphics Clock Frequency & Gating Control */
+damo22: Guest-FR: GCFC is missing from the datasheet
+damo22: so how do you know its wrong
+Guest-FR: it is my mistake.... I'm expecting to see 4 digits for conf16
+damo22: Guest-FR: ok, i would have expected GCFC to be on page 62 at the bottom but its missing
+Guest-FR: probably we should make a dump to see the value we have with an original bios. what you think ? is it possible?
+damo22: Guest-FR: however, GGC is mismatching between that datasheet and in coreboot gma
+Guest-FR: intel is a fu*** company
+damo22: ahh no, i looked up the wrong file
+damo22: it matches
+damo22: Guest-FR: i am assuming you are using patched gma to test?
+Guest-FR: damo22: no, I use the original one
+damo22: Guest-FR: http://review.coreboot.org/#/c/5320/
+Guest-FR: I try to port my board to coorboot https://github.com/coreboot-for-945g-m4/945g-m4
+Guest-FR: thx damo22
+damo22: Guest-FR: you need extra config in devicetree.cb with that
+Guest-FR: damo22: http://review.coreboot.org/#/c/5762/
+damo22: Guest-FR: i cant view it
+Guest-FR: oops, it is draft
+Guest-FR: may I add you as a reviewer ?
+damo22: Guest-FR: sure
+Guest-FR: damo at zamodio?
+damo22: correct
+Guest-FR: done
+Guest-FR: please feel free put comments (and be verbos, I'm not a developper :p )
+Guest-FR: probably my devicetree is not good,
+damo22: it still wont load
+Guest-FR: damien at zamaudio.com ?
+damo22: yes
+damo22: ok better
+Guest-FR: probably you got an email ?
+Guest-FR: for a review
+damo22: Guest-FR: i dont see native gfx init
+damo22: are you using vgarom?
+Guest-FR: I'm using a PCIE card (Radeon X300)
+damo22: dont you want to try to initialise the onboard gfx?
+Guest-FR: why not, I'll give it a go :)
+damo22: you showed me a whole bunch of code, but what is the problem?
+Guest-FR: the serial is working, but it hang on "setting up static southbridge register ..."
+Guest-FR: and some times, it went to "setting up Root Complex Topology"
+damo22: Guest-FR: well, look for that message in the code and find the next message that should be displayed and you know the problem is between the two messaged
+Guest-FR: there is some thing unstable
+damo22: messages*
+Guest-FR: ok
+damo22: Guest-FR: if its too hard to find, add some printk's
+damo22: i could really use a tip on how to enable cbmem console
+damo22: im running blind
+
+Guest-FR:  the msg ih at  " src/northbridge/intel/i945/early_init.c " i945_setup_bars function
+Guest-FR: so my problem is between "Setting up static southbridge registers..." and "Done" :)
+
+damo22: cat .config|grep CBMEM ===> http://paste.debian.net/101541/  why do i still not have any cbmem console? "No console found in coreboot table."
+content of debian paste:
+CONFIG_EARLY_CBMEM_INIT=y
+# CONFIG_DYNAMIC_CBMEM is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+damo22: No coreboot CBMEM area found!
+* Guest-FR (d5f5ab0b@gateway/web/freenode/ip.213.245.171.11) has joined #coreboot
+Guest-FR: I'd like to understand: is there any difference betweent: pci_write_config16(LPC_DEV, 0x84, 0x0a01); + pci_write_config16(LPC_DEV, 0x86, 0x00fc); vs pci_write_config32(LPC_DEV, 0x84, 0x00fc0a01);
+Guest-FR: for exemple: lenovo/x60/romstage.c we have:  pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601); however in the ich7 datasheet page 364 it is a  conf32
+
+phcoder-screen: damo22: for C segment. boot with oprom, then dd if=/dev/mem bs=64k of=seg_cdef.bin skip=12 count=4
+damo22: ok
+damo22: is that the VBT table?
+phcoder-screen: part of it is
+damo22: phcoder-screen: http://www.zamaudio.com/mbox2/seg_cdef.bin
+damo22: it looks correct because it mentions calistoga
+damo22: phcoder-screen: as a general solution, would it be possible to write a script that takes a vgarom as input and outputs a vgarom stub that will have no executable code but still have the VBT stuff and signatures to fool the OS that real vgarom is there, and will detect panels etc
+damo22: or is there a better way?
+
+phcoder-screen: damo22: there is a better way: generate it in coreboot. I have a tool to partially parse the roms. Trying it with yours.
+damo22: cool
+
+phcoder-screen: damo22: http://pastebin.com/GsYhSaNB
+Content of that paste:
+signature: <$VBT CALISTOGA      >
+version: 1.00
+VBT size: 0xea0
+VBT checksum: 0x0
+BDB version: 1.29
+section type 254, size 0xea
+	type: 0
+	relstage: 64
+	chipset: 1
+	LVDS
+	No TV
+	rsvd3[0]: 0x8
+	rsvd3[1]: 0x3
+	rsvd3[2]: 0x31
+	rsvd3[3]: 0x33
+	Signon: 13Intel(r)Calistoga PCI Accelerated SVGA BIOS
+Build Number: 1313d.dal  PC 14.20  Dev   10/17/2006  0:22:30
+DECOMPILATION OR DISASSEMBLY PROHIBITED
+
+	Copyright: 
+	Code segment: a
+	DOS Boot mode: 0
+	Bandwidth percent: c0
+	rsvd4: 0x3
+	Bandwidth percent: 8
+	rsvd5: 0x4
+section type 1, size 0x5
+General features:
+	panel_fitting = 0x3
+	flexaim = 0x1
+	download_ext_vbt = 0x1
+	*enable_ssc = 0x1
+	*ssc_freq = 0x1
+	*display_clock_mode = 0x0
+	disable_smooth_vision = 0x0
+	*fdi_rx_polarity_inverted = 0x0
+	legacy_monitor_detect = 0x1
+	*int_crt_support = 0x1
+	*int_tv_support = 0x0
+section type 254, size 0x20
+section type 2, size 0xcb
+	*CRT DDC GMBUS pin: 2
+	DPMS ACPI: 0
+	Skip boot CRT detect: 0
+	DPMS aim: 1
+	boot_display: { 0, 0 }
+	6 devices
+	*device type: 1009 (TV)
+	 *dvo_port: 5
+	 *i2c_pin: 0
+	 *slave_addr: 0
+	 *ddc_pin: 0
+	 *dvo_wiring: 0
+	 edid_ptr: 0
+	*device type: 1022 (flat panel)
+	 *dvo_port: 4
+	 *i2c_pin: 0
+	 *slave_addr: 0
+	 *ddc_pin: 3
+	 *dvo_wiring: 0
+	 edid_ptr: 0
+	*device type: 0 (Empty)
+	*device type: 0 (Empty)
+	*device type: 0 (Empty)
+	*device type: 0 (Empty)
+section type 3, size 0x1
+section type 4, size 0x1c
+section type 254, size 0x69
+section type 6, size 0x16d
+section type 7, size 0x7
+section type 8, size 0x3d
+section type 10, size 0xcb
+section type 11, size 0xc7
+section type 12, size 0xf
+	*LVDS config: 1
+	*Dual frequency: 1
+section type 13, size 0x3
+section type 14, size 0x9
+section type 15, size 0x8b
+section type 16, size 0x84
+section type 17, size 0x8
+section type 18, size 0xc
+section type 19, size 0x20
+section type 20, size 0x9e
+section type 22, size 0x15
+	*Panel type: 3
+section type 23, size 0x48
+section type 24, size 0x28
+section type 25, size 0x28
+section type 26, size 0x2
+section type 40, size 0x8
+section type 41, size 0x91
+section type 42, size 0x4a0
+section type 43, size 0x61
+section type 44, size 0x15
+damo22: phcoder-screen: does that mean for every supported board, an extra step will be needed to parse the roms so that the port can be done
+damo22: *CRT DDC GMBUS pin: 2
+damo22: i think it is trying pin 3
+phcoder-screen: damo22: CRT is VGA
+phcoder-screen: ddc_pin is 3 under lvds section
+damo22: oh yeah
+phcoder-screen: damo22: we already need some info in device tree to init. I think we can reuse it
+phcoder-screen: I can upload my parser if you want
+damo22: sure, i can parse my T60 and X60t
+damo22: and eventually T61
+phcoder-screen: CL 5842
+damo22: thanks
+
+damo22: phcoder-screen: do you think the EDID is failing to read in linux because the VBT is missing?
+
+phcoder-screen: damo22: it's a likely explanation. I'd reput first 64k of your dump back to place
+damo22: where does it belong in the flash?
+damo22: c0000?
+phcoder-screen: damo22: nowhere. c0000 is in RAM
+damo22: so how do i ensure it gets loaded into ram at c0000
+phcoder-screen: damo22: memcpy
+damo22: im convinced it will work if i do that
+damo22: thats like loading the vgarom
+damo22: but without executing it
+phcoder-screen: damo22: yes
+damo22: couldnt i just select it in menuconfig, but comment out the code that runs it?
+phcoder-screen: yes
+phcoder-screen: and keep in mind that oprom is self-modifying
+damo22: yes so i need the final dump to load not the original
+phcoder-screen: yes
+
+
+
+--
+
+Side discussion (in #libreboot, not #coreboot as above):
+
+vimuser: damo22: what was the problem?
+damo22: EDID is not being read in linux
+damo22: well it is, but it fails
+damo22: probably because the VBT signature is missing from the oprom
+vimuser: oprom?
+vimuser: You mean native init code?
+vimuser: that it doesn't put the proper data in vbt
+damo22: there is some special metadata in the oprom that native init doesnt put in
+damo22: linux looks for it
+damo22: thats how it knows where to read the EDID from
+damo22: otherwise it uses a default address that could be wrong
+damo22: in some cases it works
+damo22: other cases like my X60t it fails
+vimuser: that would explain why "read-edid" utility deosn't work on natisev gfx at the mament
+vimuser: moment
+vimuser: Basstard` ^
+
+damo22: vimuser: phcoder wrote an experimental utility to parse some of the VBT tables from a vgarom
+vimuser: Did he share it with you?
+damo22: yes
+vimuser: Did he upload it publicly?
+damo22: http://review.coreboot.org/#/c/5842/
+vimuser: Ok cool.
+vimuser: Do you think I should try it?
+
+damo22: you could use it to get more info from all your known boards, collect the parsed tables in a folder correctly named with the type of panel and the type of laptop
+vimuser: So as per #coreboot, my understanding is: move to new stolen memory address, find that metadata and how it's calculated and write that (memcpy/write32) in native init, get VBT tables parsed from ROM, replicate that in native gfx (stub code, just the addresses and pointers to the native init code)
+vimuser: Should this be run an a vgabios.bin, or on a system where vga bios is running (parse it in memory) ?
+vimuser: or both?
+damo22: we havent got a solution for native init yet, but we do need to collect info from different models
+damo22: to see how they compare
+vimuser: yes so, vgabios.bin (file) or running vga bios?
+damo22: and also we can add it to devicetree.cb somehow later
+damo22: preferably the running vgabios
+vimuser: ok
+damo22: you can dump it with this command:
+damo22: sudo dd if=/dev/mem bs=64k of=runningvga.bin skip=12 count=1
+
+damo22: coreboot/util/intelvbttool
+
+damo22: gcc intelvbttool.c -o intelvbttool
+
+vimuser: it would be good for you to run intelvbttool on vgabios.bin and runningvgabios.bin. (where vgabios.bin is extracted from lenovo rom, and runningvgabios.bin is dd'd from memory after it executed)
+vimuser: right?
+vimuser: (I will do the same)
+vimuser: just runningvgabios.bin ?
+damo22: its useless in the factory bios
+damo22: for the purposes of this test
+vimuser: ok
+vimuser: Can't hurt though (might be useful later).
+damo22: not really, it might be modified at runtime and we wont know anything about it
+damo22: we need final values
+damo22: the rest is irrelevant
+vimuser: Yes. I was saying to run it on final dump, and factory dump.
+vimuser: but ok, i will only do it for final dump
+
+--
+
+further discussion, continued in #coreboot:
+
+damo22:we could generate fake_vbt arrays for each model
+damo22:vimuser: whats the link to the vbt stuff again
+vimuser: http://review.coreboot.org/#/c/5396 for X230
+damo22:vimuser: no on libreboot
+vimuser: I also added this to the notes at http://libreboot.org/howto.html#i945_vbt and http://libreboot.org/howto.html#intelvbttool_results for future reference.
+vimuser: on libreboot? I don't understand.
+damo22:its possible that the VBT is modified by the vgarom depending on the panel it detects, assuming it can do that
+damo22:only problem is, you need info from the VBT to know where to read the EDID, so how does the vgarom do it?
+damo22:maybe its safe to assume that the EDID i2c will be the same for all panels
+vimuser: Might be hardcoded (what CareBear calls "stupid magic numbers")
+damo22:so we should check all VBTs of the same laptop model and verify that the EDID i2c or ddc pin is the same for all panel types
+vimuser: Sorry, when you say VBT do you mean the runningvga.bin dump taken with dd when vgarom is running?
+damo22:then we can hardcode that value into the coreboot devicetree.cb
+
+vimuser: I see. it's an i2c bus that connects lvds/vga/vga out
+kmalkki:damo22: in your opinion, where is this EDID eeprom physically located?
+damo22:kmalkki: on the panel, or the transformer for the panel
+kmalkki:damo22: what do you think is a transformer for the panel?
+damo22:some circuitry that interfaces between the lvds connector and the panel itself
+damo22:on the T60 there is a separate module afaik
+damo22:on other models it might be incorporated into the panel idk
+damo22:kmalkki: i believe that the VBT has information regarding which pin of the i2c to read for the EDID eeprom/storage
+damo22:and it varies panel to panel
+kmalkki:would it surprise you DDC signals are often not on the panel connector
+damo22:hmm
+
+kmalkki:like, x60 schematics is easily available, do check on some alternative ways how these are done
+damo22:ok
+
+kmalkki:damo22: for t60 however... LCD connector does have EDID lines
+damo22:kmalkki: well it would be nice to have a general solution to EDID reading
+damo22:i need to understand the wiring more and the VBT
+kmalkki:DDC signals originate from the graphics device
+kmalkki:that will be Intel for some, ATI for some T60 ?
+
+damo22:kmalkki: linux expects the VBT to be in the vgarom memory area, because it uses it to identify when a panel exists, so coreboot should provide VBT like a vendor bios ?
+
+damo22:when vgarom is used with coreboot there is no problem , but for native gfx init it doesnt always work
+kmalkki:ok.. so we can ignore ATI case for now
+damo22:kmalkki: is that because no native init will be done for that case?
+damo22:so the vgarom will always work
+kmalkki:ok.. so do you know VBT format?
+damo22:kmalkki: phcoder has done lots of work on it already
+kmalkki:and.. is there a problem in reading the EDID?
+damo22:kmalkki: idk yet, i need to test
+damo22:im having trouble building a coreboot rom that uses coreboots native framebuffer so i can see if it worked
+damo22:linux reinits the gfx so its not a good test
+damo22:but in any case, without the VBT, linux cant reinit my gfx
+damo22:it fails to read the EDID
+damo22:and without a dock, and cbmem console isnt working, i cant get the coreboot log to check what actually happened
+kmalkki:what do you mean cbmem console not working?
+damo22:kmalkki: i enabled it in menuconfig and built a rom, but when i run it on my X60t cbmem -c reports No console found
+kmalkki:we should get it fixed then
+kmalkki:paste your .config
+damo22:http://paste.debian.net/101644/
+
+kmalkki:git hash is from local tree.. it does work on master, right?
+damo22:idk
+damo22:i just cherry picked some native gfx patches
+damo22:why would it affect cbmem console
+kmalkki:mess up MTRRs or memory space mapping or UMA region...
+damo22:ok
+kmalkki:are those patches on gerrit you picked?
+damo22:well i need these patches because that is why i need the console
+damo22:yes
+damo22:actually i did minor changes too
+damo22::S
+kmalkki:yep.. which patches exactly
+damo22:5320
+damo22:then i changed 2 lines
+damo22:a minor devicetree.cb line and this:
+damo22:-       intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf,
+damo22:+       intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xfffff,
+kmalkki:ok.. also paste 'git log' so I find common hash from master
+damo22:http://paste.debian.net/101645/
+
+damo22:does anyone have better google xen than me, i cant seem to find a pdf of x60 schematics
+Basstard' damo22: Do you mean this? http://www.computerservice.es/wp-content/uploads/2013/05/IBM-X60.pdf
+
+damo22:yep thanks
+kmalkki:and now that I am awake, I see DDC signals on x60 LCD too
+kmalkki:just.. no DDC or I2C in the signal name but EDID
+damo22:yeah
+damo22:what bus does the lvds connector use
+damo22:is that i2c?
+damo22:or should i say, how standard is that lcd connector they are using on the X60
+kmalkki:mainboard side is completely non-standard AFAIK
+damo22:ohhh
+kmalkki:panel side has a few variants on the LVDS input
+damo22:ok
+damo22:this is not easy to generalise then
+damo22:SPWG_EDID_CLK and SPWG_EDID_DATA are the signals i found on the connector
+
+kmalkki:yes. and it looks like phcoder-screen has done all the work to read the EDID
+damo22:yes but the address and pins required are stored in the VBT i think
+kmalkki:solve your CBMEM console, please
+damo22:yea
+Basstard' damo22: Here's a cleaner one: http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006054.pdf
+kmalkki:just verify 1315730 works
+damo22:1315730?
+
+GNUtoo-irssi: vimuser: hi, 0x58BF58BE works fine --- cool. (not related to these discussions, but GNUtoo is happy).
+
+
+GNUtoo-irssi: phcoder-screen: if you're still working on native GPU init for i945(it seems so), I've an observation:
+GNUtoo-irssi: gtt is not setup correctly anymore with your versions, the kenrel complains
+GNUtoo-irssi: it was with a replay version, so if you're still working on it it may be an usefull hint
+GNUtoo-irssi: I've added the code that works inside git, so if you want/need it, ping me
+phcoder-screen:damo22: yes
+GNUtoo-irssi: beside the kernel warning, the effect is slow 3D with a 3.10 lts kernel
+damo22:GNUtoo-irssi: can you push it as a notformerge?
+GNUtoo-irssi: ok, good idea
+GNUtoo-irssi: ah sigh, again...
+GNUtoo-irssi:  ! [remote rejected] HEAD -> refs/for/master/NOTFORMERGE-reference-i915_gpu_init-x60 (change 3992 closed)
+GNUtoo-irssi: I'll change the IDs
+damo22:GNUtoo-irssi: have you seen 5230?
+damo22:5320*
+phcoder-screen:damo22: rank 0 of either channel is configured but not rank 1
+GNUtoo-irssi: let me look
+GNUtoo-irssi: I've tried some recent branch for the t60
+GNUtoo-irssi: it works well, beside the gtt init issue I just described
+damo22:GNUtoo-irssi: given that you were working on 3992 which is closed are you able to rebase your changes on top of 5320?
+damo22:hmm 3992 was merged
+damo22:phcoder-screen: my dimms are dual rank
+ GNUtoo-irssi: i am not too familiar with gerrit, but that error message seems to indicate that you should not try to push 3992 again because it is already merged... rebasing the remains of your changes on top of that (or origin/master) should fix that *i guess*
+
+URL to topic: http://review.coreboot.org/#/q/status:open+project:coreboot+branch:master+topic:NOTFORMERGE-reference-i915_gpu_init-x60,n,z
+(note: this is old code, not *directly* useful but might be useful later. put this somewhere else in howto.html later)
+
+GNUtoo-irssi: done, NOTFORMERGE-reference-i915_gpu_init-x60
+GNUtoo-irssi: yes, I've removed the Ids
+GNUtoo-irssi: so they were regenerated
+GNUtoo-irssi: the goal is not to rebase at all here
+GNUtoo-irssi: that's a reference code
+GNUtoo-irssi: it's not for merge either
+GNUtoo-irssi: If I start modifying it, I'll need to spend time testing it again
+GNUtoo-irssi: I've no time right now
+GNUtoo-irssi: maybe I'll have later in theses two weeks
+GNUtoo-irssi: but not right now
+damo22:GNUtoo-irssi: mainboard/lenovo/x60/i915* has been removed in favour of northbridge/intel/i945/gma.c in 5320
+damo22:i thought you had changes for that
+GNUtoo-irssi: yes, I know
+GNUtoo-irssi: what I just pushed is a *reference code* where the GTT setup works
+GNUtoo-irssi: it's old
+GNUtoo-irssi: it's not meant to be merged
+GNUtoo-irssi: it's not rebased
+GNUtoo-irssi: it's just frozen code where it's known to work
+GNUtoo-irssi: that's all
+
+damo22:ok
+GNUtoo-irssi: it doesn't even handle backlight
+GNUtoo-irssi: even with devmem2...
+damo22:i'll see if i can find the gtt stuff and compare to 5320
+damo22:could be a one liner
+damo22:physbase -> uma_memory_base+256*KiB
+phcoder-screen:damo22: yes and rank 1 config failed
+damo22:phcoder-screen: ok, so i'll get you that mchbar dump
+phcoder-screen:damo22: no need yet. I found out that in another ram config my X230 fails as well. I'll investigate this first
+
+kmalkki:GNUtoo-irssi: please abandon the duplicates in your gerrit space
+kmalkki:also any microcode files will not be removed until working copies are in 3rdparty/
+
+kmalkki:we probably want to keep the old version in gerrit, with all the comments made previously
+
+damo22:kmalkki: all those patches are noformerge
+damo22:not*
+kmalkki:damo22: still they are duplicates of already reviewed patches
+kmalkki:why the heck the new change-ids
+damo22:maybe a git diff to a pastebin would have been better
+
+GNUtoo-irssi: ls
+GNUtoo-irssi: oops
+ hunter2
+kmalkki:GNUtoo-irssi: please explain your motivation to push that stuff on gerrit
+kmalkki:it is not even rebased to current but 6 months old HEAD
+GNUtoo-irssi: GTT is setup badly on x60
+GNUtoo-irssi: with the recent changes from phcoder
+GNUtoo-irssi: what I pushed is a version that is known to have the GTT setup correctly
+GNUtoo-irssi: it's for reference
+GNUtoo-irssi: so people working on i945 native GPU init would use it to fix that issue faster
+GNUtoo-irssi: like diff both
+GNUtoo-irssi: or something like that
+GNUtoo-irssi: kmalkki: do you have a better description for the topic branch name that describe what I just said?
+kmalkki:well gerrit is not for the purpose of storing references
+kmalkki:most of those patches already had Change-IDs
+kmalkki:now we have duplicates.. and comments can end up in either place
+kmalkki:it was already a havoc with native init before
+GNUtoo-irssi: ok, so instead I should remove that branch, and push on gitorious?
+kmalkki:all of You working on it, try to work a setup that suits you all well
+GNUtoo-irssi: briefly: it's for tracking a regression
+
+kmalkki:well I do not do i915 gfx stuff.. but clearly you have a lot of problems trying to keep and follow each others work
+kmalkki:and what works and where the regressions have happened
+PaulePanter: GNUtoo-irssi: Hi. Do you know if the amount memory reserved for i945 IGD is always constant or if that is configurable?
+PaulePanter: GNUtoo-irssi: I did not see a table in the 3rd Gen datasheet.
+PaulePanter: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3rd-gen-core-family-mobile-vol-2-datasheet.pdf
+GNUtoo-irssi: PaulePanter: you mean the GSM?
+GNUtoo-irssi: (Graphics stolen memory)
+PaulePanter: GNUtoo-irssi: Yes.
+
+PaulePanter: Section 2.5.33 BDSM—Base Data of Stolen Memory Register
+GNUtoo-irssi: If I remmeber well it's configurable, but we use the values advised by the datasheet
+GNUtoo-irssi: which are derived from the ammount of RAM
+PaulePanter: This register contains the base address of graphics data stolen DRAM memory. BIOS determines the base of graphics data stolen memory by subtracting the graphics data stolen memory size (PCI Device 0 offset 52 bits 7:4) from TOLUD (PCI Device 0 offset BCh bits 31:20).
+PaulePanter: GNUtoo-irssi: Yes, I am unable to find the advised values.
+damo22:PaulePanter: are you sure thats the right datasheet for the cpu inside the X60?
+
+GNUtoo-irssi: ok
+GNUtoo-irssi: I can look
+PaulePanter: damo22: Not 100 %.
+damo22:afaik, BSDM is something kinky in the core iX processors
+GNUtoo-irssi: uma_size = 1024;
+PaulePanter: Chris Wilson from the Intel graphics Linux driver team said that BDSM ist incorrectly set up.
+PaulePanter: … on the i945.
+PaulePanter: … by coreboot.
+PaulePanter: This is Volume 2 of the Datasheet for the following products:
+PaulePanter: Mobile 3rd Generation Intel ® CoreTM processor family
+GNUtoo-irssi: in pci_domain_set_resources in northbridge.c
+PaulePanter: Mobile Intel ® Pentium ® processor family
+GNUtoo-irssi: ok
+PaulePanter: Mobile Intel ® Celeron ® processor family
+PaulePanter: GNUtoo-irssi: Thanks. So it is constant for now.
+PaulePanter: GNUtoo-irssi: So just 1 MB graphics memory?
+
+damo22:i dont remember him mentioning BDSM in the bug report, but he did say the GTT was incorrectly set up?
+damo22:graphics stolen stuff
+GNUtoo-irssi: no it's not
+GNUtoo-irssi: read the function
+PaulePanter: “Stolen memory has been set up incorrectly by coreboot.”
+PaulePanter: GNUtoo-irssi: Ok.
+PaulePanter: GNUtoo-irssi: No idea, if you are aware of https://bugs.freedesktop.org/show_bug.cgi?id=79038 .
+GNUtoo-irssi: http://paste.debian.net/101662/
+[    0.764084] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input3
+[    0.771023] pci 0000:00:00.0: Intel 945GM Chipset
+[    0.771075] pci 0000:00:00.0: detected gtt size: 262144K total, 262144K mappable
+[    0.771669] pci 0000:00:00.0: detected 8192K stolen memory
+[    0.771738] [drm] Memory usable by graphics device = 256M
+[    0.772124] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
+[    0.772126] [drm] Driver supports precise vblank timestamp query.
+[    0.772133] i915 0000:00:02.0: Invalid ROM contents
+[    0.772141] [drm] failed to find VBIOS tables
+[    0.772192] [drm] GPU crash dump saved to /sys/class/drm/card0/error
+[    0.772196] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.
+[    0.772198] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel
+[    0.772200] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue.
+[    0.772202] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it.
+[    0.772207] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
+[    0.772217] i915: render error detected, EIR: 0x00000010
+[    0.772224] i915: page table error
+[    0.772227] i915:   PGTBL_ER: 0x00000012
+[    0.772233] [drm:i915_report_and_clear_eir] *ERROR* EIR stuck: 0x00000010, masking
+[    0.772247] i915: render error detected, EIR: 0x00000010
+[    0.772252] i915: page table error
+[    0.772255] i915:   PGTBL_ER: 0x00000012
+[    0.924707] [drm] initialized overlay support
+[    1.126501] fbcon: inteldrmfb (fb0) is primary device
+[    1.360027] tsc: Refined TSC clocksource calibration: 1828.749 MHz
+[    1.482148] Console: switching to colour frame buffer device 175x65
+[    1.490507] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
+[    1.490510] i915 0000:00:02.0: registered panic notifier
+[    1.490522] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
+[    1.491931] console [netcon0] enabled
+[    1.491933] netconsole: network logging started
+[    1.494021] ACPI: bus type USB registered
+GNUtoo-irssi: that is the regression ^^^^
+GNUtoo-irssi: See PGTBL_ER
+GNUtoo-irssi: The bits are documented
+damo22:i have compared GNUtoo-irssi's patchset with the 5320 stuff that phcoder did, and i found that 1 line needs to be changed
+GNUtoo-irssi: (I don't remember where, probably in the datasheet that applies to the more recent GPUs (sic))
+
+damo22:its the base address of the gma init call
+
+PaulePanter: damo22: Are you going to push a patch for testing?
+
+damo22:but in order for it to work you need vgarom with native init, it doesnt run the rom just uses it for VBT
+PaulePanter: damo22: I still not see how that should fix the error, but we’ll see.
+damo22:how do i squash my commits into one patch that can be applied to 5320?
+PaulePanter: damo22: Is that patch really dependent on 5320? I thought it is also needed for the current native graphics init in the tree?
+
+PaulePanter: damo22: `git rebase -i
+PaulePanter: `
+PaulePanter: damo22: git rebase -i commit-hash-of-5320
+damo22:thanks
+PaulePanter: damo22: To squash you will need to change `pick` to `f` or `s` for `fixup` or `squash`.
+
+damo22:i have a patch that could be tested on X60: http://review.coreboot.org/#/c/5868/
+PaulePanter: damo22: On Nehalem:
+PaulePanter: src/northbridge/intel/nehalem/gma.c:            intel_gma_init(conf, gtt_res->base, physbase, pio_res->base,
+PaulePanter: src/northbridge/intel/nehalem/gma.c-                           lfb_res->base);
+damo22:PaulePanter: i fail to see relevance of nehalem in i945
+PaulePanter: damo22: Hopefully the code can be written in a way that common paths are written the same.
+PaulePanter: damo22: Let’s first see if the patch fixes it.
+
+PaulePanter: damo22: By the way, which datasheet do you think is correct for the Intel 945 IGD in the Lenovo T60 and X60?
+
+damo22:whichever datasheet includes 945PM (Calistoga) Graphics
+damo22:is it PM or GM?
+PaulePanter: damo22: I thought GM.
+damo22:PM has no integrated graphics so it must be GM
+PaulePanter: damo22: Document Number: 309219-006
+damo22:PaulePanter: this must be the datasheet: http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/mobile-945-express-chipset-datasheet.pdf
+
+PaulePanter: Mobile Intel® 945 Express Chipset Family
+PaulePanter: damo22: ;-)
+
+damo22:309219-006 is correct
+PaulePanter: Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From
+kmalkki:PaulePanter: did you go through the list of patches in your gerrit space that I suggested needed rebase?
+PaulePanter: the top of low used DRAM, (G)MCH claims 1 to 64 MBs of DRAM for internal graphics if
+PaulePanter: enabled.
+PaulePanter: kmalkki: I thought I did go through most of them.
+kmalkki:do you have the list
+kmalkki:I did not keep copy :/
+kmalkki:5388
+kmalkki:that is AMR
+PaulePanter: kmalkki: Don’t waste you time with it. I have a copy of your list somewhere and will go through it in the next days.
+kmalkki:PaulePanter: +1 5388
+damo22:PaulePanter: its an integrated GMA 950 afaik
+idwer: oh... 5388 has no priority whatsover to me
+idwer: not anymore ;)
+
+damo22:does GM45 support in coreboot have ddr2 AND ddr3 support?
+
+damo22:well that means X200 could be ported with ME disabled
+phcoder-screen:damo22: that's my next fun project after raminit for ivy.
+* thomasg_ is now known as thomasg
+
+damo22:vimuser: LTN150XG-L08 is my T60 EDID string (for his T60 15" -- this is already noted below in intelvbttool results)
+
+vimuser: damo22: ok, i should test 5868? I understand it puts the vgarom inside but without running it (just for getting VBT tables) but latre we could replace it with something like what the X230 "Deploy VBT" does
+damo22:yeah
+vimuser: Let me read backlog...
+damo22:vimuser: you dont need backlog, everything you need is in the 5868 commit
+vimuser: how did your X60t unbricking go, damo22?
+damo22:havent bothered finding my screwdrivers yet
+vimuser: I need to.... tidy myself up. Back in an hour or so.
+vimuser: damo22: upload a ROM for me, with 5868 and grub payload
+vimuser: I'll test it for you
+damo22:im not good with grub payloads
+damo22:i can give you one with seabios
+vimuser: ok give me that,
+vimuser: also hm ok, give me your .config. I'll add grub myself
+damo22:ok
+damo22:vimuser: http://paste.debian.net/plain/101692
+#
+# Automatically generated make config: don't edit
+# coreboot version: 4.0-5614-gdb77532
+# Mon May 26 00:11:44 2014
+#
+
+#
+# General setup
+#
+CONFIG_EXPERT=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_SCANBUILD_ENABLE is not set
+# CONFIG_CCACHE is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_EARLY_CBMEM_INIT=y
+# CONFIG_DYNAMIC_CBMEM is not set
+# CONFIG_COLLECT_TIMESTAMPS is not set
+# CONFIG_USE_BLOBS is not set
+# CONFIG_COVERAGE is not set
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_AAEON is not set
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_ADVANTECH is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_ARIMA is not set
+# CONFIG_VENDOR_ARTECGROUP is not set
+# CONFIG_VENDOR_ASI is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_AXUS is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BACHMANN is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIFFEROS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_CUBIETECH is not set
+# CONFIG_VENDOR_DIGITALLOGIC is not set
+# CONFIG_VENDOR_DMP is not set
+# CONFIG_VENDOR_EAGLELION is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GIZMOSPHERE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+CONFIG_VENDOR_LENOVO=y
+# CONFIG_VENDOR_LINUTOP is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NEWISYS is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_TECHNOLOGIC is not set
+# CONFIG_VENDOR_TELEVIDEO is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="lenovo/x60"
+CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60 / X60s"
+CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_MAINBOARD_VENDOR="Lenovo"
+CONFIG_MAX_CPUS=2
+CONFIG_RAMTOP=0x200000
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_RAMBASE=0x100000
+CONFIG_VGA_BIOS_ID="8086,27a2"
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_ONBOARD_VGA_IS_PRIMARY=y
+CONFIG_VGA_BIOS=y
+# CONFIG_CONSOLE_POST is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_DCACHE_RAM_BASE=0xffdf8000
+CONFIG_DCACHE_RAM_SIZE=0x8000
+CONFIG_SERIAL_CPU_INIT=y
+CONFIG_ACPI_SSDTX_NUM=0
+CONFIG_VGA_BIOS_FILE="vgabios.bin"
+# CONFIG_PCI_64BIT_PREF_MEM is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_ID_SECTION_OFFSET=0x80
+# CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set
+# CONFIG_BOARD_EMULATION_QEMU_X86_Q35 is not set
+# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set
+CONFIG_STACK_SIZE=0x1000
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_MMCONF_SUPPORT_DEFAULT=y
+# CONFIG_VGA is not set
+CONFIG_BOARD_LENOVO_X60=y
+# CONFIG_BOARD_LENOVO_X201 is not set
+# CONFIG_BOARD_LENOVO_X230 is not set
+# CONFIG_BOARD_LENOVO_T60 is not set
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO"
+CONFIG_SEABIOS_PS2_TIMEOUT=3000
+CONFIG_MAINBOARD_VERSION="1.0"
+CONFIG_CPU_ADDR_BITS=32
+CONFIG_CACHE_ROM_SIZE_OVERRIDE=0
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+CONFIG_LOGICAL_CPUS=y
+CONFIG_IOAPIC=y
+CONFIG_SMP=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+# CONFIG_USBDEBUG is not set
+CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_BOARD_ROMSIZE_KB_2048=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_2048=y
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=2048
+CONFIG_ROM_SIZE=0x200000
+CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X60 / X60s"
+CONFIG_ARCH_X86=y
+# CONFIG_ARCH_ARMV7 is not set
+
+#
+# Architecture (x86)
+#
+CONFIG_X86_ARCH_OPTIONS=y
+CONFIG_AP_IN_SIPI_WAIT=y
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_NUM_IPI_STARTS=2
+CONFIG_X86_BOOTBLOCK_SIMPLE=y
+# CONFIG_X86_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_ROMCC is not set
+CONFIG_PC80_SYSTEM=y
+CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c"
+CONFIG_HAVE_CMOS_DEFAULT=y
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c"
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+CONFIG_HPET_ADDRESS=0xfed00000
+CONFIG_HAVE_ARCH_MEMSET=y
+CONFIG_HAVE_ARCH_MEMCPY=y
+CONFIG_HAVE_ARCH_MEMMOVE=y
+# CONFIG_MAINBOARD_HAS_CHROMEOS is not set
+
+#
+# Chipset
+#
+
+#
+# CPU
+#
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+# CONFIG_CPU_AMD_AGESA is not set
+CONFIG_HAVE_INIT_TIMER=y
+CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0
+CONFIG_CPU_INTEL_MODEL_6EX=y
+CONFIG_CPU_INTEL_MODEL_6FX=y
+CONFIG_SMM_TSEG_SIZE=0
+CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y
+CONFIG_SSE2=y
+# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set
+# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set
+CONFIG_UDELAY_LAPIC=y
+CONFIG_LAPIC_MONOTONIC_TIMER=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+# CONFIG_TSC_SYNC_LFENCE is not set
+CONFIG_TSC_SYNC_MFENCE=y
+# CONFIG_SMM_TSEG is not set
+# CONFIG_SMM_MODULES is not set
+# CONFIG_X86_AMD_FIXED_MTRRS is not set
+# CONFIG_PARALLEL_MP is not set
+# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set
+CONFIG_CACHE_AS_RAM=y
+CONFIG_AP_SIPI_VECTOR=0xfffff000
+CONFIG_MMX=y
+CONFIG_SSE=y
+CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
+CONFIG_CPU_MICROCODE_ADDED_DURING_BUILD=y
+CONFIG_CPU_MICROCODE_CBFS_GENERATE=y
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
+
+#
+# Northbridge
+#
+CONFIG_VIDEO_MB=0
+# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
+# CONFIG_AMD_NB_CIMX is not set
+# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set
+CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y
+CONFIG_NORTHBRIDGE_INTEL_I945=y
+# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set
+CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y
+CONFIG_CHANNEL_XOR_RANDOMIZATION=y
+# CONFIG_OVERRIDE_CLOCK_DISABLE is not set
+# CONFIG_CHECK_SLFRCS_ON_RESUME is not set
+CONFIG_CBFS_SIZE=0x200000
+CONFIG_HPET_MIN_TICKS=0x80
+CONFIG_MAX_PIRQ_LINKS=4
+
+#
+# Southbridge
+#
+CONFIG_EHCI_BAR=0xfef00000
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+CONFIG_AMD_SB_SPI_TX_LEN=4
+# CONFIG_SPI_FLASH is not set
+CONFIG_SOUTHBRIDGE_INTEL_COMMON=y
+CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
+CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y
+
+#
+# Super I/O
+#
+CONFIG_SUPERIO_NSC_PC87382=y
+CONFIG_SUPERIO_NSC_PC87392=y
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_ACPI=y
+CONFIG_EC_LENOVO_H8=y
+CONFIG_H8_DOCK_EARLY_INIT=y
+CONFIG_EC_LENOVO_PMH7=y
+
+#
+# SoC
+#
+
+#
+# Devices
+#
+CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
+# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set
+CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
+# CONFIG_VGA_ROM_RUN is not set
+# CONFIG_ON_DEVICE_ROM_RUN is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+CONFIG_PCI=y
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_AGP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
+# CONFIG_PCIEXP_COMMON_CLOCK is not set
+# CONFIG_PCIEXP_ASPM is not set
+CONFIG_PCI_BUS_SEGN_BITS=0
+
+#
+# VGA BIOS
+#
+
+#
+# Display
+#
+
+#
+# PXE ROM
+#
+# CONFIG_PXE_ROM is not set
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_I2C_RTD2132 is not set
+CONFIG_DRIVERS_ICS_954309=y
+# CONFIG_INTEL_DP is not set
+# CONFIG_INTEL_DDI is not set
+CONFIG_INTEL_EDID=y
+# CONFIG_IPMI_KCS is not set
+# CONFIG_DRIVER_MAXIM_MAX77686 is not set
+# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
+# CONFIG_DRIVER_PARADE_PS8625 is not set
+# CONFIG_TPM is not set
+# CONFIG_RTL8168_ROM_DISABLE is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+# CONFIG_DRIVER_TI_TPS65090 is not set
+CONFIG_HAVE_UART_IO_MAPPED=y
+# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
+# CONFIG_HAVE_UART_SPECIAL is not set
+# CONFIG_DRIVER_XPOWERS_AXP209 is not set
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_EARLY_CONSOLE=y
+CONFIG_SQUELCH_EARLY_SMP=y
+CONFIG_CONSOLE_SERIAL=y
+CONFIG_CONSOLE_SERIAL8250=y
+CONFIG_CONSOLE_SERIAL_COM1=y
+# CONFIG_CONSOLE_SERIAL_COM2 is not set
+# CONFIG_CONSOLE_SERIAL_COM3 is not set
+# CONFIG_CONSOLE_SERIAL_COM4 is not set
+CONFIG_TTYS0_BASE=0x3f8
+CONFIG_CONSOLE_SERIAL_115200=y
+# CONFIG_CONSOLE_SERIAL_57600 is not set
+# CONFIG_CONSOLE_SERIAL_38400 is not set
+# CONFIG_CONSOLE_SERIAL_19200 is not set
+# CONFIG_CONSOLE_SERIAL_9600 is not set
+CONFIG_TTYS0_BAUD=115200
+CONFIG_TTYS0_LCS=3
+# CONFIG_SPKMODEM is not set
+CONFIG_HAVE_USBDEBUG=y
+# CONFIG_HAVE_USBDEBUG_OPTIONS is not set
+# CONFIG_CONSOLE_NE2K is not set
+# CONFIG_CONSOLE_CBMEM is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_NO_POST is not set
+# CONFIG_CMOS_POST is not set
+CONFIG_IO_POST=y
+CONFIG_IO_POST_PORT=0x80
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_HAVE_ACPI_SLIC is not set
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_MONOTONIC_TIMER=y
+# CONFIG_TIMER_QUEUE is not set
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+CONFIG_GFXUMA=y
+# CONFIG_RELOCATABLE_MODULES is not set
+# CONFIG_HAVE_REFCODE_BLOB is not set
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_HAVE_MP_TABLE=y
+CONFIG_HAVE_PIRQ_TABLE=y
+
+#
+# System tables
+#
+CONFIG_GENERATE_ACPI_TABLES=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# Payload
+#
+# CONFIG_PAYLOAD_NONE is not set
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_LINUX is not set
+CONFIG_PAYLOAD_SEABIOS=y
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_PAYLOAD_GRUB2 is not set
+# CONFIG_PAYLOAD_TIANOCORE is not set
+CONFIG_SEABIOS_STABLE=y
+# CONFIG_SEABIOS_MASTER is not set
+CONFIG_PAYLOAD_FILE="$(obj)/seabios/out/bios.bin.elf"
+CONFIG_COMPRESSED_PAYLOAD_LZMA=y
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_DEBUG_CBFS is not set
+CONFIG_HAVE_DEBUG_RAM_SETUP=y
+# CONFIG_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_DEBUG_PIRQ is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_TRACE is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+
+damo22:you need to still add the vgabios filename
+damo22:CONFIG_VGA_BIOS_FILE="vgabios.bin" is the current setting
+damo22:# CONFIG_CONSOLE_CBMEM is not set woops
+
+vimuser: damo22 »       register "gpu_lvds_is_dual_channel" = "1"
+vimuser: on x60/devicetree.cb
+damo22:vimuser: well check your VBT i think its correct though
+vimuser: so 0 was wrong?
+damo22:it might depend on panel
+
+vimuser: Oh
+vimuser: I get it now.
+vimuser: I didn't see any code in 5868 that executes anything from the vgarom but,
+vimuser: you set coreboot to load it into memory, but not execute it.
+vimuser: I thought "load" only meant put it in cbfs
+vimuser: is this a correct assessment?
+vimuser: To let kernel find vbt tables.
+vimuser: And then we "fake" it later (withotu vga rom loaded).
+vimuser: damo22: are you testing 5868 on your X60t?
+damo22:vimuser: its to make linux kernel detect lvds after native init, but if you can also test coreboot native framebuffer with grub too, that would be handy
+
+vimuser: So, vgarom has nothing to do with that patch.
+vimuser: ?
+vimuser: All I see is a change of stolen memory address, and the backlight values added
+damo22:vimuser: its tricky because the final vgabios in memory changes depending on the panel, because vgarom is self modifying
+
+vimuser: So should I include the vgarunning.bin instead of vgabios.bin ?
+damo22:yes
+
+damo22:vimuser: if you can load grub as payload and you see something, its a success
+vimuser: damo22: the problem is, without that patch I just use 5320 as-is, and I see grub as payload already.
+vimuser: Hence my question above.
+damo22:vimuser: also, if you can boot into linux after that and dont get any error messages from drm module, its a double success
+vimuser: Which error messages (besides "Invalid ROM contents") am I looking for?
+damo22:vimuser: stuff like, page fault
+vimuser: And should I enable any specific debugging options (such as drm.debug=0x06)
+damo22:yes that would help
+vimuser: Ok: which logs do you want?
+vimuser: I'll upload it for your reference
+damo22:vimuser: kernel boot log and Xorg.0.log, coreboot log if possible
+vimuser: probably kern.log and Xorg.0.log
+vimuser: coreboot log is possible, i have dock.
+vimuser: anything else?
+damo22:that is all, thanks
+vimuser: ok. will do.
+
+vimuser: damo22: I could test this on T60 aswell by cherry picking 5345, right?
+damo22:vimuser: idk
+vimuser: (and addinf backlight value to deivcetree)
+vimuser: We should devise a way to test this on T60 aswell.
+damo22:vimuser: lets just see if the x60 fix works
+
+damo22:it still needs work if the test passes
+vimuser: Ok but, you just have that one line changed in gma.c, and backlight value changed it x60/devicetree.cb
+damo22:yes
+damo22:phcoder did most of the work
+vimuser: So, I could run this same test on T60 by cherry picking 5345 on top of 5868, changing t60/devicetree.cb's backlight value and including T60 runningvga.bin and having that load (but not execute)
+damo22:its a small bug i think
+vimuser: I will do that above, after X60 is tested.
+damo22:vimuser: youre always talking about more and more combinations of tests, lets just get one right
+vimuser: Yes. Just a thought. We'll test X60 exclusively. T60 can easily be tested later.
+vimuser: Ok..... back soon. I'll get you the results you wanted. I'll be using 3.14.4 (the one samnob made).
+damo22:thanks
+
+vimuser: We should do this with the latest runningvga.bin (from extracting with dd on the latest vgabios.bin)
+vimuser: My one is older
+damo22:vimuser: version number of vgabios is irrelevant if it was taken from a lenovo bios that used to run on your machine, and since pulled from ram
+damo22:ie, it should have the correct VBT values
+damo22:for your machine
+
+
+
+
+

+ diff --git a/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/biosdecode.log b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/biosdecode.log new file mode 100644 index 00000000..70617532 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/biosdecode.log @@ -0,0 +1,24 @@ +# biosdecode 2.12 +VPD present. + BIOS Build ID: 7UET56WW + Box Serial Number: L3BLN3R + Motherboard Serial Number: VF26F91C27K + Machine Type/Model: 6475GE2 +SMBIOS 2.4 present. + Structure Table Length: 2469 bytes + Structure Table Address: 0x000E0010 + Number Of Structures: 74 + Maximum Structure Size: 120 bytes +BIOS32 Service Directory present. + Revision: 0 + Calling Interface Address: 0x000FDC80 +ACPI 2.0 present. + OEM Identifier: LENOVO + RSD Table 32-bit Address: 0xBCB6A54A + XSD Table 64-bit Address: 0x00000000BCB6A5B6 +PNP BIOS 1.0 present. + Event Notification: Not Supported + Real Mode 16-bit Code Address: E19B:1934 + Real Mode 16-bit Data Address: 0040:0000 + 16-bit Protected Mode Code Address: 0x000F8AD1 + 16-bit Protected Mode Data Address: 0x00000400 diff --git a/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/codec#0 b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/codec#0 new file mode 100644 index 00000000..66ad8121 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/codec#0 @@ -0,0 +1,208 @@ +Codec: Conexant CX20561 (Hermosa) +Address: 0 +AFG Function Id: 0x1 (unsol 1) +MFG Function Id: 0x2 (unsol 1) +Vendor Id: 0x14f15051 +Subsystem Id: 0x17aa211c +Revision Id: 0x100000 +Modem Function Group: 0x2 +Default PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM +Default Amp-In caps: N/A +Default Amp-Out caps: N/A +State of AFG node 0x01: + Power states: D0 D1 D2 D3 CLKSTOP + Power: setting=D0, actual=D0 +GPIO: io=4, o=0, i=0, unsolicited=1, wake=0 + IO[0]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[1]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[2]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[3]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 +Node 0x10 [Audio Output] wcaps 0xc1d: Stereo Amp-Out R/L + Control: name="Speaker Playback Volume", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Control: name="Speaker Playback Switch", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Device: name="CX20561 Analog", type="Audio", device=0 + Amp-Out caps: ofs=0x4a, nsteps=0x4a, stepsize=0x03, mute=0 + Amp-Out vals: [0x00 0x00] + Converter: stream=8, channel=0 + PCM: + rates [0x560]: 44100 48000 96000 192000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x11 [Audio Output] wcaps 0xc1d: Stereo Amp-Out R/L + Control: name="Headphone Playback Volume", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Control: name="Headphone Playback Switch", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Amp-Out caps: ofs=0x4a, nsteps=0x4a, stepsize=0x03, mute=0 + Amp-Out vals: [0x00 0x00] + Converter: stream=8, channel=0 + PCM: + rates [0x560]: 44100 48000 96000 192000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x12 [Audio Output] wcaps 0x211: Stereo Digital + Control: name="IEC958 Playback Con Mask", index=0, device=0 + Control: name="IEC958 Playback Pro Mask", index=0, device=0 + Control: name="IEC958 Playback Default", index=0, device=0 + Control: name="IEC958 Playback Switch", index=0, device=0 + Control: name="IEC958 Default PCM Playback Switch", index=0, device=0 + Device: name="CX20561 Digital", type="SPDIF", device=1 + Converter: stream=8, channel=0 + Digital: + Digital category: 0x0 + IEC Coding Type: 0x0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x5]: PCM AC3 +Node 0x13 [Beep Generator Widget] wcaps 0x70000c: Mono Amp-Out + Control: name="Beep Playback Volume", index=0, device=0 + ControlAmp: chs=1, dir=Out, idx=0, ofs=0 + Control: name="Beep Playback Switch", index=0, device=0 + ControlAmp: chs=1, dir=Out, idx=0, ofs=0 + Amp-Out caps: ofs=0x03, nsteps=0x03, stepsize=0x17, mute=0 + Amp-Out vals: [0x00] +Node 0x14 [Audio Input] wcaps 0x100d1b: Stereo Amp-In R/L + Device: name="CX20561 Analog", type="Audio", device=0 + Amp-In caps: ofs=0x4a, nsteps=0x50, stepsize=0x03, mute=0 + Amp-In vals: [0x50 0x50] [0x50 0x50] + Converter: stream=4, channel=0 + SDI-Select: 0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x1d* 0x17 +Node 0x15 [Audio Input] wcaps 0x100d1b: Stereo Amp-In R/L + Control: name="Capture Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=1, ofs=0 + Amp-In caps: ofs=0x4a, nsteps=0x50, stepsize=0x03, mute=0 + Amp-In vals: [0x50 0x50] + Converter: stream=0, channel=0 + SDI-Select: 0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 1 + 0x18 +Node 0x16 [Pin Complex] wcaps 0x400581: Stereo + Control: name="Headphone Jack", index=0, device=0 + Pincap 0x0000001c: OUT HP Detect + Pin Default 0x022140f0: [Jack] HP Out at Ext Front + Conn = 1/8, Color = Green + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0xc0: OUT HP + Unsolicited: tag=02, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10 0x11* +Node 0x17 [Pin Complex] wcaps 0x40048b: Stereo Amp-In + Control: name="Dock Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Dock Mic Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x27, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00001224: IN Detect + Vref caps: 50 80 + Pin Default 0x61a190f0: [N/A] Mic at Sep Rear + Conn = 1/8, Color = Pink + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x24: IN VREF_80 + Unsolicited: tag=03, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x18 [Pin Complex] wcaps 0x40048b: Stereo Amp-In + Control: name="Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Mic Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x27, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00001224: IN Detect + Vref caps: 50 80 + Pin Default 0x02a190f0: [Jack] Mic at Ext Front + Conn = 1/8, Color = Pink + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x24: IN VREF_80 + Unsolicited: tag=04, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x19 [Pin Complex] wcaps 0x400581: Stereo + Control: name="Dock Headphone Jack", index=0, device=0 + Pincap 0x00000014: OUT Detect + Pin Default 0x40f000f0: [N/A] Other at Ext N/A + Conn = Unknown, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x40: OUT + Unsolicited: tag=01, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10 0x11* +Node 0x1a [Pin Complex] wcaps 0x400501: Stereo + Control: name="Speaker Phantom Jack", index=0, device=0 + Pincap 0x00010010: OUT EAPD + EAPD 0x2: EAPD + Pin Default 0x901701f0: [Fixed] Speaker at Int N/A + Conn = Analog, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10* 0x11 +Node 0x1b [Pin Complex] wcaps 0x400500: Mono + Pincap 0x00010010: OUT EAPD + EAPD 0x2: EAPD + Pin Default 0x40f001f0: [N/A] Other at Ext N/A + Conn = Unknown, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10* 0x11 +Node 0x1c [Pin Complex] wcaps 0x400701: Stereo Digital + Control: name="SPDIF Phantom Jack", index=0, device=0 + Pincap 0x00000010: OUT + Pin Default 0x40f001f0: [N/A] Other at Ext N/A + Conn = Unknown, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 1 + 0x12 +Node 0x1d [Pin Complex] wcaps 0x40040b: Stereo Amp-In + Control: name="Internal Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Internal Mic Phantom Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x2f, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00000020: IN + Pin Default 0x90a601f0: [Fixed] Mic at Int N/A + Conn = Digital, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x20: IN + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x1e [Vendor Defined Widget] wcaps 0xf00000: Mono diff --git a/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/cpuinfo.log b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/cpuinfo.log new file mode 100644 index 00000000..36ee864f --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/cpuinfo.log @@ -0,0 +1,52 @@ +processor : 0 +vendor_id : GenuineIntel +cpu family : 6 +model : 23 +model name : Intel(R) Core(TM)2 Duo CPU P8400 @ 2.26GHz +stepping : 6 +microcode : 0x60c +cpu MHz : 1600.000 +cache size : 3072 KB +physical id : 0 +siblings : 2 +core id : 0 +cpu cores : 2 +apicid : 0 +initial apicid : 0 +fpu : yes +fpu_exception : yes +cpuid level : 10 +wp : yes +flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts nopl aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 lahf_lm dtherm tpr_shadow vnmi flexpriority +bogomips : 4521.76 +clflush size : 64 +cache_alignment : 64 +address sizes : 36 bits physical, 48 bits virtual +power management: + +processor : 1 +vendor_id : GenuineIntel +cpu family : 6 +model : 23 +model name : Intel(R) Core(TM)2 Duo CPU P8400 @ 2.26GHz +stepping : 6 +microcode : 0x60c +cpu MHz : 1600.000 +cache size : 3072 KB +physical id : 0 +siblings : 2 +core id : 1 +cpu cores : 2 +apicid : 1 +initial apicid : 1 +fpu : yes +fpu_exception : yes +cpuid level : 10 +wp : yes +flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts nopl aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 lahf_lm dtherm tpr_shadow vnmi flexpriority +bogomips : 4521.76 +clflush size : 64 +cache_alignment : 64 +address sizes : 36 bits physical, 48 bits virtual +power management: + diff --git a/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmesg.log b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmesg.log new file mode 100644 index 00000000..e3f54c49 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmesg.log @@ -0,0 +1,1042 @@ +[ 0.000000] Initializing cgroup subsys cpuset +[ 0.000000] Initializing cgroup subsys cpu +[ 0.000000] Initializing cgroup subsys cpuacct +[ 0.000000] Linux version 3.13.0-39-lowlatency (root@devel.trisquel.info) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #66+7.0trisquel2 SMP PREEMPT Wed Oct 29 17:10:10 UTC 2014 (Ubuntu 3.13.0-39.66+7.0trisquel2-lowlatency 3.13.11.8-gnu) +[ 0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-3.13.0-39-lowlatency root=UUID=35246665-9714-42dc-8ff4-580d4cf85131 ro nomdmonddf nomdmonisw nomdmonddf nomdmonisw +[ 0.000000] KERNEL supported cpus: +[ 0.000000] Intel GenuineIntel +[ 0.000000] AMD AuthenticAMD +[ 0.000000] Centaur CentaurHauls +[ 0.000000] Disabled fast string operations +[ 0.000000] e820: BIOS-provided physical RAM map: +[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009ebff] usable +[ 0.000000] BIOS-e820: [mem 0x000000000009ec00-0x000000000009ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved +[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000bc6a0fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000bc6a1000-0x00000000bc6a6fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bc6a7000-0x00000000bc7b6fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000bc7b7000-0x00000000bc80efff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bc80f000-0x00000000bc8c6fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000bc8c7000-0x00000000bc8d1fff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000bc8d2000-0x00000000bc8d4fff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x00000000bc8d5000-0x00000000bc8d8fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bc8d9000-0x00000000bc8dcfff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000bc8dd000-0x00000000bc8dffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bc8e0000-0x00000000bc906fff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000bc907000-0x00000000bc907fff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x00000000bc908000-0x00000000bcb0efff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bcb0f000-0x00000000bcb9efff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000bcb9f000-0x00000000bcbfefff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x00000000bcbff000-0x00000000bcbfffff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000bcc00000-0x00000000beffffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec0ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed003ff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed10000-0x00000000fed13fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed18000-0x00000000fed19fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed8ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000ff800000-0x00000000ffffffff] reserved +[ 0.000000] NX (Execute Disable) protection: active +[ 0.000000] SMBIOS 2.4 present. +[ 0.000000] DMI: LENOVO 6475GE2/6475GE2, BIOS 7UET56WW (2.02 ) 01/09/2009 +[ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved +[ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable +[ 0.000000] No AGP bridge found +[ 0.000000] e820: last_pfn = 0xbcc00 max_arch_pfn = 0x400000000 +[ 0.000000] MTRR default type: uncachable +[ 0.000000] MTRR fixed ranges enabled: +[ 0.000000] 00000-9FFFF write-back +[ 0.000000] A0000-BFFFF uncachable +[ 0.000000] C0000-D3FFF write-protect +[ 0.000000] D4000-DBFFF uncachable +[ 0.000000] DC000-FFFFF write-protect +[ 0.000000] MTRR variable ranges enabled: +[ 0.000000] 0 base 0BD000000 mask FFF000000 uncachable +[ 0.000000] 1 base 0BE000000 mask FFE000000 uncachable +[ 0.000000] 2 base 000000000 mask F80000000 write-back +[ 0.000000] 3 base 080000000 mask FC0000000 write-back +[ 0.000000] 4 base 0BCE00000 mask FFFE00000 uncachable +[ 0.000000] 5 disabled +[ 0.000000] 6 disabled +[ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 +[ 0.000000] original variable MTRRs +[ 0.000000] reg 0, base: 3024MB, range: 16MB, type UC +[ 0.000000] reg 1, base: 3040MB, range: 32MB, type UC +[ 0.000000] reg 2, base: 0GB, range: 2GB, type WB +[ 0.000000] reg 3, base: 2GB, range: 1GB, type WB +[ 0.000000] reg 4, base: 3022MB, range: 2MB, type UC +[ 0.000000] total RAM covered: 3022M +[ 0.000000] Found optimal setting for mtrr clean up +[ 0.000000] gran_size: 64K chunk_size: 64M num_reg: 5 lose cover RAM: 0G +[ 0.000000] New variable MTRRs +[ 0.000000] reg 0, base: 0GB, range: 2GB, type WB +[ 0.000000] reg 1, base: 2GB, range: 1GB, type WB +[ 0.000000] reg 2, base: 3022MB, range: 2MB, type UC +[ 0.000000] reg 3, base: 3024MB, range: 16MB, type UC +[ 0.000000] reg 4, base: 3040MB, range: 32MB, type UC +[ 0.000000] found SMP MP-table at [mem 0x000f6570-0x000f657f] mapped at [ffff8800000f6570] +[ 0.000000] Scanning 1 areas for low memory corruption +[ 0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576 +[ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff] +[ 0.000000] [mem 0x00000000-0x000fffff] page 4k +[ 0.000000] BRK [0x01fd9000, 0x01fd9fff] PGTABLE +[ 0.000000] BRK [0x01fda000, 0x01fdafff] PGTABLE +[ 0.000000] BRK [0x01fdb000, 0x01fdbfff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0xbc400000-0xbc5fffff] +[ 0.000000] [mem 0xbc400000-0xbc5fffff] page 2M +[ 0.000000] BRK [0x01fdc000, 0x01fdcfff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0xbc000000-0xbc3fffff] +[ 0.000000] [mem 0xbc000000-0xbc3fffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0x80000000-0xbbffffff] +[ 0.000000] [mem 0x80000000-0xbbffffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0x00100000-0x7fffffff] +[ 0.000000] [mem 0x00100000-0x001fffff] page 4k +[ 0.000000] [mem 0x00200000-0x7fffffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0xbc600000-0xbc6a0fff] +[ 0.000000] [mem 0xbc600000-0xbc6a0fff] page 4k +[ 0.000000] BRK [0x01fdd000, 0x01fddfff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0xbc6a7000-0xbc7b6fff] +[ 0.000000] [mem 0xbc6a7000-0xbc7b6fff] page 4k +[ 0.000000] init_memory_mapping: [mem 0xbc80f000-0xbc8c6fff] +[ 0.000000] [mem 0xbc80f000-0xbc8c6fff] page 4k +[ 0.000000] BRK [0x01fde000, 0x01fdefff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0xbcbff000-0xbcbfffff] +[ 0.000000] [mem 0xbcbff000-0xbcbfffff] page 4k +[ 0.000000] RAMDISK: [mem 0x3530e000-0x3697efff] +[ 0.000000] ACPI: RSDP 00000000000f6530 000024 (v02 LENOVO) +[ 0.000000] ACPI: XSDT 00000000bcb6a5b6 000094 (v01 LENOVO TP-7U 00002020 LTP 00000000) +[ 0.000000] ACPI: FACP 00000000bcb6a700 0000F4 (v03 LENOVO TP-7U 00002020 LNVO 00000001) +[ 0.000000] ACPI: DSDT 00000000bcb6aadb 00F0B8 (v01 LENOVO TP-7U 00002020 MSFT 03000000) +[ 0.000000] ACPI: FACS 00000000bcb8e000 000040 +[ 0.000000] ACPI: SSDT 00000000bcb6a8b4 000227 (v01 LENOVO TP-7U 00002020 MSFT 03000000) +[ 0.000000] ACPI: ECDT 00000000bcb79b93 000052 (v01 LENOVO TP-7U 00002020 LNVO 00000001) +[ 0.000000] ACPI: APIC 00000000bcb79be5 000078 (v01 LENOVO TP-7U 00002020 LNVO 00000001) +[ 0.000000] ACPI: MCFG 00000000bcb79c5d 00003C (v01 LENOVO TP-7U 00002020 LNVO 00000001) +[ 0.000000] ACPI: HPET 00000000bcb79c99 000038 (v01 LENOVO TP-7U 00002020 LNVO 00000001) +[ 0.000000] ACPI: SLIC 00000000bcb79dc2 000176 (v01 LENOVO TP-7U 00002020 LTP 00000000) +[ 0.000000] ACPI: BOOT 00000000bcb79f38 000028 (v01 LENOVO TP-7U 00002020 LTP 00000001) +[ 0.000000] ACPI: ASF! 00000000bcb79f60 0000A0 (v16 LENOVO TP-7U 00002020 PTL 00000001) +[ 0.000000] ACPI: SSDT 00000000bcb8d213 00054F (v01 LENOVO TP-7U 00002020 INTL 20050513) +[ 0.000000] ACPI: TCPA 00000000bc907000 000032 (v00 00000000 00000000) +[ 0.000000] ACPI: SSDT 00000000bc8d4000 000655 (v01 PmRef CpuPm 00003000 INTL 20050624) +[ 0.000000] ACPI: SSDT 00000000bc8d3000 000274 (v01 PmRef Cpu0Tst 00003000 INTL 20050624) +[ 0.000000] ACPI: SSDT 00000000bc8d2000 000242 (v01 PmRef ApTst 00003000 INTL 20050624) +[ 0.000000] ACPI: DMI detected: Lenovo ThinkPad T400 +[ 0.000000] ACPI: Local APIC address 0xfee00000 +[ 0.000000] No NUMA configuration found +[ 0.000000] Faking a node at [mem 0x0000000000000000-0x00000000bcbfffff] +[ 0.000000] Initmem setup node 0 [mem 0x00000000-0xbcbfffff] +[ 0.000000] NODE_DATA [mem 0xbc8c1000-0xbc8c5fff] +[ 0.000000] [ffffea0000000000-ffffea0002ffffff] PMD -> [ffff8800b8c00000-ffff8800bbbfffff] on node 0 +[ 0.000000] Zone ranges: +[ 0.000000] DMA [mem 0x00001000-0x00ffffff] +[ 0.000000] DMA32 [mem 0x01000000-0xffffffff] +[ 0.000000] Normal empty +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x00001000-0x0009dfff] +[ 0.000000] node 0: [mem 0x00100000-0xbc6a0fff] +[ 0.000000] node 0: [mem 0xbc6a7000-0xbc7b6fff] +[ 0.000000] node 0: [mem 0xbc80f000-0xbc8c6fff] +[ 0.000000] node 0: [mem 0xbcbff000-0xbcbfffff] +[ 0.000000] On node 0 totalpages: 772103 +[ 0.000000] DMA zone: 64 pages used for memmap +[ 0.000000] DMA zone: 21 pages reserved +[ 0.000000] DMA zone: 3997 pages, LIFO batch:0 +[ 0.000000] DMA32 zone: 12016 pages used for memmap +[ 0.000000] DMA32 zone: 768106 pages, LIFO batch:31 +[ 0.000000] ACPI: PM-Timer IO Port: 0x1008 +[ 0.000000] ACPI: Local APIC address 0xfee00000 +[ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] disabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x03] disabled) +[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1]) +[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) +[ 0.000000] ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0]) +[ 0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-23 +[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) +[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) +[ 0.000000] ACPI: IRQ0 used by override. +[ 0.000000] ACPI: IRQ2 used by override. +[ 0.000000] ACPI: IRQ9 used by override. +[ 0.000000] Using ACPI (MADT) for SMP configuration information +[ 0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000 +[ 0.000000] smpboot: Allowing 4 CPUs, 2 hotplug CPUs +[ 0.000000] nr_irqs_gsi: 40 +[ 0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x0009efff] +[ 0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff] +[ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000dbfff] +[ 0.000000] PM: Registered nosave memory: [mem 0x000dc000-0x000fffff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc6a1000-0xbc6a6fff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc7b7000-0xbc80efff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc8c7000-0xbc8d1fff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc8d2000-0xbc8d4fff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc8d5000-0xbc8d8fff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc8d9000-0xbc8dcfff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc8dd000-0xbc8dffff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc8e0000-0xbc906fff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc907000-0xbc907fff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbc908000-0xbcb0efff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbcb0f000-0xbcb9efff] +[ 0.000000] PM: Registered nosave memory: [mem 0xbcb9f000-0xbcbfefff] +[ 0.000000] e820: [mem 0xbf000000-0xdfffffff] available for PCI devices +[ 0.000000] Booting paravirtualized kernel on bare hardware +[ 0.000000] setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:4 nr_node_ids:1 +[ 0.000000] PERCPU: Embedded 29 pages/cpu @ffff8800bc200000 s86848 r8192 d23744 u524288 +[ 0.000000] pcpu-alloc: s86848 r8192 d23744 u524288 alloc=1*2097152 +[ 0.000000] pcpu-alloc: [0] 0 1 2 3 +[ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 760002 +[ 0.000000] Policy zone: DMA32 +[ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-3.13.0-39-lowlatency root=UUID=35246665-9714-42dc-8ff4-580d4cf85131 ro nomdmonddf nomdmonisw nomdmonddf nomdmonisw +[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) +[ 0.000000] Checking aperture... +[ 0.000000] No AGP bridge found +[ 0.000000] Calgary: detecting Calgary via BIOS EBDA area +[ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing! +[ 0.000000] Memory: 2999200K/3088412K available (7418K kernel code, 1135K rwdata, 3420K rodata, 1324K init, 1444K bss, 89212K reserved) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 +[ 0.000000] Preemptible hierarchical RCU implementation. +[ 0.000000] RCU dyntick-idle grace-period acceleration is enabled. +[ 0.000000] Dump stacks of tasks blocking RCU-preempt GP. +[ 0.000000] RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=4. +[ 0.000000] Offload RCU callbacks from all CPUs +[ 0.000000] Offload RCU callbacks from CPUs: 0-3. +[ 0.000000] NR_IRQS:16640 nr_irqs:712 16 +[ 0.000000] Console: colour VGA+ 80x25 +[ 0.000000] console [tty0] enabled +[ 0.000000] allocated 12582912 bytes of page_cgroup +[ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups +[ 0.000000] hpet clockevent registered +[ 0.000000] tsc: Fast TSC calibration using PIT +[ 0.000000] tsc: Detected 2260.884 MHz processor +[ 0.001004] Calibrating delay loop (skipped), value calculated using timer frequency.. 4521.76 BogoMIPS (lpj=2260884) +[ 0.001101] pid_max: default: 32768 minimum: 301 +[ 0.001183] Security Framework initialized +[ 0.002014] AppArmor: AppArmor initialized +[ 0.002061] Yama: becoming mindful. +[ 0.002519] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes) +[ 0.005045] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes) +[ 0.006304] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes) +[ 0.006363] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes) +[ 0.006750] Initializing cgroup subsys memory +[ 0.006805] Initializing cgroup subsys devices +[ 0.006852] Initializing cgroup subsys freezer +[ 0.006900] Initializing cgroup subsys blkio +[ 0.006946] Initializing cgroup subsys bfqio +[ 0.007006] Initializing cgroup subsys perf_event +[ 0.007056] Initializing cgroup subsys hugetlb +[ 0.007125] Disabled fast string operations +[ 0.007177] CPU: Physical Processor ID: 0 +[ 0.007222] CPU: Processor Core ID: 0 +[ 0.007269] mce: CPU supports 6 MCE banks +[ 0.007321] CPU0: Thermal monitoring enabled (TM2) +[ 0.007375] Last level iTLB entries: 4KB 128, 2MB 4, 4MB 4 +[ 0.007375] Last level dTLB entries: 4KB 256, 2MB 0, 4MB 32 +[ 0.007375] tlb_flushall_shift: -1 +[ 0.007532] Freeing SMP alternatives memory: 24K (ffffffff81e68000 - ffffffff81e6e000) +[ 0.009050] ACPI: Core revision 20131115 +[ 0.016028] ACPI: All ACPI Tables successfully acquired +[ 0.017012] ftrace: allocating 28647 entries in 112 pages +[ 0.026529] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 +[ 0.036750] smpboot: CPU0: Intel(R) Core(TM)2 Duo CPU P8400 @ 2.26GHz (fam: 06, model: 17, stepping: 06) +[ 0.037000] Performance Events: PEBS fmt0+, 4-deep LBR, Core2 events, Intel PMU driver. +[ 0.037000] ... version: 2 +[ 0.037000] ... bit width: 40 +[ 0.037000] ... generic registers: 2 +[ 0.037000] ... value mask: 000000ffffffffff +[ 0.037000] ... max period: 000000007fffffff +[ 0.037000] ... fixed-purpose events: 3 +[ 0.037000] ... event mask: 0000000700000003 +[ 0.045070] x86: Booting SMP configuration: +[ 0.043030] Disabled fast string operations +[ 0.057121] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter. +[ 0.045118] .... node #0, CPUs: #1 +[ 0.057282] x86: Booted up 1 node, 2 CPUs +[ 0.057369] smpboot: Total of 2 processors activated (9043.53 BogoMIPS) +[ 0.058135] devtmpfs: initialized +[ 0.066825] EVM: security.selinux +[ 0.066871] EVM: security.SMACK64 +[ 0.066916] EVM: security.ima +[ 0.066960] EVM: security.capability +[ 0.067031] PM: Registering ACPI NVS region [mem 0xbc8c7000-0xbc8d1fff] (45056 bytes) +[ 0.067093] PM: Registering ACPI NVS region [mem 0xbc8d9000-0xbc8dcfff] (16384 bytes) +[ 0.067154] PM: Registering ACPI NVS region [mem 0xbc8e0000-0xbc906fff] (159744 bytes) +[ 0.067216] PM: Registering ACPI NVS region [mem 0xbcb0f000-0xbcb9efff] (589824 bytes) +[ 0.068312] pinctrl core: initialized pinctrl subsystem +[ 0.068442] regulator-dummy: no parameters +[ 0.068524] RTC time: 18:49:50, date: 03/17/15 +[ 0.068613] NET: Registered protocol family 16 +[ 0.068793] cpuidle: using governor ladder +[ 0.068840] cpuidle: using governor menu +[ 0.068936] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it +[ 0.068997] ACPI: bus type PCI registered +[ 0.069006] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 +[ 0.069120] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) +[ 0.069184] PCI: MMCONFIG at [mem 0xe0000000-0xe3ffffff] reserved in E820 +[ 0.077236] PCI: Using configuration type 1 for base access +[ 0.078230] bio: create slab at 0 +[ 0.078230] ACPI: Added _OSI(Module Device) +[ 0.078230] ACPI: Added _OSI(Processor Device) +[ 0.078230] ACPI: Added _OSI(3.0 _SCP Extensions) +[ 0.078230] ACPI: Added _OSI(Processor Aggregator Device) +[ 0.078275] ACPI: Added _OSI(Linux) +[ 0.080439] ACPI : EC: EC description table is found, configuring boot EC +[ 0.085553] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query honored via DMI +[ 0.094201] ACPI: SSDT 00000000bc8d7c20 0002C8 (v01 PmRef Cpu0Ist 00003000 INTL 20050624) +[ 0.094729] ACPI: Dynamic OEM Table Load: +[ 0.094837] ACPI: SSDT (null) 0002C8 (v01 PmRef Cpu0Ist 00003000 INTL 20050624) +[ 0.095093] ACPI: SSDT 00000000bc8d5020 00087A (v01 PmRef Cpu0Cst 00003001 INTL 20050624) +[ 0.095644] ACPI: Dynamic OEM Table Load: +[ 0.095752] ACPI: SSDT (null) 00087A (v01 PmRef Cpu0Cst 00003001 INTL 20050624) +[ 0.099211] ACPI: SSDT 00000000bc8d6ca0 0001CF (v01 PmRef ApIst 00003000 INTL 20050624) +[ 0.100105] ACPI: Dynamic OEM Table Load: +[ 0.100213] ACPI: SSDT (null) 0001CF (v01 PmRef ApIst 00003000 INTL 20050624) +[ 0.102068] ACPI: SSDT 00000000bc8d6f20 00008D (v01 PmRef ApCst 00003000 INTL 20050624) +[ 0.102595] ACPI: Dynamic OEM Table Load: +[ 0.103046] ACPI: SSDT (null) 00008D (v01 PmRef ApCst 00003000 INTL 20050624) +[ 0.105134] ACPI: Interpreter enabled +[ 0.105185] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20131115/hwxface-580) +[ 0.105311] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20131115/hwxface-580) +[ 0.105447] ACPI: (supports S0 S3 S4 S5) +[ 0.105493] ACPI: Using IOAPIC for interrupt routing +[ 0.105564] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug +[ 0.106533] ACPI: ACPI Dock Station Driver: 3 docks/bays found +[ 0.116113] ACPI: Power Resource [PUBS] (on) +[ 0.121139] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.121590] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.122046] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.122494] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.122941] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.123386] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.123832] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.124293] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.124700] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) +[ 0.124754] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] +[ 0.125219] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] +[ 0.125311] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge +[ 0.125558] PCI host bridge to bus 0000:00 +[ 0.125606] pci_bus 0000:00: root bus resource [bus 00-ff] +[ 0.125655] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7] +[ 0.125705] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff] +[ 0.125754] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] +[ 0.125804] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff] +[ 0.125855] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff] +[ 0.125905] pci_bus 0000:00: root bus resource [mem 0xbf000000-0xfebfffff] +[ 0.125962] pci 0000:00:00.0: [8086:2a40] type 00 class 0x060000 +[ 0.125982] DMAR: Forcing write-buffer flush capability +[ 0.126005] DMAR: Disabling IOMMU for graphics on this chipset +[ 0.126128] pci 0000:00:02.0: [8086:2a42] type 00 class 0x030000 +[ 0.126141] pci 0000:00:02.0: reg 0x10: [mem 0xf4400000-0xf47fffff 64bit] +[ 0.126148] pci 0000:00:02.0: reg 0x18: [mem 0xd0000000-0xdfffffff 64bit pref] +[ 0.126154] pci 0000:00:02.0: reg 0x20: [io 0x1800-0x1807] +[ 0.126239] pci 0000:00:02.1: [8086:2a43] type 00 class 0x038000 +[ 0.126250] pci 0000:00:02.1: reg 0x10: [mem 0xf4200000-0xf42fffff 64bit] +[ 0.126347] pci 0000:00:03.0: [8086:2a44] type 00 class 0x078000 +[ 0.126363] pci 0000:00:03.0: reg 0x10: [mem 0xfc226800-0xfc22680f 64bit] +[ 0.126414] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold +[ 0.126483] pci 0000:00:03.2: [8086:2a46] type 00 class 0x010185 +[ 0.126497] pci 0000:00:03.2: reg 0x10: [io 0x1828-0x182f] +[ 0.126504] pci 0000:00:03.2: reg 0x14: [io 0x180c-0x180f] +[ 0.126511] pci 0000:00:03.2: reg 0x18: [io 0x1820-0x1827] +[ 0.126518] pci 0000:00:03.2: reg 0x1c: [io 0x1808-0x180b] +[ 0.126524] pci 0000:00:03.2: reg 0x20: [io 0x1810-0x181f] +[ 0.126622] pci 0000:00:03.3: [8086:2a47] type 00 class 0x070002 +[ 0.126636] pci 0000:00:03.3: reg 0x10: [io 0x1830-0x1837] +[ 0.126643] pci 0000:00:03.3: reg 0x14: [mem 0xfc024000-0xfc024fff] +[ 0.126800] pci 0000:00:19.0: [8086:10f5] type 00 class 0x020000 +[ 0.126825] pci 0000:00:19.0: reg 0x10: [mem 0xfc000000-0xfc01ffff] +[ 0.126837] pci 0000:00:19.0: reg 0x14: [mem 0xfc025000-0xfc025fff] +[ 0.126848] pci 0000:00:19.0: reg 0x18: [io 0x1840-0x185f] +[ 0.126939] pci 0000:00:19.0: PME# supported from D0 D3hot D3cold +[ 0.127029] pci 0000:00:19.0: System wakeup disabled by ACPI +[ 0.127114] pci 0000:00:1a.0: [8086:2937] type 00 class 0x0c0300 +[ 0.127171] pci 0000:00:1a.0: reg 0x20: [io 0x1860-0x187f] +[ 0.127276] pci 0000:00:1a.0: System wakeup disabled by ACPI +[ 0.127361] pci 0000:00:1a.1: [8086:2938] type 00 class 0x0c0300 +[ 0.127418] pci 0000:00:1a.1: reg 0x20: [io 0x1880-0x189f] +[ 0.127537] pci 0000:00:1a.2: [8086:2939] type 00 class 0x0c0300 +[ 0.127594] pci 0000:00:1a.2: reg 0x20: [io 0x18a0-0x18bf] +[ 0.127696] pci 0000:00:1a.2: System wakeup disabled by ACPI +[ 0.127792] pci 0000:00:1a.7: [8086:293c] type 00 class 0x0c0320 +[ 0.127818] pci 0000:00:1a.7: reg 0x10: [mem 0xfc226c00-0xfc226fff] +[ 0.127930] pci 0000:00:1a.7: PME# supported from D0 D3hot D3cold +[ 0.127981] pci 0000:00:1a.7: System wakeup disabled by ACPI +[ 0.128048] pci 0000:00:1b.0: [8086:293e] type 00 class 0x040300 +[ 0.128069] pci 0000:00:1b.0: reg 0x10: [mem 0xfc020000-0xfc023fff 64bit] +[ 0.128169] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold +[ 0.128224] pci 0000:00:1b.0: System wakeup disabled by ACPI +[ 0.128310] pci 0000:00:1c.0: [8086:2940] type 01 class 0x060400 +[ 0.128414] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold +[ 0.128466] pci 0000:00:1c.0: System wakeup disabled by ACPI +[ 0.128551] pci 0000:00:1c.1: [8086:2942] type 01 class 0x060400 +[ 0.128655] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold +[ 0.128706] pci 0000:00:1c.1: System wakeup disabled by ACPI +[ 0.128794] pci 0000:00:1c.3: [8086:2946] type 01 class 0x060400 +[ 0.128898] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold +[ 0.128950] pci 0000:00:1c.3: System wakeup disabled by ACPI +[ 0.129044] pci 0000:00:1c.4: [8086:2948] type 01 class 0x060400 +[ 0.129148] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold +[ 0.129202] pci 0000:00:1c.4: System wakeup disabled by ACPI +[ 0.129292] pci 0000:00:1d.0: [8086:2934] type 00 class 0x0c0300 +[ 0.129350] pci 0000:00:1d.0: reg 0x20: [io 0x18c0-0x18df] +[ 0.129453] pci 0000:00:1d.0: System wakeup disabled by ACPI +[ 0.129538] pci 0000:00:1d.1: [8086:2935] type 00 class 0x0c0300 +[ 0.129596] pci 0000:00:1d.1: reg 0x20: [io 0x18e0-0x18ff] +[ 0.129715] pci 0000:00:1d.2: [8086:2936] type 00 class 0x0c0300 +[ 0.129772] pci 0000:00:1d.2: reg 0x20: [io 0x1c00-0x1c1f] +[ 0.129902] pci 0000:00:1d.7: [8086:293a] type 00 class 0x0c0320 +[ 0.129928] pci 0000:00:1d.7: reg 0x10: [mem 0xfc227000-0xfc2273ff] +[ 0.130077] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold +[ 0.130126] pci 0000:00:1d.7: System wakeup disabled by ACPI +[ 0.130211] pci 0000:00:1e.0: [8086:2448] type 01 class 0x060401 +[ 0.130321] pci 0000:00:1e.0: System wakeup disabled by ACPI +[ 0.130413] pci 0000:00:1f.0: [8086:2917] type 00 class 0x060100 +[ 0.130633] pci 0000:00:1f.2: [8086:2929] type 00 class 0x010601 +[ 0.130660] pci 0000:00:1f.2: reg 0x10: [io 0x1c48-0x1c4f] +[ 0.130672] pci 0000:00:1f.2: reg 0x14: [io 0x183c-0x183f] +[ 0.130683] pci 0000:00:1f.2: reg 0x18: [io 0x1c40-0x1c47] +[ 0.130694] pci 0000:00:1f.2: reg 0x1c: [io 0x1838-0x183b] +[ 0.130705] pci 0000:00:1f.2: reg 0x20: [io 0x1c20-0x1c3f] +[ 0.130717] pci 0000:00:1f.2: reg 0x24: [mem 0xfc226000-0xfc2267ff] +[ 0.130788] pci 0000:00:1f.2: PME# supported from D3hot +[ 0.130868] pci 0000:00:1f.3: [8086:2930] type 00 class 0x0c0500 +[ 0.130889] pci 0000:00:1f.3: reg 0x10: [mem 0xfc227400-0xfc2274ff 64bit] +[ 0.130919] pci 0000:00:1f.3: reg 0x20: [io 0x1c60-0x1c7f] +[ 0.131080] pci 0000:00:1c.0: PCI bridge to [bus 02] +[ 0.131240] pci 0000:03:00.0: [8086:4237] type 00 class 0x028000 +[ 0.131281] pci 0000:03:00.0: reg 0x10: [mem 0xf4300000-0xf4301fff 64bit] +[ 0.131478] pci 0000:03:00.0: PME# supported from D0 D3hot D3cold +[ 0.133022] pci 0000:00:1c.1: PCI bridge to [bus 03] +[ 0.133077] pci 0000:00:1c.1: bridge window [mem 0xf4300000-0xf43fffff] +[ 0.133160] pci 0000:00:1c.3: PCI bridge to [bus 05-0c] +[ 0.133212] pci 0000:00:1c.3: bridge window [io 0x2000-0x2fff] +[ 0.133217] pci 0000:00:1c.3: bridge window [mem 0xf8000000-0xf9ffffff] +[ 0.133224] pci 0000:00:1c.3: bridge window [mem 0xf4000000-0xf40fffff 64bit pref] +[ 0.133300] pci 0000:00:1c.4: PCI bridge to [bus 0d-14] +[ 0.133300] pci 0000:00:1c.4: bridge window [io 0x3000-0x3fff] +[ 0.133300] pci 0000:00:1c.4: bridge window [mem 0xfa000000-0xfbffffff] +[ 0.133300] pci 0000:00:1c.4: bridge window [mem 0xf4100000-0xf41fffff 64bit pref] +[ 0.133300] pci 0000:15:00.0: [1180:0476] type 02 class 0x060700 +[ 0.133300] pci 0000:15:00.0: reg 0x10: [mem 0xf4800000-0xf4800fff] +[ 0.133300] pci 0000:15:00.0: supports D1 D2 +[ 0.133300] pci 0000:15:00.0: PME# supported from D0 D1 D2 D3hot D3cold +[ 0.133300] pci 0000:15:00.1: [1180:0832] type 00 class 0x0c0010 +[ 0.133300] pci 0000:15:00.1: reg 0x10: [mem 0xf4801000-0xf48017ff] +[ 0.133370] pci 0000:15:00.1: supports D1 D2 +[ 0.133372] pci 0000:15:00.1: PME# supported from D0 D1 D2 D3hot D3cold +[ 0.133486] pci 0000:00:1e.0: PCI bridge to [bus 15-18] (subtractive decode) +[ 0.133540] pci 0000:00:1e.0: bridge window [io 0x4000-0x7fff] +[ 0.133544] pci 0000:00:1e.0: bridge window [mem 0xf4800000-0xf7ffffff] +[ 0.133552] pci 0000:00:1e.0: bridge window [mem 0xf0000000-0xf3ffffff 64bit pref] +[ 0.133554] pci 0000:00:1e.0: bridge window [io 0x0000-0x0cf7] (subtractive decode) +[ 0.133556] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff] (subtractive decode) +[ 0.133558] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode) +[ 0.133560] pci 0000:00:1e.0: bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode) +[ 0.133562] pci 0000:00:1e.0: bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode) +[ 0.133564] pci 0000:00:1e.0: bridge window [mem 0xbf000000-0xfebfffff] (subtractive decode) +[ 0.133617] pci_bus 0000:16: busn_res: can not insert [bus 16-ff] under [bus 15-18] (conflicts with (null) [bus 15-18]) +[ 0.133622] pci_bus 0000:16: busn_res: [bus 16-ff] end is updated to 17 +[ 0.133662] acpi PNP0A08:00: Disabling ASPM (FADT indicates it is unsupported) +[ 0.135513] ACPI: Enabled 3 GPEs in block 00 to 3F +[ 0.136014] ACPI: \_SB_.PCI0: notify handler is installed +[ 0.136055] Found 1 acpi root devices +[ 0.136128] ACPI : EC: GPE = 0x11, I/O: command/status = 0x66, data = 0x62 +[ 0.136258] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none +[ 0.136258] vgaarb: loaded +[ 0.136258] vgaarb: bridge control possible 0000:00:02.0 +[ 0.136373] SCSI subsystem initialized +[ 0.136451] libata version 3.00 loaded. +[ 0.136451] ACPI: bus type USB registered +[ 0.136451] usbcore: registered new interface driver usbfs +[ 0.136451] usbcore: registered new interface driver hub +[ 0.136451] usbcore: registered new device driver usb +[ 0.137057] PCI: Using ACPI for IRQ routing +[ 0.139507] PCI: pci_cache_line_size set to 64 bytes +[ 0.139595] e820: reserve RAM buffer [mem 0x0009ec00-0x0009ffff] +[ 0.139597] e820: reserve RAM buffer [mem 0xbc6a1000-0xbfffffff] +[ 0.139599] e820: reserve RAM buffer [mem 0xbc7b7000-0xbfffffff] +[ 0.139602] e820: reserve RAM buffer [mem 0xbc8c7000-0xbfffffff] +[ 0.139604] e820: reserve RAM buffer [mem 0xbcc00000-0xbfffffff] +[ 0.139695] NetLabel: Initializing +[ 0.139741] NetLabel: domain hash size = 128 +[ 0.139787] NetLabel: protocols = UNLABELED CIPSOv4 +[ 0.139845] NetLabel: unlabeled traffic allowed by default +[ 0.139909] HPET: 4 timers in total, 0 timers will be used for per-cpu timer +[ 0.140009] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0 +[ 0.140210] hpet0: 4 comparators, 64-bit 14.318180 MHz counter +[ 0.142035] Switched to clocksource hpet +[ 0.148707] AppArmor: AppArmor Filesystem Enabled +[ 0.148799] pnp: PnP ACPI init +[ 0.148860] ACPI: bus type PNP registered +[ 0.169274] system 00:00: [mem 0x00000000-0x0009ffff] could not be reserved +[ 0.169326] system 00:00: [mem 0x000c0000-0x000c3fff] could not be reserved +[ 0.169377] system 00:00: [mem 0x000c4000-0x000c7fff] could not be reserved +[ 0.169428] system 00:00: [mem 0x000c8000-0x000cbfff] has been reserved +[ 0.169478] system 00:00: [mem 0x000cc000-0x000cffff] has been reserved +[ 0.169529] system 00:00: [mem 0x000d0000-0x000d3fff] could not be reserved +[ 0.169580] system 00:00: [mem 0x000dc000-0x000dffff] could not be reserved +[ 0.169630] system 00:00: [mem 0x000e0000-0x000e3fff] could not be reserved +[ 0.169681] system 00:00: [mem 0x000e4000-0x000e7fff] could not be reserved +[ 0.169732] system 00:00: [mem 0x000e8000-0x000ebfff] could not be reserved +[ 0.169782] system 00:00: [mem 0x000ec000-0x000effff] could not be reserved +[ 0.169833] system 00:00: [mem 0x000f0000-0x000fffff] could not be reserved +[ 0.169884] system 00:00: [mem 0x00100000-0xbeffffff] could not be reserved +[ 0.169935] system 00:00: [mem 0xfec00000-0xfed3ffff] could not be reserved +[ 0.169986] system 00:00: [mem 0xfed4c000-0xffffffff] could not be reserved +[ 0.170051] system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active) +[ 0.190033] system 00:01: [io 0x164e-0x164f] has been reserved +[ 0.190084] system 00:01: [io 0x1000-0x107f] could not be reserved +[ 0.190134] system 00:01: [io 0x1180-0x11ff] has been reserved +[ 0.190184] system 00:01: [io 0x0800-0x080f] has been reserved +[ 0.190234] system 00:01: [io 0x15e0-0x15ef] has been reserved +[ 0.190283] system 00:01: [io 0x1600-0x1641] has been reserved +[ 0.190332] system 00:01: [io 0x1600-0x161b] has been reserved +[ 0.190382] system 00:01: [mem 0xe0000000-0xefffffff] has been reserved +[ 0.190433] system 00:01: [mem 0xfed1c000-0xfed1ffff] has been reserved +[ 0.191031] system 00:01: [mem 0xfed10000-0xfed13fff] has been reserved +[ 0.191082] system 00:01: [mem 0xfed18000-0xfed18fff] has been reserved +[ 0.191132] system 00:01: [mem 0xfed19000-0xfed19fff] has been reserved +[ 0.191183] system 00:01: [mem 0xfed45000-0xfed4bfff] has been reserved +[ 0.191234] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active) +[ 0.191289] pnp 00:02: Plug and Play ACPI device, IDs PNP0103 (active) +[ 0.191299] pnp 00:03: [dma 4] +[ 0.191320] pnp 00:03: Plug and Play ACPI device, IDs PNP0200 (active) +[ 0.191345] pnp 00:04: Plug and Play ACPI device, IDs PNP0800 (active) +[ 0.191385] pnp 00:05: Plug and Play ACPI device, IDs PNP0c04 (active) +[ 0.191415] pnp 00:06: Plug and Play ACPI device, IDs PNP0b00 (active) +[ 0.191447] pnp 00:07: Plug and Play ACPI device, IDs PNP0303 (active) +[ 0.191477] pnp 00:08: Plug and Play ACPI device, IDs IBM0057 PNP0f13 (active) +[ 0.211407] pnp 00:09: Plug and Play ACPI device, IDs PNP0c31 (active) +[ 0.211859] pnp: PnP ACPI: found 10 devices +[ 0.211906] ACPI: bus type PNP unregistered +[ 0.218816] pci 0000:00:1c.0: bridge window [io 0x1000-0x0fff] to [bus 02] add_size 1000 +[ 0.218820] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 02] add_size 200000 +[ 0.218823] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff] to [bus 02] add_size 200000 +[ 0.218834] pci 0000:00:1c.1: bridge window [io 0x1000-0x0fff] to [bus 03] add_size 1000 +[ 0.218839] pci 0000:00:1c.1: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 03] add_size 200000 +[ 0.218880] pci 0000:00:1c.0: res[14]=[mem 0x00100000-0x000fffff] get_res_add_size add_size 200000 +[ 0.218882] pci 0000:00:1c.0: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000 +[ 0.218884] pci 0000:00:1c.1: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000 +[ 0.218887] pci 0000:00:1c.0: res[13]=[io 0x1000-0x0fff] get_res_add_size add_size 1000 +[ 0.218889] pci 0000:00:1c.1: res[13]=[io 0x1000-0x0fff] get_res_add_size add_size 1000 +[ 0.218894] pci 0000:00:1c.0: BAR 14: assigned [mem 0xbf000000-0xbf1fffff] +[ 0.218946] pci 0000:00:1c.0: BAR 15: assigned [mem 0xbf200000-0xbf3fffff 64bit pref] +[ 0.219019] pci 0000:00:1c.1: BAR 15: assigned [mem 0xbf400000-0xbf5fffff 64bit pref] +[ 0.219082] pci 0000:00:1c.0: BAR 13: assigned [io 0x8000-0x8fff] +[ 0.219133] pci 0000:00:1c.1: BAR 13: assigned [io 0x9000-0x9fff] +[ 0.219184] pci 0000:00:1c.0: PCI bridge to [bus 02] +[ 0.219234] pci 0000:00:1c.0: bridge window [io 0x8000-0x8fff] +[ 0.219287] pci 0000:00:1c.0: bridge window [mem 0xbf000000-0xbf1fffff] +[ 0.219340] pci 0000:00:1c.0: bridge window [mem 0xbf200000-0xbf3fffff 64bit pref] +[ 0.219407] pci 0000:00:1c.1: PCI bridge to [bus 03] +[ 0.219456] pci 0000:00:1c.1: bridge window [io 0x9000-0x9fff] +[ 0.219509] pci 0000:00:1c.1: bridge window [mem 0xf4300000-0xf43fffff] +[ 0.219562] pci 0000:00:1c.1: bridge window [mem 0xbf400000-0xbf5fffff 64bit pref] +[ 0.219629] pci 0000:00:1c.3: PCI bridge to [bus 05-0c] +[ 0.219678] pci 0000:00:1c.3: bridge window [io 0x2000-0x2fff] +[ 0.219731] pci 0000:00:1c.3: bridge window [mem 0xf8000000-0xf9ffffff] +[ 0.219784] pci 0000:00:1c.3: bridge window [mem 0xf4000000-0xf40fffff 64bit pref] +[ 0.219850] pci 0000:00:1c.4: PCI bridge to [bus 0d-14] +[ 0.219900] pci 0000:00:1c.4: bridge window [io 0x3000-0x3fff] +[ 0.219953] pci 0000:00:1c.4: bridge window [mem 0xfa000000-0xfbffffff] +[ 0.220016] pci 0000:00:1c.4: bridge window [mem 0xf4100000-0xf41fffff 64bit pref] +[ 0.220084] pci 0000:15:00.0: res[15]=[mem 0x04000000-0x03ffffff pref] get_res_add_size add_size 4000000 +[ 0.220087] pci 0000:15:00.0: res[16]=[mem 0x04000000-0x03ffffff] get_res_add_size add_size 4000000 +[ 0.220089] pci 0000:15:00.0: res[13]=[io 0x0100-0x00ff] get_res_add_size add_size 100 +[ 0.220091] pci 0000:15:00.0: res[14]=[io 0x0100-0x00ff] get_res_add_size add_size 100 +[ 0.220094] pci 0000:15:00.0: BAR 15: assigned [mem 0xf0000000-0xf3ffffff pref] +[ 0.220156] pci 0000:15:00.0: BAR 16: assigned [mem 0xc0000000-0xc3ffffff] +[ 0.220206] pci 0000:15:00.0: BAR 13: assigned [io 0x4000-0x40ff] +[ 0.220256] pci 0000:15:00.0: BAR 14: assigned [io 0x4400-0x44ff] +[ 0.220306] pci 0000:15:00.0: CardBus bridge to [bus 16-17] +[ 0.220354] pci 0000:15:00.0: bridge window [io 0x4000-0x40ff] +[ 0.220407] pci 0000:15:00.0: bridge window [io 0x4400-0x44ff] +[ 0.220460] pci 0000:15:00.0: bridge window [mem 0xf0000000-0xf3ffffff pref] +[ 0.220524] pci 0000:15:00.0: bridge window [mem 0xc0000000-0xc3ffffff] +[ 0.220577] pci 0000:00:1e.0: PCI bridge to [bus 15-18] +[ 0.220627] pci 0000:00:1e.0: bridge window [io 0x4000-0x7fff] +[ 0.220680] pci 0000:00:1e.0: bridge window [mem 0xf4800000-0xf7ffffff] +[ 0.220733] pci 0000:00:1e.0: bridge window [mem 0xf0000000-0xf3ffffff 64bit pref] +[ 0.220800] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7] +[ 0.220802] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff] +[ 0.220804] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff] +[ 0.220806] pci_bus 0000:00: resource 7 [mem 0x000d4000-0x000d7fff] +[ 0.220808] pci_bus 0000:00: resource 8 [mem 0x000d8000-0x000dbfff] +[ 0.220810] pci_bus 0000:00: resource 9 [mem 0xbf000000-0xfebfffff] +[ 0.220812] pci_bus 0000:02: resource 0 [io 0x8000-0x8fff] +[ 0.220814] pci_bus 0000:02: resource 1 [mem 0xbf000000-0xbf1fffff] +[ 0.220816] pci_bus 0000:02: resource 2 [mem 0xbf200000-0xbf3fffff 64bit pref] +[ 0.220819] pci_bus 0000:03: resource 0 [io 0x9000-0x9fff] +[ 0.220821] pci_bus 0000:03: resource 1 [mem 0xf4300000-0xf43fffff] +[ 0.220823] pci_bus 0000:03: resource 2 [mem 0xbf400000-0xbf5fffff 64bit pref] +[ 0.220825] pci_bus 0000:05: resource 0 [io 0x2000-0x2fff] +[ 0.220827] pci_bus 0000:05: resource 1 [mem 0xf8000000-0xf9ffffff] +[ 0.220829] pci_bus 0000:05: resource 2 [mem 0xf4000000-0xf40fffff 64bit pref] +[ 0.220831] pci_bus 0000:0d: resource 0 [io 0x3000-0x3fff] +[ 0.220833] pci_bus 0000:0d: resource 1 [mem 0xfa000000-0xfbffffff] +[ 0.220835] pci_bus 0000:0d: resource 2 [mem 0xf4100000-0xf41fffff 64bit pref] +[ 0.220837] pci_bus 0000:15: resource 0 [io 0x4000-0x7fff] +[ 0.220839] pci_bus 0000:15: resource 1 [mem 0xf4800000-0xf7ffffff] +[ 0.220841] pci_bus 0000:15: resource 2 [mem 0xf0000000-0xf3ffffff 64bit pref] +[ 0.220843] pci_bus 0000:15: resource 4 [io 0x0000-0x0cf7] +[ 0.220845] pci_bus 0000:15: resource 5 [io 0x0d00-0xffff] +[ 0.220847] pci_bus 0000:15: resource 6 [mem 0x000a0000-0x000bffff] +[ 0.220849] pci_bus 0000:15: resource 7 [mem 0x000d4000-0x000d7fff] +[ 0.220851] pci_bus 0000:15: resource 8 [mem 0x000d8000-0x000dbfff] +[ 0.220853] pci_bus 0000:15: resource 9 [mem 0xbf000000-0xfebfffff] +[ 0.220855] pci_bus 0000:16: resource 0 [io 0x4000-0x40ff] +[ 0.220857] pci_bus 0000:16: resource 1 [io 0x4400-0x44ff] +[ 0.220859] pci_bus 0000:16: resource 2 [mem 0xf0000000-0xf3ffffff pref] +[ 0.220861] pci_bus 0000:16: resource 3 [mem 0xc0000000-0xc3ffffff] +[ 0.220895] NET: Registered protocol family 2 +[ 0.221177] TCP established hash table entries: 32768 (order: 6, 262144 bytes) +[ 0.221389] TCP bind hash table entries: 32768 (order: 7, 524288 bytes) +[ 0.221653] TCP: Hash tables configured (established 32768 bind 32768) +[ 0.221760] TCP: reno registered +[ 0.221813] UDP hash table entries: 2048 (order: 4, 65536 bytes) +[ 0.221896] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes) +[ 0.222044] NET: Registered protocol family 1 +[ 0.222105] pci 0000:00:02.0: Boot video device +[ 0.223124] PCI: CLS 64 bytes, default 64 +[ 0.223191] Trying to unpack rootfs image as initramfs... +[ 0.697471] Freeing initrd memory: 22980K (ffff88003530e000 - ffff88003697f000) +[ 0.697602] Simple Boot Flag at 0x35 set to 0x1 +[ 0.697804] microcode: CPU0 sig=0x10676, pf=0x80, revision=0x60c +[ 0.697859] microcode: CPU1 sig=0x10676, pf=0x80, revision=0x60c +[ 0.698022] microcode: Microcode Update Driver: v2.00 , Peter Oruba +[ 0.698085] Scanning for low memory corruption every 60 seconds +[ 0.698408] Initialise system trusted keyring +[ 0.698509] audit: initializing netlink socket (disabled) +[ 0.698572] type=2000 audit(1426618190.697:1): initialized +[ 0.722387] HugeTLB registered 2 MB page size, pre-allocated 0 pages +[ 0.723752] zbud: loaded +[ 0.723943] VFS: Disk quotas dquot_6.5.2 +[ 0.724046] Dquot-cache hash table entries: 512 (order 0, 4096 bytes) +[ 0.724601] fuse init (API version 7.22) +[ 0.724734] msgmni has been set to 5902 +[ 0.724842] Key type big_key registered +[ 0.725412] Key type asymmetric registered +[ 0.725461] Asymmetric key parser 'x509' registered +[ 0.725541] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252) +[ 0.725640] io scheduler noop registered +[ 0.725689] io scheduler deadline registered +[ 0.725763] io scheduler cfq registered +[ 0.725812] io scheduler bfq registered (default) +[ 0.725859] BFQ I/O-scheduler version: v7r5 +[ 0.726126] pcieport 0000:00:1c.0: irq 40 for MSI/MSI-X +[ 0.726343] pcieport 0000:00:1c.1: irq 41 for MSI/MSI-X +[ 0.726516] pcieport 0000:00:1c.3: irq 42 for MSI/MSI-X +[ 0.726692] pcieport 0000:00:1c.4: irq 43 for MSI/MSI-X +[ 0.726843] pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt +[ 0.726898] pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded +[ 0.726954] pcieport 0000:00:1c.1: Signaling PME through PCIe PME interrupt +[ 0.727017] pci 0000:03:00.0: Signaling PME through PCIe PME interrupt +[ 0.727071] pcie_pme 0000:00:1c.1:pcie01: service driver pcie_pme loaded +[ 0.727130] pcieport 0000:00:1c.3: Signaling PME through PCIe PME interrupt +[ 0.727186] pcie_pme 0000:00:1c.3:pcie01: service driver pcie_pme loaded +[ 0.727249] pcieport 0000:00:1c.4: Signaling PME through PCIe PME interrupt +[ 0.727303] pcie_pme 0000:00:1c.4:pcie01: service driver pcie_pme loaded +[ 0.727318] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 +[ 0.727424] pciehp 0000:00:1c.0:pcie04: HPC vendor_id 8086 device_id 2940 ss_vid 17aa ss_did 20f3 +[ 0.727553] pciehp 0000:00:1c.0:pcie04: service driver pciehp loaded +[ 0.727568] pciehp 0000:00:1c.1:pcie04: HPC vendor_id 8086 device_id 2942 ss_vid 17aa ss_did 20f3 +[ 0.727697] pciehp 0000:00:1c.1:pcie04: service driver pciehp loaded +[ 0.727712] pciehp 0000:00:1c.3:pcie04: HPC vendor_id 8086 device_id 2946 ss_vid 17aa ss_did 20f3 +[ 0.727840] pciehp 0000:00:1c.3:pcie04: service driver pciehp loaded +[ 0.727857] pciehp 0000:00:1c.4:pcie04: HPC vendor_id 8086 device_id 2948 ss_vid 17aa ss_did 20f3 +[ 0.727983] pciehp 0000:00:1c.4:pcie04: service driver pciehp loaded +[ 0.727992] pciehp: PCI Express Hot Plug Controller Driver version: 0.4 +[ 0.728102] intel_idle: does not run on family 6 model 23 +[ 0.728108] ipmi message handler version 39.2 +[ 0.728317] ACPI: Deprecated procfs I/F for AC is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +[ 0.728552] ACPI: AC Adapter [AC] (on-line) +[ 0.728689] input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0C0D:00/input/input0 +[ 0.729044] ACPI: Lid Switch [LID] +[ 0.729128] input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input1 +[ 0.729192] ACPI: Sleep Button [SLPB] +[ 0.729278] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 +[ 0.729340] ACPI: Power Button [PWRF] +[ 0.730844] Monitor-Mwait will be used to enter C-1 state +[ 0.730850] Monitor-Mwait will be used to enter C-2 state +[ 0.730854] Monitor-Mwait will be used to enter C-3 state +[ 0.730857] tsc: Marking TSC unstable due to TSC halts in idle +[ 0.730914] ACPI: acpi_idle registered with cpuidle +[ 0.733365] thermal LNXTHERM:00: registered as thermal_zone0 +[ 0.733418] ACPI: Thermal Zone [THM0] (41 C) +[ 0.734886] thermal LNXTHERM:01: registered as thermal_zone1 +[ 0.734941] ACPI: Thermal Zone [THM1] (43 C) +[ 0.735032] GHES: HEST is not enabled! +[ 0.735212] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +[ 0.735285] ACPI: Battery Slot [BAT0] (battery absent) +[ 0.735365] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled +[ 0.757657] 0000:00:03.3: ttyS4 at I/O 0x1830 (irq = 17, base_baud = 115200) is a 16550A +[ 0.758028] Linux agpgart interface v0.103 +[ 0.758161] agpgart-intel 0000:00:00.0: Intel GM45 Chipset +[ 0.758296] agpgart-intel 0000:00:00.0: detected gtt size: 2097152K total, 262144K mappable +[ 0.759478] agpgart-intel 0000:00:00.0: detected 32768K stolen memory +[ 0.759697] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xd0000000 +[ 0.765051] tpm_tis 00:09: 1.2 TPM (device-id 0x1020, rev-id 6) +[ 0.765104] tpm_tis 00:09: Intel iTPM workaround enabled +[ 0.837123] tpm_tis 00:09: TPM is disabled/deactivated (0x6) +[ 0.838867] brd: module loaded +[ 0.839781] loop: module loaded +[ 0.840412] scsi0 : ata_generic +[ 0.840576] scsi1 : ata_generic +[ 0.840672] ata1: PATA max UDMA/100 cmd 0x1828 ctl 0x180c bmdma 0x1810 irq 18 +[ 0.840722] ata2: PATA max UDMA/100 cmd 0x1820 ctl 0x1808 bmdma 0x1818 irq 18 +[ 0.841130] libphy: Fixed MDIO Bus: probed +[ 0.841267] tun: Universal TUN/TAP device driver, 1.6 +[ 0.841315] tun: (C) 1999-2004 Max Krasnyansky +[ 0.841432] PPP generic driver version 2.4.2 +[ 0.841561] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver +[ 0.841614] ehci-pci: EHCI PCI platform driver +[ 0.841763] ehci-pci 0000:00:1a.7: EHCI Host Controller +[ 0.841816] ehci-pci 0000:00:1a.7: new USB bus registered, assigned bus number 1 +[ 0.841890] ehci-pci 0000:00:1a.7: debug port 1 +[ 0.845829] ehci-pci 0000:00:1a.7: cache line size of 64 is not supported +[ 0.845911] ehci-pci 0000:00:1a.7: irq 23, io mem 0xfc226c00 +[ 0.852066] ehci-pci 0000:00:1a.7: USB 2.0 started, EHCI 1.00 +[ 0.852201] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 +[ 0.852252] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.852312] usb usb1: Product: EHCI Host Controller +[ 0.852360] usb usb1: Manufacturer: Linux 3.13.0-39-lowlatency ehci_hcd +[ 0.852410] usb usb1: SerialNumber: 0000:00:1a.7 +[ 0.852583] hub 1-0:1.0: USB hub found +[ 0.852641] hub 1-0:1.0: 6 ports detected +[ 0.852924] ehci-pci 0000:00:1d.7: EHCI Host Controller +[ 0.852976] ehci-pci 0000:00:1d.7: new USB bus registered, assigned bus number 2 +[ 0.853060] ehci-pci 0000:00:1d.7: debug port 1 +[ 0.857027] ehci-pci 0000:00:1d.7: cache line size of 64 is not supported +[ 0.857110] ehci-pci 0000:00:1d.7: irq 19, io mem 0xfc227000 +[ 0.863125] ehci-pci 0000:00:1d.7: USB 2.0 started, EHCI 1.00 +[ 0.863229] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002 +[ 0.863286] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.863347] usb usb2: Product: EHCI Host Controller +[ 0.863394] usb usb2: Manufacturer: Linux 3.13.0-39-lowlatency ehci_hcd +[ 0.863444] usb usb2: SerialNumber: 0000:00:1d.7 +[ 0.863605] hub 2-0:1.0: USB hub found +[ 0.863663] hub 2-0:1.0: 6 ports detected +[ 0.863833] ehci-platform: EHCI generic platform driver +[ 0.863889] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver +[ 0.863938] ohci-pci: OHCI PCI platform driver +[ 0.863993] ohci-platform: OHCI generic platform driver +[ 0.864059] uhci_hcd: USB Universal Host Controller Interface driver +[ 0.864716] uhci_hcd 0000:00:1a.0: UHCI Host Controller +[ 0.864767] uhci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 3 +[ 0.864931] uhci_hcd 0000:00:1a.0: irq 20, io base 0x00001860 +[ 0.865045] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.865096] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.865156] usb usb3: Product: UHCI Host Controller +[ 0.865204] usb usb3: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.865254] usb usb3: SerialNumber: 0000:00:1a.0 +[ 0.865419] hub 3-0:1.0: USB hub found +[ 0.865473] hub 3-0:1.0: 2 ports detected +[ 0.865668] uhci_hcd 0000:00:1a.1: UHCI Host Controller +[ 0.865720] uhci_hcd 0000:00:1a.1: new USB bus registered, assigned bus number 4 +[ 0.865881] uhci_hcd 0000:00:1a.1: irq 21, io base 0x00001880 +[ 0.865991] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.866063] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.866139] usb usb4: Product: UHCI Host Controller +[ 0.866187] usb usb4: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.866243] usb usb4: SerialNumber: 0000:00:1a.1 +[ 0.866408] hub 4-0:1.0: USB hub found +[ 0.866465] hub 4-0:1.0: 2 ports detected +[ 0.866647] uhci_hcd 0000:00:1a.2: UHCI Host Controller +[ 0.866699] uhci_hcd 0000:00:1a.2: new USB bus registered, assigned bus number 5 +[ 0.866858] uhci_hcd 0000:00:1a.2: irq 22, io base 0x000018a0 +[ 0.866957] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.867019] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.867080] usb usb5: Product: UHCI Host Controller +[ 0.867128] usb usb5: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.867178] usb usb5: SerialNumber: 0000:00:1a.2 +[ 0.867353] hub 5-0:1.0: USB hub found +[ 0.867407] hub 5-0:1.0: 2 ports detected +[ 0.867607] uhci_hcd 0000:00:1d.0: UHCI Host Controller +[ 0.867660] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 6 +[ 0.867817] uhci_hcd 0000:00:1d.0: irq 16, io base 0x000018c0 +[ 0.867932] usb usb6: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.867983] usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.868061] usb usb6: Product: UHCI Host Controller +[ 0.868109] usb usb6: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.868158] usb usb6: SerialNumber: 0000:00:1d.0 +[ 0.868326] hub 6-0:1.0: USB hub found +[ 0.868383] hub 6-0:1.0: 2 ports detected +[ 0.868573] uhci_hcd 0000:00:1d.1: UHCI Host Controller +[ 0.868625] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 7 +[ 0.868782] uhci_hcd 0000:00:1d.1: irq 17, io base 0x000018e0 +[ 0.868877] usb usb7: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.868927] usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.868988] usb usb7: Product: UHCI Host Controller +[ 0.869050] usb usb7: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.869108] usb usb7: SerialNumber: 0000:00:1d.1 +[ 0.869282] hub 7-0:1.0: USB hub found +[ 0.869339] hub 7-0:1.0: 2 ports detected +[ 0.869523] uhci_hcd 0000:00:1d.2: UHCI Host Controller +[ 0.869575] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 8 +[ 0.869725] uhci_hcd 0000:00:1d.2: irq 18, io base 0x00001c00 +[ 0.869827] usb usb8: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.869878] usb usb8: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.869938] usb usb8: Product: UHCI Host Controller +[ 0.869986] usb usb8: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.870048] usb usb8: SerialNumber: 0000:00:1d.2 +[ 0.870207] hub 8-0:1.0: USB hub found +[ 0.870259] hub 8-0:1.0: 2 ports detected +[ 0.870429] i8042: PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12 +[ 0.878171] serio: i8042 KBD port at 0x60,0x64 irq 1 +[ 0.878246] serio: i8042 AUX port at 0x60,0x64 irq 12 +[ 0.878429] mousedev: PS/2 mouse device common for all mice +[ 0.878688] rtc_cmos 00:06: RTC can wake from S4 +[ 0.878876] rtc_cmos 00:06: rtc core: registered rtc_cmos as rtc0 +[ 0.878999] rtc_cmos 00:06: alarms up to one month, y3k, 114 bytes nvram, hpet irqs +[ 0.879154] device-mapper: uevent: version 1.0.3 +[ 0.879274] device-mapper: ioctl: 4.27.0-ioctl (2013-10-30) initialised: dm-devel@redhat.com +[ 0.879342] ledtrig-cpu: registered to indicate activity on CPUs +[ 0.879495] TCP: cubic registered +[ 0.879638] NET: Registered protocol family 10 +[ 0.879887] NET: Registered protocol family 17 +[ 0.879946] Key type dns_resolver registered +[ 0.880318] Loading compiled-in X.509 certificates +[ 0.881536] Loaded X.509 cert 'Magrathea: Glacier signing key: a7171335f18ca6131c1947ca87d46fb662317fa6' +[ 0.881611] registered taskstats version 1 +[ 0.883655] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3 +[ 0.884186] Key type trusted registered +[ 0.886362] Key type encrypted registered +[ 0.888541] AppArmor: AppArmor sha1 policy hashing enabled +[ 0.906069] tpm_tis 00:09: A TPM error (6) occurred attempting to read a pcr value +[ 0.906134] IMA: No TPM chip found, activating TPM-bypass! +[ 0.906542] regulator-dummy: disabling +[ 0.906622] Magic number: 7:954:847 +[ 0.906816] rtc_cmos 00:06: setting system clock to 2015-03-17 18:49:51 UTC (1426618191) +[ 0.909146] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found +[ 0.909198] EDD information not available. +[ 0.909325] PM: Hibernation image not present or could not be loaded. +[ 1.164738] Freeing unused kernel memory: 1324K (ffffffff81d1d000 - ffffffff81e68000) +[ 1.164804] Write protecting the kernel read-only data: 12288k +[ 1.168375] Freeing unused kernel memory: 764K (ffff880001741000 - ffff880001800000) +[ 1.171458] Freeing unused kernel memory: 676K (ffff880001b57000 - ffff880001c00000) +[ 1.191531] systemd-udevd[133]: starting version 204 +[ 1.220543] pps_core: LinuxPPS API ver. 1 registered +[ 1.220600] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti +[ 1.225352] PTP clock support registered +[ 1.236203] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k +[ 1.236368] e1000e: Copyright(c) 1999 - 2013 Intel Corporation. +[ 1.236654] e1000e 0000:00:19.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode +[ 1.236749] e1000e 0000:00:19.0: irq 44 for MSI/MSI-X +[ 1.245390] wmi: Mapper loaded +[ 1.246806] [drm] Initialized drm 1.1.0 20060810 +[ 1.353201] firewire_ohci 0000:15:00.1: added OHCI v1.10 device as card 0, 4 IR + 4 IT contexts, quirks 0x11 +[ 1.446329] e1000e 0000:00:19.0 eth0: (PCI Express:2.5GT/s:Width x1) 00:1c:25:9f:c6:0e +[ 1.446396] e1000e 0000:00:19.0 eth0: Intel(R) PRO/1000 Network Connection +[ 1.446475] e1000e 0000:00:19.0 eth0: MAC: 7, PHY: 8, PBA No: 1008FF-0FF +[ 1.446570] ahci 0000:00:1f.2: version 3.0 +[ 1.446766] ahci 0000:00:1f.2: irq 45 for MSI/MSI-X +[ 1.446816] ahci 0000:00:1f.2: SSS flag set, parallel bus scan disabled +[ 1.446896] ahci 0000:00:1f.2: AHCI 0001.0200 32 slots 4 ports 3 Gbps 0x3 impl SATA mode +[ 1.446962] ahci 0000:00:1f.2: flags: 64bit ncq sntf stag pm led clo pio slum part ccc sxs +[ 1.448104] scsi2 : ahci +[ 1.448255] scsi3 : ahci +[ 1.448399] scsi4 : ahci +[ 1.448552] scsi5 : ahci +[ 1.448664] ata3: SATA max UDMA/133 abar m2048@0xfc226000 port 0xfc226100 irq 45 +[ 1.448734] ata4: SATA max UDMA/133 abar m2048@0xfc226000 port 0xfc226180 irq 45 +[ 1.448797] ata5: DUMMY +[ 1.448843] ata6: DUMMY +[ 1.449570] [drm] Memory usable by graphics device = 2048M +[ 1.510078] usb 4-2: new full-speed USB device number 2 using uhci_hcd +[ 1.514075] i915 0000:00:02.0: irq 46 for MSI/MSI-X +[ 1.514086] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). +[ 1.514139] [drm] Driver supports precise vblank timestamp query. +[ 1.514341] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem +[ 1.630078] [drm] GMBUS [i915 gmbus dpb] timed out, falling back to bit banging on pin 5 +[ 1.665898] fbcon: inteldrmfb (fb0) is primary device +[ 1.667027] usb 4-2: New USB device found, idVendor=0a5c, idProduct=2145 +[ 1.667030] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 +[ 1.667032] usb 4-2: Product: ThinkPad Bluetooth with Enhanced Data Rate II +[ 1.667033] usb 4-2: Manufacturer: Lenovo Computer Corp +[ 1.755095] ata3: SATA link up 1.5 Gbps (SStatus 113 SControl 300) +[ 1.756251] ata3.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.756253] ata3.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out +[ 1.756362] ata3.00: ACPI cmd ef/5f:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.756364] ata3.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out +[ 1.809909] ata3.00: ATA-8: WDC WD1600BEVS-08VAT1, 13.01A13, max UDMA/133 +[ 1.809911] ata3.00: 312581808 sectors, multi 16: LBA48 NCQ (depth 31/32), AA +[ 1.811456] ata3.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.811459] ata3.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out +[ 1.811639] ata3.00: ACPI cmd ef/5f:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.811642] ata3.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out +[ 1.813118] ata3.00: configured for UDMA/133 +[ 1.813311] scsi 2:0:0:0: Direct-Access ATA WDC WD1600BEVS-0 13.0 PQ: 0 ANSI: 5 +[ 1.813543] sd 2:0:0:0: Attached scsi generic sg0 type 0 +[ 1.813561] sd 2:0:0:0: [sda] 312581808 512-byte logical blocks: (160 GB/149 GiB) +[ 1.813724] sd 2:0:0:0: [sda] Write Protect is off +[ 1.813726] sd 2:0:0:0: [sda] Mode Sense: 00 3a 00 00 +[ 1.813787] sd 2:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA +[ 1.848656] sda: sda1 sda2 < sda5 sda6 > +[ 1.849262] sd 2:0:0:0: [sda] Attached SCSI disk +[ 1.854171] firewire_core 0000:15:00.1: created device fw0: GUID 00016c2000a28887, S400 +[ 2.051419] psmouse serio1: synaptics: Touchpad model: 1, fw: 7.0, id: 0x1c0b1, caps: 0xd04791/0xb00000/0x20000, board id: 71, fw id: 434116 +[ 2.051428] psmouse serio1: synaptics: serio: Synaptics pass-through port at isa0060/serio1/input0 +[ 2.091571] input: SynPS/2 Synaptics TouchPad as /devices/platform/i8042/serio1/input/input5 +[ 2.118180] ata4: SATA link up 1.5 Gbps (SStatus 113 SControl 300) +[ 2.121457] ata4.00: ACPI cmd e3/00:1f:00:00:00:a0 (IDLE) succeeded +[ 2.122567] ata4.00: ACPI cmd e3/00:02:00:00:00:a0 (IDLE) succeeded +[ 2.124134] ata4.00: ATAPI: HL-DT-STCD-RW/DVD DRIVE MU10N, 1.05, max UDMA/33 +[ 2.128528] ata4.00: ACPI cmd e3/00:1f:00:00:00:a0 (IDLE) succeeded +[ 2.129580] ata4.00: ACPI cmd e3/00:02:00:00:00:a0 (IDLE) succeeded +[ 2.131137] ata4.00: configured for UDMA/33 +[ 2.140042] scsi 3:0:0:0: CD-ROM HL-DT-ST RW/DVD MU10N 1.05 PQ: 0 ANSI: 5 +[ 2.145419] sr0: scsi3-mmc drive: 24x/24x writer cd/rw xa/form2 cdda tray +[ 2.145420] cdrom: Uniform CD-ROM driver Revision: 3.20 +[ 2.145549] sr 3:0:0:0: Attached scsi CD-ROM sr0 +[ 2.145741] sr 3:0:0:0: Attached scsi generic sg1 type 5 +[ 2.208787] Console: switching to colour frame buffer device 160x50 +[ 2.227499] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device +[ 2.229383] i915 0000:00:02.0: registered panic notifier +[ 2.234366] ACPI: Video Device [VID] (multi-head: yes rom: no post: no) +[ 2.243759] acpi device:02: registered as cooling_device2 +[ 2.245794] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input7 +[ 2.247868] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0 +[ 2.578407] random: nonblocking pool is initialized +[ 2.822478] md: linear personality registered for level -1 +[ 2.826736] md: multipath personality registered for level -4 +[ 2.831280] md: raid0 personality registered for level 0 +[ 2.836263] md: raid1 personality registered for level 1 +[ 2.858032] raid6: sse2x1 2871 MB/s +[ 2.875030] raid6: sse2x2 3324 MB/s +[ 2.892030] raid6: sse2x4 4656 MB/s +[ 2.892057] raid6: using algorithm sse2x4 (4656 MB/s) +[ 2.892090] raid6: using ssse3x2 recovery algorithm +[ 2.894557] xor: measuring software checksum speed +[ 2.904030] prefetch64-sse: 6452.000 MB/sec +[ 2.914030] generic_sse: 5740.000 MB/sec +[ 2.914061] xor: using function: prefetch64-sse (6452.000 MB/sec) +[ 2.916259] async_tx: api initialized (async) +[ 2.928184] md: raid6 personality registered for level 6 +[ 2.928222] md: raid5 personality registered for level 5 +[ 2.928257] md: raid4 personality registered for level 4 +[ 2.937068] md: raid10 personality registered for level 10 +[ 3.093997] bio: create slab at 1 +[ 3.094936] Btrfs loaded +[ 3.390369] EXT4-fs (sda1): mounted filesystem with ordered data mode. Opts: (null) +[ 5.358449] psmouse serio2: alps: Unknown ALPS touchpad: E7=10 00 64, EC=10 00 64 +[ 5.988517] Adding 4230140k swap on /dev/sda5. Priority:-1 extents:1 across:4230140k FS +[ 6.808061] psmouse serio2: trackpoint: IBM TrackPoint firmware: 0x0e, buttons: 3/3 +[ 7.040928] input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/serio2/input/input6 +[ 7.402514] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +[ 7.640430] EXT4-fs (sda1): re-mounted. Opts: errors=remount-ro +[ 7.641692] systemd-udevd[425]: starting version 204 +[ 8.377312] lp: driver loaded but no devices found +[ 8.451574] ppdev: user-space parallel port driver +[ 8.663285] SGI XFS with ACLs, security attributes, realtime, large block/inode numbers, no debug enabled +[ 8.763636] XFS (sda6): Mounting Filesystem +[ 8.987137] XFS (sda6): Ending clean mount +[ 9.764969] cfg80211: Calling CRDA to update world regulatory domain +[ 9.815431] Intel(R) Wireless WiFi driver for Linux, in-tree: +[ 9.815435] Copyright(c) 2003-2013 Intel Corporation +[ 9.815585] iwlwifi 0000:03:00.0: can't disable ASPM; OS doesn't have ASPM control +[ 9.815653] iwlwifi 0000:03:00.0: irq 47 for MSI/MSI-X +[ 9.815784] 0000:03:00.0: Missing Free firmware +[ 9.817262] iwlwifi 0000:03:00.0: Couldn't request the fw +[ 9.818920] iwlwifi: probe of 0000:03:00.0 failed with error -22 +[ 10.041861] pci 0000:03:00.0: Direct firmware load failed with error -2 +[ 10.041867] pci 0000:03:00.0: Falling back to user helper +[ 10.115482] ACPI Warning: 0x0000000000001028-0x000000000000102f SystemIO conflicts with Region \_SB_.PCI0.LPC_.PMIO 1 (20131115/utaddress-251) +[ 10.115492] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 10.115497] ACPI Warning: 0x00000000000011b0-0x00000000000011bf SystemIO conflicts with Region \_SB_.PCI0.LPC_.LPIO 1 (20131115/utaddress-251) +[ 10.115501] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 10.115503] ACPI Warning: 0x0000000000001180-0x00000000000011af SystemIO conflicts with Region \_SB_.PCI0.LPC_.LPIO 1 (20131115/utaddress-251) +[ 10.115508] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 10.115510] lpc_ich: Resource conflict(s) found affecting gpio_ich +[ 10.261508] yenta_cardbus 0000:15:00.0: CardBus bridge found [17aa:20c6] +[ 10.383852] yenta_cardbus 0000:15:00.0: ISA IRQ mask 0x04b8, PCI irq 16 +[ 10.383859] yenta_cardbus 0000:15:00.0: Socket status: 30000006 +[ 10.383867] yenta_cardbus 0000:15:00.0: pcmcia: parent PCI bridge window: [io 0x4000-0x7fff] +[ 10.383870] yenta_cardbus 0000:15:00.0: pcmcia: parent PCI bridge window: [mem 0xf4800000-0xf7ffffff] +[ 10.383874] pcmcia_socket pcmcia_socket0: cs: memory probe 0xf4800000-0xf7ffffff: +[ 10.383879] excluding 0xf4800000-0xf4b7ffff +[ 10.383891] yenta_cardbus 0000:15:00.0: pcmcia: parent PCI bridge window: [mem 0xf0000000-0xf3ffffff 64bit pref] +[ 10.383894] pcmcia_socket pcmcia_socket0: cs: memory probe 0xf0000000-0xf3ffffff: +[ 10.383906] excluding 0xf0000000-0xf3ffffff +[ 10.625496] device-mapper: multipath: version 1.6.0 loaded +[ 10.870142] mei_me 0000:00:03.0: irq 47 for MSI/MSI-X +[ 10.907864] Non-volatile memory driver v1.3 +[ 10.975070] thinkpad_acpi: ThinkPad ACPI Extras v0.25 +[ 10.975074] thinkpad_acpi: http://ibm-acpi.sf.net/ +[ 10.975076] thinkpad_acpi: ThinkPad BIOS 7UET56WW (2.02 ), EC 7VHT12WW-1.01 +[ 10.975078] thinkpad_acpi: Lenovo ThinkPad T400, model 6475GE2 +[ 11.003621] thinkpad_acpi: detected a 16-level brightness capable ThinkPad +[ 11.003835] thinkpad_acpi: radio switch found; radios are enabled +[ 11.003857] thinkpad_acpi: This ThinkPad has standard ACPI backlight brightness control, supported by the ACPI video driver +[ 11.003859] thinkpad_acpi: Disabling thinkpad-acpi brightness events by default... +[ 11.008052] thinkpad_acpi: rfkill switch tpacpi_bluetooth_sw: radio is unblocked +[ 11.014406] thinkpad_acpi: Standard ACPI backlight interface available, not loading native one +[ 11.014610] thinkpad_acpi: Console audio control enabled, mode: monitor (read only) +[ 11.018306] input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input8 +[ 11.199291] kvm: disabled by bios +[ 11.205924] kvm: disabled by bios +[ 12.346341] init: avahi-cups-reload main process (668) terminated with status 1 +[ 12.979286] type=1400 audit(1426618203.572:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/sbin/dhclient" pid=602 comm="apparmor_parser" +[ 12.979296] type=1400 audit(1426618203.572:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=602 comm="apparmor_parser" +[ 12.979303] type=1400 audit(1426618203.572:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=602 comm="apparmor_parser" +[ 12.979315] type=1400 audit(1426618203.572:5): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/sbin/dhclient" pid=532 comm="apparmor_parser" +[ 12.979324] type=1400 audit(1426618203.572:6): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=532 comm="apparmor_parser" +[ 12.979331] type=1400 audit(1426618203.572:7): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=532 comm="apparmor_parser" +[ 12.979954] type=1400 audit(1426618203.572:8): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=602 comm="apparmor_parser" +[ 12.979961] type=1400 audit(1426618203.572:9): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=602 comm="apparmor_parser" +[ 12.979981] type=1400 audit(1426618203.572:10): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=532 comm="apparmor_parser" +[ 12.979988] type=1400 audit(1426618203.572:11): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=532 comm="apparmor_parser" +[ 12.996307] pcmcia_socket pcmcia_socket0: cs: memory probe 0x0c0000-0x0fffff: +[ 12.996318] excluding 0xc0000-0xd3fff 0xdc000-0xfffff +[ 12.996348] pcmcia_socket pcmcia_socket0: cs: memory probe 0xa0000000-0xa0ffffff: +[ 12.996358] excluding 0xa0000000-0xa0ffffff +[ 12.996381] pcmcia_socket pcmcia_socket0: cs: memory probe 0x60000000-0x60ffffff: +[ 12.996390] excluding 0x60000000-0x60ffffff +[ 14.072556] Bluetooth: Core ver 2.17 +[ 14.072608] NET: Registered protocol family 31 +[ 14.072611] Bluetooth: HCI device and connection manager initialized +[ 14.072623] Bluetooth: HCI socket layer initialized +[ 14.072627] Bluetooth: L2CAP socket layer initialized +[ 14.072633] Bluetooth: SCO socket layer initialized +[ 14.168500] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 +[ 14.168506] Bluetooth: BNEP filters: protocol multicast +[ 14.168518] Bluetooth: BNEP socket layer initialized +[ 14.169341] Bluetooth: RFCOMM TTY layer initialized +[ 14.169352] Bluetooth: RFCOMM socket layer initialized +[ 14.169361] Bluetooth: RFCOMM ver 1.11 +[ 14.178064] snd_hda_intel 0000:00:1b.0: irq 48 for MSI/MSI-X +[ 14.229289] hda_codec: CX20561 (Hermosa): BIOS auto-probing. +[ 14.229771] autoconfig: line_outs=1 (0x1a/0x0/0x0/0x0/0x0) type:speaker +[ 14.229774] speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) +[ 14.229776] hp_outs=2 (0x19/0x16/0x0/0x0/0x0) +[ 14.229778] mono: mono_out=0x0 +[ 14.229779] dig-out=0x1c/0x0 +[ 14.229781] inputs: +[ 14.229783] Mic=0x18 +[ 14.229785] Internal Mic=0x1d +[ 14.229787] Dock Mic=0x17 +[ 14.230909] hda_codec: Enable sync_write for stable communication +[ 14.234697] input: HDA Intel Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input12 +[ 14.234908] input: HDA Intel Dock Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input11 +[ 14.235118] input: HDA Intel Dock Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input10 +[ 14.235298] input: HDA Intel Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9 +[ 14.294724] init: failsafe main process (699) killed by TERM signal +[ 14.300364] usbcore: registered new interface driver btusb +[ 15.826334] e1000e 0000:00:19.0: irq 44 for MSI/MSI-X +[ 15.927162] e1000e 0000:00:19.0: irq 44 for MSI/MSI-X +[ 15.927347] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +[ 15.927754] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +[ 16.972911] init: alsa-restore main process (987) terminated with status 99 +[ 19.430838] init: plymouth-upstart-bridge main process ended, respawning +[ 19.613929] e1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx +[ 19.614080] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready +[ 97.723392] init: upstart-udev-bridge main process (418) terminated with status 1 +[ 97.723413] init: upstart-udev-bridge main process ended, respawning +[ 97.723636] init: upstart-file-bridge main process (528) terminated with status 1 +[ 97.723652] init: upstart-file-bridge main process ended, respawning +[ 97.723833] init: upstart-socket-bridge main process (712) terminated with status 1 +[ 97.723849] init: upstart-socket-bridge main process ended, respawning +[ 477.962196] perf samples too long (2508 > 2500), lowering kernel.perf_event_max_sample_rate to 50000 +[ 681.763788] show_signal_msg: 114 callbacks suppressed +[ 681.763795] msrtool[12415]: segfault at 0 ip (null) sp 00007fff82509228 error 14 in msrtool[400000+26be000] diff --git a/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmidecode.log b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmidecode.log new file mode 100644 index 00000000..901f7a48 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/dmidecode.log @@ -0,0 +1,611 @@ +# dmidecode 2.12 +SMBIOS 2.4 present. +74 structures occupying 2469 bytes. +Table at 0x000E0010. + +Handle 0x0000, DMI type 0, 24 bytes +BIOS Information + Vendor: LENOVO + Version: 7UET56WW (2.02 ) + Release Date: 01/09/2009 + Address: 0xE0000 + Runtime Size: 128 kB + ROM Size: 8192 kB + Characteristics: + PCI is supported + PC Card (PCMCIA) is supported + PNP is supported + BIOS is upgradeable + BIOS shadowing is allowed + ESCD support is available + Boot from CD is supported + Selectable boot is supported + BIOS ROM is socketed + EDD is supported + ACPI is supported + USB legacy is supported + BIOS boot specification is supported + Targeted content distribution is supported + BIOS Revision: 2.2 + Firmware Revision: 1.1 + +Handle 0x0001, DMI type 1, 27 bytes +System Information + Manufacturer: LENOVO + Product Name: 6475GE2 + Version: ThinkPad T400 + Serial Number: L3BLN3R + UUID: 044E2A01-4A58-11CB-B7F3-A659D406AA70 + Wake-up Type: Power Switch + SKU Number: Not Specified + Family: ThinkPad T400 + +Handle 0x0002, DMI type 2, 8 bytes +Base Board Information + Manufacturer: LENOVO + Product Name: 6475GE2 + Version: Not Available + Serial Number: VF26F91C27K + +Handle 0x0003, DMI type 3, 13 bytes +Chassis Information + Manufacturer: LENOVO + Type: Notebook + Lock: Not Present + Version: Not Available + Serial Number: Not Available + Asset Tag: 9662148 + Boot-up State: Unknown + Power Supply State: Unknown + Thermal State: Unknown + Security Status: Unknown + +Handle 0x0004, DMI type 126, 13 bytes +Inactive + +Handle 0x0005, DMI type 126, 13 bytes +Inactive + +Handle 0x0006, DMI type 4, 35 bytes +Processor Information + Socket Designation: None + Type: Central Processor + Family: Other + Manufacturer: GenuineIntel + ID: 76 06 01 00 FF FB EB BF + Signature: Type 0, Family 6, Model 23, Stepping 6 + Flags: + FPU (Floating-point unit on-chip) + VME (Virtual mode extension) + DE (Debugging extension) + PSE (Page size extension) + TSC (Time stamp counter) + MSR (Model specific registers) + PAE (Physical address extension) + MCE (Machine check exception) + CX8 (CMPXCHG8 instruction supported) + APIC (On-chip APIC hardware supported) + SEP (Fast system call) + MTRR (Memory type range registers) + PGE (Page global enable) + MCA (Machine check architecture) + CMOV (Conditional move instruction supported) + PAT (Page attribute table) + PSE-36 (36-bit page size extension) + CLFSH (CLFLUSH instruction supported) + DS (Debug store) + ACPI (ACPI supported) + MMX (MMX technology supported) + FXSR (FXSAVE and FXSTOR instructions supported) + SSE (Streaming SIMD extensions) + SSE2 (Streaming SIMD extensions 2) + SS (Self-snoop) + HTT (Multi-threading) + TM (Thermal monitor supported) + PBE (Pending break enabled) + Version: Intel(R) Core(TM)2 Duo CPU P8400 @ 2.26GHz + Voltage: 1.2 V + External Clock: 266 MHz + Max Speed: 2260 MHz + Current Speed: 2260 MHz + Status: Populated, Enabled + Upgrade: None + L1 Cache Handle: 0x000A + L2 Cache Handle: 0x000C + L3 Cache Handle: Not Provided + Serial Number: Not Specified + Asset Tag: Not Specified + Part Number: Not Specified + +Handle 0x0007, DMI type 5, 20 bytes +Memory Controller Information + Error Detecting Method: None + Error Correcting Capabilities: + None + Supported Interleave: One-way Interleave + Current Interleave: One-way Interleave + Maximum Memory Module Size: 4096 MB + Maximum Total Memory Size: 8192 MB + Supported Speeds: + Other + Supported Memory Types: + DIMM + SDRAM + Memory Module Voltage: 2.9 V + Associated Memory Slots: 2 + 0x0008 + 0x0009 + Enabled Error Correcting Capabilities: + Unknown + +Handle 0x0008, DMI type 6, 12 bytes +Memory Module Information + Socket Designation: DIMM Slot 1 + Bank Connections: 0 1 + Current Speed: 155 ns + Type: DIMM SDRAM + Installed Size: 1024 MB (Double-bank Connection) + Enabled Size: 1024 MB (Double-bank Connection) + Error Status: OK + +Handle 0x0009, DMI type 6, 12 bytes +Memory Module Information + Socket Designation: DIMM Slot 2 + Bank Connections: 2 3 + Current Speed: 155 ns + Type: DIMM SDRAM + Installed Size: 2048 MB (Single-bank Connection) + Enabled Size: 2048 MB (Single-bank Connection) + Error Status: OK + +Handle 0x000A, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L1 Cache + Configuration: Enabled, Socketed, Level 1 + Operational Mode: Write Back + Location: Internal + Installed Size: 64 kB + Maximum Size: 64 kB + Supported SRAM Types: + Synchronous + Installed SRAM Type: Synchronous + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Instruction + Associativity: 8-way Set-associative + +Handle 0x000B, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L1 Cache + Configuration: Enabled, Socketed, Level 1 + Operational Mode: Write Back + Location: Internal + Installed Size: 64 kB + Maximum Size: 64 kB + Supported SRAM Types: + Synchronous + Installed SRAM Type: Synchronous + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Data + Associativity: 8-way Set-associative + +Handle 0x000C, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L2 Cache + Configuration: Enabled, Socketed, Level 2 + Operational Mode: Write Back + Location: Internal + Installed Size: 3072 kB + Maximum Size: 3072 kB + Supported SRAM Types: + Burst + Installed SRAM Type: Burst + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Unified + Associativity: 8-way Set-associative + +Handle 0x000D, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: External Monitor + External Connector Type: DB-15 female + Port Type: Video Port + +Handle 0x000E, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Microphone Jack + External Connector Type: Mini Jack (headphones) + Port Type: Audio Port + +Handle 0x000F, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Headphone Jack + External Connector Type: Mini Jack (headphones) + Port Type: Audio Port + +Handle 0x0010, DMI type 126, 9 bytes +Inactive + +Handle 0x0011, DMI type 126, 9 bytes +Inactive + +Handle 0x0012, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Modem + External Connector Type: RJ-11 + Port Type: Modem Port + +Handle 0x0013, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Ethernet + External Connector Type: RJ-45 + Port Type: Network Port + +Handle 0x0014, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 1 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0015, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 2 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0016, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 3 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0017, DMI type 126, 9 bytes +Inactive + +Handle 0x0018, DMI type 126, 9 bytes +Inactive + +Handle 0x0019, DMI type 126, 9 bytes +Inactive + +Handle 0x001A, DMI type 126, 9 bytes +Inactive + +Handle 0x001B, DMI type 126, 9 bytes +Inactive + +Handle 0x001C, DMI type 126, 9 bytes +Inactive + +Handle 0x001D, DMI type 126, 9 bytes +Inactive + +Handle 0x001E, DMI type 126, 9 bytes +Inactive + +Handle 0x001F, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: IEEE1394 + External Connector Type: IEEE 1394 + Port Type: Firewire (IEEE P1394) + +Handle 0x0020, DMI type 9, 13 bytes +System Slot Information + Designation: ExpressCard Slot 1 + Type: x1 PCI Express + Current Usage: Available + Length: Other + ID: 0 + Characteristics: + Hot-plug devices are supported + +Handle 0x0021, DMI type 9, 13 bytes +System Slot Information + Designation: CardBus Slot 1 + Type: 32-bit PC Card (PCMCIA) + Current Usage: Available + Length: Other + ID: Adapter 1, Socket 0 + Characteristics: + 5.0 V is provided + 3.3 V is provided + PC Card-16 is supported + Cardbus is supported + Zoom Video is supported + Modem ring resume is supported + PME signal is supported + Hot-plug devices are supported + +Handle 0x0022, DMI type 126, 13 bytes +Inactive + +Handle 0x0023, DMI type 126, 13 bytes +Inactive + +Handle 0x0024, DMI type 126, 13 bytes +Inactive + +Handle 0x0025, DMI type 126, 13 bytes +Inactive + +Handle 0x0026, DMI type 126, 13 bytes +Inactive + +Handle 0x0027, DMI type 10, 6 bytes +On Board Device Information + Type: Other + Status: Disabled + Description: IBM Embedded Security hardware + +Handle 0x0028, DMI type 11, 5 bytes +OEM Strings + String 1: IBM ThinkPad Embedded Controller -[7VHT12WW-1.01 ]- + +Handle 0x0029, DMI type 13, 22 bytes +BIOS Language Information + Language Description Format: Abbreviated + Installable Languages: 1 + enUS + Currently Installed Language: enUS + +Handle 0x002A, DMI type 15, 25 bytes +System Event Log + Area Length: 0 bytes + Header Start Offset: 0x0000 + Header Length: 16 bytes + Data Start Offset: 0x0010 + Access Method: General-purpose non-volatile data functions + Access Address: 0x0000 + Status: Valid, Not Full + Change Token: 0x00000070 + Header Format: Type 1 + Supported Log Type Descriptors: 1 + Descriptor 1: POST error + Data Format 1: POST results bitmap + +Handle 0x002B, DMI type 16, 15 bytes +Physical Memory Array + Location: System Board Or Motherboard + Use: System Memory + Error Correction Type: None + Maximum Capacity: 4 GB + Error Information Handle: Not Provided + Number Of Devices: 2 + +Handle 0x002C, DMI type 17, 27 bytes +Memory Device + Array Handle: 0x002B + Error Information Handle: No Error + Total Width: 64 bits + Data Width: 64 bits + Size: 1024 MB + Form Factor: SODIMM + Set: None + Locator: DIMM 1 + Bank Locator: Bank 0/1 + Type: DDR2 + Type Detail: Synchronous + Speed: 667 MHz + Manufacturer: Not Specified + Serial Number: Not Specified + Asset Tag: Not Specified + Part Number: Not Specified + +Handle 0x002D, DMI type 17, 27 bytes +Memory Device + Array Handle: 0x002B + Error Information Handle: No Error + Total Width: 64 bits + Data Width: 64 bits + Size: 2048 MB + Form Factor: SODIMM + Set: None + Locator: DIMM 2 + Bank Locator: Bank 2/3 + Type: DDR2 + Type Detail: Synchronous + Speed: 667 MHz + Manufacturer: Not Specified + Serial Number: Not Specified + Asset Tag: Not Specified + Part Number: Not Specified + +Handle 0x002E, DMI type 18, 23 bytes +32-bit Memory Error Information + Type: OK + Granularity: Unknown + Operation: Unknown + Vendor Syndrome: Unknown + Memory Array Address: Unknown + Device Address: Unknown + Resolution: Unknown + +Handle 0x002F, DMI type 19, 15 bytes +Memory Array Mapped Address + Starting Address: 0x00000000000 + Ending Address: 0x000BFFFFFFF + Range Size: 3 GB + Physical Array Handle: 0x002B + Partition Width: 2 + +Handle 0x0030, DMI type 20, 19 bytes +Memory Device Mapped Address + Starting Address: 0x00000000000 + Ending Address: 0x0003FFFFFFF + Range Size: 1 GB + Physical Device Handle: 0x002C + Memory Array Mapped Address Handle: 0x002F + Partition Row Position: 1 + +Handle 0x0031, DMI type 20, 19 bytes +Memory Device Mapped Address + Starting Address: 0x00040000000 + Ending Address: 0x000BFFFFFFF + Range Size: 2 GB + Physical Device Handle: 0x002D + Memory Array Mapped Address Handle: 0x002F + Partition Row Position: 1 + +Handle 0x0032, DMI type 21, 7 bytes +Built-in Pointing Device + Type: Track Point + Interface: PS/2 + Buttons: 3 + +Handle 0x0033, DMI type 21, 7 bytes +Built-in Pointing Device + Type: Touch Pad + Interface: PS/2 + Buttons: 0 + +Handle 0x0034, DMI type 126, 26 bytes +Inactive + +Handle 0x0035, DMI type 126, 26 bytes +Inactive + +Handle 0x0036, DMI type 24, 5 bytes +Hardware Security + Power-On Password Status: Disabled + Keyboard Password Status: Disabled + Administrator Password Status: Disabled + Front Panel Reset Status: Unknown + +Handle 0x0037, DMI type 32, 11 bytes +System Boot Information + Status: No errors detected + +Handle 0x0038, DMI type 131, 17 bytes +OEM-specific Type + Header and Data: + 83 11 38 00 01 02 03 FF FF 1F 00 00 00 00 00 02 + 00 + Strings: + BOOTINF 20h + BOOTDEV 21h + KEYPTRS 23h + +Handle 0x0039, DMI type 131, 22 bytes +OEM-specific Type + Header and Data: + 83 16 39 00 01 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 01 + Strings: + TVT-Enablement + +Handle 0x003A, DMI type 132, 7 bytes +OEM-specific Type + Header and Data: + 84 07 3A 00 02 D8 36 + +Handle 0x003B, DMI type 133, 5 bytes +OEM-specific Type + Header and Data: + 85 05 3B 00 01 + Strings: + KHOIHGIUCCHHII + +Handle 0x003C, DMI type 134, 13 bytes +OEM-specific Type + Header and Data: + 86 0D 3C 00 05 02 09 20 00 00 00 00 00 + +Handle 0x003D, DMI type 134, 16 bytes +OEM-specific Type + Header and Data: + 86 10 3D 00 00 49 4E 54 43 01 01 00 00 02 01 02 + Strings: + TPM INFO + System Reserved + +Handle 0x003E, DMI type 135, 13 bytes +OEM-specific Type + Header and Data: + 87 0D 3E 00 54 50 07 00 01 00 00 00 00 + +Handle 0x003F, DMI type 135, 18 bytes +OEM-specific Type + Header and Data: + 87 12 3F 00 54 50 07 01 01 B8 00 00 00 00 00 00 + 00 00 + +Handle 0x0040, DMI type 135, 35 bytes +OEM-specific Type + Header and Data: + 87 23 40 00 54 50 07 02 42 41 59 20 49 2F 4F 20 + 01 00 02 00 00 0B 00 48 1C 3E 18 02 00 0B 00 40 + 1C 3A 18 + +Handle 0x0041, DMI type 135, 34 bytes +OEM-specific Type + Header and Data: + 87 22 41 00 54 50 07 04 01 06 01 01 02 00 02 01 + 02 00 03 01 02 00 04 01 02 00 05 01 02 00 06 01 + 02 00 + +Handle 0x0042, DMI type 136, 6 bytes +OEM-specific Type + Header and Data: + 88 06 42 00 5A 5A + +Handle 0x0043, DMI type 126, 28 bytes +Inactive + +Handle 0x0044, DMI type 138, 40 bytes +OEM-specific Type + Header and Data: + 8A 28 44 00 14 01 02 01 40 02 01 40 02 01 40 02 + 01 40 01 40 42 49 4F 53 20 50 61 73 73 77 6F 72 + 64 20 46 6F 72 6D 61 74 + +Handle 0x0045, DMI type 139, 37 bytes +OEM-specific Type + Header and Data: + 8B 25 45 00 11 01 0A 00 00 00 00 00 00 00 00 00 + 00 50 57 4D 53 20 4B 65 79 20 49 6E 66 6F 72 6D + 61 74 69 6F 6E + +Handle 0x0046, DMI type 129, 8 bytes +OEM-specific Type + Header and Data: + 81 08 46 00 01 01 02 01 + Strings: + Intel_ASF + Intel_ASF_001 + +Handle 0x0047, DMI type 130, 20 bytes +OEM-specific Type + Header and Data: + 82 14 47 00 24 41 4D 54 01 01 01 01 01 A5 0B 04 + 00 00 00 00 + +Handle 0x0048, DMI type 131, 64 bytes +OEM-specific Type + Header and Data: + 83 40 48 00 14 00 00 00 00 00 40 2A 00 00 00 00 + F8 00 17 29 00 00 00 00 0F 00 00 00 00 00 04 00 + 73 04 08 00 01 00 01 15 C8 00 F5 10 00 00 00 00 + 00 00 00 00 07 00 00 00 76 50 72 6F 00 00 00 00 + +Handle 0x0049, DMI type 127, 4 bytes +End Of Table + diff --git a/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/ectool.log b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/ectool.log new file mode 100644 index 00000000..11e5f963 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/ectool.log @@ -0,0 +1,19 @@ +EC RAM: + +00: a6 05 a0 40 fe 96 00 00 1f 02 47 00 00 00 80 00 +10: 00 00 ff ff f4 3c 87 09 5b ff 83 00 ff ff 2d 00 +20: 00 00 00 00 00 00 00 9f 00 00 00 00 00 00 00 80 +30: 07 00 02 00 30 04 00 00 00 00 30 10 00 50 00 00 +40: 00 00 00 00 00 00 14 00 42 01 00 00 00 00 00 00 +50: 00 c0 02 19 df 07 03 11 12 31 28 04 04 d0 07 f6 +60: 09 86 0b 7a 0d 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 12 30 80 24 23 20 80 80 80 80 80 +80: 00 00 00 06 79 07 03 00 00 00 00 00 00 00 6c 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 23 2a 27 80 80 80 80 80 11 41 00 06 00 00 00 00 +d0: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e0: 00 00 00 00 00 00 00 00 10 10 52 07 24 6e 55 03 +f0: 37 56 48 54 31 32 57 57 10 c2 48 fd 10 67 73 e5 + diff --git a/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/flashrom_info.log b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/flashrom_info.log new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/flashrom_info.log @@ -0,0 +1 @@ + diff --git a/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/flashrom_read.log b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/flashrom_read.log new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/flashrom_read.log @@ -0,0 +1 @@ + diff --git a/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/inteltool.log b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/inteltool.log new file mode 100644 index 00000000..c2c5a28a --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/inteltool.log @@ -0,0 +1,4406 @@ +CPU: ID 0x10676, Processor Type 0x0, Family 0x6, Model 0x17, Stepping 0x6 +Northbridge: 8086:2a40 (GL40/GS40/GM45/GS45/PM45) +Southbridge: 8086:2917 (ICH9M-E) + +============= GPIOS ============= + +GPIOBASE = 0x1180 (IO) + +gpiobase+0x0000: 0x197e23fe (GPIO_USE_SEL) +gpiobase+0x0004: 0xe0a26dfe (GP_IO_SEL) +gpiobase+0x0008: 0x00000000 (RESERVED) +gpiobase+0x000c: 0xe3feef3b (GP_LVL) +gpiobase+0x0010: 0x00000000 (RESERVED) +gpiobase+0x0014: 0x00000000 (RESERVED) +gpiobase+0x0018: 0x00000000 (GPO_BLINK) +gpiobase+0x001c: 0x00000000 (GP_SER_BLINK) +gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS) +gpiobase+0x0024: 0x00000000 (GP_SB_DATA) +gpiobase+0x0028: 0x00000000 (RESERVED) +gpiobase+0x002c: 0x00000102 (GPI_INV) +gpiobase+0x0030: 0x030306f6 (GPIO_USE_SEL2) +gpiobase+0x0034: 0x1f55f9f1 (GP_IO_SEL2) +gpiobase+0x0038: 0x1dfefb73 (GP_LVL2) +gpiobase+0x003c: 0x00000000 (RESERVED) + + + +============= RCBA ============== + +RCBA = 0xfed1c000 (MEM) + +0x0000: 0x10010002 +0x0004: 0x00000801 +0x0008: 0x00000001 +0x0010: 0x00000001 +0x0014: 0x80000001 +0x001c: 0x03128011 +0x0020: 0x81080080 +0x0030: 0x0000000f +0x0034: 0x000f0000 +0x003c: 0x000000f0 +0x0040: 0x0f000000 +0x0048: 0x0000f000 +0x0050: 0x0000000f +0x0054: 0x000f0000 +0x005c: 0x000000f0 +0x0060: 0x0f000000 +0x0068: 0x0000f000 +0x0088: 0x00109000 +0x0090: 0x00002000 +0x0094: 0x00002000 +0x0100: 0x1a010005 +0x0104: 0x00020802 +0x0110: 0x01010001 +0x0118: 0xfed18000 +0x0120: 0x01020003 +0x0128: 0x000e0000 +0x0130: 0x02020003 +0x0138: 0x000e1000 +0x0140: 0x03020002 +0x0148: 0x000e2000 +0x0150: 0x04020003 +0x0158: 0x000e3000 +0x0160: 0x0f020003 +0x0168: 0x000d8000 +0x0170: 0x05020003 +0x0178: 0x000e4000 +0x0180: 0x06020002 +0x0188: 0x000e5000 +0x01a0: 0x00010006 +0x01a4: 0x00012c41 +0x01a8: 0x00410003 +0x01f0: 0x00000001 +0x01f4: 0x86000040 +0x01fc: 0x0000060b +0x0200: 0x01102008 +0x0208: 0x04210044 +0x0210: 0x0000f710 +0x0220: 0x00000045 +0x0228: 0x04124aaa +0x0230: 0x00010000 +0x0234: 0x00000003 +0x0238: 0x00543210 +0x023c: 0x00000800 +0x0240: 0x00fa06a5 +0x0244: 0x000006bd +0x0248: 0x001f03e1 +0x024c: 0x000e0000 +0x0250: 0x00140000 +0x0254: 0x00150346 +0x0258: 0x00150543 +0x0260: 0x00210a4f +0x0268: 0x00030018 +0x0270: 0x00030000 +0x0274: 0x00040010 +0x0278: 0x00a20db6 +0x027c: 0x00a60dc6 +0x0280: 0x00e70000 +0x0284: 0x00ed0000 +0x0288: 0x00eb0092 +0x0f20: 0xb2b577cc +0x0f24: 0x000000c3 +0x0f28: 0x001fe000 +0x0f2c: 0x00101fff +0x0f30: 0x00000387 +0x1d3c: 0x0000007f +0x1d48: 0x00030000 +0x1e10: 0x00020800 +0x1e18: 0x814000bb +0x1e80: 0x000c0801 +0x1e84: 0x000200f0 +0x2010: 0x00080401 +0x2014: 0x14000016 +0x2018: 0xbc4abcb5 +0x2020: 0x00c9605b +0x2024: 0x0b203040 +0x2028: 0x04c8f5b2 +0x202c: 0x0af305b2 +0x2030: 0x00004454 +0x2034: 0xb2b577cc +0x2044: 0x000000c3 +0x204c: 0x001fe000 +0x2050: 0x00101fff +0x2054: 0x00000380 +0x2060: 0x81000000 +0x2080: 0x18206006 +0x2088: 0x00000260 +0x208c: 0x0006000c +0x2090: 0x32000000 +0x20a0: 0x18206006 +0x20a8: 0x00000260 +0x20ac: 0x0006000c +0x20b0: 0x09000000 +0x20c0: 0x18206006 +0x20c8: 0x00000260 +0x20cc: 0x0006000c +0x20d0: 0x09000000 +0x20e0: 0x18206006 +0x20e8: 0x00000260 +0x20ec: 0x0006000c +0x20f0: 0x06000000 +0x3100: 0x04341200 +0x3108: 0x40004321 +0x310c: 0x00014321 +0x3110: 0x00000002 +0x3114: 0x40000321 +0x3118: 0x00000001 +0x3140: 0x00003107 +0x3144: 0x76543210 +0x3148: 0x00000010 +0x314c: 0x00007654 +0x3150: 0x00000004 +0x31fc: 0x03000000 +0x3400: 0x0000001c +0x3404: 0x00000080 +0x3410: 0x00000461 +0x3418: 0x03240001 +0x341c: 0xbf4f001f +0x3430: 0x00000001 +0x3500: 0x0fff0fff +0x3504: 0x1b6db6db +0x3508: 0x0000001b +0x350c: 0x08000020 +0x3510: 0x09008fb8 +0x3528: 0x17001f9f +0x352c: 0x000bc008 +0x3530: 0x1800ff4f +0x3800: 0x07ff0600 +0x3804: 0x3f04e008 +0x3808: 0x0060efc0 +0x384c: 0xb5000000 +0x3850: 0x00001a1b +0x3858: 0x07ff0600 +0x385c: 0x05f50001 +0x3860: 0x05f705f6 +0x3864: 0x05ff05f8 +0x3874: 0x9fff07e0 +0x3884: 0x85ff85f8 +0x3890: 0x00400000 +0x3894: 0x143b5006 +0x3898: 0x05200302 +0x389c: 0x0601209f +0x38b0: 0x00000004 +0x38b4: 0x04040001 +0x38c0: 0x00000007 +0x38c4: 0x00002005 +0x38c8: 0x00002005 +0x3e00: 0xffffffff +0x3e04: 0xffffffff +0x3e08: 0xffffffff +0x3e0c: 0xffffffff +0x3e10: 0xffffffff +0x3e14: 0xffffffff +0x3e18: 0xffffffff +0x3e1c: 0xffffffff +0x3e20: 0xffffffff +0x3e24: 0xffffffff +0x3e28: 0xffffffff +0x3e2c: 0xffffffff +0x3e30: 0xffffffff +0x3e34: 0xffffffff +0x3e38: 0xffffffff +0x3e3c: 0xffffffff +0x3e40: 0xffffffff +0x3e44: 0xffffffff +0x3e48: 0xffffffff +0x3e4c: 0xffffffff +0x3e50: 0xffffffff +0x3e54: 0xffffffff +0x3e58: 0xffffffff +0x3e5c: 0xffffffff +0x3e60: 0xffffffff +0x3e64: 0xffffffff +0x3e68: 0xffffffff +0x3e6c: 0xffffffff +0x3e70: 0xffffffff +0x3e74: 0xffffffff +0x3e78: 0xffffffff +0x3e7c: 0xffffffff +0x3f00: 0x0000000b + + + +============= PMBASE ============ + +PMBASE = 0x1000 (IO) + +pmbase+0x0000: 0x0001 (PM1_STS) +pmbase+0x0002: 0x0120 (PM1_EN) +pmbase+0x0004: 0x00001c03 (PM1_CNT) +pmbase+0x0008: 0x005bb14c (PM1_TMR) +pmbase+0x000c: 0x00000000 (RESERVED) +pmbase+0x0010: 0x00000080 (PROC_CNT) +pmbase+0x0019: 0x00 (RESERVED) +pmbase+0x001a: 0x0000 (RESERVED) +pmbase+0x001c: 0x20000000 (RESERVED) +pmbase+0x0020: 0x6c380000 (GPE0_STS) + 0x00000000 +pmbase+0x0028: 0x01020046 (GPE0_EN) + 0x00000000 +pmbase+0x0030: 0x00062033 (SMI_EN) +pmbase+0x0034: 0x00004900 (SMI_STS) +pmbase+0x0038: 0x0000 (ALT_GP_SMI_EN) +pmbase+0x003a: 0x6c3a (ALT_GP_SMI_STS) +pmbase+0x003c: 0x00 (UPRWC) +pmbase+0x003d: 0x0000 (RESERVED) +pmbase+0x003f: 0x00 (RESERVED) +pmbase+0x0040: 0x0000 (RESERVED) +pmbase+0x0042: 0x00 (GPE_CNTL) +pmbase+0x0043: 0x00 (RESERVED) +pmbase+0x0044: 0x12a0 (DEVACT_STS) +pmbase+0x0046: 0x0000 (RESERVED) +pmbase+0x0048: 0x00000000 (RESERVED) +pmbase+0x004c: 0x00000000 (RESERVED) +pmbase+0x0050: 0x00 (PM2_CNT (Mobile)) +pmbase+0x0051: 0x00 (RESERVED) +pmbase+0x0052: 0x0000 (RESERVED) +pmbase+0x0054: 0x0099c5b8 (C3_RES (Mobile)) +pmbase+0x0058: 0x00000000 (C5_RES (Mobile)) +pmbase+0x005c: 0x00000000 (RESERVED) +pmbase+0x0060: 0x0004 (TCO_RLD) +pmbase+0x0062: 0x00 (TCO_DAT_IN) +pmbase+0x0063: 0x00 (TCO_DAT_OUT) +pmbase+0x0064: 0x0000 (TCO1_STS) +pmbase+0x0066: 0x0000 (TCO2_STS) +pmbase+0x0068: 0x0800 (TCO1_CNT) +pmbase+0x006a: 0x0008 (TCO2_CNT) +pmbase+0x006c: 0x0000 (TCO_MESSAGE) +pmbase+0x006e: 0x00 (TCO_WDCNT) +pmbase+0x006f: 0x00 (RESERVED) +pmbase+0x0070: 0x03 (SW_IRQ_GEN) +pmbase+0x0071: 0x00 (RESERVED) +pmbase+0x0072: 0x03ff (TCO_TMR) +pmbase+0x0074: 0x00000000 (RESERVED) +pmbase+0x0078: 0x00000000 (RESERVED) +pmbase+0x007c: 0x00000000 (RESERVED) + + + +============= MCHBAR ============ + +MCHBAR = 0xfed10000 (MEM) + +0x0034: 0x00000002 +0x0040: 0x00202200 +0x0044: 0xc6200032 +0x0048: 0x808002a8 +0x004c: 0x00100000 +0x0050: 0x00800001 +0x0054: 0x00800102 +0x0070: 0x12200009 +0x0074: 0x17000200 +0x0090: 0x00005054 +0x0094: 0x20210880 +0x00a4: 0x00d00000 +0x00b0: 0x00d00000 +0x00bc: 0x00d00000 +0x00d0: 0x00000002 +0x00f4: 0x01804000 +0x0200: 0x000f0002 +0x0204: 0x00000010 +0x0208: 0x00810060 +0x020c: 0x00180006 +0x0218: 0x86008400 +0x0220: 0x00210264 +0x0224: 0x00000300 +0x0228: 0x30000000 +0x0230: 0x34028000 +0x0234: 0x00000009 +0x0238: 0x04bdb600 +0x023c: 0x003db600 +0x0240: 0xa8000000 +0x0400: 0x000e0022 +0x0404: 0x00002202 +0x040c: 0x0f800100 +0x0410: 0x2186a000 +0x041c: 0x22222099 +0x0420: 0x0000002d +0x0424: 0x0000002d +0x0428: 0x00000050 +0x042c: 0x00000050 +0x04d0: 0x28a00012 +0x0518: 0x21250a0a +0x0530: 0x0a080005 +0x0680: 0x08080f0e +0x0684: 0x08080808 +0x0688: 0x09090808 +0x068c: 0x0d0c0b0a +0x0698: 0x100e0d0c +0x069c: 0x08080812 +0x06a0: 0x09090808 +0x06a4: 0x0b0b0a0a +0x06b0: 0x1c000055 +0x06b4: 0x00000019 +0x06c0: 0x03030303 +0x06c4: 0x04040404 +0x06c8: 0x03030505 +0x06cc: 0x03030303 +0x06d8: 0x03030303 +0x06dc: 0x04040403 +0x06e0: 0x05050504 +0x06e4: 0x03030305 +0x06f0: 0x24000066 +0x06f4: 0x00000021 +0x0700: 0x08080808 +0x0704: 0x09090909 +0x0708: 0x08080a0a +0x070c: 0x08080808 +0x0718: 0x08080808 +0x071c: 0x09090909 +0x0720: 0x0a0a0a0a +0x0724: 0x0808080a +0x0730: 0x24000066 +0x0734: 0x00000021 +0x073c: 0x80000000 +0x0740: 0x08080808 +0x0744: 0x09090909 +0x0748: 0x08080a0a +0x074c: 0x08080808 +0x0758: 0x08080808 +0x075c: 0x09090909 +0x0760: 0x0a0a0a0a +0x0764: 0x0808080a +0x0770: 0x24000066 +0x0774: 0x00000021 +0x077c: 0x80000000 +0x0780: 0x0a090909 +0x0784: 0x0c0b0b0a +0x0788: 0x06060d0c +0x078c: 0x09080707 +0x0798: 0x0a090808 +0x079c: 0x0c0b0b0a +0x07a0: 0x0e0d0d0c +0x07a4: 0x0707060e +0x07b0: 0x24000066 +0x07b4: 0x00000021 +0x07c0: 0x0a090909 +0x07c4: 0x0c0b0b0a +0x07c8: 0x06060d0c +0x07cc: 0x09080707 +0x07d8: 0x0a090808 +0x07dc: 0x0c0b0b0a +0x07e0: 0x0e0d0d0c +0x07e4: 0x0707060e +0x07f0: 0x24000066 +0x07f4: 0x00000021 +0x0840: 0x08080f0e +0x0844: 0x08080808 +0x0848: 0x09090808 +0x084c: 0x0d0c0b0a +0x0858: 0x100e0d0c +0x085c: 0x08080812 +0x0860: 0x09090808 +0x0864: 0x0b0b0a0a +0x0870: 0x1c000055 +0x0874: 0x00000019 +0x0880: 0x03030303 +0x0884: 0x04040404 +0x0888: 0x03030505 +0x088c: 0x03030303 +0x0898: 0x03030303 +0x089c: 0x04040403 +0x08a0: 0x05050504 +0x08a4: 0x03030305 +0x08b0: 0x24000066 +0x08b4: 0x00000021 +0x08c0: 0x00003731 +0x08c4: 0x00000807 +0x08c8: 0x00001f1f +0x0a00: 0x00100008 +0x0a04: 0x00100010 +0x0a08: 0x00008787 +0x0a28: 0xe0000000 +0x0a2c: 0x03100000 +0x0a34: 0x00200020 +0x0a38: 0x00200020 +0x0a3c: 0x00000088 +0x0a5c: 0x00000190 +0x0ac0: 0x0000010f +0x0ae4: 0x00001111 +0x0aec: 0x00000201 +0x0b00: 0x01400182 +0x0b28: 0x0186a000 +0x0b2c: 0x192d172b +0x0b30: 0x0e0c0e0c +0x0b34: 0x0e0c192d +0x0b38: 0x0e0c1901 +0x0b3c: 0x0c020807 +0x0b40: 0x04030201 +0x0b44: 0x08070605 +0x0b48: 0x110f0c09 +0x0b4c: 0x1a171513 +0x0b50: 0x2723201d +0x0b54: 0x312f2d2a +0x0b58: 0x3a383633 +0x0b5c: 0x3f3f3e3c +0x0b60: 0x04040302 +0x0b64: 0x08070605 +0x0b68: 0x120e0b09 +0x0b6c: 0x211d1815 +0x0b70: 0x2b292724 +0x0b74: 0x31302f2d +0x0b78: 0x39373533 +0x0b7c: 0x3f3d3b3a +0x0b84: 0x000acbab +0x0b88: 0x0045030e +0x0b8c: 0x00222222 +0x0b90: 0x00800080 +0x0b94: 0x0e1f272b +0x0b9c: 0x00000008 +0x0ba0: 0x00000008 +0x0ba4: 0x00000008 +0x0ba8: 0x00000008 +0x0bac: 0x0e1f0e1f +0x0bb0: 0x14000000 +0x0bbc: 0x0f000000 +0x0bc8: 0x00200000 +0x0bcc: 0x59470000 +0x0bd0: 0x5a222200 +0x0bd4: 0x0024005a +0x0bd8: 0x0000000c +0x0be0: 0x1b6decf3 +0x0be4: 0x367b6db6 +0x0c00: 0x00644066 +0x0c04: 0x01010101 +0x0c08: 0x00008000 +0x0c14: 0x30950002 +0x0c1c: 0x00000006 +0x0c34: 0x00008000 +0x0c38: 0x17771777 +0x0c48: 0x3f000000 +0x0c50: 0x01010101 +0x0c60: 0x80000000 +0x0c64: 0x00004080 +0x0e10: 0x003d0098 +0x0e14: 0x00000004 +0x0e50: 0x00f003c0 +0x0e54: 0x000f03c0 +0x0e58: 0x00ff03c0 +0x0e5c: 0x3c0f03c0 +0x0e60: 0x3c0003c0 +0x0e70: 0x000000b9 +0x0e74: 0xd0000000 +0x0e78: 0x0218a0a8 +0x0e7c: 0x00470a04 +0x0e80: 0x16002b90 +0x0e84: 0x80774f8f +0x0e88: 0x810000da +0x0e8c: 0x00002080 +0x0ea8: 0x00c80000 +0x0eac: 0x00002000 +0x0eb0: 0x00010000 +0x0ee8: 0x00390000 +0x0f00: 0x00000900 +0x0f04: 0x00002e80 +0x0f08: 0x0000730f +0x0f0c: 0x000010a4 +0x0f10: 0x000000a2 +0x0f14: 0x00000002 +0x0f20: 0x20000000 +0x0f60: 0x01030419 +0x0f80: 0x80000000 +0x0fb0: 0x00000003 +0x0fb8: 0x00000003 +0x0fc0: 0x061f08fd +0x0ffc: 0x0000c7c0 +0x1000: 0x0093007f +0x1004: 0x00ff0000 +0x1008: 0x000000ff +0x1010: 0x80000009 +0x1018: 0x00000085 +0x101c: 0x00008598 +0x1040: 0x0001007f +0x1044: 0x00ff0000 +0x1048: 0x000000ff +0x1050: 0x80000000 +0x1058: 0x00000080 +0x105c: 0x00008099 +0x1070: 0x00000001 +0x1080: 0x00000006 +0x10e0: 0x01010101 +0x1100: 0x00000300 +0x1110: 0x17cd17ac +0x1114: 0x179b178a +0x1118: 0x17891778 +0x111c: 0x17671756 +0x1120: 0x10111213 +0x1124: 0x14151617 +0x1128: 0x18191a1b +0x112c: 0x1c1d1e1f +0x1130: 0x00010203 +0x1134: 0x04050607 +0x1138: 0x08090a0b +0x113c: 0x0c0d0e0f +0x1190: 0x00000007 +0x119c: 0xa8000000 +0x11b8: 0x4000333c +0x11c0: 0x03030100 +0x11c4: 0x0a030a03 +0x11c8: 0x00000020 +0x11cc: 0x00000017 +0x1200: 0x00200010 +0x1204: 0x00200020 +0x1208: 0x00090033 +0x120c: 0x00000003 +0x1210: 0x48e18c61 +0x1214: 0x128090a5 +0x1218: 0x22363313 +0x121c: 0x320d0384 +0x1220: 0x68ba6035 +0x1224: 0x83435a64 +0x1228: 0x066a6804 +0x122c: 0x00000002 +0x1230: 0x43000208 +0x1234: 0x910c1800 +0x1238: 0x0c001001 +0x1248: 0x20802025 +0x124c: 0x60a47687 +0x1250: 0x000006c4 +0x1254: 0x871a066d +0x1258: 0x40100401 +0x1260: 0x0000000b +0x1264: 0x00982022 +0x1268: 0x00000006 +0x1274: 0x80000000 +0x12a0: 0x0000000a +0x12a4: 0x00000020 +0x1300: 0x00400040 +0x1304: 0x00400040 +0x1308: 0x00090003 +0x130c: 0x00000003 +0x1310: 0x48e18c61 +0x1314: 0x128090a5 +0x1318: 0x22363313 +0x131c: 0x320d0384 +0x1320: 0x68ba6035 +0x1324: 0x83435a64 +0x1328: 0x066a6804 +0x132c: 0x00000002 +0x1330: 0x41000208 +0x1334: 0xb10e1800 +0x1338: 0x0e001001 +0x1348: 0x20802025 +0x134c: 0x60a47687 +0x1350: 0x000006c4 +0x1354: 0x871a066d +0x1358: 0x40100401 +0x1360: 0x0000000b +0x1364: 0x00982022 +0x1368: 0x00000006 +0x1374: 0x80000000 +0x13a0: 0x0000000a +0x13a4: 0x00000020 +0x1400: 0x00113300 +0x1408: 0x3ffffeff +0x140c: 0x80010880 +0x1410: 0x40002040 +0x1414: 0x24049800 +0x1420: 0x2222aa22 +0x1428: 0x00555801 +0x142c: 0x05330407 +0x1430: 0x00000300 +0x1434: 0x80000243 +0x1440: 0x00000044 +0x1444: 0x02000000 +0x1450: 0x0000000a +0x1470: 0x7528060f +0x1474: 0x252b8008 +0x1478: 0x142b7408 +0x147c: 0xa7254708 +0x1490: 0x00e70067 +0x1494: 0x000d8000 +0x14a0: 0x66030003 +0x14a4: 0x50020002 +0x14a8: 0x24010001 +0x14ac: 0x23000000 +0x14b0: 0x0e361800 +0x14b4: 0x0e421800 +0x14b8: 0x0e451000 +0x14bc: 0x0e511000 +0x14c0: 0x0e560800 +0x14c4: 0x0e440800 +0x14c8: 0x0e450000 +0x14cc: 0x0e530000 +0x14e0: 0x55500000 +0x14f0: 0x00000600 +0x1570: 0x00840008 +0x1574: 0x00840008 +0x1578: 0x00840008 +0x157c: 0x008b0008 +0x1590: 0x00e70067 +0x1594: 0x000d8000 +0x15a0: 0x57030003 +0x15a4: 0x44020002 +0x15a8: 0x22010001 +0x15ac: 0x07000000 +0x15b0: 0x8e431800 +0x15b4: 0x8e401800 +0x15b8: 0x8e431000 +0x15bc: 0x8e511000 +0x15c0: 0x8e400800 +0x15c4: 0x8e340800 +0x15c8: 0x8e440000 +0x15cc: 0x0e500000 +0x15e0: 0x55500000 +0x15f0: 0x00000600 +0x16cc: 0x000000ff +0x16d4: 0x00000400 + + + +============= EPBAR ============= + +EPBAR = 0xfed19000 (MEM) + +0x0000: 0x04010002 +0x0004: 0x00000401 +0x0008: 0x00000001 +0x0010: 0x00000001 +0x0014: 0x80000001 +0x001c: 0x100a8010 +0x0020: 0x81080080 +0x0028: 0x0a0a0a0a +0x002c: 0x0000001a +0x0038: 0x01380138 +0x003c: 0x01380138 +0x0040: 0x00010005 +0x0044: 0x00010201 +0x0050: 0x01010001 +0x0058: 0xfed18000 +0x0060: 0x02000002 +0x0068: 0x00008000 +0x0100: 0x55555555 +0x0104: 0x55555555 +0x0108: 0x55555555 +0x010c: 0x55555555 +0x0110: 0x55555555 +0x0114: 0x55555555 +0x0118: 0x55555555 +0x011c: 0x00005555 + + + +============= DMIBAR ============ + +DMIBAR = 0xfed18000 (MEM) + +0x0000: 0x04010002 +0x0004: 0x00000001 +0x0008: 0x00000001 +0x0010: 0x00000001 +0x0014: 0x80000001 +0x001c: 0x00008001 +0x0020: 0x81000080 +0x0028: 0x00000001 +0x002c: 0x86000040 +0x0040: 0x08010005 +0x0044: 0x01010202 +0x0050: 0x00020001 +0x0058: 0xfed1c000 +0x0060: 0x00010001 +0x0068: 0xfed19000 +0x0080: 0x00010006 +0x0084: 0x00012c41 +0x0088: 0x00410003 +0x00f0: 0x03010000 +0x00f4: 0x00000005 +0x00fc: 0x00000013 +0x01cc: 0x00060010 +0x01d4: 0x00002000 +0x0200: 0x08006f24 +0x0204: 0x0000b13f +0x0208: 0x00007cb0 +0x0210: 0x00000100 +0x0214: 0x0008000f +0x0218: 0x0f960426 +0x021c: 0x04270427 +0x0224: 0x00030007 +0x0230: 0x1400000c +0x0234: 0xbc4abcb5 +0x0300: 0x001e03da +0x0304: 0x002003e2 +0x0308: 0x00060018 +0x030c: 0x00c50345 +0x0310: 0x00c60346 +0x0314: 0x00060000 +0x0318: 0x00190a2f +0x031c: 0x00210a4f +0x0324: 0x00030018 +0x0328: 0x00030000 +0x0334: 0x00040010 +0x0338: 0x00060000 +0x0e00: 0x000001fe +0x0e08: 0x000000c5 +0x0e0c: 0x000000c1 +0x0e10: 0x00000010 +0x0e18: 0x0000000f +0x0e1c: 0x00000001 +0x0e20: 0x0000000f +0x0e24: 0x0000000d +0x0e28: 0x3a588887 +0x0e2c: 0x88d07333 +0x0e30: 0x00009000 +0x0f00: 0x0000033c +0x0f04: 0x07050880 +0x0f08: 0x00100052 +0x0f10: 0x00010012 +0x0f14: 0x30400000 +0x0f20: 0x3c000757 +0x0f24: 0x00000100 +0x0f30: 0x0e350c08 +0x0f34: 0x000a0000 +0x0f44: 0x07050880 +0x0f48: 0x00100052 +0x0f50: 0x00010012 +0x0f54: 0x30400000 +0x0f60: 0x3c000757 +0x0f64: 0x00000100 +0x0f70: 0x0e3c0808 +0x0f74: 0x000a0000 +0x0f80: 0x0000033c +0x0f84: 0x07050880 +0x0f88: 0x00100052 +0x0f90: 0x00010012 +0x0f94: 0x30400000 +0x0fa0: 0x3c000757 +0x0fa4: 0x00000100 +0x0fb0: 0x0e3a0808 +0x0fb4: 0x000a0000 +0x0fc4: 0x07050880 +0x0fc8: 0x00100052 +0x0fd0: 0x00010012 +0x0fd4: 0x30400000 +0x0fe0: 0x3c000757 +0x0fe4: 0x00000100 +0x0ff0: 0x0e340008 +0x0ff4: 0x000a0000 + + +========= PCIEXBAR ======== + +PCIEXBAR: 0xe0000000 + +PCIe 00:00.0 extended config space: +0000: 86 80 40 2a 06 01 90 20 07 00 00 06 00 00 00 00 +0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0020: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 e0 20 +0030: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +0040: 01 90 d1 fe 00 00 00 00 01 00 d1 fe 00 00 00 00 +0050: 00 00 50 03 59 03 00 00 00 00 00 00 00 00 00 00 +0060: 01 00 00 e0 00 00 00 00 01 80 d1 fe 00 00 00 00 +0070: 01 00 60 bf 00 00 00 00 01 10 00 00 00 00 00 00 +0080: 00 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + + +Error: Dumping MSRs on this CPU (0x010670) is not (yet) supported. + + + +============= AMBs ============ + + +============= SPI / BIOS CNTL ============= + +Error: Dumping SPI on this southbridge is not (yet) supported. diff --git a/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/lspci.log b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/lspci.log new file mode 100644 index 00000000..3c5fecfc --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/logs-t400-bios2.02-ec1.01/lspci.log @@ -0,0 +1,2696 @@ +00:00.0 Host bridge [0600]: Intel Corporation Mobile 4 Series Chipset Memory Controller Hub [8086:2a40] (rev 07) + Subsystem: Lenovo Device [17aa:20e0] + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- + Kernel driver in use: agpgart-intel +00: 86 80 40 2a 06 01 90 20 07 00 00 06 00 00 00 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 e0 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 90 d1 fe 00 00 00 00 01 00 d1 fe 00 00 00 00 +50: 00 00 50 03 59 03 00 00 00 00 00 00 00 00 00 00 +60: 01 00 00 e0 00 00 00 00 01 80 d1 fe 00 00 00 00 +70: 01 00 60 bf 00 00 00 00 01 10 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 10 11 11 01 30 11 11 00 ff 03 00 00 00 1a 3b 00 +a0: 18 00 f0 0b 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 bf 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 30 02 00 00 +e0: 09 00 0a 11 88 64 00 1c 01 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 + +00:02.0 VGA compatible controller [0300]: Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a42] (rev 07) (prog-if 00 [VGA controller]) + Subsystem: Lenovo Device [17aa:20e4] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- [disabled] + Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 4162 + Capabilities: [d0] Power Management version 3 + Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Kernel driver in use: i915 +00: 86 80 42 2a 07 04 90 00 07 00 00 03 00 00 80 00 +10: 04 00 40 f4 00 00 00 00 0c 00 00 d0 00 00 00 00 +20: 01 18 00 00 00 00 00 00 00 00 00 00 aa 17 e4 20 +30: 00 00 00 00 90 00 00 00 00 00 00 00 0b 01 00 00 +40: 00 00 00 00 48 00 00 00 09 00 0a 11 88 64 00 1c +50: 01 00 50 03 19 00 00 00 00 00 00 00 00 00 00 bd +60: 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 05 d0 01 00 0c 30 e0 fe 62 41 00 00 00 00 00 00 +a0: 00 00 00 00 09 00 06 20 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 40 01 00 00 +d0: 01 00 23 00 00 00 00 00 00 00 00 00 34 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 80 00 1a 41 20 00 00 +f0: 0d 1c 34 07 ff 00 00 00 a0 0f 07 00 13 b2 b8 bc + +00:02.1 Display controller [0380]: Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a43] (rev 07) + Subsystem: Lenovo Device [17aa:20e4] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #0, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- + Changed: MRL- PresDet- LinkState- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41c1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=01 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c000 + Kernel driver in use: pcieport +00: 86 80 40 29 07 05 10 00 03 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 02 02 00 80 80 00 20 +20: 00 bf 10 bf 21 bf 31 bf 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 04 00 +40: 10 80 41 01 00 80 00 00 00 00 10 00 11 4c 11 01 +50: 00 00 01 10 e0 a0 00 00 38 00 00 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe c1 41 00 00 00 00 00 00 +90: 0d a0 00 00 aa 17 f3 20 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 11 08 00 00 00 00 +e0: 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00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:1c.1 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 2 [8086:2942] (rev 03) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <256ns, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #1, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- + Changed: MRL- PresDet- LinkState+ + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41d1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=02 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c000 + Kernel driver in use: pcieport +00: 86 80 42 29 07 05 10 00 03 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 03 03 00 90 90 00 20 +20: 30 f4 30 f4 41 bf 51 bf 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 02 04 00 +40: 10 80 41 01 00 80 00 00 00 00 10 00 11 2c 11 02 +50: 40 00 11 30 e0 a0 08 00 38 00 40 01 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 +f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:1c.3 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 4 [8086:2946] (rev 03) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #3, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- + Changed: MRL- PresDet- LinkState- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41e1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=04 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c000 + Kernel driver in use: pcieport +00: 86 80 46 29 07 05 10 00 03 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 05 0c 00 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00 00 00 00 00 00 00 00 00 +f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:1c.4 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 5 [8086:2948] (rev 03) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #5, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #4, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- + Changed: MRL- PresDet- LinkState- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 4122 + Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=05 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c000 + Kernel driver in use: pcieport +00: 86 80 48 29 07 05 10 00 03 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 0d 14 00 30 30 00 20 +20: 00 fa f0 fb 11 f4 11 f4 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 04 00 +40: 10 80 41 01 00 80 00 00 00 00 10 00 11 4c 11 05 +50: 03 00 01 10 e0 a0 20 00 38 00 00 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +90: 0d a0 00 00 aa 17 f3 20 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 11 48 00 00 00 00 +e0: 00 0f c7 00 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00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:1d.0 USB controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934] (rev 03) (prog-if 00 [UHCI]) + Subsystem: Lenovo Device [17aa:20f0] + Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [50] Subsystem: Lenovo Device [17aa:20f4] +00: 86 80 48 24 07 01 10 00 93 01 04 06 00 00 01 00 +10: 00 00 00 00 00 00 00 00 00 15 18 20 40 70 80 22 +20: 80 f4 f0 f7 01 f0 f1 f3 00 00 00 00 00 00 00 00 +30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 04 00 +40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00 +50: 0d 00 00 00 aa 17 f4 20 00 00 00 00 00 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 03 00 00 00 00 00 + +00:1f.0 ISA bridge [0601]: Intel Corporation ICH9M-E LPC Interface Controller [8086:2917] (rev 03) + Subsystem: Lenovo Device [17aa:20f5] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- + Kernel driver in use: lpc_ich +00: 86 80 17 29 07 00 10 02 03 00 01 06 00 00 80 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 f5 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 10 00 00 80 00 00 00 81 11 00 00 10 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 8b 8b 8b 8b 90 00 00 00 8b 8b 8b 8b f8 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 10 02 0e 3f 01 16 7c 00 e1 15 0c 00 81 16 1c 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 24 0a 00 00 39 00 80 00 2b 1c 0a 00 00 03 00 c0 +b0: 00 00 f0 00 00 00 00 00 08 00 02 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 67 45 00 00 00 ff 00 00 00 00 00 00 +e0: 09 00 0c 10 00 02 c4 03 04 00 00 00 00 00 00 00 +f0: 01 c0 d1 fe 00 00 00 00 86 0f 03 00 00 00 00 00 + +00:1f.2 SATA controller [0106]: Intel Corporation 82801IBM/IEM (ICH9M/ICH9M-E) 4 port SATA Controller [AHCI mode] [8086:2929] (rev 03) (prog-if 01 [AHCI 1.0]) + Subsystem: Lenovo Device [17aa:20f8] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- Reset- 16bInt+ PostWrite+ + 16-bit legacy interface ports at 0001 + Capabilities: [dc] Power Management version 2 + Flags: PMEClk+ DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME- + Bridge: PM- B3+ + Kernel driver in use: yenta_cardbus +00: 80 11 76 04 07 00 10 02 ba 00 07 06 00 a8 82 00 +10: 00 00 80 f4 dc 00 00 02 15 16 17 b0 00 00 00 f0 +20: 00 f0 ff f3 00 00 00 c0 00 f0 ff c3 00 40 00 00 +30: fc 40 00 00 00 44 00 00 fc 44 00 00 0b 01 80 05 +40: aa 17 c6 20 01 00 00 00 00 00 00 00 00 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 01 00 a0 04 00 03 00 00 63 04 63 04 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 01 00 00 f0 00 05 00 00 00 +b0: 00 00 00 00 00 00 00 fa 00 30 00 00 00 00 00 00 +c0: aa 17 c6 20 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 0a fe +e0: 00 40 c0 24 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +15:00.1 FireWire (IEEE 1394) [0c00]: Ricoh Co Ltd R5C832 IEEE 1394 Controller [1180:0832] (rev 04) (prog-if 10 [OHCI]) + Subsystem: Lenovo ThinkPad R61 [17aa:20c7] + Physical Slot: 1 + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- reserved +[ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable +[ 0.000000] No AGP bridge found +[ 0.000000] e820: last_pfn = 0x7f6d5 max_arch_pfn = 0x400000000 +[ 0.000000] MTRR default type: uncachable +[ 0.000000] MTRR fixed ranges enabled: +[ 0.000000] 00000-9FFFF write-back +[ 0.000000] A0000-BFFFF uncachable +[ 0.000000] C0000-FFFFF write-back +[ 0.000000] MTRR variable ranges enabled: +[ 0.000000] 0 base 000000000 mask F80000000 write-back +[ 0.000000] 1 base 07F800000 mask FFF800000 uncachable +[ 0.000000] 2 base 0D0000000 mask FF0000000 write-combining +[ 0.000000] 3 disabled +[ 0.000000] 4 disabled +[ 0.000000] 5 disabled +[ 0.000000] 6 disabled +[ 0.000000] 7 disabled +[ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 +[ 0.000000] found SMP MP-table at [mem 0x000f0400-0x000f040f] mapped at [ffff8800000f0400] +[ 0.000000] Scanning 1 areas for low memory corruption +[ 0.000000] Base memory trampoline at [ffff880000099000] 99000 size 24576 +[ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff] +[ 0.000000] [mem 0x00000000-0x000fffff] page 4k +[ 0.000000] BRK [0x01fe0000, 0x01fe0fff] PGTABLE +[ 0.000000] BRK [0x01fe1000, 0x01fe1fff] PGTABLE +[ 0.000000] BRK [0x01fe2000, 0x01fe2fff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0x7f400000-0x7f5fffff] +[ 0.000000] [mem 0x7f400000-0x7f5fffff] page 2M +[ 0.000000] BRK [0x01fe3000, 0x01fe3fff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0x7c000000-0x7f3fffff] +[ 0.000000] [mem 0x7c000000-0x7f3fffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0x00100000-0x7bffffff] +[ 0.000000] [mem 0x00100000-0x001fffff] page 4k +[ 0.000000] [mem 0x00200000-0x7bffffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0x7f600000-0x7f6d4fff] +[ 0.000000] [mem 0x7f600000-0x7f6d4fff] page 4k +[ 0.000000] BRK [0x01fe4000, 0x01fe4fff] PGTABLE +[ 0.000000] RAMDISK: [mem 0x35122000-0x36888fff] +[ 0.000000] ACPI: RSDP 00000000000f0800 000024 (v02 CORE ) +[ 0.000000] ACPI: XSDT 000000007f7de0e0 00004C (v01 CORE COREBOOT 00000000 CORE 00000000) +[ 0.000000] ACPI: HPET 000000007f7de210 000038 (v01 CORE COREBOOT 00000000 CORE 00000000) +[ 0.000000] ACPI: APIC 000000007f7de250 000068 (v01 CORE COREBOOT 00000000 CORE 00000000) +[ 0.000000] ACPI: MCFG 000000007f7de2c0 00003C (v01 CORE COREBOOT 00000000 CORE 00000000) +[ 0.000000] ACPI: FACP 000000007f7e15c0 0000F4 (v03 CORE COREBOOT 00000000 CORE 00000000) +[ 0.000000] ACPI: DSDT 000000007f7de340 003171 (v03 COREv4 COREBOOT 20090419 INTL 20140114) +[ 0.000000] ACPI: FACS 000000007f7de300 000040 +[ 0.000000] ACPI: SSDT 000000007f7e16c0 000306 (v02 CORE COREBOOT 0000002A CORE 0000002A) +[ 0.000000] ACPI: Local APIC address 0xfee00000 +[ 0.000000] No NUMA configuration found +[ 0.000000] Faking a node at [mem 0x0000000000000000-0x000000007f6d4fff] +[ 0.000000] Initmem setup node 0 [mem 0x00000000-0x7f6d4fff] +[ 0.000000] NODE_DATA [mem 0x7f6d0000-0x7f6d4fff] +[ 0.000000] [ffffea0000000000-ffffea0001ffffff] PMD -> [ffff88007ce00000-ffff88007edfffff] on node 0 +[ 0.000000] Zone ranges: +[ 0.000000] DMA [mem 0x00001000-0x00ffffff] +[ 0.000000] DMA32 [mem 0x01000000-0xffffffff] +[ 0.000000] Normal empty +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x00001000-0x0009ffff] +[ 0.000000] node 0: [mem 0x00100000-0x7f6d4fff] +[ 0.000000] On node 0 totalpages: 521844 +[ 0.000000] DMA zone: 64 pages used for memmap +[ 0.000000] DMA zone: 22 pages reserved +[ 0.000000] DMA zone: 3999 pages, LIFO batch:0 +[ 0.000000] DMA32 zone: 8092 pages used for memmap +[ 0.000000] DMA32 zone: 517845 pages, LIFO batch:31 +[ 0.000000] ACPI: PM-Timer IO Port: 0x508 +[ 0.000000] ACPI: Local APIC address 0xfee00000 +[ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled) +[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1]) +[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) +[ 0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0]) +[ 0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23 +[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 high edge) +[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) +[ 0.000000] ACPI: IRQ0 used by override. +[ 0.000000] ACPI: IRQ2 used by override. +[ 0.000000] ACPI: IRQ9 used by override. +[ 0.000000] Using ACPI (MADT) for SMP configuration information +[ 0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000 +[ 0.000000] smpboot: Allowing 2 CPUs, 0 hotplug CPUs +[ 0.000000] nr_irqs_gsi: 40 +[ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000bffff] +[ 0.000000] PM: Registered nosave memory: [mem 0x000c0000-0x000fffff] +[ 0.000000] e820: [mem 0x80000000-0xefffffff] available for PCI devices +[ 0.000000] Booting paravirtualized kernel on bare hardware +[ 0.000000] setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:2 nr_node_ids:1 +[ 0.000000] PERCPU: Embedded 29 pages/cpu @ffff88007f400000 s86336 r8192 d24256 u1048576 +[ 0.000000] pcpu-alloc: s86336 r8192 d24256 u1048576 alloc=1*2097152 +[ 0.000000] pcpu-alloc: [0] 0 1 +[ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 513666 +[ 0.000000] Policy zone: DMA32 +[ 0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz root=/dev/mapper/buzz-distro cryptdevice=/dev/mapper/buzz-distro:root quiet splash drm.debug=0x06 ro +[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) +[ 0.000000] Checking aperture... +[ 0.000000] No AGP bridge found +[ 0.000000] Calgary: detecting Calgary via BIOS EBDA area +[ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing! +[ 0.000000] Memory: 2013772K/2087376K available (7391K kernel code, 1145K rwdata, 3416K rodata, 1336K init, 1440K bss, 73604K reserved) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 +[ 0.000000] Hierarchical RCU implementation. +[ 0.000000] RCU dyntick-idle grace-period acceleration is enabled. +[ 0.000000] RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2. +[ 0.000000] Offload RCU callbacks from all CPUs +[ 0.000000] Offload RCU callbacks from CPUs: 0-1. +[ 0.000000] NR_IRQS:16640 nr_irqs:512 16 +[ 0.000000] Console: colour VGA+ 80x25 +[ 0.000000] console [tty0] enabled +[ 0.000000] allocated 8388608 bytes of page_cgroup +[ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups +[ 0.000000] hpet clockevent registered +[ 0.000000] tsc: Fast TSC calibration using PIT +[ 0.000000] tsc: Detected 1496.227 MHz processor +[ 0.004006] Calibrating delay loop (skipped), value calculated using timer frequency.. 2992.45 BogoMIPS (lpj=5984908) +[ 0.004013] pid_max: default: 32768 minimum: 301 +[ 0.004059] Security Framework initialized +[ 0.004095] AppArmor: AppArmor initialized +[ 0.004097] Yama: becoming mindful. +[ 0.004475] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes) +[ 0.008553] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes) +[ 0.009333] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes) +[ 0.009340] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes) +[ 0.009749] Initializing cgroup subsys memory +[ 0.009764] Initializing cgroup subsys devices +[ 0.009767] Initializing cgroup subsys freezer +[ 0.009771] Initializing cgroup subsys blkio +[ 0.009775] Initializing cgroup subsys bfqio +[ 0.009778] Initializing cgroup subsys perf_event +[ 0.009783] Initializing cgroup subsys hugetlb +[ 0.009821] CPU: Physical Processor ID: 0 +[ 0.009823] CPU: Processor Core ID: 0 +[ 0.009827] mce: CPU supports 6 MCE banks +[ 0.009839] CPU0: Thermal monitoring enabled (TM2) +[ 0.009850] Last level iTLB entries: 4KB 128, 2MB 4, 4MB 4 +[ 0.009850] Last level dTLB entries: 4KB 256, 2MB 0, 4MB 32 +[ 0.009850] tlb_flushall_shift: -1 +[ 0.010001] Freeing SMP alternatives memory: 32K (ffffffff81e6e000 - ffffffff81e76000) +[ 0.012383] ACPI: Core revision 20131115 +[ 0.015473] ACPI: All ACPI Tables successfully acquired +[ 0.016025] ftrace: allocating 28599 entries in 112 pages +[ 0.028599] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 +[ 0.070880] smpboot: CPU0: Intel(R) Core(TM)2 CPU L7400 @ 1.50GHz (fam: 06, model: 0f, stepping: 06) +[ 0.072000] Performance Events: PEBS fmt0-, 4-deep LBR, Core2 events, Intel PMU driver. +[ 0.072000] perf_event_intel: PEBS disabled due to CPU errata +[ 0.072000] ... version: 2 +[ 0.072000] ... bit width: 40 +[ 0.072000] ... generic registers: 2 +[ 0.072000] ... value mask: 000000ffffffffff +[ 0.072000] ... max period: 000000007fffffff +[ 0.072000] ... fixed-purpose events: 3 +[ 0.072000] ... event mask: 0000000700000003 +[ 0.072000] x86: Booting SMP configuration: +[ 0.072000] .... node #0, CPUs: #1 +[ 0.084066] x86: Booted up 1 node, 2 CPUs +[ 0.084074] smpboot: Total of 2 processors activated (5984.90 BogoMIPS) +[ 0.084177] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter. +[ 0.088071] devtmpfs: initialized +[ 0.098352] EVM: security.selinux +[ 0.098355] EVM: security.SMACK64 +[ 0.098357] EVM: security.ima +[ 0.098359] EVM: security.capability +[ 0.100096] pinctrl core: initialized pinctrl subsystem +[ 0.100211] regulator-dummy: no parameters +[ 0.100257] RTC time: 21:49:54, date: 08/31/14 +[ 0.100319] NET: Registered protocol family 16 +[ 0.100522] cpuidle: using governor ladder +[ 0.100525] cpuidle: using governor menu +[ 0.100592] ACPI: bus type PCI registered +[ 0.100595] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 +[ 0.100691] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xf0000000-0xf3ffffff] (base 0xf0000000) +[ 0.100695] PCI: MMCONFIG at [mem 0xf0000000-0xf3ffffff] reserved in E820 +[ 0.105678] PCI: Using configuration type 1 for base access +[ 0.108094] bio: create slab at 0 +[ 0.108141] ACPI: Added _OSI(Module Device) +[ 0.108144] ACPI: Added _OSI(Processor Device) +[ 0.108147] ACPI: Added _OSI(3.0 _SCP Extensions) +[ 0.108149] ACPI: Added _OSI(Processor Aggregator Device) +[ 0.111400] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored +[ 0.111850] ACPI: Interpreter enabled +[ 0.111859] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20131115/hwxface-580) +[ 0.111867] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20131115/hwxface-580) +[ 0.111889] ACPI: (supports S0 S3 S4 S5) +[ 0.111892] ACPI: Using IOAPIC for interrupt routing +[ 0.111927] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug +[ 0.112256] ACPI: ACPI Dock Station Driver: 1 docks/bays found +[ 0.121379] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) +[ 0.121389] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] +[ 0.121498] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] +[ 0.121642] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge +[ 0.121922] PCI host bridge to bus 0000:00 +[ 0.121927] pci_bus 0000:00: root bus resource [bus 00-ff] +[ 0.121931] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7] +[ 0.121935] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff] +[ 0.121938] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] +[ 0.121942] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000c3fff] +[ 0.121945] pci_bus 0000:00: root bus resource [mem 0x000c4000-0x000c7fff] +[ 0.121948] pci_bus 0000:00: root bus resource [mem 0x000c8000-0x000cbfff] +[ 0.121951] pci_bus 0000:00: root bus resource [mem 0x000cc000-0x000cffff] +[ 0.121955] pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff] +[ 0.121958] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff] +[ 0.121961] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff] +[ 0.121965] pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff] +[ 0.121968] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000e3fff] +[ 0.121971] pci_bus 0000:00: root bus resource [mem 0x000e4000-0x000e7fff] +[ 0.121975] pci_bus 0000:00: root bus resource [mem 0x000e8000-0x000ebfff] +[ 0.121978] pci_bus 0000:00: root bus resource [mem 0x000ec000-0x000effff] +[ 0.121981] pci_bus 0000:00: root bus resource [mem 0x000f0000-0x000fffff] +[ 0.121985] pci_bus 0000:00: root bus resource [mem 0x80000000-0xfebfffff] +[ 0.121988] pci_bus 0000:00: root bus resource [mem 0xfed40000-0xfed44fff] +[ 0.122002] pci 0000:00:00.0: [8086:27a0] type 00 class 0x060000 +[ 0.122153] pci 0000:00:02.0: [8086:27a2] type 00 class 0x030000 +[ 0.122170] pci 0000:00:02.0: reg 0x10: [mem 0xe4200000-0xe427ffff] +[ 0.122179] pci 0000:00:02.0: reg 0x14: [io 0x50a0-0x50a7] +[ 0.122188] pci 0000:00:02.0: reg 0x18: [mem 0xd0000000-0xdfffffff pref] +[ 0.122198] pci 0000:00:02.0: reg 0x1c: [mem 0xe4300000-0xe433ffff] +[ 0.122338] pci 0000:00:02.1: [8086:27a6] type 00 class 0x038000 +[ 0.122352] pci 0000:00:02.1: reg 0x10: [mem 0xe4280000-0xe42fffff] +[ 0.122564] pci 0000:00:1b.0: [8086:27d8] type 00 class 0x040300 +[ 0.122591] pci 0000:00:1b.0: reg 0x10: [mem 0xe4340000-0xe4343fff 64bit] +[ 0.122706] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold +[ 0.122785] pci 0000:00:1b.0: System wakeup disabled by ACPI +[ 0.122842] pci 0000:00:1c.0: [8086:27d0] type 01 class 0x060400 +[ 0.122964] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold +[ 0.123100] pci 0000:00:1c.1: [8086:27d2] type 01 class 0x060400 +[ 0.123210] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold +[ 0.123337] pci 0000:00:1c.2: [8086:27d4] type 01 class 0x060400 +[ 0.123447] pci 0000:00:1c.2: PME# supported from D0 D3hot D3cold +[ 0.123579] pci 0000:00:1c.3: [8086:27d6] type 01 class 0x060400 +[ 0.123689] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold +[ 0.123817] pci 0000:00:1d.0: [8086:27c8] type 00 class 0x0c0300 +[ 0.123881] pci 0000:00:1d.0: reg 0x20: [io 0x5000-0x501f] +[ 0.124006] pci 0000:00:1d.0: System wakeup disabled by ACPI +[ 0.124057] pci 0000:00:1d.1: [8086:27c9] type 00 class 0x0c0300 +[ 0.124120] pci 0000:00:1d.1: reg 0x20: [io 0x5020-0x503f] +[ 0.124236] pci 0000:00:1d.1: System wakeup disabled by ACPI +[ 0.124286] pci 0000:00:1d.2: [8086:27ca] type 00 class 0x0c0300 +[ 0.124349] pci 0000:00:1d.2: reg 0x20: [io 0x5040-0x505f] +[ 0.124464] pci 0000:00:1d.2: System wakeup disabled by ACPI +[ 0.124515] pci 0000:00:1d.3: [8086:27cb] type 00 class 0x0c0300 +[ 0.124578] pci 0000:00:1d.3: reg 0x20: [io 0x5060-0x507f] +[ 0.124695] pci 0000:00:1d.3: System wakeup disabled by ACPI +[ 0.124759] pci 0000:00:1d.7: [8086:27cc] type 00 class 0x0c0320 +[ 0.124787] pci 0000:00:1d.7: reg 0x10: [mem 0xe4344000-0xe43443ff] +[ 0.124905] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold +[ 0.124978] pci 0000:00:1d.7: System wakeup disabled by ACPI +[ 0.125032] pci 0000:00:1e.0: [8086:2448] type 01 class 0x060401 +[ 0.125214] pci 0000:00:1f.0: [8086:27b9] type 00 class 0x060100 +[ 0.125339] pci 0000:00:1f.0: address space collision: [io 0x0500-0x057f] conflicts with ACPI CPU throttle [??? 0x00000510-0x00000515 flags 0x80000000] +[ 0.125347] pci 0000:00:1f.0: quirk: [io 0x0480-0x04bf] claimed by ICH6 GPIO +[ 0.125353] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 1 PIO at 1600 (mask 007f) +[ 0.125359] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 2 PIO at 15e0 (mask 000f) +[ 0.125364] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 3 PIO at 1680 (mask 001f) +[ 0.125515] pci 0000:00:1f.1: [8086:27df] type 00 class 0x01018a +[ 0.125535] pci 0000:00:1f.1: reg 0x10: [io 0x50a8-0x50af] +[ 0.125550] pci 0000:00:1f.1: reg 0x14: [io 0x50c8-0x50cb] +[ 0.125564] pci 0000:00:1f.1: reg 0x18: [io 0x50b0-0x50b7] +[ 0.125578] pci 0000:00:1f.1: reg 0x1c: [io 0x50cc-0x50cf] +[ 0.125592] pci 0000:00:1f.1: reg 0x20: [io 0x5080-0x508f] +[ 0.125736] pci 0000:00:1f.2: [8086:27c5] type 00 class 0x010601 +[ 0.125764] pci 0000:00:1f.2: reg 0x10: [io 0x50b8-0x50bf] +[ 0.125777] pci 0000:00:1f.2: reg 0x14: [io 0x50d0-0x50d3] +[ 0.125792] pci 0000:00:1f.2: reg 0x18: [io 0x50c0-0x50c7] +[ 0.125806] pci 0000:00:1f.2: reg 0x1c: [io 0x50d4-0x50d7] +[ 0.125820] pci 0000:00:1f.2: reg 0x20: [io 0x5090-0x509f] +[ 0.125835] pci 0000:00:1f.2: reg 0x24: [mem 0xe4344400-0xe43447ff] +[ 0.125899] pci 0000:00:1f.2: PME# supported from D3hot +[ 0.126016] pci 0000:00:1f.3: [8086:27da] type 00 class 0x0c0500 +[ 0.126096] pci 0000:00:1f.3: reg 0x20: [io 0x0400-0x041f] +[ 0.126355] pci 0000:01:00.0: [8086:109a] type 00 class 0x020000 +[ 0.126389] pci 0000:01:00.0: reg 0x10: [mem 0xe4100000-0xe411ffff] +[ 0.126434] pci 0000:01:00.0: reg 0x18: [io 0x4000-0x401f] +[ 0.126628] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold +[ 0.126710] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force' +[ 0.126731] pci 0000:00:1c.0: PCI bridge to [bus 01] +[ 0.126737] pci 0000:00:1c.0: bridge window [io 0x4000-0x4fff] +[ 0.126744] pci 0000:00:1c.0: bridge window [mem 0xe4100000-0xe41fffff] +[ 0.126838] pci 0000:00:1c.1: PCI bridge to [bus 02] +[ 0.126938] pci 0000:00:1c.2: PCI bridge to [bus 03] +[ 0.127032] pci 0000:00:1c.3: PCI bridge to [bus 04] +[ 0.127187] pci 0000:05:00.0: [1180:0476] type 02 class 0x060700 +[ 0.127210] pci 0000:05:00.0: proprietary Ricoh MMC controller disabled (via cardbus function) +[ 0.127213] pci 0000:05:00.0: MMC cards are now supported by standard SDHCI controller +[ 0.127233] pci 0000:05:00.0: reg 0x10: [mem 0xe2000000-0xe2000fff] +[ 0.127274] pci 0000:05:00.0: supports D1 D2 +[ 0.127278] pci 0000:05:00.0: PME# supported from D0 D1 D2 D3hot D3cold +[ 0.127318] pci 0000:05:00.0: System wakeup disabled by ACPI +[ 0.127377] pci 0000:05:00.1: [1180:0552] type 00 class 0x0c0010 +[ 0.127403] pci 0000:05:00.1: reg 0x10: [mem 0xe2001000-0xe20017ff] +[ 0.127512] pci 0000:05:00.1: supports D1 D2 +[ 0.127516] pci 0000:05:00.1: PME# supported from D0 D1 D2 D3hot D3cold +[ 0.127599] pci 0000:05:00.2: [1180:0822] type 00 class 0x080500 +[ 0.127626] pci 0000:05:00.2: reg 0x10: [mem 0xe2001800-0xe20018ff] +[ 0.127736] pci 0000:05:00.2: supports D1 D2 +[ 0.127740] pci 0000:05:00.2: PME# supported from D0 D1 D2 D3hot D3cold +[ 0.127880] pci 0000:00:1e.0: PCI bridge to [bus 05-06] (subtractive decode) +[ 0.127887] pci 0000:00:1e.0: bridge window [io 0x2000-0x3fff] +[ 0.127894] pci 0000:00:1e.0: bridge window [mem 0xe0000000-0xe20fffff] +[ 0.127904] pci 0000:00:1e.0: bridge window [mem 0xe2100000-0xe40fffff 64bit pref] +[ 0.127908] pci 0000:00:1e.0: bridge window [io 0x0000-0x0cf7] (subtractive decode) +[ 0.127911] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff] (subtractive decode) +[ 0.127915] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode) +[ 0.127918] pci 0000:00:1e.0: bridge window [mem 0x000c0000-0x000c3fff] (subtractive decode) +[ 0.127922] pci 0000:00:1e.0: bridge window [mem 0x000c4000-0x000c7fff] (subtractive decode) +[ 0.127925] pci 0000:00:1e.0: bridge window [mem 0x000c8000-0x000cbfff] (subtractive decode) +[ 0.127928] pci 0000:00:1e.0: bridge window [mem 0x000cc000-0x000cffff] (subtractive decode) +[ 0.127932] pci 0000:00:1e.0: bridge window [mem 0x000d0000-0x000d3fff] (subtractive decode) +[ 0.127935] pci 0000:00:1e.0: bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode) +[ 0.127938] pci 0000:00:1e.0: bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode) +[ 0.127942] pci 0000:00:1e.0: bridge window [mem 0x000dc000-0x000dffff] (subtractive decode) +[ 0.127945] pci 0000:00:1e.0: bridge window [mem 0x000e0000-0x000e3fff] (subtractive decode) +[ 0.127949] pci 0000:00:1e.0: bridge window [mem 0x000e4000-0x000e7fff] (subtractive decode) +[ 0.127952] pci 0000:00:1e.0: bridge window [mem 0x000e8000-0x000ebfff] (subtractive decode) +[ 0.127955] pci 0000:00:1e.0: bridge window [mem 0x000ec000-0x000effff] (subtractive decode) +[ 0.127959] pci 0000:00:1e.0: bridge window [mem 0x000f0000-0x000fffff] (subtractive decode) +[ 0.127962] pci 0000:00:1e.0: bridge window [mem 0x80000000-0xfebfffff] (subtractive decode) +[ 0.127966] pci 0000:00:1e.0: bridge window [mem 0xfed40000-0xfed44fff] (subtractive decode) +[ 0.128041] pci_bus 0000:06: busn_res: can not insert [bus 06-ff] under [bus 05-06] (conflicts with (null) [bus 05-06]) +[ 0.128049] pci_bus 0000:06: busn_res: [bus 06-ff] end is updated to 09 +[ 0.128053] pci_bus 0000:06: busn_res: can not insert [bus 06-09] under [bus 05-06] (conflicts with (null) [bus 05-06]) +[ 0.128060] pci_bus 0000:06: [bus 06-09] partially hidden behind transparent bridge 0000:05 [bus 05-06] +[ 0.128336] ACPI: PCI Interrupt Link [LNKA] (IRQs 1 3 4 5 6 7 10 12 14 15) *11 +[ 0.128426] ACPI: PCI Interrupt Link [LNKB] (IRQs 1 3 4 5 6 7 *11 12 14 15) +[ 0.128512] ACPI: PCI Interrupt Link [LNKC] (IRQs 1 3 4 5 6 7 10 12 14 15) *11 +[ 0.128597] ACPI: PCI Interrupt Link [LNKD] (IRQs 1 3 4 5 6 7 *11 12 14 15) +[ 0.128682] ACPI: PCI Interrupt Link [LNKE] (IRQs 1 3 4 5 6 7 10 12 14 15) *11 +[ 0.128766] ACPI: PCI Interrupt Link [LNKF] (IRQs 1 3 4 5 6 7 *11 12 14 15) +[ 0.128850] ACPI: PCI Interrupt Link [LNKG] (IRQs 1 3 4 5 6 7 10 12 14 15) *11 +[ 0.128935] ACPI: PCI Interrupt Link [LNKH] (IRQs 1 3 4 5 6 7 *11 12 14 15) +[ 0.129051] ACPI: \_SB_.PCI0: notify handler is installed +[ 0.129051] Found 1 acpi root devices +[ 0.129051] ACPI : EC: GPE = 0x1c, I/O: command/status = 0x66, data = 0x62 +[ 0.129051] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none +[ 0.129051] vgaarb: loaded +[ 0.129051] vgaarb: bridge control possible 0000:00:02.0 +[ 0.129051] SCSI subsystem initialized +[ 0.129051] libata version 3.00 loaded. +[ 0.129051] ACPI: bus type USB registered +[ 0.129051] usbcore: registered new interface driver usbfs +[ 0.129051] usbcore: registered new interface driver hub +[ 0.129051] usbcore: registered new device driver usb +[ 0.129051] PCI: Using ACPI for IRQ routing +[ 0.133275] PCI: pci_cache_line_size set to 64 bytes +[ 0.133369] e820: reserve RAM buffer [mem 0x7f6d5000-0x7fffffff] +[ 0.133506] NetLabel: Initializing +[ 0.133509] NetLabel: domain hash size = 128 +[ 0.133510] NetLabel: protocols = UNLABELED CIPSOv4 +[ 0.133537] NetLabel: unlabeled traffic allowed by default +[ 0.133557] HPET: 3 timers in total, 0 timers will be used for per-cpu timer +[ 0.133557] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0 +[ 0.133557] hpet0: 3 comparators, 64-bit 14.318180 MHz counter +[ 0.134098] Switched to clocksource hpet +[ 0.142214] AppArmor: AppArmor Filesystem Enabled +[ 0.142264] pnp: PnP ACPI init +[ 0.142291] ACPI: bus type PNP registered +[ 0.142445] system 00:00: [mem 0xfed1c000-0xfed1ffff] has been reserved +[ 0.142450] system 00:00: [mem 0xfed14000-0xfed17fff] has been reserved +[ 0.142454] system 00:00: [mem 0xfed18000-0xfed18fff] has been reserved +[ 0.142458] system 00:00: [mem 0xfed19000-0xfed19fff] has been reserved +[ 0.142462] system 00:00: [mem 0xf0000000-0xf3ffffff] has been reserved +[ 0.142466] system 00:00: [mem 0xfed20000-0xfed3ffff] has been reserved +[ 0.142470] system 00:00: [mem 0xfed40000-0xfed44fff] has been reserved +[ 0.142474] system 00:00: [mem 0xfed45000-0xfed8ffff] has been reserved +[ 0.142481] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active) +[ 0.143002] pnp 00:01: [dma 4] +[ 0.143047] pnp 00:01: Plug and Play ACPI device, IDs PNP0200 (active) +[ 0.143092] pnp 00:02: Plug and Play ACPI device, IDs INT0800 (active) +[ 0.143244] system 00:03: [mem 0xfed00000-0xfed003ff] has been reserved +[ 0.143250] system 00:03: Plug and Play ACPI device, IDs PNP0103 PNP0c01 (active) +[ 0.143320] pnp 00:04: Plug and Play ACPI device, IDs PNP0c04 (active) +[ 0.143397] system 00:05: [io 0x0800-0x080f] has been reserved +[ 0.143402] system 00:05: [io 0x0500-0x057f] could not be reserved +[ 0.143406] system 00:05: [io 0x0480-0x04bf] has been reserved +[ 0.143411] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active) +[ 0.143463] pnp 00:06: Plug and Play ACPI device, IDs PNP0b00 (active) +[ 0.143529] pnp 00:07: Plug and Play ACPI device, IDs PNP0303 PNP030b (active) +[ 0.143593] pnp 00:08: Plug and Play ACPI device, IDs PNP0f13 (active) +[ 0.143654] pnp 00:09: Plug and Play ACPI device, IDs PNP0501 (active) +[ 0.143699] pnp: PnP ACPI: found 10 devices +[ 0.143702] ACPI: bus type PNP unregistered +[ 0.151684] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 01] add_size 200000 +[ 0.151738] pci 0000:00:1f.0: BAR 13: [io 0x0500-0x057f] has bogus alignment +[ 0.151744] pci 0000:00:1c.0: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000 +[ 0.151755] pci 0000:00:1c.0: BAR 15: assigned [mem 0x80000000-0x801fffff 64bit pref] +[ 0.151759] pci 0000:00:1c.0: PCI bridge to [bus 01] +[ 0.151765] pci 0000:00:1c.0: bridge window [io 0x4000-0x4fff] +[ 0.151773] pci 0000:00:1c.0: bridge window [mem 0xe4100000-0xe41fffff] +[ 0.151780] pci 0000:00:1c.0: bridge window [mem 0x80000000-0x801fffff 64bit pref] +[ 0.151790] pci 0000:00:1c.1: PCI bridge to [bus 02] +[ 0.151807] pci 0000:00:1c.2: PCI bridge to [bus 03] +[ 0.151824] pci 0000:00:1c.3: PCI bridge to [bus 04] +[ 0.151848] pci 0000:05:00.0: res[15]=[mem 0x04000000-0x03ffffff pref] get_res_add_size add_size 4000000 +[ 0.151852] pci 0000:05:00.0: res[16]=[mem 0x04000000-0x03ffffff] get_res_add_size add_size 4000000 +[ 0.151856] pci 0000:05:00.0: res[13]=[io 0x0100-0x00ff] get_res_add_size add_size 100 +[ 0.151860] pci 0000:05:00.0: res[14]=[io 0x0100-0x00ff] get_res_add_size add_size 100 +[ 0.151868] pci 0000:05:00.0: BAR 15: assigned [mem 0x84000000-0x87ffffff pref] +[ 0.151875] pci 0000:05:00.0: BAR 16: assigned [mem 0x88000000-0x8bffffff] +[ 0.151879] pci 0000:05:00.0: BAR 13: assigned [io 0x2000-0x20ff] +[ 0.151883] pci 0000:05:00.0: BAR 14: assigned [io 0x2400-0x24ff] +[ 0.151888] pci 0000:05:00.0: CardBus bridge to [bus 06-09] +[ 0.151891] pci 0000:05:00.0: bridge window [io 0x2000-0x20ff] +[ 0.151897] pci 0000:05:00.0: bridge window [io 0x2400-0x24ff] +[ 0.151904] pci 0000:05:00.0: bridge window [mem 0x84000000-0x87ffffff pref] +[ 0.151910] pci 0000:05:00.0: bridge window [mem 0x88000000-0x8bffffff] +[ 0.151917] pci 0000:00:1e.0: PCI bridge to [bus 05-06] +[ 0.151922] pci 0000:00:1e.0: bridge window [io 0x2000-0x3fff] +[ 0.151930] pci 0000:00:1e.0: bridge window [mem 0xe0000000-0xe20fffff] +[ 0.151937] pci 0000:00:1e.0: bridge window [mem 0xe2100000-0xe40fffff 64bit pref] +[ 0.151947] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7] +[ 0.151951] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff] +[ 0.151955] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff] +[ 0.151958] pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000c3fff] +[ 0.151962] pci_bus 0000:00: resource 8 [mem 0x000c4000-0x000c7fff] +[ 0.151965] pci_bus 0000:00: resource 9 [mem 0x000c8000-0x000cbfff] +[ 0.151968] pci_bus 0000:00: resource 10 [mem 0x000cc000-0x000cffff] +[ 0.151972] pci_bus 0000:00: resource 11 [mem 0x000d0000-0x000d3fff] +[ 0.151975] pci_bus 0000:00: resource 12 [mem 0x000d4000-0x000d7fff] +[ 0.151978] pci_bus 0000:00: resource 13 [mem 0x000d8000-0x000dbfff] +[ 0.151981] pci_bus 0000:00: resource 14 [mem 0x000dc000-0x000dffff] +[ 0.151985] pci_bus 0000:00: resource 15 [mem 0x000e0000-0x000e3fff] +[ 0.151988] pci_bus 0000:00: resource 16 [mem 0x000e4000-0x000e7fff] +[ 0.151991] pci_bus 0000:00: resource 17 [mem 0x000e8000-0x000ebfff] +[ 0.151994] pci_bus 0000:00: resource 18 [mem 0x000ec000-0x000effff] +[ 0.151998] pci_bus 0000:00: resource 19 [mem 0x000f0000-0x000fffff] +[ 0.152014] pci_bus 0000:00: resource 20 [mem 0x80000000-0xfebfffff] +[ 0.152018] pci_bus 0000:00: resource 21 [mem 0xfed40000-0xfed44fff] +[ 0.152022] pci_bus 0000:01: resource 0 [io 0x4000-0x4fff] +[ 0.152025] pci_bus 0000:01: resource 1 [mem 0xe4100000-0xe41fffff] +[ 0.152029] pci_bus 0000:01: resource 2 [mem 0x80000000-0x801fffff 64bit pref] +[ 0.152033] pci_bus 0000:05: resource 0 [io 0x2000-0x3fff] +[ 0.152036] pci_bus 0000:05: resource 1 [mem 0xe0000000-0xe20fffff] +[ 0.152040] pci_bus 0000:05: resource 2 [mem 0xe2100000-0xe40fffff 64bit pref] +[ 0.152043] pci_bus 0000:05: resource 4 [io 0x0000-0x0cf7] +[ 0.152047] pci_bus 0000:05: resource 5 [io 0x0d00-0xffff] +[ 0.152050] pci_bus 0000:05: resource 6 [mem 0x000a0000-0x000bffff] +[ 0.152054] pci_bus 0000:05: resource 7 [mem 0x000c0000-0x000c3fff] +[ 0.152057] pci_bus 0000:05: resource 8 [mem 0x000c4000-0x000c7fff] +[ 0.152061] pci_bus 0000:05: resource 9 [mem 0x000c8000-0x000cbfff] +[ 0.152064] pci_bus 0000:05: resource 10 [mem 0x000cc000-0x000cffff] +[ 0.152067] pci_bus 0000:05: resource 11 [mem 0x000d0000-0x000d3fff] +[ 0.152071] pci_bus 0000:05: resource 12 [mem 0x000d4000-0x000d7fff] +[ 0.152074] pci_bus 0000:05: resource 13 [mem 0x000d8000-0x000dbfff] +[ 0.152077] pci_bus 0000:05: resource 14 [mem 0x000dc000-0x000dffff] +[ 0.152080] pci_bus 0000:05: resource 15 [mem 0x000e0000-0x000e3fff] +[ 0.152084] pci_bus 0000:05: resource 16 [mem 0x000e4000-0x000e7fff] +[ 0.152087] pci_bus 0000:05: resource 17 [mem 0x000e8000-0x000ebfff] +[ 0.152090] pci_bus 0000:05: resource 18 [mem 0x000ec000-0x000effff] +[ 0.152093] pci_bus 0000:05: resource 19 [mem 0x000f0000-0x000fffff] +[ 0.152097] pci_bus 0000:05: resource 20 [mem 0x80000000-0xfebfffff] +[ 0.152100] pci_bus 0000:05: resource 21 [mem 0xfed40000-0xfed44fff] +[ 0.152104] pci_bus 0000:06: resource 0 [io 0x2000-0x20ff] +[ 0.152107] pci_bus 0000:06: resource 1 [io 0x2400-0x24ff] +[ 0.152111] pci_bus 0000:06: resource 2 [mem 0x84000000-0x87ffffff pref] +[ 0.152114] pci_bus 0000:06: resource 3 [mem 0x88000000-0x8bffffff] +[ 0.152167] NET: Registered protocol family 2 +[ 0.152410] TCP established hash table entries: 16384 (order: 5, 131072 bytes) +[ 0.152518] TCP bind hash table entries: 16384 (order: 6, 262144 bytes) +[ 0.152669] TCP: Hash tables configured (established 16384 bind 16384) +[ 0.152731] TCP: reno registered +[ 0.152739] UDP hash table entries: 1024 (order: 3, 32768 bytes) +[ 0.152763] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes) +[ 0.152861] NET: Registered protocol family 1 +[ 0.152882] pci 0000:00:02.0: Boot video device +[ 0.154029] PCI: CLS 64 bytes, default 64 +[ 0.154130] Trying to unpack rootfs image as initramfs... +[ 0.891588] Freeing initrd memory: 23964K (ffff880035122000 - ffff880036889000) +[ 0.891983] microcode: CPU0 sig=0x6f6, pf=0x20, revision=0x0 +[ 0.891991] microcode: CPU1 sig=0x6f6, pf=0x20, revision=0x0 +[ 0.892123] microcode: Microcode Update Driver: v2.00 , Peter Oruba +[ 0.892126] Scanning for low memory corruption every 60 seconds +[ 0.892509] Initialise system trusted keyring +[ 0.892592] audit: initializing netlink socket (disabled) +[ 0.892616] type=2000 audit(1409521794.892:1): initialized +[ 0.938675] HugeTLB registered 2 MB page size, pre-allocated 0 pages +[ 0.940706] zbud: loaded +[ 0.940918] VFS: Disk quotas dquot_6.5.2 +[ 0.940988] Dquot-cache hash table entries: 512 (order 0, 4096 bytes) +[ 0.941797] fuse init (API version 7.22) +[ 0.941924] msgmni has been set to 3980 +[ 0.942015] Key type big_key registered +[ 0.942641] Key type asymmetric registered +[ 0.942645] Asymmetric key parser 'x509' registered +[ 0.942697] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252) +[ 0.942747] io scheduler noop registered +[ 0.942751] io scheduler deadline registered (default) +[ 0.942789] io scheduler cfq registered +[ 0.942802] io scheduler bfq registered +[ 0.942804] BFQ I/O-scheduler version: v7r5 +[ 0.943133] pcieport 0000:00:1c.0: irq 40 for MSI/MSI-X +[ 0.943399] pcieport 0000:00:1c.1: irq 41 for MSI/MSI-X +[ 0.943635] pcieport 0000:00:1c.2: irq 42 for MSI/MSI-X +[ 0.943873] pcieport 0000:00:1c.3: irq 43 for MSI/MSI-X +[ 0.944051] pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt +[ 0.944061] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt +[ 0.944068] pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded +[ 0.944102] pcieport 0000:00:1c.1: Signaling PME through PCIe PME interrupt +[ 0.944109] pcie_pme 0000:00:1c.1:pcie01: service driver pcie_pme loaded +[ 0.944142] pcieport 0000:00:1c.2: Signaling PME through PCIe PME interrupt +[ 0.944149] pcie_pme 0000:00:1c.2:pcie01: service driver pcie_pme loaded +[ 0.944178] pcieport 0000:00:1c.3: Signaling PME through PCIe PME interrupt +[ 0.944185] pcie_pme 0000:00:1c.3:pcie01: service driver pcie_pme loaded +[ 0.944207] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 +[ 0.944253] pciehp 0000:00:1c.0:pcie04: HPC vendor_id 8086 device_id 27d0 ss_vid 8086 ss_did 27d0 +[ 0.944297] pciehp 0000:00:1c.0:pcie04: service driver pciehp loaded +[ 0.944307] pciehp: PCI Express Hot Plug Controller Driver version: 0.4 +[ 0.944385] intel_idle: does not run on family 6 model 15 +[ 0.944397] ipmi message handler version 39.2 +[ 0.944733] ACPI: AC Adapter [AC] (off-line) +[ 0.944807] ACPI Exception: AE_NOT_FOUND, Error reading AC Adapter state (20131115/ac-108) +[ 0.945053] input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0A08:00/device:24/PNP0C09:00/PNP0C0E:00/input/input0 +[ 0.945061] ACPI: Sleep Button [SLPB] +[ 0.945124] input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0A08:00/device:24/PNP0C09:00/PNP0C0D:00/input/input1 +[ 0.945243] ACPI: Lid Switch [LID] +[ 0.945307] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 +[ 0.945312] ACPI: Power Button [PWRF] +[ 0.946267] Monitor-Mwait will be used to enter C-1 state +[ 0.946279] tsc: Marking TSC unstable due to TSC halts in idle +[ 0.946288] ACPI: acpi_idle registered with cpuidle +[ 0.947899] thermal LNXTHERM:00: registered as thermal_zone0 +[ 0.947904] ACPI: Thermal Zone [THM0] (39 C) +[ 0.948530] thermal LNXTHERM:01: registered as thermal_zone1 +[ 0.948533] ACPI: Thermal Zone [THM1] (27 C) +[ 0.948573] GHES: HEST is not enabled! +[ 0.948770] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled +[ 0.952564] Linux agpgart interface v0.103 +[ 0.952903] agpgart-intel 0000:00:00.0: Intel 945GM Chipset +[ 0.952979] agpgart-intel 0000:00:00.0: detected gtt size: 262144K total, 262144K mappable +[ 0.954238] agpgart-intel 0000:00:00.0: detected 8192K stolen memory +[ 0.954581] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xd0000000 +[ 0.960749] brd: module loaded +[ 0.962506] loop: module loaded +[ 0.962983] ata_piix 0000:00:1f.1: version 2.13 +[ 0.963770] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +[ 0.963780] ACPI: Battery Slot [BAT0] (battery present) +[ 0.963927] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +[ 0.963935] ACPI: Battery Slot [BAT1] (battery absent) +[ 0.964039] scsi0 : ata_piix +[ 0.964177] scsi1 : ata_piix +[ 0.964231] ata1: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0x5080 irq 14 +[ 0.964235] ata2: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x5088 irq 15 +[ 0.964290] ata1: port disabled--ignoring +[ 0.964327] ata2: port disabled--ignoring +[ 0.964709] libphy: Fixed MDIO Bus: probed +[ 0.964859] tun: Universal TUN/TAP device driver, 1.6 +[ 0.964861] tun: (C) 1999-2004 Max Krasnyansky +[ 0.964949] PPP generic driver version 2.4.2 +[ 0.965035] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver +[ 0.965043] ehci-pci: EHCI PCI platform driver +[ 0.965215] ehci-pci 0000:00:1d.7: EHCI Host Controller +[ 0.965228] ehci-pci 0000:00:1d.7: new USB bus registered, assigned bus number 1 +[ 0.965248] ehci-pci 0000:00:1d.7: debug port 1 +[ 0.969175] ehci-pci 0000:00:1d.7: cache line size of 64 is not supported +[ 0.969198] ehci-pci 0000:00:1d.7: irq 19, io mem 0xe4344000 +[ 0.980055] ehci-pci 0000:00:1d.7: USB 2.0 started, EHCI 1.00 +[ 0.980167] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 +[ 0.980171] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.980174] usb usb1: Product: EHCI Host Controller +[ 0.980178] usb usb1: Manufacturer: Linux 3.13.0-34-generic ehci_hcd +[ 0.980181] usb usb1: SerialNumber: 0000:00:1d.7 +[ 0.980361] hub 1-0:1.0: USB hub found +[ 0.980376] hub 1-0:1.0: 8 ports detected +[ 0.980772] ehci-platform: EHCI generic platform driver +[ 0.980789] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver +[ 0.980791] ohci-pci: OHCI PCI platform driver +[ 0.980807] ohci-platform: OHCI generic platform driver +[ 0.980820] uhci_hcd: USB Universal Host Controller Interface driver +[ 0.980960] uhci_hcd 0000:00:1d.0: UHCI Host Controller +[ 0.980969] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2 +[ 0.981013] uhci_hcd 0000:00:1d.0: irq 16, io base 0x00005000 +[ 0.981094] usb usb2: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.981099] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.981102] usb usb2: Product: UHCI Host Controller +[ 0.981106] usb usb2: Manufacturer: Linux 3.13.0-34-generic uhci_hcd +[ 0.981109] usb usb2: SerialNumber: 0000:00:1d.0 +[ 0.981266] hub 2-0:1.0: USB hub found +[ 0.981279] hub 2-0:1.0: 2 ports detected +[ 0.981522] uhci_hcd 0000:00:1d.1: UHCI Host Controller +[ 0.981530] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 3 +[ 0.981575] uhci_hcd 0000:00:1d.1: irq 17, io base 0x00005020 +[ 0.981654] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.981658] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.981662] usb usb3: Product: UHCI Host Controller +[ 0.981665] usb usb3: Manufacturer: Linux 3.13.0-34-generic uhci_hcd +[ 0.981669] usb usb3: SerialNumber: 0000:00:1d.1 +[ 0.981825] hub 3-0:1.0: USB hub found +[ 0.981840] hub 3-0:1.0: 2 ports detected +[ 0.982079] uhci_hcd 0000:00:1d.2: UHCI Host Controller +[ 0.982090] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 4 +[ 0.982135] uhci_hcd 0000:00:1d.2: irq 18, io base 0x00005040 +[ 0.982218] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.982222] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.982225] usb usb4: Product: UHCI Host Controller +[ 0.982229] usb usb4: Manufacturer: Linux 3.13.0-34-generic uhci_hcd +[ 0.982232] usb usb4: SerialNumber: 0000:00:1d.2 +[ 0.982388] hub 4-0:1.0: USB hub found +[ 0.982401] hub 4-0:1.0: 2 ports detected +[ 0.982648] uhci_hcd 0000:00:1d.3: UHCI Host Controller +[ 0.982656] uhci_hcd 0000:00:1d.3: new USB bus registered, assigned bus number 5 +[ 0.982688] uhci_hcd 0000:00:1d.3: irq 19, io base 0x00005060 +[ 0.982769] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.982774] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.982777] usb usb5: Product: UHCI Host Controller +[ 0.982781] usb usb5: Manufacturer: Linux 3.13.0-34-generic uhci_hcd +[ 0.982784] usb usb5: SerialNumber: 0000:00:1d.3 +[ 0.982935] hub 5-0:1.0: USB hub found +[ 0.982947] hub 5-0:1.0: 2 ports detected +[ 0.983162] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at 0x60,0x64 irq 1,12 +[ 0.996933] serio: i8042 KBD port at 0x60,0x64 irq 1 +[ 0.996948] serio: i8042 AUX port at 0x60,0x64 irq 12 +[ 0.997177] mousedev: PS/2 mouse device common for all mice +[ 0.997526] rtc_cmos 00:06: RTC can wake from S4 +[ 0.997724] rtc_cmos 00:06: rtc core: registered rtc_cmos as rtc0 +[ 0.997761] rtc_cmos 00:06: alarms up to one month, y3k, 242 bytes nvram, hpet irqs +[ 0.997869] device-mapper: uevent: version 1.0.3 +[ 0.997988] device-mapper: ioctl: 4.27.0-ioctl (2013-10-30) initialised: dm-devel@redhat.com +[ 0.998000] ledtrig-cpu: registered to indicate activity on CPUs +[ 0.998153] TCP: cubic registered +[ 0.998301] NET: Registered protocol family 10 +[ 0.998581] NET: Registered protocol family 17 +[ 0.998598] Key type dns_resolver registered +[ 0.999003] Loading compiled-in X.509 certificates +[ 1.000843] Loaded X.509 cert 'Magrathea: Glacier signing key: 0cadd161e4220740356b3090aabd2b3fcb83a5d0' +[ 1.000865] registered taskstats version 1 +[ 1.004840] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3 +[ 1.006130] Key type trusted registered +[ 1.010130] Key type encrypted registered +[ 1.015532] AppArmor: AppArmor sha1 policy hashing enabled +[ 1.015538] IMA: No TPM chip found, activating TPM-bypass! +[ 1.015959] regulator-dummy: disabling +[ 1.016046] Magic number: 10:359:855 +[ 1.016202] rtc_cmos 00:06: setting system clock to 2014-08-31 21:49:55 UTC (1409521795) +[ 1.017114] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found +[ 1.017120] EDD information not available. +[ 1.017162] PM: Hibernation image not present or could not be loaded. +[ 1.019541] Freeing unused kernel memory: 1336K (ffffffff81d20000 - ffffffff81e6e000) +[ 1.019544] Write protecting the kernel read-only data: 12288k +[ 1.023552] Freeing unused kernel memory: 788K (ffff88000173b000 - ffff880001800000) +[ 1.026751] Freeing unused kernel memory: 680K (ffff880001b56000 - ffff880001c00000) +[ 1.052928] systemd-udevd[101]: starting version 204 +[ 1.094875] pps_core: LinuxPPS API ver. 1 registered +[ 1.094880] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti +[ 1.098290] [drm] Initialized drm 1.1.0 20060810 +[ 1.102066] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) +[ 1.106256] PTP clock support registered +[ 1.113596] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k +[ 1.113602] e1000e: Copyright(c) 1999 - 2013 Intel Corporation. +[ 1.124513] e1000e 0000:01:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode +[ 1.124561] e1000e 0000:01:00.0: irq 44 for MSI/MSI-X +[ 1.124660] acpi device:04: registered as cooling_device2 +[ 1.124749] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input5 +[ 1.147236] [drm:i915_dump_device_info], i915 device info: gen=3, pciid=0x27a2 flags=is_mobile,is_i945gm,has_hotplug,cursor_needs_physical,has_overlay,overlay_needs_physical,supports_tv, +[ 1.147327] [drm:intel_detect_pch], No PCH found. +[ 1.147333] [drm] Memory usable by graphics device = 256M +[ 1.147335] [drm:i915_gem_gtt_init], GMADR size = 256M +[ 1.147338] [drm:i915_gem_gtt_init], GTT stolen size = 8M +[ 1.149656] sdhci: Secure Digital Host Controller Interface driver +[ 1.149659] sdhci: Copyright(c) Pierre Ossman +[ 1.152120] sdhci-pci 0000:05:00.2: SDHCI controller found [1180:0822] (rev 18) +[ 1.152136] pci 0000:00:1e.0: enabling device (0004 -> 0007) +[ 1.180299] [drm:intel_opregion_setup], graphic opregion physical addr: 0x0 +[ 1.180306] [drm:intel_opregion_setup], ACPI OpRegion not supported! +[ 1.180346] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). +[ 1.180348] [drm] Driver supports precise vblank timestamp query. +[ 1.180351] [drm:init_vbt_defaults], Set default to SSC at 100MHz +[ 1.180358] i915 0000:00:02.0: Invalid ROM contents +[ 1.180360] [drm:intel_parse_bios], VBT signature missing +[ 1.180363] [drm] failed to find VBIOS tables +[ 1.180369] [drm:intel_dsm_pci_probe], no _DSM method for intel device +[ 1.180383] [drm:i915_gem_init_stolen], found 8388608 bytes of stolen memory at 7f800000 +[ 1.180409] [drm] GPU crash dump saved to /sys/class/drm/card0/error +[ 1.180412] [drm:intel_modeset_init], 2 display pipes available. +[ 1.180419] [drm:intel_crtc_init], swapping pipes & planes for FBC +[ 1.180421] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace. +[ 1.180423] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel +[ 1.180425] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue. +[ 1.180427] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it. +[ 1.180429] [drm:intel_modeset_init], pipe A sprite A init failed: -19 +[ 1.180435] [drm:intel_crtc_init], swapping pipes & planes for FBC +[ 1.180437] [drm:intel_modeset_init], pipe B sprite B init failed: -19 +[ 1.180440] [drm:intel_shared_dpll_init], 0 shared PLLs initialized +[ 1.180448] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem +[ 1.180450] i915: render error detected, EIR: 0x00000010 +[ 1.180452] i915: page table error +[ 1.180454] i915: PGTBL_ER: 0x00000012 +[ 1.180457] [drm:i915_report_and_clear_eir] *ERROR* EIR stuck: 0x00000010, masking +[ 1.180463] [drm:i915_irq_handler], pipe B underrun +[ 1.180469] i915: render error detected, EIR: 0x00000010 +[ 1.180471] i915: page table error +[ 1.180473] i915: PGTBL_ER: 0x00000012 +[ 1.182043] sdhci-pci 0000:05:00.2: Will use DMA mode even though HW doesn't fully claim to support it. +[ 1.182056] sdhci-pci 0000:05:00.2: dummy supplies not allowed +[ 1.182059] mmc0: no vqmmc regulator found +[ 1.182062] sdhci-pci 0000:05:00.2: dummy supplies not allowed +[ 1.182064] mmc0: no vmmc regulator found +[ 1.183062] sdhci-pci 0000:05:00.2: Will use DMA mode even though HW doesn't fully claim to support it. +[ 1.183862] mmc0: SDHCI controller on PCI [0000:05:00.2] using DMA +[ 1.236462] e1000e 0000:01:00.0 eth0: (PCI Express:2.5GT/s:Width x1) 00:16:d3:b6:d0:98 +[ 1.236469] e1000e 0000:01:00.0 eth0: Intel(R) PRO/1000 Network Connection +[ 1.236549] e1000e 0000:01:00.0 eth0: MAC: 2, PHY: 2, PBA No: 005302-003 +[ 1.248155] firewire_ohci 0000:05:00.1: added OHCI v1.10 device as card 0, 4 IR + 4 IT contexts, quirks 0x11 +[ 1.264281] [drm:intel_lvds_init], using preferred mode from EDID: +[ 1.264287] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +[ 1.264297] [drm:intel_lvds_init], detected single-link lvds configuration +[ 1.264356] [drm:intel_panel_get_backlight], get backlight PWM = 24832 +[ 1.264360] [drm:intel_panel_get_max_backlight], max backlight PWM = 24832 +[ 1.264505] [drm:i915_gem_setup_global_gtt], clearing unused GTT space: [0, ffff000] +[ 1.264889] [drm:i915_gem_object_create_stolen], creating stolen object: size=20000 +[ 1.264897] [drm:i915_pages_create_for_stolen], offset=0x0, size=131072 +[ 1.264946] [drm:i915_gem_context_init], Disabling HW Contexts; old hardware +[ 1.264996] [drm] initialized overlay support +[ 1.265002] [drm:intel_modeset_readout_hw_state], [CRTC:3] hw state readout: disabled +[ 1.265012] [drm:intel_modeset_readout_hw_state], [CRTC:4] hw state readout: enabled +[ 1.265017] [drm:intel_modeset_readout_hw_state], [ENCODER:6:LVDS-6] hw state readout: enabled, pipe B +[ 1.265022] [drm:intel_modeset_readout_hw_state], [ENCODER:16:DAC-16] hw state readout: disabled, pipe A +[ 1.265026] [drm:intel_modeset_readout_hw_state], [ENCODER:18:TV-18] hw state readout: disabled, pipe A +[ 1.265031] [drm:intel_modeset_readout_hw_state], [CONNECTOR:5:LVDS-1] hw state readout: enabled +[ 1.265035] [drm:intel_modeset_readout_hw_state], [CONNECTOR:15:VGA-1] hw state readout: disabled +[ 1.265039] [drm:intel_modeset_readout_hw_state], [CONNECTOR:17:SVIDEO-1] hw state readout: disabled +[ 1.265044] [drm:intel_dump_pipe_config], [CRTC:3][setup_hw_state] config for pipe A +[ 1.265047] [drm:intel_dump_pipe_config], cpu_transcoder: A +[ 1.265050] [drm:intel_dump_pipe_config], pipe bpp: 0, dithering: 0 +[ 1.265053] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 1.265057] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 1.265060] [drm:intel_dump_pipe_config], requested mode: +[ 1.265063] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 +[ 1.265067] [drm:intel_dump_pipe_config], adjusted mode: +[ 1.265070] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 +[ 1.265074] [drm:intel_dump_crtc_timings], crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 +[ 1.265078] [drm:intel_dump_pipe_config], port clock: 0 +[ 1.265081] [drm:intel_dump_pipe_config], pipe src size: 0x0 +[ 1.265084] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +[ 1.265087] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 1.265090] [drm:intel_dump_pipe_config], ips: 0 +[ 1.265093] [drm:intel_dump_pipe_config], double wide: 0 +[ 1.265097] [drm:intel_dump_pipe_config], [CRTC:4][setup_hw_state] config for pipe B +[ 1.265100] [drm:intel_dump_pipe_config], cpu_transcoder: B +[ 1.265102] [drm:intel_dump_pipe_config], pipe bpp: 0, dithering: 0 +[ 1.265105] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 1.265109] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 1.265112] [drm:intel_dump_pipe_config], requested mode: +[ 1.265115] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 640 0 0 0 400 0 0 0 0x0 0x0 +[ 1.265119] [drm:intel_dump_pipe_config], adjusted mode: +[ 1.265122] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0xa +[ 1.265126] [drm:intel_dump_crtc_timings], crtc timings: 45982 1024 1048 1184 1344 768 779 1 806, type: 0x0 flags: 0xa +[ 1.265130] [drm:intel_dump_pipe_config], port clock: 45982 +[ 1.265133] [drm:intel_dump_pipe_config], pipe src size: 640x400 +[ 1.265136] [drm:intel_dump_pipe_config], gmch pfit: control: 0x80000220, ratios: 0x00000000, lvds border: 0x00000000 +[ 1.265139] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 1.265142] [drm:intel_dump_pipe_config], ips: 0 +[ 1.265145] [drm:intel_dump_pipe_config], double wide: 0 +[ 1.265149] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 1.265153] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 1.265157] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 1.265160] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 1.265163] [drm:check_crtc_state], [CRTC:3] +[ 1.265166] [drm:check_crtc_state], [CRTC:4] +[ 1.265183] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +[ 1.265187] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +[ 1.265204] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +[ 1.265208] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +[ 1.265213] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 1.265218] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 1.265222] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +[ 1.265227] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +[ 1.265232] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +[ 1.265235] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +[ 1.280167] [drm:intel_crt_detect], CRT not detected via hotplug +[ 1.284121] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +[ 1.284128] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 1.284131] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +[ 1.284134] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +[ 1.284413] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 1.284416] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +[ 1.284419] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +[ 1.284423] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +[ 1.284429] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +[ 1.284432] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +[ 1.284437] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 1.284441] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +[ 1.284454] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +[ 1.284460] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +[ 1.284464] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +[ 1.284467] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +[ 1.284470] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +[ 1.284473] [drm:intel_dump_pipe_config], cpu_transcoder: A +[ 1.284476] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +[ 1.284479] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 1.284483] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 1.284486] [drm:intel_dump_pipe_config], requested mode: +[ 1.284488] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 1.284493] [drm:intel_dump_pipe_config], adjusted mode: +[ 1.284496] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 1.284501] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +[ 1.284505] [drm:intel_dump_pipe_config], port clock: 108000 +[ 1.284508] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +[ 1.284511] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +[ 1.284514] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 1.284517] [drm:intel_dump_pipe_config], ips: 0 +[ 1.284520] [drm:intel_dump_pipe_config], double wide: 0 +[ 1.292029] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 5120 +[ 1.292040] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +[ 1.297668] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 1.297673] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 1.297676] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +[ 1.297679] [drm:intel_calculate_wm], FIFO watermark level: -5 +[ 1.297681] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 1 +[ 1.297685] [drm:i9xx_update_wm], self-refresh entries: 80 +[ 1.297687] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 1, C: 2, SR 47 +[ 1.297691] [drm:i9xx_update_wm], memory self refresh enabled +[ 1.320114] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 1.320123] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +[ 1.320128] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 1.320133] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 1.320138] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 1.320142] [drm:check_crtc_state], [CRTC:3] +[ 1.320155] [drm:check_crtc_state], [CRTC:4] +[ 1.360100] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +[ 1.360106] [drm:intel_tv_detect_type], Unrecognised TV connection +[ 1.376107] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 1.376114] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +[ 1.421067] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 1.421071] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 1.421074] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29 +[ 1.421077] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1 +[ 1.421080] [drm:i9xx_update_wm], memory self refresh disabled +[ 1.421087] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 1.421091] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 1.421094] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 1.421098] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 1.421101] [drm:check_crtc_state], [CRTC:3] +[ 1.421104] [drm:check_crtc_state], [CRTC:4] +[ 1.421246] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +[ 1.421251] [drm:drm_setup_crtcs], +[ 1.421254] [drm:drm_enable_connectors], connector 5 enabled? yes +[ 1.421257] [drm:drm_enable_connectors], connector 15 enabled? no +[ 1.421260] [drm:drm_enable_connectors], connector 17 enabled? no +[ 1.421263] [drm:drm_target_preferred], looking for cmdline mode on connector 5 +[ 1.421266] [drm:drm_target_preferred], looking for preferred mode on connector 5 +[ 1.421268] [drm:drm_target_preferred], found mode 1024x768 +[ 1.421271] [drm:drm_setup_crtcs], picking CRTCs for 4096x4096 config +[ 1.421275] [drm:drm_setup_crtcs], desired mode 1024x768 set on crtc 4 +[ 1.421281] [drm:i915_gem_object_create_stolen], creating stolen object: size=300000 +[ 1.421285] [drm:i915_pages_create_for_stolen], offset=0x20000, size=3145728 +[ 1.422732] [drm:intelfb_create], allocated 1024x768 fb: 0x00020000, bo ffff880035eaa300 +[ 1.422872] fbcon: inteldrmfb (fb0) is primary device +[ 1.423535] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] +[ 1.423538] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0 +[ 1.423541] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +[ 1.423544] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +[ 1.423546] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set +[ 1.423548] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set +[ 1.423552] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 +[ 1.423556] [drm:drm_mode_debug_printmodeline], Modeline 32:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +[ 1.423558] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=1, fb_changed=0 +[ 1.423560] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +[ 1.423563] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0 +[ 1.423566] [drm:connected_sink_compute_bpp], [CONNECTOR:5:LVDS-1] checking for sink bpp constrains +[ 1.423570] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18) +[ 1.423573] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1 +[ 1.423576] [drm:intel_dump_pipe_config], [CRTC:4][modeset] config for pipe B +[ 1.423577] [drm:intel_dump_pipe_config], cpu_transcoder: B +[ 1.423579] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 +[ 1.423582] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 1.423584] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 1.423586] [drm:intel_dump_pipe_config], requested mode: +[ 1.423589] [drm:drm_mode_debug_printmodeline], Modeline 0:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +[ 1.423591] [drm:intel_dump_pipe_config], adjusted mode: +[ 1.423595] [drm:drm_mode_debug_printmodeline], Modeline 0:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +[ 1.423598] [drm:intel_dump_crtc_timings], crtc timings: 54160 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa +[ 1.423600] [drm:intel_dump_pipe_config], port clock: 54160 +[ 1.423602] [drm:intel_dump_pipe_config], pipe src size: 1024x768 +[ 1.423604] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000008, ratios: 0x00000000, lvds border: 0x00000000 +[ 1.423607] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 1.423608] [drm:intel_dump_pipe_config], ips: 0 +[ 1.423610] [drm:intel_dump_pipe_config], double wide: 0 +[ 1.423613] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 +[ 1.457065] [drm:i9xx_pfit_disable], disabling pfit, current: 0x80000220 +[ 1.457069] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 1.457071] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 1.457073] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29 +[ 1.457076] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1 +[ 1.457077] [drm:i9xx_update_wm], memory self refresh disabled +[ 1.457082] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz +[ 1.457252] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096 +[ 1.457256] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:1024x768] +[ 1.457893] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 1.457895] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 1.457896] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 1.457898] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 1.457900] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +[ 1.457902] [drm:i9xx_update_wm], self-refresh entries: 64 +[ 1.457905] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +[ 1.457906] [drm:i9xx_update_wm], memory self refresh enabled +[ 1.650555] psmouse serio1: alps: Unknown ALPS touchpad: E7=10 00 64, EC=10 00 64 +[ 1.748270] firewire_core 0000:05:00.1: created device fw0: GUID 0000000000000000, S400 +[ 1.800110] [drm:intel_panel_enable_backlight], pipe B +[ 1.800114] [drm:intel_panel_actually_set_backlight], set backlight PWM = 24832 +[ 1.800120] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 1.800125] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 1.800129] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 1.800133] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 1.800136] [drm:check_crtc_state], [CRTC:3] +[ 1.800139] [drm:check_crtc_state], [CRTC:4] +[ 1.800178] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +[ 1.800182] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +[ 1.800186] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +[ 1.803473] Console: switching to colour frame buffer device 128x48 +[ 1.803478] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +[ 1.803481] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +[ 1.803483] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +[ 1.806832] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device +[ 1.806835] i915 0000:00:02.0: registered panic notifier +[ 1.806859] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0 +[ 1.806909] ahci 0000:00:1f.2: version 3.0 +[ 1.807136] ahci 0000:00:1f.2: irq 45 for MSI/MSI-X +[ 1.807190] ahci 0000:00:1f.2: SSS flag set, parallel bus scan disabled +[ 1.807222] ahci 0000:00:1f.2: AHCI 0001.0100 32 slots 4 ports 1.5 Gbps 0x1 impl SATA mode +[ 1.807228] ahci 0000:00:1f.2: flags: 64bit ncq ilck stag pm led clo pmp pio slum part +[ 1.808040] scsi2 : ahci +[ 1.808204] scsi3 : ahci +[ 1.808350] scsi4 : ahci +[ 1.808499] scsi5 : ahci +[ 1.808567] ata3: SATA max UDMA/133 abar m1024@0xe4344400 port 0xe4344500 irq 45 +[ 1.808570] ata4: DUMMY +[ 1.808572] ata5: DUMMY +[ 1.808574] ata6: DUMMY +[ 2.014396] psmouse serio1: trackpoint: IBM TrackPoint firmware: 0x0e, buttons: 3/3 +[ 2.033367] input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/input/input6 +[ 2.304119] ata3: SATA link up 1.5 Gbps (SStatus 113 SControl 300) +[ 2.305312] ata3.00: ATA-8: HITACHI HTS722010K9SA00, DC2ZC75A, max UDMA/133 +[ 2.305317] ata3.00: 195371568 sectors, multi 0: LBA48 NCQ (depth 31/32), AA +[ 2.306684] ata3.00: configured for UDMA/133 +[ 2.306893] scsi 2:0:0:0: Direct-Access ATA HITACHI HTS72201 DC2Z PQ: 0 ANSI: 5 +[ 2.307119] sd 2:0:0:0: Attached scsi generic sg0 type 0 +[ 2.307251] sd 2:0:0:0: [sda] 195371568 512-byte logical blocks: (100 GB/93.1 GiB) +[ 2.307395] sd 2:0:0:0: [sda] Write Protect is off +[ 2.307400] sd 2:0:0:0: [sda] Mode Sense: 00 3a 00 00 +[ 2.307477] sd 2:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA +[ 2.632829] sda: sda1 +[ 2.633271] sd 2:0:0:0: [sda] Attached SCSI disk +[ 2.784099] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +[ 2.784104] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +[ 2.784107] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +[ 2.908607] [drm:i915_gem_open], +[ 2.908634] [drm:intel_crtc_cursor_set], cursor off +[ 2.908638] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] +[ 2.908643] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0 +[ 2.908648] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +[ 2.908652] [drm:intel_crtc_cursor_set], cursor off +[ 2.908655] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +[ 2.908660] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +[ 2.908663] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +[ 2.908682] [drm:i915_gem_open], +[ 2.908697] [drm:intel_crtc_cursor_set], cursor off +[ 2.908700] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] +[ 2.908703] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0 +[ 2.908706] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +[ 2.908709] [drm:intel_crtc_cursor_set], cursor off +[ 2.908712] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +[ 2.908716] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +[ 2.908719] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +[ 2.908735] [drm:i915_gem_open], +[ 2.908824] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +[ 2.908830] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +[ 2.908841] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 2.908846] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +[ 2.908850] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +[ 2.908871] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +[ 2.908874] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +[ 2.908880] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 2.908885] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 2.908889] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +[ 2.908894] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +[ 2.908901] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 2.912519] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +[ 2.912529] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +[ 2.912533] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +[ 2.928108] [drm:intel_crt_detect], CRT not detected via hotplug +[ 2.932103] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +[ 2.932110] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 2.932115] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +[ 2.932118] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +[ 2.932404] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 2.932407] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +[ 2.932410] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +[ 2.932413] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +[ 2.932424] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +[ 2.932427] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +[ 2.932430] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +[ 2.948104] [drm:intel_crt_detect], CRT not detected via hotplug +[ 2.952104] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +[ 2.952111] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 2.952115] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +[ 2.952118] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +[ 2.952401] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 2.952403] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +[ 2.952406] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +[ 2.952409] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +[ 2.952420] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +[ 2.952423] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +[ 2.952427] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +[ 2.952431] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 2.952436] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +[ 2.952459] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +[ 2.952466] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +[ 2.952471] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +[ 2.952474] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +[ 2.952477] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +[ 2.952480] [drm:intel_dump_pipe_config], cpu_transcoder: A +[ 2.952483] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +[ 2.952486] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 2.952489] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 2.952493] [drm:intel_dump_pipe_config], requested mode: +[ 2.952495] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 2.952500] [drm:intel_dump_pipe_config], adjusted mode: +[ 2.952503] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 2.952508] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +[ 2.952512] [drm:intel_dump_pipe_config], port clock: 108000 +[ 2.952514] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +[ 2.952517] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +[ 2.952521] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 2.952524] [drm:intel_dump_pipe_config], ips: 0 +[ 2.952527] [drm:intel_dump_pipe_config], double wide: 0 +[ 2.959612] [drm:i9xx_update_plane], Writing base 00320000 00000000 0 0 5120 +[ 2.959624] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +[ 2.965254] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 2.965259] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 2.965261] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 2.965264] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 2.965267] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +[ 2.965270] [drm:intel_calculate_wm], FIFO watermark level: -5 +[ 2.965272] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +[ 2.965276] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +[ 2.965279] [drm:i9xx_update_wm], memory self refresh disabled +[ 2.988110] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 2.988118] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +[ 2.988123] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 2.988128] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 2.988133] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 2.988138] [drm:check_crtc_state], [CRTC:3] +[ 2.988151] [drm:check_crtc_state], [CRTC:4] +[ 3.028106] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +[ 3.028114] [drm:intel_tv_detect_type], Unrecognised TV connection +[ 3.044104] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 3.044113] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +[ 3.089061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 3.089065] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 3.089067] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 3.089070] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 3.089074] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +[ 3.089077] [drm:i9xx_update_wm], self-refresh entries: 64 +[ 3.089079] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +[ 3.089083] [drm:i9xx_update_wm], memory self refresh enabled +[ 3.089089] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 3.089094] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 3.089097] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 3.089100] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 3.089103] [drm:check_crtc_state], [CRTC:3] +[ 3.089106] [drm:check_crtc_state], [CRTC:4] +[ 3.089258] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +[ 3.090319] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +[ 3.090324] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +[ 3.090327] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +[ 3.090331] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 3.090335] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +[ 3.090351] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +[ 3.090356] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +[ 3.090359] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +[ 3.090362] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +[ 3.090365] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +[ 3.090369] [drm:intel_dump_pipe_config], cpu_transcoder: A +[ 3.090371] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +[ 3.090374] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 3.090378] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 3.090381] [drm:intel_dump_pipe_config], requested mode: +[ 3.090384] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 3.090389] [drm:intel_dump_pipe_config], adjusted mode: +[ 3.090391] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 3.090396] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +[ 3.090400] [drm:intel_dump_pipe_config], port clock: 108000 +[ 3.090403] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +[ 3.090406] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +[ 3.090409] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 3.090412] [drm:intel_dump_pipe_config], ips: 0 +[ 3.090415] [drm:intel_dump_pipe_config], double wide: 0 +[ 3.096851] [drm:i9xx_update_plane], Writing base 00320000 00000000 0 0 5120 +[ 3.096864] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +[ 3.102491] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 3.102495] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 3.102498] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 3.102501] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 3.102504] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +[ 3.102506] [drm:intel_calculate_wm], FIFO watermark level: -5 +[ 3.102509] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +[ 3.102512] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +[ 3.102515] [drm:i9xx_update_wm], memory self refresh disabled +[ 3.124103] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 3.124110] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +[ 3.124116] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 3.124121] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 3.124126] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 3.124131] [drm:check_crtc_state], [CRTC:3] +[ 3.124143] [drm:check_crtc_state], [CRTC:4] +[ 3.164099] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +[ 3.164104] [drm:intel_tv_detect_type], Unrecognised TV connection +[ 3.188098] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 3.188105] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +[ 3.229059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 3.229063] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 3.229065] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 3.229068] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 3.229071] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +[ 3.229075] [drm:i9xx_update_wm], self-refresh entries: 64 +[ 3.229077] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +[ 3.229081] [drm:i9xx_update_wm], memory self refresh enabled +[ 3.229086] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 3.229091] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 3.229094] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 3.229097] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 3.229100] [drm:check_crtc_state], [CRTC:3] +[ 3.229103] [drm:check_crtc_state], [CRTC:4] +[ 3.229256] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +[ 3.230324] [drm:drm_mode_addfb], [FB:34] +[ 3.603108] [drm:drm_mode_addfb], [FB:34] +[ 3.603201] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +[ 3.603207] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +[ 3.603211] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +[ 3.606628] [drm:drm_mode_setcrtc], [CRTC:4] +[ 3.606636] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1] +[ 3.606640] [drm:intel_crtc_set_config], [CRTC:4] [FB:34] #connectors=1 (x y) (0 0) +[ 3.606645] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=1 +[ 3.606648] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +[ 3.610935] [drm:i9xx_update_plane], Writing base 00320000 00000000 0 0 4096 +[ 3.627861] md: linear personality registered for level -1 +[ 3.628773] [drm:drm_mode_setcrtc], [CRTC:4] +[ 3.628782] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1] +[ 3.628787] [drm:intel_crtc_set_config], [CRTC:4] [FB:34] #connectors=1 (x y) (0 0) +[ 3.628793] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +[ 3.628797] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +[ 3.633141] md: multipath personality registered for level -4 +[ 3.638092] md: raid0 personality registered for level 0 +[ 3.643718] md: raid1 personality registered for level 1 +[ 3.716024] raid6: sse2x1 2266 MB/s +[ 3.784028] raid6: sse2x2 4053 MB/s +[ 3.852032] raid6: sse2x4 4547 MB/s +[ 3.852036] raid6: using algorithm sse2x4 (4547 MB/s) +[ 3.852038] raid6: using ssse3x2 recovery algorithm +[ 3.854266] xor: measuring software checksum speed +[ 3.892019] prefetch64-sse: 6047.000 MB/sec +[ 3.932018] generic_sse: 5363.000 MB/sec +[ 3.932021] xor: using function: prefetch64-sse (6047.000 MB/sec) +[ 3.934078] async_tx: api initialized (async) +[ 3.946437] md: raid6 personality registered for level 6 +[ 3.946441] md: raid5 personality registered for level 5 +[ 3.946444] md: raid4 personality registered for level 4 +[ 3.957827] md: raid10 personality registered for level 10 +[ 9.243505] random: cryptsetup urandom read with 119 bits of entropy available +[ 9.246108] random: nonblocking pool is initialized +[ 9.266100] bio: create slab at 1 +[ 9.513079] bio: create slab at 1 +[ 10.331147] bio: create slab at 2 +[ 10.332723] Btrfs loaded +[ 11.808132] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 15.403838] EXT4-fs (dm-1): INFO: recovery required on readonly filesystem +[ 15.403844] EXT4-fs (dm-1): write access will be enabled during recovery +[ 17.127673] EXT4-fs (dm-1): orphan cleanup on readonly fs +[ 17.127796] EXT4-fs (dm-1): 1 orphan inode deleted +[ 17.127800] EXT4-fs (dm-1): recovery complete +[ 17.216730] EXT4-fs (dm-1): mounted filesystem with ordered data mode. Opts: (null) +[ 21.824056] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 28.044685] EXT4-fs (dm-1): re-mounted. Opts: errors=remount-ro +[ 29.253227] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +[ 29.453218] systemd-udevd[569]: starting version 204 +[ 29.727869] lp: driver loaded but no devices found +[ 29.764157] ppdev: user-space parallel port driver +[ 30.065222] type=1400 audit(1409521824.544:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/cups/backend/cups-pdf" pid=647 comm="apparmor_parser" +[ 30.065234] type=1400 audit(1409521824.544:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/cupsd" pid=647 comm="apparmor_parser" +[ 30.065934] type=1400 audit(1409521824.544:4): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/sbin/cupsd" pid=647 comm="apparmor_parser" +[ 30.182531] Bluetooth: Core ver 2.17 +[ 30.184399] NET: Registered protocol family 31 +[ 30.184403] Bluetooth: HCI device and connection manager initialized +[ 30.184417] Bluetooth: HCI socket layer initialized +[ 30.184422] Bluetooth: L2CAP socket layer initialized +[ 30.184430] Bluetooth: SCO socket layer initialized +[ 30.216147] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 +[ 30.216153] Bluetooth: BNEP filters: protocol multicast +[ 30.216167] Bluetooth: BNEP socket layer initialized +[ 30.217692] Bluetooth: RFCOMM TTY layer initialized +[ 30.217701] Bluetooth: RFCOMM socket layer initialized +[ 30.217712] Bluetooth: RFCOMM ver 1.11 +[ 30.227989] intel_rng: FWH not detected +[ 30.348498] ACPI Warning: 0x0000000000000528-0x000000000000052f SystemIO conflicts with Region \PMIO 1 (20131115/utaddress-251) +[ 30.348510] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 30.348517] ACPI Warning: 0x00000000000004b0-0x00000000000004bf SystemIO conflicts with Region \GPIO 1 (20131115/utaddress-251) +[ 30.348522] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 30.348525] ACPI Warning: 0x0000000000000480-0x00000000000004af SystemIO conflicts with Region \GPIO 1 (20131115/utaddress-251) +[ 30.348530] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 30.348533] lpc_ich: Resource conflict(s) found affecting gpio_ich +[ 30.372503] leds_ss4200: no LED devices found +[ 30.372824] yenta_cardbus 0000:05:00.0: CardBus bridge found [0000:0000] +[ 30.398295] init: cups main process (656) killed by HUP signal +[ 30.398320] init: cups main process ended, respawning +[ 30.493456] type=1400 audit(1409521824.972:5): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/sbin/dhclient" pid=696 comm="apparmor_parser" +[ 30.493470] type=1400 audit(1409521824.972:6): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=696 comm="apparmor_parser" +[ 30.493478] type=1400 audit(1409521824.972:7): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=696 comm="apparmor_parser" +[ 30.496483] type=1400 audit(1409521824.976:8): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=696 comm="apparmor_parser" +[ 30.496497] type=1400 audit(1409521824.976:9): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=696 comm="apparmor_parser" +[ 30.496998] type=1400 audit(1409521824.976:10): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=696 comm="apparmor_parser" +[ 30.501113] yenta_cardbus 0000:05:00.0: ISA IRQ mask 0x0cb8, PCI irq 16 +[ 30.501120] yenta_cardbus 0000:05:00.0: Socket status: 30000006 +[ 30.501126] pci_bus 0000:05: Raising subordinate bus# of parent bus (#05) from #06 to #09 +[ 30.501295] yenta_cardbus 0000:05:00.0: pcmcia: parent PCI bridge window: [io 0x2000-0x3fff] +[ 30.501300] yenta_cardbus 0000:05:00.0: pcmcia: parent PCI bridge window: [mem 0xe0000000-0xe20fffff] +[ 30.501305] pcmcia_socket pcmcia_socket0: cs: memory probe 0xe0000000-0xe20fffff: +[ 30.501318] excluding 0xe1ef0000-0xe20fffff +[ 30.501325] yenta_cardbus 0000:05:00.0: pcmcia: parent PCI bridge window: [mem 0xe2100000-0xe40fffff 64bit pref] +[ 30.501329] pcmcia_socket pcmcia_socket0: cs: memory probe 0xe2100000-0xe40fffff: +[ 30.501411] excluding 0xe2100000-0xe40fffff +[ 30.761785] e1000e 0000:01:00.0: irq 44 for MSI/MSI-X +[ 30.772718] device-mapper: multipath: version 1.6.0 loaded +[ 30.841196] Non-volatile memory driver v1.3 +[ 30.846354] thinkpad_acpi: ThinkPad ACPI Extras v0.25 +[ 30.846360] thinkpad_acpi: http://ibm-acpi.sf.net/ +[ 30.846363] thinkpad_acpi: ThinkPad BIOS CBET4000 7BETC7WW (2.08 ), EC 7BHT37WW-3.4 +[ 30.846365] thinkpad_acpi: Lenovo ThinkPad X60s, model 1702L8G +[ 30.853545] thinkpad_acpi: detected a 8-level brightness capable ThinkPad +[ 30.853591] thinkpad_acpi: This ThinkPad has standard ACPI backlight brightness control, supported by the ACPI video driver +[ 30.853594] thinkpad_acpi: Disabling thinkpad-acpi brightness events by default... +[ 30.864133] e1000e 0000:01:00.0: irq 44 for MSI/MSI-X +[ 30.864654] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +[ 30.904471] thinkpad_acpi: Standard ACPI backlight interface available, not loading native one +[ 30.904716] thinkpad_acpi: Console audio control enabled, mode: monitor (read only) +[ 30.917451] input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input7 +[ 31.070696] hda_intel: probe_mask set to 0x1 for device 17aa:2010 +[ 31.070755] snd_hda_intel 0000:00:1b.0: irq 46 for MSI/MSI-X +[ 31.221006] autoconfig: line_outs=1 (0x5/0x0/0x0/0x0/0x0) type:line +[ 31.221013] speaker_outs=1 (0x7/0x0/0x0/0x0/0x0) +[ 31.221016] hp_outs=1 (0x6/0x0/0x0/0x0/0x0) +[ 31.221018] mono: mono_out=0x0 +[ 31.221020] dig-out=0xa/0x0 +[ 31.221022] inputs: +[ 31.221073] Rear Mic=0x18 +[ 31.221076] Front Mic=0x8 +[ 31.221079] Line=0x9 +[ 31.221081] CD=0x19 +[ 31.221084] Aux=0x17 +[ 31.306204] input: HDA Intel Front Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input12 +[ 31.309615] input: HDA Intel Line Out as /devices/pci0000:00/0000:00:1b.0/sound/card0/input11 +[ 31.312192] input: HDA Intel Line as /devices/pci0000:00/0000:00:1b.0/sound/card0/input10 +[ 31.316499] input: HDA Intel Front Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9 +[ 31.316647] input: HDA Intel Rear Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input8 +[ 31.491549] pcmcia_socket pcmcia_socket0: cs: memory probe 0x0c0000-0x0fffff: +[ 31.491580] excluding 0xf0000-0xfffff +[ 31.491611] pcmcia_socket pcmcia_socket0: cs: memory probe 0xa0000000-0xa0ffffff: +[ 31.491646] clean. +[ 31.491672] pcmcia_socket pcmcia_socket0: cs: memory probe 0x60000000-0x60ffffff: +[ 31.491705] excluding 0x60000000-0x60ffffff +[ 31.840110] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 41.856122] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 51.872113] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 60.227922] type=1400 audit(1409521854.704:11): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/cups/backend/cups-pdf" pid=1132 comm="apparmor_parser" +[ 60.227937] type=1400 audit(1409521854.704:12): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/sbin/cupsd" pid=1132 comm="apparmor_parser" +[ 60.228674] type=1400 audit(1409521854.708:13): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/sbin/cupsd" pid=1132 comm="apparmor_parser" +[ 60.787283] type=1400 audit(1409521855.264:14): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/cups-browsed" pid=1143 comm="apparmor_parser" +[ 61.888127] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 70.140147] usb 1-1: new high-speed USB device number 2 using ehci-pci +[ 70.289002] usb 1-1: New USB device found, idVendor=0cf3, idProduct=9271 +[ 70.289008] usb 1-1: New USB device strings: Mfr=16, Product=32, SerialNumber=48 +[ 70.289012] usb 1-1: Product: UB93 +[ 70.289015] usb 1-1: Manufacturer: ATHEROS +[ 70.289019] usb 1-1: SerialNumber: 12345 +[ 70.441093] cfg80211: Calling CRDA to update world regulatory domain +[ 70.579584] cfg80211: World regulatory domain updated: +[ 70.579590] cfg80211: (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp) +[ 70.579594] cfg80211: (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) +[ 70.579598] cfg80211: (2457000 KHz - 2482000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) +[ 70.579601] cfg80211: (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm) +[ 70.579604] cfg80211: (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) +[ 70.579607] cfg80211: (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) +[ 70.613130] usb 1-1: ath9k_htc: Firmware htc_9271.fw requested +[ 70.613246] usbcore: registered new interface driver ath9k_htc +[ 70.909647] usb 1-1: ath9k_htc: Transferred FW: htc_9271.fw, size: 50980 +[ 71.150263] ath9k_htc 1-1:1.0: ath9k_htc: HTC initialized with 33 credits +[ 71.418766] ath9k_htc 1-1:1.0: ath9k_htc: FW Version: 1.3 +[ 71.418770] ath: EEPROM regdomain: 0x65 +[ 71.418773] ath: EEPROM indicates we should expect a direct regpair map +[ 71.418777] ath: Country alpha2 being used: 00 +[ 71.418779] ath: Regpair used: 0x65 +[ 71.460149] ieee80211 phy0: Atheros AR9271 Rev:1 +[ 71.904067] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 79.945375] usb 1-1: USB disconnect, device number 2 +[ 80.151202] usb 1-1: ath9k_htc: USB layer deinitialized +[ 81.920129] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 91.936033] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 101.952108] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 111.968120] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 121.984105] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 132.000103] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 142.016108] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 149.297093] e1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx +[ 149.297248] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready +[ 151.231682] init: failsafe main process (837) killed by TERM signal +[ 151.489247] type=1400 audit(1409521945.968:15): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/sbin/dhclient" pid=1314 comm="apparmor_parser" +[ 151.489262] type=1400 audit(1409521945.968:16): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=1314 comm="apparmor_parser" +[ 151.489271] type=1400 audit(1409521945.968:17): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=1314 comm="apparmor_parser" +[ 151.490046] type=1400 audit(1409521945.968:18): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=1314 comm="apparmor_parser" +[ 151.490055] type=1400 audit(1409521945.968:19): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=1314 comm="apparmor_parser" +[ 151.490416] type=1400 audit(1409521945.968:20): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=1314 comm="apparmor_parser" +[ 151.495908] type=1400 audit(1409521945.972:21): apparmor="STATUS" operation="profile_load" profile="unconfined" name="system_tor" pid=1315 comm="apparmor_parser" +[ 151.500387] type=1400 audit(1409521945.980:22): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/lightdm/lightdm-guest-session" pid=1313 comm="apparmor_parser" +[ 151.500398] type=1400 audit(1409521945.980:23): apparmor="STATUS" operation="profile_load" profile="unconfined" name="chromium" pid=1313 comm="apparmor_parser" +[ 151.500825] type=1400 audit(1409521945.980:24): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="chromium" pid=1313 comm="apparmor_parser" +[ 152.032044] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 152.229628] init: lxdm main process (1372) killed by TERM signal +[ 153.407166] [drm:i915_gem_open], +[ 154.128716] [drm:i915_gem_open], +[ 154.128739] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +[ 154.129127] [drm:i915_gem_open], +[ 154.129142] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +[ 154.129149] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +[ 154.130884] [drm:drm_mode_addfb], [FB:35] +[ 154.131523] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +[ 154.131530] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +[ 154.131585] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 154.131595] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 154.131939] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +[ 154.131949] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +[ 154.131987] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +[ 154.131996] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +[ 154.256944] [drm:drm_mode_addfb], [FB:35] +[ 154.256966] [drm:drm_mode_setcrtc], [CRTC:4] +[ 154.256976] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1] +[ 154.256980] [drm:intel_crtc_set_config], [CRTC:4] [FB:35] #connectors=1 (x y) (0 0) +[ 154.256986] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=1 +[ 154.256991] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +[ 154.258670] [drm:i9xx_update_plane], Writing base 00800000 00000000 0 0 4096 +[ 154.543643] init: plymouth-upstart-bridge main process (377) killed by TERM signal +[ 158.275793] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 158.275804] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +[ 158.275809] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +[ 158.275832] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +[ 158.275836] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +[ 158.275841] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 158.275846] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 158.275851] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +[ 158.275856] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +[ 158.275865] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 158.276430] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +[ 158.276435] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +[ 158.276439] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +[ 158.288160] [drm:intel_crt_detect], CRT not detected via hotplug +[ 158.292045] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +[ 158.292055] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 158.292059] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +[ 158.292062] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +[ 158.292346] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 158.292349] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +[ 158.292352] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +[ 158.292358] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +[ 158.292396] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +[ 158.292401] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +[ 158.292404] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +[ 158.292410] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 158.292414] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +[ 158.292433] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +[ 158.292439] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +[ 158.292443] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +[ 158.292447] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +[ 158.292450] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +[ 158.292454] [drm:intel_dump_pipe_config], cpu_transcoder: A +[ 158.292457] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +[ 158.292459] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 158.292463] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 158.292467] [drm:intel_dump_pipe_config], requested mode: +[ 158.292469] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 158.292475] [drm:intel_dump_pipe_config], adjusted mode: +[ 158.292477] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 158.292482] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +[ 158.292486] [drm:intel_dump_pipe_config], port clock: 108000 +[ 158.292489] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +[ 158.292492] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +[ 158.292495] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 158.292499] [drm:intel_dump_pipe_config], ips: 0 +[ 158.292501] [drm:intel_dump_pipe_config], double wide: 0 +[ 158.300167] [drm:i9xx_update_plane], Writing base 00C00000 00000000 0 0 5120 +[ 158.300181] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +[ 158.305816] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 158.305823] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 158.305825] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 158.305828] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 158.305832] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +[ 158.305834] [drm:intel_calculate_wm], FIFO watermark level: -5 +[ 158.305837] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +[ 158.305840] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +[ 158.305844] [drm:i9xx_update_wm], memory self refresh disabled +[ 158.324056] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 158.324066] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +[ 158.324071] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 158.324074] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 158.324078] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 158.324081] [drm:check_crtc_state], [CRTC:3] +[ 158.324093] [drm:check_crtc_state], [CRTC:4] +[ 158.376040] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +[ 158.376049] [drm:intel_tv_detect_type], Unrecognised TV connection +[ 158.392042] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 158.392052] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +[ 158.433012] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 158.433022] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 158.433025] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 158.433028] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 158.433031] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +[ 158.433034] [drm:i9xx_update_wm], self-refresh entries: 64 +[ 158.433037] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +[ 158.433041] [drm:i9xx_update_wm], memory self refresh enabled +[ 158.433052] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 158.433058] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 158.433061] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 158.433065] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 158.433068] [drm:check_crtc_state], [CRTC:3] +[ 158.433072] [drm:check_crtc_state], [CRTC:4] +[ 158.433226] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +[ 158.887022] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +[ 158.887071] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +[ 158.887077] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 158.887081] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +[ 158.887098] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +[ 158.887104] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +[ 158.887108] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +[ 158.887112] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +[ 158.887115] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +[ 158.887118] [drm:intel_dump_pipe_config], cpu_transcoder: A +[ 158.887121] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +[ 158.887124] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 158.887128] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 158.887131] [drm:intel_dump_pipe_config], requested mode: +[ 158.887134] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 158.887139] [drm:intel_dump_pipe_config], adjusted mode: +[ 158.887142] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 158.887147] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +[ 158.887151] [drm:intel_dump_pipe_config], port clock: 108000 +[ 158.887154] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +[ 158.887157] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +[ 158.887160] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 158.887164] [drm:intel_dump_pipe_config], ips: 0 +[ 158.887167] [drm:intel_dump_pipe_config], double wide: 0 +[ 158.895657] [drm:i9xx_update_plane], Writing base 00C00000 00000000 0 0 5120 +[ 158.895671] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +[ 158.901303] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 158.901308] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 158.901310] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 158.901313] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 158.901317] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +[ 158.901319] [drm:intel_calculate_wm], FIFO watermark level: -5 +[ 158.901322] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +[ 158.901325] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +[ 158.901328] [drm:i9xx_update_wm], memory self refresh disabled +[ 158.924049] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 158.924061] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +[ 158.924065] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 158.924069] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 158.924072] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 158.924076] [drm:check_crtc_state], [CRTC:3] +[ 158.924086] [drm:check_crtc_state], [CRTC:4] +[ 158.964043] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +[ 158.964051] [drm:intel_tv_detect_type], Unrecognised TV connection +[ 158.984046] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 158.984058] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +[ 159.033005] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 159.033015] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 159.033018] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 159.033021] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 159.033025] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +[ 159.033028] [drm:i9xx_update_wm], self-refresh entries: 64 +[ 159.033031] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +[ 159.033035] [drm:i9xx_update_wm], memory self refresh enabled +[ 159.033047] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 159.033053] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 159.033057] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 159.033060] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 159.033064] [drm:check_crtc_state], [CRTC:3] +[ 159.033067] [drm:check_crtc_state], [CRTC:4] +[ 159.034333] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +[ 159.056046] [drm:intel_crt_detect], CRT not detected via hotplug +[ 159.060079] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +[ 159.060087] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 159.060091] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +[ 159.060094] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +[ 159.060374] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 159.060377] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +[ 159.060380] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +[ 162.048052] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 168.846014] [drm:i915_gem_open], +[ 169.194795] [drm:i915_gem_open], +[ 169.249719] [drm:i915_gem_open], +[ 169.283957] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 169.283968] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +[ 169.283973] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +[ 169.283995] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +[ 169.284035] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +[ 169.284041] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 169.284046] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 169.284051] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +[ 169.284055] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +[ 169.284065] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 169.284300] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +[ 169.284305] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +[ 169.284308] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +[ 169.300132] [drm:intel_crt_detect], CRT not detected via hotplug +[ 169.304126] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +[ 169.304134] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 169.304138] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +[ 169.304142] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +[ 169.304438] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 169.304441] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +[ 169.304445] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +[ 169.304449] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +[ 169.304503] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +[ 169.304508] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +[ 169.304512] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +[ 169.304516] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 169.304521] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +[ 169.304535] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +[ 169.304541] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +[ 169.304544] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +[ 169.304548] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +[ 169.304551] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +[ 169.304554] [drm:intel_dump_pipe_config], cpu_transcoder: A +[ 169.304557] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +[ 169.304560] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 169.304563] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 169.304567] [drm:intel_dump_pipe_config], requested mode: +[ 169.304569] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 169.304575] [drm:intel_dump_pipe_config], adjusted mode: +[ 169.304577] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 169.304582] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +[ 169.304586] [drm:intel_dump_pipe_config], port clock: 108000 +[ 169.304589] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +[ 169.304592] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +[ 169.304595] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 169.304599] [drm:intel_dump_pipe_config], ips: 0 +[ 169.304601] [drm:intel_dump_pipe_config], double wide: 0 +[ 169.312528] [drm:i9xx_update_plane], Writing base 02800000 00000000 0 0 5120 +[ 169.312539] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +[ 169.318168] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 169.318172] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 169.318175] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 169.318178] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 169.318181] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +[ 169.318184] [drm:intel_calculate_wm], FIFO watermark level: -5 +[ 169.318187] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +[ 169.318190] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +[ 169.318193] [drm:i9xx_update_wm], memory self refresh disabled +[ 169.340052] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 169.340063] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +[ 169.340070] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 169.340075] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 169.340080] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 169.340085] [drm:check_crtc_state], [CRTC:3] +[ 169.340098] [drm:check_crtc_state], [CRTC:4] +[ 169.380054] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +[ 169.380062] [drm:intel_tv_detect_type], Unrecognised TV connection +[ 169.424049] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 169.424058] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +[ 169.465004] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 169.465012] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 169.465015] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 169.465018] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 169.465021] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +[ 169.465025] [drm:i9xx_update_wm], self-refresh entries: 64 +[ 169.465028] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +[ 169.465031] [drm:i9xx_update_wm], memory self refresh enabled +[ 169.465043] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 169.465048] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 169.465052] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 169.465055] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 169.465059] [drm:check_crtc_state], [CRTC:3] +[ 169.465062] [drm:check_crtc_state], [CRTC:4] +[ 169.465213] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +[ 169.535204] [drm:intel_crtc_cursor_set], cursor off +[ 169.646187] [drm:intel_crtc_cursor_set], cursor off +[ 170.257502] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 170.257514] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +[ 170.257520] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +[ 170.257543] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +[ 170.257547] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +[ 170.257553] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 170.257558] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 170.257563] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +[ 170.257568] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +[ 170.257576] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 170.257806] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +[ 170.257811] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +[ 170.257815] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +[ 170.272041] [drm:intel_crt_detect], CRT not detected via hotplug +[ 170.276070] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +[ 170.276077] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 170.276080] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +[ 170.276083] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +[ 170.276360] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 170.276363] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +[ 170.276366] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +[ 170.276370] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +[ 170.276393] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +[ 170.276397] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +[ 170.276401] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +[ 170.276405] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 170.276410] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +[ 170.276424] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +[ 170.276430] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +[ 170.276433] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +[ 170.276437] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +[ 170.276440] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +[ 170.276443] [drm:intel_dump_pipe_config], cpu_transcoder: A +[ 170.276446] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +[ 170.276449] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 170.276453] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 170.276456] [drm:intel_dump_pipe_config], requested mode: +[ 170.276459] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 170.276464] [drm:intel_dump_pipe_config], adjusted mode: +[ 170.276467] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 170.276472] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +[ 170.276476] [drm:intel_dump_pipe_config], port clock: 108000 +[ 170.276479] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +[ 170.276482] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +[ 170.276485] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 170.276488] [drm:intel_dump_pipe_config], ips: 0 +[ 170.276491] [drm:intel_dump_pipe_config], double wide: 0 +[ 170.283303] [drm:i9xx_update_plane], Writing base 02800000 00000000 0 0 5120 +[ 170.283314] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +[ 170.288947] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 170.288952] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 170.288954] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 170.288958] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 170.288961] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +[ 170.288963] [drm:intel_calculate_wm], FIFO watermark level: -5 +[ 170.288966] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +[ 170.288969] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +[ 170.288972] [drm:i9xx_update_wm], memory self refresh disabled +[ 170.328052] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 170.328061] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +[ 170.328066] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 170.328069] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 170.328073] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 170.328076] [drm:check_crtc_state], [CRTC:3] +[ 170.328087] [drm:check_crtc_state], [CRTC:4] +[ 170.368047] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +[ 170.368054] [drm:intel_tv_detect_type], Unrecognised TV connection +[ 170.384041] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 170.384048] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +[ 170.429004] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 170.429010] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 170.429013] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 170.429016] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 170.429020] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +[ 170.429023] [drm:i9xx_update_wm], self-refresh entries: 64 +[ 170.429026] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +[ 170.429029] [drm:i9xx_update_wm], memory self refresh enabled +[ 170.429043] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 170.429048] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 170.429052] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 170.429055] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 170.429058] [drm:check_crtc_state], [CRTC:3] +[ 170.429062] [drm:check_crtc_state], [CRTC:4] +[ 170.429212] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +[ 171.084188] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 171.084198] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +[ 171.084203] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +[ 171.084225] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +[ 171.084229] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +[ 171.084235] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 171.084240] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 171.084245] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +[ 171.084249] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +[ 171.084258] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 171.084505] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +[ 171.084510] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +[ 171.084514] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +[ 171.100045] [drm:intel_crt_detect], CRT not detected via hotplug +[ 171.104195] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +[ 171.104204] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 171.104207] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +[ 171.104210] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +[ 171.104487] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 171.104490] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +[ 171.104494] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +[ 171.104498] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +[ 171.104532] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +[ 171.104537] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +[ 171.104541] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +[ 171.104546] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 171.104550] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +[ 171.104568] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +[ 171.104574] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +[ 171.104577] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +[ 171.104581] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +[ 171.104584] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +[ 171.104588] [drm:intel_dump_pipe_config], cpu_transcoder: A +[ 171.104590] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +[ 171.104593] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 171.104597] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 171.104600] [drm:intel_dump_pipe_config], requested mode: +[ 171.104603] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 171.104608] [drm:intel_dump_pipe_config], adjusted mode: +[ 171.104611] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 171.104616] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +[ 171.104620] [drm:intel_dump_pipe_config], port clock: 108000 +[ 171.104623] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +[ 171.104626] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +[ 171.104629] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 171.104633] [drm:intel_dump_pipe_config], ips: 0 +[ 171.104635] [drm:intel_dump_pipe_config], double wide: 0 +[ 171.113463] [drm:i9xx_update_plane], Writing base 02800000 00000000 0 0 5120 +[ 171.113476] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +[ 171.119107] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 171.119112] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 171.119115] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 171.119118] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 171.119122] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +[ 171.119124] [drm:intel_calculate_wm], FIFO watermark level: -5 +[ 171.119127] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +[ 171.119130] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +[ 171.119133] [drm:i9xx_update_wm], memory self refresh disabled +[ 171.144051] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 171.144061] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +[ 171.144065] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 171.144069] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 171.144073] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 171.144076] [drm:check_crtc_state], [CRTC:3] +[ 171.144087] [drm:check_crtc_state], [CRTC:4] +[ 171.212055] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +[ 171.212063] [drm:intel_tv_detect_type], Unrecognised TV connection +[ 171.228056] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 171.228066] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +[ 171.269008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 171.269017] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 171.269020] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 171.269023] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 171.269026] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +[ 171.269029] [drm:i9xx_update_wm], self-refresh entries: 64 +[ 171.269032] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +[ 171.269036] [drm:i9xx_update_wm], memory self refresh enabled +[ 171.271055] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 171.271062] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 171.271065] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 171.271069] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 171.271072] [drm:check_crtc_state], [CRTC:3] +[ 171.271076] [drm:check_crtc_state], [CRTC:4] +[ 171.271234] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +[ 171.449390] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 171.449401] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +[ 171.449406] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +[ 171.449429] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +[ 171.449433] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +[ 171.449439] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 171.449444] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 171.449449] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +[ 171.449453] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +[ 171.449462] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 171.449715] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +[ 171.449720] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +[ 171.449724] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +[ 171.464239] [drm:intel_crt_detect], CRT not detected via hotplug +[ 171.468039] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +[ 171.468046] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 171.468050] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +[ 171.468053] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +[ 171.468335] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 171.468338] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +[ 171.468341] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +[ 171.468346] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +[ 171.468379] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +[ 171.468384] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +[ 171.468388] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +[ 171.468393] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 171.468397] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +[ 171.468414] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +[ 171.468420] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +[ 171.468424] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +[ 171.468427] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +[ 171.468431] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +[ 171.468434] [drm:intel_dump_pipe_config], cpu_transcoder: A +[ 171.468437] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +[ 171.468440] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 171.468443] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 171.468447] [drm:intel_dump_pipe_config], requested mode: +[ 171.468450] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 171.468455] [drm:intel_dump_pipe_config], adjusted mode: +[ 171.468458] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 171.468462] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +[ 171.468467] [drm:intel_dump_pipe_config], port clock: 108000 +[ 171.468469] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +[ 171.468472] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +[ 171.468476] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 171.468479] [drm:intel_dump_pipe_config], ips: 0 +[ 171.468482] [drm:intel_dump_pipe_config], double wide: 0 +[ 171.475659] [drm:i9xx_update_plane], Writing base 02860000 00000000 0 0 5120 +[ 171.475670] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +[ 171.481311] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 171.481317] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 171.481320] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 171.481323] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 171.481326] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +[ 171.481329] [drm:intel_calculate_wm], FIFO watermark level: -5 +[ 171.481331] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +[ 171.481335] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +[ 171.481338] [drm:i9xx_update_wm], memory self refresh disabled +[ 171.504105] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 171.504115] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +[ 171.504119] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 171.504123] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 171.504127] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 171.504130] [drm:check_crtc_state], [CRTC:3] +[ 171.504141] [drm:check_crtc_state], [CRTC:4] +[ 171.568041] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +[ 171.568048] [drm:intel_tv_detect_type], Unrecognised TV connection +[ 171.628046] [drm:intel_wait_for_vblank], vblank wait timed out +[ 171.628054] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 171.628059] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +[ 171.673007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 171.673014] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 171.673017] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 171.673020] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 171.673023] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +[ 171.673027] [drm:i9xx_update_wm], self-refresh entries: 64 +[ 171.673029] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +[ 171.673033] [drm:i9xx_update_wm], memory self refresh enabled +[ 171.673133] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 171.673139] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 171.673143] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 171.673147] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 171.673151] [drm:check_crtc_state], [CRTC:3] +[ 171.673154] [drm:check_crtc_state], [CRTC:4] +[ 171.673361] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +[ 171.676431] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 171.676439] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +[ 171.676444] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +[ 171.676465] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +[ 171.676468] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +[ 171.676474] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 171.676479] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 171.676483] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +[ 171.676488] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +[ 171.676497] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 171.676719] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +[ 171.676724] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +[ 171.676727] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +[ 171.692056] [drm:intel_crt_detect], CRT not detected via hotplug +[ 171.697188] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +[ 171.697197] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 171.697201] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +[ 171.697203] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +[ 171.697483] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 171.697486] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +[ 171.697489] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +[ 171.697494] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +[ 171.697528] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +[ 171.697534] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +[ 171.697537] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +[ 171.697542] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 171.697546] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +[ 171.697564] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +[ 171.697570] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +[ 171.697574] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +[ 171.697578] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +[ 171.697581] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +[ 171.697585] [drm:intel_dump_pipe_config], cpu_transcoder: A +[ 171.697588] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +[ 171.697590] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 171.697594] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 171.697598] [drm:intel_dump_pipe_config], requested mode: +[ 171.697600] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 171.697605] [drm:intel_dump_pipe_config], adjusted mode: +[ 171.697608] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 171.697613] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +[ 171.697617] [drm:intel_dump_pipe_config], port clock: 108000 +[ 171.697620] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +[ 171.697623] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +[ 171.697626] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 171.697629] [drm:intel_dump_pipe_config], ips: 0 +[ 171.697632] [drm:intel_dump_pipe_config], double wide: 0 +[ 171.705575] [drm:i9xx_update_plane], Writing base 02860000 00000000 0 0 5120 +[ 171.705587] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +[ 171.711217] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 171.711221] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 171.711224] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 171.711227] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 171.711230] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +[ 171.711233] [drm:intel_calculate_wm], FIFO watermark level: -5 +[ 171.711235] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +[ 171.711239] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +[ 171.711242] [drm:i9xx_update_wm], memory self refresh disabled +[ 171.732081] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 171.732087] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +[ 171.732091] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 171.732095] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 171.732098] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 171.732102] [drm:check_crtc_state], [CRTC:3] +[ 171.732112] [drm:check_crtc_state], [CRTC:4] +[ 171.772048] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +[ 171.772053] [drm:intel_tv_detect_type], Unrecognised TV connection +[ 171.788030] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 171.788036] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +[ 171.837008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 171.837016] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 171.837019] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 171.837022] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 171.837026] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +[ 171.837029] [drm:i9xx_update_wm], self-refresh entries: 64 +[ 171.837032] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +[ 171.837035] [drm:i9xx_update_wm], memory self refresh enabled +[ 171.837045] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 171.837050] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 171.837053] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 171.837057] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 171.837060] [drm:check_crtc_state], [CRTC:3] +[ 171.837064] [drm:check_crtc_state], [CRTC:4] +[ 171.837214] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +[ 171.997747] [drm:drm_mode_addfb], [FB:34] +[ 172.064040] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 182.080084] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 191.573667] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 191.573678] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +[ 191.573684] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +[ 191.573706] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +[ 191.573710] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +[ 191.573715] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 191.573720] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +[ 191.573725] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +[ 191.573730] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +[ 191.573739] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +[ 191.573976] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +[ 191.573980] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +[ 191.573984] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +[ 191.596041] [drm:intel_crt_detect], CRT not detected via hotplug +[ 191.600059] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +[ 191.600066] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 191.600070] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +[ 191.600072] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +[ 191.600350] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +[ 191.600353] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +[ 191.600356] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +[ 191.600359] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +[ 191.600384] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +[ 191.600388] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +[ 191.600392] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +[ 191.600397] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 191.600401] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +[ 191.600417] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +[ 191.600423] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +[ 191.600426] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +[ 191.600429] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +[ 191.600433] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +[ 191.600436] [drm:intel_dump_pipe_config], cpu_transcoder: A +[ 191.600439] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +[ 191.600442] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 191.600445] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +[ 191.600449] [drm:intel_dump_pipe_config], requested mode: +[ 191.600452] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 191.600457] [drm:intel_dump_pipe_config], adjusted mode: +[ 191.600459] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +[ 191.600464] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +[ 191.600468] [drm:intel_dump_pipe_config], port clock: 108000 +[ 191.600471] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +[ 191.600474] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +[ 191.600477] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +[ 191.600481] [drm:intel_dump_pipe_config], ips: 0 +[ 191.600484] [drm:intel_dump_pipe_config], double wide: 0 +[ 191.607207] [drm:i9xx_update_plane], Writing base 05040000 00000000 0 0 5120 +[ 191.607218] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +[ 191.612854] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 191.612859] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 191.612862] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 191.612865] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 191.612868] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +[ 191.612870] [drm:intel_calculate_wm], FIFO watermark level: -5 +[ 191.612873] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +[ 191.612876] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +[ 191.612880] [drm:i9xx_update_wm], memory self refresh disabled +[ 191.636051] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 191.636059] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +[ 191.636063] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 191.636066] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 191.636070] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 191.636073] [drm:check_crtc_state], [CRTC:3] +[ 191.636083] [drm:check_crtc_state], [CRTC:4] +[ 191.676047] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +[ 191.676053] [drm:intel_tv_detect_type], Unrecognised TV connection +[ 191.692041] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +[ 191.692047] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +[ 191.745006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +[ 191.745014] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +[ 191.745017] [drm:intel_calculate_wm], FIFO watermark level: 9 +[ 191.745020] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +[ 191.745024] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +[ 191.745027] [drm:i9xx_update_wm], self-refresh entries: 64 +[ 191.745030] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +[ 191.745034] [drm:i9xx_update_wm], memory self refresh enabled +[ 191.745045] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +[ 191.745050] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +[ 191.745053] [drm:check_encoder_state], [ENCODER:16:DAC-16] +[ 191.745057] [drm:check_encoder_state], [ENCODER:18:TV-18] +[ 191.745060] [drm:check_crtc_state], [CRTC:3] +[ 191.745064] [drm:check_crtc_state], [CRTC:4] +[ 191.745217] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +[ 192.096128] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 202.112100] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 212.128145] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 222.144192] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 232.160064] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 242.176124] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 251.926550] [drm:intel_crtc_cursor_set], cursor off +[ 252.192155] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 262.208177] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 272.224155] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 282.240058] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 288.627538] [drm:i915_gem_open], +[ 292.256054] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 302.272054] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 312.288157] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 322.304125] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 332.320142] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 333.456176] usb 1-5: new high-speed USB device number 3 using ehci-pci +[ 333.589307] usb 1-5: New USB device found, idVendor=8644, idProduct=8003 +[ 333.589312] usb 1-5: New USB device strings: Mfr=1, Product=2, SerialNumber=3 +[ 333.589317] usb 1-5: Product: USB Flash Disk +[ 333.589320] usb 1-5: Manufacturer: General +[ 333.589323] usb 1-5: SerialNumber: 04040310000181F6 +[ 333.679670] usb-storage 1-5:1.0: USB Mass Storage device detected +[ 333.679783] scsi6 : usb-storage 1-5:1.0 +[ 333.679899] usbcore: registered new interface driver usb-storage +[ 334.676977] scsi 6:0:0:0: Direct-Access General USB Flash Disk 1.00 PQ: 0 ANSI: 2 +[ 334.677369] sd 6:0:0:0: Attached scsi generic sg1 type 0 +[ 334.678067] sd 6:0:0:0: [sdb] 15669248 512-byte logical blocks: (8.02 GB/7.47 GiB) +[ 334.679430] sd 6:0:0:0: [sdb] Write Protect is off +[ 334.679436] sd 6:0:0:0: [sdb] Mode Sense: 03 00 00 00 +[ 334.680147] sd 6:0:0:0: [sdb] No Caching mode page found +[ 334.680153] sd 6:0:0:0: [sdb] Assuming drive cache: write through +[ 334.685053] sd 6:0:0:0: [sdb] No Caching mode page found +[ 334.685059] sd 6:0:0:0: [sdb] Assuming drive cache: write through +[ 334.687362] sdb: sdb1 +[ 334.690313] sd 6:0:0:0: [sdb] No Caching mode page found +[ 334.690318] sd 6:0:0:0: [sdb] Assuming drive cache: write through +[ 334.690323] sd 6:0:0:0: [sdb] Attached SCSI removable disk +[ 342.336060] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 343.641289] systemd-hostnamed[2780]: Warning: nss-myhostname is not installed. Changing the local hostname might make it unresolveable. Please install nss-myhostname! +[ 347.448355] FAT-fs (sdb1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck. +[ 352.352127] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +[ 353.599097] [drm:intel_crtc_cursor_set], cursor off +[ 362.368145] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 diff --git a/i18n/fr_FR/docs/future/dumps/pte_x60_6718/kern.log b/i18n/fr_FR/docs/future/dumps/pte_x60_6718/kern.log new file mode 100644 index 00000000..b74142a5 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/pte_x60_6718/kern.log @@ -0,0 +1,2026 @@ +Aug 31 01:30:17 minifree kernel: [ 2923.992095] perf samples too long (2511 > 2500), lowering kernel.perf_event_max_sample_rate to 50000 +Aug 31 22:50:24 minifree kernel: [ 0.000000] Initializing cgroup subsys cpuset +Aug 31 22:50:24 minifree kernel: [ 0.000000] Initializing cgroup subsys cpu +Aug 31 22:50:24 minifree kernel: [ 0.000000] Initializing cgroup subsys cpuacct +Aug 31 22:50:24 minifree kernel: [ 0.000000] Linux version 3.13.0-34-generic (root@devel.trisquel.info) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #0trisquel2 SMP Wed Aug 27 02:19:14 UTC 2014 (Ubuntu 3.13.0-34.60+7.0trisquel2-generic 3.13.11.4-gnu) +Aug 31 22:50:24 minifree kernel: [ 0.000000] Command line: BOOT_IMAGE=/vmlinuz root=/dev/mapper/buzz-distro cryptdevice=/dev/mapper/buzz-distro:root quiet splash drm.debug=0x06 ro +Aug 31 22:50:24 minifree kernel: [ 0.000000] KERNEL supported cpus: +Aug 31 22:50:24 minifree kernel: [ 0.000000] Intel GenuineIntel +Aug 31 22:50:24 minifree kernel: [ 0.000000] AMD AuthenticAMD +Aug 31 22:50:24 minifree kernel: [ 0.000000] Centaur CentaurHauls +Aug 31 22:50:24 minifree kernel: [ 0.000000] e820: BIOS-provided physical RAM map: +Aug 31 22:50:24 minifree kernel: [ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16 +Aug 31 22:50:24 minifree kernel: [ 0.000000] BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable +Aug 31 22:50:24 minifree kernel: [ 0.000000] BIOS-e820: [mem 0x00000000000c0000-0x00000000000fffff] reserved +Aug 31 22:50:24 minifree kernel: [ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000007f6d4fff] usable +Aug 31 22:50:24 minifree kernel: [ 0.000000] BIOS-e820: [mem 0x000000007f6d5000-0x000000007f7fffff] type 16 +Aug 31 22:50:24 minifree kernel: [ 0.000000] BIOS-e820: [mem 0x000000007f800000-0x000000007fffffff] reserved +Aug 31 22:50:24 minifree kernel: [ 0.000000] BIOS-e820: [mem 0x00000000f0000000-0x00000000f3ffffff] reserved +Aug 31 22:50:24 minifree kernel: [ 0.000000] NX (Execute Disable) protection: active +Aug 31 22:50:24 minifree kernel: [ 0.000000] SMBIOS 2.7 present. +Aug 31 22:50:24 minifree kernel: [ 0.000000] DMI: LENOVO 1702L8G/1702L8G, BIOS CBET4000 7BETC7WW (2.08 ) 08/30/2014 +Aug 31 22:50:24 minifree kernel: [ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved +Aug 31 22:50:24 minifree kernel: [ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable +Aug 31 22:50:24 minifree kernel: [ 0.000000] No AGP bridge found +Aug 31 22:50:24 minifree kernel: [ 0.000000] e820: last_pfn = 0x7f6d5 max_arch_pfn = 0x400000000 +Aug 31 22:50:24 minifree kernel: [ 0.000000] MTRR default type: uncachable +Aug 31 22:50:24 minifree kernel: [ 0.000000] MTRR fixed ranges enabled: +Aug 31 22:50:24 minifree kernel: [ 0.000000] 00000-9FFFF write-back +Aug 31 22:50:24 minifree kernel: [ 0.000000] A0000-BFFFF uncachable +Aug 31 22:50:24 minifree kernel: [ 0.000000] C0000-FFFFF write-back +Aug 31 22:50:24 minifree kernel: [ 0.000000] MTRR variable ranges enabled: +Aug 31 22:50:24 minifree kernel: [ 0.000000] 0 base 000000000 mask F80000000 write-back +Aug 31 22:50:24 minifree kernel: [ 0.000000] 1 base 07F800000 mask FFF800000 uncachable +Aug 31 22:50:24 minifree kernel: [ 0.000000] 2 base 0D0000000 mask FF0000000 write-combining +Aug 31 22:50:24 minifree kernel: [ 0.000000] 3 disabled +Aug 31 22:50:24 minifree kernel: [ 0.000000] 4 disabled +Aug 31 22:50:24 minifree kernel: [ 0.000000] 5 disabled +Aug 31 22:50:24 minifree kernel: [ 0.000000] 6 disabled +Aug 31 22:50:24 minifree kernel: [ 0.000000] 7 disabled +Aug 31 22:50:24 minifree kernel: [ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 +Aug 31 22:50:24 minifree kernel: [ 0.000000] found SMP MP-table at [mem 0x000f0400-0x000f040f] mapped at [ffff8800000f0400] +Aug 31 22:50:24 minifree kernel: [ 0.000000] Scanning 1 areas for low memory corruption +Aug 31 22:50:24 minifree kernel: [ 0.000000] Base memory trampoline at [ffff880000099000] 99000 size 24576 +Aug 31 22:50:24 minifree kernel: [ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] [mem 0x00000000-0x000fffff] page 4k +Aug 31 22:50:24 minifree kernel: [ 0.000000] BRK [0x01fe0000, 0x01fe0fff] PGTABLE +Aug 31 22:50:24 minifree kernel: [ 0.000000] BRK [0x01fe1000, 0x01fe1fff] PGTABLE +Aug 31 22:50:24 minifree kernel: [ 0.000000] BRK [0x01fe2000, 0x01fe2fff] PGTABLE +Aug 31 22:50:24 minifree kernel: [ 0.000000] init_memory_mapping: [mem 0x7f400000-0x7f5fffff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] [mem 0x7f400000-0x7f5fffff] page 2M +Aug 31 22:50:24 minifree kernel: [ 0.000000] BRK [0x01fe3000, 0x01fe3fff] PGTABLE +Aug 31 22:50:24 minifree kernel: [ 0.000000] init_memory_mapping: [mem 0x7c000000-0x7f3fffff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] [mem 0x7c000000-0x7f3fffff] page 2M +Aug 31 22:50:24 minifree kernel: [ 0.000000] init_memory_mapping: [mem 0x00100000-0x7bffffff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] [mem 0x00100000-0x001fffff] page 4k +Aug 31 22:50:24 minifree kernel: [ 0.000000] [mem 0x00200000-0x7bffffff] page 2M +Aug 31 22:50:24 minifree kernel: [ 0.000000] init_memory_mapping: [mem 0x7f600000-0x7f6d4fff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] [mem 0x7f600000-0x7f6d4fff] page 4k +Aug 31 22:50:24 minifree kernel: [ 0.000000] BRK [0x01fe4000, 0x01fe4fff] PGTABLE +Aug 31 22:50:24 minifree kernel: [ 0.000000] RAMDISK: [mem 0x35122000-0x36888fff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: RSDP 00000000000f0800 000024 (v02 CORE ) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: XSDT 000000007f7de0e0 00004C (v01 CORE COREBOOT 00000000 CORE 00000000) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: HPET 000000007f7de210 000038 (v01 CORE COREBOOT 00000000 CORE 00000000) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: APIC 000000007f7de250 000068 (v01 CORE COREBOOT 00000000 CORE 00000000) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: MCFG 000000007f7de2c0 00003C (v01 CORE COREBOOT 00000000 CORE 00000000) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: FACP 000000007f7e15c0 0000F4 (v03 CORE COREBOOT 00000000 CORE 00000000) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: DSDT 000000007f7de340 003171 (v03 COREv4 COREBOOT 20090419 INTL 20140114) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: FACS 000000007f7de300 000040 +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: SSDT 000000007f7e16c0 000306 (v02 CORE COREBOOT 0000002A CORE 0000002A) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: Local APIC address 0xfee00000 +Aug 31 22:50:24 minifree kernel: [ 0.000000] No NUMA configuration found +Aug 31 22:50:24 minifree kernel: [ 0.000000] Faking a node at [mem 0x0000000000000000-0x000000007f6d4fff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] Initmem setup node 0 [mem 0x00000000-0x7f6d4fff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] NODE_DATA [mem 0x7f6d0000-0x7f6d4fff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] [ffffea0000000000-ffffea0001ffffff] PMD -> [ffff88007ce00000-ffff88007edfffff] on node 0 +Aug 31 22:50:24 minifree kernel: [ 0.000000] Zone ranges: +Aug 31 22:50:24 minifree kernel: [ 0.000000] DMA [mem 0x00001000-0x00ffffff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] DMA32 [mem 0x01000000-0xffffffff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] Normal empty +Aug 31 22:50:24 minifree kernel: [ 0.000000] Movable zone start for each node +Aug 31 22:50:24 minifree kernel: [ 0.000000] Early memory node ranges +Aug 31 22:50:24 minifree kernel: [ 0.000000] node 0: [mem 0x00001000-0x0009ffff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] node 0: [mem 0x00100000-0x7f6d4fff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] On node 0 totalpages: 521844 +Aug 31 22:50:24 minifree kernel: [ 0.000000] DMA zone: 64 pages used for memmap +Aug 31 22:50:24 minifree kernel: [ 0.000000] DMA zone: 22 pages reserved +Aug 31 22:50:24 minifree kernel: [ 0.000000] DMA zone: 3999 pages, LIFO batch:0 +Aug 31 22:50:24 minifree kernel: [ 0.000000] DMA32 zone: 8092 pages used for memmap +Aug 31 22:50:24 minifree kernel: [ 0.000000] DMA32 zone: 517845 pages, LIFO batch:31 +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: PM-Timer IO Port: 0x508 +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: Local APIC address 0xfee00000 +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1]) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: IOAPIC (id[0x02] address[0xfec00000] gsi_base[0]) +Aug 31 22:50:24 minifree kernel: [ 0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23 +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 high edge) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: IRQ0 used by override. +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: IRQ2 used by override. +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: IRQ9 used by override. +Aug 31 22:50:24 minifree kernel: [ 0.000000] Using ACPI (MADT) for SMP configuration information +Aug 31 22:50:24 minifree kernel: [ 0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000 +Aug 31 22:50:24 minifree kernel: [ 0.000000] smpboot: Allowing 2 CPUs, 0 hotplug CPUs +Aug 31 22:50:24 minifree kernel: [ 0.000000] nr_irqs_gsi: 40 +Aug 31 22:50:24 minifree kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000bffff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] PM: Registered nosave memory: [mem 0x000c0000-0x000fffff] +Aug 31 22:50:24 minifree kernel: [ 0.000000] e820: [mem 0x80000000-0xefffffff] available for PCI devices +Aug 31 22:50:24 minifree kernel: [ 0.000000] Booting paravirtualized kernel on bare hardware +Aug 31 22:50:24 minifree kernel: [ 0.000000] setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:2 nr_node_ids:1 +Aug 31 22:50:24 minifree kernel: [ 0.000000] PERCPU: Embedded 29 pages/cpu @ffff88007f400000 s86336 r8192 d24256 u1048576 +Aug 31 22:50:24 minifree kernel: [ 0.000000] pcpu-alloc: s86336 r8192 d24256 u1048576 alloc=1*2097152 +Aug 31 22:50:24 minifree kernel: [ 0.000000] pcpu-alloc: [0] 0 1 +Aug 31 22:50:24 minifree kernel: [ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 513666 +Aug 31 22:50:24 minifree kernel: [ 0.000000] Policy zone: DMA32 +Aug 31 22:50:24 minifree kernel: [ 0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz root=/dev/mapper/buzz-distro cryptdevice=/dev/mapper/buzz-distro:root quiet splash drm.debug=0x06 ro +Aug 31 22:50:24 minifree kernel: [ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) +Aug 31 22:50:24 minifree kernel: [ 0.000000] Checking aperture... +Aug 31 22:50:24 minifree kernel: [ 0.000000] No AGP bridge found +Aug 31 22:50:24 minifree kernel: [ 0.000000] Calgary: detecting Calgary via BIOS EBDA area +Aug 31 22:50:24 minifree kernel: [ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing! +Aug 31 22:50:24 minifree kernel: [ 0.000000] Memory: 2013772K/2087376K available (7391K kernel code, 1145K rwdata, 3416K rodata, 1336K init, 1440K bss, 73604K reserved) +Aug 31 22:50:24 minifree kernel: [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 +Aug 31 22:50:24 minifree kernel: [ 0.000000] Hierarchical RCU implementation. +Aug 31 22:50:24 minifree kernel: [ 0.000000] RCU dyntick-idle grace-period acceleration is enabled. +Aug 31 22:50:24 minifree kernel: [ 0.000000] RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=2. +Aug 31 22:50:24 minifree kernel: [ 0.000000] Offload RCU callbacks from all CPUs +Aug 31 22:50:24 minifree kernel: [ 0.000000] Offload RCU callbacks from CPUs: 0-1. +Aug 31 22:50:24 minifree kernel: [ 0.000000] NR_IRQS:16640 nr_irqs:512 16 +Aug 31 22:50:24 minifree kernel: [ 0.000000] Console: colour VGA+ 80x25 +Aug 31 22:50:24 minifree kernel: [ 0.000000] console [tty0] enabled +Aug 31 22:50:24 minifree kernel: [ 0.000000] allocated 8388608 bytes of page_cgroup +Aug 31 22:50:24 minifree kernel: [ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups +Aug 31 22:50:24 minifree kernel: [ 0.000000] hpet clockevent registered +Aug 31 22:50:24 minifree kernel: [ 0.000000] tsc: Fast TSC calibration using PIT +Aug 31 22:50:24 minifree kernel: [ 0.000000] tsc: Detected 1496.227 MHz processor +Aug 31 22:50:24 minifree kernel: [ 0.004006] Calibrating delay loop (skipped), value calculated using timer frequency.. 2992.45 BogoMIPS (lpj=5984908) +Aug 31 22:50:24 minifree kernel: [ 0.004013] pid_max: default: 32768 minimum: 301 +Aug 31 22:50:24 minifree kernel: [ 0.004059] Security Framework initialized +Aug 31 22:50:24 minifree kernel: [ 0.004095] AppArmor: AppArmor initialized +Aug 31 22:50:24 minifree kernel: [ 0.004097] Yama: becoming mindful. +Aug 31 22:50:24 minifree kernel: [ 0.004475] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes) +Aug 31 22:50:24 minifree kernel: [ 0.008553] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes) +Aug 31 22:50:24 minifree kernel: [ 0.009333] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes) +Aug 31 22:50:24 minifree kernel: [ 0.009340] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes) +Aug 31 22:50:24 minifree kernel: [ 0.009749] Initializing cgroup subsys memory +Aug 31 22:50:24 minifree kernel: [ 0.009764] Initializing cgroup subsys devices +Aug 31 22:50:24 minifree kernel: [ 0.009767] Initializing cgroup subsys freezer +Aug 31 22:50:24 minifree kernel: [ 0.009771] Initializing cgroup subsys blkio +Aug 31 22:50:24 minifree kernel: [ 0.009775] Initializing cgroup subsys bfqio +Aug 31 22:50:24 minifree kernel: [ 0.009778] Initializing cgroup subsys perf_event +Aug 31 22:50:24 minifree kernel: [ 0.009783] Initializing cgroup subsys hugetlb +Aug 31 22:50:24 minifree kernel: [ 0.009821] CPU: Physical Processor ID: 0 +Aug 31 22:50:24 minifree kernel: [ 0.009823] CPU: Processor Core ID: 0 +Aug 31 22:50:24 minifree kernel: [ 0.009827] mce: CPU supports 6 MCE banks +Aug 31 22:50:24 minifree kernel: [ 0.009839] CPU0: Thermal monitoring enabled (TM2) +Aug 31 22:50:24 minifree kernel: [ 0.009850] Last level iTLB entries: 4KB 128, 2MB 4, 4MB 4 +Aug 31 22:50:24 minifree kernel: [ 0.009850] Last level dTLB entries: 4KB 256, 2MB 0, 4MB 32 +Aug 31 22:50:24 minifree kernel: [ 0.009850] tlb_flushall_shift: -1 +Aug 31 22:50:24 minifree kernel: [ 0.010001] Freeing SMP alternatives memory: 32K (ffffffff81e6e000 - ffffffff81e76000) +Aug 31 22:50:24 minifree kernel: [ 0.012383] ACPI: Core revision 20131115 +Aug 31 22:50:24 minifree kernel: [ 0.015473] ACPI: All ACPI Tables successfully acquired +Aug 31 22:50:24 minifree kernel: [ 0.016025] ftrace: allocating 28599 entries in 112 pages +Aug 31 22:50:24 minifree kernel: [ 0.028599] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 +Aug 31 22:50:24 minifree kernel: [ 0.070880] smpboot: CPU0: Intel(R) Core(TM)2 CPU L7400 @ 1.50GHz (fam: 06, model: 0f, stepping: 06) +Aug 31 22:50:24 minifree kernel: [ 0.072000] Performance Events: PEBS fmt0-, 4-deep LBR, Core2 events, Intel PMU driver. +Aug 31 22:50:24 minifree kernel: [ 0.072000] perf_event_intel: PEBS disabled due to CPU errata +Aug 31 22:50:24 minifree kernel: [ 0.072000] ... version: 2 +Aug 31 22:50:24 minifree kernel: [ 0.072000] ... bit width: 40 +Aug 31 22:50:24 minifree kernel: [ 0.072000] ... generic registers: 2 +Aug 31 22:50:24 minifree kernel: [ 0.072000] ... value mask: 000000ffffffffff +Aug 31 22:50:24 minifree kernel: [ 0.072000] ... max period: 000000007fffffff +Aug 31 22:50:24 minifree kernel: [ 0.072000] ... fixed-purpose events: 3 +Aug 31 22:50:24 minifree kernel: [ 0.072000] ... event mask: 0000000700000003 +Aug 31 22:50:24 minifree kernel: [ 0.072000] x86: Booting SMP configuration: +Aug 31 22:50:24 minifree kernel: [ 0.072000] .... node #0, CPUs: #1 +Aug 31 22:50:24 minifree kernel: [ 0.084066] x86: Booted up 1 node, 2 CPUs +Aug 31 22:50:24 minifree kernel: [ 0.084074] smpboot: Total of 2 processors activated (5984.90 BogoMIPS) +Aug 31 22:50:24 minifree kernel: [ 0.084177] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter. +Aug 31 22:50:24 minifree kernel: [ 0.088071] devtmpfs: initialized +Aug 31 22:50:24 minifree kernel: [ 0.098352] EVM: security.selinux +Aug 31 22:50:24 minifree kernel: [ 0.098355] EVM: security.SMACK64 +Aug 31 22:50:24 minifree kernel: [ 0.098357] EVM: security.ima +Aug 31 22:50:24 minifree kernel: [ 0.098359] EVM: security.capability +Aug 31 22:50:24 minifree kernel: [ 0.100096] pinctrl core: initialized pinctrl subsystem +Aug 31 22:50:24 minifree kernel: [ 0.100211] regulator-dummy: no parameters +Aug 31 22:50:24 minifree kernel: [ 0.100257] RTC time: 21:49:54, date: 08/31/14 +Aug 31 22:50:24 minifree kernel: [ 0.100319] NET: Registered protocol family 16 +Aug 31 22:50:24 minifree kernel: [ 0.100522] cpuidle: using governor ladder +Aug 31 22:50:24 minifree kernel: [ 0.100525] cpuidle: using governor menu +Aug 31 22:50:24 minifree kernel: [ 0.100592] ACPI: bus type PCI registered +Aug 31 22:50:24 minifree kernel: [ 0.100595] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 +Aug 31 22:50:24 minifree kernel: [ 0.100691] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xf0000000-0xf3ffffff] (base 0xf0000000) +Aug 31 22:50:24 minifree kernel: [ 0.100695] PCI: MMCONFIG at [mem 0xf0000000-0xf3ffffff] reserved in E820 +Aug 31 22:50:24 minifree kernel: [ 0.105678] PCI: Using configuration type 1 for base access +Aug 31 22:50:24 minifree kernel: [ 0.108094] bio: create slab at 0 +Aug 31 22:50:24 minifree kernel: [ 0.108141] ACPI: Added _OSI(Module Device) +Aug 31 22:50:24 minifree kernel: [ 0.108144] ACPI: Added _OSI(Processor Device) +Aug 31 22:50:24 minifree kernel: [ 0.108147] ACPI: Added _OSI(3.0 _SCP Extensions) +Aug 31 22:50:24 minifree kernel: [ 0.108149] ACPI: Added _OSI(Processor Aggregator Device) +Aug 31 22:50:24 minifree kernel: [ 0.111400] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored +Aug 31 22:50:24 minifree kernel: [ 0.111850] ACPI: Interpreter enabled +Aug 31 22:50:24 minifree kernel: [ 0.111859] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20131115/hwxface-580) +Aug 31 22:50:24 minifree kernel: [ 0.111867] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20131115/hwxface-580) +Aug 31 22:50:24 minifree kernel: [ 0.111889] ACPI: (supports S0 S3 S4 S5) +Aug 31 22:50:24 minifree kernel: [ 0.111892] ACPI: Using IOAPIC for interrupt routing +Aug 31 22:50:24 minifree kernel: [ 0.111927] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug +Aug 31 22:50:24 minifree kernel: [ 0.112256] ACPI: ACPI Dock Station Driver: 1 docks/bays found +Aug 31 22:50:24 minifree kernel: [ 0.121379] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) +Aug 31 22:50:24 minifree kernel: [ 0.121389] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] +Aug 31 22:50:24 minifree kernel: [ 0.121498] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] +Aug 31 22:50:24 minifree kernel: [ 0.121642] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge +Aug 31 22:50:24 minifree kernel: [ 0.121922] PCI host bridge to bus 0000:00 +Aug 31 22:50:24 minifree kernel: [ 0.121927] pci_bus 0000:00: root bus resource [bus 00-ff] +Aug 31 22:50:24 minifree kernel: [ 0.121931] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7] +Aug 31 22:50:24 minifree kernel: [ 0.121935] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff] +Aug 31 22:50:24 minifree kernel: [ 0.121938] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] +Aug 31 22:50:24 minifree kernel: [ 0.121942] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000c3fff] +Aug 31 22:50:24 minifree kernel: [ 0.121945] pci_bus 0000:00: root bus resource [mem 0x000c4000-0x000c7fff] +Aug 31 22:50:24 minifree kernel: [ 0.121948] pci_bus 0000:00: root bus resource [mem 0x000c8000-0x000cbfff] +Aug 31 22:50:24 minifree kernel: [ 0.121951] pci_bus 0000:00: root bus resource [mem 0x000cc000-0x000cffff] +Aug 31 22:50:24 minifree kernel: [ 0.121955] pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff] +Aug 31 22:50:24 minifree kernel: [ 0.121958] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff] +Aug 31 22:50:24 minifree kernel: [ 0.121961] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff] +Aug 31 22:50:24 minifree kernel: [ 0.121965] pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff] +Aug 31 22:50:24 minifree kernel: [ 0.121968] pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000e3fff] +Aug 31 22:50:24 minifree kernel: [ 0.121971] pci_bus 0000:00: root bus resource [mem 0x000e4000-0x000e7fff] +Aug 31 22:50:24 minifree kernel: [ 0.121975] pci_bus 0000:00: root bus resource [mem 0x000e8000-0x000ebfff] +Aug 31 22:50:24 minifree kernel: [ 0.121978] pci_bus 0000:00: root bus resource [mem 0x000ec000-0x000effff] +Aug 31 22:50:24 minifree kernel: [ 0.121981] pci_bus 0000:00: root bus resource [mem 0x000f0000-0x000fffff] +Aug 31 22:50:24 minifree kernel: [ 0.121985] pci_bus 0000:00: root bus resource [mem 0x80000000-0xfebfffff] +Aug 31 22:50:24 minifree kernel: [ 0.121988] pci_bus 0000:00: root bus resource [mem 0xfed40000-0xfed44fff] +Aug 31 22:50:24 minifree kernel: [ 0.122002] pci 0000:00:00.0: [8086:27a0] type 00 class 0x060000 +Aug 31 22:50:24 minifree kernel: [ 0.122153] pci 0000:00:02.0: [8086:27a2] type 00 class 0x030000 +Aug 31 22:50:24 minifree kernel: [ 0.122170] pci 0000:00:02.0: reg 0x10: [mem 0xe4200000-0xe427ffff] +Aug 31 22:50:24 minifree kernel: [ 0.122179] pci 0000:00:02.0: reg 0x14: [io 0x50a0-0x50a7] +Aug 31 22:50:24 minifree kernel: [ 0.122188] pci 0000:00:02.0: reg 0x18: [mem 0xd0000000-0xdfffffff pref] +Aug 31 22:50:24 minifree kernel: [ 0.122198] pci 0000:00:02.0: reg 0x1c: [mem 0xe4300000-0xe433ffff] +Aug 31 22:50:24 minifree kernel: [ 0.122338] pci 0000:00:02.1: [8086:27a6] type 00 class 0x038000 +Aug 31 22:50:24 minifree kernel: [ 0.122352] pci 0000:00:02.1: reg 0x10: [mem 0xe4280000-0xe42fffff] +Aug 31 22:50:24 minifree kernel: [ 0.122564] pci 0000:00:1b.0: [8086:27d8] type 00 class 0x040300 +Aug 31 22:50:24 minifree kernel: [ 0.122591] pci 0000:00:1b.0: reg 0x10: [mem 0xe4340000-0xe4343fff 64bit] +Aug 31 22:50:24 minifree kernel: [ 0.122706] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold +Aug 31 22:50:24 minifree kernel: [ 0.122785] pci 0000:00:1b.0: System wakeup disabled by ACPI +Aug 31 22:50:24 minifree kernel: [ 0.122842] pci 0000:00:1c.0: [8086:27d0] type 01 class 0x060400 +Aug 31 22:50:24 minifree kernel: [ 0.122964] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold +Aug 31 22:50:24 minifree kernel: [ 0.123100] pci 0000:00:1c.1: [8086:27d2] type 01 class 0x060400 +Aug 31 22:50:24 minifree kernel: [ 0.123210] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold +Aug 31 22:50:24 minifree kernel: [ 0.123337] pci 0000:00:1c.2: [8086:27d4] type 01 class 0x060400 +Aug 31 22:50:24 minifree kernel: [ 0.123447] pci 0000:00:1c.2: PME# supported from D0 D3hot D3cold +Aug 31 22:50:24 minifree kernel: [ 0.123579] pci 0000:00:1c.3: [8086:27d6] type 01 class 0x060400 +Aug 31 22:50:24 minifree kernel: [ 0.123689] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold +Aug 31 22:50:24 minifree kernel: [ 0.123817] pci 0000:00:1d.0: [8086:27c8] type 00 class 0x0c0300 +Aug 31 22:50:24 minifree kernel: [ 0.123881] pci 0000:00:1d.0: reg 0x20: [io 0x5000-0x501f] +Aug 31 22:50:24 minifree kernel: [ 0.124006] pci 0000:00:1d.0: System wakeup disabled by ACPI +Aug 31 22:50:24 minifree kernel: [ 0.124057] pci 0000:00:1d.1: [8086:27c9] type 00 class 0x0c0300 +Aug 31 22:50:24 minifree kernel: [ 0.124120] pci 0000:00:1d.1: reg 0x20: [io 0x5020-0x503f] +Aug 31 22:50:24 minifree kernel: [ 0.124236] pci 0000:00:1d.1: System wakeup disabled by ACPI +Aug 31 22:50:24 minifree kernel: [ 0.124286] pci 0000:00:1d.2: [8086:27ca] type 00 class 0x0c0300 +Aug 31 22:50:24 minifree kernel: [ 0.124349] pci 0000:00:1d.2: reg 0x20: [io 0x5040-0x505f] +Aug 31 22:50:24 minifree kernel: [ 0.124464] pci 0000:00:1d.2: System wakeup disabled by ACPI +Aug 31 22:50:24 minifree kernel: [ 0.124515] pci 0000:00:1d.3: [8086:27cb] type 00 class 0x0c0300 +Aug 31 22:50:24 minifree kernel: [ 0.124578] pci 0000:00:1d.3: reg 0x20: [io 0x5060-0x507f] +Aug 31 22:50:24 minifree kernel: [ 0.124695] pci 0000:00:1d.3: System wakeup disabled by ACPI +Aug 31 22:50:24 minifree kernel: [ 0.124759] pci 0000:00:1d.7: [8086:27cc] type 00 class 0x0c0320 +Aug 31 22:50:24 minifree kernel: [ 0.124787] pci 0000:00:1d.7: reg 0x10: [mem 0xe4344000-0xe43443ff] +Aug 31 22:50:24 minifree kernel: [ 0.124905] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold +Aug 31 22:50:24 minifree kernel: [ 0.124978] pci 0000:00:1d.7: System wakeup disabled by ACPI +Aug 31 22:50:24 minifree kernel: [ 0.125032] pci 0000:00:1e.0: [8086:2448] type 01 class 0x060401 +Aug 31 22:50:24 minifree kernel: [ 0.125214] pci 0000:00:1f.0: [8086:27b9] type 00 class 0x060100 +Aug 31 22:50:24 minifree kernel: [ 0.125339] pci 0000:00:1f.0: address space collision: [io 0x0500-0x057f] conflicts with ACPI CPU throttle [??? 0x00000510-0x00000515 flags 0x80000000] +Aug 31 22:50:24 minifree kernel: [ 0.125347] pci 0000:00:1f.0: quirk: [io 0x0480-0x04bf] claimed by ICH6 GPIO +Aug 31 22:50:24 minifree kernel: [ 0.125353] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 1 PIO at 1600 (mask 007f) +Aug 31 22:50:24 minifree kernel: [ 0.125359] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 2 PIO at 15e0 (mask 000f) +Aug 31 22:50:24 minifree kernel: [ 0.125364] pci 0000:00:1f.0: ICH7 LPC Generic IO decode 3 PIO at 1680 (mask 001f) +Aug 31 22:50:24 minifree kernel: [ 0.125515] pci 0000:00:1f.1: [8086:27df] type 00 class 0x01018a +Aug 31 22:50:24 minifree kernel: [ 0.125535] pci 0000:00:1f.1: reg 0x10: [io 0x50a8-0x50af] +Aug 31 22:50:24 minifree kernel: [ 0.125550] pci 0000:00:1f.1: reg 0x14: [io 0x50c8-0x50cb] +Aug 31 22:50:24 minifree kernel: [ 0.125564] pci 0000:00:1f.1: reg 0x18: [io 0x50b0-0x50b7] +Aug 31 22:50:24 minifree kernel: [ 0.125578] pci 0000:00:1f.1: reg 0x1c: [io 0x50cc-0x50cf] +Aug 31 22:50:24 minifree kernel: [ 0.125592] pci 0000:00:1f.1: reg 0x20: [io 0x5080-0x508f] +Aug 31 22:50:24 minifree kernel: [ 0.125736] pci 0000:00:1f.2: [8086:27c5] type 00 class 0x010601 +Aug 31 22:50:24 minifree kernel: [ 0.125764] pci 0000:00:1f.2: reg 0x10: [io 0x50b8-0x50bf] +Aug 31 22:50:24 minifree kernel: [ 0.125777] pci 0000:00:1f.2: reg 0x14: [io 0x50d0-0x50d3] +Aug 31 22:50:24 minifree kernel: [ 0.125792] pci 0000:00:1f.2: reg 0x18: [io 0x50c0-0x50c7] +Aug 31 22:50:24 minifree kernel: [ 0.125806] pci 0000:00:1f.2: reg 0x1c: [io 0x50d4-0x50d7] +Aug 31 22:50:24 minifree kernel: [ 0.125820] pci 0000:00:1f.2: reg 0x20: [io 0x5090-0x509f] +Aug 31 22:50:24 minifree kernel: [ 0.125835] pci 0000:00:1f.2: reg 0x24: [mem 0xe4344400-0xe43447ff] +Aug 31 22:50:24 minifree kernel: [ 0.125899] pci 0000:00:1f.2: PME# supported from D3hot +Aug 31 22:50:24 minifree kernel: [ 0.126016] pci 0000:00:1f.3: [8086:27da] type 00 class 0x0c0500 +Aug 31 22:50:24 minifree kernel: [ 0.126096] pci 0000:00:1f.3: reg 0x20: [io 0x0400-0x041f] +Aug 31 22:50:24 minifree kernel: [ 0.126355] pci 0000:01:00.0: [8086:109a] type 00 class 0x020000 +Aug 31 22:50:24 minifree kernel: [ 0.126389] pci 0000:01:00.0: reg 0x10: [mem 0xe4100000-0xe411ffff] +Aug 31 22:50:24 minifree kernel: [ 0.126434] pci 0000:01:00.0: reg 0x18: [io 0x4000-0x401f] +Aug 31 22:50:24 minifree kernel: [ 0.126628] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold +Aug 31 22:50:24 minifree kernel: [ 0.126710] pci 0000:01:00.0: disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force' +Aug 31 22:50:24 minifree kernel: [ 0.126731] pci 0000:00:1c.0: PCI bridge to [bus 01] +Aug 31 22:50:24 minifree kernel: [ 0.126737] pci 0000:00:1c.0: bridge window [io 0x4000-0x4fff] +Aug 31 22:50:24 minifree kernel: [ 0.126744] pci 0000:00:1c.0: bridge window [mem 0xe4100000-0xe41fffff] +Aug 31 22:50:24 minifree kernel: [ 0.126838] pci 0000:00:1c.1: PCI bridge to [bus 02] +Aug 31 22:50:24 minifree kernel: [ 0.126938] pci 0000:00:1c.2: PCI bridge to [bus 03] +Aug 31 22:50:24 minifree kernel: [ 0.127032] pci 0000:00:1c.3: PCI bridge to [bus 04] +Aug 31 22:50:24 minifree kernel: [ 0.127187] pci 0000:05:00.0: [1180:0476] type 02 class 0x060700 +Aug 31 22:50:24 minifree kernel: [ 0.127210] pci 0000:05:00.0: proprietary Ricoh MMC controller disabled (via cardbus function) +Aug 31 22:50:24 minifree kernel: [ 0.127213] pci 0000:05:00.0: MMC cards are now supported by standard SDHCI controller +Aug 31 22:50:24 minifree kernel: [ 0.127233] pci 0000:05:00.0: reg 0x10: [mem 0xe2000000-0xe2000fff] +Aug 31 22:50:24 minifree kernel: [ 0.127274] pci 0000:05:00.0: supports D1 D2 +Aug 31 22:50:24 minifree kernel: [ 0.127278] pci 0000:05:00.0: PME# supported from D0 D1 D2 D3hot D3cold +Aug 31 22:50:24 minifree kernel: [ 0.127318] pci 0000:05:00.0: System wakeup disabled by ACPI +Aug 31 22:50:24 minifree kernel: [ 0.127377] pci 0000:05:00.1: [1180:0552] type 00 class 0x0c0010 +Aug 31 22:50:24 minifree kernel: [ 0.127403] pci 0000:05:00.1: reg 0x10: [mem 0xe2001000-0xe20017ff] +Aug 31 22:50:24 minifree kernel: [ 0.127512] pci 0000:05:00.1: supports D1 D2 +Aug 31 22:50:24 minifree kernel: [ 0.127516] pci 0000:05:00.1: PME# supported from D0 D1 D2 D3hot D3cold +Aug 31 22:50:24 minifree kernel: [ 0.127599] pci 0000:05:00.2: [1180:0822] type 00 class 0x080500 +Aug 31 22:50:24 minifree kernel: [ 0.127626] pci 0000:05:00.2: reg 0x10: [mem 0xe2001800-0xe20018ff] +Aug 31 22:50:24 minifree kernel: [ 0.127736] pci 0000:05:00.2: supports D1 D2 +Aug 31 22:50:24 minifree kernel: [ 0.127740] pci 0000:05:00.2: PME# supported from D0 D1 D2 D3hot D3cold +Aug 31 22:50:24 minifree kernel: [ 0.127880] pci 0000:00:1e.0: PCI bridge to [bus 05-06] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127887] pci 0000:00:1e.0: bridge window [io 0x2000-0x3fff] +Aug 31 22:50:24 minifree kernel: [ 0.127894] pci 0000:00:1e.0: bridge window [mem 0xe0000000-0xe20fffff] +Aug 31 22:50:24 minifree kernel: [ 0.127904] pci 0000:00:1e.0: bridge window [mem 0xe2100000-0xe40fffff 64bit pref] +Aug 31 22:50:24 minifree kernel: [ 0.127908] pci 0000:00:1e.0: bridge window [io 0x0000-0x0cf7] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127911] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127915] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127918] pci 0000:00:1e.0: bridge window [mem 0x000c0000-0x000c3fff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127922] pci 0000:00:1e.0: bridge window [mem 0x000c4000-0x000c7fff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127925] pci 0000:00:1e.0: bridge window [mem 0x000c8000-0x000cbfff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127928] pci 0000:00:1e.0: bridge window [mem 0x000cc000-0x000cffff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127932] pci 0000:00:1e.0: bridge window [mem 0x000d0000-0x000d3fff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127935] pci 0000:00:1e.0: bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127938] pci 0000:00:1e.0: bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127942] pci 0000:00:1e.0: bridge window [mem 0x000dc000-0x000dffff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127945] pci 0000:00:1e.0: bridge window [mem 0x000e0000-0x000e3fff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127949] pci 0000:00:1e.0: bridge window [mem 0x000e4000-0x000e7fff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127952] pci 0000:00:1e.0: bridge window [mem 0x000e8000-0x000ebfff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127955] pci 0000:00:1e.0: bridge window [mem 0x000ec000-0x000effff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127959] pci 0000:00:1e.0: bridge window [mem 0x000f0000-0x000fffff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127962] pci 0000:00:1e.0: bridge window [mem 0x80000000-0xfebfffff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.127966] pci 0000:00:1e.0: bridge window [mem 0xfed40000-0xfed44fff] (subtractive decode) +Aug 31 22:50:24 minifree kernel: [ 0.128041] pci_bus 0000:06: busn_res: can not insert [bus 06-ff] under [bus 05-06] (conflicts with (null) [bus 05-06]) +Aug 31 22:50:24 minifree kernel: [ 0.128049] pci_bus 0000:06: busn_res: [bus 06-ff] end is updated to 09 +Aug 31 22:50:24 minifree kernel: [ 0.128053] pci_bus 0000:06: busn_res: can not insert [bus 06-09] under [bus 05-06] (conflicts with (null) [bus 05-06]) +Aug 31 22:50:24 minifree kernel: [ 0.128060] pci_bus 0000:06: [bus 06-09] partially hidden behind transparent bridge 0000:05 [bus 05-06] +Aug 31 22:50:24 minifree kernel: [ 0.128336] ACPI: PCI Interrupt Link [LNKA] (IRQs 1 3 4 5 6 7 10 12 14 15) *11 +Aug 31 22:50:24 minifree kernel: [ 0.128426] ACPI: PCI Interrupt Link [LNKB] (IRQs 1 3 4 5 6 7 *11 12 14 15) +Aug 31 22:50:24 minifree kernel: [ 0.128512] ACPI: PCI Interrupt Link [LNKC] (IRQs 1 3 4 5 6 7 10 12 14 15) *11 +Aug 31 22:50:24 minifree kernel: [ 0.128597] ACPI: PCI Interrupt Link [LNKD] (IRQs 1 3 4 5 6 7 *11 12 14 15) +Aug 31 22:50:24 minifree kernel: [ 0.128682] ACPI: PCI Interrupt Link [LNKE] (IRQs 1 3 4 5 6 7 10 12 14 15) *11 +Aug 31 22:50:24 minifree kernel: [ 0.128766] ACPI: PCI Interrupt Link [LNKF] (IRQs 1 3 4 5 6 7 *11 12 14 15) +Aug 31 22:50:24 minifree kernel: [ 0.128850] ACPI: PCI Interrupt Link [LNKG] (IRQs 1 3 4 5 6 7 10 12 14 15) *11 +Aug 31 22:50:24 minifree kernel: [ 0.128935] ACPI: PCI Interrupt Link [LNKH] (IRQs 1 3 4 5 6 7 *11 12 14 15) +Aug 31 22:50:24 minifree kernel: [ 0.129051] ACPI: \_SB_.PCI0: notify handler is installed +Aug 31 22:50:24 minifree kernel: [ 0.129051] Found 1 acpi root devices +Aug 31 22:50:24 minifree kernel: [ 0.129051] ACPI : EC: GPE = 0x1c, I/O: command/status = 0x66, data = 0x62 +Aug 31 22:50:24 minifree kernel: [ 0.129051] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none +Aug 31 22:50:24 minifree kernel: [ 0.129051] vgaarb: loaded +Aug 31 22:50:24 minifree kernel: [ 0.129051] vgaarb: bridge control possible 0000:00:02.0 +Aug 31 22:50:24 minifree kernel: [ 0.129051] SCSI subsystem initialized +Aug 31 22:50:24 minifree kernel: [ 0.129051] libata version 3.00 loaded. +Aug 31 22:50:24 minifree kernel: [ 0.129051] ACPI: bus type USB registered +Aug 31 22:50:24 minifree kernel: [ 0.129051] usbcore: registered new interface driver usbfs +Aug 31 22:50:24 minifree kernel: [ 0.129051] usbcore: registered new interface driver hub +Aug 31 22:50:24 minifree kernel: [ 0.129051] usbcore: registered new device driver usb +Aug 31 22:50:24 minifree kernel: [ 0.129051] PCI: Using ACPI for IRQ routing +Aug 31 22:50:24 minifree kernel: [ 0.133275] PCI: pci_cache_line_size set to 64 bytes +Aug 31 22:50:24 minifree kernel: [ 0.133369] e820: reserve RAM buffer [mem 0x7f6d5000-0x7fffffff] +Aug 31 22:50:24 minifree kernel: [ 0.133506] NetLabel: Initializing +Aug 31 22:50:24 minifree kernel: [ 0.133509] NetLabel: domain hash size = 128 +Aug 31 22:50:24 minifree kernel: [ 0.133510] NetLabel: protocols = UNLABELED CIPSOv4 +Aug 31 22:50:24 minifree kernel: [ 0.133537] NetLabel: unlabeled traffic allowed by default +Aug 31 22:50:24 minifree kernel: [ 0.133557] HPET: 3 timers in total, 0 timers will be used for per-cpu timer +Aug 31 22:50:24 minifree kernel: [ 0.133557] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0 +Aug 31 22:50:24 minifree kernel: [ 0.133557] hpet0: 3 comparators, 64-bit 14.318180 MHz counter +Aug 31 22:50:24 minifree kernel: [ 0.134098] Switched to clocksource hpet +Aug 31 22:50:24 minifree kernel: [ 0.142214] AppArmor: AppArmor Filesystem Enabled +Aug 31 22:50:24 minifree kernel: [ 0.142264] pnp: PnP ACPI init +Aug 31 22:50:24 minifree kernel: [ 0.142291] ACPI: bus type PNP registered +Aug 31 22:50:24 minifree kernel: [ 0.142445] system 00:00: [mem 0xfed1c000-0xfed1ffff] has been reserved +Aug 31 22:50:24 minifree kernel: [ 0.142450] system 00:00: [mem 0xfed14000-0xfed17fff] has been reserved +Aug 31 22:50:24 minifree kernel: [ 0.142454] system 00:00: [mem 0xfed18000-0xfed18fff] has been reserved +Aug 31 22:50:24 minifree kernel: [ 0.142458] system 00:00: [mem 0xfed19000-0xfed19fff] has been reserved +Aug 31 22:50:24 minifree kernel: [ 0.142462] system 00:00: [mem 0xf0000000-0xf3ffffff] has been reserved +Aug 31 22:50:24 minifree kernel: [ 0.142466] system 00:00: [mem 0xfed20000-0xfed3ffff] has been reserved +Aug 31 22:50:24 minifree kernel: [ 0.142470] system 00:00: [mem 0xfed40000-0xfed44fff] has been reserved +Aug 31 22:50:24 minifree kernel: [ 0.142474] system 00:00: [mem 0xfed45000-0xfed8ffff] has been reserved +Aug 31 22:50:24 minifree kernel: [ 0.142481] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active) +Aug 31 22:50:24 minifree kernel: [ 0.143002] pnp 00:01: [dma 4] +Aug 31 22:50:24 minifree kernel: [ 0.143047] pnp 00:01: Plug and Play ACPI device, IDs PNP0200 (active) +Aug 31 22:50:24 minifree kernel: [ 0.143092] pnp 00:02: Plug and Play ACPI device, IDs INT0800 (active) +Aug 31 22:50:24 minifree kernel: [ 0.143244] system 00:03: [mem 0xfed00000-0xfed003ff] has been reserved +Aug 31 22:50:24 minifree kernel: [ 0.143250] system 00:03: Plug and Play ACPI device, IDs PNP0103 PNP0c01 (active) +Aug 31 22:50:24 minifree kernel: [ 0.143320] pnp 00:04: Plug and Play ACPI device, IDs PNP0c04 (active) +Aug 31 22:50:24 minifree kernel: [ 0.143397] system 00:05: [io 0x0800-0x080f] has been reserved +Aug 31 22:50:24 minifree kernel: [ 0.143402] system 00:05: [io 0x0500-0x057f] could not be reserved +Aug 31 22:50:24 minifree kernel: [ 0.143406] system 00:05: [io 0x0480-0x04bf] has been reserved +Aug 31 22:50:24 minifree kernel: [ 0.143411] system 00:05: Plug and Play ACPI device, IDs PNP0c02 (active) +Aug 31 22:50:24 minifree kernel: [ 0.143463] pnp 00:06: Plug and Play ACPI device, IDs PNP0b00 (active) +Aug 31 22:50:24 minifree kernel: [ 0.143529] pnp 00:07: Plug and Play ACPI device, IDs PNP0303 PNP030b (active) +Aug 31 22:50:24 minifree kernel: [ 0.143593] pnp 00:08: Plug and Play ACPI device, IDs PNP0f13 (active) +Aug 31 22:50:24 minifree kernel: [ 0.143654] pnp 00:09: Plug and Play ACPI device, IDs PNP0501 (active) +Aug 31 22:50:24 minifree kernel: [ 0.143699] pnp: PnP ACPI: found 10 devices +Aug 31 22:50:24 minifree kernel: [ 0.143702] ACPI: bus type PNP unregistered +Aug 31 22:50:24 minifree kernel: [ 0.151684] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 01] add_size 200000 +Aug 31 22:50:24 minifree kernel: [ 0.151738] pci 0000:00:1f.0: BAR 13: [io 0x0500-0x057f] has bogus alignment +Aug 31 22:50:24 minifree kernel: [ 0.151744] pci 0000:00:1c.0: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000 +Aug 31 22:50:24 minifree kernel: [ 0.151755] pci 0000:00:1c.0: BAR 15: assigned [mem 0x80000000-0x801fffff 64bit pref] +Aug 31 22:50:24 minifree kernel: [ 0.151759] pci 0000:00:1c.0: PCI bridge to [bus 01] +Aug 31 22:50:24 minifree kernel: [ 0.151765] pci 0000:00:1c.0: bridge window [io 0x4000-0x4fff] +Aug 31 22:50:24 minifree kernel: [ 0.151773] pci 0000:00:1c.0: bridge window [mem 0xe4100000-0xe41fffff] +Aug 31 22:50:24 minifree kernel: [ 0.151780] pci 0000:00:1c.0: bridge window [mem 0x80000000-0x801fffff 64bit pref] +Aug 31 22:50:24 minifree kernel: [ 0.151790] pci 0000:00:1c.1: PCI bridge to [bus 02] +Aug 31 22:50:24 minifree kernel: [ 0.151807] pci 0000:00:1c.2: PCI bridge to [bus 03] +Aug 31 22:50:24 minifree kernel: [ 0.151824] pci 0000:00:1c.3: PCI bridge to [bus 04] +Aug 31 22:50:24 minifree kernel: [ 0.151848] pci 0000:05:00.0: res[15]=[mem 0x04000000-0x03ffffff pref] get_res_add_size add_size 4000000 +Aug 31 22:50:24 minifree kernel: [ 0.151852] pci 0000:05:00.0: res[16]=[mem 0x04000000-0x03ffffff] get_res_add_size add_size 4000000 +Aug 31 22:50:24 minifree kernel: [ 0.151856] pci 0000:05:00.0: res[13]=[io 0x0100-0x00ff] get_res_add_size add_size 100 +Aug 31 22:50:24 minifree kernel: [ 0.151860] pci 0000:05:00.0: res[14]=[io 0x0100-0x00ff] get_res_add_size add_size 100 +Aug 31 22:50:24 minifree kernel: [ 0.151868] pci 0000:05:00.0: BAR 15: assigned [mem 0x84000000-0x87ffffff pref] +Aug 31 22:50:24 minifree kernel: [ 0.151875] pci 0000:05:00.0: BAR 16: assigned [mem 0x88000000-0x8bffffff] +Aug 31 22:50:24 minifree kernel: [ 0.151879] pci 0000:05:00.0: BAR 13: assigned [io 0x2000-0x20ff] +Aug 31 22:50:24 minifree kernel: [ 0.151883] pci 0000:05:00.0: BAR 14: assigned [io 0x2400-0x24ff] +Aug 31 22:50:24 minifree kernel: [ 0.151888] pci 0000:05:00.0: CardBus bridge to [bus 06-09] +Aug 31 22:50:24 minifree kernel: [ 0.151891] pci 0000:05:00.0: bridge window [io 0x2000-0x20ff] +Aug 31 22:50:24 minifree kernel: [ 0.151897] pci 0000:05:00.0: bridge window [io 0x2400-0x24ff] +Aug 31 22:50:24 minifree kernel: [ 0.151904] pci 0000:05:00.0: bridge window [mem 0x84000000-0x87ffffff pref] +Aug 31 22:50:24 minifree kernel: [ 0.151910] pci 0000:05:00.0: bridge window [mem 0x88000000-0x8bffffff] +Aug 31 22:50:24 minifree kernel: [ 0.151917] pci 0000:00:1e.0: PCI bridge to [bus 05-06] +Aug 31 22:50:24 minifree kernel: [ 0.151922] pci 0000:00:1e.0: bridge window [io 0x2000-0x3fff] +Aug 31 22:50:24 minifree kernel: [ 0.151930] pci 0000:00:1e.0: bridge window [mem 0xe0000000-0xe20fffff] +Aug 31 22:50:24 minifree kernel: [ 0.151937] pci 0000:00:1e.0: bridge window [mem 0xe2100000-0xe40fffff 64bit pref] +Aug 31 22:50:24 minifree kernel: [ 0.151947] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7] +Aug 31 22:50:24 minifree kernel: [ 0.151951] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff] +Aug 31 22:50:24 minifree kernel: [ 0.151955] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff] +Aug 31 22:50:24 minifree kernel: [ 0.151958] pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000c3fff] +Aug 31 22:50:24 minifree kernel: [ 0.151962] pci_bus 0000:00: resource 8 [mem 0x000c4000-0x000c7fff] +Aug 31 22:50:24 minifree kernel: [ 0.151965] pci_bus 0000:00: resource 9 [mem 0x000c8000-0x000cbfff] +Aug 31 22:50:24 minifree kernel: [ 0.151968] pci_bus 0000:00: resource 10 [mem 0x000cc000-0x000cffff] +Aug 31 22:50:24 minifree kernel: [ 0.151972] pci_bus 0000:00: resource 11 [mem 0x000d0000-0x000d3fff] +Aug 31 22:50:24 minifree kernel: [ 0.151975] pci_bus 0000:00: resource 12 [mem 0x000d4000-0x000d7fff] +Aug 31 22:50:24 minifree kernel: [ 0.151978] pci_bus 0000:00: resource 13 [mem 0x000d8000-0x000dbfff] +Aug 31 22:50:24 minifree kernel: [ 0.151981] pci_bus 0000:00: resource 14 [mem 0x000dc000-0x000dffff] +Aug 31 22:50:24 minifree kernel: [ 0.151985] pci_bus 0000:00: resource 15 [mem 0x000e0000-0x000e3fff] +Aug 31 22:50:24 minifree kernel: [ 0.151988] pci_bus 0000:00: resource 16 [mem 0x000e4000-0x000e7fff] +Aug 31 22:50:24 minifree kernel: [ 0.151991] pci_bus 0000:00: resource 17 [mem 0x000e8000-0x000ebfff] +Aug 31 22:50:24 minifree kernel: [ 0.151994] pci_bus 0000:00: resource 18 [mem 0x000ec000-0x000effff] +Aug 31 22:50:24 minifree kernel: [ 0.151998] pci_bus 0000:00: resource 19 [mem 0x000f0000-0x000fffff] +Aug 31 22:50:24 minifree kernel: [ 0.152014] pci_bus 0000:00: resource 20 [mem 0x80000000-0xfebfffff] +Aug 31 22:50:24 minifree kernel: [ 0.152018] pci_bus 0000:00: resource 21 [mem 0xfed40000-0xfed44fff] +Aug 31 22:50:24 minifree kernel: [ 0.152022] pci_bus 0000:01: resource 0 [io 0x4000-0x4fff] +Aug 31 22:50:24 minifree kernel: [ 0.152025] pci_bus 0000:01: resource 1 [mem 0xe4100000-0xe41fffff] +Aug 31 22:50:24 minifree kernel: [ 0.152029] pci_bus 0000:01: resource 2 [mem 0x80000000-0x801fffff 64bit pref] +Aug 31 22:50:24 minifree kernel: [ 0.152033] pci_bus 0000:05: resource 0 [io 0x2000-0x3fff] +Aug 31 22:50:24 minifree kernel: [ 0.152036] pci_bus 0000:05: resource 1 [mem 0xe0000000-0xe20fffff] +Aug 31 22:50:24 minifree kernel: [ 0.152040] pci_bus 0000:05: resource 2 [mem 0xe2100000-0xe40fffff 64bit pref] +Aug 31 22:50:24 minifree kernel: [ 0.152043] pci_bus 0000:05: resource 4 [io 0x0000-0x0cf7] +Aug 31 22:50:24 minifree kernel: [ 0.152047] pci_bus 0000:05: resource 5 [io 0x0d00-0xffff] +Aug 31 22:50:24 minifree kernel: [ 0.152050] pci_bus 0000:05: resource 6 [mem 0x000a0000-0x000bffff] +Aug 31 22:50:24 minifree kernel: [ 0.152054] pci_bus 0000:05: resource 7 [mem 0x000c0000-0x000c3fff] +Aug 31 22:50:24 minifree kernel: [ 0.152057] pci_bus 0000:05: resource 8 [mem 0x000c4000-0x000c7fff] +Aug 31 22:50:24 minifree kernel: [ 0.152061] pci_bus 0000:05: resource 9 [mem 0x000c8000-0x000cbfff] +Aug 31 22:50:24 minifree kernel: [ 0.152064] pci_bus 0000:05: resource 10 [mem 0x000cc000-0x000cffff] +Aug 31 22:50:24 minifree kernel: [ 0.152067] pci_bus 0000:05: resource 11 [mem 0x000d0000-0x000d3fff] +Aug 31 22:50:24 minifree kernel: [ 0.152071] pci_bus 0000:05: resource 12 [mem 0x000d4000-0x000d7fff] +Aug 31 22:50:24 minifree kernel: [ 0.152074] pci_bus 0000:05: resource 13 [mem 0x000d8000-0x000dbfff] +Aug 31 22:50:24 minifree kernel: [ 0.152077] pci_bus 0000:05: resource 14 [mem 0x000dc000-0x000dffff] +Aug 31 22:50:24 minifree kernel: [ 0.152080] pci_bus 0000:05: resource 15 [mem 0x000e0000-0x000e3fff] +Aug 31 22:50:24 minifree kernel: [ 0.152084] pci_bus 0000:05: resource 16 [mem 0x000e4000-0x000e7fff] +Aug 31 22:50:24 minifree kernel: [ 0.152087] pci_bus 0000:05: resource 17 [mem 0x000e8000-0x000ebfff] +Aug 31 22:50:24 minifree kernel: [ 0.152090] pci_bus 0000:05: resource 18 [mem 0x000ec000-0x000effff] +Aug 31 22:50:24 minifree kernel: [ 0.152093] pci_bus 0000:05: resource 19 [mem 0x000f0000-0x000fffff] +Aug 31 22:50:24 minifree kernel: [ 0.152097] pci_bus 0000:05: resource 20 [mem 0x80000000-0xfebfffff] +Aug 31 22:50:24 minifree kernel: [ 0.152100] pci_bus 0000:05: resource 21 [mem 0xfed40000-0xfed44fff] +Aug 31 22:50:24 minifree kernel: [ 0.152104] pci_bus 0000:06: resource 0 [io 0x2000-0x20ff] +Aug 31 22:50:24 minifree kernel: [ 0.152107] pci_bus 0000:06: resource 1 [io 0x2400-0x24ff] +Aug 31 22:50:24 minifree kernel: [ 0.152111] pci_bus 0000:06: resource 2 [mem 0x84000000-0x87ffffff pref] +Aug 31 22:50:24 minifree kernel: [ 0.152114] pci_bus 0000:06: resource 3 [mem 0x88000000-0x8bffffff] +Aug 31 22:50:24 minifree kernel: [ 0.152167] NET: Registered protocol family 2 +Aug 31 22:50:24 minifree kernel: [ 0.152410] TCP established hash table entries: 16384 (order: 5, 131072 bytes) +Aug 31 22:50:24 minifree kernel: [ 0.152518] TCP bind hash table entries: 16384 (order: 6, 262144 bytes) +Aug 31 22:50:24 minifree kernel: [ 0.152669] TCP: Hash tables configured (established 16384 bind 16384) +Aug 31 22:50:24 minifree kernel: [ 0.152731] TCP: reno registered +Aug 31 22:50:24 minifree kernel: [ 0.152739] UDP hash table entries: 1024 (order: 3, 32768 bytes) +Aug 31 22:50:24 minifree kernel: [ 0.152763] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes) +Aug 31 22:50:24 minifree kernel: [ 0.152861] NET: Registered protocol family 1 +Aug 31 22:50:24 minifree kernel: [ 0.152882] pci 0000:00:02.0: Boot video device +Aug 31 22:50:24 minifree kernel: [ 0.154029] PCI: CLS 64 bytes, default 64 +Aug 31 22:50:24 minifree kernel: [ 0.154130] Trying to unpack rootfs image as initramfs... +Aug 31 22:50:24 minifree kernel: [ 0.891588] Freeing initrd memory: 23964K (ffff880035122000 - ffff880036889000) +Aug 31 22:50:24 minifree kernel: [ 0.891983] microcode: CPU0 sig=0x6f6, pf=0x20, revision=0x0 +Aug 31 22:50:24 minifree kernel: [ 0.891991] microcode: CPU1 sig=0x6f6, pf=0x20, revision=0x0 +Aug 31 22:50:24 minifree kernel: [ 0.892123] microcode: Microcode Update Driver: v2.00 , Peter Oruba +Aug 31 22:50:24 minifree kernel: [ 0.892126] Scanning for low memory corruption every 60 seconds +Aug 31 22:50:24 minifree kernel: [ 0.892509] Initialise system trusted keyring +Aug 31 22:50:24 minifree kernel: [ 0.892592] audit: initializing netlink socket (disabled) +Aug 31 22:50:24 minifree kernel: [ 0.892616] type=2000 audit(1409521794.892:1): initialized +Aug 31 22:50:24 minifree kernel: [ 0.938675] HugeTLB registered 2 MB page size, pre-allocated 0 pages +Aug 31 22:50:24 minifree kernel: [ 0.940706] zbud: loaded +Aug 31 22:50:24 minifree kernel: [ 0.940918] VFS: Disk quotas dquot_6.5.2 +Aug 31 22:50:24 minifree kernel: [ 0.940988] Dquot-cache hash table entries: 512 (order 0, 4096 bytes) +Aug 31 22:50:24 minifree kernel: [ 0.941797] fuse init (API version 7.22) +Aug 31 22:50:24 minifree kernel: [ 0.941924] msgmni has been set to 3980 +Aug 31 22:50:24 minifree kernel: [ 0.942015] Key type big_key registered +Aug 31 22:50:24 minifree kernel: [ 0.942641] Key type asymmetric registered +Aug 31 22:50:24 minifree kernel: [ 0.942645] Asymmetric key parser 'x509' registered +Aug 31 22:50:24 minifree kernel: [ 0.942697] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252) +Aug 31 22:50:24 minifree kernel: [ 0.942747] io scheduler noop registered +Aug 31 22:50:24 minifree kernel: [ 0.942751] io scheduler deadline registered (default) +Aug 31 22:50:24 minifree kernel: [ 0.942789] io scheduler cfq registered +Aug 31 22:50:24 minifree kernel: [ 0.942802] io scheduler bfq registered +Aug 31 22:50:24 minifree kernel: [ 0.942804] BFQ I/O-scheduler version: v7r5 +Aug 31 22:50:24 minifree kernel: [ 0.943133] pcieport 0000:00:1c.0: irq 40 for MSI/MSI-X +Aug 31 22:50:24 minifree kernel: [ 0.943399] pcieport 0000:00:1c.1: irq 41 for MSI/MSI-X +Aug 31 22:50:24 minifree kernel: [ 0.943635] pcieport 0000:00:1c.2: irq 42 for MSI/MSI-X +Aug 31 22:50:24 minifree kernel: [ 0.943873] pcieport 0000:00:1c.3: irq 43 for MSI/MSI-X +Aug 31 22:50:24 minifree kernel: [ 0.944051] pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt +Aug 31 22:50:24 minifree kernel: [ 0.944061] pci 0000:01:00.0: Signaling PME through PCIe PME interrupt +Aug 31 22:50:24 minifree kernel: [ 0.944068] pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded +Aug 31 22:50:24 minifree kernel: [ 0.944102] pcieport 0000:00:1c.1: Signaling PME through PCIe PME interrupt +Aug 31 22:50:24 minifree kernel: [ 0.944109] pcie_pme 0000:00:1c.1:pcie01: service driver pcie_pme loaded +Aug 31 22:50:24 minifree kernel: [ 0.944142] pcieport 0000:00:1c.2: Signaling PME through PCIe PME interrupt +Aug 31 22:50:24 minifree kernel: [ 0.944149] pcie_pme 0000:00:1c.2:pcie01: service driver pcie_pme loaded +Aug 31 22:50:24 minifree kernel: [ 0.944178] pcieport 0000:00:1c.3: Signaling PME through PCIe PME interrupt +Aug 31 22:50:24 minifree kernel: [ 0.944185] pcie_pme 0000:00:1c.3:pcie01: service driver pcie_pme loaded +Aug 31 22:50:24 minifree kernel: [ 0.944207] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 +Aug 31 22:50:24 minifree kernel: [ 0.944253] pciehp 0000:00:1c.0:pcie04: HPC vendor_id 8086 device_id 27d0 ss_vid 8086 ss_did 27d0 +Aug 31 22:50:24 minifree kernel: [ 0.944297] pciehp 0000:00:1c.0:pcie04: service driver pciehp loaded +Aug 31 22:50:24 minifree kernel: [ 0.944307] pciehp: PCI Express Hot Plug Controller Driver version: 0.4 +Aug 31 22:50:24 minifree kernel: [ 0.944385] intel_idle: does not run on family 6 model 15 +Aug 31 22:50:24 minifree kernel: [ 0.944397] ipmi message handler version 39.2 +Aug 31 22:50:24 minifree kernel: [ 0.944733] ACPI: AC Adapter [AC] (off-line) +Aug 31 22:50:24 minifree kernel: [ 0.944807] ACPI Exception: AE_NOT_FOUND, Error reading AC Adapter state (20131115/ac-108) +Aug 31 22:50:24 minifree kernel: [ 0.945053] input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0A08:00/device:24/PNP0C09:00/PNP0C0E:00/input/input0 +Aug 31 22:50:24 minifree kernel: [ 0.945061] ACPI: Sleep Button [SLPB] +Aug 31 22:50:24 minifree kernel: [ 0.945124] input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0A08:00/device:24/PNP0C09:00/PNP0C0D:00/input/input1 +Aug 31 22:50:24 minifree kernel: [ 0.945243] ACPI: Lid Switch [LID] +Aug 31 22:50:24 minifree kernel: [ 0.945307] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 +Aug 31 22:50:24 minifree kernel: [ 0.945312] ACPI: Power Button [PWRF] +Aug 31 22:50:24 minifree kernel: [ 0.946267] Monitor-Mwait will be used to enter C-1 state +Aug 31 22:50:24 minifree kernel: [ 0.946279] tsc: Marking TSC unstable due to TSC halts in idle +Aug 31 22:50:24 minifree kernel: [ 0.946288] ACPI: acpi_idle registered with cpuidle +Aug 31 22:50:24 minifree kernel: [ 0.947899] thermal LNXTHERM:00: registered as thermal_zone0 +Aug 31 22:50:24 minifree kernel: [ 0.947904] ACPI: Thermal Zone [THM0] (39 C) +Aug 31 22:50:24 minifree kernel: [ 0.948530] thermal LNXTHERM:01: registered as thermal_zone1 +Aug 31 22:50:24 minifree kernel: [ 0.948533] ACPI: Thermal Zone [THM1] (27 C) +Aug 31 22:50:24 minifree kernel: [ 0.948573] GHES: HEST is not enabled! +Aug 31 22:50:24 minifree kernel: [ 0.948770] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled +Aug 31 22:50:24 minifree kernel: [ 0.952564] Linux agpgart interface v0.103 +Aug 31 22:50:24 minifree kernel: [ 0.952903] agpgart-intel 0000:00:00.0: Intel 945GM Chipset +Aug 31 22:50:24 minifree kernel: [ 0.952979] agpgart-intel 0000:00:00.0: detected gtt size: 262144K total, 262144K mappable +Aug 31 22:50:24 minifree kernel: [ 0.954238] agpgart-intel 0000:00:00.0: detected 8192K stolen memory +Aug 31 22:50:24 minifree kernel: [ 0.954581] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xd0000000 +Aug 31 22:50:24 minifree kernel: [ 0.960749] brd: module loaded +Aug 31 22:50:24 minifree kernel: [ 0.962506] loop: module loaded +Aug 31 22:50:24 minifree kernel: [ 0.962983] ata_piix 0000:00:1f.1: version 2.13 +Aug 31 22:50:24 minifree kernel: [ 0.963770] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +Aug 31 22:50:24 minifree kernel: [ 0.963780] ACPI: Battery Slot [BAT0] (battery present) +Aug 31 22:50:24 minifree kernel: [ 0.963927] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +Aug 31 22:50:24 minifree kernel: [ 0.963935] ACPI: Battery Slot [BAT1] (battery absent) +Aug 31 22:50:24 minifree kernel: [ 0.964039] scsi0 : ata_piix +Aug 31 22:50:24 minifree kernel: [ 0.964177] scsi1 : ata_piix +Aug 31 22:50:24 minifree kernel: [ 0.964231] ata1: PATA max UDMA/100 cmd 0x1f0 ctl 0x3f6 bmdma 0x5080 irq 14 +Aug 31 22:50:24 minifree kernel: [ 0.964235] ata2: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x5088 irq 15 +Aug 31 22:50:24 minifree kernel: [ 0.964290] ata1: port disabled--ignoring +Aug 31 22:50:24 minifree kernel: [ 0.964327] ata2: port disabled--ignoring +Aug 31 22:50:24 minifree kernel: [ 0.964709] libphy: Fixed MDIO Bus: probed +Aug 31 22:50:24 minifree kernel: [ 0.964859] tun: Universal TUN/TAP device driver, 1.6 +Aug 31 22:50:24 minifree kernel: [ 0.964861] tun: (C) 1999-2004 Max Krasnyansky +Aug 31 22:50:24 minifree kernel: [ 0.964949] PPP generic driver version 2.4.2 +Aug 31 22:50:24 minifree kernel: [ 0.965035] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver +Aug 31 22:50:24 minifree kernel: [ 0.965043] ehci-pci: EHCI PCI platform driver +Aug 31 22:50:24 minifree kernel: [ 0.965215] ehci-pci 0000:00:1d.7: EHCI Host Controller +Aug 31 22:50:24 minifree kernel: [ 0.965228] ehci-pci 0000:00:1d.7: new USB bus registered, assigned bus number 1 +Aug 31 22:50:24 minifree kernel: [ 0.965248] ehci-pci 0000:00:1d.7: debug port 1 +Aug 31 22:50:24 minifree kernel: [ 0.969175] ehci-pci 0000:00:1d.7: cache line size of 64 is not supported +Aug 31 22:50:24 minifree kernel: [ 0.969198] ehci-pci 0000:00:1d.7: irq 19, io mem 0xe4344000 +Aug 31 22:50:24 minifree kernel: [ 0.980055] ehci-pci 0000:00:1d.7: USB 2.0 started, EHCI 1.00 +Aug 31 22:50:24 minifree kernel: [ 0.980167] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 +Aug 31 22:50:24 minifree kernel: [ 0.980171] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +Aug 31 22:50:24 minifree kernel: [ 0.980174] usb usb1: Product: EHCI Host Controller +Aug 31 22:50:24 minifree kernel: [ 0.980178] usb usb1: Manufacturer: Linux 3.13.0-34-generic ehci_hcd +Aug 31 22:50:24 minifree kernel: [ 0.980181] usb usb1: SerialNumber: 0000:00:1d.7 +Aug 31 22:50:24 minifree kernel: [ 0.980361] hub 1-0:1.0: USB hub found +Aug 31 22:50:24 minifree kernel: [ 0.980376] hub 1-0:1.0: 8 ports detected +Aug 31 22:50:24 minifree kernel: [ 0.980772] ehci-platform: EHCI generic platform driver +Aug 31 22:50:24 minifree kernel: [ 0.980789] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver +Aug 31 22:50:24 minifree kernel: [ 0.980791] ohci-pci: OHCI PCI platform driver +Aug 31 22:50:24 minifree kernel: [ 0.980807] ohci-platform: OHCI generic platform driver +Aug 31 22:50:24 minifree kernel: [ 0.980820] uhci_hcd: USB Universal Host Controller Interface driver +Aug 31 22:50:24 minifree kernel: [ 0.980960] uhci_hcd 0000:00:1d.0: UHCI Host Controller +Aug 31 22:50:24 minifree kernel: [ 0.980969] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2 +Aug 31 22:50:24 minifree kernel: [ 0.981013] uhci_hcd 0000:00:1d.0: irq 16, io base 0x00005000 +Aug 31 22:50:24 minifree kernel: [ 0.981094] usb usb2: New USB device found, idVendor=1d6b, idProduct=0001 +Aug 31 22:50:24 minifree kernel: [ 0.981099] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +Aug 31 22:50:24 minifree kernel: [ 0.981102] usb usb2: Product: UHCI Host Controller +Aug 31 22:50:24 minifree kernel: [ 0.981106] usb usb2: Manufacturer: Linux 3.13.0-34-generic uhci_hcd +Aug 31 22:50:24 minifree kernel: [ 0.981109] usb usb2: SerialNumber: 0000:00:1d.0 +Aug 31 22:50:24 minifree kernel: [ 0.981266] hub 2-0:1.0: USB hub found +Aug 31 22:50:24 minifree kernel: [ 0.981279] hub 2-0:1.0: 2 ports detected +Aug 31 22:50:24 minifree kernel: [ 0.981522] uhci_hcd 0000:00:1d.1: UHCI Host Controller +Aug 31 22:50:24 minifree kernel: [ 0.981530] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 3 +Aug 31 22:50:24 minifree kernel: [ 0.981575] uhci_hcd 0000:00:1d.1: irq 17, io base 0x00005020 +Aug 31 22:50:24 minifree kernel: [ 0.981654] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001 +Aug 31 22:50:24 minifree kernel: [ 0.981658] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +Aug 31 22:50:24 minifree kernel: [ 0.981662] usb usb3: Product: UHCI Host Controller +Aug 31 22:50:24 minifree kernel: [ 0.981665] usb usb3: Manufacturer: Linux 3.13.0-34-generic uhci_hcd +Aug 31 22:50:24 minifree kernel: [ 0.981669] usb usb3: SerialNumber: 0000:00:1d.1 +Aug 31 22:50:24 minifree kernel: [ 0.981825] hub 3-0:1.0: USB hub found +Aug 31 22:50:24 minifree kernel: [ 0.981840] hub 3-0:1.0: 2 ports detected +Aug 31 22:50:24 minifree kernel: [ 0.982079] uhci_hcd 0000:00:1d.2: UHCI Host Controller +Aug 31 22:50:24 minifree kernel: [ 0.982090] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 4 +Aug 31 22:50:24 minifree kernel: [ 0.982135] uhci_hcd 0000:00:1d.2: irq 18, io base 0x00005040 +Aug 31 22:50:24 minifree kernel: [ 0.982218] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001 +Aug 31 22:50:24 minifree kernel: [ 0.982222] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +Aug 31 22:50:24 minifree kernel: [ 0.982225] usb usb4: Product: UHCI Host Controller +Aug 31 22:50:24 minifree kernel: [ 0.982229] usb usb4: Manufacturer: Linux 3.13.0-34-generic uhci_hcd +Aug 31 22:50:24 minifree kernel: [ 0.982232] usb usb4: SerialNumber: 0000:00:1d.2 +Aug 31 22:50:24 minifree kernel: [ 0.982388] hub 4-0:1.0: USB hub found +Aug 31 22:50:24 minifree kernel: [ 0.982401] hub 4-0:1.0: 2 ports detected +Aug 31 22:50:24 minifree kernel: [ 0.982648] uhci_hcd 0000:00:1d.3: UHCI Host Controller +Aug 31 22:50:24 minifree kernel: [ 0.982656] uhci_hcd 0000:00:1d.3: new USB bus registered, assigned bus number 5 +Aug 31 22:50:24 minifree kernel: [ 0.982688] uhci_hcd 0000:00:1d.3: irq 19, io base 0x00005060 +Aug 31 22:50:24 minifree kernel: [ 0.982769] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001 +Aug 31 22:50:24 minifree kernel: [ 0.982774] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +Aug 31 22:50:24 minifree kernel: [ 0.982777] usb usb5: Product: UHCI Host Controller +Aug 31 22:50:24 minifree kernel: [ 0.982781] usb usb5: Manufacturer: Linux 3.13.0-34-generic uhci_hcd +Aug 31 22:50:24 minifree kernel: [ 0.982784] usb usb5: SerialNumber: 0000:00:1d.3 +Aug 31 22:50:24 minifree kernel: [ 0.982935] hub 5-0:1.0: USB hub found +Aug 31 22:50:24 minifree kernel: [ 0.982947] hub 5-0:1.0: 2 ports detected +Aug 31 22:50:24 minifree kernel: [ 0.983162] i8042: PNP: PS/2 Controller [PNP0303:PS2K,PNP0f13:PS2M] at 0x60,0x64 irq 1,12 +Aug 31 22:50:24 minifree kernel: [ 0.996933] serio: i8042 KBD port at 0x60,0x64 irq 1 +Aug 31 22:50:24 minifree kernel: [ 0.996948] serio: i8042 AUX port at 0x60,0x64 irq 12 +Aug 31 22:50:24 minifree kernel: [ 0.997177] mousedev: PS/2 mouse device common for all mice +Aug 31 22:50:24 minifree kernel: [ 0.997526] rtc_cmos 00:06: RTC can wake from S4 +Aug 31 22:50:24 minifree kernel: [ 0.997724] rtc_cmos 00:06: rtc core: registered rtc_cmos as rtc0 +Aug 31 22:50:24 minifree kernel: [ 0.997761] rtc_cmos 00:06: alarms up to one month, y3k, 242 bytes nvram, hpet irqs +Aug 31 22:50:24 minifree kernel: [ 0.997869] device-mapper: uevent: version 1.0.3 +Aug 31 22:50:24 minifree kernel: [ 0.997988] device-mapper: ioctl: 4.27.0-ioctl (2013-10-30) initialised: dm-devel@redhat.com +Aug 31 22:50:24 minifree kernel: [ 0.998000] ledtrig-cpu: registered to indicate activity on CPUs +Aug 31 22:50:24 minifree kernel: [ 0.998153] TCP: cubic registered +Aug 31 22:50:24 minifree kernel: [ 0.998301] NET: Registered protocol family 10 +Aug 31 22:50:24 minifree kernel: [ 0.998581] NET: Registered protocol family 17 +Aug 31 22:50:24 minifree kernel: [ 0.998598] Key type dns_resolver registered +Aug 31 22:50:24 minifree kernel: [ 0.999003] Loading compiled-in X.509 certificates +Aug 31 22:50:24 minifree kernel: [ 1.000843] Loaded X.509 cert 'Magrathea: Glacier signing key: 0cadd161e4220740356b3090aabd2b3fcb83a5d0' +Aug 31 22:50:24 minifree kernel: [ 1.000865] registered taskstats version 1 +Aug 31 22:50:24 minifree kernel: [ 1.004840] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3 +Aug 31 22:50:24 minifree kernel: [ 1.006130] Key type trusted registered +Aug 31 22:50:24 minifree kernel: [ 1.010130] Key type encrypted registered +Aug 31 22:50:24 minifree kernel: [ 1.015532] AppArmor: AppArmor sha1 policy hashing enabled +Aug 31 22:50:24 minifree kernel: [ 1.015538] IMA: No TPM chip found, activating TPM-bypass! +Aug 31 22:50:24 minifree kernel: [ 1.015959] regulator-dummy: disabling +Aug 31 22:50:24 minifree kernel: [ 1.016046] Magic number: 10:359:855 +Aug 31 22:50:24 minifree kernel: [ 1.016202] rtc_cmos 00:06: setting system clock to 2014-08-31 21:49:55 UTC (1409521795) +Aug 31 22:50:24 minifree kernel: [ 1.017114] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found +Aug 31 22:50:24 minifree kernel: [ 1.017120] EDD information not available. +Aug 31 22:50:24 minifree kernel: [ 1.017162] PM: Hibernation image not present or could not be loaded. +Aug 31 22:50:24 minifree kernel: [ 1.019541] Freeing unused kernel memory: 1336K (ffffffff81d20000 - ffffffff81e6e000) +Aug 31 22:50:24 minifree kernel: [ 1.019544] Write protecting the kernel read-only data: 12288k +Aug 31 22:50:24 minifree kernel: [ 1.023552] Freeing unused kernel memory: 788K (ffff88000173b000 - ffff880001800000) +Aug 31 22:50:24 minifree kernel: [ 1.026751] Freeing unused kernel memory: 680K (ffff880001b56000 - ffff880001c00000) +Aug 31 22:50:24 minifree kernel: [ 1.094875] pps_core: LinuxPPS API ver. 1 registered +Aug 31 22:50:24 minifree kernel: [ 1.094880] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti +Aug 31 22:50:24 minifree kernel: [ 1.098290] [drm] Initialized drm 1.1.0 20060810 +Aug 31 22:50:24 minifree kernel: [ 1.102066] ACPI: Video Device [GFX0] (multi-head: yes rom: no post: no) +Aug 31 22:50:24 minifree kernel: [ 1.106256] PTP clock support registered +Aug 31 22:50:24 minifree kernel: [ 1.113596] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k +Aug 31 22:50:24 minifree kernel: [ 1.113602] e1000e: Copyright(c) 1999 - 2013 Intel Corporation. +Aug 31 22:50:24 minifree kernel: [ 1.124513] e1000e 0000:01:00.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode +Aug 31 22:50:24 minifree kernel: [ 1.124561] e1000e 0000:01:00.0: irq 44 for MSI/MSI-X +Aug 31 22:50:24 minifree kernel: [ 1.124660] acpi device:04: registered as cooling_device2 +Aug 31 22:50:24 minifree kernel: [ 1.124749] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input5 +Aug 31 22:50:24 minifree kernel: [ 1.147236] [drm:i915_dump_device_info], i915 device info: gen=3, pciid=0x27a2 flags=is_mobile,is_i945gm,has_hotplug,cursor_needs_physical,has_overlay,overlay_needs_physical,supports_tv, +Aug 31 22:50:24 minifree kernel: [ 1.147327] [drm:intel_detect_pch], No PCH found. +Aug 31 22:50:24 minifree kernel: [ 1.147333] [drm] Memory usable by graphics device = 256M +Aug 31 22:50:24 minifree kernel: [ 1.147335] [drm:i915_gem_gtt_init], GMADR size = 256M +Aug 31 22:50:24 minifree kernel: [ 1.147338] [drm:i915_gem_gtt_init], GTT stolen size = 8M +Aug 31 22:50:24 minifree kernel: [ 1.149656] sdhci: Secure Digital Host Controller Interface driver +Aug 31 22:50:24 minifree kernel: [ 1.149659] sdhci: Copyright(c) Pierre Ossman +Aug 31 22:50:24 minifree kernel: [ 1.152120] sdhci-pci 0000:05:00.2: SDHCI controller found [1180:0822] (rev 18) +Aug 31 22:50:24 minifree kernel: [ 1.152136] pci 0000:00:1e.0: enabling device (0004 -> 0007) +Aug 31 22:50:24 minifree kernel: [ 1.180299] [drm:intel_opregion_setup], graphic opregion physical addr: 0x0 +Aug 31 22:50:24 minifree kernel: [ 1.180306] [drm:intel_opregion_setup], ACPI OpRegion not supported! +Aug 31 22:50:24 minifree kernel: [ 1.180346] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). +Aug 31 22:50:24 minifree kernel: [ 1.180348] [drm] Driver supports precise vblank timestamp query. +Aug 31 22:50:24 minifree kernel: [ 1.180351] [drm:init_vbt_defaults], Set default to SSC at 100MHz +Aug 31 22:50:24 minifree kernel: [ 1.180358] i915 0000:00:02.0: Invalid ROM contents +Aug 31 22:50:24 minifree kernel: [ 1.180360] [drm:intel_parse_bios], VBT signature missing +Aug 31 22:50:24 minifree kernel: [ 1.180363] [drm] failed to find VBIOS tables +Aug 31 22:50:24 minifree kernel: [ 1.180369] [drm:intel_dsm_pci_probe], no _DSM method for intel device +Aug 31 22:50:24 minifree kernel: [ 1.180383] [drm:i915_gem_init_stolen], found 8388608 bytes of stolen memory at 7f800000 +Aug 31 22:50:24 minifree kernel: [ 1.180409] [drm] GPU crash dump saved to /sys/class/drm/card0/error +Aug 31 22:50:24 minifree kernel: [ 1.180412] [drm:intel_modeset_init], 2 display pipes available. +Aug 31 22:50:24 minifree kernel: [ 1.180419] [drm:intel_crtc_init], swapping pipes & planes for FBC +Aug 31 22:50:24 minifree kernel: [ 1.180421] [drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace. +Aug 31 22:50:24 minifree kernel: [ 1.180423] [drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel +Aug 31 22:50:24 minifree kernel: [ 1.180425] [drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue. +Aug 31 22:50:24 minifree kernel: [ 1.180427] [drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it. +Aug 31 22:50:24 minifree kernel: [ 1.180429] [drm:intel_modeset_init], pipe A sprite A init failed: -19 +Aug 31 22:50:24 minifree kernel: [ 1.180435] [drm:intel_crtc_init], swapping pipes & planes for FBC +Aug 31 22:50:24 minifree kernel: [ 1.180437] [drm:intel_modeset_init], pipe B sprite B init failed: -19 +Aug 31 22:50:24 minifree kernel: [ 1.180440] [drm:intel_shared_dpll_init], 0 shared PLLs initialized +Aug 31 22:50:24 minifree kernel: [ 1.180448] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem +Aug 31 22:50:24 minifree kernel: [ 1.180450] i915: render error detected, EIR: 0x00000010 +Aug 31 22:50:24 minifree kernel: [ 1.180452] i915: page table error +Aug 31 22:50:24 minifree kernel: [ 1.180454] i915: PGTBL_ER: 0x00000012 +Aug 31 22:50:24 minifree kernel: [ 1.180457] [drm:i915_report_and_clear_eir] *ERROR* EIR stuck: 0x00000010, masking +Aug 31 22:50:24 minifree kernel: [ 1.180463] [drm:i915_irq_handler], pipe B underrun +Aug 31 22:50:24 minifree kernel: [ 1.180469] i915: render error detected, EIR: 0x00000010 +Aug 31 22:50:24 minifree kernel: [ 1.180471] i915: page table error +Aug 31 22:50:24 minifree kernel: [ 1.180473] i915: PGTBL_ER: 0x00000012 +Aug 31 22:50:24 minifree kernel: [ 1.182043] sdhci-pci 0000:05:00.2: Will use DMA mode even though HW doesn't fully claim to support it. +Aug 31 22:50:24 minifree kernel: [ 1.182056] sdhci-pci 0000:05:00.2: dummy supplies not allowed +Aug 31 22:50:24 minifree kernel: [ 1.182059] mmc0: no vqmmc regulator found +Aug 31 22:50:24 minifree kernel: [ 1.182062] sdhci-pci 0000:05:00.2: dummy supplies not allowed +Aug 31 22:50:24 minifree kernel: [ 1.182064] mmc0: no vmmc regulator found +Aug 31 22:50:24 minifree kernel: [ 1.183062] sdhci-pci 0000:05:00.2: Will use DMA mode even though HW doesn't fully claim to support it. +Aug 31 22:50:24 minifree kernel: [ 1.183862] mmc0: SDHCI controller on PCI [0000:05:00.2] using DMA +Aug 31 22:50:24 minifree kernel: [ 1.236462] e1000e 0000:01:00.0 eth0: (PCI Express:2.5GT/s:Width x1) 00:16:d3:b6:d0:98 +Aug 31 22:50:24 minifree kernel: [ 1.236469] e1000e 0000:01:00.0 eth0: Intel(R) PRO/1000 Network Connection +Aug 31 22:50:24 minifree kernel: [ 1.236549] e1000e 0000:01:00.0 eth0: MAC: 2, PHY: 2, PBA No: 005302-003 +Aug 31 22:50:24 minifree kernel: [ 1.248155] firewire_ohci 0000:05:00.1: added OHCI v1.10 device as card 0, 4 IR + 4 IT contexts, quirks 0x11 +Aug 31 22:50:24 minifree kernel: [ 1.264281] [drm:intel_lvds_init], using preferred mode from EDID: +Aug 31 22:50:24 minifree kernel: [ 1.264287] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +Aug 31 22:50:24 minifree kernel: [ 1.264297] [drm:intel_lvds_init], detected single-link lvds configuration +Aug 31 22:50:24 minifree kernel: [ 1.264356] [drm:intel_panel_get_backlight], get backlight PWM = 24832 +Aug 31 22:50:24 minifree kernel: [ 1.264360] [drm:intel_panel_get_max_backlight], max backlight PWM = 24832 +Aug 31 22:50:24 minifree kernel: [ 1.264505] [drm:i915_gem_setup_global_gtt], clearing unused GTT space: [0, ffff000] +Aug 31 22:50:24 minifree kernel: [ 1.264889] [drm:i915_gem_object_create_stolen], creating stolen object: size=20000 +Aug 31 22:50:24 minifree kernel: [ 1.264897] [drm:i915_pages_create_for_stolen], offset=0x0, size=131072 +Aug 31 22:50:24 minifree kernel: [ 1.264946] [drm:i915_gem_context_init], Disabling HW Contexts; old hardware +Aug 31 22:50:24 minifree kernel: [ 1.264996] [drm] initialized overlay support +Aug 31 22:50:24 minifree kernel: [ 1.265002] [drm:intel_modeset_readout_hw_state], [CRTC:3] hw state readout: disabled +Aug 31 22:50:24 minifree kernel: [ 1.265012] [drm:intel_modeset_readout_hw_state], [CRTC:4] hw state readout: enabled +Aug 31 22:50:24 minifree kernel: [ 1.265017] [drm:intel_modeset_readout_hw_state], [ENCODER:6:LVDS-6] hw state readout: enabled, pipe B +Aug 31 22:50:24 minifree kernel: [ 1.265022] [drm:intel_modeset_readout_hw_state], [ENCODER:16:DAC-16] hw state readout: disabled, pipe A +Aug 31 22:50:24 minifree kernel: [ 1.265026] [drm:intel_modeset_readout_hw_state], [ENCODER:18:TV-18] hw state readout: disabled, pipe A +Aug 31 22:50:24 minifree kernel: [ 1.265031] [drm:intel_modeset_readout_hw_state], [CONNECTOR:5:LVDS-1] hw state readout: enabled +Aug 31 22:50:24 minifree kernel: [ 1.265035] [drm:intel_modeset_readout_hw_state], [CONNECTOR:15:VGA-1] hw state readout: disabled +Aug 31 22:50:24 minifree kernel: [ 1.265039] [drm:intel_modeset_readout_hw_state], [CONNECTOR:17:SVIDEO-1] hw state readout: disabled +Aug 31 22:50:24 minifree kernel: [ 1.265044] [drm:intel_dump_pipe_config], [CRTC:3][setup_hw_state] config for pipe A +Aug 31 22:50:24 minifree kernel: [ 1.265047] [drm:intel_dump_pipe_config], cpu_transcoder: A +Aug 31 22:50:24 minifree kernel: [ 1.265050] [drm:intel_dump_pipe_config], pipe bpp: 0, dithering: 0 +Aug 31 22:50:24 minifree kernel: [ 1.265053] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:50:24 minifree kernel: [ 1.265057] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:50:24 minifree kernel: [ 1.265060] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:50:24 minifree kernel: [ 1.265063] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 +Aug 31 22:50:24 minifree kernel: [ 1.265067] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:50:24 minifree kernel: [ 1.265070] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 +Aug 31 22:50:24 minifree kernel: [ 1.265074] [drm:intel_dump_crtc_timings], crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0 +Aug 31 22:50:24 minifree kernel: [ 1.265078] [drm:intel_dump_pipe_config], port clock: 0 +Aug 31 22:50:24 minifree kernel: [ 1.265081] [drm:intel_dump_pipe_config], pipe src size: 0x0 +Aug 31 22:50:24 minifree kernel: [ 1.265084] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:50:24 minifree kernel: [ 1.265087] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:50:24 minifree kernel: [ 1.265090] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:50:24 minifree kernel: [ 1.265093] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:50:24 minifree kernel: [ 1.265097] [drm:intel_dump_pipe_config], [CRTC:4][setup_hw_state] config for pipe B +Aug 31 22:50:24 minifree kernel: [ 1.265100] [drm:intel_dump_pipe_config], cpu_transcoder: B +Aug 31 22:50:24 minifree kernel: [ 1.265102] [drm:intel_dump_pipe_config], pipe bpp: 0, dithering: 0 +Aug 31 22:50:24 minifree kernel: [ 1.265105] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:50:24 minifree kernel: [ 1.265109] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:50:24 minifree kernel: [ 1.265112] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:50:24 minifree kernel: [ 1.265115] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 640 0 0 0 400 0 0 0 0x0 0x0 +Aug 31 22:50:24 minifree kernel: [ 1.265119] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:50:24 minifree kernel: [ 1.265122] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0xa +Aug 31 22:50:24 minifree kernel: [ 1.265126] [drm:intel_dump_crtc_timings], crtc timings: 45982 1024 1048 1184 1344 768 779 1 806, type: 0x0 flags: 0xa +Aug 31 22:50:24 minifree kernel: [ 1.265130] [drm:intel_dump_pipe_config], port clock: 45982 +Aug 31 22:50:24 minifree kernel: [ 1.265133] [drm:intel_dump_pipe_config], pipe src size: 640x400 +Aug 31 22:50:24 minifree kernel: [ 1.265136] [drm:intel_dump_pipe_config], gmch pfit: control: 0x80000220, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:50:24 minifree kernel: [ 1.265139] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:50:24 minifree kernel: [ 1.265142] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:50:24 minifree kernel: [ 1.265145] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:50:24 minifree kernel: [ 1.265149] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 1.265153] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:50:24 minifree kernel: [ 1.265157] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:50:24 minifree kernel: [ 1.265160] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 1.265163] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:50:24 minifree kernel: [ 1.265166] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 1.265183] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 1.265187] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 1.265204] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +Aug 31 22:50:24 minifree kernel: [ 1.265208] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +Aug 31 22:50:24 minifree kernel: [ 1.265213] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:50:24 minifree kernel: [ 1.265218] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:50:24 minifree kernel: [ 1.265222] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +Aug 31 22:50:24 minifree kernel: [ 1.265227] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +Aug 31 22:50:24 minifree kernel: [ 1.265232] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +Aug 31 22:50:24 minifree kernel: [ 1.265235] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +Aug 31 22:50:24 minifree kernel: [ 1.280167] [drm:intel_crt_detect], CRT not detected via hotplug +Aug 31 22:50:24 minifree kernel: [ 1.284121] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +Aug 31 22:50:24 minifree kernel: [ 1.284128] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:50:24 minifree kernel: [ 1.284131] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +Aug 31 22:50:24 minifree kernel: [ 1.284134] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +Aug 31 22:50:24 minifree kernel: [ 1.284413] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:50:24 minifree kernel: [ 1.284416] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +Aug 31 22:50:24 minifree kernel: [ 1.284419] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +Aug 31 22:50:24 minifree kernel: [ 1.284423] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +Aug 31 22:50:24 minifree kernel: [ 1.284429] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:50:24 minifree kernel: [ 1.284432] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +Aug 31 22:50:24 minifree kernel: [ 1.284437] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 1.284441] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +Aug 31 22:50:24 minifree kernel: [ 1.284454] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +Aug 31 22:50:24 minifree kernel: [ 1.284460] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +Aug 31 22:50:24 minifree kernel: [ 1.284464] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +Aug 31 22:50:24 minifree kernel: [ 1.284467] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +Aug 31 22:50:24 minifree kernel: [ 1.284470] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +Aug 31 22:50:24 minifree kernel: [ 1.284473] [drm:intel_dump_pipe_config], cpu_transcoder: A +Aug 31 22:50:24 minifree kernel: [ 1.284476] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +Aug 31 22:50:24 minifree kernel: [ 1.284479] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:50:24 minifree kernel: [ 1.284483] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:50:24 minifree kernel: [ 1.284486] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:50:24 minifree kernel: [ 1.284488] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:50:24 minifree kernel: [ 1.284493] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:50:24 minifree kernel: [ 1.284496] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:50:24 minifree kernel: [ 1.284501] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +Aug 31 22:50:24 minifree kernel: [ 1.284505] [drm:intel_dump_pipe_config], port clock: 108000 +Aug 31 22:50:24 minifree kernel: [ 1.284508] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +Aug 31 22:50:24 minifree kernel: [ 1.284511] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:50:24 minifree kernel: [ 1.284514] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:50:24 minifree kernel: [ 1.284517] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:50:24 minifree kernel: [ 1.284520] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:50:24 minifree kernel: [ 1.292029] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 5120 +Aug 31 22:50:24 minifree kernel: [ 1.292040] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +Aug 31 22:50:24 minifree kernel: [ 1.297668] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:50:24 minifree kernel: [ 1.297673] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:50:24 minifree kernel: [ 1.297676] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +Aug 31 22:50:24 minifree kernel: [ 1.297679] [drm:intel_calculate_wm], FIFO watermark level: -5 +Aug 31 22:50:24 minifree kernel: [ 1.297681] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 1 +Aug 31 22:50:24 minifree kernel: [ 1.297685] [drm:i9xx_update_wm], self-refresh entries: 80 +Aug 31 22:50:24 minifree kernel: [ 1.297687] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 1, C: 2, SR 47 +Aug 31 22:50:24 minifree kernel: [ 1.297691] [drm:i9xx_update_wm], memory self refresh enabled +Aug 31 22:50:24 minifree kernel: [ 1.320114] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 1.320123] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:50:24 minifree kernel: [ 1.320128] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:50:24 minifree kernel: [ 1.320133] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:50:24 minifree kernel: [ 1.320138] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 1.320142] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:50:24 minifree kernel: [ 1.320155] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 1.360100] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +Aug 31 22:50:24 minifree kernel: [ 1.360106] [drm:intel_tv_detect_type], Unrecognised TV connection +Aug 31 22:50:24 minifree kernel: [ 1.376107] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 1.376114] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +Aug 31 22:50:24 minifree kernel: [ 1.421067] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:50:24 minifree kernel: [ 1.421071] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:50:24 minifree kernel: [ 1.421074] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29 +Aug 31 22:50:24 minifree kernel: [ 1.421077] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1 +Aug 31 22:50:24 minifree kernel: [ 1.421080] [drm:i9xx_update_wm], memory self refresh disabled +Aug 31 22:50:24 minifree kernel: [ 1.421087] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 1.421091] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:50:24 minifree kernel: [ 1.421094] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:50:24 minifree kernel: [ 1.421098] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 1.421101] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:50:24 minifree kernel: [ 1.421104] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 1.421246] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +Aug 31 22:50:24 minifree kernel: [ 1.421251] [drm:drm_setup_crtcs], +Aug 31 22:50:24 minifree kernel: [ 1.421254] [drm:drm_enable_connectors], connector 5 enabled? yes +Aug 31 22:50:24 minifree kernel: [ 1.421257] [drm:drm_enable_connectors], connector 15 enabled? no +Aug 31 22:50:24 minifree kernel: [ 1.421260] [drm:drm_enable_connectors], connector 17 enabled? no +Aug 31 22:50:24 minifree kernel: [ 1.421263] [drm:drm_target_preferred], looking for cmdline mode on connector 5 +Aug 31 22:50:24 minifree kernel: [ 1.421266] [drm:drm_target_preferred], looking for preferred mode on connector 5 +Aug 31 22:50:24 minifree kernel: [ 1.421268] [drm:drm_target_preferred], found mode 1024x768 +Aug 31 22:50:24 minifree kernel: [ 1.421271] [drm:drm_setup_crtcs], picking CRTCs for 4096x4096 config +Aug 31 22:50:24 minifree kernel: [ 1.421275] [drm:drm_setup_crtcs], desired mode 1024x768 set on crtc 4 +Aug 31 22:50:24 minifree kernel: [ 1.421281] [drm:i915_gem_object_create_stolen], creating stolen object: size=300000 +Aug 31 22:50:24 minifree kernel: [ 1.421285] [drm:i915_pages_create_for_stolen], offset=0x20000, size=3145728 +Aug 31 22:50:24 minifree kernel: [ 1.422732] [drm:intelfb_create], allocated 1024x768 fb: 0x00020000, bo ffff880035eaa300 +Aug 31 22:50:24 minifree kernel: [ 1.422872] fbcon: inteldrmfb (fb0) is primary device +Aug 31 22:50:24 minifree kernel: [ 1.423535] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] +Aug 31 22:50:24 minifree kernel: [ 1.423538] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0 +Aug 31 22:50:24 minifree kernel: [ 1.423541] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 1.423544] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +Aug 31 22:50:24 minifree kernel: [ 1.423546] [drm:intel_set_config_compute_mode_changes], inactive crtc, full mode set +Aug 31 22:50:24 minifree kernel: [ 1.423548] [drm:intel_set_config_compute_mode_changes], modes are different, full mode set +Aug 31 22:50:24 minifree kernel: [ 1.423552] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0 +Aug 31 22:50:24 minifree kernel: [ 1.423556] [drm:drm_mode_debug_printmodeline], Modeline 32:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +Aug 31 22:50:24 minifree kernel: [ 1.423558] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=1, fb_changed=0 +Aug 31 22:50:24 minifree kernel: [ 1.423560] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 1.423563] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 2, prepare: 2, disable: 0 +Aug 31 22:50:24 minifree kernel: [ 1.423566] [drm:connected_sink_compute_bpp], [CONNECTOR:5:LVDS-1] checking for sink bpp constrains +Aug 31 22:50:24 minifree kernel: [ 1.423570] [drm:intel_lvds_compute_config], forcing display bpp (was 24) to LVDS (18) +Aug 31 22:50:24 minifree kernel: [ 1.423573] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 18, dithering: 1 +Aug 31 22:50:24 minifree kernel: [ 1.423576] [drm:intel_dump_pipe_config], [CRTC:4][modeset] config for pipe B +Aug 31 22:50:24 minifree kernel: [ 1.423577] [drm:intel_dump_pipe_config], cpu_transcoder: B +Aug 31 22:50:24 minifree kernel: [ 1.423579] [drm:intel_dump_pipe_config], pipe bpp: 18, dithering: 1 +Aug 31 22:50:24 minifree kernel: [ 1.423582] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:50:24 minifree kernel: [ 1.423584] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:50:24 minifree kernel: [ 1.423586] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:50:24 minifree kernel: [ 1.423589] [drm:drm_mode_debug_printmodeline], Modeline 0:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +Aug 31 22:50:24 minifree kernel: [ 1.423591] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:50:24 minifree kernel: [ 1.423595] [drm:drm_mode_debug_printmodeline], Modeline 0:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +Aug 31 22:50:24 minifree kernel: [ 1.423598] [drm:intel_dump_crtc_timings], crtc timings: 54160 1024 1048 1184 1344 768 771 777 806, type: 0x48 flags: 0xa +Aug 31 22:50:24 minifree kernel: [ 1.423600] [drm:intel_dump_pipe_config], port clock: 54160 +Aug 31 22:50:24 minifree kernel: [ 1.423602] [drm:intel_dump_pipe_config], pipe src size: 1024x768 +Aug 31 22:50:24 minifree kernel: [ 1.423604] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000008, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:50:24 minifree kernel: [ 1.423607] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:50:24 minifree kernel: [ 1.423608] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:50:24 minifree kernel: [ 1.423610] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:50:24 minifree kernel: [ 1.423613] [drm:intel_panel_actually_set_backlight], set backlight PWM = 0 +Aug 31 22:50:24 minifree kernel: [ 1.457065] [drm:i9xx_pfit_disable], disabling pfit, current: 0x80000220 +Aug 31 22:50:24 minifree kernel: [ 1.457069] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:50:24 minifree kernel: [ 1.457071] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:50:24 minifree kernel: [ 1.457073] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 29 +Aug 31 22:50:24 minifree kernel: [ 1.457076] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 29, C: 2, SR 1 +Aug 31 22:50:24 minifree kernel: [ 1.457077] [drm:i9xx_update_wm], memory self refresh disabled +Aug 31 22:50:24 minifree kernel: [ 1.457082] [drm:i9xx_get_refclk], using SSC reference clock of 100 MHz +Aug 31 22:50:24 minifree kernel: [ 1.457252] [drm:i9xx_update_plane], Writing base 00020000 00000000 0 0 4096 +Aug 31 22:50:24 minifree kernel: [ 1.457256] [drm:intel_crtc_mode_set], [ENCODER:6:LVDS-6] set [MODE:0:1024x768] +Aug 31 22:50:24 minifree kernel: [ 1.457893] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:50:24 minifree kernel: [ 1.457895] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:50:24 minifree kernel: [ 1.457896] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:50:24 minifree kernel: [ 1.457898] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:50:24 minifree kernel: [ 1.457900] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +Aug 31 22:50:24 minifree kernel: [ 1.457902] [drm:i9xx_update_wm], self-refresh entries: 64 +Aug 31 22:50:24 minifree kernel: [ 1.457905] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +Aug 31 22:50:24 minifree kernel: [ 1.457906] [drm:i9xx_update_wm], memory self refresh enabled +Aug 31 22:50:24 minifree kernel: [ 1.650555] psmouse serio1: alps: Unknown ALPS touchpad: E7=10 00 64, EC=10 00 64 +Aug 31 22:50:24 minifree kernel: [ 1.748270] firewire_core 0000:05:00.1: created device fw0: GUID 0000000000000000, S400 +Aug 31 22:50:24 minifree kernel: [ 1.800110] [drm:intel_panel_enable_backlight], pipe B +Aug 31 22:50:24 minifree kernel: [ 1.800114] [drm:intel_panel_actually_set_backlight], set backlight PWM = 24832 +Aug 31 22:50:24 minifree kernel: [ 1.800120] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 1.800125] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:50:24 minifree kernel: [ 1.800129] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:50:24 minifree kernel: [ 1.800133] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 1.800136] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:50:24 minifree kernel: [ 1.800139] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 1.800178] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +Aug 31 22:50:24 minifree kernel: [ 1.800182] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +Aug 31 22:50:24 minifree kernel: [ 1.800186] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 1.803473] Console: switching to colour frame buffer device 128x48 +Aug 31 22:50:24 minifree kernel: [ 1.803478] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +Aug 31 22:50:24 minifree kernel: [ 1.803481] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +Aug 31 22:50:24 minifree kernel: [ 1.803483] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 1.806832] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device +Aug 31 22:50:24 minifree kernel: [ 1.806835] i915 0000:00:02.0: registered panic notifier +Aug 31 22:50:24 minifree kernel: [ 1.806859] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0 +Aug 31 22:50:24 minifree kernel: [ 1.806909] ahci 0000:00:1f.2: version 3.0 +Aug 31 22:50:24 minifree kernel: [ 1.807136] ahci 0000:00:1f.2: irq 45 for MSI/MSI-X +Aug 31 22:50:24 minifree kernel: [ 1.807190] ahci 0000:00:1f.2: SSS flag set, parallel bus scan disabled +Aug 31 22:50:24 minifree kernel: [ 1.807222] ahci 0000:00:1f.2: AHCI 0001.0100 32 slots 4 ports 1.5 Gbps 0x1 impl SATA mode +Aug 31 22:50:24 minifree kernel: [ 1.807228] ahci 0000:00:1f.2: flags: 64bit ncq ilck stag pm led clo pmp pio slum part +Aug 31 22:50:24 minifree kernel: [ 1.808040] scsi2 : ahci +Aug 31 22:50:24 minifree kernel: [ 1.808204] scsi3 : ahci +Aug 31 22:50:24 minifree kernel: [ 1.808350] scsi4 : ahci +Aug 31 22:50:24 minifree kernel: [ 1.808499] scsi5 : ahci +Aug 31 22:50:24 minifree kernel: [ 1.808567] ata3: SATA max UDMA/133 abar m1024@0xe4344400 port 0xe4344500 irq 45 +Aug 31 22:50:24 minifree kernel: [ 1.808570] ata4: DUMMY +Aug 31 22:50:24 minifree kernel: [ 1.808572] ata5: DUMMY +Aug 31 22:50:24 minifree kernel: [ 1.808574] ata6: DUMMY +Aug 31 22:50:24 minifree kernel: [ 2.014396] psmouse serio1: trackpoint: IBM TrackPoint firmware: 0x0e, buttons: 3/3 +Aug 31 22:50:24 minifree kernel: [ 2.033367] input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/input/input6 +Aug 31 22:50:24 minifree kernel: [ 2.304119] ata3: SATA link up 1.5 Gbps (SStatus 113 SControl 300) +Aug 31 22:50:24 minifree kernel: [ 2.305312] ata3.00: ATA-8: HITACHI HTS722010K9SA00, DC2ZC75A, max UDMA/133 +Aug 31 22:50:24 minifree kernel: [ 2.305317] ata3.00: 195371568 sectors, multi 0: LBA48 NCQ (depth 31/32), AA +Aug 31 22:50:24 minifree kernel: [ 2.306684] ata3.00: configured for UDMA/133 +Aug 31 22:50:24 minifree kernel: [ 2.306893] scsi 2:0:0:0: Direct-Access ATA HITACHI HTS72201 DC2Z PQ: 0 ANSI: 5 +Aug 31 22:50:24 minifree kernel: [ 2.307119] sd 2:0:0:0: Attached scsi generic sg0 type 0 +Aug 31 22:50:24 minifree kernel: [ 2.307251] sd 2:0:0:0: [sda] 195371568 512-byte logical blocks: (100 GB/93.1 GiB) +Aug 31 22:50:24 minifree kernel: [ 2.307395] sd 2:0:0:0: [sda] Write Protect is off +Aug 31 22:50:24 minifree kernel: [ 2.307400] sd 2:0:0:0: [sda] Mode Sense: 00 3a 00 00 +Aug 31 22:50:24 minifree kernel: [ 2.307477] sd 2:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA +Aug 31 22:50:24 minifree kernel: [ 2.632829] sda: sda1 +Aug 31 22:50:24 minifree kernel: [ 2.633271] sd 2:0:0:0: [sda] Attached SCSI disk +Aug 31 22:50:24 minifree kernel: [ 2.784099] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +Aug 31 22:50:24 minifree kernel: [ 2.784104] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +Aug 31 22:50:24 minifree kernel: [ 2.784107] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 2.908607] [drm:i915_gem_open], +Aug 31 22:50:24 minifree kernel: [ 2.908634] [drm:intel_crtc_cursor_set], cursor off +Aug 31 22:50:24 minifree kernel: [ 2.908638] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] +Aug 31 22:50:24 minifree kernel: [ 2.908643] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0 +Aug 31 22:50:24 minifree kernel: [ 2.908648] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 2.908652] [drm:intel_crtc_cursor_set], cursor off +Aug 31 22:50:24 minifree kernel: [ 2.908655] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +Aug 31 22:50:24 minifree kernel: [ 2.908660] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +Aug 31 22:50:24 minifree kernel: [ 2.908663] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 2.908682] [drm:i915_gem_open], +Aug 31 22:50:24 minifree kernel: [ 2.908697] [drm:intel_crtc_cursor_set], cursor off +Aug 31 22:50:24 minifree kernel: [ 2.908700] [drm:intel_crtc_set_config], [CRTC:3] [NOFB] +Aug 31 22:50:24 minifree kernel: [ 2.908703] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0 +Aug 31 22:50:24 minifree kernel: [ 2.908706] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 2.908709] [drm:intel_crtc_cursor_set], cursor off +Aug 31 22:50:24 minifree kernel: [ 2.908712] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +Aug 31 22:50:24 minifree kernel: [ 2.908716] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +Aug 31 22:50:24 minifree kernel: [ 2.908719] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 2.908735] [drm:i915_gem_open], +Aug 31 22:50:24 minifree kernel: [ 2.908824] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +Aug 31 22:50:24 minifree kernel: [ 2.908830] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +Aug 31 22:50:24 minifree kernel: [ 2.908841] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:50:24 minifree kernel: [ 2.908846] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 2.908850] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 2.908871] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +Aug 31 22:50:24 minifree kernel: [ 2.908874] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +Aug 31 22:50:24 minifree kernel: [ 2.908880] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:50:24 minifree kernel: [ 2.908885] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:50:24 minifree kernel: [ 2.908889] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +Aug 31 22:50:24 minifree kernel: [ 2.908894] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +Aug 31 22:50:24 minifree kernel: [ 2.908901] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:50:24 minifree kernel: [ 2.912519] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +Aug 31 22:50:24 minifree kernel: [ 2.912529] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +Aug 31 22:50:24 minifree kernel: [ 2.912533] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +Aug 31 22:50:24 minifree kernel: [ 2.928108] [drm:intel_crt_detect], CRT not detected via hotplug +Aug 31 22:50:24 minifree kernel: [ 2.932103] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +Aug 31 22:50:24 minifree kernel: [ 2.932110] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:50:24 minifree kernel: [ 2.932115] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +Aug 31 22:50:24 minifree kernel: [ 2.932118] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +Aug 31 22:50:24 minifree kernel: [ 2.932404] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:50:24 minifree kernel: [ 2.932407] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +Aug 31 22:50:24 minifree kernel: [ 2.932410] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +Aug 31 22:50:24 minifree kernel: [ 2.932413] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +Aug 31 22:50:24 minifree kernel: [ 2.932424] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +Aug 31 22:50:24 minifree kernel: [ 2.932427] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +Aug 31 22:50:24 minifree kernel: [ 2.932430] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +Aug 31 22:50:24 minifree kernel: [ 2.948104] [drm:intel_crt_detect], CRT not detected via hotplug +Aug 31 22:50:24 minifree kernel: [ 2.952104] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +Aug 31 22:50:24 minifree kernel: [ 2.952111] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:50:24 minifree kernel: [ 2.952115] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +Aug 31 22:50:24 minifree kernel: [ 2.952118] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +Aug 31 22:50:24 minifree kernel: [ 2.952401] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:50:24 minifree kernel: [ 2.952403] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +Aug 31 22:50:24 minifree kernel: [ 2.952406] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +Aug 31 22:50:24 minifree kernel: [ 2.952409] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +Aug 31 22:50:24 minifree kernel: [ 2.952420] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +Aug 31 22:50:24 minifree kernel: [ 2.952423] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:50:24 minifree kernel: [ 2.952427] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +Aug 31 22:50:24 minifree kernel: [ 2.952431] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 2.952436] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +Aug 31 22:50:24 minifree kernel: [ 2.952459] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +Aug 31 22:50:24 minifree kernel: [ 2.952466] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +Aug 31 22:50:24 minifree kernel: [ 2.952471] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +Aug 31 22:50:24 minifree kernel: [ 2.952474] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +Aug 31 22:50:24 minifree kernel: [ 2.952477] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +Aug 31 22:50:24 minifree kernel: [ 2.952480] [drm:intel_dump_pipe_config], cpu_transcoder: A +Aug 31 22:50:24 minifree kernel: [ 2.952483] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +Aug 31 22:50:24 minifree kernel: [ 2.952486] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:50:24 minifree kernel: [ 2.952489] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:50:24 minifree kernel: [ 2.952493] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:50:24 minifree kernel: [ 2.952495] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:50:24 minifree kernel: [ 2.952500] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:50:24 minifree kernel: [ 2.952503] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:50:24 minifree kernel: [ 2.952508] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +Aug 31 22:50:24 minifree kernel: [ 2.952512] [drm:intel_dump_pipe_config], port clock: 108000 +Aug 31 22:50:24 minifree kernel: [ 2.952514] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +Aug 31 22:50:24 minifree kernel: [ 2.952517] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:50:24 minifree kernel: [ 2.952521] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:50:24 minifree kernel: [ 2.952524] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:50:24 minifree kernel: [ 2.952527] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:50:24 minifree kernel: [ 2.959612] [drm:i9xx_update_plane], Writing base 00320000 00000000 0 0 5120 +Aug 31 22:50:24 minifree kernel: [ 2.959624] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +Aug 31 22:50:24 minifree kernel: [ 2.965254] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:50:24 minifree kernel: [ 2.965259] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:50:24 minifree kernel: [ 2.965261] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:50:24 minifree kernel: [ 2.965264] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:50:24 minifree kernel: [ 2.965267] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +Aug 31 22:50:24 minifree kernel: [ 2.965270] [drm:intel_calculate_wm], FIFO watermark level: -5 +Aug 31 22:50:24 minifree kernel: [ 2.965272] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +Aug 31 22:50:24 minifree kernel: [ 2.965276] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +Aug 31 22:50:24 minifree kernel: [ 2.965279] [drm:i9xx_update_wm], memory self refresh disabled +Aug 31 22:50:24 minifree kernel: [ 2.988110] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 2.988118] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:50:24 minifree kernel: [ 2.988123] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:50:24 minifree kernel: [ 2.988128] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:50:24 minifree kernel: [ 2.988133] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 2.988138] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:50:24 minifree kernel: [ 2.988151] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 3.028106] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +Aug 31 22:50:24 minifree kernel: [ 3.028114] [drm:intel_tv_detect_type], Unrecognised TV connection +Aug 31 22:50:24 minifree kernel: [ 3.044104] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 3.044113] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +Aug 31 22:50:24 minifree kernel: [ 3.089061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:50:24 minifree kernel: [ 3.089065] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:50:24 minifree kernel: [ 3.089067] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:50:24 minifree kernel: [ 3.089070] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:50:24 minifree kernel: [ 3.089074] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +Aug 31 22:50:24 minifree kernel: [ 3.089077] [drm:i9xx_update_wm], self-refresh entries: 64 +Aug 31 22:50:24 minifree kernel: [ 3.089079] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +Aug 31 22:50:24 minifree kernel: [ 3.089083] [drm:i9xx_update_wm], memory self refresh enabled +Aug 31 22:50:24 minifree kernel: [ 3.089089] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 3.089094] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:50:24 minifree kernel: [ 3.089097] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:50:24 minifree kernel: [ 3.089100] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 3.089103] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:50:24 minifree kernel: [ 3.089106] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 3.089258] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +Aug 31 22:50:24 minifree kernel: [ 3.090319] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +Aug 31 22:50:24 minifree kernel: [ 3.090324] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:50:24 minifree kernel: [ 3.090327] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +Aug 31 22:50:24 minifree kernel: [ 3.090331] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 3.090335] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +Aug 31 22:50:24 minifree kernel: [ 3.090351] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +Aug 31 22:50:24 minifree kernel: [ 3.090356] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +Aug 31 22:50:24 minifree kernel: [ 3.090359] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +Aug 31 22:50:24 minifree kernel: [ 3.090362] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +Aug 31 22:50:24 minifree kernel: [ 3.090365] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +Aug 31 22:50:24 minifree kernel: [ 3.090369] [drm:intel_dump_pipe_config], cpu_transcoder: A +Aug 31 22:50:24 minifree kernel: [ 3.090371] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +Aug 31 22:50:24 minifree kernel: [ 3.090374] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:50:24 minifree kernel: [ 3.090378] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:50:24 minifree kernel: [ 3.090381] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:50:24 minifree kernel: [ 3.090384] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:50:24 minifree kernel: [ 3.090389] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:50:24 minifree kernel: [ 3.090391] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:50:24 minifree kernel: [ 3.090396] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +Aug 31 22:50:24 minifree kernel: [ 3.090400] [drm:intel_dump_pipe_config], port clock: 108000 +Aug 31 22:50:24 minifree kernel: [ 3.090403] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +Aug 31 22:50:24 minifree kernel: [ 3.090406] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:50:24 minifree kernel: [ 3.090409] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:50:24 minifree kernel: [ 3.090412] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:50:24 minifree kernel: [ 3.090415] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:50:24 minifree kernel: [ 3.096851] [drm:i9xx_update_plane], Writing base 00320000 00000000 0 0 5120 +Aug 31 22:50:24 minifree kernel: [ 3.096864] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +Aug 31 22:50:24 minifree kernel: [ 3.102491] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:50:24 minifree kernel: [ 3.102495] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:50:24 minifree kernel: [ 3.102498] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:50:24 minifree kernel: [ 3.102501] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:50:24 minifree kernel: [ 3.102504] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +Aug 31 22:50:24 minifree kernel: [ 3.102506] [drm:intel_calculate_wm], FIFO watermark level: -5 +Aug 31 22:50:24 minifree kernel: [ 3.102509] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +Aug 31 22:50:24 minifree kernel: [ 3.102512] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +Aug 31 22:50:24 minifree kernel: [ 3.102515] [drm:i9xx_update_wm], memory self refresh disabled +Aug 31 22:50:24 minifree kernel: [ 3.124103] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 3.124110] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:50:24 minifree kernel: [ 3.124116] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:50:24 minifree kernel: [ 3.124121] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:50:24 minifree kernel: [ 3.124126] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 3.124131] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:50:24 minifree kernel: [ 3.124143] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 3.164099] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +Aug 31 22:50:24 minifree kernel: [ 3.164104] [drm:intel_tv_detect_type], Unrecognised TV connection +Aug 31 22:50:24 minifree kernel: [ 3.188098] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 3.188105] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +Aug 31 22:50:24 minifree kernel: [ 3.229059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:50:24 minifree kernel: [ 3.229063] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:50:24 minifree kernel: [ 3.229065] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:50:24 minifree kernel: [ 3.229068] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:50:24 minifree kernel: [ 3.229071] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +Aug 31 22:50:24 minifree kernel: [ 3.229075] [drm:i9xx_update_wm], self-refresh entries: 64 +Aug 31 22:50:24 minifree kernel: [ 3.229077] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +Aug 31 22:50:24 minifree kernel: [ 3.229081] [drm:i9xx_update_wm], memory self refresh enabled +Aug 31 22:50:24 minifree kernel: [ 3.229086] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 3.229091] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:50:24 minifree kernel: [ 3.229094] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:50:24 minifree kernel: [ 3.229097] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:50:24 minifree kernel: [ 3.229100] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:50:24 minifree kernel: [ 3.229103] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 3.229256] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +Aug 31 22:50:24 minifree kernel: [ 3.230324] [drm:drm_mode_addfb], [FB:34] +Aug 31 22:50:24 minifree kernel: [ 3.603108] [drm:drm_mode_addfb], [FB:34] +Aug 31 22:50:24 minifree kernel: [ 3.603201] [drm:intel_crtc_set_config], [CRTC:4] [FB:33] #connectors=1 (x y) (0 0) +Aug 31 22:50:24 minifree kernel: [ 3.603207] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +Aug 31 22:50:24 minifree kernel: [ 3.603211] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 3.606628] [drm:drm_mode_setcrtc], [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 3.606636] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 3.606640] [drm:intel_crtc_set_config], [CRTC:4] [FB:34] #connectors=1 (x y) (0 0) +Aug 31 22:50:24 minifree kernel: [ 3.606645] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=1 +Aug 31 22:50:24 minifree kernel: [ 3.606648] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 3.610935] [drm:i9xx_update_plane], Writing base 00320000 00000000 0 0 4096 +Aug 31 22:50:24 minifree kernel: [ 3.627861] md: linear personality registered for level -1 +Aug 31 22:50:24 minifree kernel: [ 3.628773] [drm:drm_mode_setcrtc], [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 3.628782] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1] +Aug 31 22:50:24 minifree kernel: [ 3.628787] [drm:intel_crtc_set_config], [CRTC:4] [FB:34] #connectors=1 (x y) (0 0) +Aug 31 22:50:24 minifree kernel: [ 3.628793] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=0 +Aug 31 22:50:24 minifree kernel: [ 3.628797] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +Aug 31 22:50:24 minifree kernel: [ 3.633141] md: multipath personality registered for level -4 +Aug 31 22:50:24 minifree kernel: [ 3.638092] md: raid0 personality registered for level 0 +Aug 31 22:50:24 minifree kernel: [ 3.643718] md: raid1 personality registered for level 1 +Aug 31 22:50:24 minifree kernel: [ 3.716024] raid6: sse2x1 2266 MB/s +Aug 31 22:50:24 minifree kernel: [ 3.784028] raid6: sse2x2 4053 MB/s +Aug 31 22:50:24 minifree kernel: [ 3.852032] raid6: sse2x4 4547 MB/s +Aug 31 22:50:24 minifree kernel: [ 3.852036] raid6: using algorithm sse2x4 (4547 MB/s) +Aug 31 22:50:24 minifree kernel: [ 3.852038] raid6: using ssse3x2 recovery algorithm +Aug 31 22:50:24 minifree kernel: [ 3.854266] xor: measuring software checksum speed +Aug 31 22:50:24 minifree kernel: [ 3.892019] prefetch64-sse: 6047.000 MB/sec +Aug 31 22:50:24 minifree kernel: [ 3.932018] generic_sse: 5363.000 MB/sec +Aug 31 22:50:24 minifree kernel: [ 3.932021] xor: using function: prefetch64-sse (6047.000 MB/sec) +Aug 31 22:50:24 minifree kernel: [ 3.934078] async_tx: api initialized (async) +Aug 31 22:50:24 minifree kernel: [ 3.946437] md: raid6 personality registered for level 6 +Aug 31 22:50:24 minifree kernel: [ 3.946441] md: raid5 personality registered for level 5 +Aug 31 22:50:24 minifree kernel: [ 3.946444] md: raid4 personality registered for level 4 +Aug 31 22:50:24 minifree kernel: [ 3.957827] md: raid10 personality registered for level 10 +Aug 31 22:50:24 minifree kernel: [ 9.243505] random: cryptsetup urandom read with 119 bits of entropy available +Aug 31 22:50:24 minifree kernel: [ 9.246108] random: nonblocking pool is initialized +Aug 31 22:50:24 minifree kernel: [ 9.266100] bio: create slab at 1 +Aug 31 22:50:24 minifree kernel: [ 9.513079] bio: create slab at 1 +Aug 31 22:50:24 minifree kernel: [ 10.331147] bio: create slab at 2 +Aug 31 22:50:24 minifree kernel: [ 10.332723] Btrfs loaded +Aug 31 22:50:24 minifree kernel: [ 11.808132] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:50:24 minifree kernel: [ 15.403838] EXT4-fs (dm-1): INFO: recovery required on readonly filesystem +Aug 31 22:50:24 minifree kernel: [ 15.403844] EXT4-fs (dm-1): write access will be enabled during recovery +Aug 31 22:50:24 minifree kernel: [ 17.127673] EXT4-fs (dm-1): orphan cleanup on readonly fs +Aug 31 22:50:24 minifree kernel: [ 17.127796] EXT4-fs (dm-1): 1 orphan inode deleted +Aug 31 22:50:24 minifree kernel: [ 17.127800] EXT4-fs (dm-1): recovery complete +Aug 31 22:50:24 minifree kernel: [ 17.216730] EXT4-fs (dm-1): mounted filesystem with ordered data mode. Opts: (null) +Aug 31 22:50:24 minifree kernel: [ 21.824056] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:50:24 minifree kernel: [ 28.044685] EXT4-fs (dm-1): re-mounted. Opts: errors=remount-ro +Aug 31 22:50:24 minifree kernel: [ 29.253227] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +Aug 31 22:50:24 minifree kernel: [ 29.727869] lp: driver loaded but no devices found +Aug 31 22:50:24 minifree kernel: [ 29.764157] ppdev: user-space parallel port driver +Aug 31 22:50:24 minifree kernel: [ 30.065222] type=1400 audit(1409521824.544:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/cups/backend/cups-pdf" pid=647 comm="apparmor_parser" +Aug 31 22:50:24 minifree kernel: [ 30.065234] type=1400 audit(1409521824.544:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/cupsd" pid=647 comm="apparmor_parser" +Aug 31 22:50:24 minifree kernel: [ 30.065934] type=1400 audit(1409521824.544:4): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/sbin/cupsd" pid=647 comm="apparmor_parser" +Aug 31 22:50:24 minifree kernel: [ 30.182531] Bluetooth: Core ver 2.17 +Aug 31 22:50:24 minifree kernel: [ 30.184399] NET: Registered protocol family 31 +Aug 31 22:50:24 minifree kernel: [ 30.184403] Bluetooth: HCI device and connection manager initialized +Aug 31 22:50:24 minifree kernel: [ 30.184417] Bluetooth: HCI socket layer initialized +Aug 31 22:50:24 minifree kernel: [ 30.184422] Bluetooth: L2CAP socket layer initialized +Aug 31 22:50:24 minifree kernel: [ 30.184430] Bluetooth: SCO socket layer initialized +Aug 31 22:50:24 minifree kernel: [ 30.216147] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 +Aug 31 22:50:24 minifree kernel: [ 30.216153] Bluetooth: BNEP filters: protocol multicast +Aug 31 22:50:24 minifree kernel: [ 30.216167] Bluetooth: BNEP socket layer initialized +Aug 31 22:50:24 minifree kernel: [ 30.217692] Bluetooth: RFCOMM TTY layer initialized +Aug 31 22:50:24 minifree kernel: [ 30.217701] Bluetooth: RFCOMM socket layer initialized +Aug 31 22:50:24 minifree kernel: [ 30.217712] Bluetooth: RFCOMM ver 1.11 +Aug 31 22:50:24 minifree kernel: [ 30.227989] intel_rng: FWH not detected +Aug 31 22:50:24 minifree kernel: [ 30.348498] ACPI Warning: 0x0000000000000528-0x000000000000052f SystemIO conflicts with Region \PMIO 1 (20131115/utaddress-251) +Aug 31 22:50:24 minifree kernel: [ 30.348510] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +Aug 31 22:50:24 minifree kernel: [ 30.348517] ACPI Warning: 0x00000000000004b0-0x00000000000004bf SystemIO conflicts with Region \GPIO 1 (20131115/utaddress-251) +Aug 31 22:50:24 minifree kernel: [ 30.348522] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +Aug 31 22:50:24 minifree kernel: [ 30.348525] ACPI Warning: 0x0000000000000480-0x00000000000004af SystemIO conflicts with Region \GPIO 1 (20131115/utaddress-251) +Aug 31 22:50:24 minifree kernel: [ 30.348530] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +Aug 31 22:50:24 minifree kernel: [ 30.348533] lpc_ich: Resource conflict(s) found affecting gpio_ich +Aug 31 22:50:24 minifree kernel: [ 30.372503] leds_ss4200: no LED devices found +Aug 31 22:50:24 minifree kernel: [ 30.372824] yenta_cardbus 0000:05:00.0: CardBus bridge found [0000:0000] +Aug 31 22:50:24 minifree kernel: [ 30.493456] type=1400 audit(1409521824.972:5): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/sbin/dhclient" pid=696 comm="apparmor_parser" +Aug 31 22:50:24 minifree kernel: [ 30.493470] type=1400 audit(1409521824.972:6): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=696 comm="apparmor_parser" +Aug 31 22:50:24 minifree kernel: [ 30.493478] type=1400 audit(1409521824.972:7): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=696 comm="apparmor_parser" +Aug 31 22:50:24 minifree kernel: [ 30.496483] type=1400 audit(1409521824.976:8): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=696 comm="apparmor_parser" +Aug 31 22:50:24 minifree kernel: [ 30.496497] type=1400 audit(1409521824.976:9): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=696 comm="apparmor_parser" +Aug 31 22:50:24 minifree kernel: [ 30.496998] type=1400 audit(1409521824.976:10): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=696 comm="apparmor_parser" +Aug 31 22:50:24 minifree kernel: [ 30.501113] yenta_cardbus 0000:05:00.0: ISA IRQ mask 0x0cb8, PCI irq 16 +Aug 31 22:50:24 minifree kernel: [ 30.501120] yenta_cardbus 0000:05:00.0: Socket status: 30000006 +Aug 31 22:50:24 minifree kernel: [ 30.501126] pci_bus 0000:05: Raising subordinate bus# of parent bus (#05) from #06 to #09 +Aug 31 22:50:24 minifree kernel: [ 30.501295] yenta_cardbus 0000:05:00.0: pcmcia: parent PCI bridge window: [io 0x2000-0x3fff] +Aug 31 22:50:24 minifree kernel: [ 30.501300] yenta_cardbus 0000:05:00.0: pcmcia: parent PCI bridge window: [mem 0xe0000000-0xe20fffff] +Aug 31 22:50:24 minifree kernel: [ 30.501305] pcmcia_socket pcmcia_socket0: cs: memory probe 0xe0000000-0xe20fffff: +Aug 31 22:50:24 minifree kernel: [ 30.501318] excluding 0xe1ef0000-0xe20fffff +Aug 31 22:50:24 minifree kernel: [ 30.501325] yenta_cardbus 0000:05:00.0: pcmcia: parent PCI bridge window: [mem 0xe2100000-0xe40fffff 64bit pref] +Aug 31 22:50:24 minifree kernel: [ 30.501329] pcmcia_socket pcmcia_socket0: cs: memory probe 0xe2100000-0xe40fffff: +Aug 31 22:50:24 minifree kernel: [ 30.501411] excluding 0xe2100000-0xe40fffff +Aug 31 22:50:25 minifree kernel: [ 30.761785] e1000e 0000:01:00.0: irq 44 for MSI/MSI-X +Aug 31 22:50:25 minifree kernel: [ 30.772718] device-mapper: multipath: version 1.6.0 loaded +Aug 31 22:50:25 minifree kernel: [ 30.841196] Non-volatile memory driver v1.3 +Aug 31 22:50:25 minifree kernel: [ 30.846354] thinkpad_acpi: ThinkPad ACPI Extras v0.25 +Aug 31 22:50:25 minifree kernel: [ 30.846360] thinkpad_acpi: http://ibm-acpi.sf.net/ +Aug 31 22:50:25 minifree kernel: [ 30.846363] thinkpad_acpi: ThinkPad BIOS CBET4000 7BETC7WW (2.08 ), EC 7BHT37WW-3.4 +Aug 31 22:50:25 minifree kernel: [ 30.846365] thinkpad_acpi: Lenovo ThinkPad X60s, model 1702L8G +Aug 31 22:50:25 minifree kernel: [ 30.853545] thinkpad_acpi: detected a 8-level brightness capable ThinkPad +Aug 31 22:50:25 minifree kernel: [ 30.853591] thinkpad_acpi: This ThinkPad has standard ACPI backlight brightness control, supported by the ACPI video driver +Aug 31 22:50:25 minifree kernel: [ 30.853594] thinkpad_acpi: Disabling thinkpad-acpi brightness events by default... +Aug 31 22:50:25 minifree kernel: [ 30.864133] e1000e 0000:01:00.0: irq 44 for MSI/MSI-X +Aug 31 22:50:25 minifree kernel: [ 30.864654] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +Aug 31 22:50:25 minifree kernel: [ 30.904471] thinkpad_acpi: Standard ACPI backlight interface available, not loading native one +Aug 31 22:50:25 minifree kernel: [ 30.904716] thinkpad_acpi: Console audio control enabled, mode: monitor (read only) +Aug 31 22:50:25 minifree kernel: [ 30.917451] input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input7 +Aug 31 22:50:25 minifree kernel: [ 31.070696] hda_intel: probe_mask set to 0x1 for device 17aa:2010 +Aug 31 22:50:25 minifree kernel: [ 31.070755] snd_hda_intel 0000:00:1b.0: irq 46 for MSI/MSI-X +Aug 31 22:50:25 minifree kernel: [ 31.221006] autoconfig: line_outs=1 (0x5/0x0/0x0/0x0/0x0) type:line +Aug 31 22:50:25 minifree kernel: [ 31.221013] speaker_outs=1 (0x7/0x0/0x0/0x0/0x0) +Aug 31 22:50:25 minifree kernel: [ 31.221016] hp_outs=1 (0x6/0x0/0x0/0x0/0x0) +Aug 31 22:50:25 minifree kernel: [ 31.221018] mono: mono_out=0x0 +Aug 31 22:50:25 minifree kernel: [ 31.221020] dig-out=0xa/0x0 +Aug 31 22:50:25 minifree kernel: [ 31.221022] inputs: +Aug 31 22:50:25 minifree kernel: [ 31.221073] Rear Mic=0x18 +Aug 31 22:50:25 minifree kernel: [ 31.221076] Front Mic=0x8 +Aug 31 22:50:25 minifree kernel: [ 31.221079] Line=0x9 +Aug 31 22:50:25 minifree kernel: [ 31.221081] CD=0x19 +Aug 31 22:50:25 minifree kernel: [ 31.221084] Aux=0x17 +Aug 31 22:50:25 minifree kernel: [ 31.306204] input: HDA Intel Front Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input12 +Aug 31 22:50:25 minifree kernel: [ 31.309615] input: HDA Intel Line Out as /devices/pci0000:00/0000:00:1b.0/sound/card0/input11 +Aug 31 22:50:25 minifree kernel: [ 31.312192] input: HDA Intel Line as /devices/pci0000:00/0000:00:1b.0/sound/card0/input10 +Aug 31 22:50:25 minifree kernel: [ 31.316499] input: HDA Intel Front Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9 +Aug 31 22:50:25 minifree kernel: [ 31.316647] input: HDA Intel Rear Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input8 +Aug 31 22:50:25 minifree kernel: [ 31.491549] pcmcia_socket pcmcia_socket0: cs: memory probe 0x0c0000-0x0fffff: +Aug 31 22:50:25 minifree kernel: [ 31.491580] excluding 0xf0000-0xfffff +Aug 31 22:50:25 minifree kernel: [ 31.491611] pcmcia_socket pcmcia_socket0: cs: memory probe 0xa0000000-0xa0ffffff: +Aug 31 22:50:25 minifree kernel: [ 31.491646] clean. +Aug 31 22:50:25 minifree kernel: [ 31.491672] pcmcia_socket pcmcia_socket0: cs: memory probe 0x60000000-0x60ffffff: +Aug 31 22:50:25 minifree kernel: [ 31.491705] excluding 0x60000000-0x60ffffff +Aug 31 22:50:26 minifree kernel: [ 31.840110] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:50:36 minifree kernel: [ 41.856122] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:50:46 minifree kernel: [ 51.872113] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:50:54 minifree kernel: [ 60.227922] type=1400 audit(1409521854.704:11): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/cups/backend/cups-pdf" pid=1132 comm="apparmor_parser" +Aug 31 22:50:54 minifree kernel: [ 60.227937] type=1400 audit(1409521854.704:12): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/sbin/cupsd" pid=1132 comm="apparmor_parser" +Aug 31 22:50:54 minifree kernel: [ 60.228674] type=1400 audit(1409521854.708:13): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/sbin/cupsd" pid=1132 comm="apparmor_parser" +Aug 31 22:50:55 minifree kernel: [ 60.787283] type=1400 audit(1409521855.264:14): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/cups-browsed" pid=1143 comm="apparmor_parser" +Aug 31 22:50:56 minifree kernel: [ 61.888127] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:51:04 minifree kernel: [ 70.140147] usb 1-1: new high-speed USB device number 2 using ehci-pci +Aug 31 22:51:04 minifree kernel: [ 70.289002] usb 1-1: New USB device found, idVendor=0cf3, idProduct=9271 +Aug 31 22:51:04 minifree kernel: [ 70.289008] usb 1-1: New USB device strings: Mfr=16, Product=32, SerialNumber=48 +Aug 31 22:51:04 minifree kernel: [ 70.289012] usb 1-1: Product: UB93 +Aug 31 22:51:04 minifree kernel: [ 70.289015] usb 1-1: Manufacturer: ATHEROS +Aug 31 22:51:04 minifree kernel: [ 70.289019] usb 1-1: SerialNumber: 12345 +Aug 31 22:51:04 minifree kernel: [ 70.441093] cfg80211: Calling CRDA to update world regulatory domain +Aug 31 22:51:05 minifree kernel: [ 70.579584] cfg80211: World regulatory domain updated: +Aug 31 22:51:05 minifree kernel: [ 70.579590] cfg80211: (start_freq - end_freq @ bandwidth), (max_antenna_gain, max_eirp) +Aug 31 22:51:05 minifree kernel: [ 70.579594] cfg80211: (2402000 KHz - 2472000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) +Aug 31 22:51:05 minifree kernel: [ 70.579598] cfg80211: (2457000 KHz - 2482000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) +Aug 31 22:51:05 minifree kernel: [ 70.579601] cfg80211: (2474000 KHz - 2494000 KHz @ 20000 KHz), (300 mBi, 2000 mBm) +Aug 31 22:51:05 minifree kernel: [ 70.579604] cfg80211: (5170000 KHz - 5250000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) +Aug 31 22:51:05 minifree kernel: [ 70.579607] cfg80211: (5735000 KHz - 5835000 KHz @ 40000 KHz), (300 mBi, 2000 mBm) +Aug 31 22:51:05 minifree kernel: [ 70.613130] usb 1-1: ath9k_htc: Firmware htc_9271.fw requested +Aug 31 22:51:05 minifree kernel: [ 70.613246] usbcore: registered new interface driver ath9k_htc +Aug 31 22:51:05 minifree kernel: [ 70.909647] usb 1-1: ath9k_htc: Transferred FW: htc_9271.fw, size: 50980 +Aug 31 22:51:05 minifree kernel: [ 71.150263] ath9k_htc 1-1:1.0: ath9k_htc: HTC initialized with 33 credits +Aug 31 22:51:05 minifree kernel: [ 71.418766] ath9k_htc 1-1:1.0: ath9k_htc: FW Version: 1.3 +Aug 31 22:51:05 minifree kernel: [ 71.418770] ath: EEPROM regdomain: 0x65 +Aug 31 22:51:05 minifree kernel: [ 71.418773] ath: EEPROM indicates we should expect a direct regpair map +Aug 31 22:51:05 minifree kernel: [ 71.418777] ath: Country alpha2 being used: 00 +Aug 31 22:51:05 minifree kernel: [ 71.418779] ath: Regpair used: 0x65 +Aug 31 22:51:05 minifree kernel: [ 71.460149] ieee80211 phy0: Atheros AR9271 Rev:1 +Aug 31 22:51:06 minifree kernel: [ 71.904067] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:51:14 minifree kernel: [ 79.945375] usb 1-1: USB disconnect, device number 2 +Aug 31 22:51:14 minifree kernel: [ 80.151202] usb 1-1: ath9k_htc: USB layer deinitialized +Aug 31 22:51:16 minifree kernel: [ 81.920129] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:51:26 minifree kernel: [ 91.936033] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:51:36 minifree kernel: [ 101.952108] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:51:46 minifree kernel: [ 111.968120] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:51:56 minifree kernel: [ 121.984105] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:52:06 minifree kernel: [ 132.000103] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:52:16 minifree kernel: [ 142.016108] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:52:23 minifree kernel: [ 149.297093] e1000e: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx +Aug 31 22:52:23 minifree kernel: [ 149.297248] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready +Aug 31 22:52:25 minifree kernel: [ 151.489247] type=1400 audit(1409521945.968:15): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/sbin/dhclient" pid=1314 comm="apparmor_parser" +Aug 31 22:52:25 minifree kernel: [ 151.489262] type=1400 audit(1409521945.968:16): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=1314 comm="apparmor_parser" +Aug 31 22:52:25 minifree kernel: [ 151.489271] type=1400 audit(1409521945.968:17): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=1314 comm="apparmor_parser" +Aug 31 22:52:25 minifree kernel: [ 151.490046] type=1400 audit(1409521945.968:18): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=1314 comm="apparmor_parser" +Aug 31 22:52:25 minifree kernel: [ 151.490055] type=1400 audit(1409521945.968:19): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=1314 comm="apparmor_parser" +Aug 31 22:52:25 minifree kernel: [ 151.490416] type=1400 audit(1409521945.968:20): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=1314 comm="apparmor_parser" +Aug 31 22:52:25 minifree kernel: [ 151.495908] type=1400 audit(1409521945.972:21): apparmor="STATUS" operation="profile_load" profile="unconfined" name="system_tor" pid=1315 comm="apparmor_parser" +Aug 31 22:52:25 minifree kernel: [ 151.500387] type=1400 audit(1409521945.980:22): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/lightdm/lightdm-guest-session" pid=1313 comm="apparmor_parser" +Aug 31 22:52:25 minifree kernel: [ 151.500398] type=1400 audit(1409521945.980:23): apparmor="STATUS" operation="profile_load" profile="unconfined" name="chromium" pid=1313 comm="apparmor_parser" +Aug 31 22:52:25 minifree kernel: [ 151.500825] type=1400 audit(1409521945.980:24): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="chromium" pid=1313 comm="apparmor_parser" +Aug 31 22:52:26 minifree kernel: [ 152.032044] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:52:27 minifree kernel: [ 153.407166] [drm:i915_gem_open], +Aug 31 22:52:28 minifree kernel: [ 154.128716] [drm:i915_gem_open], +Aug 31 22:52:28 minifree kernel: [ 154.128739] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +Aug 31 22:52:28 minifree kernel: [ 154.129127] [drm:i915_gem_open], +Aug 31 22:52:28 minifree kernel: [ 154.129142] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +Aug 31 22:52:28 minifree kernel: [ 154.129149] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +Aug 31 22:52:28 minifree kernel: [ 154.130884] [drm:drm_mode_addfb], [FB:35] +Aug 31 22:52:28 minifree kernel: [ 154.131523] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +Aug 31 22:52:28 minifree kernel: [ 154.131530] [drm:drm_mode_getresources], CRTC[2] CONNECTORS[3] ENCODERS[3] +Aug 31 22:52:28 minifree kernel: [ 154.131585] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:28 minifree kernel: [ 154.131595] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:28 minifree kernel: [ 154.131939] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +Aug 31 22:52:28 minifree kernel: [ 154.131949] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +Aug 31 22:52:28 minifree kernel: [ 154.131987] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +Aug 31 22:52:28 minifree kernel: [ 154.131996] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +Aug 31 22:52:28 minifree kernel: [ 154.256944] [drm:drm_mode_addfb], [FB:35] +Aug 31 22:52:28 minifree kernel: [ 154.256966] [drm:drm_mode_setcrtc], [CRTC:4] +Aug 31 22:52:28 minifree kernel: [ 154.256976] [drm:drm_mode_setcrtc], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:28 minifree kernel: [ 154.256980] [drm:intel_crtc_set_config], [CRTC:4] [FB:35] #connectors=1 (x y) (0 0) +Aug 31 22:52:28 minifree kernel: [ 154.256986] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:4], mode_changed=0, fb_changed=1 +Aug 31 22:52:28 minifree kernel: [ 154.256991] [drm:intel_modeset_stage_output_state], [CONNECTOR:5:LVDS-1] to [CRTC:4] +Aug 31 22:52:28 minifree kernel: [ 154.258670] [drm:i9xx_update_plane], Writing base 00800000 00000000 0 0 4096 +Aug 31 22:52:32 minifree kernel: [ 158.275793] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:32 minifree kernel: [ 158.275804] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:32 minifree kernel: [ 158.275809] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:32 minifree kernel: [ 158.275832] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +Aug 31 22:52:32 minifree kernel: [ 158.275836] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +Aug 31 22:52:32 minifree kernel: [ 158.275841] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:52:32 minifree kernel: [ 158.275846] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:52:32 minifree kernel: [ 158.275851] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +Aug 31 22:52:32 minifree kernel: [ 158.275856] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +Aug 31 22:52:32 minifree kernel: [ 158.275865] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:32 minifree kernel: [ 158.276430] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +Aug 31 22:52:32 minifree kernel: [ 158.276435] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +Aug 31 22:52:32 minifree kernel: [ 158.276439] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +Aug 31 22:52:32 minifree kernel: [ 158.288160] [drm:intel_crt_detect], CRT not detected via hotplug +Aug 31 22:52:32 minifree kernel: [ 158.292045] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +Aug 31 22:52:32 minifree kernel: [ 158.292055] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:32 minifree kernel: [ 158.292059] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +Aug 31 22:52:32 minifree kernel: [ 158.292062] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +Aug 31 22:52:32 minifree kernel: [ 158.292346] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:32 minifree kernel: [ 158.292349] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +Aug 31 22:52:32 minifree kernel: [ 158.292352] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +Aug 31 22:52:32 minifree kernel: [ 158.292358] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +Aug 31 22:52:32 minifree kernel: [ 158.292396] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +Aug 31 22:52:32 minifree kernel: [ 158.292401] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:52:32 minifree kernel: [ 158.292404] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +Aug 31 22:52:32 minifree kernel: [ 158.292410] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:32 minifree kernel: [ 158.292414] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +Aug 31 22:52:32 minifree kernel: [ 158.292433] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +Aug 31 22:52:32 minifree kernel: [ 158.292439] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +Aug 31 22:52:32 minifree kernel: [ 158.292443] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +Aug 31 22:52:32 minifree kernel: [ 158.292447] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +Aug 31 22:52:32 minifree kernel: [ 158.292450] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +Aug 31 22:52:32 minifree kernel: [ 158.292454] [drm:intel_dump_pipe_config], cpu_transcoder: A +Aug 31 22:52:32 minifree kernel: [ 158.292457] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +Aug 31 22:52:32 minifree kernel: [ 158.292459] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:32 minifree kernel: [ 158.292463] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:32 minifree kernel: [ 158.292467] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:52:32 minifree kernel: [ 158.292469] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:32 minifree kernel: [ 158.292475] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:52:32 minifree kernel: [ 158.292477] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:32 minifree kernel: [ 158.292482] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +Aug 31 22:52:32 minifree kernel: [ 158.292486] [drm:intel_dump_pipe_config], port clock: 108000 +Aug 31 22:52:32 minifree kernel: [ 158.292489] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +Aug 31 22:52:32 minifree kernel: [ 158.292492] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:52:32 minifree kernel: [ 158.292495] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:52:32 minifree kernel: [ 158.292499] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:52:32 minifree kernel: [ 158.292501] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:52:32 minifree kernel: [ 158.300167] [drm:i9xx_update_plane], Writing base 00C00000 00000000 0 0 5120 +Aug 31 22:52:32 minifree kernel: [ 158.300181] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +Aug 31 22:52:32 minifree kernel: [ 158.305816] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:32 minifree kernel: [ 158.305823] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:32 minifree kernel: [ 158.305825] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:32 minifree kernel: [ 158.305828] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:32 minifree kernel: [ 158.305832] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +Aug 31 22:52:32 minifree kernel: [ 158.305834] [drm:intel_calculate_wm], FIFO watermark level: -5 +Aug 31 22:52:32 minifree kernel: [ 158.305837] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +Aug 31 22:52:32 minifree kernel: [ 158.305840] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +Aug 31 22:52:32 minifree kernel: [ 158.305844] [drm:i9xx_update_wm], memory self refresh disabled +Aug 31 22:52:32 minifree kernel: [ 158.324056] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:32 minifree kernel: [ 158.324066] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:52:32 minifree kernel: [ 158.324071] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:32 minifree kernel: [ 158.324074] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:32 minifree kernel: [ 158.324078] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:32 minifree kernel: [ 158.324081] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:32 minifree kernel: [ 158.324093] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:32 minifree kernel: [ 158.376040] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +Aug 31 22:52:32 minifree kernel: [ 158.376049] [drm:intel_tv_detect_type], Unrecognised TV connection +Aug 31 22:52:32 minifree kernel: [ 158.392042] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:32 minifree kernel: [ 158.392052] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +Aug 31 22:52:32 minifree kernel: [ 158.433012] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:32 minifree kernel: [ 158.433022] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:32 minifree kernel: [ 158.433025] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:32 minifree kernel: [ 158.433028] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:32 minifree kernel: [ 158.433031] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +Aug 31 22:52:32 minifree kernel: [ 158.433034] [drm:i9xx_update_wm], self-refresh entries: 64 +Aug 31 22:52:32 minifree kernel: [ 158.433037] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +Aug 31 22:52:32 minifree kernel: [ 158.433041] [drm:i9xx_update_wm], memory self refresh enabled +Aug 31 22:52:32 minifree kernel: [ 158.433052] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:32 minifree kernel: [ 158.433058] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:32 minifree kernel: [ 158.433061] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:32 minifree kernel: [ 158.433065] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:32 minifree kernel: [ 158.433068] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:32 minifree kernel: [ 158.433072] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:32 minifree kernel: [ 158.433226] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +Aug 31 22:52:33 minifree kernel: [ 158.887022] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:33 minifree kernel: [ 158.887071] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +Aug 31 22:52:33 minifree kernel: [ 158.887077] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:33 minifree kernel: [ 158.887081] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +Aug 31 22:52:33 minifree kernel: [ 158.887098] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +Aug 31 22:52:33 minifree kernel: [ 158.887104] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +Aug 31 22:52:33 minifree kernel: [ 158.887108] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +Aug 31 22:52:33 minifree kernel: [ 158.887112] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +Aug 31 22:52:33 minifree kernel: [ 158.887115] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +Aug 31 22:52:33 minifree kernel: [ 158.887118] [drm:intel_dump_pipe_config], cpu_transcoder: A +Aug 31 22:52:33 minifree kernel: [ 158.887121] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +Aug 31 22:52:33 minifree kernel: [ 158.887124] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:33 minifree kernel: [ 158.887128] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:33 minifree kernel: [ 158.887131] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:52:33 minifree kernel: [ 158.887134] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:33 minifree kernel: [ 158.887139] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:52:33 minifree kernel: [ 158.887142] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:33 minifree kernel: [ 158.887147] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +Aug 31 22:52:33 minifree kernel: [ 158.887151] [drm:intel_dump_pipe_config], port clock: 108000 +Aug 31 22:52:33 minifree kernel: [ 158.887154] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +Aug 31 22:52:33 minifree kernel: [ 158.887157] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:52:33 minifree kernel: [ 158.887160] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:52:33 minifree kernel: [ 158.887164] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:52:33 minifree kernel: [ 158.887167] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:52:33 minifree kernel: [ 158.895657] [drm:i9xx_update_plane], Writing base 00C00000 00000000 0 0 5120 +Aug 31 22:52:33 minifree kernel: [ 158.895671] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +Aug 31 22:52:33 minifree kernel: [ 158.901303] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:33 minifree kernel: [ 158.901308] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:33 minifree kernel: [ 158.901310] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:33 minifree kernel: [ 158.901313] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:33 minifree kernel: [ 158.901317] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +Aug 31 22:52:33 minifree kernel: [ 158.901319] [drm:intel_calculate_wm], FIFO watermark level: -5 +Aug 31 22:52:33 minifree kernel: [ 158.901322] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +Aug 31 22:52:33 minifree kernel: [ 158.901325] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +Aug 31 22:52:33 minifree kernel: [ 158.901328] [drm:i9xx_update_wm], memory self refresh disabled +Aug 31 22:52:33 minifree kernel: [ 158.924049] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:33 minifree kernel: [ 158.924061] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:52:33 minifree kernel: [ 158.924065] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:33 minifree kernel: [ 158.924069] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:33 minifree kernel: [ 158.924072] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:33 minifree kernel: [ 158.924076] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:33 minifree kernel: [ 158.924086] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:33 minifree kernel: [ 158.964043] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +Aug 31 22:52:33 minifree kernel: [ 158.964051] [drm:intel_tv_detect_type], Unrecognised TV connection +Aug 31 22:52:33 minifree kernel: [ 158.984046] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:33 minifree kernel: [ 158.984058] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +Aug 31 22:52:33 minifree kernel: [ 159.033005] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:33 minifree kernel: [ 159.033015] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:33 minifree kernel: [ 159.033018] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:33 minifree kernel: [ 159.033021] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:33 minifree kernel: [ 159.033025] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +Aug 31 22:52:33 minifree kernel: [ 159.033028] [drm:i9xx_update_wm], self-refresh entries: 64 +Aug 31 22:52:33 minifree kernel: [ 159.033031] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +Aug 31 22:52:33 minifree kernel: [ 159.033035] [drm:i9xx_update_wm], memory self refresh enabled +Aug 31 22:52:33 minifree kernel: [ 159.033047] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:33 minifree kernel: [ 159.033053] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:33 minifree kernel: [ 159.033057] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:33 minifree kernel: [ 159.033060] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:33 minifree kernel: [ 159.033064] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:33 minifree kernel: [ 159.033067] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:33 minifree kernel: [ 159.034333] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +Aug 31 22:52:33 minifree kernel: [ 159.056046] [drm:intel_crt_detect], CRT not detected via hotplug +Aug 31 22:52:33 minifree kernel: [ 159.060079] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +Aug 31 22:52:33 minifree kernel: [ 159.060087] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:33 minifree kernel: [ 159.060091] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +Aug 31 22:52:33 minifree kernel: [ 159.060094] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +Aug 31 22:52:33 minifree kernel: [ 159.060374] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:33 minifree kernel: [ 159.060377] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +Aug 31 22:52:33 minifree kernel: [ 159.060380] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +Aug 31 22:52:36 minifree kernel: [ 162.048052] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:52:43 minifree kernel: [ 168.846014] [drm:i915_gem_open], +Aug 31 22:52:43 minifree kernel: [ 169.194795] [drm:i915_gem_open], +Aug 31 22:52:43 minifree kernel: [ 169.249719] [drm:i915_gem_open], +Aug 31 22:52:43 minifree kernel: [ 169.283957] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:43 minifree kernel: [ 169.283968] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:43 minifree kernel: [ 169.283973] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:43 minifree kernel: [ 169.283995] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +Aug 31 22:52:43 minifree kernel: [ 169.284035] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +Aug 31 22:52:43 minifree kernel: [ 169.284041] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:52:43 minifree kernel: [ 169.284046] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:52:43 minifree kernel: [ 169.284051] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +Aug 31 22:52:43 minifree kernel: [ 169.284055] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +Aug 31 22:52:43 minifree kernel: [ 169.284065] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:43 minifree kernel: [ 169.284300] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +Aug 31 22:52:43 minifree kernel: [ 169.284305] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +Aug 31 22:52:43 minifree kernel: [ 169.284308] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +Aug 31 22:52:43 minifree kernel: [ 169.300132] [drm:intel_crt_detect], CRT not detected via hotplug +Aug 31 22:52:43 minifree kernel: [ 169.304126] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +Aug 31 22:52:43 minifree kernel: [ 169.304134] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:43 minifree kernel: [ 169.304138] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +Aug 31 22:52:43 minifree kernel: [ 169.304142] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +Aug 31 22:52:43 minifree kernel: [ 169.304438] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:43 minifree kernel: [ 169.304441] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +Aug 31 22:52:43 minifree kernel: [ 169.304445] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +Aug 31 22:52:43 minifree kernel: [ 169.304449] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +Aug 31 22:52:43 minifree kernel: [ 169.304503] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +Aug 31 22:52:43 minifree kernel: [ 169.304508] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:52:43 minifree kernel: [ 169.304512] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +Aug 31 22:52:43 minifree kernel: [ 169.304516] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:43 minifree kernel: [ 169.304521] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +Aug 31 22:52:43 minifree kernel: [ 169.304535] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +Aug 31 22:52:43 minifree kernel: [ 169.304541] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +Aug 31 22:52:43 minifree kernel: [ 169.304544] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +Aug 31 22:52:43 minifree kernel: [ 169.304548] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +Aug 31 22:52:43 minifree kernel: [ 169.304551] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +Aug 31 22:52:43 minifree kernel: [ 169.304554] [drm:intel_dump_pipe_config], cpu_transcoder: A +Aug 31 22:52:43 minifree kernel: [ 169.304557] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +Aug 31 22:52:43 minifree kernel: [ 169.304560] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:43 minifree kernel: [ 169.304563] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:43 minifree kernel: [ 169.304567] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:52:43 minifree kernel: [ 169.304569] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:43 minifree kernel: [ 169.304575] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:52:43 minifree kernel: [ 169.304577] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:43 minifree kernel: [ 169.304582] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +Aug 31 22:52:43 minifree kernel: [ 169.304586] [drm:intel_dump_pipe_config], port clock: 108000 +Aug 31 22:52:43 minifree kernel: [ 169.304589] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +Aug 31 22:52:43 minifree kernel: [ 169.304592] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:52:43 minifree kernel: [ 169.304595] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:52:43 minifree kernel: [ 169.304599] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:52:43 minifree kernel: [ 169.304601] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:52:43 minifree kernel: [ 169.312528] [drm:i9xx_update_plane], Writing base 02800000 00000000 0 0 5120 +Aug 31 22:52:43 minifree kernel: [ 169.312539] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +Aug 31 22:52:43 minifree kernel: [ 169.318168] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:43 minifree kernel: [ 169.318172] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:43 minifree kernel: [ 169.318175] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:43 minifree kernel: [ 169.318178] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:43 minifree kernel: [ 169.318181] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +Aug 31 22:52:43 minifree kernel: [ 169.318184] [drm:intel_calculate_wm], FIFO watermark level: -5 +Aug 31 22:52:43 minifree kernel: [ 169.318187] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +Aug 31 22:52:43 minifree kernel: [ 169.318190] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +Aug 31 22:52:43 minifree kernel: [ 169.318193] [drm:i9xx_update_wm], memory self refresh disabled +Aug 31 22:52:43 minifree kernel: [ 169.340052] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:43 minifree kernel: [ 169.340063] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:52:43 minifree kernel: [ 169.340070] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:43 minifree kernel: [ 169.340075] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:43 minifree kernel: [ 169.340080] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:43 minifree kernel: [ 169.340085] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:43 minifree kernel: [ 169.340098] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:43 minifree kernel: [ 169.380054] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +Aug 31 22:52:43 minifree kernel: [ 169.380062] [drm:intel_tv_detect_type], Unrecognised TV connection +Aug 31 22:52:43 minifree kernel: [ 169.424049] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:43 minifree kernel: [ 169.424058] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +Aug 31 22:52:43 minifree kernel: [ 169.465004] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:43 minifree kernel: [ 169.465012] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:43 minifree kernel: [ 169.465015] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:43 minifree kernel: [ 169.465018] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:43 minifree kernel: [ 169.465021] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +Aug 31 22:52:43 minifree kernel: [ 169.465025] [drm:i9xx_update_wm], self-refresh entries: 64 +Aug 31 22:52:43 minifree kernel: [ 169.465028] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +Aug 31 22:52:43 minifree kernel: [ 169.465031] [drm:i9xx_update_wm], memory self refresh enabled +Aug 31 22:52:43 minifree kernel: [ 169.465043] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:43 minifree kernel: [ 169.465048] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:43 minifree kernel: [ 169.465052] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:43 minifree kernel: [ 169.465055] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:43 minifree kernel: [ 169.465059] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:43 minifree kernel: [ 169.465062] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:43 minifree kernel: [ 169.465213] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +Aug 31 22:52:44 minifree kernel: [ 169.535204] [drm:intel_crtc_cursor_set], cursor off +Aug 31 22:52:44 minifree kernel: [ 169.646187] [drm:intel_crtc_cursor_set], cursor off +Aug 31 22:52:44 minifree kernel: [ 170.257502] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:44 minifree kernel: [ 170.257514] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:44 minifree kernel: [ 170.257520] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:44 minifree kernel: [ 170.257543] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +Aug 31 22:52:44 minifree kernel: [ 170.257547] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +Aug 31 22:52:44 minifree kernel: [ 170.257553] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:52:44 minifree kernel: [ 170.257558] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:52:44 minifree kernel: [ 170.257563] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +Aug 31 22:52:44 minifree kernel: [ 170.257568] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +Aug 31 22:52:44 minifree kernel: [ 170.257576] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:44 minifree kernel: [ 170.257806] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +Aug 31 22:52:44 minifree kernel: [ 170.257811] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +Aug 31 22:52:44 minifree kernel: [ 170.257815] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +Aug 31 22:52:44 minifree kernel: [ 170.272041] [drm:intel_crt_detect], CRT not detected via hotplug +Aug 31 22:52:44 minifree kernel: [ 170.276070] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +Aug 31 22:52:44 minifree kernel: [ 170.276077] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:44 minifree kernel: [ 170.276080] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +Aug 31 22:52:44 minifree kernel: [ 170.276083] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +Aug 31 22:52:44 minifree kernel: [ 170.276360] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:44 minifree kernel: [ 170.276363] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +Aug 31 22:52:44 minifree kernel: [ 170.276366] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +Aug 31 22:52:44 minifree kernel: [ 170.276370] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +Aug 31 22:52:44 minifree kernel: [ 170.276393] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +Aug 31 22:52:44 minifree kernel: [ 170.276397] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:52:44 minifree kernel: [ 170.276401] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +Aug 31 22:52:44 minifree kernel: [ 170.276405] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:44 minifree kernel: [ 170.276410] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +Aug 31 22:52:44 minifree kernel: [ 170.276424] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +Aug 31 22:52:44 minifree kernel: [ 170.276430] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +Aug 31 22:52:44 minifree kernel: [ 170.276433] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +Aug 31 22:52:44 minifree kernel: [ 170.276437] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +Aug 31 22:52:44 minifree kernel: [ 170.276440] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +Aug 31 22:52:44 minifree kernel: [ 170.276443] [drm:intel_dump_pipe_config], cpu_transcoder: A +Aug 31 22:52:44 minifree kernel: [ 170.276446] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +Aug 31 22:52:44 minifree kernel: [ 170.276449] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:44 minifree kernel: [ 170.276453] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:44 minifree kernel: [ 170.276456] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:52:44 minifree kernel: [ 170.276459] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:44 minifree kernel: [ 170.276464] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:52:44 minifree kernel: [ 170.276467] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:44 minifree kernel: [ 170.276472] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +Aug 31 22:52:44 minifree kernel: [ 170.276476] [drm:intel_dump_pipe_config], port clock: 108000 +Aug 31 22:52:44 minifree kernel: [ 170.276479] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +Aug 31 22:52:44 minifree kernel: [ 170.276482] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:52:44 minifree kernel: [ 170.276485] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:52:44 minifree kernel: [ 170.276488] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:52:44 minifree kernel: [ 170.276491] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:52:44 minifree kernel: [ 170.283303] [drm:i9xx_update_plane], Writing base 02800000 00000000 0 0 5120 +Aug 31 22:52:44 minifree kernel: [ 170.283314] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +Aug 31 22:52:44 minifree kernel: [ 170.288947] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:44 minifree kernel: [ 170.288952] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:44 minifree kernel: [ 170.288954] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:44 minifree kernel: [ 170.288958] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:44 minifree kernel: [ 170.288961] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +Aug 31 22:52:44 minifree kernel: [ 170.288963] [drm:intel_calculate_wm], FIFO watermark level: -5 +Aug 31 22:52:44 minifree kernel: [ 170.288966] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +Aug 31 22:52:44 minifree kernel: [ 170.288969] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +Aug 31 22:52:44 minifree kernel: [ 170.288972] [drm:i9xx_update_wm], memory self refresh disabled +Aug 31 22:52:44 minifree kernel: [ 170.328052] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:44 minifree kernel: [ 170.328061] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:52:44 minifree kernel: [ 170.328066] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:44 minifree kernel: [ 170.328069] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:44 minifree kernel: [ 170.328073] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:44 minifree kernel: [ 170.328076] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:44 minifree kernel: [ 170.328087] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:44 minifree kernel: [ 170.368047] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +Aug 31 22:52:44 minifree kernel: [ 170.368054] [drm:intel_tv_detect_type], Unrecognised TV connection +Aug 31 22:52:44 minifree kernel: [ 170.384041] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:44 minifree kernel: [ 170.384048] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +Aug 31 22:52:44 minifree kernel: [ 170.429004] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:44 minifree kernel: [ 170.429010] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:44 minifree kernel: [ 170.429013] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:44 minifree kernel: [ 170.429016] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:44 minifree kernel: [ 170.429020] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +Aug 31 22:52:44 minifree kernel: [ 170.429023] [drm:i9xx_update_wm], self-refresh entries: 64 +Aug 31 22:52:44 minifree kernel: [ 170.429026] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +Aug 31 22:52:44 minifree kernel: [ 170.429029] [drm:i9xx_update_wm], memory self refresh enabled +Aug 31 22:52:44 minifree kernel: [ 170.429043] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:44 minifree kernel: [ 170.429048] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:44 minifree kernel: [ 170.429052] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:44 minifree kernel: [ 170.429055] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:44 minifree kernel: [ 170.429058] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:44 minifree kernel: [ 170.429062] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:44 minifree kernel: [ 170.429212] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +Aug 31 22:52:45 minifree kernel: [ 171.084188] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:45 minifree kernel: [ 171.084198] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:45 minifree kernel: [ 171.084203] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:45 minifree kernel: [ 171.084225] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +Aug 31 22:52:45 minifree kernel: [ 171.084229] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +Aug 31 22:52:45 minifree kernel: [ 171.084235] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:52:45 minifree kernel: [ 171.084240] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:52:45 minifree kernel: [ 171.084245] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +Aug 31 22:52:45 minifree kernel: [ 171.084249] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +Aug 31 22:52:45 minifree kernel: [ 171.084258] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:45 minifree kernel: [ 171.084505] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +Aug 31 22:52:45 minifree kernel: [ 171.084510] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +Aug 31 22:52:45 minifree kernel: [ 171.084514] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +Aug 31 22:52:45 minifree kernel: [ 171.100045] [drm:intel_crt_detect], CRT not detected via hotplug +Aug 31 22:52:45 minifree kernel: [ 171.104195] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +Aug 31 22:52:45 minifree kernel: [ 171.104204] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:45 minifree kernel: [ 171.104207] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +Aug 31 22:52:45 minifree kernel: [ 171.104210] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +Aug 31 22:52:45 minifree kernel: [ 171.104487] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:45 minifree kernel: [ 171.104490] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +Aug 31 22:52:45 minifree kernel: [ 171.104494] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +Aug 31 22:52:45 minifree kernel: [ 171.104498] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +Aug 31 22:52:45 minifree kernel: [ 171.104532] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +Aug 31 22:52:45 minifree kernel: [ 171.104537] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:52:45 minifree kernel: [ 171.104541] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +Aug 31 22:52:45 minifree kernel: [ 171.104546] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:45 minifree kernel: [ 171.104550] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +Aug 31 22:52:45 minifree kernel: [ 171.104568] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +Aug 31 22:52:45 minifree kernel: [ 171.104574] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +Aug 31 22:52:45 minifree kernel: [ 171.104577] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +Aug 31 22:52:45 minifree kernel: [ 171.104581] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +Aug 31 22:52:45 minifree kernel: [ 171.104584] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +Aug 31 22:52:45 minifree kernel: [ 171.104588] [drm:intel_dump_pipe_config], cpu_transcoder: A +Aug 31 22:52:45 minifree kernel: [ 171.104590] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +Aug 31 22:52:45 minifree kernel: [ 171.104593] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:45 minifree kernel: [ 171.104597] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:45 minifree kernel: [ 171.104600] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:52:45 minifree kernel: [ 171.104603] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:45 minifree kernel: [ 171.104608] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:52:45 minifree kernel: [ 171.104611] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:45 minifree kernel: [ 171.104616] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +Aug 31 22:52:45 minifree kernel: [ 171.104620] [drm:intel_dump_pipe_config], port clock: 108000 +Aug 31 22:52:45 minifree kernel: [ 171.104623] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +Aug 31 22:52:45 minifree kernel: [ 171.104626] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:52:45 minifree kernel: [ 171.104629] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:52:45 minifree kernel: [ 171.104633] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:52:45 minifree kernel: [ 171.104635] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:52:45 minifree kernel: [ 171.113463] [drm:i9xx_update_plane], Writing base 02800000 00000000 0 0 5120 +Aug 31 22:52:45 minifree kernel: [ 171.113476] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +Aug 31 22:52:45 minifree kernel: [ 171.119107] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:45 minifree kernel: [ 171.119112] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:45 minifree kernel: [ 171.119115] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:45 minifree kernel: [ 171.119118] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:45 minifree kernel: [ 171.119122] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +Aug 31 22:52:45 minifree kernel: [ 171.119124] [drm:intel_calculate_wm], FIFO watermark level: -5 +Aug 31 22:52:45 minifree kernel: [ 171.119127] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +Aug 31 22:52:45 minifree kernel: [ 171.119130] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +Aug 31 22:52:45 minifree kernel: [ 171.119133] [drm:i9xx_update_wm], memory self refresh disabled +Aug 31 22:52:45 minifree kernel: [ 171.144051] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:45 minifree kernel: [ 171.144061] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:52:45 minifree kernel: [ 171.144065] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:45 minifree kernel: [ 171.144069] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:45 minifree kernel: [ 171.144073] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:45 minifree kernel: [ 171.144076] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:45 minifree kernel: [ 171.144087] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:45 minifree kernel: [ 171.212055] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +Aug 31 22:52:45 minifree kernel: [ 171.212063] [drm:intel_tv_detect_type], Unrecognised TV connection +Aug 31 22:52:45 minifree kernel: [ 171.228056] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:45 minifree kernel: [ 171.228066] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +Aug 31 22:52:45 minifree kernel: [ 171.269008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:45 minifree kernel: [ 171.269017] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:45 minifree kernel: [ 171.269020] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:45 minifree kernel: [ 171.269023] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:45 minifree kernel: [ 171.269026] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +Aug 31 22:52:45 minifree kernel: [ 171.269029] [drm:i9xx_update_wm], self-refresh entries: 64 +Aug 31 22:52:45 minifree kernel: [ 171.269032] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +Aug 31 22:52:45 minifree kernel: [ 171.269036] [drm:i9xx_update_wm], memory self refresh enabled +Aug 31 22:52:45 minifree kernel: [ 171.271055] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:45 minifree kernel: [ 171.271062] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:45 minifree kernel: [ 171.271065] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:45 minifree kernel: [ 171.271069] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:45 minifree kernel: [ 171.271072] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:45 minifree kernel: [ 171.271076] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:45 minifree kernel: [ 171.271234] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +Aug 31 22:52:45 minifree kernel: [ 171.449390] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:45 minifree kernel: [ 171.449401] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:45 minifree kernel: [ 171.449406] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:45 minifree kernel: [ 171.449429] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +Aug 31 22:52:45 minifree kernel: [ 171.449433] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +Aug 31 22:52:45 minifree kernel: [ 171.449439] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:52:45 minifree kernel: [ 171.449444] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:52:45 minifree kernel: [ 171.449449] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +Aug 31 22:52:45 minifree kernel: [ 171.449453] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +Aug 31 22:52:45 minifree kernel: [ 171.449462] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:45 minifree kernel: [ 171.449715] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +Aug 31 22:52:45 minifree kernel: [ 171.449720] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +Aug 31 22:52:45 minifree kernel: [ 171.449724] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +Aug 31 22:52:45 minifree kernel: [ 171.464239] [drm:intel_crt_detect], CRT not detected via hotplug +Aug 31 22:52:45 minifree kernel: [ 171.468039] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +Aug 31 22:52:45 minifree kernel: [ 171.468046] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:45 minifree kernel: [ 171.468050] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +Aug 31 22:52:45 minifree kernel: [ 171.468053] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +Aug 31 22:52:45 minifree kernel: [ 171.468335] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:45 minifree kernel: [ 171.468338] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +Aug 31 22:52:45 minifree kernel: [ 171.468341] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +Aug 31 22:52:45 minifree kernel: [ 171.468346] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +Aug 31 22:52:45 minifree kernel: [ 171.468379] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +Aug 31 22:52:45 minifree kernel: [ 171.468384] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:52:45 minifree kernel: [ 171.468388] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +Aug 31 22:52:45 minifree kernel: [ 171.468393] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:45 minifree kernel: [ 171.468397] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +Aug 31 22:52:45 minifree kernel: [ 171.468414] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +Aug 31 22:52:45 minifree kernel: [ 171.468420] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +Aug 31 22:52:45 minifree kernel: [ 171.468424] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +Aug 31 22:52:45 minifree kernel: [ 171.468427] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +Aug 31 22:52:45 minifree kernel: [ 171.468431] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +Aug 31 22:52:45 minifree kernel: [ 171.468434] [drm:intel_dump_pipe_config], cpu_transcoder: A +Aug 31 22:52:45 minifree kernel: [ 171.468437] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +Aug 31 22:52:45 minifree kernel: [ 171.468440] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:45 minifree kernel: [ 171.468443] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:45 minifree kernel: [ 171.468447] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:52:45 minifree kernel: [ 171.468450] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:45 minifree kernel: [ 171.468455] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:52:45 minifree kernel: [ 171.468458] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:45 minifree kernel: [ 171.468462] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +Aug 31 22:52:45 minifree kernel: [ 171.468467] [drm:intel_dump_pipe_config], port clock: 108000 +Aug 31 22:52:45 minifree kernel: [ 171.468469] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +Aug 31 22:52:45 minifree kernel: [ 171.468472] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:52:45 minifree kernel: [ 171.468476] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:52:45 minifree kernel: [ 171.468479] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:52:45 minifree kernel: [ 171.468482] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:52:45 minifree kernel: [ 171.475659] [drm:i9xx_update_plane], Writing base 02860000 00000000 0 0 5120 +Aug 31 22:52:45 minifree kernel: [ 171.475670] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +Aug 31 22:52:45 minifree kernel: [ 171.481311] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:45 minifree kernel: [ 171.481317] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:45 minifree kernel: [ 171.481320] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:45 minifree kernel: [ 171.481323] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:45 minifree kernel: [ 171.481326] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +Aug 31 22:52:45 minifree kernel: [ 171.481329] [drm:intel_calculate_wm], FIFO watermark level: -5 +Aug 31 22:52:45 minifree kernel: [ 171.481331] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +Aug 31 22:52:45 minifree kernel: [ 171.481335] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +Aug 31 22:52:45 minifree kernel: [ 171.481338] [drm:i9xx_update_wm], memory self refresh disabled +Aug 31 22:52:45 minifree kernel: [ 171.504105] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:45 minifree kernel: [ 171.504115] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:52:45 minifree kernel: [ 171.504119] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:45 minifree kernel: [ 171.504123] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:45 minifree kernel: [ 171.504127] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:45 minifree kernel: [ 171.504130] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:45 minifree kernel: [ 171.504141] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:46 minifree kernel: [ 171.568041] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +Aug 31 22:52:46 minifree kernel: [ 171.568048] [drm:intel_tv_detect_type], Unrecognised TV connection +Aug 31 22:52:46 minifree kernel: [ 171.628046] [drm:intel_wait_for_vblank], vblank wait timed out +Aug 31 22:52:46 minifree kernel: [ 171.628054] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:46 minifree kernel: [ 171.628059] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +Aug 31 22:52:46 minifree kernel: [ 171.673007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:46 minifree kernel: [ 171.673014] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:46 minifree kernel: [ 171.673017] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:46 minifree kernel: [ 171.673020] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:46 minifree kernel: [ 171.673023] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +Aug 31 22:52:46 minifree kernel: [ 171.673027] [drm:i9xx_update_wm], self-refresh entries: 64 +Aug 31 22:52:46 minifree kernel: [ 171.673029] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +Aug 31 22:52:46 minifree kernel: [ 171.673033] [drm:i9xx_update_wm], memory self refresh enabled +Aug 31 22:52:46 minifree kernel: [ 171.673133] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:46 minifree kernel: [ 171.673139] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:46 minifree kernel: [ 171.673143] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:46 minifree kernel: [ 171.673147] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:46 minifree kernel: [ 171.673151] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:46 minifree kernel: [ 171.673154] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:46 minifree kernel: [ 171.673361] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +Aug 31 22:52:46 minifree kernel: [ 171.676431] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:46 minifree kernel: [ 171.676439] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:46 minifree kernel: [ 171.676444] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:46 minifree kernel: [ 171.676465] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +Aug 31 22:52:46 minifree kernel: [ 171.676468] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +Aug 31 22:52:46 minifree kernel: [ 171.676474] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:52:46 minifree kernel: [ 171.676479] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:52:46 minifree kernel: [ 171.676483] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +Aug 31 22:52:46 minifree kernel: [ 171.676488] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +Aug 31 22:52:46 minifree kernel: [ 171.676497] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:52:46 minifree kernel: [ 171.676719] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +Aug 31 22:52:46 minifree kernel: [ 171.676724] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +Aug 31 22:52:46 minifree kernel: [ 171.676727] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +Aug 31 22:52:46 minifree kernel: [ 171.692056] [drm:intel_crt_detect], CRT not detected via hotplug +Aug 31 22:52:46 minifree kernel: [ 171.697188] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +Aug 31 22:52:46 minifree kernel: [ 171.697197] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:46 minifree kernel: [ 171.697201] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +Aug 31 22:52:46 minifree kernel: [ 171.697203] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +Aug 31 22:52:46 minifree kernel: [ 171.697483] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:52:46 minifree kernel: [ 171.697486] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +Aug 31 22:52:46 minifree kernel: [ 171.697489] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +Aug 31 22:52:46 minifree kernel: [ 171.697494] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +Aug 31 22:52:46 minifree kernel: [ 171.697528] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +Aug 31 22:52:46 minifree kernel: [ 171.697534] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:52:46 minifree kernel: [ 171.697537] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +Aug 31 22:52:46 minifree kernel: [ 171.697542] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:46 minifree kernel: [ 171.697546] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +Aug 31 22:52:46 minifree kernel: [ 171.697564] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +Aug 31 22:52:46 minifree kernel: [ 171.697570] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +Aug 31 22:52:46 minifree kernel: [ 171.697574] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +Aug 31 22:52:46 minifree kernel: [ 171.697578] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +Aug 31 22:52:46 minifree kernel: [ 171.697581] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +Aug 31 22:52:46 minifree kernel: [ 171.697585] [drm:intel_dump_pipe_config], cpu_transcoder: A +Aug 31 22:52:46 minifree kernel: [ 171.697588] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +Aug 31 22:52:46 minifree kernel: [ 171.697590] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:46 minifree kernel: [ 171.697594] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:52:46 minifree kernel: [ 171.697598] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:52:46 minifree kernel: [ 171.697600] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:46 minifree kernel: [ 171.697605] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:52:46 minifree kernel: [ 171.697608] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:52:46 minifree kernel: [ 171.697613] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +Aug 31 22:52:46 minifree kernel: [ 171.697617] [drm:intel_dump_pipe_config], port clock: 108000 +Aug 31 22:52:46 minifree kernel: [ 171.697620] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +Aug 31 22:52:46 minifree kernel: [ 171.697623] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:52:46 minifree kernel: [ 171.697626] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:52:46 minifree kernel: [ 171.697629] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:52:46 minifree kernel: [ 171.697632] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:52:46 minifree kernel: [ 171.705575] [drm:i9xx_update_plane], Writing base 02860000 00000000 0 0 5120 +Aug 31 22:52:46 minifree kernel: [ 171.705587] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +Aug 31 22:52:46 minifree kernel: [ 171.711217] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:46 minifree kernel: [ 171.711221] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:46 minifree kernel: [ 171.711224] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:46 minifree kernel: [ 171.711227] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:46 minifree kernel: [ 171.711230] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +Aug 31 22:52:46 minifree kernel: [ 171.711233] [drm:intel_calculate_wm], FIFO watermark level: -5 +Aug 31 22:52:46 minifree kernel: [ 171.711235] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +Aug 31 22:52:46 minifree kernel: [ 171.711239] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +Aug 31 22:52:46 minifree kernel: [ 171.711242] [drm:i9xx_update_wm], memory self refresh disabled +Aug 31 22:52:46 minifree kernel: [ 171.732081] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:46 minifree kernel: [ 171.732087] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:52:46 minifree kernel: [ 171.732091] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:46 minifree kernel: [ 171.732095] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:46 minifree kernel: [ 171.732098] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:46 minifree kernel: [ 171.732102] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:46 minifree kernel: [ 171.732112] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:46 minifree kernel: [ 171.772048] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +Aug 31 22:52:46 minifree kernel: [ 171.772053] [drm:intel_tv_detect_type], Unrecognised TV connection +Aug 31 22:52:46 minifree kernel: [ 171.788030] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:52:46 minifree kernel: [ 171.788036] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +Aug 31 22:52:46 minifree kernel: [ 171.837008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:52:46 minifree kernel: [ 171.837016] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:52:46 minifree kernel: [ 171.837019] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:52:46 minifree kernel: [ 171.837022] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:52:46 minifree kernel: [ 171.837026] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +Aug 31 22:52:46 minifree kernel: [ 171.837029] [drm:i9xx_update_wm], self-refresh entries: 64 +Aug 31 22:52:46 minifree kernel: [ 171.837032] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +Aug 31 22:52:46 minifree kernel: [ 171.837035] [drm:i9xx_update_wm], memory self refresh enabled +Aug 31 22:52:46 minifree kernel: [ 171.837045] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:52:46 minifree kernel: [ 171.837050] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:52:46 minifree kernel: [ 171.837053] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:52:46 minifree kernel: [ 171.837057] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:52:46 minifree kernel: [ 171.837060] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:52:46 minifree kernel: [ 171.837064] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:52:46 minifree kernel: [ 171.837214] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +Aug 31 22:52:46 minifree kernel: [ 171.997747] [drm:drm_mode_addfb], [FB:34] +Aug 31 22:52:46 minifree kernel: [ 172.064040] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:52:56 minifree kernel: [ 182.080084] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:53:06 minifree kernel: [ 191.573667] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:53:06 minifree kernel: [ 191.573678] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] +Aug 31 22:53:06 minifree kernel: [ 191.573684] [drm:intel_lvds_detect], [CONNECTOR:5:LVDS-1] +Aug 31 22:53:06 minifree kernel: [ 191.573706] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] probed modes : +Aug 31 22:53:06 minifree kernel: [ 191.573710] [drm:drm_mode_debug_printmodeline], Modeline 8:"1024x768" 50 54160 1024 1048 1184 1344 768 771 777 806 0x48 0xa +Aug 31 22:53:06 minifree kernel: [ 191.573715] [drm:drm_mode_debug_printmodeline], Modeline 12:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:53:06 minifree kernel: [ 191.573720] [drm:drm_mode_debug_printmodeline], Modeline 9:"1024x768" 40 43330 1024 1048 1184 1344 768 771 777 806 0x40 0xa +Aug 31 22:53:06 minifree kernel: [ 191.573725] [drm:drm_mode_debug_printmodeline], Modeline 10:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 +Aug 31 22:53:06 minifree kernel: [ 191.573730] [drm:drm_mode_debug_printmodeline], Modeline 11:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa +Aug 31 22:53:06 minifree kernel: [ 191.573739] [drm:drm_mode_getconnector], [CONNECTOR:5:?] +Aug 31 22:53:06 minifree kernel: [ 191.573976] [drm:drm_mode_getconnector], [CONNECTOR:15:?] +Aug 31 22:53:06 minifree kernel: [ 191.573980] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] +Aug 31 22:53:06 minifree kernel: [ 191.573984] [drm:intel_crt_detect], [CONNECTOR:15:VGA-1] force=1 +Aug 31 22:53:06 minifree kernel: [ 191.596041] [drm:intel_crt_detect], CRT not detected via hotplug +Aug 31 22:53:06 minifree kernel: [ 191.600059] [drm:gmbus_xfer], GMBUS [i915 gmbus vga] NAK for addr: 0050 r(1) +Aug 31 22:53:06 minifree kernel: [ 191.600066] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:53:06 minifree kernel: [ 191.600070] [drm:intel_crt_get_edid], CRT GMBUS EDID read failed, retry using GPIO bit-banging +Aug 31 22:53:06 minifree kernel: [ 191.600072] [drm:intel_gmbus_force_bit], enabling bit-banging on i915 gmbus vga. force bit now 1 +Aug 31 22:53:06 minifree kernel: [ 191.600350] [drm:drm_do_probe_ddc_edid], drm: skipping non-existent adapter i915 gmbus vga +Aug 31 22:53:06 minifree kernel: [ 191.600353] [drm:intel_gmbus_force_bit], disabling bit-banging on i915 gmbus vga. force bit now 0 +Aug 31 22:53:06 minifree kernel: [ 191.600356] [drm:intel_crt_detect_ddc], CRT not detected via DDC:0x50 [no valid EDID found] +Aug 31 22:53:06 minifree kernel: [ 191.600359] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:VGA-1] disconnected +Aug 31 22:53:06 minifree kernel: [ 191.600384] [drm:drm_mode_getconnector], [CONNECTOR:17:?] +Aug 31 22:53:06 minifree kernel: [ 191.600388] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:53:06 minifree kernel: [ 191.600392] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=1 +Aug 31 22:53:06 minifree kernel: [ 191.600397] [drm:intel_get_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:53:06 minifree kernel: [ 191.600401] [drm:intel_get_load_detect_pipe], creating tmp fb for load-detection +Aug 31 22:53:06 minifree kernel: [ 191.600417] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 1, prepare: 1, disable: 0 +Aug 31 22:53:06 minifree kernel: [ 191.600423] [drm:connected_sink_compute_bpp], [CONNECTOR:17:SVIDEO-1] checking for sink bpp constrains +Aug 31 22:53:06 minifree kernel: [ 191.600426] [drm:intel_tv_compute_config], forcing bpc to 8 for TV +Aug 31 22:53:06 minifree kernel: [ 191.600429] [drm:intel_modeset_pipe_config], plane bpp: 24, pipe bpp: 24, dithering: 0 +Aug 31 22:53:06 minifree kernel: [ 191.600433] [drm:intel_dump_pipe_config], [CRTC:3][modeset] config for pipe A +Aug 31 22:53:06 minifree kernel: [ 191.600436] [drm:intel_dump_pipe_config], cpu_transcoder: A +Aug 31 22:53:06 minifree kernel: [ 191.600439] [drm:intel_dump_pipe_config], pipe bpp: 24, dithering: 0 +Aug 31 22:53:06 minifree kernel: [ 191.600442] [drm:intel_dump_pipe_config], fdi/pch: 0, lanes: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:53:06 minifree kernel: [ 191.600445] [drm:intel_dump_pipe_config], dp: 0, gmch_m: 0, gmch_n: 0, link_m: 0, link_n: 0, tu: 0 +Aug 31 22:53:06 minifree kernel: [ 191.600449] [drm:intel_dump_pipe_config], requested mode: +Aug 31 22:53:06 minifree kernel: [ 191.600452] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:53:06 minifree kernel: [ 191.600457] [drm:intel_dump_pipe_config], adjusted mode: +Aug 31 22:53:06 minifree kernel: [ 191.600459] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 +Aug 31 22:53:06 minifree kernel: [ 191.600464] [drm:intel_dump_crtc_timings], crtc timings: 108000 1280 1368 1496 1712 1024 1027 1034 1104, type: 0x40 flags: 0x0 +Aug 31 22:53:06 minifree kernel: [ 191.600468] [drm:intel_dump_pipe_config], port clock: 108000 +Aug 31 22:53:06 minifree kernel: [ 191.600471] [drm:intel_dump_pipe_config], pipe src size: 1280x1024 +Aug 31 22:53:06 minifree kernel: [ 191.600474] [drm:intel_dump_pipe_config], gmch pfit: control: 0x00000000, ratios: 0x00000000, lvds border: 0x00000000 +Aug 31 22:53:06 minifree kernel: [ 191.600477] [drm:intel_dump_pipe_config], pch pfit: pos: 0x00000000, size: 0x00000000, disabled +Aug 31 22:53:06 minifree kernel: [ 191.600481] [drm:intel_dump_pipe_config], ips: 0 +Aug 31 22:53:06 minifree kernel: [ 191.600484] [drm:intel_dump_pipe_config], double wide: 0 +Aug 31 22:53:06 minifree kernel: [ 191.607207] [drm:i9xx_update_plane], Writing base 05040000 00000000 0 0 5120 +Aug 31 22:53:06 minifree kernel: [ 191.607218] [drm:intel_crtc_mode_set], [ENCODER:18:TV-18] set [MODE:0:NTSC 480i] +Aug 31 22:53:06 minifree kernel: [ 191.612854] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:53:06 minifree kernel: [ 191.612859] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:53:06 minifree kernel: [ 191.612862] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:53:06 minifree kernel: [ 191.612865] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:53:06 minifree kernel: [ 191.612868] [drm:intel_calculate_wm], FIFO entries required for mode: 34 +Aug 31 22:53:06 minifree kernel: [ 191.612870] [drm:intel_calculate_wm], FIFO watermark level: -5 +Aug 31 22:53:06 minifree kernel: [ 191.612873] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 1 +Aug 31 22:53:06 minifree kernel: [ 191.612876] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 1, C: 2, SR 1 +Aug 31 22:53:06 minifree kernel: [ 191.612880] [drm:i9xx_update_wm], memory self refresh disabled +Aug 31 22:53:06 minifree kernel: [ 191.636051] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:53:06 minifree kernel: [ 191.636059] [drm:intel_connector_check_state], [CONNECTOR:17:SVIDEO-1] +Aug 31 22:53:06 minifree kernel: [ 191.636063] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:53:06 minifree kernel: [ 191.636066] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:53:06 minifree kernel: [ 191.636070] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:53:06 minifree kernel: [ 191.636073] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:53:06 minifree kernel: [ 191.636083] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:53:06 minifree kernel: [ 191.676047] [drm:intel_tv_detect_type], TV detected: c0007, 7f0000aa +Aug 31 22:53:06 minifree kernel: [ 191.676053] [drm:intel_tv_detect_type], Unrecognised TV connection +Aug 31 22:53:06 minifree kernel: [ 191.692041] [drm:intel_release_load_detect_pipe], [CONNECTOR:17:SVIDEO-1], [ENCODER:18:TV-18] +Aug 31 22:53:06 minifree kernel: [ 191.692047] [drm:intel_modeset_affected_pipes], set mode pipe masks: modeset: 0, prepare: 0, disable: 1 +Aug 31 22:53:06 minifree kernel: [ 191.745006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 +Aug 31 22:53:06 minifree kernel: [ 191.745014] [drm:intel_calculate_wm], FIFO entries required for mode: 17 +Aug 31 22:53:06 minifree kernel: [ 191.745017] [drm:intel_calculate_wm], FIFO watermark level: 9 +Aug 31 22:53:06 minifree kernel: [ 191.745020] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 +Aug 31 22:53:06 minifree kernel: [ 191.745024] [drm:i9xx_update_wm], FIFO watermarks - A: 9, B: 29 +Aug 31 22:53:06 minifree kernel: [ 191.745027] [drm:i9xx_update_wm], self-refresh entries: 64 +Aug 31 22:53:06 minifree kernel: [ 191.745030] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 9, B: 29, C: 2, SR 63 +Aug 31 22:53:06 minifree kernel: [ 191.745034] [drm:i9xx_update_wm], memory self refresh enabled +Aug 31 22:53:06 minifree kernel: [ 191.745045] [drm:intel_connector_check_state], [CONNECTOR:5:LVDS-1] +Aug 31 22:53:06 minifree kernel: [ 191.745050] [drm:check_encoder_state], [ENCODER:6:LVDS-6] +Aug 31 22:53:06 minifree kernel: [ 191.745053] [drm:check_encoder_state], [ENCODER:16:DAC-16] +Aug 31 22:53:06 minifree kernel: [ 191.745057] [drm:check_encoder_state], [ENCODER:18:TV-18] +Aug 31 22:53:06 minifree kernel: [ 191.745060] [drm:check_crtc_state], [CRTC:3] +Aug 31 22:53:06 minifree kernel: [ 191.745064] [drm:check_crtc_state], [CRTC:4] +Aug 31 22:53:06 minifree kernel: [ 191.745217] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:SVIDEO-1] disconnected +Aug 31 22:53:06 minifree kernel: [ 192.096128] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:53:16 minifree kernel: [ 202.112100] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:53:26 minifree kernel: [ 212.128145] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:53:36 minifree kernel: [ 222.144192] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:53:46 minifree kernel: [ 232.160064] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 +Aug 31 22:53:56 minifree kernel: [ 242.176124] [drm:intel_tv_detect], [CONNECTOR:17:SVIDEO-1] force=0 diff --git a/i18n/fr_FR/docs/future/dumps/t500_x200_descriptor/descriptor_diff_t500_x200.txt b/i18n/fr_FR/docs/future/dumps/t500_x200_descriptor/descriptor_diff_t500_x200.txt new file mode 100644 index 00000000..f05f6859 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/t500_x200_descriptor/descriptor_diff_t500_x200.txt @@ -0,0 +1,3366 @@ +--- mkdescriptor.c 2015-03-31 04:46:11.840747724 +0100 ++++ ../lbdev/libreboot/resources/utilities/ich9deblob/src/ich9gen/mkdescriptor.c 2015-03-26 16:55:12.243313103 +0000 +@@ -1,5 +1,19 @@ +-/* mkdescriptor.c: generated C code from ich9deblob */ +-/* .c source file for the descriptor-generating C code */ ++/* ++ * Copyright (C) 2014 Leah Rowe ++ * ++ * This program is free software: you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 3 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ + + #include "mkdescriptor.h" + +@@ -35,7 +49,7 @@ + + /* Component Section Record */ + /* FLCOMP */ +- descriptorStruct.componentSection.flcomp.component1Density = 0x3; ++ descriptorStruct.componentSection.flcomp.component1Density = 0x4; + descriptorStruct.componentSection.flcomp.component2Density = 0x2; + descriptorStruct.componentSection.flcomp.reserved1 = 0x0; + descriptorStruct.componentSection.flcomp.reserved2 = 0x00; +@@ -65,7 +79,7 @@ + /* descriptorStruct.regionSection.flReg1.BASE = 0x0003; */ + descriptorStruct.regionSection.flReg1.BASE = (DESCRIPTORREGIONSIZE + GBEREGIONSIZE_8K) >> FLREGIONBITSHIFT; /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg1.reserved1 = 0x0; +- /* descriptorStruct.regionSection.flReg1.LIMIT = 0x03ff; */ ++ /* descriptorStruct.regionSection.flReg1.LIMIT = 0x07ff; */ + descriptorStruct.regionSection.flReg1.LIMIT = ((romSize >> FLREGIONBITSHIFT) - 1); /* see ../descriptor/descriptor.c */ + descriptorStruct.regionSection.flReg1.reserved2 = 0x0; + /* FLREG2 (ME) */ +@@ -177,3314 +191,25 @@ + descriptorStruct.mchStraps.mchStrap0.reserved2 = 0xff; + descriptorStruct.mchStraps.mchStrap0.reserved3 = 0xffff; + /* Padding */ +- descriptorStruct.mchStraps.padding[0] = 0xff; +- descriptorStruct.mchStraps.padding[1] = 0xff; +- descriptorStruct.mchStraps.padding[2] = 0xff; +- descriptorStruct.mchStraps.padding[3] = 0xff; +- descriptorStruct.mchStraps.padding[4] = 0xff; +- descriptorStruct.mchStraps.padding[5] = 0xff; +- descriptorStruct.mchStraps.padding[6] = 0xff; +- descriptorStruct.mchStraps.padding[7] = 0xff; +- descriptorStruct.mchStraps.padding[8] = 0xff; +- descriptorStruct.mchStraps.padding[9] = 0xff; +- descriptorStruct.mchStraps.padding[10] = 0xff; +- descriptorStruct.mchStraps.padding[11] = 0xff; +- descriptorStruct.mchStraps.padding[12] = 0xff; +- descriptorStruct.mchStraps.padding[13] = 0xff; +- descriptorStruct.mchStraps.padding[14] = 0xff; +- descriptorStruct.mchStraps.padding[15] = 0xff; +- descriptorStruct.mchStraps.padding[16] = 0xff; +- descriptorStruct.mchStraps.padding[17] = 0xff; +- descriptorStruct.mchStraps.padding[18] = 0xff; +- descriptorStruct.mchStraps.padding[19] = 0xff; +- descriptorStruct.mchStraps.padding[20] = 0xff; +- descriptorStruct.mchStraps.padding[21] = 0xff; +- descriptorStruct.mchStraps.padding[22] = 0xff; +- descriptorStruct.mchStraps.padding[23] = 0xff; +- descriptorStruct.mchStraps.padding[24] = 0xff; +- descriptorStruct.mchStraps.padding[25] = 0xff; +- descriptorStruct.mchStraps.padding[26] = 0xff; +- descriptorStruct.mchStraps.padding[27] = 0xff; +- descriptorStruct.mchStraps.padding[28] = 0xff; +- descriptorStruct.mchStraps.padding[29] = 0xff; +- descriptorStruct.mchStraps.padding[30] = 0xff; +- descriptorStruct.mchStraps.padding[31] = 0xff; +- descriptorStruct.mchStraps.padding[32] = 0xff; +- descriptorStruct.mchStraps.padding[33] = 0xff; +- descriptorStruct.mchStraps.padding[34] = 0xff; +- descriptorStruct.mchStraps.padding[35] = 0xff; +- descriptorStruct.mchStraps.padding[36] = 0xff; +- descriptorStruct.mchStraps.padding[37] = 0xff; +- descriptorStruct.mchStraps.padding[38] = 0xff; +- descriptorStruct.mchStraps.padding[39] = 0xff; +- descriptorStruct.mchStraps.padding[40] = 0xff; +- descriptorStruct.mchStraps.padding[41] = 0xff; +- descriptorStruct.mchStraps.padding[42] = 0xff; +- descriptorStruct.mchStraps.padding[43] = 0xff; +- descriptorStruct.mchStraps.padding[44] = 0xff; +- descriptorStruct.mchStraps.padding[45] = 0xff; +- descriptorStruct.mchStraps.padding[46] = 0xff; +- descriptorStruct.mchStraps.padding[47] = 0xff; +- descriptorStruct.mchStraps.padding[48] = 0xff; +- descriptorStruct.mchStraps.padding[49] = 0xff; +- descriptorStruct.mchStraps.padding[50] = 0xff; +- descriptorStruct.mchStraps.padding[51] = 0xff; +- descriptorStruct.mchStraps.padding[52] = 0xff; +- descriptorStruct.mchStraps.padding[53] = 0xff; +- descriptorStruct.mchStraps.padding[54] = 0xff; +- descriptorStruct.mchStraps.padding[55] = 0xff; +- descriptorStruct.mchStraps.padding[56] = 0xff; +- descriptorStruct.mchStraps.padding[57] = 0xff; +- descriptorStruct.mchStraps.padding[58] = 0xff; +- descriptorStruct.mchStraps.padding[59] = 0xff; +- descriptorStruct.mchStraps.padding[60] = 0xff; +- descriptorStruct.mchStraps.padding[61] = 0xff; +- descriptorStruct.mchStraps.padding[62] = 0xff; +- descriptorStruct.mchStraps.padding[63] = 0xff; +- descriptorStruct.mchStraps.padding[64] = 0xff; +- descriptorStruct.mchStraps.padding[65] = 0xff; +- descriptorStruct.mchStraps.padding[66] = 0xff; +- descriptorStruct.mchStraps.padding[67] = 0xff; +- descriptorStruct.mchStraps.padding[68] = 0xff; +- descriptorStruct.mchStraps.padding[69] = 0xff; +- descriptorStruct.mchStraps.padding[70] = 0xff; +- descriptorStruct.mchStraps.padding[71] = 0xff; +- descriptorStruct.mchStraps.padding[72] = 0xff; +- descriptorStruct.mchStraps.padding[73] = 0xff; +- descriptorStruct.mchStraps.padding[74] = 0xff; +- descriptorStruct.mchStraps.padding[75] = 0xff; +- descriptorStruct.mchStraps.padding[76] = 0xff; +- descriptorStruct.mchStraps.padding[77] = 0xff; +- descriptorStruct.mchStraps.padding[78] = 0xff; +- descriptorStruct.mchStraps.padding[79] = 0xff; +- descriptorStruct.mchStraps.padding[80] = 0xff; +- descriptorStruct.mchStraps.padding[81] = 0xff; +- descriptorStruct.mchStraps.padding[82] = 0xff; +- descriptorStruct.mchStraps.padding[83] = 0xff; +- descriptorStruct.mchStraps.padding[84] = 0xff; +- descriptorStruct.mchStraps.padding[85] = 0xff; +- descriptorStruct.mchStraps.padding[86] = 0xff; +- descriptorStruct.mchStraps.padding[87] = 0xff; +- descriptorStruct.mchStraps.padding[88] = 0xff; +- descriptorStruct.mchStraps.padding[89] = 0xff; +- descriptorStruct.mchStraps.padding[90] = 0xff; +- descriptorStruct.mchStraps.padding[91] = 0xff; +- descriptorStruct.mchStraps.padding[92] = 0xff; +- descriptorStruct.mchStraps.padding[93] = 0xff; +- descriptorStruct.mchStraps.padding[94] = 0xff; +- descriptorStruct.mchStraps.padding[95] = 0xff; +- descriptorStruct.mchStraps.padding[96] = 0xff; +- descriptorStruct.mchStraps.padding[97] = 0xff; +- descriptorStruct.mchStraps.padding[98] = 0xff; +- descriptorStruct.mchStraps.padding[99] = 0xff; +- descriptorStruct.mchStraps.padding[100] = 0xff; +- descriptorStruct.mchStraps.padding[101] = 0xff; +- descriptorStruct.mchStraps.padding[102] = 0xff; +- descriptorStruct.mchStraps.padding[103] = 0xff; +- descriptorStruct.mchStraps.padding[104] = 0xff; +- descriptorStruct.mchStraps.padding[105] = 0xff; +- descriptorStruct.mchStraps.padding[106] = 0xff; +- descriptorStruct.mchStraps.padding[107] = 0xff; +- descriptorStruct.mchStraps.padding[108] = 0xff; +- descriptorStruct.mchStraps.padding[109] = 0xff; +- descriptorStruct.mchStraps.padding[110] = 0xff; +- descriptorStruct.mchStraps.padding[111] = 0xff; +- descriptorStruct.mchStraps.padding[112] = 0xff; +- descriptorStruct.mchStraps.padding[113] = 0xff; +- descriptorStruct.mchStraps.padding[114] = 0xff; +- descriptorStruct.mchStraps.padding[115] = 0xff; +- descriptorStruct.mchStraps.padding[116] = 0xff; +- descriptorStruct.mchStraps.padding[117] = 0xff; +- descriptorStruct.mchStraps.padding[118] = 0xff; +- descriptorStruct.mchStraps.padding[119] = 0xff; +- descriptorStruct.mchStraps.padding[120] = 0xff; +- descriptorStruct.mchStraps.padding[121] = 0xff; +- descriptorStruct.mchStraps.padding[122] = 0xff; +- descriptorStruct.mchStraps.padding[123] = 0xff; +- descriptorStruct.mchStraps.padding[124] = 0xff; +- descriptorStruct.mchStraps.padding[125] = 0xff; +- descriptorStruct.mchStraps.padding[126] = 0xff; +- descriptorStruct.mchStraps.padding[127] = 0xff; +- descriptorStruct.mchStraps.padding[128] = 0xff; +- descriptorStruct.mchStraps.padding[129] = 0xff; +- descriptorStruct.mchStraps.padding[130] = 0xff; +- descriptorStruct.mchStraps.padding[131] = 0xff; +- descriptorStruct.mchStraps.padding[132] = 0xff; +- descriptorStruct.mchStraps.padding[133] = 0xff; +- descriptorStruct.mchStraps.padding[134] = 0xff; +- descriptorStruct.mchStraps.padding[135] = 0xff; +- descriptorStruct.mchStraps.padding[136] = 0xff; +- descriptorStruct.mchStraps.padding[137] = 0xff; +- descriptorStruct.mchStraps.padding[138] = 0xff; +- descriptorStruct.mchStraps.padding[139] = 0xff; +- descriptorStruct.mchStraps.padding[140] = 0xff; +- descriptorStruct.mchStraps.padding[141] = 0xff; +- descriptorStruct.mchStraps.padding[142] = 0xff; +- descriptorStruct.mchStraps.padding[143] = 0xff; +- descriptorStruct.mchStraps.padding[144] = 0xff; +- descriptorStruct.mchStraps.padding[145] = 0xff; +- descriptorStruct.mchStraps.padding[146] = 0xff; +- descriptorStruct.mchStraps.padding[147] = 0xff; +- descriptorStruct.mchStraps.padding[148] = 0xff; +- descriptorStruct.mchStraps.padding[149] = 0xff; +- descriptorStruct.mchStraps.padding[150] = 0xff; +- descriptorStruct.mchStraps.padding[151] = 0xff; +- descriptorStruct.mchStraps.padding[152] = 0xff; +- descriptorStruct.mchStraps.padding[153] = 0xff; +- descriptorStruct.mchStraps.padding[154] = 0xff; +- descriptorStruct.mchStraps.padding[155] = 0xff; +- descriptorStruct.mchStraps.padding[156] = 0xff; +- descriptorStruct.mchStraps.padding[157] = 0xff; +- descriptorStruct.mchStraps.padding[158] = 0xff; +- descriptorStruct.mchStraps.padding[159] = 0xff; +- descriptorStruct.mchStraps.padding[160] = 0xff; +- descriptorStruct.mchStraps.padding[161] = 0xff; +- descriptorStruct.mchStraps.padding[162] = 0xff; +- descriptorStruct.mchStraps.padding[163] = 0xff; +- descriptorStruct.mchStraps.padding[164] = 0xff; +- descriptorStruct.mchStraps.padding[165] = 0xff; +- descriptorStruct.mchStraps.padding[166] = 0xff; +- descriptorStruct.mchStraps.padding[167] = 0xff; +- descriptorStruct.mchStraps.padding[168] = 0xff; +- descriptorStruct.mchStraps.padding[169] = 0xff; +- descriptorStruct.mchStraps.padding[170] = 0xff; +- descriptorStruct.mchStraps.padding[171] = 0xff; +- descriptorStruct.mchStraps.padding[172] = 0xff; +- descriptorStruct.mchStraps.padding[173] = 0xff; +- descriptorStruct.mchStraps.padding[174] = 0xff; +- descriptorStruct.mchStraps.padding[175] = 0xff; +- descriptorStruct.mchStraps.padding[176] = 0xff; +- descriptorStruct.mchStraps.padding[177] = 0xff; +- descriptorStruct.mchStraps.padding[178] = 0xff; +- descriptorStruct.mchStraps.padding[179] = 0xff; +- descriptorStruct.mchStraps.padding[180] = 0xff; +- descriptorStruct.mchStraps.padding[181] = 0xff; +- descriptorStruct.mchStraps.padding[182] = 0xff; +- descriptorStruct.mchStraps.padding[183] = 0xff; +- descriptorStruct.mchStraps.padding[184] = 0xff; +- descriptorStruct.mchStraps.padding[185] = 0xff; +- descriptorStruct.mchStraps.padding[186] = 0xff; +- descriptorStruct.mchStraps.padding[187] = 0xff; +- descriptorStruct.mchStraps.padding[188] = 0xff; +- descriptorStruct.mchStraps.padding[189] = 0xff; +- descriptorStruct.mchStraps.padding[190] = 0xff; +- descriptorStruct.mchStraps.padding[191] = 0xff; +- descriptorStruct.mchStraps.padding[192] = 0xff; +- descriptorStruct.mchStraps.padding[193] = 0xff; +- descriptorStruct.mchStraps.padding[194] = 0xff; +- descriptorStruct.mchStraps.padding[195] = 0xff; +- descriptorStruct.mchStraps.padding[196] = 0xff; +- descriptorStruct.mchStraps.padding[197] = 0xff; +- descriptorStruct.mchStraps.padding[198] = 0xff; +- descriptorStruct.mchStraps.padding[199] = 0xff; +- descriptorStruct.mchStraps.padding[200] = 0xff; +- descriptorStruct.mchStraps.padding[201] = 0xff; +- descriptorStruct.mchStraps.padding[202] = 0xff; +- descriptorStruct.mchStraps.padding[203] = 0xff; +- descriptorStruct.mchStraps.padding[204] = 0xff; +- descriptorStruct.mchStraps.padding[205] = 0xff; +- descriptorStruct.mchStraps.padding[206] = 0xff; +- descriptorStruct.mchStraps.padding[207] = 0xff; +- descriptorStruct.mchStraps.padding[208] = 0xff; +- descriptorStruct.mchStraps.padding[209] = 0xff; +- descriptorStruct.mchStraps.padding[210] = 0xff; +- descriptorStruct.mchStraps.padding[211] = 0xff; +- descriptorStruct.mchStraps.padding[212] = 0xff; +- descriptorStruct.mchStraps.padding[213] = 0xff; +- descriptorStruct.mchStraps.padding[214] = 0xff; +- descriptorStruct.mchStraps.padding[215] = 0xff; +- descriptorStruct.mchStraps.padding[216] = 0xff; +- descriptorStruct.mchStraps.padding[217] = 0xff; +- descriptorStruct.mchStraps.padding[218] = 0xff; +- descriptorStruct.mchStraps.padding[219] = 0xff; +- descriptorStruct.mchStraps.padding[220] = 0xff; +- descriptorStruct.mchStraps.padding[221] = 0xff; +- descriptorStruct.mchStraps.padding[222] = 0xff; +- descriptorStruct.mchStraps.padding[223] = 0xff; +- descriptorStruct.mchStraps.padding[224] = 0xff; +- descriptorStruct.mchStraps.padding[225] = 0xff; +- descriptorStruct.mchStraps.padding[226] = 0xff; +- descriptorStruct.mchStraps.padding[227] = 0xff; +- descriptorStruct.mchStraps.padding[228] = 0xff; +- descriptorStruct.mchStraps.padding[229] = 0xff; +- descriptorStruct.mchStraps.padding[230] = 0xff; +- descriptorStruct.mchStraps.padding[231] = 0xff; +- descriptorStruct.mchStraps.padding[232] = 0xff; +- descriptorStruct.mchStraps.padding[233] = 0xff; +- descriptorStruct.mchStraps.padding[234] = 0xff; +- descriptorStruct.mchStraps.padding[235] = 0xff; +- descriptorStruct.mchStraps.padding[236] = 0xff; +- descriptorStruct.mchStraps.padding[237] = 0xff; +- descriptorStruct.mchStraps.padding[238] = 0xff; +- descriptorStruct.mchStraps.padding[239] = 0xff; +- descriptorStruct.mchStraps.padding[240] = 0xff; +- descriptorStruct.mchStraps.padding[241] = 0xff; +- descriptorStruct.mchStraps.padding[242] = 0xff; +- descriptorStruct.mchStraps.padding[243] = 0xff; +- descriptorStruct.mchStraps.padding[244] = 0xff; +- descriptorStruct.mchStraps.padding[245] = 0xff; +- descriptorStruct.mchStraps.padding[246] = 0xff; +- descriptorStruct.mchStraps.padding[247] = 0xff; +- descriptorStruct.mchStraps.padding[248] = 0xff; +- descriptorStruct.mchStraps.padding[249] = 0xff; +- descriptorStruct.mchStraps.padding[250] = 0xff; +- descriptorStruct.mchStraps.padding[251] = 0xff; +- descriptorStruct.mchStraps.padding[252] = 0xff; +- descriptorStruct.mchStraps.padding[253] = 0xff; +- descriptorStruct.mchStraps.padding[254] = 0xff; +- descriptorStruct.mchStraps.padding[255] = 0xff; +- descriptorStruct.mchStraps.padding[256] = 0xff; +- descriptorStruct.mchStraps.padding[257] = 0xff; +- descriptorStruct.mchStraps.padding[258] = 0xff; +- descriptorStruct.mchStraps.padding[259] = 0xff; +- descriptorStruct.mchStraps.padding[260] = 0xff; +- descriptorStruct.mchStraps.padding[261] = 0xff; +- descriptorStruct.mchStraps.padding[262] = 0xff; +- descriptorStruct.mchStraps.padding[263] = 0xff; +- descriptorStruct.mchStraps.padding[264] = 0xff; +- descriptorStruct.mchStraps.padding[265] = 0xff; +- descriptorStruct.mchStraps.padding[266] = 0xff; +- descriptorStruct.mchStraps.padding[267] = 0xff; +- descriptorStruct.mchStraps.padding[268] = 0xff; +- descriptorStruct.mchStraps.padding[269] = 0xff; +- descriptorStruct.mchStraps.padding[270] = 0xff; +- descriptorStruct.mchStraps.padding[271] = 0xff; +- descriptorStruct.mchStraps.padding[272] = 0xff; +- descriptorStruct.mchStraps.padding[273] = 0xff; +- descriptorStruct.mchStraps.padding[274] = 0xff; +- descriptorStruct.mchStraps.padding[275] = 0xff; +- descriptorStruct.mchStraps.padding[276] = 0xff; +- descriptorStruct.mchStraps.padding[277] = 0xff; +- descriptorStruct.mchStraps.padding[278] = 0xff; +- descriptorStruct.mchStraps.padding[279] = 0xff; +- descriptorStruct.mchStraps.padding[280] = 0xff; +- descriptorStruct.mchStraps.padding[281] = 0xff; +- descriptorStruct.mchStraps.padding[282] = 0xff; +- descriptorStruct.mchStraps.padding[283] = 0xff; +- descriptorStruct.mchStraps.padding[284] = 0xff; +- descriptorStruct.mchStraps.padding[285] = 0xff; +- descriptorStruct.mchStraps.padding[286] = 0xff; +- descriptorStruct.mchStraps.padding[287] = 0xff; +- descriptorStruct.mchStraps.padding[288] = 0xff; +- descriptorStruct.mchStraps.padding[289] = 0xff; +- descriptorStruct.mchStraps.padding[290] = 0xff; +- descriptorStruct.mchStraps.padding[291] = 0xff; +- descriptorStruct.mchStraps.padding[292] = 0xff; +- descriptorStruct.mchStraps.padding[293] = 0xff; +- descriptorStruct.mchStraps.padding[294] = 0xff; +- descriptorStruct.mchStraps.padding[295] = 0xff; +- descriptorStruct.mchStraps.padding[296] = 0xff; +- descriptorStruct.mchStraps.padding[297] = 0xff; +- descriptorStruct.mchStraps.padding[298] = 0xff; +- descriptorStruct.mchStraps.padding[299] = 0xff; +- descriptorStruct.mchStraps.padding[300] = 0xff; +- descriptorStruct.mchStraps.padding[301] = 0xff; +- descriptorStruct.mchStraps.padding[302] = 0xff; +- descriptorStruct.mchStraps.padding[303] = 0xff; +- descriptorStruct.mchStraps.padding[304] = 0xff; +- descriptorStruct.mchStraps.padding[305] = 0xff; +- descriptorStruct.mchStraps.padding[306] = 0xff; +- descriptorStruct.mchStraps.padding[307] = 0xff; +- descriptorStruct.mchStraps.padding[308] = 0xff; +- descriptorStruct.mchStraps.padding[309] = 0xff; +- descriptorStruct.mchStraps.padding[310] = 0xff; +- descriptorStruct.mchStraps.padding[311] = 0xff; +- descriptorStruct.mchStraps.padding[312] = 0xff; +- descriptorStruct.mchStraps.padding[313] = 0xff; +- descriptorStruct.mchStraps.padding[314] = 0xff; +- descriptorStruct.mchStraps.padding[315] = 0xff; +- descriptorStruct.mchStraps.padding[316] = 0xff; +- descriptorStruct.mchStraps.padding[317] = 0xff; +- descriptorStruct.mchStraps.padding[318] = 0xff; +- descriptorStruct.mchStraps.padding[319] = 0xff; +- descriptorStruct.mchStraps.padding[320] = 0xff; +- descriptorStruct.mchStraps.padding[321] = 0xff; +- descriptorStruct.mchStraps.padding[322] = 0xff; +- descriptorStruct.mchStraps.padding[323] = 0xff; +- descriptorStruct.mchStraps.padding[324] = 0xff; +- descriptorStruct.mchStraps.padding[325] = 0xff; +- descriptorStruct.mchStraps.padding[326] = 0xff; +- descriptorStruct.mchStraps.padding[327] = 0xff; +- descriptorStruct.mchStraps.padding[328] = 0xff; +- descriptorStruct.mchStraps.padding[329] = 0xff; +- descriptorStruct.mchStraps.padding[330] = 0xff; +- descriptorStruct.mchStraps.padding[331] = 0xff; +- descriptorStruct.mchStraps.padding[332] = 0xff; +- descriptorStruct.mchStraps.padding[333] = 0xff; +- descriptorStruct.mchStraps.padding[334] = 0xff; +- descriptorStruct.mchStraps.padding[335] = 0xff; +- descriptorStruct.mchStraps.padding[336] = 0xff; +- descriptorStruct.mchStraps.padding[337] = 0xff; +- descriptorStruct.mchStraps.padding[338] = 0xff; +- descriptorStruct.mchStraps.padding[339] = 0xff; +- descriptorStruct.mchStraps.padding[340] = 0xff; +- descriptorStruct.mchStraps.padding[341] = 0xff; +- descriptorStruct.mchStraps.padding[342] = 0xff; +- descriptorStruct.mchStraps.padding[343] = 0xff; +- descriptorStruct.mchStraps.padding[344] = 0xff; +- descriptorStruct.mchStraps.padding[345] = 0xff; +- descriptorStruct.mchStraps.padding[346] = 0xff; +- descriptorStruct.mchStraps.padding[347] = 0xff; +- descriptorStruct.mchStraps.padding[348] = 0xff; +- descriptorStruct.mchStraps.padding[349] = 0xff; +- descriptorStruct.mchStraps.padding[350] = 0xff; +- descriptorStruct.mchStraps.padding[351] = 0xff; +- descriptorStruct.mchStraps.padding[352] = 0xff; +- descriptorStruct.mchStraps.padding[353] = 0xff; +- descriptorStruct.mchStraps.padding[354] = 0xff; +- descriptorStruct.mchStraps.padding[355] = 0xff; +- descriptorStruct.mchStraps.padding[356] = 0xff; +- descriptorStruct.mchStraps.padding[357] = 0xff; +- descriptorStruct.mchStraps.padding[358] = 0xff; +- descriptorStruct.mchStraps.padding[359] = 0xff; +- descriptorStruct.mchStraps.padding[360] = 0xff; +- descriptorStruct.mchStraps.padding[361] = 0xff; +- descriptorStruct.mchStraps.padding[362] = 0xff; +- descriptorStruct.mchStraps.padding[363] = 0xff; +- descriptorStruct.mchStraps.padding[364] = 0xff; +- descriptorStruct.mchStraps.padding[365] = 0xff; +- descriptorStruct.mchStraps.padding[366] = 0xff; +- descriptorStruct.mchStraps.padding[367] = 0xff; +- descriptorStruct.mchStraps.padding[368] = 0xff; +- descriptorStruct.mchStraps.padding[369] = 0xff; +- descriptorStruct.mchStraps.padding[370] = 0xff; +- descriptorStruct.mchStraps.padding[371] = 0xff; +- descriptorStruct.mchStraps.padding[372] = 0xff; +- descriptorStruct.mchStraps.padding[373] = 0xff; +- descriptorStruct.mchStraps.padding[374] = 0xff; +- descriptorStruct.mchStraps.padding[375] = 0xff; +- descriptorStruct.mchStraps.padding[376] = 0xff; +- descriptorStruct.mchStraps.padding[377] = 0xff; +- descriptorStruct.mchStraps.padding[378] = 0xff; +- descriptorStruct.mchStraps.padding[379] = 0xff; +- descriptorStruct.mchStraps.padding[380] = 0xff; +- descriptorStruct.mchStraps.padding[381] = 0xff; +- descriptorStruct.mchStraps.padding[382] = 0xff; +- descriptorStruct.mchStraps.padding[383] = 0xff; +- descriptorStruct.mchStraps.padding[384] = 0xff; +- descriptorStruct.mchStraps.padding[385] = 0xff; +- descriptorStruct.mchStraps.padding[386] = 0xff; +- descriptorStruct.mchStraps.padding[387] = 0xff; +- descriptorStruct.mchStraps.padding[388] = 0xff; +- descriptorStruct.mchStraps.padding[389] = 0xff; +- descriptorStruct.mchStraps.padding[390] = 0xff; +- descriptorStruct.mchStraps.padding[391] = 0xff; +- descriptorStruct.mchStraps.padding[392] = 0xff; +- descriptorStruct.mchStraps.padding[393] = 0xff; +- descriptorStruct.mchStraps.padding[394] = 0xff; +- descriptorStruct.mchStraps.padding[395] = 0xff; +- descriptorStruct.mchStraps.padding[396] = 0xff; +- descriptorStruct.mchStraps.padding[397] = 0xff; +- descriptorStruct.mchStraps.padding[398] = 0xff; +- descriptorStruct.mchStraps.padding[399] = 0xff; +- descriptorStruct.mchStraps.padding[400] = 0xff; +- descriptorStruct.mchStraps.padding[401] = 0xff; +- descriptorStruct.mchStraps.padding[402] = 0xff; +- descriptorStruct.mchStraps.padding[403] = 0xff; +- descriptorStruct.mchStraps.padding[404] = 0xff; +- descriptorStruct.mchStraps.padding[405] = 0xff; +- descriptorStruct.mchStraps.padding[406] = 0xff; +- descriptorStruct.mchStraps.padding[407] = 0xff; +- descriptorStruct.mchStraps.padding[408] = 0xff; +- descriptorStruct.mchStraps.padding[409] = 0xff; +- descriptorStruct.mchStraps.padding[410] = 0xff; +- descriptorStruct.mchStraps.padding[411] = 0xff; +- descriptorStruct.mchStraps.padding[412] = 0xff; +- descriptorStruct.mchStraps.padding[413] = 0xff; +- descriptorStruct.mchStraps.padding[414] = 0xff; +- descriptorStruct.mchStraps.padding[415] = 0xff; +- descriptorStruct.mchStraps.padding[416] = 0xff; +- descriptorStruct.mchStraps.padding[417] = 0xff; +- descriptorStruct.mchStraps.padding[418] = 0xff; +- descriptorStruct.mchStraps.padding[419] = 0xff; +- descriptorStruct.mchStraps.padding[420] = 0xff; +- descriptorStruct.mchStraps.padding[421] = 0xff; +- descriptorStruct.mchStraps.padding[422] = 0xff; +- descriptorStruct.mchStraps.padding[423] = 0xff; +- descriptorStruct.mchStraps.padding[424] = 0xff; +- descriptorStruct.mchStraps.padding[425] = 0xff; +- descriptorStruct.mchStraps.padding[426] = 0xff; +- descriptorStruct.mchStraps.padding[427] = 0xff; +- descriptorStruct.mchStraps.padding[428] = 0xff; +- descriptorStruct.mchStraps.padding[429] = 0xff; +- descriptorStruct.mchStraps.padding[430] = 0xff; +- descriptorStruct.mchStraps.padding[431] = 0xff; +- descriptorStruct.mchStraps.padding[432] = 0xff; +- descriptorStruct.mchStraps.padding[433] = 0xff; +- descriptorStruct.mchStraps.padding[434] = 0xff; +- descriptorStruct.mchStraps.padding[435] = 0xff; +- descriptorStruct.mchStraps.padding[436] = 0xff; +- descriptorStruct.mchStraps.padding[437] = 0xff; +- descriptorStruct.mchStraps.padding[438] = 0xff; +- descriptorStruct.mchStraps.padding[439] = 0xff; +- descriptorStruct.mchStraps.padding[440] = 0xff; +- descriptorStruct.mchStraps.padding[441] = 0xff; +- descriptorStruct.mchStraps.padding[442] = 0xff; +- descriptorStruct.mchStraps.padding[443] = 0xff; +- descriptorStruct.mchStraps.padding[444] = 0xff; +- descriptorStruct.mchStraps.padding[445] = 0xff; +- descriptorStruct.mchStraps.padding[446] = 0xff; +- descriptorStruct.mchStraps.padding[447] = 0xff; +- descriptorStruct.mchStraps.padding[448] = 0xff; +- descriptorStruct.mchStraps.padding[449] = 0xff; +- descriptorStruct.mchStraps.padding[450] = 0xff; +- descriptorStruct.mchStraps.padding[451] = 0xff; +- descriptorStruct.mchStraps.padding[452] = 0xff; +- descriptorStruct.mchStraps.padding[453] = 0xff; +- descriptorStruct.mchStraps.padding[454] = 0xff; +- descriptorStruct.mchStraps.padding[455] = 0xff; +- descriptorStruct.mchStraps.padding[456] = 0xff; +- descriptorStruct.mchStraps.padding[457] = 0xff; +- descriptorStruct.mchStraps.padding[458] = 0xff; +- descriptorStruct.mchStraps.padding[459] = 0xff; +- descriptorStruct.mchStraps.padding[460] = 0xff; +- descriptorStruct.mchStraps.padding[461] = 0xff; +- descriptorStruct.mchStraps.padding[462] = 0xff; +- descriptorStruct.mchStraps.padding[463] = 0xff; +- descriptorStruct.mchStraps.padding[464] = 0xff; +- descriptorStruct.mchStraps.padding[465] = 0xff; +- descriptorStruct.mchStraps.padding[466] = 0xff; +- descriptorStruct.mchStraps.padding[467] = 0xff; +- descriptorStruct.mchStraps.padding[468] = 0xff; +- descriptorStruct.mchStraps.padding[469] = 0xff; +- descriptorStruct.mchStraps.padding[470] = 0xff; +- descriptorStruct.mchStraps.padding[471] = 0xff; +- descriptorStruct.mchStraps.padding[472] = 0xff; +- descriptorStruct.mchStraps.padding[473] = 0xff; +- descriptorStruct.mchStraps.padding[474] = 0xff; +- descriptorStruct.mchStraps.padding[475] = 0xff; +- descriptorStruct.mchStraps.padding[476] = 0xff; +- descriptorStruct.mchStraps.padding[477] = 0xff; +- descriptorStruct.mchStraps.padding[478] = 0xff; +- descriptorStruct.mchStraps.padding[479] = 0xff; +- descriptorStruct.mchStraps.padding[480] = 0xff; +- descriptorStruct.mchStraps.padding[481] = 0xff; +- descriptorStruct.mchStraps.padding[482] = 0xff; +- descriptorStruct.mchStraps.padding[483] = 0xff; +- descriptorStruct.mchStraps.padding[484] = 0xff; +- descriptorStruct.mchStraps.padding[485] = 0xff; +- descriptorStruct.mchStraps.padding[486] = 0xff; +- descriptorStruct.mchStraps.padding[487] = 0xff; +- descriptorStruct.mchStraps.padding[488] = 0xff; +- descriptorStruct.mchStraps.padding[489] = 0xff; +- descriptorStruct.mchStraps.padding[490] = 0xff; +- descriptorStruct.mchStraps.padding[491] = 0xff; +- descriptorStruct.mchStraps.padding[492] = 0xff; +- descriptorStruct.mchStraps.padding[493] = 0xff; +- descriptorStruct.mchStraps.padding[494] = 0xff; +- descriptorStruct.mchStraps.padding[495] = 0xff; +- descriptorStruct.mchStraps.padding[496] = 0xff; +- descriptorStruct.mchStraps.padding[497] = 0xff; +- descriptorStruct.mchStraps.padding[498] = 0xff; +- descriptorStruct.mchStraps.padding[499] = 0xff; +- descriptorStruct.mchStraps.padding[500] = 0xff; +- descriptorStruct.mchStraps.padding[501] = 0xff; +- descriptorStruct.mchStraps.padding[502] = 0xff; +- descriptorStruct.mchStraps.padding[503] = 0xff; +- descriptorStruct.mchStraps.padding[504] = 0xff; +- descriptorStruct.mchStraps.padding[505] = 0xff; +- descriptorStruct.mchStraps.padding[506] = 0xff; +- descriptorStruct.mchStraps.padding[507] = 0xff; +- descriptorStruct.mchStraps.padding[508] = 0xff; +- descriptorStruct.mchStraps.padding[509] = 0xff; +- descriptorStruct.mchStraps.padding[510] = 0xff; +- descriptorStruct.mchStraps.padding[511] = 0xff; +- descriptorStruct.mchStraps.padding[512] = 0xff; +- descriptorStruct.mchStraps.padding[513] = 0xff; +- descriptorStruct.mchStraps.padding[514] = 0xff; +- descriptorStruct.mchStraps.padding[515] = 0xff; +- descriptorStruct.mchStraps.padding[516] = 0xff; +- descriptorStruct.mchStraps.padding[517] = 0xff; +- descriptorStruct.mchStraps.padding[518] = 0xff; +- descriptorStruct.mchStraps.padding[519] = 0xff; +- descriptorStruct.mchStraps.padding[520] = 0xff; +- descriptorStruct.mchStraps.padding[521] = 0xff; +- descriptorStruct.mchStraps.padding[522] = 0xff; +- descriptorStruct.mchStraps.padding[523] = 0xff; +- descriptorStruct.mchStraps.padding[524] = 0xff; +- descriptorStruct.mchStraps.padding[525] = 0xff; +- descriptorStruct.mchStraps.padding[526] = 0xff; +- descriptorStruct.mchStraps.padding[527] = 0xff; +- descriptorStruct.mchStraps.padding[528] = 0xff; +- descriptorStruct.mchStraps.padding[529] = 0xff; +- descriptorStruct.mchStraps.padding[530] = 0xff; +- descriptorStruct.mchStraps.padding[531] = 0xff; +- descriptorStruct.mchStraps.padding[532] = 0xff; +- descriptorStruct.mchStraps.padding[533] = 0xff; +- descriptorStruct.mchStraps.padding[534] = 0xff; +- descriptorStruct.mchStraps.padding[535] = 0xff; +- descriptorStruct.mchStraps.padding[536] = 0xff; +- descriptorStruct.mchStraps.padding[537] = 0xff; +- descriptorStruct.mchStraps.padding[538] = 0xff; +- descriptorStruct.mchStraps.padding[539] = 0xff; +- descriptorStruct.mchStraps.padding[540] = 0xff; +- descriptorStruct.mchStraps.padding[541] = 0xff; +- descriptorStruct.mchStraps.padding[542] = 0xff; +- descriptorStruct.mchStraps.padding[543] = 0xff; +- descriptorStruct.mchStraps.padding[544] = 0xff; +- descriptorStruct.mchStraps.padding[545] = 0xff; +- descriptorStruct.mchStraps.padding[546] = 0xff; +- descriptorStruct.mchStraps.padding[547] = 0xff; +- descriptorStruct.mchStraps.padding[548] = 0xff; +- descriptorStruct.mchStraps.padding[549] = 0xff; +- descriptorStruct.mchStraps.padding[550] = 0xff; +- descriptorStruct.mchStraps.padding[551] = 0xff; +- descriptorStruct.mchStraps.padding[552] = 0xff; +- descriptorStruct.mchStraps.padding[553] = 0xff; +- descriptorStruct.mchStraps.padding[554] = 0xff; +- descriptorStruct.mchStraps.padding[555] = 0xff; +- descriptorStruct.mchStraps.padding[556] = 0xff; +- descriptorStruct.mchStraps.padding[557] = 0xff; +- descriptorStruct.mchStraps.padding[558] = 0xff; +- descriptorStruct.mchStraps.padding[559] = 0xff; +- descriptorStruct.mchStraps.padding[560] = 0xff; +- descriptorStruct.mchStraps.padding[561] = 0xff; +- descriptorStruct.mchStraps.padding[562] = 0xff; +- descriptorStruct.mchStraps.padding[563] = 0xff; +- descriptorStruct.mchStraps.padding[564] = 0xff; +- descriptorStruct.mchStraps.padding[565] = 0xff; +- descriptorStruct.mchStraps.padding[566] = 0xff; +- descriptorStruct.mchStraps.padding[567] = 0xff; +- descriptorStruct.mchStraps.padding[568] = 0xff; +- descriptorStruct.mchStraps.padding[569] = 0xff; +- descriptorStruct.mchStraps.padding[570] = 0xff; +- descriptorStruct.mchStraps.padding[571] = 0xff; +- descriptorStruct.mchStraps.padding[572] = 0xff; +- descriptorStruct.mchStraps.padding[573] = 0xff; +- descriptorStruct.mchStraps.padding[574] = 0xff; +- descriptorStruct.mchStraps.padding[575] = 0xff; +- descriptorStruct.mchStraps.padding[576] = 0xff; +- descriptorStruct.mchStraps.padding[577] = 0xff; +- descriptorStruct.mchStraps.padding[578] = 0xff; +- descriptorStruct.mchStraps.padding[579] = 0xff; +- descriptorStruct.mchStraps.padding[580] = 0xff; +- descriptorStruct.mchStraps.padding[581] = 0xff; +- descriptorStruct.mchStraps.padding[582] = 0xff; +- descriptorStruct.mchStraps.padding[583] = 0xff; +- descriptorStruct.mchStraps.padding[584] = 0xff; +- descriptorStruct.mchStraps.padding[585] = 0xff; +- descriptorStruct.mchStraps.padding[586] = 0xff; +- descriptorStruct.mchStraps.padding[587] = 0xff; +- descriptorStruct.mchStraps.padding[588] = 0xff; +- descriptorStruct.mchStraps.padding[589] = 0xff; +- descriptorStruct.mchStraps.padding[590] = 0xff; +- descriptorStruct.mchStraps.padding[591] = 0xff; +- descriptorStruct.mchStraps.padding[592] = 0xff; +- descriptorStruct.mchStraps.padding[593] = 0xff; +- descriptorStruct.mchStraps.padding[594] = 0xff; +- descriptorStruct.mchStraps.padding[595] = 0xff; +- descriptorStruct.mchStraps.padding[596] = 0xff; +- descriptorStruct.mchStraps.padding[597] = 0xff; +- descriptorStruct.mchStraps.padding[598] = 0xff; +- descriptorStruct.mchStraps.padding[599] = 0xff; +- descriptorStruct.mchStraps.padding[600] = 0xff; +- descriptorStruct.mchStraps.padding[601] = 0xff; +- descriptorStruct.mchStraps.padding[602] = 0xff; +- descriptorStruct.mchStraps.padding[603] = 0xff; +- descriptorStruct.mchStraps.padding[604] = 0xff; +- descriptorStruct.mchStraps.padding[605] = 0xff; +- descriptorStruct.mchStraps.padding[606] = 0xff; +- descriptorStruct.mchStraps.padding[607] = 0xff; +- descriptorStruct.mchStraps.padding[608] = 0xff; +- descriptorStruct.mchStraps.padding[609] = 0xff; +- descriptorStruct.mchStraps.padding[610] = 0xff; +- descriptorStruct.mchStraps.padding[611] = 0xff; +- descriptorStruct.mchStraps.padding[612] = 0xff; +- descriptorStruct.mchStraps.padding[613] = 0xff; +- descriptorStruct.mchStraps.padding[614] = 0xff; +- descriptorStruct.mchStraps.padding[615] = 0xff; +- descriptorStruct.mchStraps.padding[616] = 0xff; +- descriptorStruct.mchStraps.padding[617] = 0xff; +- descriptorStruct.mchStraps.padding[618] = 0xff; +- descriptorStruct.mchStraps.padding[619] = 0xff; +- descriptorStruct.mchStraps.padding[620] = 0xff; +- descriptorStruct.mchStraps.padding[621] = 0xff; +- descriptorStruct.mchStraps.padding[622] = 0xff; +- descriptorStruct.mchStraps.padding[623] = 0xff; +- descriptorStruct.mchStraps.padding[624] = 0xff; +- descriptorStruct.mchStraps.padding[625] = 0xff; +- descriptorStruct.mchStraps.padding[626] = 0xff; +- descriptorStruct.mchStraps.padding[627] = 0xff; +- descriptorStruct.mchStraps.padding[628] = 0xff; +- descriptorStruct.mchStraps.padding[629] = 0xff; +- descriptorStruct.mchStraps.padding[630] = 0xff; +- descriptorStruct.mchStraps.padding[631] = 0xff; +- descriptorStruct.mchStraps.padding[632] = 0xff; +- descriptorStruct.mchStraps.padding[633] = 0xff; +- descriptorStruct.mchStraps.padding[634] = 0xff; +- descriptorStruct.mchStraps.padding[635] = 0xff; +- descriptorStruct.mchStraps.padding[636] = 0xff; +- descriptorStruct.mchStraps.padding[637] = 0xff; +- descriptorStruct.mchStraps.padding[638] = 0xff; +- descriptorStruct.mchStraps.padding[639] = 0xff; +- descriptorStruct.mchStraps.padding[640] = 0xff; +- descriptorStruct.mchStraps.padding[641] = 0xff; +- descriptorStruct.mchStraps.padding[642] = 0xff; +- descriptorStruct.mchStraps.padding[643] = 0xff; +- descriptorStruct.mchStraps.padding[644] = 0xff; +- descriptorStruct.mchStraps.padding[645] = 0xff; +- descriptorStruct.mchStraps.padding[646] = 0xff; +- descriptorStruct.mchStraps.padding[647] = 0xff; +- descriptorStruct.mchStraps.padding[648] = 0xff; +- descriptorStruct.mchStraps.padding[649] = 0xff; +- descriptorStruct.mchStraps.padding[650] = 0xff; +- descriptorStruct.mchStraps.padding[651] = 0xff; +- descriptorStruct.mchStraps.padding[652] = 0xff; +- descriptorStruct.mchStraps.padding[653] = 0xff; +- descriptorStruct.mchStraps.padding[654] = 0xff; +- descriptorStruct.mchStraps.padding[655] = 0xff; +- descriptorStruct.mchStraps.padding[656] = 0xff; +- descriptorStruct.mchStraps.padding[657] = 0xff; +- descriptorStruct.mchStraps.padding[658] = 0xff; +- descriptorStruct.mchStraps.padding[659] = 0xff; +- descriptorStruct.mchStraps.padding[660] = 0xff; +- descriptorStruct.mchStraps.padding[661] = 0xff; +- descriptorStruct.mchStraps.padding[662] = 0xff; +- descriptorStruct.mchStraps.padding[663] = 0xff; +- descriptorStruct.mchStraps.padding[664] = 0xff; +- descriptorStruct.mchStraps.padding[665] = 0xff; +- descriptorStruct.mchStraps.padding[666] = 0xff; +- descriptorStruct.mchStraps.padding[667] = 0xff; +- descriptorStruct.mchStraps.padding[668] = 0xff; +- descriptorStruct.mchStraps.padding[669] = 0xff; +- descriptorStruct.mchStraps.padding[670] = 0xff; +- descriptorStruct.mchStraps.padding[671] = 0xff; +- descriptorStruct.mchStraps.padding[672] = 0xff; +- descriptorStruct.mchStraps.padding[673] = 0xff; +- descriptorStruct.mchStraps.padding[674] = 0xff; +- descriptorStruct.mchStraps.padding[675] = 0xff; +- descriptorStruct.mchStraps.padding[676] = 0xff; +- descriptorStruct.mchStraps.padding[677] = 0xff; +- descriptorStruct.mchStraps.padding[678] = 0xff; +- descriptorStruct.mchStraps.padding[679] = 0xff; +- descriptorStruct.mchStraps.padding[680] = 0xff; +- descriptorStruct.mchStraps.padding[681] = 0xff; +- descriptorStruct.mchStraps.padding[682] = 0xff; +- descriptorStruct.mchStraps.padding[683] = 0xff; +- descriptorStruct.mchStraps.padding[684] = 0xff; +- descriptorStruct.mchStraps.padding[685] = 0xff; +- descriptorStruct.mchStraps.padding[686] = 0xff; +- descriptorStruct.mchStraps.padding[687] = 0xff; +- descriptorStruct.mchStraps.padding[688] = 0xff; +- descriptorStruct.mchStraps.padding[689] = 0xff; +- descriptorStruct.mchStraps.padding[690] = 0xff; +- descriptorStruct.mchStraps.padding[691] = 0xff; +- descriptorStruct.mchStraps.padding[692] = 0xff; +- descriptorStruct.mchStraps.padding[693] = 0xff; +- descriptorStruct.mchStraps.padding[694] = 0xff; +- descriptorStruct.mchStraps.padding[695] = 0xff; +- descriptorStruct.mchStraps.padding[696] = 0xff; +- descriptorStruct.mchStraps.padding[697] = 0xff; +- descriptorStruct.mchStraps.padding[698] = 0xff; +- descriptorStruct.mchStraps.padding[699] = 0xff; +- descriptorStruct.mchStraps.padding[700] = 0xff; +- descriptorStruct.mchStraps.padding[701] = 0xff; +- descriptorStruct.mchStraps.padding[702] = 0xff; +- descriptorStruct.mchStraps.padding[703] = 0xff; +- descriptorStruct.mchStraps.padding[704] = 0xff; +- descriptorStruct.mchStraps.padding[705] = 0xff; +- descriptorStruct.mchStraps.padding[706] = 0xff; +- descriptorStruct.mchStraps.padding[707] = 0xff; +- descriptorStruct.mchStraps.padding[708] = 0xff; +- descriptorStruct.mchStraps.padding[709] = 0xff; +- descriptorStruct.mchStraps.padding[710] = 0xff; +- descriptorStruct.mchStraps.padding[711] = 0xff; +- descriptorStruct.mchStraps.padding[712] = 0xff; +- descriptorStruct.mchStraps.padding[713] = 0xff; +- descriptorStruct.mchStraps.padding[714] = 0xff; +- descriptorStruct.mchStraps.padding[715] = 0xff; +- descriptorStruct.mchStraps.padding[716] = 0xff; +- descriptorStruct.mchStraps.padding[717] = 0xff; +- descriptorStruct.mchStraps.padding[718] = 0xff; +- descriptorStruct.mchStraps.padding[719] = 0xff; +- descriptorStruct.mchStraps.padding[720] = 0xff; +- descriptorStruct.mchStraps.padding[721] = 0xff; +- descriptorStruct.mchStraps.padding[722] = 0xff; +- descriptorStruct.mchStraps.padding[723] = 0xff; +- descriptorStruct.mchStraps.padding[724] = 0xff; +- descriptorStruct.mchStraps.padding[725] = 0xff; +- descriptorStruct.mchStraps.padding[726] = 0xff; +- descriptorStruct.mchStraps.padding[727] = 0xff; +- descriptorStruct.mchStraps.padding[728] = 0xff; +- descriptorStruct.mchStraps.padding[729] = 0xff; +- descriptorStruct.mchStraps.padding[730] = 0xff; +- descriptorStruct.mchStraps.padding[731] = 0xff; +- descriptorStruct.mchStraps.padding[732] = 0xff; +- descriptorStruct.mchStraps.padding[733] = 0xff; +- descriptorStruct.mchStraps.padding[734] = 0xff; +- descriptorStruct.mchStraps.padding[735] = 0xff; +- descriptorStruct.mchStraps.padding[736] = 0xff; +- descriptorStruct.mchStraps.padding[737] = 0xff; +- descriptorStruct.mchStraps.padding[738] = 0xff; +- descriptorStruct.mchStraps.padding[739] = 0xff; +- descriptorStruct.mchStraps.padding[740] = 0xff; +- descriptorStruct.mchStraps.padding[741] = 0xff; +- descriptorStruct.mchStraps.padding[742] = 0xff; +- descriptorStruct.mchStraps.padding[743] = 0xff; +- descriptorStruct.mchStraps.padding[744] = 0xff; +- descriptorStruct.mchStraps.padding[745] = 0xff; +- descriptorStruct.mchStraps.padding[746] = 0xff; +- descriptorStruct.mchStraps.padding[747] = 0xff; +- descriptorStruct.mchStraps.padding[748] = 0xff; +- descriptorStruct.mchStraps.padding[749] = 0xff; +- descriptorStruct.mchStraps.padding[750] = 0xff; +- descriptorStruct.mchStraps.padding[751] = 0xff; +- descriptorStruct.mchStraps.padding[752] = 0xff; +- descriptorStruct.mchStraps.padding[753] = 0xff; +- descriptorStruct.mchStraps.padding[754] = 0xff; +- descriptorStruct.mchStraps.padding[755] = 0xff; +- descriptorStruct.mchStraps.padding[756] = 0xff; +- descriptorStruct.mchStraps.padding[757] = 0xff; +- descriptorStruct.mchStraps.padding[758] = 0xff; +- descriptorStruct.mchStraps.padding[759] = 0xff; +- descriptorStruct.mchStraps.padding[760] = 0xff; +- descriptorStruct.mchStraps.padding[761] = 0xff; +- descriptorStruct.mchStraps.padding[762] = 0xff; +- descriptorStruct.mchStraps.padding[763] = 0xff; +- descriptorStruct.mchStraps.padding[764] = 0xff; +- descriptorStruct.mchStraps.padding[765] = 0xff; +- descriptorStruct.mchStraps.padding[766] = 0xff; +- descriptorStruct.mchStraps.padding[767] = 0xff; +- descriptorStruct.mchStraps.padding[768] = 0xff; +- descriptorStruct.mchStraps.padding[769] = 0xff; +- descriptorStruct.mchStraps.padding[770] = 0xff; +- descriptorStruct.mchStraps.padding[771] = 0xff; +- descriptorStruct.mchStraps.padding[772] = 0xff; +- descriptorStruct.mchStraps.padding[773] = 0xff; +- descriptorStruct.mchStraps.padding[774] = 0xff; +- descriptorStruct.mchStraps.padding[775] = 0xff; +- descriptorStruct.mchStraps.padding[776] = 0xff; +- descriptorStruct.mchStraps.padding[777] = 0xff; +- descriptorStruct.mchStraps.padding[778] = 0xff; +- descriptorStruct.mchStraps.padding[779] = 0xff; +- descriptorStruct.mchStraps.padding[780] = 0xff; +- descriptorStruct.mchStraps.padding[781] = 0xff; +- descriptorStruct.mchStraps.padding[782] = 0xff; +- descriptorStruct.mchStraps.padding[783] = 0xff; +- descriptorStruct.mchStraps.padding[784] = 0xff; +- descriptorStruct.mchStraps.padding[785] = 0xff; +- descriptorStruct.mchStraps.padding[786] = 0xff; +- descriptorStruct.mchStraps.padding[787] = 0xff; +- descriptorStruct.mchStraps.padding[788] = 0xff; +- descriptorStruct.mchStraps.padding[789] = 0xff; +- descriptorStruct.mchStraps.padding[790] = 0xff; +- descriptorStruct.mchStraps.padding[791] = 0xff; +- descriptorStruct.mchStraps.padding[792] = 0xff; +- descriptorStruct.mchStraps.padding[793] = 0xff; +- descriptorStruct.mchStraps.padding[794] = 0xff; +- descriptorStruct.mchStraps.padding[795] = 0xff; +- descriptorStruct.mchStraps.padding[796] = 0xff; +- descriptorStruct.mchStraps.padding[797] = 0xff; +- descriptorStruct.mchStraps.padding[798] = 0xff; +- descriptorStruct.mchStraps.padding[799] = 0xff; +- descriptorStruct.mchStraps.padding[800] = 0xff; +- descriptorStruct.mchStraps.padding[801] = 0xff; +- descriptorStruct.mchStraps.padding[802] = 0xff; +- descriptorStruct.mchStraps.padding[803] = 0xff; +- descriptorStruct.mchStraps.padding[804] = 0xff; +- descriptorStruct.mchStraps.padding[805] = 0xff; +- descriptorStruct.mchStraps.padding[806] = 0xff; +- descriptorStruct.mchStraps.padding[807] = 0xff; +- descriptorStruct.mchStraps.padding[808] = 0xff; +- descriptorStruct.mchStraps.padding[809] = 0xff; +- descriptorStruct.mchStraps.padding[810] = 0xff; +- descriptorStruct.mchStraps.padding[811] = 0xff; +- descriptorStruct.mchStraps.padding[812] = 0xff; +- descriptorStruct.mchStraps.padding[813] = 0xff; +- descriptorStruct.mchStraps.padding[814] = 0xff; +- descriptorStruct.mchStraps.padding[815] = 0xff; +- descriptorStruct.mchStraps.padding[816] = 0xff; +- descriptorStruct.mchStraps.padding[817] = 0xff; +- descriptorStruct.mchStraps.padding[818] = 0xff; +- descriptorStruct.mchStraps.padding[819] = 0xff; +- descriptorStruct.mchStraps.padding[820] = 0xff; +- descriptorStruct.mchStraps.padding[821] = 0xff; +- descriptorStruct.mchStraps.padding[822] = 0xff; +- descriptorStruct.mchStraps.padding[823] = 0xff; +- descriptorStruct.mchStraps.padding[824] = 0xff; +- descriptorStruct.mchStraps.padding[825] = 0xff; +- descriptorStruct.mchStraps.padding[826] = 0xff; +- descriptorStruct.mchStraps.padding[827] = 0xff; +- descriptorStruct.mchStraps.padding[828] = 0xff; +- descriptorStruct.mchStraps.padding[829] = 0xff; +- descriptorStruct.mchStraps.padding[830] = 0xff; +- descriptorStruct.mchStraps.padding[831] = 0xff; +- descriptorStruct.mchStraps.padding[832] = 0xff; +- descriptorStruct.mchStraps.padding[833] = 0xff; +- descriptorStruct.mchStraps.padding[834] = 0xff; +- descriptorStruct.mchStraps.padding[835] = 0xff; +- descriptorStruct.mchStraps.padding[836] = 0xff; +- descriptorStruct.mchStraps.padding[837] = 0xff; +- descriptorStruct.mchStraps.padding[838] = 0xff; +- descriptorStruct.mchStraps.padding[839] = 0xff; +- descriptorStruct.mchStraps.padding[840] = 0xff; +- descriptorStruct.mchStraps.padding[841] = 0xff; +- descriptorStruct.mchStraps.padding[842] = 0xff; +- descriptorStruct.mchStraps.padding[843] = 0xff; +- descriptorStruct.mchStraps.padding[844] = 0xff; +- descriptorStruct.mchStraps.padding[845] = 0xff; +- descriptorStruct.mchStraps.padding[846] = 0xff; +- descriptorStruct.mchStraps.padding[847] = 0xff; +- descriptorStruct.mchStraps.padding[848] = 0xff; +- descriptorStruct.mchStraps.padding[849] = 0xff; +- descriptorStruct.mchStraps.padding[850] = 0xff; +- descriptorStruct.mchStraps.padding[851] = 0xff; +- descriptorStruct.mchStraps.padding[852] = 0xff; +- descriptorStruct.mchStraps.padding[853] = 0xff; +- descriptorStruct.mchStraps.padding[854] = 0xff; +- descriptorStruct.mchStraps.padding[855] = 0xff; +- descriptorStruct.mchStraps.padding[856] = 0xff; +- descriptorStruct.mchStraps.padding[857] = 0xff; +- descriptorStruct.mchStraps.padding[858] = 0xff; +- descriptorStruct.mchStraps.padding[859] = 0xff; +- descriptorStruct.mchStraps.padding[860] = 0xff; +- descriptorStruct.mchStraps.padding[861] = 0xff; +- descriptorStruct.mchStraps.padding[862] = 0xff; +- descriptorStruct.mchStraps.padding[863] = 0xff; +- descriptorStruct.mchStraps.padding[864] = 0xff; +- descriptorStruct.mchStraps.padding[865] = 0xff; +- descriptorStruct.mchStraps.padding[866] = 0xff; +- descriptorStruct.mchStraps.padding[867] = 0xff; +- descriptorStruct.mchStraps.padding[868] = 0xff; +- descriptorStruct.mchStraps.padding[869] = 0xff; +- descriptorStruct.mchStraps.padding[870] = 0xff; +- descriptorStruct.mchStraps.padding[871] = 0xff; +- descriptorStruct.mchStraps.padding[872] = 0xff; +- descriptorStruct.mchStraps.padding[873] = 0xff; +- descriptorStruct.mchStraps.padding[874] = 0xff; +- descriptorStruct.mchStraps.padding[875] = 0xff; +- descriptorStruct.mchStraps.padding[876] = 0xff; +- descriptorStruct.mchStraps.padding[877] = 0xff; +- descriptorStruct.mchStraps.padding[878] = 0xff; +- descriptorStruct.mchStraps.padding[879] = 0xff; +- descriptorStruct.mchStraps.padding[880] = 0xff; +- descriptorStruct.mchStraps.padding[881] = 0xff; +- descriptorStruct.mchStraps.padding[882] = 0xff; +- descriptorStruct.mchStraps.padding[883] = 0xff; +- descriptorStruct.mchStraps.padding[884] = 0xff; +- descriptorStruct.mchStraps.padding[885] = 0xff; +- descriptorStruct.mchStraps.padding[886] = 0xff; +- descriptorStruct.mchStraps.padding[887] = 0xff; +- descriptorStruct.mchStraps.padding[888] = 0xff; +- descriptorStruct.mchStraps.padding[889] = 0xff; +- descriptorStruct.mchStraps.padding[890] = 0xff; +- descriptorStruct.mchStraps.padding[891] = 0xff; +- descriptorStruct.mchStraps.padding[892] = 0xff; +- descriptorStruct.mchStraps.padding[893] = 0xff; +- descriptorStruct.mchStraps.padding[894] = 0xff; +- descriptorStruct.mchStraps.padding[895] = 0xff; +- descriptorStruct.mchStraps.padding[896] = 0xff; +- descriptorStruct.mchStraps.padding[897] = 0xff; +- descriptorStruct.mchStraps.padding[898] = 0xff; +- descriptorStruct.mchStraps.padding[899] = 0xff; +- descriptorStruct.mchStraps.padding[900] = 0xff; +- descriptorStruct.mchStraps.padding[901] = 0xff; +- descriptorStruct.mchStraps.padding[902] = 0xff; +- descriptorStruct.mchStraps.padding[903] = 0xff; +- descriptorStruct.mchStraps.padding[904] = 0xff; +- descriptorStruct.mchStraps.padding[905] = 0xff; +- descriptorStruct.mchStraps.padding[906] = 0xff; +- descriptorStruct.mchStraps.padding[907] = 0xff; +- descriptorStruct.mchStraps.padding[908] = 0xff; +- descriptorStruct.mchStraps.padding[909] = 0xff; +- descriptorStruct.mchStraps.padding[910] = 0xff; +- descriptorStruct.mchStraps.padding[911] = 0xff; +- descriptorStruct.mchStraps.padding[912] = 0xff; +- descriptorStruct.mchStraps.padding[913] = 0xff; +- descriptorStruct.mchStraps.padding[914] = 0xff; +- descriptorStruct.mchStraps.padding[915] = 0xff; +- descriptorStruct.mchStraps.padding[916] = 0xff; +- descriptorStruct.mchStraps.padding[917] = 0xff; +- descriptorStruct.mchStraps.padding[918] = 0xff; +- descriptorStruct.mchStraps.padding[919] = 0xff; +- descriptorStruct.mchStraps.padding[920] = 0xff; +- descriptorStruct.mchStraps.padding[921] = 0xff; +- descriptorStruct.mchStraps.padding[922] = 0xff; +- descriptorStruct.mchStraps.padding[923] = 0xff; +- descriptorStruct.mchStraps.padding[924] = 0xff; +- descriptorStruct.mchStraps.padding[925] = 0xff; +- descriptorStruct.mchStraps.padding[926] = 0xff; +- descriptorStruct.mchStraps.padding[927] = 0xff; +- descriptorStruct.mchStraps.padding[928] = 0xff; +- descriptorStruct.mchStraps.padding[929] = 0xff; +- descriptorStruct.mchStraps.padding[930] = 0xff; +- descriptorStruct.mchStraps.padding[931] = 0xff; +- descriptorStruct.mchStraps.padding[932] = 0xff; +- descriptorStruct.mchStraps.padding[933] = 0xff; +- descriptorStruct.mchStraps.padding[934] = 0xff; +- descriptorStruct.mchStraps.padding[935] = 0xff; +- descriptorStruct.mchStraps.padding[936] = 0xff; +- descriptorStruct.mchStraps.padding[937] = 0xff; +- descriptorStruct.mchStraps.padding[938] = 0xff; +- descriptorStruct.mchStraps.padding[939] = 0xff; +- descriptorStruct.mchStraps.padding[940] = 0xff; +- descriptorStruct.mchStraps.padding[941] = 0xff; +- descriptorStruct.mchStraps.padding[942] = 0xff; +- descriptorStruct.mchStraps.padding[943] = 0xff; +- descriptorStruct.mchStraps.padding[944] = 0xff; +- descriptorStruct.mchStraps.padding[945] = 0xff; +- descriptorStruct.mchStraps.padding[946] = 0xff; +- descriptorStruct.mchStraps.padding[947] = 0xff; +- descriptorStruct.mchStraps.padding[948] = 0xff; +- descriptorStruct.mchStraps.padding[949] = 0xff; +- descriptorStruct.mchStraps.padding[950] = 0xff; +- descriptorStruct.mchStraps.padding[951] = 0xff; +- descriptorStruct.mchStraps.padding[952] = 0xff; +- descriptorStruct.mchStraps.padding[953] = 0xff; +- descriptorStruct.mchStraps.padding[954] = 0xff; +- descriptorStruct.mchStraps.padding[955] = 0xff; +- descriptorStruct.mchStraps.padding[956] = 0xff; +- descriptorStruct.mchStraps.padding[957] = 0xff; +- descriptorStruct.mchStraps.padding[958] = 0xff; +- descriptorStruct.mchStraps.padding[959] = 0xff; +- descriptorStruct.mchStraps.padding[960] = 0xff; +- descriptorStruct.mchStraps.padding[961] = 0xff; +- descriptorStruct.mchStraps.padding[962] = 0xff; +- descriptorStruct.mchStraps.padding[963] = 0xff; +- descriptorStruct.mchStraps.padding[964] = 0xff; +- descriptorStruct.mchStraps.padding[965] = 0xff; +- descriptorStruct.mchStraps.padding[966] = 0xff; +- descriptorStruct.mchStraps.padding[967] = 0xff; +- descriptorStruct.mchStraps.padding[968] = 0xff; +- descriptorStruct.mchStraps.padding[969] = 0xff; +- descriptorStruct.mchStraps.padding[970] = 0xff; +- descriptorStruct.mchStraps.padding[971] = 0xff; +- descriptorStruct.mchStraps.padding[972] = 0xff; +- descriptorStruct.mchStraps.padding[973] = 0xff; +- descriptorStruct.mchStraps.padding[974] = 0xff; +- descriptorStruct.mchStraps.padding[975] = 0xff; +- descriptorStruct.mchStraps.padding[976] = 0xff; +- descriptorStruct.mchStraps.padding[977] = 0xff; +- descriptorStruct.mchStraps.padding[978] = 0xff; +- descriptorStruct.mchStraps.padding[979] = 0xff; +- descriptorStruct.mchStraps.padding[980] = 0xff; +- descriptorStruct.mchStraps.padding[981] = 0xff; +- descriptorStruct.mchStraps.padding[982] = 0xff; +- descriptorStruct.mchStraps.padding[983] = 0xff; +- descriptorStruct.mchStraps.padding[984] = 0xff; +- descriptorStruct.mchStraps.padding[985] = 0xff; +- descriptorStruct.mchStraps.padding[986] = 0xff; +- descriptorStruct.mchStraps.padding[987] = 0xff; +- descriptorStruct.mchStraps.padding[988] = 0xff; +- descriptorStruct.mchStraps.padding[989] = 0xff; +- descriptorStruct.mchStraps.padding[990] = 0xff; +- descriptorStruct.mchStraps.padding[991] = 0xff; +- descriptorStruct.mchStraps.padding[992] = 0xff; +- descriptorStruct.mchStraps.padding[993] = 0xff; +- descriptorStruct.mchStraps.padding[994] = 0xff; +- descriptorStruct.mchStraps.padding[995] = 0xff; +- descriptorStruct.mchStraps.padding[996] = 0xff; +- descriptorStruct.mchStraps.padding[997] = 0xff; +- descriptorStruct.mchStraps.padding[998] = 0xff; +- descriptorStruct.mchStraps.padding[999] = 0xff; +- descriptorStruct.mchStraps.padding[1000] = 0xff; +- descriptorStruct.mchStraps.padding[1001] = 0xff; +- descriptorStruct.mchStraps.padding[1002] = 0xff; +- descriptorStruct.mchStraps.padding[1003] = 0xff; +- descriptorStruct.mchStraps.padding[1004] = 0xff; +- descriptorStruct.mchStraps.padding[1005] = 0xff; +- descriptorStruct.mchStraps.padding[1006] = 0xff; +- descriptorStruct.mchStraps.padding[1007] = 0xff; +- descriptorStruct.mchStraps.padding[1008] = 0xff; +- descriptorStruct.mchStraps.padding[1009] = 0xff; +- descriptorStruct.mchStraps.padding[1010] = 0xff; +- descriptorStruct.mchStraps.padding[1011] = 0xff; +- descriptorStruct.mchStraps.padding[1012] = 0xff; +- descriptorStruct.mchStraps.padding[1013] = 0xff; +- descriptorStruct.mchStraps.padding[1014] = 0xff; +- descriptorStruct.mchStraps.padding[1015] = 0xff; +- descriptorStruct.mchStraps.padding[1016] = 0xff; +- descriptorStruct.mchStraps.padding[1017] = 0xff; +- descriptorStruct.mchStraps.padding[1018] = 0xff; +- descriptorStruct.mchStraps.padding[1019] = 0xff; +- descriptorStruct.mchStraps.padding[1020] = 0xff; +- descriptorStruct.mchStraps.padding[1021] = 0xff; +- descriptorStruct.mchStraps.padding[1022] = 0xff; +- descriptorStruct.mchStraps.padding[1023] = 0xff; +- descriptorStruct.mchStraps.padding[1024] = 0xff; +- descriptorStruct.mchStraps.padding[1025] = 0xff; +- descriptorStruct.mchStraps.padding[1026] = 0xff; +- descriptorStruct.mchStraps.padding[1027] = 0xff; +- descriptorStruct.mchStraps.padding[1028] = 0xff; +- descriptorStruct.mchStraps.padding[1029] = 0xff; +- descriptorStruct.mchStraps.padding[1030] = 0xff; +- descriptorStruct.mchStraps.padding[1031] = 0xff; +- descriptorStruct.mchStraps.padding[1032] = 0xff; +- descriptorStruct.mchStraps.padding[1033] = 0xff; +- descriptorStruct.mchStraps.padding[1034] = 0xff; +- descriptorStruct.mchStraps.padding[1035] = 0xff; +- descriptorStruct.mchStraps.padding[1036] = 0xff; +- descriptorStruct.mchStraps.padding[1037] = 0xff; +- descriptorStruct.mchStraps.padding[1038] = 0xff; +- descriptorStruct.mchStraps.padding[1039] = 0xff; +- descriptorStruct.mchStraps.padding[1040] = 0xff; +- descriptorStruct.mchStraps.padding[1041] = 0xff; +- descriptorStruct.mchStraps.padding[1042] = 0xff; +- descriptorStruct.mchStraps.padding[1043] = 0xff; +- descriptorStruct.mchStraps.padding[1044] = 0xff; +- descriptorStruct.mchStraps.padding[1045] = 0xff; +- descriptorStruct.mchStraps.padding[1046] = 0xff; +- descriptorStruct.mchStraps.padding[1047] = 0xff; +- descriptorStruct.mchStraps.padding[1048] = 0xff; +- descriptorStruct.mchStraps.padding[1049] = 0xff; +- descriptorStruct.mchStraps.padding[1050] = 0xff; +- descriptorStruct.mchStraps.padding[1051] = 0xff; +- descriptorStruct.mchStraps.padding[1052] = 0xff; +- descriptorStruct.mchStraps.padding[1053] = 0xff; +- descriptorStruct.mchStraps.padding[1054] = 0xff; +- descriptorStruct.mchStraps.padding[1055] = 0xff; +- descriptorStruct.mchStraps.padding[1056] = 0xff; +- descriptorStruct.mchStraps.padding[1057] = 0xff; +- descriptorStruct.mchStraps.padding[1058] = 0xff; +- descriptorStruct.mchStraps.padding[1059] = 0xff; +- descriptorStruct.mchStraps.padding[1060] = 0xff; +- descriptorStruct.mchStraps.padding[1061] = 0xff; +- descriptorStruct.mchStraps.padding[1062] = 0xff; +- descriptorStruct.mchStraps.padding[1063] = 0xff; +- descriptorStruct.mchStraps.padding[1064] = 0xff; +- descriptorStruct.mchStraps.padding[1065] = 0xff; +- descriptorStruct.mchStraps.padding[1066] = 0xff; +- descriptorStruct.mchStraps.padding[1067] = 0xff; +- descriptorStruct.mchStraps.padding[1068] = 0xff; +- descriptorStruct.mchStraps.padding[1069] = 0xff; +- descriptorStruct.mchStraps.padding[1070] = 0xff; +- descriptorStruct.mchStraps.padding[1071] = 0xff; +- descriptorStruct.mchStraps.padding[1072] = 0xff; +- descriptorStruct.mchStraps.padding[1073] = 0xff; +- descriptorStruct.mchStraps.padding[1074] = 0xff; +- descriptorStruct.mchStraps.padding[1075] = 0xff; +- descriptorStruct.mchStraps.padding[1076] = 0xff; +- descriptorStruct.mchStraps.padding[1077] = 0xff; +- descriptorStruct.mchStraps.padding[1078] = 0xff; +- descriptorStruct.mchStraps.padding[1079] = 0xff; +- descriptorStruct.mchStraps.padding[1080] = 0xff; +- descriptorStruct.mchStraps.padding[1081] = 0xff; +- descriptorStruct.mchStraps.padding[1082] = 0xff; +- descriptorStruct.mchStraps.padding[1083] = 0xff; +- descriptorStruct.mchStraps.padding[1084] = 0xff; +- descriptorStruct.mchStraps.padding[1085] = 0xff; +- descriptorStruct.mchStraps.padding[1086] = 0xff; +- descriptorStruct.mchStraps.padding[1087] = 0xff; +- descriptorStruct.mchStraps.padding[1088] = 0xff; +- descriptorStruct.mchStraps.padding[1089] = 0xff; +- descriptorStruct.mchStraps.padding[1090] = 0xff; +- descriptorStruct.mchStraps.padding[1091] = 0xff; +- descriptorStruct.mchStraps.padding[1092] = 0xff; +- descriptorStruct.mchStraps.padding[1093] = 0xff; +- descriptorStruct.mchStraps.padding[1094] = 0xff; +- descriptorStruct.mchStraps.padding[1095] = 0xff; +- descriptorStruct.mchStraps.padding[1096] = 0xff; +- descriptorStruct.mchStraps.padding[1097] = 0xff; +- descriptorStruct.mchStraps.padding[1098] = 0xff; +- descriptorStruct.mchStraps.padding[1099] = 0xff; +- descriptorStruct.mchStraps.padding[1100] = 0xff; +- descriptorStruct.mchStraps.padding[1101] = 0xff; +- descriptorStruct.mchStraps.padding[1102] = 0xff; +- descriptorStruct.mchStraps.padding[1103] = 0xff; +- descriptorStruct.mchStraps.padding[1104] = 0xff; +- descriptorStruct.mchStraps.padding[1105] = 0xff; +- descriptorStruct.mchStraps.padding[1106] = 0xff; +- descriptorStruct.mchStraps.padding[1107] = 0xff; +- descriptorStruct.mchStraps.padding[1108] = 0xff; +- descriptorStruct.mchStraps.padding[1109] = 0xff; +- descriptorStruct.mchStraps.padding[1110] = 0xff; +- descriptorStruct.mchStraps.padding[1111] = 0xff; +- descriptorStruct.mchStraps.padding[1112] = 0xff; +- descriptorStruct.mchStraps.padding[1113] = 0xff; +- descriptorStruct.mchStraps.padding[1114] = 0xff; +- descriptorStruct.mchStraps.padding[1115] = 0xff; +- descriptorStruct.mchStraps.padding[1116] = 0xff; +- descriptorStruct.mchStraps.padding[1117] = 0xff; +- descriptorStruct.mchStraps.padding[1118] = 0xff; +- descriptorStruct.mchStraps.padding[1119] = 0xff; +- descriptorStruct.mchStraps.padding[1120] = 0xff; +- descriptorStruct.mchStraps.padding[1121] = 0xff; +- descriptorStruct.mchStraps.padding[1122] = 0xff; +- descriptorStruct.mchStraps.padding[1123] = 0xff; +- descriptorStruct.mchStraps.padding[1124] = 0xff; +- descriptorStruct.mchStraps.padding[1125] = 0xff; +- descriptorStruct.mchStraps.padding[1126] = 0xff; +- descriptorStruct.mchStraps.padding[1127] = 0xff; +- descriptorStruct.mchStraps.padding[1128] = 0xff; +- descriptorStruct.mchStraps.padding[1129] = 0xff; +- descriptorStruct.mchStraps.padding[1130] = 0xff; +- descriptorStruct.mchStraps.padding[1131] = 0xff; +- descriptorStruct.mchStraps.padding[1132] = 0xff; +- descriptorStruct.mchStraps.padding[1133] = 0xff; +- descriptorStruct.mchStraps.padding[1134] = 0xff; +- descriptorStruct.mchStraps.padding[1135] = 0xff; +- descriptorStruct.mchStraps.padding[1136] = 0xff; +- descriptorStruct.mchStraps.padding[1137] = 0xff; +- descriptorStruct.mchStraps.padding[1138] = 0xff; +- descriptorStruct.mchStraps.padding[1139] = 0xff; +- descriptorStruct.mchStraps.padding[1140] = 0xff; +- descriptorStruct.mchStraps.padding[1141] = 0xff; +- descriptorStruct.mchStraps.padding[1142] = 0xff; +- descriptorStruct.mchStraps.padding[1143] = 0xff; +- descriptorStruct.mchStraps.padding[1144] = 0xff; +- descriptorStruct.mchStraps.padding[1145] = 0xff; +- descriptorStruct.mchStraps.padding[1146] = 0xff; +- descriptorStruct.mchStraps.padding[1147] = 0xff; +- descriptorStruct.mchStraps.padding[1148] = 0xff; +- descriptorStruct.mchStraps.padding[1149] = 0xff; +- descriptorStruct.mchStraps.padding[1150] = 0xff; +- descriptorStruct.mchStraps.padding[1151] = 0xff; +- descriptorStruct.mchStraps.padding[1152] = 0xff; +- descriptorStruct.mchStraps.padding[1153] = 0xff; +- descriptorStruct.mchStraps.padding[1154] = 0xff; +- descriptorStruct.mchStraps.padding[1155] = 0xff; +- descriptorStruct.mchStraps.padding[1156] = 0xff; +- descriptorStruct.mchStraps.padding[1157] = 0xff; +- descriptorStruct.mchStraps.padding[1158] = 0xff; +- descriptorStruct.mchStraps.padding[1159] = 0xff; +- descriptorStruct.mchStraps.padding[1160] = 0xff; +- descriptorStruct.mchStraps.padding[1161] = 0xff; +- descriptorStruct.mchStraps.padding[1162] = 0xff; +- descriptorStruct.mchStraps.padding[1163] = 0xff; +- descriptorStruct.mchStraps.padding[1164] = 0xff; +- descriptorStruct.mchStraps.padding[1165] = 0xff; +- descriptorStruct.mchStraps.padding[1166] = 0xff; +- descriptorStruct.mchStraps.padding[1167] = 0xff; +- descriptorStruct.mchStraps.padding[1168] = 0xff; +- descriptorStruct.mchStraps.padding[1169] = 0xff; +- descriptorStruct.mchStraps.padding[1170] = 0xff; +- descriptorStruct.mchStraps.padding[1171] = 0xff; +- descriptorStruct.mchStraps.padding[1172] = 0xff; +- descriptorStruct.mchStraps.padding[1173] = 0xff; +- descriptorStruct.mchStraps.padding[1174] = 0xff; +- descriptorStruct.mchStraps.padding[1175] = 0xff; +- descriptorStruct.mchStraps.padding[1176] = 0xff; +- descriptorStruct.mchStraps.padding[1177] = 0xff; +- descriptorStruct.mchStraps.padding[1178] = 0xff; +- descriptorStruct.mchStraps.padding[1179] = 0xff; +- descriptorStruct.mchStraps.padding[1180] = 0xff; +- descriptorStruct.mchStraps.padding[1181] = 0xff; +- descriptorStruct.mchStraps.padding[1182] = 0xff; +- descriptorStruct.mchStraps.padding[1183] = 0xff; +- descriptorStruct.mchStraps.padding[1184] = 0xff; +- descriptorStruct.mchStraps.padding[1185] = 0xff; +- descriptorStruct.mchStraps.padding[1186] = 0xff; +- descriptorStruct.mchStraps.padding[1187] = 0xff; +- descriptorStruct.mchStraps.padding[1188] = 0xff; +- descriptorStruct.mchStraps.padding[1189] = 0xff; +- descriptorStruct.mchStraps.padding[1190] = 0xff; +- descriptorStruct.mchStraps.padding[1191] = 0xff; +- descriptorStruct.mchStraps.padding[1192] = 0xff; +- descriptorStruct.mchStraps.padding[1193] = 0xff; +- descriptorStruct.mchStraps.padding[1194] = 0xff; +- descriptorStruct.mchStraps.padding[1195] = 0xff; +- descriptorStruct.mchStraps.padding[1196] = 0xff; +- descriptorStruct.mchStraps.padding[1197] = 0xff; +- descriptorStruct.mchStraps.padding[1198] = 0xff; +- descriptorStruct.mchStraps.padding[1199] = 0xff; +- descriptorStruct.mchStraps.padding[1200] = 0xff; +- descriptorStruct.mchStraps.padding[1201] = 0xff; +- descriptorStruct.mchStraps.padding[1202] = 0xff; +- descriptorStruct.mchStraps.padding[1203] = 0xff; +- descriptorStruct.mchStraps.padding[1204] = 0xff; +- descriptorStruct.mchStraps.padding[1205] = 0xff; +- descriptorStruct.mchStraps.padding[1206] = 0xff; +- descriptorStruct.mchStraps.padding[1207] = 0xff; +- descriptorStruct.mchStraps.padding[1208] = 0xff; +- descriptorStruct.mchStraps.padding[1209] = 0xff; +- descriptorStruct.mchStraps.padding[1210] = 0xff; +- descriptorStruct.mchStraps.padding[1211] = 0xff; +- descriptorStruct.mchStraps.padding[1212] = 0xff; +- descriptorStruct.mchStraps.padding[1213] = 0xff; +- descriptorStruct.mchStraps.padding[1214] = 0xff; +- descriptorStruct.mchStraps.padding[1215] = 0xff; +- descriptorStruct.mchStraps.padding[1216] = 0xff; +- descriptorStruct.mchStraps.padding[1217] = 0xff; +- descriptorStruct.mchStraps.padding[1218] = 0xff; +- descriptorStruct.mchStraps.padding[1219] = 0xff; +- descriptorStruct.mchStraps.padding[1220] = 0xff; +- descriptorStruct.mchStraps.padding[1221] = 0xff; +- descriptorStruct.mchStraps.padding[1222] = 0xff; +- descriptorStruct.mchStraps.padding[1223] = 0xff; +- descriptorStruct.mchStraps.padding[1224] = 0xff; +- descriptorStruct.mchStraps.padding[1225] = 0xff; +- descriptorStruct.mchStraps.padding[1226] = 0xff; +- descriptorStruct.mchStraps.padding[1227] = 0xff; +- descriptorStruct.mchStraps.padding[1228] = 0xff; +- descriptorStruct.mchStraps.padding[1229] = 0xff; +- descriptorStruct.mchStraps.padding[1230] = 0xff; +- descriptorStruct.mchStraps.padding[1231] = 0xff; +- descriptorStruct.mchStraps.padding[1232] = 0xff; +- descriptorStruct.mchStraps.padding[1233] = 0xff; +- descriptorStruct.mchStraps.padding[1234] = 0xff; +- descriptorStruct.mchStraps.padding[1235] = 0xff; +- descriptorStruct.mchStraps.padding[1236] = 0xff; +- descriptorStruct.mchStraps.padding[1237] = 0xff; +- descriptorStruct.mchStraps.padding[1238] = 0xff; +- descriptorStruct.mchStraps.padding[1239] = 0xff; +- descriptorStruct.mchStraps.padding[1240] = 0xff; +- descriptorStruct.mchStraps.padding[1241] = 0xff; +- descriptorStruct.mchStraps.padding[1242] = 0xff; +- descriptorStruct.mchStraps.padding[1243] = 0xff; +- descriptorStruct.mchStraps.padding[1244] = 0xff; +- descriptorStruct.mchStraps.padding[1245] = 0xff; +- descriptorStruct.mchStraps.padding[1246] = 0xff; +- descriptorStruct.mchStraps.padding[1247] = 0xff; +- descriptorStruct.mchStraps.padding[1248] = 0xff; +- descriptorStruct.mchStraps.padding[1249] = 0xff; +- descriptorStruct.mchStraps.padding[1250] = 0xff; +- descriptorStruct.mchStraps.padding[1251] = 0xff; +- descriptorStruct.mchStraps.padding[1252] = 0xff; +- descriptorStruct.mchStraps.padding[1253] = 0xff; +- descriptorStruct.mchStraps.padding[1254] = 0xff; +- descriptorStruct.mchStraps.padding[1255] = 0xff; +- descriptorStruct.mchStraps.padding[1256] = 0xff; +- descriptorStruct.mchStraps.padding[1257] = 0xff; +- descriptorStruct.mchStraps.padding[1258] = 0xff; +- descriptorStruct.mchStraps.padding[1259] = 0xff; +- descriptorStruct.mchStraps.padding[1260] = 0xff; +- descriptorStruct.mchStraps.padding[1261] = 0xff; +- descriptorStruct.mchStraps.padding[1262] = 0xff; +- descriptorStruct.mchStraps.padding[1263] = 0xff; +- descriptorStruct.mchStraps.padding[1264] = 0xff; +- descriptorStruct.mchStraps.padding[1265] = 0xff; +- descriptorStruct.mchStraps.padding[1266] = 0xff; +- descriptorStruct.mchStraps.padding[1267] = 0xff; +- descriptorStruct.mchStraps.padding[1268] = 0xff; +- descriptorStruct.mchStraps.padding[1269] = 0xff; +- descriptorStruct.mchStraps.padding[1270] = 0xff; +- descriptorStruct.mchStraps.padding[1271] = 0xff; +- descriptorStruct.mchStraps.padding[1272] = 0xff; +- descriptorStruct.mchStraps.padding[1273] = 0xff; +- descriptorStruct.mchStraps.padding[1274] = 0xff; +- descriptorStruct.mchStraps.padding[1275] = 0xff; +- descriptorStruct.mchStraps.padding[1276] = 0xff; +- descriptorStruct.mchStraps.padding[1277] = 0xff; +- descriptorStruct.mchStraps.padding[1278] = 0xff; +- descriptorStruct.mchStraps.padding[1279] = 0xff; +- descriptorStruct.mchStraps.padding[1280] = 0xff; +- descriptorStruct.mchStraps.padding[1281] = 0xff; +- descriptorStruct.mchStraps.padding[1282] = 0xff; +- descriptorStruct.mchStraps.padding[1283] = 0xff; +- descriptorStruct.mchStraps.padding[1284] = 0xff; +- descriptorStruct.mchStraps.padding[1285] = 0xff; +- descriptorStruct.mchStraps.padding[1286] = 0xff; +- descriptorStruct.mchStraps.padding[1287] = 0xff; +- descriptorStruct.mchStraps.padding[1288] = 0xff; +- descriptorStruct.mchStraps.padding[1289] = 0xff; +- descriptorStruct.mchStraps.padding[1290] = 0xff; +- descriptorStruct.mchStraps.padding[1291] = 0xff; +- descriptorStruct.mchStraps.padding[1292] = 0xff; +- descriptorStruct.mchStraps.padding[1293] = 0xff; +- descriptorStruct.mchStraps.padding[1294] = 0xff; +- descriptorStruct.mchStraps.padding[1295] = 0xff; +- descriptorStruct.mchStraps.padding[1296] = 0xff; +- descriptorStruct.mchStraps.padding[1297] = 0xff; +- descriptorStruct.mchStraps.padding[1298] = 0xff; +- descriptorStruct.mchStraps.padding[1299] = 0xff; +- descriptorStruct.mchStraps.padding[1300] = 0xff; +- descriptorStruct.mchStraps.padding[1301] = 0xff; +- descriptorStruct.mchStraps.padding[1302] = 0xff; +- descriptorStruct.mchStraps.padding[1303] = 0xff; +- descriptorStruct.mchStraps.padding[1304] = 0xff; +- descriptorStruct.mchStraps.padding[1305] = 0xff; +- descriptorStruct.mchStraps.padding[1306] = 0xff; +- descriptorStruct.mchStraps.padding[1307] = 0xff; +- descriptorStruct.mchStraps.padding[1308] = 0xff; +- descriptorStruct.mchStraps.padding[1309] = 0xff; +- descriptorStruct.mchStraps.padding[1310] = 0xff; +- descriptorStruct.mchStraps.padding[1311] = 0xff; +- descriptorStruct.mchStraps.padding[1312] = 0xff; +- descriptorStruct.mchStraps.padding[1313] = 0xff; +- descriptorStruct.mchStraps.padding[1314] = 0xff; +- descriptorStruct.mchStraps.padding[1315] = 0xff; +- descriptorStruct.mchStraps.padding[1316] = 0xff; +- descriptorStruct.mchStraps.padding[1317] = 0xff; +- descriptorStruct.mchStraps.padding[1318] = 0xff; +- descriptorStruct.mchStraps.padding[1319] = 0xff; +- descriptorStruct.mchStraps.padding[1320] = 0xff; +- descriptorStruct.mchStraps.padding[1321] = 0xff; +- descriptorStruct.mchStraps.padding[1322] = 0xff; +- descriptorStruct.mchStraps.padding[1323] = 0xff; +- descriptorStruct.mchStraps.padding[1324] = 0xff; +- descriptorStruct.mchStraps.padding[1325] = 0xff; +- descriptorStruct.mchStraps.padding[1326] = 0xff; +- descriptorStruct.mchStraps.padding[1327] = 0xff; +- descriptorStruct.mchStraps.padding[1328] = 0xff; +- descriptorStruct.mchStraps.padding[1329] = 0xff; +- descriptorStruct.mchStraps.padding[1330] = 0xff; +- descriptorStruct.mchStraps.padding[1331] = 0xff; +- descriptorStruct.mchStraps.padding[1332] = 0xff; +- descriptorStruct.mchStraps.padding[1333] = 0xff; +- descriptorStruct.mchStraps.padding[1334] = 0xff; +- descriptorStruct.mchStraps.padding[1335] = 0xff; +- descriptorStruct.mchStraps.padding[1336] = 0xff; +- descriptorStruct.mchStraps.padding[1337] = 0xff; +- descriptorStruct.mchStraps.padding[1338] = 0xff; +- descriptorStruct.mchStraps.padding[1339] = 0xff; +- descriptorStruct.mchStraps.padding[1340] = 0xff; +- descriptorStruct.mchStraps.padding[1341] = 0xff; +- descriptorStruct.mchStraps.padding[1342] = 0xff; +- descriptorStruct.mchStraps.padding[1343] = 0xff; +- descriptorStruct.mchStraps.padding[1344] = 0xff; +- descriptorStruct.mchStraps.padding[1345] = 0xff; +- descriptorStruct.mchStraps.padding[1346] = 0xff; +- descriptorStruct.mchStraps.padding[1347] = 0xff; +- descriptorStruct.mchStraps.padding[1348] = 0xff; +- descriptorStruct.mchStraps.padding[1349] = 0xff; +- descriptorStruct.mchStraps.padding[1350] = 0xff; +- descriptorStruct.mchStraps.padding[1351] = 0xff; +- descriptorStruct.mchStraps.padding[1352] = 0xff; +- descriptorStruct.mchStraps.padding[1353] = 0xff; +- descriptorStruct.mchStraps.padding[1354] = 0xff; +- descriptorStruct.mchStraps.padding[1355] = 0xff; +- descriptorStruct.mchStraps.padding[1356] = 0xff; +- descriptorStruct.mchStraps.padding[1357] = 0xff; +- descriptorStruct.mchStraps.padding[1358] = 0xff; +- descriptorStruct.mchStraps.padding[1359] = 0xff; +- descriptorStruct.mchStraps.padding[1360] = 0xff; +- descriptorStruct.mchStraps.padding[1361] = 0xff; +- descriptorStruct.mchStraps.padding[1362] = 0xff; +- descriptorStruct.mchStraps.padding[1363] = 0xff; +- descriptorStruct.mchStraps.padding[1364] = 0xff; +- descriptorStruct.mchStraps.padding[1365] = 0xff; +- descriptorStruct.mchStraps.padding[1366] = 0xff; +- descriptorStruct.mchStraps.padding[1367] = 0xff; +- descriptorStruct.mchStraps.padding[1368] = 0xff; +- descriptorStruct.mchStraps.padding[1369] = 0xff; +- descriptorStruct.mchStraps.padding[1370] = 0xff; +- descriptorStruct.mchStraps.padding[1371] = 0xff; +- descriptorStruct.mchStraps.padding[1372] = 0xff; +- descriptorStruct.mchStraps.padding[1373] = 0xff; +- descriptorStruct.mchStraps.padding[1374] = 0xff; +- descriptorStruct.mchStraps.padding[1375] = 0xff; +- descriptorStruct.mchStraps.padding[1376] = 0xff; +- descriptorStruct.mchStraps.padding[1377] = 0xff; +- descriptorStruct.mchStraps.padding[1378] = 0xff; +- descriptorStruct.mchStraps.padding[1379] = 0xff; +- descriptorStruct.mchStraps.padding[1380] = 0xff; +- descriptorStruct.mchStraps.padding[1381] = 0xff; +- descriptorStruct.mchStraps.padding[1382] = 0xff; +- descriptorStruct.mchStraps.padding[1383] = 0xff; +- descriptorStruct.mchStraps.padding[1384] = 0xff; +- descriptorStruct.mchStraps.padding[1385] = 0xff; +- descriptorStruct.mchStraps.padding[1386] = 0xff; +- descriptorStruct.mchStraps.padding[1387] = 0xff; +- descriptorStruct.mchStraps.padding[1388] = 0xff; +- descriptorStruct.mchStraps.padding[1389] = 0xff; +- descriptorStruct.mchStraps.padding[1390] = 0xff; +- descriptorStruct.mchStraps.padding[1391] = 0xff; +- descriptorStruct.mchStraps.padding[1392] = 0xff; +- descriptorStruct.mchStraps.padding[1393] = 0xff; +- descriptorStruct.mchStraps.padding[1394] = 0xff; +- descriptorStruct.mchStraps.padding[1395] = 0xff; +- descriptorStruct.mchStraps.padding[1396] = 0xff; +- descriptorStruct.mchStraps.padding[1397] = 0xff; +- descriptorStruct.mchStraps.padding[1398] = 0xff; +- descriptorStruct.mchStraps.padding[1399] = 0xff; +- descriptorStruct.mchStraps.padding[1400] = 0xff; +- descriptorStruct.mchStraps.padding[1401] = 0xff; +- descriptorStruct.mchStraps.padding[1402] = 0xff; +- descriptorStruct.mchStraps.padding[1403] = 0xff; +- descriptorStruct.mchStraps.padding[1404] = 0xff; +- descriptorStruct.mchStraps.padding[1405] = 0xff; +- descriptorStruct.mchStraps.padding[1406] = 0xff; +- descriptorStruct.mchStraps.padding[1407] = 0xff; +- descriptorStruct.mchStraps.padding[1408] = 0xff; +- descriptorStruct.mchStraps.padding[1409] = 0xff; +- descriptorStruct.mchStraps.padding[1410] = 0xff; +- descriptorStruct.mchStraps.padding[1411] = 0xff; +- descriptorStruct.mchStraps.padding[1412] = 0xff; +- descriptorStruct.mchStraps.padding[1413] = 0xff; +- descriptorStruct.mchStraps.padding[1414] = 0xff; +- descriptorStruct.mchStraps.padding[1415] = 0xff; +- descriptorStruct.mchStraps.padding[1416] = 0xff; +- descriptorStruct.mchStraps.padding[1417] = 0xff; +- descriptorStruct.mchStraps.padding[1418] = 0xff; +- descriptorStruct.mchStraps.padding[1419] = 0xff; +- descriptorStruct.mchStraps.padding[1420] = 0xff; +- descriptorStruct.mchStraps.padding[1421] = 0xff; +- descriptorStruct.mchStraps.padding[1422] = 0xff; +- descriptorStruct.mchStraps.padding[1423] = 0xff; +- descriptorStruct.mchStraps.padding[1424] = 0xff; +- descriptorStruct.mchStraps.padding[1425] = 0xff; +- descriptorStruct.mchStraps.padding[1426] = 0xff; +- descriptorStruct.mchStraps.padding[1427] = 0xff; +- descriptorStruct.mchStraps.padding[1428] = 0xff; +- descriptorStruct.mchStraps.padding[1429] = 0xff; +- descriptorStruct.mchStraps.padding[1430] = 0xff; +- descriptorStruct.mchStraps.padding[1431] = 0xff; +- descriptorStruct.mchStraps.padding[1432] = 0xff; +- descriptorStruct.mchStraps.padding[1433] = 0xff; +- descriptorStruct.mchStraps.padding[1434] = 0xff; +- descriptorStruct.mchStraps.padding[1435] = 0xff; +- descriptorStruct.mchStraps.padding[1436] = 0xff; +- descriptorStruct.mchStraps.padding[1437] = 0xff; +- descriptorStruct.mchStraps.padding[1438] = 0xff; +- descriptorStruct.mchStraps.padding[1439] = 0xff; +- descriptorStruct.mchStraps.padding[1440] = 0xff; +- descriptorStruct.mchStraps.padding[1441] = 0xff; +- descriptorStruct.mchStraps.padding[1442] = 0xff; +- descriptorStruct.mchStraps.padding[1443] = 0xff; +- descriptorStruct.mchStraps.padding[1444] = 0xff; +- descriptorStruct.mchStraps.padding[1445] = 0xff; +- descriptorStruct.mchStraps.padding[1446] = 0xff; +- descriptorStruct.mchStraps.padding[1447] = 0xff; +- descriptorStruct.mchStraps.padding[1448] = 0xff; +- descriptorStruct.mchStraps.padding[1449] = 0xff; +- descriptorStruct.mchStraps.padding[1450] = 0xff; +- descriptorStruct.mchStraps.padding[1451] = 0xff; +- descriptorStruct.mchStraps.padding[1452] = 0xff; +- descriptorStruct.mchStraps.padding[1453] = 0xff; +- descriptorStruct.mchStraps.padding[1454] = 0xff; +- descriptorStruct.mchStraps.padding[1455] = 0xff; +- descriptorStruct.mchStraps.padding[1456] = 0xff; +- descriptorStruct.mchStraps.padding[1457] = 0xff; +- descriptorStruct.mchStraps.padding[1458] = 0xff; +- descriptorStruct.mchStraps.padding[1459] = 0xff; +- descriptorStruct.mchStraps.padding[1460] = 0xff; +- descriptorStruct.mchStraps.padding[1461] = 0xff; +- descriptorStruct.mchStraps.padding[1462] = 0xff; +- descriptorStruct.mchStraps.padding[1463] = 0xff; +- descriptorStruct.mchStraps.padding[1464] = 0xff; +- descriptorStruct.mchStraps.padding[1465] = 0xff; +- descriptorStruct.mchStraps.padding[1466] = 0xff; +- descriptorStruct.mchStraps.padding[1467] = 0xff; +- descriptorStruct.mchStraps.padding[1468] = 0xff; +- descriptorStruct.mchStraps.padding[1469] = 0xff; +- descriptorStruct.mchStraps.padding[1470] = 0xff; +- descriptorStruct.mchStraps.padding[1471] = 0xff; +- descriptorStruct.mchStraps.padding[1472] = 0xff; +- descriptorStruct.mchStraps.padding[1473] = 0xff; +- descriptorStruct.mchStraps.padding[1474] = 0xff; +- descriptorStruct.mchStraps.padding[1475] = 0xff; +- descriptorStruct.mchStraps.padding[1476] = 0xff; +- descriptorStruct.mchStraps.padding[1477] = 0xff; +- descriptorStruct.mchStraps.padding[1478] = 0xff; +- descriptorStruct.mchStraps.padding[1479] = 0xff; +- descriptorStruct.mchStraps.padding[1480] = 0xff; +- descriptorStruct.mchStraps.padding[1481] = 0xff; +- descriptorStruct.mchStraps.padding[1482] = 0xff; +- descriptorStruct.mchStraps.padding[1483] = 0xff; +- descriptorStruct.mchStraps.padding[1484] = 0xff; +- descriptorStruct.mchStraps.padding[1485] = 0xff; +- descriptorStruct.mchStraps.padding[1486] = 0xff; +- descriptorStruct.mchStraps.padding[1487] = 0xff; +- descriptorStruct.mchStraps.padding[1488] = 0xff; +- descriptorStruct.mchStraps.padding[1489] = 0xff; +- descriptorStruct.mchStraps.padding[1490] = 0xff; +- descriptorStruct.mchStraps.padding[1491] = 0xff; +- descriptorStruct.mchStraps.padding[1492] = 0xff; +- descriptorStruct.mchStraps.padding[1493] = 0xff; +- descriptorStruct.mchStraps.padding[1494] = 0xff; +- descriptorStruct.mchStraps.padding[1495] = 0xff; +- descriptorStruct.mchStraps.padding[1496] = 0xff; +- descriptorStruct.mchStraps.padding[1497] = 0xff; +- descriptorStruct.mchStraps.padding[1498] = 0xff; +- descriptorStruct.mchStraps.padding[1499] = 0xff; +- descriptorStruct.mchStraps.padding[1500] = 0xff; +- descriptorStruct.mchStraps.padding[1501] = 0xff; +- descriptorStruct.mchStraps.padding[1502] = 0xff; +- descriptorStruct.mchStraps.padding[1503] = 0xff; +- descriptorStruct.mchStraps.padding[1504] = 0xff; +- descriptorStruct.mchStraps.padding[1505] = 0xff; +- descriptorStruct.mchStraps.padding[1506] = 0xff; +- descriptorStruct.mchStraps.padding[1507] = 0xff; +- descriptorStruct.mchStraps.padding[1508] = 0xff; +- descriptorStruct.mchStraps.padding[1509] = 0xff; +- descriptorStruct.mchStraps.padding[1510] = 0xff; +- descriptorStruct.mchStraps.padding[1511] = 0xff; +- descriptorStruct.mchStraps.padding[1512] = 0xff; +- descriptorStruct.mchStraps.padding[1513] = 0xff; +- descriptorStruct.mchStraps.padding[1514] = 0xff; +- descriptorStruct.mchStraps.padding[1515] = 0xff; +- descriptorStruct.mchStraps.padding[1516] = 0xff; +- descriptorStruct.mchStraps.padding[1517] = 0xff; +- descriptorStruct.mchStraps.padding[1518] = 0xff; +- descriptorStruct.mchStraps.padding[1519] = 0xff; +- descriptorStruct.mchStraps.padding[1520] = 0xff; +- descriptorStruct.mchStraps.padding[1521] = 0xff; +- descriptorStruct.mchStraps.padding[1522] = 0xff; +- descriptorStruct.mchStraps.padding[1523] = 0xff; +- descriptorStruct.mchStraps.padding[1524] = 0xff; +- descriptorStruct.mchStraps.padding[1525] = 0xff; +- descriptorStruct.mchStraps.padding[1526] = 0xff; +- descriptorStruct.mchStraps.padding[1527] = 0xff; +- descriptorStruct.mchStraps.padding[1528] = 0xff; +- descriptorStruct.mchStraps.padding[1529] = 0xff; +- descriptorStruct.mchStraps.padding[1530] = 0xff; +- descriptorStruct.mchStraps.padding[1531] = 0xff; +- descriptorStruct.mchStraps.padding[1532] = 0xff; +- descriptorStruct.mchStraps.padding[1533] = 0xff; +- descriptorStruct.mchStraps.padding[1534] = 0xff; +- descriptorStruct.mchStraps.padding[1535] = 0xff; +- descriptorStruct.mchStraps.padding[1536] = 0xff; +- descriptorStruct.mchStraps.padding[1537] = 0xff; +- descriptorStruct.mchStraps.padding[1538] = 0xff; +- descriptorStruct.mchStraps.padding[1539] = 0xff; +- descriptorStruct.mchStraps.padding[1540] = 0xff; +- descriptorStruct.mchStraps.padding[1541] = 0xff; +- descriptorStruct.mchStraps.padding[1542] = 0xff; +- descriptorStruct.mchStraps.padding[1543] = 0xff; +- descriptorStruct.mchStraps.padding[1544] = 0xff; +- descriptorStruct.mchStraps.padding[1545] = 0xff; +- descriptorStruct.mchStraps.padding[1546] = 0xff; +- descriptorStruct.mchStraps.padding[1547] = 0xff; +- descriptorStruct.mchStraps.padding[1548] = 0xff; +- descriptorStruct.mchStraps.padding[1549] = 0xff; +- descriptorStruct.mchStraps.padding[1550] = 0xff; +- descriptorStruct.mchStraps.padding[1551] = 0xff; +- descriptorStruct.mchStraps.padding[1552] = 0xff; +- descriptorStruct.mchStraps.padding[1553] = 0xff; +- descriptorStruct.mchStraps.padding[1554] = 0xff; +- descriptorStruct.mchStraps.padding[1555] = 0xff; +- descriptorStruct.mchStraps.padding[1556] = 0xff; +- descriptorStruct.mchStraps.padding[1557] = 0xff; +- descriptorStruct.mchStraps.padding[1558] = 0xff; +- descriptorStruct.mchStraps.padding[1559] = 0xff; +- descriptorStruct.mchStraps.padding[1560] = 0xff; +- descriptorStruct.mchStraps.padding[1561] = 0xff; +- descriptorStruct.mchStraps.padding[1562] = 0xff; +- descriptorStruct.mchStraps.padding[1563] = 0xff; +- descriptorStruct.mchStraps.padding[1564] = 0xff; +- descriptorStruct.mchStraps.padding[1565] = 0xff; +- descriptorStruct.mchStraps.padding[1566] = 0xff; +- descriptorStruct.mchStraps.padding[1567] = 0xff; +- descriptorStruct.mchStraps.padding[1568] = 0xff; +- descriptorStruct.mchStraps.padding[1569] = 0xff; +- descriptorStruct.mchStraps.padding[1570] = 0xff; +- descriptorStruct.mchStraps.padding[1571] = 0xff; +- descriptorStruct.mchStraps.padding[1572] = 0xff; +- descriptorStruct.mchStraps.padding[1573] = 0xff; +- descriptorStruct.mchStraps.padding[1574] = 0xff; +- descriptorStruct.mchStraps.padding[1575] = 0xff; +- descriptorStruct.mchStraps.padding[1576] = 0xff; +- descriptorStruct.mchStraps.padding[1577] = 0xff; +- descriptorStruct.mchStraps.padding[1578] = 0xff; +- descriptorStruct.mchStraps.padding[1579] = 0xff; +- descriptorStruct.mchStraps.padding[1580] = 0xff; +- descriptorStruct.mchStraps.padding[1581] = 0xff; +- descriptorStruct.mchStraps.padding[1582] = 0xff; +- descriptorStruct.mchStraps.padding[1583] = 0xff; +- descriptorStruct.mchStraps.padding[1584] = 0xff; +- descriptorStruct.mchStraps.padding[1585] = 0xff; +- descriptorStruct.mchStraps.padding[1586] = 0xff; +- descriptorStruct.mchStraps.padding[1587] = 0xff; +- descriptorStruct.mchStraps.padding[1588] = 0xff; +- descriptorStruct.mchStraps.padding[1589] = 0xff; +- descriptorStruct.mchStraps.padding[1590] = 0xff; +- descriptorStruct.mchStraps.padding[1591] = 0xff; +- descriptorStruct.mchStraps.padding[1592] = 0xff; +- descriptorStruct.mchStraps.padding[1593] = 0xff; +- descriptorStruct.mchStraps.padding[1594] = 0xff; +- descriptorStruct.mchStraps.padding[1595] = 0xff; +- descriptorStruct.mchStraps.padding[1596] = 0xff; +- descriptorStruct.mchStraps.padding[1597] = 0xff; +- descriptorStruct.mchStraps.padding[1598] = 0xff; +- descriptorStruct.mchStraps.padding[1599] = 0xff; +- descriptorStruct.mchStraps.padding[1600] = 0xff; +- descriptorStruct.mchStraps.padding[1601] = 0xff; +- descriptorStruct.mchStraps.padding[1602] = 0xff; +- descriptorStruct.mchStraps.padding[1603] = 0xff; +- descriptorStruct.mchStraps.padding[1604] = 0xff; +- descriptorStruct.mchStraps.padding[1605] = 0xff; +- descriptorStruct.mchStraps.padding[1606] = 0xff; +- descriptorStruct.mchStraps.padding[1607] = 0xff; +- descriptorStruct.mchStraps.padding[1608] = 0xff; +- descriptorStruct.mchStraps.padding[1609] = 0xff; +- descriptorStruct.mchStraps.padding[1610] = 0xff; +- descriptorStruct.mchStraps.padding[1611] = 0xff; +- descriptorStruct.mchStraps.padding[1612] = 0xff; +- descriptorStruct.mchStraps.padding[1613] = 0xff; +- descriptorStruct.mchStraps.padding[1614] = 0xff; +- descriptorStruct.mchStraps.padding[1615] = 0xff; +- descriptorStruct.mchStraps.padding[1616] = 0xff; +- descriptorStruct.mchStraps.padding[1617] = 0xff; +- descriptorStruct.mchStraps.padding[1618] = 0xff; +- descriptorStruct.mchStraps.padding[1619] = 0xff; +- descriptorStruct.mchStraps.padding[1620] = 0xff; +- descriptorStruct.mchStraps.padding[1621] = 0xff; +- descriptorStruct.mchStraps.padding[1622] = 0xff; +- descriptorStruct.mchStraps.padding[1623] = 0xff; +- descriptorStruct.mchStraps.padding[1624] = 0xff; +- descriptorStruct.mchStraps.padding[1625] = 0xff; +- descriptorStruct.mchStraps.padding[1626] = 0xff; +- descriptorStruct.mchStraps.padding[1627] = 0xff; +- descriptorStruct.mchStraps.padding[1628] = 0xff; +- descriptorStruct.mchStraps.padding[1629] = 0xff; +- descriptorStruct.mchStraps.padding[1630] = 0xff; +- descriptorStruct.mchStraps.padding[1631] = 0xff; +- descriptorStruct.mchStraps.padding[1632] = 0xff; +- descriptorStruct.mchStraps.padding[1633] = 0xff; +- descriptorStruct.mchStraps.padding[1634] = 0xff; +- descriptorStruct.mchStraps.padding[1635] = 0xff; +- descriptorStruct.mchStraps.padding[1636] = 0xff; +- descriptorStruct.mchStraps.padding[1637] = 0xff; +- descriptorStruct.mchStraps.padding[1638] = 0xff; +- descriptorStruct.mchStraps.padding[1639] = 0xff; +- descriptorStruct.mchStraps.padding[1640] = 0xff; +- descriptorStruct.mchStraps.padding[1641] = 0xff; +- descriptorStruct.mchStraps.padding[1642] = 0xff; +- descriptorStruct.mchStraps.padding[1643] = 0xff; +- descriptorStruct.mchStraps.padding[1644] = 0xff; +- descriptorStruct.mchStraps.padding[1645] = 0xff; +- descriptorStruct.mchStraps.padding[1646] = 0xff; +- descriptorStruct.mchStraps.padding[1647] = 0xff; +- descriptorStruct.mchStraps.padding[1648] = 0xff; +- descriptorStruct.mchStraps.padding[1649] = 0xff; +- descriptorStruct.mchStraps.padding[1650] = 0xff; +- descriptorStruct.mchStraps.padding[1651] = 0xff; +- descriptorStruct.mchStraps.padding[1652] = 0xff; +- descriptorStruct.mchStraps.padding[1653] = 0xff; +- descriptorStruct.mchStraps.padding[1654] = 0xff; +- descriptorStruct.mchStraps.padding[1655] = 0xff; +- descriptorStruct.mchStraps.padding[1656] = 0xff; +- descriptorStruct.mchStraps.padding[1657] = 0xff; +- descriptorStruct.mchStraps.padding[1658] = 0xff; +- descriptorStruct.mchStraps.padding[1659] = 0xff; +- descriptorStruct.mchStraps.padding[1660] = 0xff; +- descriptorStruct.mchStraps.padding[1661] = 0xff; +- descriptorStruct.mchStraps.padding[1662] = 0xff; +- descriptorStruct.mchStraps.padding[1663] = 0xff; +- descriptorStruct.mchStraps.padding[1664] = 0xff; +- descriptorStruct.mchStraps.padding[1665] = 0xff; +- descriptorStruct.mchStraps.padding[1666] = 0xff; +- descriptorStruct.mchStraps.padding[1667] = 0xff; +- descriptorStruct.mchStraps.padding[1668] = 0xff; +- descriptorStruct.mchStraps.padding[1669] = 0xff; +- descriptorStruct.mchStraps.padding[1670] = 0xff; +- descriptorStruct.mchStraps.padding[1671] = 0xff; +- descriptorStruct.mchStraps.padding[1672] = 0xff; +- descriptorStruct.mchStraps.padding[1673] = 0xff; +- descriptorStruct.mchStraps.padding[1674] = 0xff; +- descriptorStruct.mchStraps.padding[1675] = 0xff; +- descriptorStruct.mchStraps.padding[1676] = 0xff; +- descriptorStruct.mchStraps.padding[1677] = 0xff; +- descriptorStruct.mchStraps.padding[1678] = 0xff; +- descriptorStruct.mchStraps.padding[1679] = 0xff; +- descriptorStruct.mchStraps.padding[1680] = 0xff; +- descriptorStruct.mchStraps.padding[1681] = 0xff; +- descriptorStruct.mchStraps.padding[1682] = 0xff; +- descriptorStruct.mchStraps.padding[1683] = 0xff; +- descriptorStruct.mchStraps.padding[1684] = 0xff; +- descriptorStruct.mchStraps.padding[1685] = 0xff; +- descriptorStruct.mchStraps.padding[1686] = 0xff; +- descriptorStruct.mchStraps.padding[1687] = 0xff; +- descriptorStruct.mchStraps.padding[1688] = 0xff; +- descriptorStruct.mchStraps.padding[1689] = 0xff; +- descriptorStruct.mchStraps.padding[1690] = 0xff; +- descriptorStruct.mchStraps.padding[1691] = 0xff; +- descriptorStruct.mchStraps.padding[1692] = 0xff; +- descriptorStruct.mchStraps.padding[1693] = 0xff; +- descriptorStruct.mchStraps.padding[1694] = 0xff; +- descriptorStruct.mchStraps.padding[1695] = 0xff; +- descriptorStruct.mchStraps.padding[1696] = 0xff; +- descriptorStruct.mchStraps.padding[1697] = 0xff; +- descriptorStruct.mchStraps.padding[1698] = 0xff; +- descriptorStruct.mchStraps.padding[1699] = 0xff; +- descriptorStruct.mchStraps.padding[1700] = 0xff; +- descriptorStruct.mchStraps.padding[1701] = 0xff; +- descriptorStruct.mchStraps.padding[1702] = 0xff; +- descriptorStruct.mchStraps.padding[1703] = 0xff; +- descriptorStruct.mchStraps.padding[1704] = 0xff; +- descriptorStruct.mchStraps.padding[1705] = 0xff; +- descriptorStruct.mchStraps.padding[1706] = 0xff; +- descriptorStruct.mchStraps.padding[1707] = 0xff; +- descriptorStruct.mchStraps.padding[1708] = 0xff; +- descriptorStruct.mchStraps.padding[1709] = 0xff; +- descriptorStruct.mchStraps.padding[1710] = 0xff; +- descriptorStruct.mchStraps.padding[1711] = 0xff; +- descriptorStruct.mchStraps.padding[1712] = 0xff; +- descriptorStruct.mchStraps.padding[1713] = 0xff; +- descriptorStruct.mchStraps.padding[1714] = 0xff; +- descriptorStruct.mchStraps.padding[1715] = 0xff; +- descriptorStruct.mchStraps.padding[1716] = 0xff; +- descriptorStruct.mchStraps.padding[1717] = 0xff; +- descriptorStruct.mchStraps.padding[1718] = 0xff; +- descriptorStruct.mchStraps.padding[1719] = 0xff; +- descriptorStruct.mchStraps.padding[1720] = 0xff; +- descriptorStruct.mchStraps.padding[1721] = 0xff; +- descriptorStruct.mchStraps.padding[1722] = 0xff; +- descriptorStruct.mchStraps.padding[1723] = 0xff; +- descriptorStruct.mchStraps.padding[1724] = 0xff; +- descriptorStruct.mchStraps.padding[1725] = 0xff; +- descriptorStruct.mchStraps.padding[1726] = 0xff; +- descriptorStruct.mchStraps.padding[1727] = 0xff; +- descriptorStruct.mchStraps.padding[1728] = 0xff; +- descriptorStruct.mchStraps.padding[1729] = 0xff; +- descriptorStruct.mchStraps.padding[1730] = 0xff; +- descriptorStruct.mchStraps.padding[1731] = 0xff; +- descriptorStruct.mchStraps.padding[1732] = 0xff; +- descriptorStruct.mchStraps.padding[1733] = 0xff; +- descriptorStruct.mchStraps.padding[1734] = 0xff; +- descriptorStruct.mchStraps.padding[1735] = 0xff; +- descriptorStruct.mchStraps.padding[1736] = 0xff; +- descriptorStruct.mchStraps.padding[1737] = 0xff; +- descriptorStruct.mchStraps.padding[1738] = 0xff; +- descriptorStruct.mchStraps.padding[1739] = 0xff; +- descriptorStruct.mchStraps.padding[1740] = 0xff; +- descriptorStruct.mchStraps.padding[1741] = 0xff; +- descriptorStruct.mchStraps.padding[1742] = 0xff; +- descriptorStruct.mchStraps.padding[1743] = 0xff; +- descriptorStruct.mchStraps.padding[1744] = 0xff; +- descriptorStruct.mchStraps.padding[1745] = 0xff; +- descriptorStruct.mchStraps.padding[1746] = 0xff; +- descriptorStruct.mchStraps.padding[1747] = 0xff; +- descriptorStruct.mchStraps.padding[1748] = 0xff; +- descriptorStruct.mchStraps.padding[1749] = 0xff; +- descriptorStruct.mchStraps.padding[1750] = 0xff; +- descriptorStruct.mchStraps.padding[1751] = 0xff; +- descriptorStruct.mchStraps.padding[1752] = 0xff; +- descriptorStruct.mchStraps.padding[1753] = 0xff; +- descriptorStruct.mchStraps.padding[1754] = 0xff; +- descriptorStruct.mchStraps.padding[1755] = 0xff; +- descriptorStruct.mchStraps.padding[1756] = 0xff; +- descriptorStruct.mchStraps.padding[1757] = 0xff; +- descriptorStruct.mchStraps.padding[1758] = 0xff; +- descriptorStruct.mchStraps.padding[1759] = 0xff; +- descriptorStruct.mchStraps.padding[1760] = 0xff; +- descriptorStruct.mchStraps.padding[1761] = 0xff; +- descriptorStruct.mchStraps.padding[1762] = 0xff; +- descriptorStruct.mchStraps.padding[1763] = 0xff; +- descriptorStruct.mchStraps.padding[1764] = 0xff; +- descriptorStruct.mchStraps.padding[1765] = 0xff; +- descriptorStruct.mchStraps.padding[1766] = 0xff; +- descriptorStruct.mchStraps.padding[1767] = 0xff; +- descriptorStruct.mchStraps.padding[1768] = 0xff; +- descriptorStruct.mchStraps.padding[1769] = 0xff; +- descriptorStruct.mchStraps.padding[1770] = 0xff; +- descriptorStruct.mchStraps.padding[1771] = 0xff; +- descriptorStruct.mchStraps.padding[1772] = 0xff; +- descriptorStruct.mchStraps.padding[1773] = 0xff; +- descriptorStruct.mchStraps.padding[1774] = 0xff; +- descriptorStruct.mchStraps.padding[1775] = 0xff; +- descriptorStruct.mchStraps.padding[1776] = 0xff; +- descriptorStruct.mchStraps.padding[1777] = 0xff; +- descriptorStruct.mchStraps.padding[1778] = 0xff; +- descriptorStruct.mchStraps.padding[1779] = 0xff; +- descriptorStruct.mchStraps.padding[1780] = 0xff; +- descriptorStruct.mchStraps.padding[1781] = 0xff; +- descriptorStruct.mchStraps.padding[1782] = 0xff; +- descriptorStruct.mchStraps.padding[1783] = 0xff; +- descriptorStruct.mchStraps.padding[1784] = 0xff; +- descriptorStruct.mchStraps.padding[1785] = 0xff; +- descriptorStruct.mchStraps.padding[1786] = 0xff; +- descriptorStruct.mchStraps.padding[1787] = 0xff; +- descriptorStruct.mchStraps.padding[1788] = 0xff; +- descriptorStruct.mchStraps.padding[1789] = 0xff; +- descriptorStruct.mchStraps.padding[1790] = 0xff; +- descriptorStruct.mchStraps.padding[1791] = 0xff; +- descriptorStruct.mchStraps.padding[1792] = 0xff; +- descriptorStruct.mchStraps.padding[1793] = 0xff; +- descriptorStruct.mchStraps.padding[1794] = 0xff; +- descriptorStruct.mchStraps.padding[1795] = 0xff; +- descriptorStruct.mchStraps.padding[1796] = 0xff; +- descriptorStruct.mchStraps.padding[1797] = 0xff; +- descriptorStruct.mchStraps.padding[1798] = 0xff; +- descriptorStruct.mchStraps.padding[1799] = 0xff; +- descriptorStruct.mchStraps.padding[1800] = 0xff; +- descriptorStruct.mchStraps.padding[1801] = 0xff; +- descriptorStruct.mchStraps.padding[1802] = 0xff; +- descriptorStruct.mchStraps.padding[1803] = 0xff; +- descriptorStruct.mchStraps.padding[1804] = 0xff; +- descriptorStruct.mchStraps.padding[1805] = 0xff; +- descriptorStruct.mchStraps.padding[1806] = 0xff; +- descriptorStruct.mchStraps.padding[1807] = 0xff; +- descriptorStruct.mchStraps.padding[1808] = 0xff; +- descriptorStruct.mchStraps.padding[1809] = 0xff; +- descriptorStruct.mchStraps.padding[1810] = 0xff; +- descriptorStruct.mchStraps.padding[1811] = 0xff; +- descriptorStruct.mchStraps.padding[1812] = 0xff; +- descriptorStruct.mchStraps.padding[1813] = 0xff; +- descriptorStruct.mchStraps.padding[1814] = 0xff; +- descriptorStruct.mchStraps.padding[1815] = 0xff; +- descriptorStruct.mchStraps.padding[1816] = 0xff; +- descriptorStruct.mchStraps.padding[1817] = 0xff; +- descriptorStruct.mchStraps.padding[1818] = 0xff; +- descriptorStruct.mchStraps.padding[1819] = 0xff; +- descriptorStruct.mchStraps.padding[1820] = 0xff; +- descriptorStruct.mchStraps.padding[1821] = 0xff; +- descriptorStruct.mchStraps.padding[1822] = 0xff; +- descriptorStruct.mchStraps.padding[1823] = 0xff; +- descriptorStruct.mchStraps.padding[1824] = 0xff; +- descriptorStruct.mchStraps.padding[1825] = 0xff; +- descriptorStruct.mchStraps.padding[1826] = 0xff; +- descriptorStruct.mchStraps.padding[1827] = 0xff; +- descriptorStruct.mchStraps.padding[1828] = 0xff; +- descriptorStruct.mchStraps.padding[1829] = 0xff; +- descriptorStruct.mchStraps.padding[1830] = 0xff; +- descriptorStruct.mchStraps.padding[1831] = 0xff; +- descriptorStruct.mchStraps.padding[1832] = 0xff; +- descriptorStruct.mchStraps.padding[1833] = 0xff; +- descriptorStruct.mchStraps.padding[1834] = 0xff; +- descriptorStruct.mchStraps.padding[1835] = 0xff; +- descriptorStruct.mchStraps.padding[1836] = 0xff; +- descriptorStruct.mchStraps.padding[1837] = 0xff; +- descriptorStruct.mchStraps.padding[1838] = 0xff; +- descriptorStruct.mchStraps.padding[1839] = 0xff; +- descriptorStruct.mchStraps.padding[1840] = 0xff; +- descriptorStruct.mchStraps.padding[1841] = 0xff; +- descriptorStruct.mchStraps.padding[1842] = 0xff; +- descriptorStruct.mchStraps.padding[1843] = 0xff; +- descriptorStruct.mchStraps.padding[1844] = 0xff; +- descriptorStruct.mchStraps.padding[1845] = 0xff; +- descriptorStruct.mchStraps.padding[1846] = 0xff; +- descriptorStruct.mchStraps.padding[1847] = 0xff; +- descriptorStruct.mchStraps.padding[1848] = 0xff; +- descriptorStruct.mchStraps.padding[1849] = 0xff; +- descriptorStruct.mchStraps.padding[1850] = 0xff; +- descriptorStruct.mchStraps.padding[1851] = 0xff; +- descriptorStruct.mchStraps.padding[1852] = 0xff; +- descriptorStruct.mchStraps.padding[1853] = 0xff; +- descriptorStruct.mchStraps.padding[1854] = 0xff; +- descriptorStruct.mchStraps.padding[1855] = 0xff; +- descriptorStruct.mchStraps.padding[1856] = 0xff; +- descriptorStruct.mchStraps.padding[1857] = 0xff; +- descriptorStruct.mchStraps.padding[1858] = 0xff; +- descriptorStruct.mchStraps.padding[1859] = 0xff; +- descriptorStruct.mchStraps.padding[1860] = 0xff; +- descriptorStruct.mchStraps.padding[1861] = 0xff; +- descriptorStruct.mchStraps.padding[1862] = 0xff; +- descriptorStruct.mchStraps.padding[1863] = 0xff; +- descriptorStruct.mchStraps.padding[1864] = 0xff; +- descriptorStruct.mchStraps.padding[1865] = 0xff; +- descriptorStruct.mchStraps.padding[1866] = 0xff; +- descriptorStruct.mchStraps.padding[1867] = 0xff; +- descriptorStruct.mchStraps.padding[1868] = 0xff; +- descriptorStruct.mchStraps.padding[1869] = 0xff; +- descriptorStruct.mchStraps.padding[1870] = 0xff; +- descriptorStruct.mchStraps.padding[1871] = 0xff; +- descriptorStruct.mchStraps.padding[1872] = 0xff; +- descriptorStruct.mchStraps.padding[1873] = 0xff; +- descriptorStruct.mchStraps.padding[1874] = 0xff; +- descriptorStruct.mchStraps.padding[1875] = 0xff; +- descriptorStruct.mchStraps.padding[1876] = 0xff; +- descriptorStruct.mchStraps.padding[1877] = 0xff; +- descriptorStruct.mchStraps.padding[1878] = 0xff; +- descriptorStruct.mchStraps.padding[1879] = 0xff; +- descriptorStruct.mchStraps.padding[1880] = 0xff; +- descriptorStruct.mchStraps.padding[1881] = 0xff; +- descriptorStruct.mchStraps.padding[1882] = 0xff; +- descriptorStruct.mchStraps.padding[1883] = 0xff; +- descriptorStruct.mchStraps.padding[1884] = 0xff; +- descriptorStruct.mchStraps.padding[1885] = 0xff; +- descriptorStruct.mchStraps.padding[1886] = 0xff; +- descriptorStruct.mchStraps.padding[1887] = 0xff; +- descriptorStruct.mchStraps.padding[1888] = 0xff; +- descriptorStruct.mchStraps.padding[1889] = 0xff; +- descriptorStruct.mchStraps.padding[1890] = 0xff; +- descriptorStruct.mchStraps.padding[1891] = 0xff; +- descriptorStruct.mchStraps.padding[1892] = 0xff; +- descriptorStruct.mchStraps.padding[1893] = 0xff; +- descriptorStruct.mchStraps.padding[1894] = 0xff; +- descriptorStruct.mchStraps.padding[1895] = 0xff; +- descriptorStruct.mchStraps.padding[1896] = 0xff; +- descriptorStruct.mchStraps.padding[1897] = 0xff; +- descriptorStruct.mchStraps.padding[1898] = 0xff; +- descriptorStruct.mchStraps.padding[1899] = 0xff; +- descriptorStruct.mchStraps.padding[1900] = 0xff; +- descriptorStruct.mchStraps.padding[1901] = 0xff; +- descriptorStruct.mchStraps.padding[1902] = 0xff; +- descriptorStruct.mchStraps.padding[1903] = 0xff; +- descriptorStruct.mchStraps.padding[1904] = 0xff; +- descriptorStruct.mchStraps.padding[1905] = 0xff; +- descriptorStruct.mchStraps.padding[1906] = 0xff; +- descriptorStruct.mchStraps.padding[1907] = 0xff; +- descriptorStruct.mchStraps.padding[1908] = 0xff; +- descriptorStruct.mchStraps.padding[1909] = 0xff; +- descriptorStruct.mchStraps.padding[1910] = 0xff; +- descriptorStruct.mchStraps.padding[1911] = 0xff; +- descriptorStruct.mchStraps.padding[1912] = 0xff; +- descriptorStruct.mchStraps.padding[1913] = 0xff; +- descriptorStruct.mchStraps.padding[1914] = 0xff; +- descriptorStruct.mchStraps.padding[1915] = 0xff; +- descriptorStruct.mchStraps.padding[1916] = 0xff; +- descriptorStruct.mchStraps.padding[1917] = 0xff; +- descriptorStruct.mchStraps.padding[1918] = 0xff; +- descriptorStruct.mchStraps.padding[1919] = 0xff; +- descriptorStruct.mchStraps.padding[1920] = 0xff; +- descriptorStruct.mchStraps.padding[1921] = 0xff; +- descriptorStruct.mchStraps.padding[1922] = 0xff; +- descriptorStruct.mchStraps.padding[1923] = 0xff; +- descriptorStruct.mchStraps.padding[1924] = 0xff; +- descriptorStruct.mchStraps.padding[1925] = 0xff; +- descriptorStruct.mchStraps.padding[1926] = 0xff; +- descriptorStruct.mchStraps.padding[1927] = 0xff; +- descriptorStruct.mchStraps.padding[1928] = 0xff; +- descriptorStruct.mchStraps.padding[1929] = 0xff; +- descriptorStruct.mchStraps.padding[1930] = 0xff; +- descriptorStruct.mchStraps.padding[1931] = 0xff; +- descriptorStruct.mchStraps.padding[1932] = 0xff; +- descriptorStruct.mchStraps.padding[1933] = 0xff; +- descriptorStruct.mchStraps.padding[1934] = 0xff; +- descriptorStruct.mchStraps.padding[1935] = 0xff; +- descriptorStruct.mchStraps.padding[1936] = 0xff; +- descriptorStruct.mchStraps.padding[1937] = 0xff; +- descriptorStruct.mchStraps.padding[1938] = 0xff; +- descriptorStruct.mchStraps.padding[1939] = 0xff; +- descriptorStruct.mchStraps.padding[1940] = 0xff; +- descriptorStruct.mchStraps.padding[1941] = 0xff; +- descriptorStruct.mchStraps.padding[1942] = 0xff; +- descriptorStruct.mchStraps.padding[1943] = 0xff; +- descriptorStruct.mchStraps.padding[1944] = 0xff; +- descriptorStruct.mchStraps.padding[1945] = 0xff; +- descriptorStruct.mchStraps.padding[1946] = 0xff; +- descriptorStruct.mchStraps.padding[1947] = 0xff; +- descriptorStruct.mchStraps.padding[1948] = 0xff; +- descriptorStruct.mchStraps.padding[1949] = 0xff; +- descriptorStruct.mchStraps.padding[1950] = 0xff; +- descriptorStruct.mchStraps.padding[1951] = 0xff; +- descriptorStruct.mchStraps.padding[1952] = 0xff; +- descriptorStruct.mchStraps.padding[1953] = 0xff; +- descriptorStruct.mchStraps.padding[1954] = 0xff; +- descriptorStruct.mchStraps.padding[1955] = 0xff; +- descriptorStruct.mchStraps.padding[1956] = 0xff; +- descriptorStruct.mchStraps.padding[1957] = 0xff; +- descriptorStruct.mchStraps.padding[1958] = 0xff; +- descriptorStruct.mchStraps.padding[1959] = 0xff; +- descriptorStruct.mchStraps.padding[1960] = 0xff; +- descriptorStruct.mchStraps.padding[1961] = 0xff; +- descriptorStruct.mchStraps.padding[1962] = 0xff; +- descriptorStruct.mchStraps.padding[1963] = 0xff; +- descriptorStruct.mchStraps.padding[1964] = 0xff; +- descriptorStruct.mchStraps.padding[1965] = 0xff; +- descriptorStruct.mchStraps.padding[1966] = 0xff; +- descriptorStruct.mchStraps.padding[1967] = 0xff; +- descriptorStruct.mchStraps.padding[1968] = 0xff; +- descriptorStruct.mchStraps.padding[1969] = 0xff; +- descriptorStruct.mchStraps.padding[1970] = 0xff; +- descriptorStruct.mchStraps.padding[1971] = 0xff; +- descriptorStruct.mchStraps.padding[1972] = 0xff; +- descriptorStruct.mchStraps.padding[1973] = 0xff; +- descriptorStruct.mchStraps.padding[1974] = 0xff; +- descriptorStruct.mchStraps.padding[1975] = 0xff; +- descriptorStruct.mchStraps.padding[1976] = 0xff; +- descriptorStruct.mchStraps.padding[1977] = 0xff; +- descriptorStruct.mchStraps.padding[1978] = 0xff; +- descriptorStruct.mchStraps.padding[1979] = 0xff; +- descriptorStruct.mchStraps.padding[1980] = 0xff; +- descriptorStruct.mchStraps.padding[1981] = 0xff; +- descriptorStruct.mchStraps.padding[1982] = 0xff; +- descriptorStruct.mchStraps.padding[1983] = 0xff; +- descriptorStruct.mchStraps.padding[1984] = 0xff; +- descriptorStruct.mchStraps.padding[1985] = 0xff; +- descriptorStruct.mchStraps.padding[1986] = 0xff; +- descriptorStruct.mchStraps.padding[1987] = 0xff; +- descriptorStruct.mchStraps.padding[1988] = 0xff; +- descriptorStruct.mchStraps.padding[1989] = 0xff; +- descriptorStruct.mchStraps.padding[1990] = 0xff; +- descriptorStruct.mchStraps.padding[1991] = 0xff; +- descriptorStruct.mchStraps.padding[1992] = 0xff; +- descriptorStruct.mchStraps.padding[1993] = 0xff; +- descriptorStruct.mchStraps.padding[1994] = 0xff; +- descriptorStruct.mchStraps.padding[1995] = 0xff; +- descriptorStruct.mchStraps.padding[1996] = 0xff; +- descriptorStruct.mchStraps.padding[1997] = 0xff; +- descriptorStruct.mchStraps.padding[1998] = 0xff; +- descriptorStruct.mchStraps.padding[1999] = 0xff; +- descriptorStruct.mchStraps.padding[2000] = 0xff; +- descriptorStruct.mchStraps.padding[2001] = 0xff; +- descriptorStruct.mchStraps.padding[2002] = 0xff; +- descriptorStruct.mchStraps.padding[2003] = 0xff; +- descriptorStruct.mchStraps.padding[2004] = 0xff; +- descriptorStruct.mchStraps.padding[2005] = 0xff; +- descriptorStruct.mchStraps.padding[2006] = 0xff; +- descriptorStruct.mchStraps.padding[2007] = 0xff; +- descriptorStruct.mchStraps.padding[2008] = 0xff; +- descriptorStruct.mchStraps.padding[2009] = 0xff; +- descriptorStruct.mchStraps.padding[2010] = 0xff; +- descriptorStruct.mchStraps.padding[2011] = 0xff; +- descriptorStruct.mchStraps.padding[2012] = 0xff; +- descriptorStruct.mchStraps.padding[2013] = 0xff; +- descriptorStruct.mchStraps.padding[2014] = 0xff; +- descriptorStruct.mchStraps.padding[2015] = 0xff; +- descriptorStruct.mchStraps.padding[2016] = 0xff; +- descriptorStruct.mchStraps.padding[2017] = 0xff; +- descriptorStruct.mchStraps.padding[2018] = 0xff; +- descriptorStruct.mchStraps.padding[2019] = 0xff; +- descriptorStruct.mchStraps.padding[2020] = 0xff; +- descriptorStruct.mchStraps.padding[2021] = 0xff; +- descriptorStruct.mchStraps.padding[2022] = 0xff; +- descriptorStruct.mchStraps.padding[2023] = 0xff; +- descriptorStruct.mchStraps.padding[2024] = 0xff; +- descriptorStruct.mchStraps.padding[2025] = 0xff; +- descriptorStruct.mchStraps.padding[2026] = 0xff; +- descriptorStruct.mchStraps.padding[2027] = 0xff; +- descriptorStruct.mchStraps.padding[2028] = 0xff; +- descriptorStruct.mchStraps.padding[2029] = 0xff; +- descriptorStruct.mchStraps.padding[2030] = 0xff; +- descriptorStruct.mchStraps.padding[2031] = 0xff; +- descriptorStruct.mchStraps.padding[2032] = 0xff; +- descriptorStruct.mchStraps.padding[2033] = 0xff; +- descriptorStruct.mchStraps.padding[2034] = 0xff; +- descriptorStruct.mchStraps.padding[2035] = 0xff; +- descriptorStruct.mchStraps.padding[2036] = 0xff; +- descriptorStruct.mchStraps.padding[2037] = 0xff; +- descriptorStruct.mchStraps.padding[2038] = 0xff; +- descriptorStruct.mchStraps.padding[2039] = 0xff; +- descriptorStruct.mchStraps.padding[2040] = 0xff; +- descriptorStruct.mchStraps.padding[2041] = 0xff; +- descriptorStruct.mchStraps.padding[2042] = 0xff; +- descriptorStruct.mchStraps.padding[2043] = 0xff; +- descriptorStruct.mchStraps.padding[2044] = 0xff; +- descriptorStruct.mchStraps.padding[2045] = 0xff; +- descriptorStruct.mchStraps.padding[2046] = 0xff; +- descriptorStruct.mchStraps.padding[2047] = 0xff; +- descriptorStruct.mchStraps.padding[2048] = 0xff; +- descriptorStruct.mchStraps.padding[2049] = 0xff; +- descriptorStruct.mchStraps.padding[2050] = 0xff; +- descriptorStruct.mchStraps.padding[2051] = 0xff; +- descriptorStruct.mchStraps.padding[2052] = 0xff; +- descriptorStruct.mchStraps.padding[2053] = 0xff; +- descriptorStruct.mchStraps.padding[2054] = 0xff; +- descriptorStruct.mchStraps.padding[2055] = 0xff; +- descriptorStruct.mchStraps.padding[2056] = 0xff; +- descriptorStruct.mchStraps.padding[2057] = 0xff; +- descriptorStruct.mchStraps.padding[2058] = 0xff; +- descriptorStruct.mchStraps.padding[2059] = 0xff; +- descriptorStruct.mchStraps.padding[2060] = 0xff; +- descriptorStruct.mchStraps.padding[2061] = 0xff; +- descriptorStruct.mchStraps.padding[2062] = 0xff; +- descriptorStruct.mchStraps.padding[2063] = 0xff; +- descriptorStruct.mchStraps.padding[2064] = 0xff; +- descriptorStruct.mchStraps.padding[2065] = 0xff; +- descriptorStruct.mchStraps.padding[2066] = 0xff; +- descriptorStruct.mchStraps.padding[2067] = 0xff; +- descriptorStruct.mchStraps.padding[2068] = 0xff; +- descriptorStruct.mchStraps.padding[2069] = 0xff; +- descriptorStruct.mchStraps.padding[2070] = 0xff; +- descriptorStruct.mchStraps.padding[2071] = 0xff; +- descriptorStruct.mchStraps.padding[2072] = 0xff; +- descriptorStruct.mchStraps.padding[2073] = 0xff; +- descriptorStruct.mchStraps.padding[2074] = 0xff; +- descriptorStruct.mchStraps.padding[2075] = 0xff; +- descriptorStruct.mchStraps.padding[2076] = 0xff; +- descriptorStruct.mchStraps.padding[2077] = 0xff; +- descriptorStruct.mchStraps.padding[2078] = 0xff; +- descriptorStruct.mchStraps.padding[2079] = 0xff; +- descriptorStruct.mchStraps.padding[2080] = 0xff; +- descriptorStruct.mchStraps.padding[2081] = 0xff; +- descriptorStruct.mchStraps.padding[2082] = 0xff; +- descriptorStruct.mchStraps.padding[2083] = 0xff; +- descriptorStruct.mchStraps.padding[2084] = 0xff; +- descriptorStruct.mchStraps.padding[2085] = 0xff; +- descriptorStruct.mchStraps.padding[2086] = 0xff; +- descriptorStruct.mchStraps.padding[2087] = 0xff; +- descriptorStruct.mchStraps.padding[2088] = 0xff; +- descriptorStruct.mchStraps.padding[2089] = 0xff; +- descriptorStruct.mchStraps.padding[2090] = 0xff; +- descriptorStruct.mchStraps.padding[2091] = 0xff; +- descriptorStruct.mchStraps.padding[2092] = 0xff; +- descriptorStruct.mchStraps.padding[2093] = 0xff; +- descriptorStruct.mchStraps.padding[2094] = 0xff; +- descriptorStruct.mchStraps.padding[2095] = 0xff; +- descriptorStruct.mchStraps.padding[2096] = 0xff; +- descriptorStruct.mchStraps.padding[2097] = 0xff; +- descriptorStruct.mchStraps.padding[2098] = 0xff; +- descriptorStruct.mchStraps.padding[2099] = 0xff; +- descriptorStruct.mchStraps.padding[2100] = 0xff; +- descriptorStruct.mchStraps.padding[2101] = 0xff; +- descriptorStruct.mchStraps.padding[2102] = 0xff; +- descriptorStruct.mchStraps.padding[2103] = 0xff; +- descriptorStruct.mchStraps.padding[2104] = 0xff; +- descriptorStruct.mchStraps.padding[2105] = 0xff; +- descriptorStruct.mchStraps.padding[2106] = 0xff; +- descriptorStruct.mchStraps.padding[2107] = 0xff; +- descriptorStruct.mchStraps.padding[2108] = 0xff; +- descriptorStruct.mchStraps.padding[2109] = 0xff; +- descriptorStruct.mchStraps.padding[2110] = 0xff; +- descriptorStruct.mchStraps.padding[2111] = 0xff; +- descriptorStruct.mchStraps.padding[2112] = 0xff; +- descriptorStruct.mchStraps.padding[2113] = 0xff; +- descriptorStruct.mchStraps.padding[2114] = 0xff; +- descriptorStruct.mchStraps.padding[2115] = 0xff; +- descriptorStruct.mchStraps.padding[2116] = 0xff; +- descriptorStruct.mchStraps.padding[2117] = 0xff; +- descriptorStruct.mchStraps.padding[2118] = 0xff; +- descriptorStruct.mchStraps.padding[2119] = 0xff; +- descriptorStruct.mchStraps.padding[2120] = 0xff; +- descriptorStruct.mchStraps.padding[2121] = 0xff; +- descriptorStruct.mchStraps.padding[2122] = 0xff; +- descriptorStruct.mchStraps.padding[2123] = 0xff; +- descriptorStruct.mchStraps.padding[2124] = 0xff; +- descriptorStruct.mchStraps.padding[2125] = 0xff; +- descriptorStruct.mchStraps.padding[2126] = 0xff; +- descriptorStruct.mchStraps.padding[2127] = 0xff; +- descriptorStruct.mchStraps.padding[2128] = 0xff; +- descriptorStruct.mchStraps.padding[2129] = 0xff; +- descriptorStruct.mchStraps.padding[2130] = 0xff; +- descriptorStruct.mchStraps.padding[2131] = 0xff; +- descriptorStruct.mchStraps.padding[2132] = 0xff; +- descriptorStruct.mchStraps.padding[2133] = 0xff; +- descriptorStruct.mchStraps.padding[2134] = 0xff; +- descriptorStruct.mchStraps.padding[2135] = 0xff; +- descriptorStruct.mchStraps.padding[2136] = 0xff; +- descriptorStruct.mchStraps.padding[2137] = 0xff; +- descriptorStruct.mchStraps.padding[2138] = 0xff; +- descriptorStruct.mchStraps.padding[2139] = 0xff; +- descriptorStruct.mchStraps.padding[2140] = 0xff; +- descriptorStruct.mchStraps.padding[2141] = 0xff; +- descriptorStruct.mchStraps.padding[2142] = 0xff; +- descriptorStruct.mchStraps.padding[2143] = 0xff; +- descriptorStruct.mchStraps.padding[2144] = 0xff; +- descriptorStruct.mchStraps.padding[2145] = 0xff; +- descriptorStruct.mchStraps.padding[2146] = 0xff; +- descriptorStruct.mchStraps.padding[2147] = 0xff; +- descriptorStruct.mchStraps.padding[2148] = 0xff; +- descriptorStruct.mchStraps.padding[2149] = 0xff; +- descriptorStruct.mchStraps.padding[2150] = 0xff; +- descriptorStruct.mchStraps.padding[2151] = 0xff; +- descriptorStruct.mchStraps.padding[2152] = 0xff; +- descriptorStruct.mchStraps.padding[2153] = 0xff; +- descriptorStruct.mchStraps.padding[2154] = 0xff; +- descriptorStruct.mchStraps.padding[2155] = 0xff; +- descriptorStruct.mchStraps.padding[2156] = 0xff; +- descriptorStruct.mchStraps.padding[2157] = 0xff; +- descriptorStruct.mchStraps.padding[2158] = 0xff; +- descriptorStruct.mchStraps.padding[2159] = 0xff; +- descriptorStruct.mchStraps.padding[2160] = 0xff; +- descriptorStruct.mchStraps.padding[2161] = 0xff; +- descriptorStruct.mchStraps.padding[2162] = 0xff; +- descriptorStruct.mchStraps.padding[2163] = 0xff; +- descriptorStruct.mchStraps.padding[2164] = 0xff; +- descriptorStruct.mchStraps.padding[2165] = 0xff; +- descriptorStruct.mchStraps.padding[2166] = 0xff; +- descriptorStruct.mchStraps.padding[2167] = 0xff; +- descriptorStruct.mchStraps.padding[2168] = 0xff; +- descriptorStruct.mchStraps.padding[2169] = 0xff; +- descriptorStruct.mchStraps.padding[2170] = 0xff; +- descriptorStruct.mchStraps.padding[2171] = 0xff; +- descriptorStruct.mchStraps.padding[2172] = 0xff; +- descriptorStruct.mchStraps.padding[2173] = 0xff; +- descriptorStruct.mchStraps.padding[2174] = 0xff; +- descriptorStruct.mchStraps.padding[2175] = 0xff; +- descriptorStruct.mchStraps.padding[2176] = 0xff; +- descriptorStruct.mchStraps.padding[2177] = 0xff; +- descriptorStruct.mchStraps.padding[2178] = 0xff; +- descriptorStruct.mchStraps.padding[2179] = 0xff; +- descriptorStruct.mchStraps.padding[2180] = 0xff; +- descriptorStruct.mchStraps.padding[2181] = 0xff; +- descriptorStruct.mchStraps.padding[2182] = 0xff; +- descriptorStruct.mchStraps.padding[2183] = 0xff; +- descriptorStruct.mchStraps.padding[2184] = 0xff; +- descriptorStruct.mchStraps.padding[2185] = 0xff; +- descriptorStruct.mchStraps.padding[2186] = 0xff; +- descriptorStruct.mchStraps.padding[2187] = 0xff; +- descriptorStruct.mchStraps.padding[2188] = 0xff; +- descriptorStruct.mchStraps.padding[2189] = 0xff; +- descriptorStruct.mchStraps.padding[2190] = 0xff; +- descriptorStruct.mchStraps.padding[2191] = 0xff; +- descriptorStruct.mchStraps.padding[2192] = 0xff; +- descriptorStruct.mchStraps.padding[2193] = 0xff; +- descriptorStruct.mchStraps.padding[2194] = 0xff; +- descriptorStruct.mchStraps.padding[2195] = 0xff; +- descriptorStruct.mchStraps.padding[2196] = 0xff; +- descriptorStruct.mchStraps.padding[2197] = 0xff; +- descriptorStruct.mchStraps.padding[2198] = 0xff; +- descriptorStruct.mchStraps.padding[2199] = 0xff; +- descriptorStruct.mchStraps.padding[2200] = 0xff; +- descriptorStruct.mchStraps.padding[2201] = 0xff; +- descriptorStruct.mchStraps.padding[2202] = 0xff; +- descriptorStruct.mchStraps.padding[2203] = 0xff; +- descriptorStruct.mchStraps.padding[2204] = 0xff; +- descriptorStruct.mchStraps.padding[2205] = 0xff; +- descriptorStruct.mchStraps.padding[2206] = 0xff; +- descriptorStruct.mchStraps.padding[2207] = 0xff; +- descriptorStruct.mchStraps.padding[2208] = 0xff; +- descriptorStruct.mchStraps.padding[2209] = 0xff; +- descriptorStruct.mchStraps.padding[2210] = 0xff; +- descriptorStruct.mchStraps.padding[2211] = 0xff; +- descriptorStruct.mchStraps.padding[2212] = 0xff; +- descriptorStruct.mchStraps.padding[2213] = 0xff; +- descriptorStruct.mchStraps.padding[2214] = 0xff; +- descriptorStruct.mchStraps.padding[2215] = 0xff; +- descriptorStruct.mchStraps.padding[2216] = 0xff; +- descriptorStruct.mchStraps.padding[2217] = 0xff; +- descriptorStruct.mchStraps.padding[2218] = 0xff; +- descriptorStruct.mchStraps.padding[2219] = 0xff; +- descriptorStruct.mchStraps.padding[2220] = 0xff; +- descriptorStruct.mchStraps.padding[2221] = 0xff; +- descriptorStruct.mchStraps.padding[2222] = 0xff; +- descriptorStruct.mchStraps.padding[2223] = 0xff; +- descriptorStruct.mchStraps.padding[2224] = 0xff; +- descriptorStruct.mchStraps.padding[2225] = 0xff; +- descriptorStruct.mchStraps.padding[2226] = 0xff; +- descriptorStruct.mchStraps.padding[2227] = 0xff; +- descriptorStruct.mchStraps.padding[2228] = 0xff; +- descriptorStruct.mchStraps.padding[2229] = 0xff; +- descriptorStruct.mchStraps.padding[2230] = 0xff; +- descriptorStruct.mchStraps.padding[2231] = 0xff; +- descriptorStruct.mchStraps.padding[2232] = 0xff; +- descriptorStruct.mchStraps.padding[2233] = 0xff; +- descriptorStruct.mchStraps.padding[2234] = 0xff; +- descriptorStruct.mchStraps.padding[2235] = 0xff; +- descriptorStruct.mchStraps.padding[2236] = 0xff; +- descriptorStruct.mchStraps.padding[2237] = 0xff; +- descriptorStruct.mchStraps.padding[2238] = 0xff; +- descriptorStruct.mchStraps.padding[2239] = 0xff; +- descriptorStruct.mchStraps.padding[2240] = 0xff; +- descriptorStruct.mchStraps.padding[2241] = 0xff; +- descriptorStruct.mchStraps.padding[2242] = 0xff; +- descriptorStruct.mchStraps.padding[2243] = 0xff; +- descriptorStruct.mchStraps.padding[2244] = 0xff; +- descriptorStruct.mchStraps.padding[2245] = 0xff; +- descriptorStruct.mchStraps.padding[2246] = 0xff; +- descriptorStruct.mchStraps.padding[2247] = 0xff; +- descriptorStruct.mchStraps.padding[2248] = 0xff; +- descriptorStruct.mchStraps.padding[2249] = 0xff; +- descriptorStruct.mchStraps.padding[2250] = 0xff; +- descriptorStruct.mchStraps.padding[2251] = 0xff; +- descriptorStruct.mchStraps.padding[2252] = 0xff; +- descriptorStruct.mchStraps.padding[2253] = 0xff; +- descriptorStruct.mchStraps.padding[2254] = 0xff; +- descriptorStruct.mchStraps.padding[2255] = 0xff; +- descriptorStruct.mchStraps.padding[2256] = 0xff; +- descriptorStruct.mchStraps.padding[2257] = 0xff; +- descriptorStruct.mchStraps.padding[2258] = 0xff; +- descriptorStruct.mchStraps.padding[2259] = 0xff; +- descriptorStruct.mchStraps.padding[2260] = 0xff; +- descriptorStruct.mchStraps.padding[2261] = 0xff; +- descriptorStruct.mchStraps.padding[2262] = 0xff; +- descriptorStruct.mchStraps.padding[2263] = 0xff; +- descriptorStruct.mchStraps.padding[2264] = 0xff; +- descriptorStruct.mchStraps.padding[2265] = 0xff; +- descriptorStruct.mchStraps.padding[2266] = 0xff; +- descriptorStruct.mchStraps.padding[2267] = 0xff; +- descriptorStruct.mchStraps.padding[2268] = 0xff; +- descriptorStruct.mchStraps.padding[2269] = 0xff; +- descriptorStruct.mchStraps.padding[2270] = 0xff; +- descriptorStruct.mchStraps.padding[2271] = 0xff; +- descriptorStruct.mchStraps.padding[2272] = 0xff; +- descriptorStruct.mchStraps.padding[2273] = 0xff; +- descriptorStruct.mchStraps.padding[2274] = 0xff; +- descriptorStruct.mchStraps.padding[2275] = 0xff; +- descriptorStruct.mchStraps.padding[2276] = 0xff; +- descriptorStruct.mchStraps.padding[2277] = 0xff; +- descriptorStruct.mchStraps.padding[2278] = 0xff; +- descriptorStruct.mchStraps.padding[2279] = 0xff; +- descriptorStruct.mchStraps.padding[2280] = 0xff; +- descriptorStruct.mchStraps.padding[2281] = 0xff; +- descriptorStruct.mchStraps.padding[2282] = 0xff; +- descriptorStruct.mchStraps.padding[2283] = 0xff; +- descriptorStruct.mchStraps.padding[2284] = 0xff; +- descriptorStruct.mchStraps.padding[2285] = 0xff; +- descriptorStruct.mchStraps.padding[2286] = 0xff; +- descriptorStruct.mchStraps.padding[2287] = 0xff; +- descriptorStruct.mchStraps.padding[2288] = 0xff; +- descriptorStruct.mchStraps.padding[2289] = 0xff; +- descriptorStruct.mchStraps.padding[2290] = 0xff; +- descriptorStruct.mchStraps.padding[2291] = 0xff; +- descriptorStruct.mchStraps.padding[2292] = 0xff; +- descriptorStruct.mchStraps.padding[2293] = 0xff; +- descriptorStruct.mchStraps.padding[2294] = 0xff; +- descriptorStruct.mchStraps.padding[2295] = 0xff; +- descriptorStruct.mchStraps.padding[2296] = 0xff; +- descriptorStruct.mchStraps.padding[2297] = 0xff; +- descriptorStruct.mchStraps.padding[2298] = 0xff; +- descriptorStruct.mchStraps.padding[2299] = 0xff; +- descriptorStruct.mchStraps.padding[2300] = 0xff; +- descriptorStruct.mchStraps.padding[2301] = 0xff; +- descriptorStruct.mchStraps.padding[2302] = 0xff; +- descriptorStruct.mchStraps.padding[2303] = 0xff; +- descriptorStruct.mchStraps.padding[2304] = 0xff; +- descriptorStruct.mchStraps.padding[2305] = 0xff; +- descriptorStruct.mchStraps.padding[2306] = 0xff; +- descriptorStruct.mchStraps.padding[2307] = 0xff; +- descriptorStruct.mchStraps.padding[2308] = 0xff; +- descriptorStruct.mchStraps.padding[2309] = 0xff; +- descriptorStruct.mchStraps.padding[2310] = 0xff; +- descriptorStruct.mchStraps.padding[2311] = 0xff; +- descriptorStruct.mchStraps.padding[2312] = 0xff; +- descriptorStruct.mchStraps.padding[2313] = 0xff; +- descriptorStruct.mchStraps.padding[2314] = 0xff; +- descriptorStruct.mchStraps.padding[2315] = 0xff; +- descriptorStruct.mchStraps.padding[2316] = 0xff; +- descriptorStruct.mchStraps.padding[2317] = 0xff; +- descriptorStruct.mchStraps.padding[2318] = 0xff; +- descriptorStruct.mchStraps.padding[2319] = 0xff; +- descriptorStruct.mchStraps.padding[2320] = 0xff; +- descriptorStruct.mchStraps.padding[2321] = 0xff; +- descriptorStruct.mchStraps.padding[2322] = 0xff; +- descriptorStruct.mchStraps.padding[2323] = 0xff; +- descriptorStruct.mchStraps.padding[2324] = 0xff; +- descriptorStruct.mchStraps.padding[2325] = 0xff; +- descriptorStruct.mchStraps.padding[2326] = 0xff; +- descriptorStruct.mchStraps.padding[2327] = 0xff; +- descriptorStruct.mchStraps.padding[2328] = 0xff; +- descriptorStruct.mchStraps.padding[2329] = 0xff; +- descriptorStruct.mchStraps.padding[2330] = 0xff; +- descriptorStruct.mchStraps.padding[2331] = 0xff; +- descriptorStruct.mchStraps.padding[2332] = 0xff; +- descriptorStruct.mchStraps.padding[2333] = 0xff; +- descriptorStruct.mchStraps.padding[2334] = 0xff; +- descriptorStruct.mchStraps.padding[2335] = 0xff; +- descriptorStruct.mchStraps.padding[2336] = 0xff; +- descriptorStruct.mchStraps.padding[2337] = 0xff; +- descriptorStruct.mchStraps.padding[2338] = 0xff; +- descriptorStruct.mchStraps.padding[2339] = 0xff; +- descriptorStruct.mchStraps.padding[2340] = 0xff; +- descriptorStruct.mchStraps.padding[2341] = 0xff; +- descriptorStruct.mchStraps.padding[2342] = 0xff; +- descriptorStruct.mchStraps.padding[2343] = 0xff; +- descriptorStruct.mchStraps.padding[2344] = 0xff; +- descriptorStruct.mchStraps.padding[2345] = 0xff; +- descriptorStruct.mchStraps.padding[2346] = 0xff; +- descriptorStruct.mchStraps.padding[2347] = 0xff; +- descriptorStruct.mchStraps.padding[2348] = 0xff; +- descriptorStruct.mchStraps.padding[2349] = 0xff; +- descriptorStruct.mchStraps.padding[2350] = 0xff; +- descriptorStruct.mchStraps.padding[2351] = 0xff; +- descriptorStruct.mchStraps.padding[2352] = 0xff; +- descriptorStruct.mchStraps.padding[2353] = 0xff; +- descriptorStruct.mchStraps.padding[2354] = 0xff; +- descriptorStruct.mchStraps.padding[2355] = 0xff; +- descriptorStruct.mchStraps.padding[2356] = 0xff; +- descriptorStruct.mchStraps.padding[2357] = 0xff; +- descriptorStruct.mchStraps.padding[2358] = 0xff; +- descriptorStruct.mchStraps.padding[2359] = 0xff; +- descriptorStruct.mchStraps.padding[2360] = 0xff; +- descriptorStruct.mchStraps.padding[2361] = 0xff; +- descriptorStruct.mchStraps.padding[2362] = 0xff; +- descriptorStruct.mchStraps.padding[2363] = 0xff; +- descriptorStruct.mchStraps.padding[2364] = 0xff; +- descriptorStruct.mchStraps.padding[2365] = 0xff; +- descriptorStruct.mchStraps.padding[2366] = 0xff; +- descriptorStruct.mchStraps.padding[2367] = 0xff; +- descriptorStruct.mchStraps.padding[2368] = 0xff; +- descriptorStruct.mchStraps.padding[2369] = 0xff; +- descriptorStruct.mchStraps.padding[2370] = 0xff; +- descriptorStruct.mchStraps.padding[2371] = 0xff; +- descriptorStruct.mchStraps.padding[2372] = 0xff; +- descriptorStruct.mchStraps.padding[2373] = 0xff; +- descriptorStruct.mchStraps.padding[2374] = 0xff; +- descriptorStruct.mchStraps.padding[2375] = 0xff; +- descriptorStruct.mchStraps.padding[2376] = 0xff; +- descriptorStruct.mchStraps.padding[2377] = 0xff; +- descriptorStruct.mchStraps.padding[2378] = 0xff; +- descriptorStruct.mchStraps.padding[2379] = 0xff; +- descriptorStruct.mchStraps.padding[2380] = 0xff; +- descriptorStruct.mchStraps.padding[2381] = 0xff; +- descriptorStruct.mchStraps.padding[2382] = 0xff; +- descriptorStruct.mchStraps.padding[2383] = 0xff; +- descriptorStruct.mchStraps.padding[2384] = 0xff; +- descriptorStruct.mchStraps.padding[2385] = 0xff; +- descriptorStruct.mchStraps.padding[2386] = 0xff; +- descriptorStruct.mchStraps.padding[2387] = 0xff; +- descriptorStruct.mchStraps.padding[2388] = 0xff; +- descriptorStruct.mchStraps.padding[2389] = 0xff; +- descriptorStruct.mchStraps.padding[2390] = 0xff; +- descriptorStruct.mchStraps.padding[2391] = 0xff; +- descriptorStruct.mchStraps.padding[2392] = 0xff; +- descriptorStruct.mchStraps.padding[2393] = 0xff; +- descriptorStruct.mchStraps.padding[2394] = 0xff; +- descriptorStruct.mchStraps.padding[2395] = 0xff; +- descriptorStruct.mchStraps.padding[2396] = 0xff; +- descriptorStruct.mchStraps.padding[2397] = 0xff; +- descriptorStruct.mchStraps.padding[2398] = 0xff; +- descriptorStruct.mchStraps.padding[2399] = 0xff; +- descriptorStruct.mchStraps.padding[2400] = 0xff; +- descriptorStruct.mchStraps.padding[2401] = 0xff; +- descriptorStruct.mchStraps.padding[2402] = 0xff; +- descriptorStruct.mchStraps.padding[2403] = 0xff; +- descriptorStruct.mchStraps.padding[2404] = 0xff; +- descriptorStruct.mchStraps.padding[2405] = 0xff; +- descriptorStruct.mchStraps.padding[2406] = 0xff; +- descriptorStruct.mchStraps.padding[2407] = 0xff; +- descriptorStruct.mchStraps.padding[2408] = 0xff; +- descriptorStruct.mchStraps.padding[2409] = 0xff; +- descriptorStruct.mchStraps.padding[2410] = 0xff; +- descriptorStruct.mchStraps.padding[2411] = 0xff; +- descriptorStruct.mchStraps.padding[2412] = 0xff; +- descriptorStruct.mchStraps.padding[2413] = 0xff; +- descriptorStruct.mchStraps.padding[2414] = 0xff; +- descriptorStruct.mchStraps.padding[2415] = 0xff; +- descriptorStruct.mchStraps.padding[2416] = 0xff; +- descriptorStruct.mchStraps.padding[2417] = 0xff; +- descriptorStruct.mchStraps.padding[2418] = 0xff; +- descriptorStruct.mchStraps.padding[2419] = 0xff; +- descriptorStruct.mchStraps.padding[2420] = 0xff; +- descriptorStruct.mchStraps.padding[2421] = 0xff; +- descriptorStruct.mchStraps.padding[2422] = 0xff; +- descriptorStruct.mchStraps.padding[2423] = 0xff; +- descriptorStruct.mchStraps.padding[2424] = 0xff; +- descriptorStruct.mchStraps.padding[2425] = 0xff; +- descriptorStruct.mchStraps.padding[2426] = 0xff; +- descriptorStruct.mchStraps.padding[2427] = 0xff; +- descriptorStruct.mchStraps.padding[2428] = 0xff; +- descriptorStruct.mchStraps.padding[2429] = 0xff; +- descriptorStruct.mchStraps.padding[2430] = 0xff; +- descriptorStruct.mchStraps.padding[2431] = 0xff; +- descriptorStruct.mchStraps.padding[2432] = 0xff; +- descriptorStruct.mchStraps.padding[2433] = 0xff; +- descriptorStruct.mchStraps.padding[2434] = 0xff; +- descriptorStruct.mchStraps.padding[2435] = 0xff; +- descriptorStruct.mchStraps.padding[2436] = 0xff; +- descriptorStruct.mchStraps.padding[2437] = 0xff; +- descriptorStruct.mchStraps.padding[2438] = 0xff; +- descriptorStruct.mchStraps.padding[2439] = 0xff; +- descriptorStruct.mchStraps.padding[2440] = 0xff; +- descriptorStruct.mchStraps.padding[2441] = 0xff; +- descriptorStruct.mchStraps.padding[2442] = 0xff; +- descriptorStruct.mchStraps.padding[2443] = 0xff; +- descriptorStruct.mchStraps.padding[2444] = 0xff; +- descriptorStruct.mchStraps.padding[2445] = 0xff; +- descriptorStruct.mchStraps.padding[2446] = 0xff; +- descriptorStruct.mchStraps.padding[2447] = 0xff; +- descriptorStruct.mchStraps.padding[2448] = 0xff; +- descriptorStruct.mchStraps.padding[2449] = 0xff; +- descriptorStruct.mchStraps.padding[2450] = 0xff; +- descriptorStruct.mchStraps.padding[2451] = 0xff; +- descriptorStruct.mchStraps.padding[2452] = 0xff; +- descriptorStruct.mchStraps.padding[2453] = 0xff; +- descriptorStruct.mchStraps.padding[2454] = 0xff; +- descriptorStruct.mchStraps.padding[2455] = 0xff; +- descriptorStruct.mchStraps.padding[2456] = 0xff; +- descriptorStruct.mchStraps.padding[2457] = 0xff; +- descriptorStruct.mchStraps.padding[2458] = 0xff; +- descriptorStruct.mchStraps.padding[2459] = 0xff; +- descriptorStruct.mchStraps.padding[2460] = 0xff; +- descriptorStruct.mchStraps.padding[2461] = 0xff; +- descriptorStruct.mchStraps.padding[2462] = 0xff; +- descriptorStruct.mchStraps.padding[2463] = 0xff; +- descriptorStruct.mchStraps.padding[2464] = 0xff; +- descriptorStruct.mchStraps.padding[2465] = 0xff; +- descriptorStruct.mchStraps.padding[2466] = 0xff; +- descriptorStruct.mchStraps.padding[2467] = 0xff; +- descriptorStruct.mchStraps.padding[2468] = 0xff; +- descriptorStruct.mchStraps.padding[2469] = 0xff; +- descriptorStruct.mchStraps.padding[2470] = 0xff; +- descriptorStruct.mchStraps.padding[2471] = 0xff; +- descriptorStruct.mchStraps.padding[2472] = 0xff; +- descriptorStruct.mchStraps.padding[2473] = 0xff; +- descriptorStruct.mchStraps.padding[2474] = 0xff; +- descriptorStruct.mchStraps.padding[2475] = 0xff; +- descriptorStruct.mchStraps.padding[2476] = 0xff; +- descriptorStruct.mchStraps.padding[2477] = 0xff; +- descriptorStruct.mchStraps.padding[2478] = 0xff; +- descriptorStruct.mchStraps.padding[2479] = 0xff; +- descriptorStruct.mchStraps.padding[2480] = 0xff; +- descriptorStruct.mchStraps.padding[2481] = 0xff; +- descriptorStruct.mchStraps.padding[2482] = 0xff; +- descriptorStruct.mchStraps.padding[2483] = 0xff; +- descriptorStruct.mchStraps.padding[2484] = 0xff; +- descriptorStruct.mchStraps.padding[2485] = 0xff; +- descriptorStruct.mchStraps.padding[2486] = 0xff; +- descriptorStruct.mchStraps.padding[2487] = 0xff; +- descriptorStruct.mchStraps.padding[2488] = 0xff; +- descriptorStruct.mchStraps.padding[2489] = 0xff; +- descriptorStruct.mchStraps.padding[2490] = 0xff; +- descriptorStruct.mchStraps.padding[2491] = 0xff; +- descriptorStruct.mchStraps.padding[2492] = 0xff; +- descriptorStruct.mchStraps.padding[2493] = 0xff; +- descriptorStruct.mchStraps.padding[2494] = 0xff; +- descriptorStruct.mchStraps.padding[2495] = 0xff; +- descriptorStruct.mchStraps.padding[2496] = 0xff; +- descriptorStruct.mchStraps.padding[2497] = 0xff; +- descriptorStruct.mchStraps.padding[2498] = 0xff; +- descriptorStruct.mchStraps.padding[2499] = 0xff; +- descriptorStruct.mchStraps.padding[2500] = 0xff; +- descriptorStruct.mchStraps.padding[2501] = 0xff; +- descriptorStruct.mchStraps.padding[2502] = 0xff; +- descriptorStruct.mchStraps.padding[2503] = 0xff; +- descriptorStruct.mchStraps.padding[2504] = 0xff; +- descriptorStruct.mchStraps.padding[2505] = 0xff; +- descriptorStruct.mchStraps.padding[2506] = 0xff; +- descriptorStruct.mchStraps.padding[2507] = 0xff; +- descriptorStruct.mchStraps.padding[2508] = 0xff; +- descriptorStruct.mchStraps.padding[2509] = 0xff; +- descriptorStruct.mchStraps.padding[2510] = 0xff; +- descriptorStruct.mchStraps.padding[2511] = 0xff; +- descriptorStruct.mchStraps.padding[2512] = 0xff; +- descriptorStruct.mchStraps.padding[2513] = 0xff; +- descriptorStruct.mchStraps.padding[2514] = 0xff; +- descriptorStruct.mchStraps.padding[2515] = 0xff; +- descriptorStruct.mchStraps.padding[2516] = 0xff; +- descriptorStruct.mchStraps.padding[2517] = 0xff; +- descriptorStruct.mchStraps.padding[2518] = 0xff; +- descriptorStruct.mchStraps.padding[2519] = 0xff; +- descriptorStruct.mchStraps.padding[2520] = 0xff; +- descriptorStruct.mchStraps.padding[2521] = 0xff; +- descriptorStruct.mchStraps.padding[2522] = 0xff; +- descriptorStruct.mchStraps.padding[2523] = 0xff; +- descriptorStruct.mchStraps.padding[2524] = 0xff; +- descriptorStruct.mchStraps.padding[2525] = 0xff; +- descriptorStruct.mchStraps.padding[2526] = 0xff; +- descriptorStruct.mchStraps.padding[2527] = 0xff; +- descriptorStruct.mchStraps.padding[2528] = 0xff; +- descriptorStruct.mchStraps.padding[2529] = 0xff; +- descriptorStruct.mchStraps.padding[2530] = 0xff; +- descriptorStruct.mchStraps.padding[2531] = 0xff; +- descriptorStruct.mchStraps.padding[2532] = 0xff; +- descriptorStruct.mchStraps.padding[2533] = 0xff; +- descriptorStruct.mchStraps.padding[2534] = 0xff; +- descriptorStruct.mchStraps.padding[2535] = 0xff; +- descriptorStruct.mchStraps.padding[2536] = 0xff; +- descriptorStruct.mchStraps.padding[2537] = 0xff; +- descriptorStruct.mchStraps.padding[2538] = 0xff; +- descriptorStruct.mchStraps.padding[2539] = 0xff; +- descriptorStruct.mchStraps.padding[2540] = 0xff; +- descriptorStruct.mchStraps.padding[2541] = 0xff; +- descriptorStruct.mchStraps.padding[2542] = 0xff; +- descriptorStruct.mchStraps.padding[2543] = 0xff; +- descriptorStruct.mchStraps.padding[2544] = 0xff; +- descriptorStruct.mchStraps.padding[2545] = 0xff; +- descriptorStruct.mchStraps.padding[2546] = 0xff; +- descriptorStruct.mchStraps.padding[2547] = 0xff; +- descriptorStruct.mchStraps.padding[2548] = 0xff; +- descriptorStruct.mchStraps.padding[2549] = 0xff; +- descriptorStruct.mchStraps.padding[2550] = 0xff; +- descriptorStruct.mchStraps.padding[2551] = 0xff; +- descriptorStruct.mchStraps.padding[2552] = 0xff; +- descriptorStruct.mchStraps.padding[2553] = 0xff; +- descriptorStruct.mchStraps.padding[2554] = 0xff; +- descriptorStruct.mchStraps.padding[2555] = 0xff; +- descriptorStruct.mchStraps.padding[2556] = 0xff; +- descriptorStruct.mchStraps.padding[2557] = 0xff; +- descriptorStruct.mchStraps.padding[2558] = 0xff; +- descriptorStruct.mchStraps.padding[2559] = 0xff; +- descriptorStruct.mchStraps.padding[2560] = 0xff; +- descriptorStruct.mchStraps.padding[2561] = 0xff; +- descriptorStruct.mchStraps.padding[2562] = 0xff; +- descriptorStruct.mchStraps.padding[2563] = 0xff; +- descriptorStruct.mchStraps.padding[2564] = 0xff; +- descriptorStruct.mchStraps.padding[2565] = 0xff; +- descriptorStruct.mchStraps.padding[2566] = 0xff; +- descriptorStruct.mchStraps.padding[2567] = 0xff; +- descriptorStruct.mchStraps.padding[2568] = 0xff; +- descriptorStruct.mchStraps.padding[2569] = 0xff; +- descriptorStruct.mchStraps.padding[2570] = 0xff; +- descriptorStruct.mchStraps.padding[2571] = 0xff; +- descriptorStruct.mchStraps.padding[2572] = 0xff; +- descriptorStruct.mchStraps.padding[2573] = 0xff; +- descriptorStruct.mchStraps.padding[2574] = 0xff; +- descriptorStruct.mchStraps.padding[2575] = 0xff; +- descriptorStruct.mchStraps.padding[2576] = 0xff; +- descriptorStruct.mchStraps.padding[2577] = 0xff; +- descriptorStruct.mchStraps.padding[2578] = 0xff; +- descriptorStruct.mchStraps.padding[2579] = 0xff; +- descriptorStruct.mchStraps.padding[2580] = 0xff; +- descriptorStruct.mchStraps.padding[2581] = 0xff; +- descriptorStruct.mchStraps.padding[2582] = 0xff; +- descriptorStruct.mchStraps.padding[2583] = 0xff; +- descriptorStruct.mchStraps.padding[2584] = 0xff; +- descriptorStruct.mchStraps.padding[2585] = 0xff; +- descriptorStruct.mchStraps.padding[2586] = 0xff; +- descriptorStruct.mchStraps.padding[2587] = 0xff; +- descriptorStruct.mchStraps.padding[2588] = 0xff; +- descriptorStruct.mchStraps.padding[2589] = 0xff; +- descriptorStruct.mchStraps.padding[2590] = 0xff; +- descriptorStruct.mchStraps.padding[2591] = 0xff; +- descriptorStruct.mchStraps.padding[2592] = 0xff; +- descriptorStruct.mchStraps.padding[2593] = 0xff; +- descriptorStruct.mchStraps.padding[2594] = 0xff; +- descriptorStruct.mchStraps.padding[2595] = 0xff; +- descriptorStruct.mchStraps.padding[2596] = 0xff; +- descriptorStruct.mchStraps.padding[2597] = 0xff; +- descriptorStruct.mchStraps.padding[2598] = 0xff; +- descriptorStruct.mchStraps.padding[2599] = 0xff; +- descriptorStruct.mchStraps.padding[2600] = 0xff; +- descriptorStruct.mchStraps.padding[2601] = 0xff; +- descriptorStruct.mchStraps.padding[2602] = 0xff; +- descriptorStruct.mchStraps.padding[2603] = 0xff; +- descriptorStruct.mchStraps.padding[2604] = 0xff; +- descriptorStruct.mchStraps.padding[2605] = 0xff; +- descriptorStruct.mchStraps.padding[2606] = 0xff; +- descriptorStruct.mchStraps.padding[2607] = 0xff; +- descriptorStruct.mchStraps.padding[2608] = 0xff; +- descriptorStruct.mchStraps.padding[2609] = 0xff; +- descriptorStruct.mchStraps.padding[2610] = 0xff; +- descriptorStruct.mchStraps.padding[2611] = 0xff; +- descriptorStruct.mchStraps.padding[2612] = 0xff; +- descriptorStruct.mchStraps.padding[2613] = 0xff; +- descriptorStruct.mchStraps.padding[2614] = 0xff; +- descriptorStruct.mchStraps.padding[2615] = 0xff; +- descriptorStruct.mchStraps.padding[2616] = 0xff; +- descriptorStruct.mchStraps.padding[2617] = 0xff; +- descriptorStruct.mchStraps.padding[2618] = 0xff; +- descriptorStruct.mchStraps.padding[2619] = 0xff; +- descriptorStruct.mchStraps.padding[2620] = 0xff; +- descriptorStruct.mchStraps.padding[2621] = 0xff; +- descriptorStruct.mchStraps.padding[2622] = 0xff; +- descriptorStruct.mchStraps.padding[2623] = 0xff; +- descriptorStruct.mchStraps.padding[2624] = 0xff; +- descriptorStruct.mchStraps.padding[2625] = 0xff; +- descriptorStruct.mchStraps.padding[2626] = 0xff; +- descriptorStruct.mchStraps.padding[2627] = 0xff; +- descriptorStruct.mchStraps.padding[2628] = 0xff; +- descriptorStruct.mchStraps.padding[2629] = 0xff; +- descriptorStruct.mchStraps.padding[2630] = 0xff; +- descriptorStruct.mchStraps.padding[2631] = 0xff; +- descriptorStruct.mchStraps.padding[2632] = 0xff; +- descriptorStruct.mchStraps.padding[2633] = 0xff; +- descriptorStruct.mchStraps.padding[2634] = 0xff; +- descriptorStruct.mchStraps.padding[2635] = 0xff; +- descriptorStruct.mchStraps.padding[2636] = 0xff; +- descriptorStruct.mchStraps.padding[2637] = 0xff; +- descriptorStruct.mchStraps.padding[2638] = 0xff; +- descriptorStruct.mchStraps.padding[2639] = 0xff; +- descriptorStruct.mchStraps.padding[2640] = 0xff; +- descriptorStruct.mchStraps.padding[2641] = 0xff; +- descriptorStruct.mchStraps.padding[2642] = 0xff; +- descriptorStruct.mchStraps.padding[2643] = 0xff; +- descriptorStruct.mchStraps.padding[2644] = 0xff; +- descriptorStruct.mchStraps.padding[2645] = 0xff; +- descriptorStruct.mchStraps.padding[2646] = 0xff; +- descriptorStruct.mchStraps.padding[2647] = 0xff; +- descriptorStruct.mchStraps.padding[2648] = 0xff; +- descriptorStruct.mchStraps.padding[2649] = 0xff; +- descriptorStruct.mchStraps.padding[2650] = 0xff; +- descriptorStruct.mchStraps.padding[2651] = 0xff; +- descriptorStruct.mchStraps.padding[2652] = 0xff; +- descriptorStruct.mchStraps.padding[2653] = 0xff; +- descriptorStruct.mchStraps.padding[2654] = 0xff; +- descriptorStruct.mchStraps.padding[2655] = 0xff; +- descriptorStruct.mchStraps.padding[2656] = 0xff; +- descriptorStruct.mchStraps.padding[2657] = 0xff; +- descriptorStruct.mchStraps.padding[2658] = 0xff; +- descriptorStruct.mchStraps.padding[2659] = 0xff; +- descriptorStruct.mchStraps.padding[2660] = 0xff; +- descriptorStruct.mchStraps.padding[2661] = 0xff; +- descriptorStruct.mchStraps.padding[2662] = 0xff; +- descriptorStruct.mchStraps.padding[2663] = 0xff; +- descriptorStruct.mchStraps.padding[2664] = 0xff; +- descriptorStruct.mchStraps.padding[2665] = 0xff; +- descriptorStruct.mchStraps.padding[2666] = 0xff; +- descriptorStruct.mchStraps.padding[2667] = 0xff; +- descriptorStruct.mchStraps.padding[2668] = 0xff; +- descriptorStruct.mchStraps.padding[2669] = 0xff; +- descriptorStruct.mchStraps.padding[2670] = 0xff; +- descriptorStruct.mchStraps.padding[2671] = 0xff; +- descriptorStruct.mchStraps.padding[2672] = 0xff; +- descriptorStruct.mchStraps.padding[2673] = 0xff; +- descriptorStruct.mchStraps.padding[2674] = 0xff; +- descriptorStruct.mchStraps.padding[2675] = 0xff; +- descriptorStruct.mchStraps.padding[2676] = 0xff; +- descriptorStruct.mchStraps.padding[2677] = 0xff; +- descriptorStruct.mchStraps.padding[2678] = 0xff; +- descriptorStruct.mchStraps.padding[2679] = 0xff; +- descriptorStruct.mchStraps.padding[2680] = 0xff; +- descriptorStruct.mchStraps.padding[2681] = 0xff; +- descriptorStruct.mchStraps.padding[2682] = 0xff; +- descriptorStruct.mchStraps.padding[2683] = 0xff; +- descriptorStruct.mchStraps.padding[2684] = 0xff; +- descriptorStruct.mchStraps.padding[2685] = 0xff; +- descriptorStruct.mchStraps.padding[2686] = 0xff; +- descriptorStruct.mchStraps.padding[2687] = 0xff; +- descriptorStruct.mchStraps.padding[2688] = 0xff; +- descriptorStruct.mchStraps.padding[2689] = 0xff; +- descriptorStruct.mchStraps.padding[2690] = 0xff; +- descriptorStruct.mchStraps.padding[2691] = 0xff; +- descriptorStruct.mchStraps.padding[2692] = 0xff; +- descriptorStruct.mchStraps.padding[2693] = 0xff; +- descriptorStruct.mchStraps.padding[2694] = 0xff; +- descriptorStruct.mchStraps.padding[2695] = 0xff; +- descriptorStruct.mchStraps.padding[2696] = 0xff; +- descriptorStruct.mchStraps.padding[2697] = 0xff; +- descriptorStruct.mchStraps.padding[2698] = 0xff; +- descriptorStruct.mchStraps.padding[2699] = 0xff; +- descriptorStruct.mchStraps.padding[2700] = 0xff; +- descriptorStruct.mchStraps.padding[2701] = 0xff; +- descriptorStruct.mchStraps.padding[2702] = 0xff; +- descriptorStruct.mchStraps.padding[2703] = 0xff; +- descriptorStruct.mchStraps.padding[2704] = 0xff; +- descriptorStruct.mchStraps.padding[2705] = 0xff; +- descriptorStruct.mchStraps.padding[2706] = 0xff; +- descriptorStruct.mchStraps.padding[2707] = 0xff; +- descriptorStruct.mchStraps.padding[2708] = 0xff; +- descriptorStruct.mchStraps.padding[2709] = 0xff; +- descriptorStruct.mchStraps.padding[2710] = 0xff; +- descriptorStruct.mchStraps.padding[2711] = 0xff; +- descriptorStruct.mchStraps.padding[2712] = 0xff; +- descriptorStruct.mchStraps.padding[2713] = 0xff; +- descriptorStruct.mchStraps.padding[2714] = 0xff; +- descriptorStruct.mchStraps.padding[2715] = 0xff; +- descriptorStruct.mchStraps.padding[2716] = 0xff; +- descriptorStruct.mchStraps.padding[2717] = 0xff; +- descriptorStruct.mchStraps.padding[2718] = 0xff; +- descriptorStruct.mchStraps.padding[2719] = 0xff; +- descriptorStruct.mchStraps.padding[2720] = 0xff; +- descriptorStruct.mchStraps.padding[2721] = 0xff; +- descriptorStruct.mchStraps.padding[2722] = 0xff; +- descriptorStruct.mchStraps.padding[2723] = 0xff; +- descriptorStruct.mchStraps.padding[2724] = 0xff; +- descriptorStruct.mchStraps.padding[2725] = 0xff; +- descriptorStruct.mchStraps.padding[2726] = 0xff; +- descriptorStruct.mchStraps.padding[2727] = 0xff; +- descriptorStruct.mchStraps.padding[2728] = 0xff; +- descriptorStruct.mchStraps.padding[2729] = 0xff; +- descriptorStruct.mchStraps.padding[2730] = 0xff; +- descriptorStruct.mchStraps.padding[2731] = 0xff; +- descriptorStruct.mchStraps.padding[2732] = 0xff; +- descriptorStruct.mchStraps.padding[2733] = 0xff; +- descriptorStruct.mchStraps.padding[2734] = 0xff; +- descriptorStruct.mchStraps.padding[2735] = 0xff; +- descriptorStruct.mchStraps.padding[2736] = 0xff; +- descriptorStruct.mchStraps.padding[2737] = 0xff; +- descriptorStruct.mchStraps.padding[2738] = 0xff; +- descriptorStruct.mchStraps.padding[2739] = 0xff; +- descriptorStruct.mchStraps.padding[2740] = 0xff; +- descriptorStruct.mchStraps.padding[2741] = 0xff; +- descriptorStruct.mchStraps.padding[2742] = 0xff; +- descriptorStruct.mchStraps.padding[2743] = 0xff; +- descriptorStruct.mchStraps.padding[2744] = 0xff; +- descriptorStruct.mchStraps.padding[2745] = 0xff; +- descriptorStruct.mchStraps.padding[2746] = 0xff; +- descriptorStruct.mchStraps.padding[2747] = 0xff; +- descriptorStruct.mchStraps.padding[2748] = 0xff; +- descriptorStruct.mchStraps.padding[2749] = 0xff; +- descriptorStruct.mchStraps.padding[2750] = 0xff; +- descriptorStruct.mchStraps.padding[2751] = 0xff; +- descriptorStruct.mchStraps.padding[2752] = 0xff; +- descriptorStruct.mchStraps.padding[2753] = 0xff; +- descriptorStruct.mchStraps.padding[2754] = 0xff; +- descriptorStruct.mchStraps.padding[2755] = 0xff; +- descriptorStruct.mchStraps.padding[2756] = 0xff; +- descriptorStruct.mchStraps.padding[2757] = 0xff; +- descriptorStruct.mchStraps.padding[2758] = 0xff; +- descriptorStruct.mchStraps.padding[2759] = 0xff; +- descriptorStruct.mchStraps.padding[2760] = 0xff; +- descriptorStruct.mchStraps.padding[2761] = 0xff; +- descriptorStruct.mchStraps.padding[2762] = 0xff; +- descriptorStruct.mchStraps.padding[2763] = 0xff; +- descriptorStruct.mchStraps.padding[2764] = 0xff; +- descriptorStruct.mchStraps.padding[2765] = 0xff; +- descriptorStruct.mchStraps.padding[2766] = 0xff; +- descriptorStruct.mchStraps.padding[2767] = 0xff; +- descriptorStruct.mchStraps.padding[2768] = 0xff; +- descriptorStruct.mchStraps.padding[2769] = 0xff; +- descriptorStruct.mchStraps.padding[2770] = 0xff; +- descriptorStruct.mchStraps.padding[2771] = 0xff; +- descriptorStruct.mchStraps.padding[2772] = 0xff; +- descriptorStruct.mchStraps.padding[2773] = 0xff; +- descriptorStruct.mchStraps.padding[2774] = 0xff; +- descriptorStruct.mchStraps.padding[2775] = 0xff; +- descriptorStruct.mchStraps.padding[2776] = 0xff; +- descriptorStruct.mchStraps.padding[2777] = 0xff; +- descriptorStruct.mchStraps.padding[2778] = 0xff; +- descriptorStruct.mchStraps.padding[2779] = 0xff; +- descriptorStruct.mchStraps.padding[2780] = 0xff; +- descriptorStruct.mchStraps.padding[2781] = 0xff; +- descriptorStruct.mchStraps.padding[2782] = 0xff; +- descriptorStruct.mchStraps.padding[2783] = 0xff; +- descriptorStruct.mchStraps.padding[2784] = 0xff; +- descriptorStruct.mchStraps.padding[2785] = 0xff; +- descriptorStruct.mchStraps.padding[2786] = 0xff; +- descriptorStruct.mchStraps.padding[2787] = 0xff; +- descriptorStruct.mchStraps.padding[2788] = 0xff; +- descriptorStruct.mchStraps.padding[2789] = 0xff; +- descriptorStruct.mchStraps.padding[2790] = 0xff; +- descriptorStruct.mchStraps.padding[2791] = 0xff; +- descriptorStruct.mchStraps.padding[2792] = 0xff; +- descriptorStruct.mchStraps.padding[2793] = 0xff; +- descriptorStruct.mchStraps.padding[2794] = 0xff; +- descriptorStruct.mchStraps.padding[2795] = 0xff; +- descriptorStruct.mchStraps.padding[2796] = 0xff; +- descriptorStruct.mchStraps.padding[2797] = 0xff; +- descriptorStruct.mchStraps.padding[2798] = 0xff; +- descriptorStruct.mchStraps.padding[2799] = 0xff; +- descriptorStruct.mchStraps.padding[2800] = 0xff; +- descriptorStruct.mchStraps.padding[2801] = 0xff; +- descriptorStruct.mchStraps.padding[2802] = 0xff; +- descriptorStruct.mchStraps.padding[2803] = 0xff; +- descriptorStruct.mchStraps.padding[2804] = 0xff; +- descriptorStruct.mchStraps.padding[2805] = 0xff; +- descriptorStruct.mchStraps.padding[2806] = 0xff; +- descriptorStruct.mchStraps.padding[2807] = 0xff; +- descriptorStruct.mchStraps.padding[2808] = 0xff; +- descriptorStruct.mchStraps.padding[2809] = 0xff; +- descriptorStruct.mchStraps.padding[2810] = 0xff; +- descriptorStruct.mchStraps.padding[2811] = 0xff; +- descriptorStruct.mchStraps.padding[2812] = 0xff; +- descriptorStruct.mchStraps.padding[2813] = 0xff; +- descriptorStruct.mchStraps.padding[2814] = 0xff; +- descriptorStruct.mchStraps.padding[2815] = 0xff; +- descriptorStruct.mchStraps.padding[2816] = 0xff; +- descriptorStruct.mchStraps.padding[2817] = 0xff; +- descriptorStruct.mchStraps.padding[2818] = 0xff; +- descriptorStruct.mchStraps.padding[2819] = 0xff; +- descriptorStruct.mchStraps.padding[2820] = 0xff; +- descriptorStruct.mchStraps.padding[2821] = 0xff; +- descriptorStruct.mchStraps.padding[2822] = 0xff; +- descriptorStruct.mchStraps.padding[2823] = 0xff; +- descriptorStruct.mchStraps.padding[2824] = 0xff; +- descriptorStruct.mchStraps.padding[2825] = 0xff; +- descriptorStruct.mchStraps.padding[2826] = 0xff; +- descriptorStruct.mchStraps.padding[2827] = 0xff; +- descriptorStruct.mchStraps.padding[2828] = 0xff; +- descriptorStruct.mchStraps.padding[2829] = 0xff; +- descriptorStruct.mchStraps.padding[2830] = 0xff; +- descriptorStruct.mchStraps.padding[2831] = 0xff; +- descriptorStruct.mchStraps.padding[2832] = 0xff; +- descriptorStruct.mchStraps.padding[2833] = 0xff; +- descriptorStruct.mchStraps.padding[2834] = 0xff; +- descriptorStruct.mchStraps.padding[2835] = 0xff; +- descriptorStruct.mchStraps.padding[2836] = 0xff; +- descriptorStruct.mchStraps.padding[2837] = 0xff; +- descriptorStruct.mchStraps.padding[2838] = 0xff; +- descriptorStruct.mchStraps.padding[2839] = 0xff; +- descriptorStruct.mchStraps.padding[2840] = 0xff; +- descriptorStruct.mchStraps.padding[2841] = 0xff; +- descriptorStruct.mchStraps.padding[2842] = 0xff; +- descriptorStruct.mchStraps.padding[2843] = 0xff; +- descriptorStruct.mchStraps.padding[2844] = 0xff; +- descriptorStruct.mchStraps.padding[2845] = 0xff; +- descriptorStruct.mchStraps.padding[2846] = 0xff; +- descriptorStruct.mchStraps.padding[2847] = 0xff; +- descriptorStruct.mchStraps.padding[2848] = 0xff; +- descriptorStruct.mchStraps.padding[2849] = 0xff; +- descriptorStruct.mchStraps.padding[2850] = 0xff; +- descriptorStruct.mchStraps.padding[2851] = 0xff; +- descriptorStruct.mchStraps.padding[2852] = 0xff; +- descriptorStruct.mchStraps.padding[2853] = 0xff; +- descriptorStruct.mchStraps.padding[2854] = 0xff; +- descriptorStruct.mchStraps.padding[2855] = 0xff; +- descriptorStruct.mchStraps.padding[2856] = 0xff; +- descriptorStruct.mchStraps.padding[2857] = 0xff; +- descriptorStruct.mchStraps.padding[2858] = 0xff; +- descriptorStruct.mchStraps.padding[2859] = 0xff; +- descriptorStruct.mchStraps.padding[2860] = 0xff; +- descriptorStruct.mchStraps.padding[2861] = 0xff; +- descriptorStruct.mchStraps.padding[2862] = 0xff; +- descriptorStruct.mchStraps.padding[2863] = 0xff; +- descriptorStruct.mchStraps.padding[2864] = 0xff; +- descriptorStruct.mchStraps.padding[2865] = 0xff; +- descriptorStruct.mchStraps.padding[2866] = 0xff; +- descriptorStruct.mchStraps.padding[2867] = 0xff; +- descriptorStruct.mchStraps.padding[2868] = 0xff; +- descriptorStruct.mchStraps.padding[2869] = 0xff; +- descriptorStruct.mchStraps.padding[2870] = 0xff; +- descriptorStruct.mchStraps.padding[2871] = 0xff; +- descriptorStruct.mchStraps.padding[2872] = 0xff; +- descriptorStruct.mchStraps.padding[2873] = 0xff; +- descriptorStruct.mchStraps.padding[2874] = 0xff; +- descriptorStruct.mchStraps.padding[2875] = 0xff; +- descriptorStruct.mchStraps.padding[2876] = 0xff; +- descriptorStruct.mchStraps.padding[2877] = 0xff; +- descriptorStruct.mchStraps.padding[2878] = 0xff; +- descriptorStruct.mchStraps.padding[2879] = 0xff; +- descriptorStruct.mchStraps.padding[2880] = 0xff; +- descriptorStruct.mchStraps.padding[2881] = 0xff; +- descriptorStruct.mchStraps.padding[2882] = 0xff; +- descriptorStruct.mchStraps.padding[2883] = 0xff; +- descriptorStruct.mchStraps.padding[2884] = 0xff; +- descriptorStruct.mchStraps.padding[2885] = 0xff; +- descriptorStruct.mchStraps.padding[2886] = 0xff; +- descriptorStruct.mchStraps.padding[2887] = 0xff; +- descriptorStruct.mchStraps.padding[2888] = 0xff; +- descriptorStruct.mchStraps.padding[2889] = 0xff; +- descriptorStruct.mchStraps.padding[2890] = 0xff; +- descriptorStruct.mchStraps.padding[2891] = 0xff; +- descriptorStruct.mchStraps.padding[2892] = 0xff; +- descriptorStruct.mchStraps.padding[2893] = 0xff; +- descriptorStruct.mchStraps.padding[2894] = 0xff; +- descriptorStruct.mchStraps.padding[2895] = 0xff; +- descriptorStruct.mchStraps.padding[2896] = 0xff; +- descriptorStruct.mchStraps.padding[2897] = 0xff; +- descriptorStruct.mchStraps.padding[2898] = 0xff; +- descriptorStruct.mchStraps.padding[2899] = 0xff; +- descriptorStruct.mchStraps.padding[2900] = 0xff; +- descriptorStruct.mchStraps.padding[2901] = 0xff; +- descriptorStruct.mchStraps.padding[2902] = 0xff; +- descriptorStruct.mchStraps.padding[2903] = 0xff; +- descriptorStruct.mchStraps.padding[2904] = 0xff; +- descriptorStruct.mchStraps.padding[2905] = 0xff; +- descriptorStruct.mchStraps.padding[2906] = 0xff; +- descriptorStruct.mchStraps.padding[2907] = 0xff; +- descriptorStruct.mchStraps.padding[2908] = 0xff; +- descriptorStruct.mchStraps.padding[2909] = 0xff; +- descriptorStruct.mchStraps.padding[2910] = 0xff; +- descriptorStruct.mchStraps.padding[2911] = 0xff; +- descriptorStruct.mchStraps.padding[2912] = 0xff; +- descriptorStruct.mchStraps.padding[2913] = 0xff; +- descriptorStruct.mchStraps.padding[2914] = 0xff; +- descriptorStruct.mchStraps.padding[2915] = 0xff; +- descriptorStruct.mchStraps.padding[2916] = 0xff; +- descriptorStruct.mchStraps.padding[2917] = 0xff; +- descriptorStruct.mchStraps.padding[2918] = 0xff; +- descriptorStruct.mchStraps.padding[2919] = 0xff; +- descriptorStruct.mchStraps.padding[2920] = 0xff; +- descriptorStruct.mchStraps.padding[2921] = 0xff; +- descriptorStruct.mchStraps.padding[2922] = 0xff; +- descriptorStruct.mchStraps.padding[2923] = 0xff; +- descriptorStruct.mchStraps.padding[2924] = 0xff; +- descriptorStruct.mchStraps.padding[2925] = 0xff; +- descriptorStruct.mchStraps.padding[2926] = 0xff; +- descriptorStruct.mchStraps.padding[2927] = 0xff; +- descriptorStruct.mchStraps.padding[2928] = 0xff; +- descriptorStruct.mchStraps.padding[2929] = 0xff; +- descriptorStruct.mchStraps.padding[2930] = 0xff; +- descriptorStruct.mchStraps.padding[2931] = 0xff; +- descriptorStruct.mchStraps.padding[2932] = 0xff; +- descriptorStruct.mchStraps.padding[2933] = 0xff; +- descriptorStruct.mchStraps.padding[2934] = 0xff; +- descriptorStruct.mchStraps.padding[2935] = 0xff; +- descriptorStruct.mchStraps.padding[2936] = 0xff; +- descriptorStruct.mchStraps.padding[2937] = 0xff; +- descriptorStruct.mchStraps.padding[2938] = 0xff; +- descriptorStruct.mchStraps.padding[2939] = 0xff; +- descriptorStruct.mchStraps.padding[2940] = 0xff; +- descriptorStruct.mchStraps.padding[2941] = 0xff; +- descriptorStruct.mchStraps.padding[2942] = 0xff; +- descriptorStruct.mchStraps.padding[2943] = 0xff; +- descriptorStruct.mchStraps.padding[2944] = 0xff; +- descriptorStruct.mchStraps.padding[2945] = 0xff; +- descriptorStruct.mchStraps.padding[2946] = 0xff; +- descriptorStruct.mchStraps.padding[2947] = 0xff; +- descriptorStruct.mchStraps.padding[2948] = 0xff; +- descriptorStruct.mchStraps.padding[2949] = 0xff; +- descriptorStruct.mchStraps.padding[2950] = 0xff; +- descriptorStruct.mchStraps.padding[2951] = 0xff; +- descriptorStruct.mchStraps.padding[2952] = 0xff; +- descriptorStruct.mchStraps.padding[2953] = 0xff; +- descriptorStruct.mchStraps.padding[2954] = 0xff; +- descriptorStruct.mchStraps.padding[2955] = 0xff; +- descriptorStruct.mchStraps.padding[2956] = 0xff; +- descriptorStruct.mchStraps.padding[2957] = 0xff; +- descriptorStruct.mchStraps.padding[2958] = 0xff; +- descriptorStruct.mchStraps.padding[2959] = 0xff; +- descriptorStruct.mchStraps.padding[2960] = 0xff; +- descriptorStruct.mchStraps.padding[2961] = 0xff; +- descriptorStruct.mchStraps.padding[2962] = 0xff; +- descriptorStruct.mchStraps.padding[2963] = 0xff; +- descriptorStruct.mchStraps.padding[2964] = 0xff; +- descriptorStruct.mchStraps.padding[2965] = 0xff; +- descriptorStruct.mchStraps.padding[2966] = 0xff; +- descriptorStruct.mchStraps.padding[2967] = 0xff; +- descriptorStruct.mchStraps.padding[2968] = 0xff; +- descriptorStruct.mchStraps.padding[2969] = 0xff; +- descriptorStruct.mchStraps.padding[2970] = 0xff; +- descriptorStruct.mchStraps.padding[2971] = 0xff; +- descriptorStruct.mchStraps.padding[2972] = 0xff; +- descriptorStruct.mchStraps.padding[2973] = 0xff; +- descriptorStruct.mchStraps.padding[2974] = 0xff; +- descriptorStruct.mchStraps.padding[2975] = 0xff; +- descriptorStruct.mchStraps.padding[2976] = 0xff; +- descriptorStruct.mchStraps.padding[2977] = 0xff; +- descriptorStruct.mchStraps.padding[2978] = 0xff; +- descriptorStruct.mchStraps.padding[2979] = 0xff; +- descriptorStruct.mchStraps.padding[2980] = 0xff; +- descriptorStruct.mchStraps.padding[2981] = 0xff; +- descriptorStruct.mchStraps.padding[2982] = 0xff; +- descriptorStruct.mchStraps.padding[2983] = 0xff; +- descriptorStruct.mchStraps.padding[2984] = 0xff; +- descriptorStruct.mchStraps.padding[2985] = 0xff; +- descriptorStruct.mchStraps.padding[2986] = 0xff; +- descriptorStruct.mchStraps.padding[2987] = 0xff; +- descriptorStruct.mchStraps.padding[2988] = 0xff; +- descriptorStruct.mchStraps.padding[2989] = 0xff; +- descriptorStruct.mchStraps.padding[2990] = 0xff; +- descriptorStruct.mchStraps.padding[2991] = 0xff; +- descriptorStruct.mchStraps.padding[2992] = 0xff; +- descriptorStruct.mchStraps.padding[2993] = 0xff; +- descriptorStruct.mchStraps.padding[2994] = 0xff; +- descriptorStruct.mchStraps.padding[2995] = 0xff; +- descriptorStruct.mchStraps.padding[2996] = 0xff; +- descriptorStruct.mchStraps.padding[2997] = 0xff; +- descriptorStruct.mchStraps.padding[2998] = 0xff; +- descriptorStruct.mchStraps.padding[2999] = 0xff; +- descriptorStruct.mchStraps.padding[3000] = 0xff; +- descriptorStruct.mchStraps.padding[3001] = 0xff; +- descriptorStruct.mchStraps.padding[3002] = 0xff; +- descriptorStruct.mchStraps.padding[3003] = 0xff; +- descriptorStruct.mchStraps.padding[3004] = 0xff; +- descriptorStruct.mchStraps.padding[3005] = 0xff; +- descriptorStruct.mchStraps.padding[3006] = 0xff; +- descriptorStruct.mchStraps.padding[3007] = 0xff; +- descriptorStruct.mchStraps.padding[3008] = 0xff; +- descriptorStruct.mchStraps.padding[3009] = 0xff; +- descriptorStruct.mchStraps.padding[3010] = 0xff; +- descriptorStruct.mchStraps.padding[3011] = 0xff; +- descriptorStruct.mchStraps.padding[3012] = 0xff; +- descriptorStruct.mchStraps.padding[3013] = 0xff; +- descriptorStruct.mchStraps.padding[3014] = 0xff; +- descriptorStruct.mchStraps.padding[3015] = 0xff; +- descriptorStruct.mchStraps.padding[3016] = 0xff; +- descriptorStruct.mchStraps.padding[3017] = 0xff; +- descriptorStruct.mchStraps.padding[3018] = 0xff; +- descriptorStruct.mchStraps.padding[3019] = 0xff; +- descriptorStruct.mchStraps.padding[3020] = 0xff; +- descriptorStruct.mchStraps.padding[3021] = 0xff; +- descriptorStruct.mchStraps.padding[3022] = 0xff; +- descriptorStruct.mchStraps.padding[3023] = 0xff; +- descriptorStruct.mchStraps.padding[3024] = 0xff; +- descriptorStruct.mchStraps.padding[3025] = 0xff; +- descriptorStruct.mchStraps.padding[3026] = 0xff; +- descriptorStruct.mchStraps.padding[3027] = 0xff; +- descriptorStruct.mchStraps.padding[3028] = 0xff; +- descriptorStruct.mchStraps.padding[3029] = 0xff; +- descriptorStruct.mchStraps.padding[3030] = 0xff; +- descriptorStruct.mchStraps.padding[3031] = 0xff; +- descriptorStruct.mchStraps.padding[3032] = 0xff; +- descriptorStruct.mchStraps.padding[3033] = 0xff; +- descriptorStruct.mchStraps.padding[3034] = 0xff; +- descriptorStruct.mchStraps.padding[3035] = 0xff; +- descriptorStruct.mchStraps.padding[3036] = 0xff; +- descriptorStruct.mchStraps.padding[3037] = 0xff; +- descriptorStruct.mchStraps.padding[3038] = 0xff; +- descriptorStruct.mchStraps.padding[3039] = 0xff; +- descriptorStruct.mchStraps.padding[3040] = 0xff; +- descriptorStruct.mchStraps.padding[3041] = 0xff; +- descriptorStruct.mchStraps.padding[3042] = 0xff; +- descriptorStruct.mchStraps.padding[3043] = 0xff; +- descriptorStruct.mchStraps.padding[3044] = 0xff; +- descriptorStruct.mchStraps.padding[3045] = 0xff; +- descriptorStruct.mchStraps.padding[3046] = 0xff; +- descriptorStruct.mchStraps.padding[3047] = 0xff; +- descriptorStruct.mchStraps.padding[3048] = 0xff; +- descriptorStruct.mchStraps.padding[3049] = 0xff; +- descriptorStruct.mchStraps.padding[3050] = 0xff; +- descriptorStruct.mchStraps.padding[3051] = 0xff; +- descriptorStruct.mchStraps.padding[3052] = 0xff; +- descriptorStruct.mchStraps.padding[3053] = 0xff; +- descriptorStruct.mchStraps.padding[3054] = 0xff; +- descriptorStruct.mchStraps.padding[3055] = 0xff; +- descriptorStruct.mchStraps.padding[3056] = 0xff; +- descriptorStruct.mchStraps.padding[3057] = 0xff; +- descriptorStruct.mchStraps.padding[3058] = 0xff; +- descriptorStruct.mchStraps.padding[3059] = 0xff; +- descriptorStruct.mchStraps.padding[3060] = 0xff; +- descriptorStruct.mchStraps.padding[3061] = 0xff; +- descriptorStruct.mchStraps.padding[3062] = 0xff; +- descriptorStruct.mchStraps.padding[3063] = 0xff; +- descriptorStruct.mchStraps.padding[3064] = 0xff; +- descriptorStruct.mchStraps.padding[3065] = 0xff; +- descriptorStruct.mchStraps.padding[3066] = 0xff; +- descriptorStruct.mchStraps.padding[3067] = 0xff; +- descriptorStruct.mchStraps.padding[3068] = 0xff; +- descriptorStruct.mchStraps.padding[3069] = 0xff; +- descriptorStruct.mchStraps.padding[3070] = 0xff; +- descriptorStruct.mchStraps.padding[3071] = 0xff; +- descriptorStruct.mchStraps.padding[3072] = 0xff; +- descriptorStruct.mchStraps.padding[3073] = 0xff; +- descriptorStruct.mchStraps.padding[3074] = 0xff; +- descriptorStruct.mchStraps.padding[3075] = 0xff; +- descriptorStruct.mchStraps.padding[3076] = 0xff; +- descriptorStruct.mchStraps.padding[3077] = 0xff; +- descriptorStruct.mchStraps.padding[3078] = 0xff; +- descriptorStruct.mchStraps.padding[3079] = 0xff; +- descriptorStruct.mchStraps.padding[3080] = 0xff; +- descriptorStruct.mchStraps.padding[3081] = 0xff; +- descriptorStruct.mchStraps.padding[3082] = 0xff; +- descriptorStruct.mchStraps.padding[3083] = 0xff; +- descriptorStruct.mchStraps.padding[3084] = 0xff; +- descriptorStruct.mchStraps.padding[3085] = 0xff; +- descriptorStruct.mchStraps.padding[3086] = 0xff; +- descriptorStruct.mchStraps.padding[3087] = 0xff; +- descriptorStruct.mchStraps.padding[3088] = 0xff; +- descriptorStruct.mchStraps.padding[3089] = 0xff; +- descriptorStruct.mchStraps.padding[3090] = 0xff; +- descriptorStruct.mchStraps.padding[3091] = 0xff; +- descriptorStruct.mchStraps.padding[3092] = 0xff; +- descriptorStruct.mchStraps.padding[3093] = 0xff; +- descriptorStruct.mchStraps.padding[3094] = 0xff; +- descriptorStruct.mchStraps.padding[3095] = 0xff; +- descriptorStruct.mchStraps.padding[3096] = 0xff; +- descriptorStruct.mchStraps.padding[3097] = 0xff; +- descriptorStruct.mchStraps.padding[3098] = 0xff; +- descriptorStruct.mchStraps.padding[3099] = 0xff; +- descriptorStruct.mchStraps.padding[3100] = 0xff; +- descriptorStruct.mchStraps.padding[3101] = 0xff; +- descriptorStruct.mchStraps.padding[3102] = 0xff; +- descriptorStruct.mchStraps.padding[3103] = 0xff; +- descriptorStruct.mchStraps.padding[3104] = 0xff; +- descriptorStruct.mchStraps.padding[3105] = 0xff; +- descriptorStruct.mchStraps.padding[3106] = 0xff; +- descriptorStruct.mchStraps.padding[3107] = 0xff; +- descriptorStruct.mchStraps.padding[3108] = 0xff; +- descriptorStruct.mchStraps.padding[3109] = 0xff; +- descriptorStruct.mchStraps.padding[3110] = 0xff; +- descriptorStruct.mchStraps.padding[3111] = 0xff; +- descriptorStruct.mchStraps.padding[3112] = 0xff; +- descriptorStruct.mchStraps.padding[3113] = 0xff; +- descriptorStruct.mchStraps.padding[3114] = 0xff; +- descriptorStruct.mchStraps.padding[3115] = 0xff; +- descriptorStruct.mchStraps.padding[3116] = 0xff; +- descriptorStruct.mchStraps.padding[3117] = 0xff; +- descriptorStruct.mchStraps.padding[3118] = 0xff; +- descriptorStruct.mchStraps.padding[3119] = 0xff; +- descriptorStruct.mchStraps.padding[3120] = 0xff; +- descriptorStruct.mchStraps.padding[3121] = 0xff; +- descriptorStruct.mchStraps.padding[3122] = 0xff; +- descriptorStruct.mchStraps.padding[3123] = 0xff; +- descriptorStruct.mchStraps.padding[3124] = 0xff; +- descriptorStruct.mchStraps.padding[3125] = 0xff; +- descriptorStruct.mchStraps.padding[3126] = 0xff; +- descriptorStruct.mchStraps.padding[3127] = 0xff; +- descriptorStruct.mchStraps.padding[3128] = 0xff; +- descriptorStruct.mchStraps.padding[3129] = 0xff; +- descriptorStruct.mchStraps.padding[3130] = 0xff; +- descriptorStruct.mchStraps.padding[3131] = 0xff; +- descriptorStruct.mchStraps.padding[3132] = 0xff; +- descriptorStruct.mchStraps.padding[3133] = 0xff; +- descriptorStruct.mchStraps.padding[3134] = 0xff; +- descriptorStruct.mchStraps.padding[3135] = 0xff; +- descriptorStruct.mchStraps.padding[3136] = 0xff; +- descriptorStruct.mchStraps.padding[3137] = 0xff; +- descriptorStruct.mchStraps.padding[3138] = 0xff; +- descriptorStruct.mchStraps.padding[3139] = 0xff; +- descriptorStruct.mchStraps.padding[3140] = 0xff; +- descriptorStruct.mchStraps.padding[3141] = 0xff; +- descriptorStruct.mchStraps.padding[3142] = 0xff; +- descriptorStruct.mchStraps.padding[3143] = 0xff; +- descriptorStruct.mchStraps.padding[3144] = 0xff; +- descriptorStruct.mchStraps.padding[3145] = 0xff; +- descriptorStruct.mchStraps.padding[3146] = 0xff; +- descriptorStruct.mchStraps.padding[3147] = 0xff; +- descriptorStruct.mchStraps.padding[3148] = 0xff; +- descriptorStruct.mchStraps.padding[3149] = 0xff; +- descriptorStruct.mchStraps.padding[3150] = 0xff; +- descriptorStruct.mchStraps.padding[3151] = 0xff; +- descriptorStruct.mchStraps.padding[3152] = 0xff; +- descriptorStruct.mchStraps.padding[3153] = 0xff; +- descriptorStruct.mchStraps.padding[3154] = 0xff; +- descriptorStruct.mchStraps.padding[3155] = 0xff; +- descriptorStruct.mchStraps.padding[3156] = 0xff; +- descriptorStruct.mchStraps.padding[3157] = 0xff; +- descriptorStruct.mchStraps.padding[3158] = 0xff; +- descriptorStruct.mchStraps.padding[3159] = 0xff; +- descriptorStruct.mchStraps.padding[3160] = 0xff; +- descriptorStruct.mchStraps.padding[3161] = 0xff; +- descriptorStruct.mchStraps.padding[3162] = 0xff; +- descriptorStruct.mchStraps.padding[3163] = 0xff; +- descriptorStruct.mchStraps.padding[3164] = 0xff; +- descriptorStruct.mchStraps.padding[3165] = 0xff; +- descriptorStruct.mchStraps.padding[3166] = 0xff; +- descriptorStruct.mchStraps.padding[3167] = 0xff; +- descriptorStruct.mchStraps.padding[3168] = 0xff; +- descriptorStruct.mchStraps.padding[3169] = 0xff; +- descriptorStruct.mchStraps.padding[3170] = 0xff; +- descriptorStruct.mchStraps.padding[3171] = 0xff; +- descriptorStruct.mchStraps.padding[3172] = 0xff; +- descriptorStruct.mchStraps.padding[3173] = 0xff; +- descriptorStruct.mchStraps.padding[3174] = 0xff; +- descriptorStruct.mchStraps.padding[3175] = 0xff; +- descriptorStruct.mchStraps.padding[3176] = 0xff; +- descriptorStruct.mchStraps.padding[3177] = 0xff; +- descriptorStruct.mchStraps.padding[3178] = 0xff; +- descriptorStruct.mchStraps.padding[3179] = 0xff; +- descriptorStruct.mchStraps.padding[3180] = 0xff; +- descriptorStruct.mchStraps.padding[3181] = 0xff; +- descriptorStruct.mchStraps.padding[3182] = 0xff; +- descriptorStruct.mchStraps.padding[3183] = 0xff; +- descriptorStruct.mchStraps.padding[3184] = 0xff; +- descriptorStruct.mchStraps.padding[3185] = 0xff; +- descriptorStruct.mchStraps.padding[3186] = 0xff; +- descriptorStruct.mchStraps.padding[3187] = 0xff; +- descriptorStruct.mchStraps.padding[3188] = 0xff; +- descriptorStruct.mchStraps.padding[3189] = 0xff; +- descriptorStruct.mchStraps.padding[3190] = 0xff; +- descriptorStruct.mchStraps.padding[3191] = 0xff; +- descriptorStruct.mchStraps.padding[3192] = 0xff; +- descriptorStruct.mchStraps.padding[3193] = 0xff; +- descriptorStruct.mchStraps.padding[3194] = 0xff; +- descriptorStruct.mchStraps.padding[3195] = 0xff; +- descriptorStruct.mchStraps.padding[3196] = 0xff; +- descriptorStruct.mchStraps.padding[3197] = 0xff; +- descriptorStruct.mchStraps.padding[3198] = 0xff; +- descriptorStruct.mchStraps.padding[3199] = 0xff; +- descriptorStruct.mchStraps.padding[3200] = 0xff; +- descriptorStruct.mchStraps.padding[3201] = 0xff; +- descriptorStruct.mchStraps.padding[3202] = 0xff; +- descriptorStruct.mchStraps.padding[3203] = 0xff; +- descriptorStruct.mchStraps.padding[3204] = 0xff; +- descriptorStruct.mchStraps.padding[3205] = 0xff; +- descriptorStruct.mchStraps.padding[3206] = 0xff; +- descriptorStruct.mchStraps.padding[3207] = 0xff; +- descriptorStruct.mchStraps.padding[3208] = 0xff; +- descriptorStruct.mchStraps.padding[3209] = 0xff; +- descriptorStruct.mchStraps.padding[3210] = 0xff; +- descriptorStruct.mchStraps.padding[3211] = 0xff; +- descriptorStruct.mchStraps.padding[3212] = 0xff; +- descriptorStruct.mchStraps.padding[3213] = 0xff; +- descriptorStruct.mchStraps.padding[3214] = 0xff; +- descriptorStruct.mchStraps.padding[3215] = 0xff; +- descriptorStruct.mchStraps.padding[3216] = 0xff; +- descriptorStruct.mchStraps.padding[3217] = 0xff; +- descriptorStruct.mchStraps.padding[3218] = 0xff; +- descriptorStruct.mchStraps.padding[3219] = 0xff; +- descriptorStruct.mchStraps.padding[3220] = 0xff; +- descriptorStruct.mchStraps.padding[3221] = 0xff; +- descriptorStruct.mchStraps.padding[3222] = 0xff; +- descriptorStruct.mchStraps.padding[3223] = 0xff; +- descriptorStruct.mchStraps.padding[3224] = 0xff; +- descriptorStruct.mchStraps.padding[3225] = 0xff; +- descriptorStruct.mchStraps.padding[3226] = 0xff; +- descriptorStruct.mchStraps.padding[3227] = 0xff; +- descriptorStruct.mchStraps.padding[3228] = 0xff; +- descriptorStruct.mchStraps.padding[3229] = 0xff; +- descriptorStruct.mchStraps.padding[3230] = 0xff; +- descriptorStruct.mchStraps.padding[3231] = 0xff; +- descriptorStruct.mchStraps.padding[3232] = 0xff; +- descriptorStruct.mchStraps.padding[3233] = 0xff; +- descriptorStruct.mchStraps.padding[3234] = 0xff; +- descriptorStruct.mchStraps.padding[3235] = 0xff; +- descriptorStruct.mchStraps.padding[3236] = 0xff; +- descriptorStruct.mchStraps.padding[3237] = 0xff; +- descriptorStruct.mchStraps.padding[3238] = 0xff; +- descriptorStruct.mchStraps.padding[3239] = 0xff; +- descriptorStruct.mchStraps.padding[3240] = 0xff; +- descriptorStruct.mchStraps.padding[3241] = 0xff; +- descriptorStruct.mchStraps.padding[3242] = 0xff; +- descriptorStruct.mchStraps.padding[3243] = 0xff; +- descriptorStruct.mchStraps.padding[3244] = 0xff; +- descriptorStruct.mchStraps.padding[3245] = 0xff; +- descriptorStruct.mchStraps.padding[3246] = 0xff; +- descriptorStruct.mchStraps.padding[3247] = 0xff; +- descriptorStruct.mchStraps.padding[3248] = 0xff; +- descriptorStruct.mchStraps.padding[3249] = 0xff; +- descriptorStruct.mchStraps.padding[3250] = 0xff; +- descriptorStruct.mchStraps.padding[3251] = 0xff; +- descriptorStruct.mchStraps.padding[3252] = 0xff; +- descriptorStruct.mchStraps.padding[3253] = 0xff; +- descriptorStruct.mchStraps.padding[3254] = 0xff; +- descriptorStruct.mchStraps.padding[3255] = 0xff; +- descriptorStruct.mchStraps.padding[3256] = 0xff; +- descriptorStruct.mchStraps.padding[3257] = 0xff; +- descriptorStruct.mchStraps.padding[3258] = 0xff; +- descriptorStruct.mchStraps.padding[3259] = 0xff; +- descriptorStruct.mchStraps.padding[3260] = 0xff; +- descriptorStruct.mchStraps.padding[3261] = 0xff; +- descriptorStruct.mchStraps.padding[3262] = 0xff; +- descriptorStruct.mchStraps.padding[3263] = 0xff; +- descriptorStruct.mchStraps.padding[3264] = 0xff; +- descriptorStruct.mchStraps.padding[3265] = 0xff; +- descriptorStruct.mchStraps.padding[3266] = 0xff; +- descriptorStruct.mchStraps.padding[3267] = 0xff; +- descriptorStruct.mchStraps.padding[3268] = 0xff; +- descriptorStruct.mchStraps.padding[3269] = 0xff; +- descriptorStruct.mchStraps.padding[3270] = 0xff; +- descriptorStruct.mchStraps.padding[3271] = 0xff; +- descriptorStruct.mchStraps.padding[3272] = 0xff; +- descriptorStruct.mchStraps.padding[3273] = 0xff; +- descriptorStruct.mchStraps.padding[3274] = 0xff; +- descriptorStruct.mchStraps.padding[3275] = 0xff; +- descriptorStruct.mchStraps.padding[3276] = 0xbf; +- descriptorStruct.mchStraps.padding[3277] = 0x25; +- descriptorStruct.mchStraps.padding[3278] = 0x4a; +- descriptorStruct.mchStraps.padding[3279] = 0x00; +- descriptorStruct.mchStraps.padding[3280] = 0x09; +- descriptorStruct.mchStraps.padding[3281] = 0x20; +- descriptorStruct.mchStraps.padding[3282] = 0x09; +- descriptorStruct.mchStraps.padding[3283] = 0x20; +- descriptorStruct.mchStraps.padding[3284] = 0x1f; +- descriptorStruct.mchStraps.padding[3285] = 0x47; +- descriptorStruct.mchStraps.padding[3286] = 0x00; +- descriptorStruct.mchStraps.padding[3287] = 0x00; +- descriptorStruct.mchStraps.padding[3288] = 0x15; +- descriptorStruct.mchStraps.padding[3289] = 0x20; +- descriptorStruct.mchStraps.padding[3290] = 0x15; +- descriptorStruct.mchStraps.padding[3291] = 0x20; ++ for (i = 0; i < 3292; i++) { ++ descriptorStruct.mchStraps.padding[i] = 0xFF; ++ } + + /* ME VSCC Table */ +- descriptorStruct.meVsccTable.jid0 = 0x001630ef; ++ descriptorStruct.meVsccTable.jid0 = 0x001720c2; + descriptorStruct.meVsccTable.vscc0 = 0x20052005; +- descriptorStruct.meVsccTable.jid1 = 0x00167020; ++ descriptorStruct.meVsccTable.jid1 = 0x001730ef; + descriptorStruct.meVsccTable.vscc1 = 0x20052005; +- descriptorStruct.meVsccTable.jid2 = 0x001620c2; +- descriptorStruct.meVsccTable.vscc2 = 0x20052005; ++ descriptorStruct.meVsccTable.jid2 = 0x0000481f; ++ descriptorStruct.meVsccTable.vscc2 = 0x20152015; + /* Padding */ + for (i = 0; i < 4; i++) { + descriptorStruct.meVsccTable.padding[i] = 0xFF; + } + + /* Descriptor Map 2 Record */ +- descriptorStruct.descriptor2Map.meVsccTableBaseAddress = 0xed; +- descriptorStruct.descriptor2Map.meVsccTableLength = 0x0a; ++ descriptorStruct.descriptor2Map.meVsccTableBaseAddress = 0xee; ++ descriptorStruct.descriptor2Map.meVsccTableLength = 0x06; + descriptorStruct.descriptor2Map.reserved = 0x0000; + + /* OEM section */ diff --git a/i18n/fr_FR/docs/future/dumps/t500_x200_descriptor/gbe_diff_t500_x200.txt b/i18n/fr_FR/docs/future/dumps/t500_x200_descriptor/gbe_diff_t500_x200.txt new file mode 100644 index 00000000..40b20057 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/t500_x200_descriptor/gbe_diff_t500_x200.txt @@ -0,0 +1,68 @@ +--- mkgbe.c 2015-03-31 04:46:11.840747724 +0100 ++++ ../lbdev/libreboot/resources/utilities/ich9deblob/src/ich9gen/mkgbe.c 2015-03-26 16:55:12.243313103 +0000 +@@ -1,5 +1,19 @@ +-/* mkgbe.c: generated C code from ich9deblob */ +-/* .c source file for the gbe-generating C code */ ++/* ++ * Copyright (C) 2014 Leah Rowe ++ * ++ * This program is free software: you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation, either version 3 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program. If not, see . ++ */ + + #include "mkgbe.h" + +@@ -14,11 +28,11 @@ + /* MAC address (words 00h to 02h) */ + /* see ../gbe/gbe.c */ + gbeStruct4k.macAddress[0] = 0x00; +- gbeStruct4k.macAddress[1] = 0x22; +- gbeStruct4k.macAddress[2] = 0x68; +- gbeStruct4k.macAddress[3] = 0x1d; +- gbeStruct4k.macAddress[4] = 0x5f; +- gbeStruct4k.macAddress[5] = 0xc1; ++ gbeStruct4k.macAddress[1] = 0xf5; ++ gbeStruct4k.macAddress[2] = 0xf0; ++ gbeStruct4k.macAddress[3] = 0x40; ++ gbeStruct4k.macAddress[4] = 0x71; ++ gbeStruct4k.macAddress[5] = 0xfe; + + /* Word 03h (Reserved) */ + gbeStruct4k.reservedWord03h.reserved1_0 = 0x00; +@@ -83,7 +97,7 @@ + gbeStruct4k.sharedInitializationControlWord.phyPowerDownEnable = 0x1; + gbeStruct4k.sharedInitializationControlWord.reserved3 = 0x1; + gbeStruct4k.sharedInitializationControlWord.reserved4 = 0x0; +- gbeStruct4k.sharedInitializationControlWord.sign = 0x0; ++ gbeStruct4k.sharedInitializationControlWord.sign = 0x2; + + /* Word 14h (Extended Configuration Control Word 1) */ + gbeStruct4k.extendedConfigurationControlWord1.extendedConfigurationPointer = 0x020; +@@ -198,7 +212,7 @@ + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.reserved2 = 0x0; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions31h.signature = 0x1; + /* Boot Agent Configuration Customization Options (Word 32h) */ +- gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.buildNumber = 0x24; ++ gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.buildNumber = 0x18; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.minorVersionNumber = 0x3; + gbeStruct4k.pxeSoftwareRegion.bootAgentConfigurationCustomizationOptions32h.majorVersionNumber = 0x1; + /* IBA Capabilities (Word 33h) */ +@@ -223,7 +237,7 @@ + gbeStruct4k.pxeSoftwareRegion.paddingWords34hTo3Eh[10] = 0xffff; + + /* Word 3Fh (Checksum) */ +- gbeStruct4k.checkSum = 0xe818; ++ gbeStruct4k.checkSum = 0x348a; + + /* The rest of Gbe (word 40h or byte 80h onwards) is just padding (0xFF) */ + for (i = 0; i < 3968; i++) { diff --git a/i18n/fr_FR/docs/future/dumps/t500log/biosdecode.log b/i18n/fr_FR/docs/future/dumps/t500log/biosdecode.log new file mode 100644 index 00000000..2e979247 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/t500log/biosdecode.log @@ -0,0 +1,24 @@ +# biosdecode 2.12 +VPD present. + BIOS Build ID: 7VET83WW + Box Serial Number: R889Z75 + Motherboard Serial Number: VQ11102N32T + Machine Type/Model: 224397G +SMBIOS 2.4 present. + Structure Table Length: 2833 bytes + Structure Table Address: 0x000E0010 + Number Of Structures: 80 + Maximum Structure Size: 120 bytes +BIOS32 Service Directory present. + Revision: 0 + Calling Interface Address: 0x000FDC50 +ACPI 2.0 present. + OEM Identifier: LENOVO + RSD Table 32-bit Address: 0xBDB49BBA + XSD Table 64-bit Address: 0x00000000BDB49C22 +PNP BIOS 1.0 present. + Event Notification: Not Supported + Real Mode 16-bit Code Address: E13F:1A19 + Real Mode 16-bit Data Address: 0040:0000 + 16-bit Protected Mode Code Address: 0x000F8A9D + 16-bit Protected Mode Data Address: 0x00000400 diff --git a/i18n/fr_FR/docs/future/dumps/t500log/codec#0 b/i18n/fr_FR/docs/future/dumps/t500log/codec#0 new file mode 100644 index 00000000..b9d0ab3d --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/t500log/codec#0 @@ -0,0 +1,208 @@ +Codec: Conexant CX20561 (Hermosa) +Address: 0 +AFG Function Id: 0x1 (unsol 1) +MFG Function Id: 0x2 (unsol 1) +Vendor Id: 0x14f15051 +Subsystem Id: 0x17aa2100 +Revision Id: 0x100000 +Modem Function Group: 0x2 +Default PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM +Default Amp-In caps: N/A +Default Amp-Out caps: N/A +State of AFG node 0x01: + Power states: D0 D1 D2 D3 CLKSTOP + Power: setting=D0, actual=D0 +GPIO: io=4, o=0, i=0, unsolicited=1, wake=0 + IO[0]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[1]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[2]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[3]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 +Node 0x10 [Audio Output] wcaps 0xc1d: Stereo Amp-Out R/L + Control: name="Speaker Playback Volume", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Control: name="Speaker Playback Switch", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Device: name="CX20561 Analog", type="Audio", device=0 + Amp-Out caps: ofs=0x4a, nsteps=0x4a, stepsize=0x03, mute=0 + Amp-Out vals: [0x29 0x29] + Converter: stream=8, channel=0 + PCM: + rates [0x560]: 44100 48000 96000 192000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x11 [Audio Output] wcaps 0xc1d: Stereo Amp-Out R/L + Control: name="Headphone Playback Volume", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Control: name="Headphone Playback Switch", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Amp-Out caps: ofs=0x4a, nsteps=0x4a, stepsize=0x03, mute=0 + Amp-Out vals: [0x29 0x29] + Converter: stream=8, channel=0 + PCM: + rates [0x560]: 44100 48000 96000 192000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x12 [Audio Output] wcaps 0x211: Stereo Digital + Control: name="IEC958 Playback Con Mask", index=0, device=0 + Control: name="IEC958 Playback Pro Mask", index=0, device=0 + Control: name="IEC958 Playback Default", index=0, device=0 + Control: name="IEC958 Playback Switch", index=0, device=0 + Control: name="IEC958 Default PCM Playback Switch", index=0, device=0 + Device: name="CX20561 Digital", type="SPDIF", device=1 + Converter: stream=8, channel=0 + Digital: + Digital category: 0x0 + IEC Coding Type: 0x0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x5]: PCM AC3 +Node 0x13 [Beep Generator Widget] wcaps 0x70000c: Mono Amp-Out + Control: name="Beep Playback Volume", index=0, device=0 + ControlAmp: chs=1, dir=Out, idx=0, ofs=0 + Control: name="Beep Playback Switch", index=0, device=0 + ControlAmp: chs=1, dir=Out, idx=0, ofs=0 + Amp-Out caps: ofs=0x03, nsteps=0x03, stepsize=0x17, mute=0 + Amp-Out vals: [0x00] +Node 0x14 [Audio Input] wcaps 0x100d1b: Stereo Amp-In R/L + Device: name="CX20561 Analog", type="Audio", device=0 + Amp-In caps: ofs=0x4a, nsteps=0x50, stepsize=0x03, mute=0 + Amp-In vals: [0x50 0x50] [0x50 0x50] + Converter: stream=4, channel=0 + SDI-Select: 0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x1d* 0x17 +Node 0x15 [Audio Input] wcaps 0x100d1b: Stereo Amp-In R/L + Control: name="Capture Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=1, ofs=0 + Amp-In caps: ofs=0x4a, nsteps=0x50, stepsize=0x03, mute=0 + Amp-In vals: [0x50 0x50] + Converter: stream=0, channel=0 + SDI-Select: 0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 1 + 0x18 +Node 0x16 [Pin Complex] wcaps 0x400581: Stereo + Control: name="Headphone Jack", index=0, device=0 + Pincap 0x0000001c: OUT HP Detect + Pin Default 0x022140f0: [Jack] HP Out at Ext Front + Conn = 1/8, Color = Green + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0xc0: OUT HP + Unsolicited: tag=02, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10 0x11* +Node 0x17 [Pin Complex] wcaps 0x40048b: Stereo Amp-In + Control: name="Dock Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Dock Mic Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x27, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00001224: IN Detect + Vref caps: 50 80 + Pin Default 0x61a190f0: [N/A] Mic at Sep Rear + Conn = 1/8, Color = Pink + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x24: IN VREF_80 + Unsolicited: tag=03, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x18 [Pin Complex] wcaps 0x40048b: Stereo Amp-In + Control: name="Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Mic Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x27, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00001224: IN Detect + Vref caps: 50 80 + Pin Default 0x02a190f0: [Jack] Mic at Ext Front + Conn = 1/8, Color = Pink + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x24: IN VREF_80 + Unsolicited: tag=04, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x19 [Pin Complex] wcaps 0x400581: Stereo + Control: name="Dock Headphone Jack", index=0, device=0 + Pincap 0x00000014: OUT Detect + Pin Default 0x40f000f0: [N/A] Other at Ext N/A + Conn = Unknown, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x40: OUT + Unsolicited: tag=01, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10 0x11* +Node 0x1a [Pin Complex] wcaps 0x400501: Stereo + Control: name="Speaker Phantom Jack", index=0, device=0 + Pincap 0x00010010: OUT EAPD + EAPD 0x2: EAPD + Pin Default 0x901701f0: [Fixed] Speaker at Int N/A + Conn = Analog, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10* 0x11 +Node 0x1b [Pin Complex] wcaps 0x400500: Mono + Pincap 0x00010010: OUT EAPD + EAPD 0x2: EAPD + Pin Default 0x40f001f0: [N/A] Other at Ext N/A + Conn = Unknown, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10* 0x11 +Node 0x1c [Pin Complex] wcaps 0x400701: Stereo Digital + Control: name="SPDIF Phantom Jack", index=0, device=0 + Pincap 0x00000010: OUT + Pin Default 0x40f001f0: [N/A] Other at Ext N/A + Conn = Unknown, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 1 + 0x12 +Node 0x1d [Pin Complex] wcaps 0x40040b: Stereo Amp-In + Control: name="Internal Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Internal Mic Phantom Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x2f, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00000020: IN + Pin Default 0x90a601f0: [Fixed] Mic at Int N/A + Conn = Digital, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x20: IN + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x1e [Vendor Defined Widget] wcaps 0xf00000: Mono diff --git a/i18n/fr_FR/docs/future/dumps/t500log/cpuinfo.log b/i18n/fr_FR/docs/future/dumps/t500log/cpuinfo.log new file mode 100644 index 00000000..9d142692 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/t500log/cpuinfo.log @@ -0,0 +1,58 @@ +processor : 0 +vendor_id : GenuineIntel +cpu family : 6 +model : 23 +model name : Intel(R) Core(TM)2 Duo CPU P8700 @ 2.53GHz +stepping : 10 +microcode : 0xa07 +cpu MHz : 800.000 +cache size : 3072 KB +physical id : 0 +siblings : 2 +core id : 0 +cpu cores : 2 +apicid : 0 +initial apicid : 0 +fdiv_bug : no +f00f_bug : no +coma_bug : no +fpu : yes +fpu_exception : yes +cpuid level : 13 +wp : yes +flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm ida dtherm tpr_shadow vnmi flexpriority +bogomips : 5053.79 +clflush size : 64 +cache_alignment : 64 +address sizes : 36 bits physical, 48 bits virtual +power management: + +processor : 1 +vendor_id : GenuineIntel +cpu family : 6 +model : 23 +model name : Intel(R) Core(TM)2 Duo CPU P8700 @ 2.53GHz +stepping : 10 +microcode : 0xa07 +cpu MHz : 1600.000 +cache size : 3072 KB +physical id : 0 +siblings : 2 +core id : 1 +cpu cores : 2 +apicid : 1 +initial apicid : 1 +fdiv_bug : no +f00f_bug : no +coma_bug : no +fpu : yes +fpu_exception : yes +cpuid level : 13 +wp : yes +flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe nx lm constant_tsc arch_perfmon pebs bts aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm ida dtherm tpr_shadow vnmi flexpriority +bogomips : 5053.79 +clflush size : 64 +cache_alignment : 64 +address sizes : 36 bits physical, 48 bits virtual +power management: + diff --git a/i18n/fr_FR/docs/future/dumps/t500log/dmesg.log b/i18n/fr_FR/docs/future/dumps/t500log/dmesg.log new file mode 100644 index 00000000..353fe26b --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/t500log/dmesg.log @@ -0,0 +1,1062 @@ +[ 0.000000] Initializing cgroup subsys cpuset +[ 0.000000] Initializing cgroup subsys cpu +[ 0.000000] Initializing cgroup subsys cpuacct +[ 0.000000] Linux version 3.13.0-39-lowlatency (root@devel.trisquel.info) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #66+7.0trisquel2 SMP PREEMPT Wed Oct 29 14:55:34 UTC 2014 (Ubuntu 3.13.0-39.66+7.0trisquel2-lowlatency 3.13.11.8-gnu) +[ 0.000000] KERNEL supported cpus: +[ 0.000000] Intel GenuineIntel +[ 0.000000] AMD AuthenticAMD +[ 0.000000] NSC Geode by NSC +[ 0.000000] Cyrix CyrixInstead +[ 0.000000] Centaur CentaurHauls +[ 0.000000] Transmeta GenuineTMx86 +[ 0.000000] Transmeta TransmetaCPU +[ 0.000000] UMC UMC UMC UMC +[ 0.000000] Disabled fast string operations +[ 0.000000] e820: BIOS-provided physical RAM map: +[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009ebff] usable +[ 0.000000] BIOS-e820: [mem 0x000000000009ec00-0x000000000009ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved +[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000bd6a0fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000bd6a1000-0x00000000bd6a6fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bd6a7000-0x00000000bd7b7fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000bd7b8000-0x00000000bd80efff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bd80f000-0x00000000bd8c6fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000bd8c7000-0x00000000bd8d1fff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000bd8d2000-0x00000000bd8d4fff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x00000000bd8d5000-0x00000000bd8d8fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bd8d9000-0x00000000bd8dcfff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000bd8dd000-0x00000000bd8dffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bd8e0000-0x00000000bd906fff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000bd907000-0x00000000bd907fff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x00000000bd908000-0x00000000bdb0efff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000bdb0f000-0x00000000bdb9efff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000bdb9f000-0x00000000bdbfefff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x00000000bdbff000-0x00000000bdbfffff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000bdc00000-0x00000000bfffffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec0ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed003ff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed10000-0x00000000fed13fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed18000-0x00000000fed19fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed8ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000ff800000-0x00000000ffffffff] reserved +[ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000013bffffff] usable +[ 0.000000] NX (Execute Disable) protection: active +[ 0.000000] SMBIOS 2.4 present. +[ 0.000000] DMI: LENOVO 224397G/224397G, BIOS 7VET83WW (3.13 ) 03/12/2010 +[ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved +[ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable +[ 0.000000] e820: last_pfn = 0x13c000 max_arch_pfn = 0x1000000 +[ 0.000000] MTRR default type: uncachable +[ 0.000000] MTRR fixed ranges enabled: +[ 0.000000] 00000-9FFFF write-back +[ 0.000000] A0000-BFFFF uncachable +[ 0.000000] C0000-D3FFF write-protect +[ 0.000000] D4000-DBFFF uncachable +[ 0.000000] DC000-FFFFF write-protect +[ 0.000000] MTRR variable ranges enabled: +[ 0.000000] 0 base 13C000000 mask FFC000000 uncachable +[ 0.000000] 1 base 0BE000000 mask FFE000000 uncachable +[ 0.000000] 2 base 000000000 mask F80000000 write-back +[ 0.000000] 3 base 080000000 mask FC0000000 write-back +[ 0.000000] 4 base 100000000 mask FC0000000 write-back +[ 0.000000] 5 base 0BDE00000 mask FFFE00000 uncachable +[ 0.000000] 6 disabled +[ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 +[ 0.000000] original variable MTRRs +[ 0.000000] reg 0, base: 5056MB, range: 64MB, type UC +[ 0.000000] reg 1, base: 3040MB, range: 32MB, type UC +[ 0.000000] reg 2, base: 0GB, range: 2GB, type WB +[ 0.000000] reg 3, base: 2GB, range: 1GB, type WB +[ 0.000000] reg 4, base: 4GB, range: 1GB, type WB +[ 0.000000] reg 5, base: 3038MB, range: 2MB, type UC +[ 0.000000] total RAM covered: 3998M +[ 0.000000] Found optimal setting for mtrr clean up +[ 0.000000] gran_size: 64K chunk_size: 128M num_reg: 6 lose cover RAM: 0G +[ 0.000000] New variable MTRRs +[ 0.000000] reg 0, base: 0GB, range: 2GB, type WB +[ 0.000000] reg 1, base: 2GB, range: 1GB, type WB +[ 0.000000] reg 2, base: 3038MB, range: 2MB, type UC +[ 0.000000] reg 3, base: 3040MB, range: 32MB, type UC +[ 0.000000] reg 4, base: 4GB, range: 1GB, type WB +[ 0.000000] reg 5, base: 5056MB, range: 64MB, type UC +[ 0.000000] e820: update [mem 0xbde00000-0xffffffff] usable ==> reserved +[ 0.000000] found SMP MP-table at [mem 0x000f6480-0x000f648f] mapped at [c00f6480] +[ 0.000000] Scanning 1 areas for low memory corruption +[ 0.000000] initial memory mapped: [mem 0x00000000-0x01ffffff] +[ 0.000000] Base memory trampoline at [c009a000] 9a000 size 16384 +[ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff] +[ 0.000000] [mem 0x00000000-0x000fffff] page 4k +[ 0.000000] init_memory_mapping: [mem 0x37800000-0x379fffff] +[ 0.000000] [mem 0x37800000-0x379fffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0x34000000-0x377fffff] +[ 0.000000] [mem 0x34000000-0x377fffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0x00100000-0x33ffffff] +[ 0.000000] [mem 0x00100000-0x001fffff] page 4k +[ 0.000000] [mem 0x00200000-0x33ffffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0x37a00000-0x37bfdfff] +[ 0.000000] [mem 0x37a00000-0x37bfdfff] page 4k +[ 0.000000] BRK [0x01b9a000, 0x01b9afff] PGTABLE +[ 0.000000] RAMDISK: [mem 0x3553e000-0x36a96fff] +[ 0.000000] ACPI: RSDP 000f6440 000024 (v02 LENOVO) +[ 0.000000] ACPI: XSDT bdb49c22 00008C (v01 LENOVO TP-7V 00003130 LTP 00000000) +[ 0.000000] ACPI: FACP bdb49d00 0000F4 (v03 LENOVO TP-7V 00003130 LNVO 00000001) +[ 0.000000] ACPI: DSDT bdb4a10e 00FAC1 (v01 LENOVO TP-7V 00003130 MSFT 03000000) +[ 0.000000] ACPI: FACS bdb8e000 000040 +[ 0.000000] ACPI: SSDT bdb49eb4 00025A (v01 LENOVO TP-7V 00003130 MSFT 03000000) +[ 0.000000] ACPI: ECDT bdb59bcf 000052 (v01 LENOVO TP-7V 00003130 LNVO 00000001) +[ 0.000000] ACPI: APIC bdb59c21 000078 (v01 LENOVO TP-7V 00003130 LNVO 00000001) +[ 0.000000] ACPI: MCFG bdb59c99 00003C (v01 LENOVO TP-7V 00003130 LNVO 00000001) +[ 0.000000] ACPI: HPET bdb59cd5 000038 (v01 LENOVO TP-7V 00003130 LNVO 00000001) +[ 0.000000] ACPI: SLIC bdb59e62 000176 (v01 LENOVO TP-7V 00003130 LTP 00000000) +[ 0.000000] ACPI: BOOT bdb59fd8 000028 (v01 LENOVO TP-7V 00003130 LTP 00000001) +[ 0.000000] ACPI: SSDT bdb8d1fa 000568 (v01 LENOVO TP-7V 00003130 INTL 20050513) +[ 0.000000] ACPI: TCPA bd907000 000032 (v00 00000000 00000000) +[ 0.000000] ACPI: SSDT bd8d4000 000655 (v01 PmRef CpuPm 00003000 INTL 20050624) +[ 0.000000] ACPI: SSDT bd8d3000 000274 (v01 PmRef Cpu0Tst 00003000 INTL 20050624) +[ 0.000000] ACPI: SSDT bd8d2000 000242 (v01 PmRef ApTst 00003000 INTL 20050624) +[ 0.000000] ACPI: DMI detected: Lenovo ThinkPad T500 +[ 0.000000] ACPI: Local APIC address 0xfee00000 +[ 0.000000] 4164MB HIGHMEM available. +[ 0.000000] 891MB LOWMEM available. +[ 0.000000] mapped low ram: 0 - 37bfe000 +[ 0.000000] low ram: 0 - 37bfe000 +[ 0.000000] BRK [0x01b9b000, 0x01b9bfff] PGTABLE +[ 0.000000] Zone ranges: +[ 0.000000] DMA [mem 0x00001000-0x00ffffff] +[ 0.000000] Normal [mem 0x01000000-0x37bfdfff] +[ 0.000000] HighMem [mem 0x37bfe000-0x3bffffff] +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x00001000-0x0009dfff] +[ 0.000000] node 0: [mem 0x00100000-0xbd6a0fff] +[ 0.000000] node 0: [mem 0xbd6a7000-0xbd7b7fff] +[ 0.000000] node 0: [mem 0xbd80f000-0xbd8c6fff] +[ 0.000000] node 0: [mem 0xbdbff000-0xbdbfffff] +[ 0.000000] node 0: [mem 0x00000000-0x3bffffff] +[ 0.000000] On node 0 totalpages: 1021960 +[ 0.000000] free_area_init_node: node 0, pgdat c19a7bc0, node_mem_map f2dbe020 +[ 0.000000] DMA zone: 32 pages used for memmap +[ 0.000000] DMA zone: 0 pages reserved +[ 0.000000] DMA zone: 3997 pages, LIFO batch:0 +[ 0.000000] Normal zone: 1752 pages used for memmap +[ 0.000000] Normal zone: 224254 pages, LIFO batch:31 +[ 0.000000] HighMem zone: 8329 pages used for memmap +[ 0.000000] HighMem zone: 793709 pages, LIFO batch:31 +[ 0.000000] Using APIC driver default +[ 0.000000] ACPI: PM-Timer IO Port: 0x1008 +[ 0.000000] ACPI: Local APIC address 0xfee00000 +[ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] disabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x03] disabled) +[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1]) +[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) +[ 0.000000] ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0]) +[ 0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-23 +[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) +[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) +[ 0.000000] ACPI: IRQ0 used by override. +[ 0.000000] ACPI: IRQ2 used by override. +[ 0.000000] ACPI: IRQ9 used by override. +[ 0.000000] Using ACPI (MADT) for SMP configuration information +[ 0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000 +[ 0.000000] smpboot: Allowing 4 CPUs, 2 hotplug CPUs +[ 0.000000] nr_irqs_gsi: 40 +[ 0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x0009efff] +[ 0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff] +[ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000dbfff] +[ 0.000000] PM: Registered nosave memory: [mem 0x000dc000-0x000fffff] +[ 0.000000] e820: [mem 0xc0000000-0xdfffffff] available for PCI devices +[ 0.000000] Booting paravirtualized kernel on bare hardware +[ 0.000000] setup_percpu: NR_CPUS:8 nr_cpumask_bits:8 nr_cpu_ids:4 nr_node_ids:1 +[ 0.000000] PERCPU: Embedded 14 pages/cpu @f7bb3000 s36288 r0 d21056 u57344 +[ 0.000000] pcpu-alloc: s36288 r0 d21056 u57344 alloc=14*4096 +[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 +[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 1020176 +[ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-3.13.0-39-lowlatency root=UUID=900a05b1-d125-4de4-93a6-2cdaa0e68d09 ro nomdmonddf nomdmonisw nomdmonddf nomdmonisw +[ 0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes) +[ 0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) +[ 0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) +[ 0.000000] Initializing CPU#0 +[ 0.000000] xsave: enabled xstate_bv 0x3, cntxt size 0x240 +[ 0.000000] allocated 10354680 bytes of page_cgroup +[ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups +[ 0.000000] Initializing HighMem for node 0 (00037bfe:0013c000) +[ 0.000000] Memory: 4002360K/4087840K available (6578K kernel code, 638K rwdata, 2772K rodata, 868K init, 924K bss, 85480K reserved, 3174836K highmem) +[ 0.000000] virtual kernel memory layout: +[ 0.000000] fixmap : 0xfff14000 - 0xfffff000 ( 940 kB) +[ 0.000000] pkmap : 0xffc00000 - 0xffe00000 (2048 kB) +[ 0.000000] vmalloc : 0xf83fe000 - 0xffbfe000 ( 120 MB) +[ 0.000000] lowmem : 0xc0000000 - 0xf7bfe000 ( 891 MB) +[ 0.000000] .init : 0xc19c3000 - 0xc1a9c000 ( 868 kB) +[ 0.000000] .data : 0xc166cd34 - 0xc19c2ac0 (3415 kB) +[ 0.000000] .text : 0xc1000000 - 0xc166cd34 (6579 kB) +[ 0.000000] Checking if this processor honours the WP bit even in supervisor mode...Ok. +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 +[ 0.000000] Preemptible hierarchical RCU implementation. +[ 0.000000] RCU dyntick-idle grace-period acceleration is enabled. +[ 0.000000] Dump stacks of tasks blocking RCU-preempt GP. +[ 0.000000] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4. +[ 0.000000] NR_IRQS:2304 nr_irqs:712 16 +[ 0.000000] CPU 0 irqstacks, hard=f6c08000 soft=f6c0a000 +[ 0.000000] Console: colour VGA+ 80x25 +[ 0.000000] console [tty0] enabled +[ 0.000000] hpet clockevent registered +[ 0.000000] tsc: Fast TSC calibration using PIT +[ 0.000000] tsc: Detected 2526.897 MHz processor +[ 0.002002] Calibrating delay loop (skipped), value calculated using timer frequency.. 5053.79 BogoMIPS (lpj=2526897) +[ 0.002096] pid_max: default: 32768 minimum: 301 +[ 0.002171] Security Framework initialized +[ 0.002233] AppArmor: AppArmor initialized +[ 0.002278] Yama: becoming mindful. +[ 0.002367] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes) +[ 0.002417] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes) +[ 0.002697] Initializing cgroup subsys memory +[ 0.002748] Initializing cgroup subsys devices +[ 0.002795] Initializing cgroup subsys freezer +[ 0.002841] Initializing cgroup subsys blkio +[ 0.002887] Initializing cgroup subsys bfqio +[ 0.002933] Initializing cgroup subsys perf_event +[ 0.003005] Initializing cgroup subsys hugetlb +[ 0.003074] Disabled fast string operations +[ 0.003123] CPU: Physical Processor ID: 0 +[ 0.003168] CPU: Processor Core ID: 0 +[ 0.003214] mce: CPU supports 6 MCE banks +[ 0.003266] CPU0: Thermal monitoring enabled (TM2) +[ 0.003322] Last level iTLB entries: 4KB 128, 2MB 4, 4MB 4 +[ 0.003322] Last level dTLB entries: 4KB 256, 2MB 0, 4MB 32 +[ 0.003322] tlb_flushall_shift: -1 +[ 0.003703] Freeing SMP alternatives memory: 24K (c1a9c000 - c1aa2000) +[ 0.004536] ACPI: Core revision 20131115 +[ 0.013161] ACPI: All ACPI Tables successfully acquired +[ 0.014010] ftrace: allocating 27933 entries in 55 pages +[ 0.021082] Enabling APIC mode: Flat. Using 1 I/O APICs +[ 0.022308] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 +[ 0.032367] smpboot: CPU0: Intel(R) Core(TM)2 Duo CPU P8700 @ 2.53GHz (fam: 06, model: 17, stepping: 0a) +[ 0.033000] Performance Events: PEBS fmt0+, 4-deep LBR, Core2 events, Intel PMU driver. +[ 0.033000] ... version: 2 +[ 0.033000] ... bit width: 40 +[ 0.033000] ... generic registers: 2 +[ 0.033000] ... value mask: 000000ffffffffff +[ 0.033000] ... max period: 000000007fffffff +[ 0.033001] ... fixed-purpose events: 3 +[ 0.033046] ... event mask: 0000000700000003 +[ 0.042062] CPU 1 irqstacks, hard=f6d28000 soft=f6d2a000 +[ 0.042064] x86: Booting SMP configuration: +[ 0.003000] Initializing CPU#1 +[ 0.003000] Disabled fast string operations +[ 0.054122] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter. +[ 0.042111] .... node #0, CPUs: #1 +[ 0.054315] x86: Booted up 1 node, 2 CPUs +[ 0.054401] smpboot: Total of 2 processors activated (10107.58 BogoMIPS) +[ 0.055109] devtmpfs: initialized +[ 0.055315] EVM: security.selinux +[ 0.055361] EVM: security.SMACK64 +[ 0.055406] EVM: security.ima +[ 0.055450] EVM: security.capability +[ 0.056086] PM: Registering ACPI NVS region [mem 0xbd8c7000-0xbd8d1fff] (45056 bytes) +[ 0.056086] PM: Registering ACPI NVS region [mem 0xbd8d9000-0xbd8dcfff] (16384 bytes) +[ 0.056086] PM: Registering ACPI NVS region [mem 0xbd8e0000-0xbd906fff] (159744 bytes) +[ 0.056129] PM: Registering ACPI NVS region [mem 0xbdb0f000-0xbdb9efff] (589824 bytes) +[ 0.057217] pinctrl core: initialized pinctrl subsystem +[ 0.057342] regulator-dummy: no parameters +[ 0.057422] RTC time: 12:05:17, date: 05/03/15 +[ 0.057510] NET: Registered protocol family 16 +[ 0.057754] EISA bus registered +[ 0.057799] cpuidle: using governor ladder +[ 0.057845] cpuidle: using governor menu +[ 0.057984] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it +[ 0.058006] ACPI: bus type PCI registered +[ 0.058053] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 +[ 0.058173] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) +[ 0.058237] PCI: MMCONFIG at [mem 0xe0000000-0xe3ffffff] reserved in E820 +[ 0.058287] PCI: Using MMCONFIG for extended config space +[ 0.058334] PCI: Using configuration type 1 for base access +[ 0.060062] bio: create slab at 0 +[ 0.060087] ACPI: Added _OSI(Module Device) +[ 0.060134] ACPI: Added _OSI(Processor Device) +[ 0.060181] ACPI: Added _OSI(3.0 _SCP Extensions) +[ 0.060227] ACPI: Added _OSI(Processor Aggregator Device) +[ 0.060276] ACPI: Added _OSI(Linux) +[ 0.062197] ACPI : EC: EC description table is found, configuring boot EC +[ 0.069031] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query honored via DMI +[ 0.078455] ACPI: SSDT bd8d7c20 0002C8 (v01 PmRef Cpu0Ist 00003000 INTL 20050624) +[ 0.079266] ACPI: Dynamic OEM Table Load: +[ 0.079373] ACPI: SSDT (null) 0002C8 (v01 PmRef Cpu0Ist 00003000 INTL 20050624) +[ 0.079625] ACPI: SSDT bd8d5020 00087A (v01 PmRef Cpu0Cst 00003001 INTL 20050624) +[ 0.080244] ACPI: Dynamic OEM Table Load: +[ 0.080351] ACPI: SSDT (null) 00087A (v01 PmRef Cpu0Cst 00003001 INTL 20050624) +[ 0.087240] ACPI: SSDT bd8d6ca0 0001CF (v01 PmRef ApIst 00003000 INTL 20050624) +[ 0.088177] ACPI: Dynamic OEM Table Load: +[ 0.088284] ACPI: SSDT (null) 0001CF (v01 PmRef ApIst 00003000 INTL 20050624) +[ 0.092077] ACPI: SSDT bd8d6f20 00008D (v01 PmRef ApCst 00003000 INTL 20050624) +[ 0.092339] ACPI: Dynamic OEM Table Load: +[ 0.092446] ACPI: SSDT (null) 00008D (v01 PmRef ApCst 00003000 INTL 20050624) +[ 0.097163] ACPI: Interpreter enabled +[ 0.097216] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20131115/hwxface-580) +[ 0.097341] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20131115/hwxface-580) +[ 0.097476] ACPI: (supports S0 S3 S4 S5) +[ 0.097522] ACPI: Using IOAPIC for interrupt routing +[ 0.097593] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug +[ 0.098665] ACPI: ACPI Dock Station Driver: 3 docks/bays found +[ 0.107215] ACPI: Power Resource [PUBS] (on) +[ 0.114068] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.114526] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.114981] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.115423] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.115877] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.116331] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.116785] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.117270] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.117675] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) +[ 0.117728] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] +[ 0.118326] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] +[ 0.118414] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge +[ 0.118691] PCI host bridge to bus 0000:00 +[ 0.118739] pci_bus 0000:00: root bus resource [bus 00-ff] +[ 0.118788] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7] +[ 0.118838] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff] +[ 0.118887] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] +[ 0.118937] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff] +[ 0.118987] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff] +[ 0.119006] pci_bus 0000:00: root bus resource [mem 0xc0000000-0xfebfffff] +[ 0.119064] pci 0000:00:00.0: [8086:2a40] type 00 class 0x060000 +[ 0.119085] DMAR: Forcing write-buffer flush capability +[ 0.119133] DMAR: Disabling IOMMU for graphics on this chipset +[ 0.119260] pci 0000:00:02.0: [8086:2a42] type 00 class 0x030000 +[ 0.119273] pci 0000:00:02.0: reg 0x10: [mem 0xfc000000-0xfc3fffff 64bit] +[ 0.119281] pci 0000:00:02.0: reg 0x18: [mem 0xd0000000-0xdfffffff 64bit pref] +[ 0.119287] pci 0000:00:02.0: reg 0x20: [io 0x1800-0x1807] +[ 0.119380] pci 0000:00:02.1: [8086:2a43] type 00 class 0x038000 +[ 0.119391] pci 0000:00:02.1: reg 0x10: [mem 0xf4200000-0xf42fffff 64bit] +[ 0.119495] pci 0000:00:03.0: [8086:2a44] type 00 class 0x078000 +[ 0.119511] pci 0000:00:03.0: reg 0x10: [mem 0xfc625800-0xfc62580f 64bit] +[ 0.119562] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold +[ 0.119692] pci 0000:00:19.0: [8086:10bf] type 00 class 0x020000 +[ 0.119717] pci 0000:00:19.0: reg 0x10: [mem 0xfc400000-0xfc41ffff] +[ 0.119729] pci 0000:00:19.0: reg 0x14: [mem 0xfc424000-0xfc424fff] +[ 0.119741] pci 0000:00:19.0: reg 0x18: [io 0x1820-0x183f] +[ 0.119831] pci 0000:00:19.0: PME# supported from D0 D3hot D3cold +[ 0.119885] pci 0000:00:19.0: System wakeup disabled by ACPI +[ 0.120018] pci 0000:00:1a.0: [8086:2937] type 00 class 0x0c0300 +[ 0.120076] pci 0000:00:1a.0: reg 0x20: [io 0x1840-0x185f] +[ 0.120187] pci 0000:00:1a.0: System wakeup disabled by ACPI +[ 0.120273] pci 0000:00:1a.1: [8086:2938] type 00 class 0x0c0300 +[ 0.120331] pci 0000:00:1a.1: reg 0x20: [io 0x1860-0x187f] +[ 0.120457] pci 0000:00:1a.2: [8086:2939] type 00 class 0x0c0300 +[ 0.120514] pci 0000:00:1a.2: reg 0x20: [io 0x1880-0x189f] +[ 0.120623] pci 0000:00:1a.2: System wakeup disabled by ACPI +[ 0.120722] pci 0000:00:1a.7: [8086:293c] type 00 class 0x0c0320 +[ 0.120748] pci 0000:00:1a.7: reg 0x10: [mem 0xfc625c00-0xfc625fff] +[ 0.120859] pci 0000:00:1a.7: PME# supported from D0 D3hot D3cold +[ 0.120914] pci 0000:00:1a.7: System wakeup disabled by ACPI +[ 0.121012] pci 0000:00:1b.0: [8086:293e] type 00 class 0x040300 +[ 0.121034] pci 0000:00:1b.0: reg 0x10: [mem 0xfc420000-0xfc423fff 64bit] +[ 0.121133] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold +[ 0.121195] pci 0000:00:1b.0: System wakeup disabled by ACPI +[ 0.121284] pci 0000:00:1c.0: [8086:2940] type 01 class 0x060400 +[ 0.121389] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold +[ 0.121447] pci 0000:00:1c.0: System wakeup disabled by ACPI +[ 0.121537] pci 0000:00:1c.3: [8086:2946] type 01 class 0x060400 +[ 0.121642] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold +[ 0.121700] pci 0000:00:1c.3: System wakeup disabled by ACPI +[ 0.121788] pci 0000:00:1c.4: [8086:2948] type 01 class 0x060400 +[ 0.121891] pci 0000:00:1c.4: PME# supported from D0 D3hot D3cold +[ 0.121952] pci 0000:00:1c.4: System wakeup disabled by ACPI +[ 0.122047] pci 0000:00:1d.0: [8086:2934] type 00 class 0x0c0300 +[ 0.122105] pci 0000:00:1d.0: reg 0x20: [io 0x18a0-0x18bf] +[ 0.122216] pci 0000:00:1d.0: System wakeup disabled by ACPI +[ 0.122304] pci 0000:00:1d.1: [8086:2935] type 00 class 0x0c0300 +[ 0.122361] pci 0000:00:1d.1: reg 0x20: [io 0x18c0-0x18df] +[ 0.122485] pci 0000:00:1d.2: [8086:2936] type 00 class 0x0c0300 +[ 0.122542] pci 0000:00:1d.2: reg 0x20: [io 0x18e0-0x18ff] +[ 0.122678] pci 0000:00:1d.7: [8086:293a] type 00 class 0x0c0320 +[ 0.122704] pci 0000:00:1d.7: reg 0x10: [mem 0xfc626000-0xfc6263ff] +[ 0.122816] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold +[ 0.122870] pci 0000:00:1d.7: System wakeup disabled by ACPI +[ 0.122955] pci 0000:00:1e.0: [8086:2448] type 01 class 0x060401 +[ 0.123078] pci 0000:00:1e.0: System wakeup disabled by ACPI +[ 0.123169] pci 0000:00:1f.0: [8086:2919] type 00 class 0x060100 +[ 0.123394] pci 0000:00:1f.2: [8086:2929] type 00 class 0x010601 +[ 0.123423] pci 0000:00:1f.2: reg 0x10: [io 0x1818-0x181f] +[ 0.123434] pci 0000:00:1f.2: reg 0x14: [io 0x180c-0x180f] +[ 0.123445] pci 0000:00:1f.2: reg 0x18: [io 0x1810-0x1817] +[ 0.123457] pci 0000:00:1f.2: reg 0x1c: [io 0x1808-0x180b] +[ 0.123468] pci 0000:00:1f.2: reg 0x20: [io 0x1c00-0x1c1f] +[ 0.123480] pci 0000:00:1f.2: reg 0x24: [mem 0xfc625000-0xfc6257ff] +[ 0.123551] pci 0000:00:1f.2: PME# supported from D3hot +[ 0.123636] pci 0000:00:1f.3: [8086:2930] type 00 class 0x0c0500 +[ 0.123658] pci 0000:00:1f.3: reg 0x10: [mem 0xfc626400-0xfc6264ff 64bit] +[ 0.123688] pci 0000:00:1f.3: reg 0x20: [io 0x1c20-0x1c3f] +[ 0.123852] pci 0000:00:1c.0: PCI bridge to [bus 02] +[ 0.123984] pci 0000:00:1c.3: PCI bridge to [bus 05-0c] +[ 0.124008] pci 0000:00:1c.3: bridge window [io 0x2000-0x2fff] +[ 0.124013] pci 0000:00:1c.3: bridge window [mem 0xf8000000-0xf9ffffff] +[ 0.124021] pci 0000:00:1c.3: bridge window [mem 0xf4000000-0xf40fffff 64bit pref] +[ 0.124099] pci 0000:00:1c.4: PCI bridge to [bus 0d-14] +[ 0.124151] pci 0000:00:1c.4: bridge window [io 0x3000-0x3fff] +[ 0.124155] pci 0000:00:1c.4: bridge window [mem 0xfa000000-0xfbffffff] +[ 0.124163] pci 0000:00:1c.4: bridge window [mem 0xf4100000-0xf41fffff 64bit pref] +[ 0.124236] pci 0000:15:00.0: [1180:0476] type 02 class 0x060700 +[ 0.124260] pci 0000:15:00.0: proprietary Ricoh MMC controller disabled (via cardbus function) +[ 0.124322] pci 0000:15:00.0: MMC cards are now supported by standard SDHCI controller +[ 0.124400] pci 0000:15:00.0: reg 0x10: [mem 0xf4300000-0xf4300fff] +[ 0.124444] pci 0000:15:00.0: supports D1 D2 +[ 0.124446] pci 0000:15:00.0: PME# supported from D0 D1 D2 D3hot D3cold +[ 0.124507] pci 0000:15:00.1: [1180:0832] type 00 class 0x0c0010 +[ 0.124534] pci 0000:15:00.1: reg 0x10: [mem 0xf4301000-0xf43017ff] +[ 0.124651] pci 0000:15:00.1: supports D1 D2 +[ 0.124653] pci 0000:15:00.1: PME# supported from D0 D1 D2 D3hot D3cold +[ 0.124712] pci 0000:15:00.2: [1180:0822] type 00 class 0x080500 +[ 0.124738] pci 0000:15:00.2: reg 0x10: [mem 0xf4301800-0xf43018ff] +[ 0.124855] pci 0000:15:00.2: supports D1 D2 +[ 0.124857] pci 0000:15:00.2: PME# supported from D0 D1 D2 D3hot D3cold +[ 0.124916] pci 0000:15:00.4: [1180:0592] type 00 class 0x088000 +[ 0.124942] pci 0000:15:00.4: reg 0x10: [mem 0xf4302000-0xf43020ff] +[ 0.125099] pci 0000:15:00.4: supports D1 D2 +[ 0.125101] pci 0000:15:00.4: PME# supported from D0 D1 D2 D3hot D3cold +[ 0.125161] pci 0000:15:00.5: [1180:0852] type 00 class 0x088000 +[ 0.125187] pci 0000:15:00.5: reg 0x10: [mem 0xf4302400-0xf43024ff] +[ 0.125305] pci 0000:15:00.5: supports D1 D2 +[ 0.125307] pci 0000:15:00.5: PME# supported from D0 D1 D2 D3hot D3cold +[ 0.125413] pci 0000:00:1e.0: PCI bridge to [bus 15-18] (subtractive decode) +[ 0.125466] pci 0000:00:1e.0: bridge window [io 0x4000-0x7fff] +[ 0.125471] pci 0000:00:1e.0: bridge window [mem 0xf4300000-0xf7ffffff] +[ 0.125479] pci 0000:00:1e.0: bridge window [mem 0xf0000000-0xf3ffffff 64bit pref] +[ 0.125481] pci 0000:00:1e.0: bridge window [io 0x0000-0x0cf7] (subtractive decode) +[ 0.125483] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff] (subtractive decode) +[ 0.125486] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode) +[ 0.125488] pci 0000:00:1e.0: bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode) +[ 0.125490] pci 0000:00:1e.0: bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode) +[ 0.125492] pci 0000:00:1e.0: bridge window [mem 0xc0000000-0xfebfffff] (subtractive decode) +[ 0.125556] pci_bus 0000:16: busn_res: can not insert [bus 16-ff] under [bus 15-18] (conflicts with (null) [bus 15-18]) +[ 0.125562] pci_bus 0000:16: busn_res: [bus 16-ff] end is updated to 17 +[ 0.125591] pci_bus 0000:00: on NUMA node 0 +[ 0.125592] acpi PNP0A08:00: Disabling ASPM (FADT indicates it is unsupported) +[ 0.127540] ACPI: Enabled 3 GPEs in block 00 to 3F +[ 0.127663] ACPI: \_SB_.PCI0: notify handler is installed +[ 0.127780] Found 1 acpi root devices +[ 0.131062] ACPI : EC: GPE = 0x11, I/O: command/status = 0x66, data = 0x62 +[ 0.131203] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none +[ 0.131203] vgaarb: loaded +[ 0.131203] vgaarb: bridge control possible 0000:00:02.0 +[ 0.131348] SCSI subsystem initialized +[ 0.131406] libata version 3.00 loaded. +[ 0.131406] ACPI: bus type USB registered +[ 0.131406] usbcore: registered new interface driver usbfs +[ 0.131406] usbcore: registered new interface driver hub +[ 0.132009] usbcore: registered new device driver usb +[ 0.132102] PCI: Using ACPI for IRQ routing +[ 0.134560] PCI: pci_cache_line_size set to 64 bytes +[ 0.134646] e820: reserve RAM buffer [mem 0x0009ec00-0x0009ffff] +[ 0.134648] e820: reserve RAM buffer [mem 0xbd6a1000-0xbfffffff] +[ 0.134652] e820: reserve RAM buffer [mem 0xbd7b8000-0xbfffffff] +[ 0.134655] e820: reserve RAM buffer [mem 0xbd8c7000-0xbfffffff] +[ 0.134658] e820: reserve RAM buffer [mem 0xbdc00000-0xbfffffff] +[ 0.134756] NetLabel: Initializing +[ 0.134802] NetLabel: domain hash size = 128 +[ 0.134848] NetLabel: protocols = UNLABELED CIPSOv4 +[ 0.134905] NetLabel: unlabeled traffic allowed by default +[ 0.135086] HPET: 4 timers in total, 0 timers will be used for per-cpu timer +[ 0.135142] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0 +[ 0.135343] hpet0: 4 comparators, 64-bit 14.318180 MHz counter +[ 0.137029] Switched to clocksource hpet +[ 0.144380] AppArmor: AppArmor Filesystem Enabled +[ 0.144459] pnp: PnP ACPI init +[ 0.144518] ACPI: bus type PNP registered +[ 0.164925] system 00:00: [mem 0x00000000-0x0009ffff] could not be reserved +[ 0.164977] system 00:00: [mem 0x000c0000-0x000c3fff] could not be reserved +[ 0.165039] system 00:00: [mem 0x000c4000-0x000c7fff] could not be reserved +[ 0.165091] system 00:00: [mem 0x000c8000-0x000cbfff] has been reserved +[ 0.165141] system 00:00: [mem 0x000cc000-0x000cffff] has been reserved +[ 0.165191] system 00:00: [mem 0x000d0000-0x000d3fff] could not be reserved +[ 0.165242] system 00:00: [mem 0x000dc000-0x000dffff] could not be reserved +[ 0.165293] system 00:00: [mem 0x000e0000-0x000e3fff] could not be reserved +[ 0.165343] system 00:00: [mem 0x000e4000-0x000e7fff] could not be reserved +[ 0.165394] system 00:00: [mem 0x000e8000-0x000ebfff] could not be reserved +[ 0.165445] system 00:00: [mem 0x000ec000-0x000effff] could not be reserved +[ 0.165495] system 00:00: [mem 0x000f0000-0x000fffff] could not be reserved +[ 0.165546] system 00:00: [mem 0x00100000-0xbfffffff] could not be reserved +[ 0.165597] system 00:00: [mem 0xfec00000-0xfed3ffff] could not be reserved +[ 0.165648] system 00:00: [mem 0xfed4c000-0xffffffff] could not be reserved +[ 0.165701] system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active) +[ 0.185630] system 00:01: [io 0x1000-0x107f] could not be reserved +[ 0.185680] system 00:01: [io 0x1180-0x11ff] has been reserved +[ 0.185731] system 00:01: [io 0x0800-0x080f] has been reserved +[ 0.185780] system 00:01: [io 0x15e0-0x15ef] has been reserved +[ 0.185829] system 00:01: [io 0x1600-0x167f] has been reserved +[ 0.185879] system 00:01: [io 0x1680-0x169f] has been reserved +[ 0.185928] system 00:01: [mem 0xe0000000-0xefffffff] has been reserved +[ 0.185979] system 00:01: [mem 0xfed1c000-0xfed1ffff] has been reserved +[ 0.186041] system 00:01: [mem 0xfed10000-0xfed13fff] has been reserved +[ 0.186092] system 00:01: [mem 0xfed18000-0xfed18fff] has been reserved +[ 0.186142] system 00:01: [mem 0xfed19000-0xfed19fff] has been reserved +[ 0.186193] system 00:01: [mem 0xfed45000-0xfed4bfff] has been reserved +[ 0.186839] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active) +[ 0.186896] pnp 00:02: Plug and Play ACPI device, IDs PNP0103 (active) +[ 0.186906] pnp 00:03: [dma 4] +[ 0.186930] pnp 00:03: Plug and Play ACPI device, IDs PNP0200 (active) +[ 0.186958] pnp 00:04: Plug and Play ACPI device, IDs PNP0800 (active) +[ 0.186998] pnp 00:05: Plug and Play ACPI device, IDs PNP0c04 (active) +[ 0.187044] pnp 00:06: Plug and Play ACPI device, IDs PNP0b00 (active) +[ 0.187077] pnp 00:07: Plug and Play ACPI device, IDs PNP0303 (active) +[ 0.187110] pnp 00:08: Plug and Play ACPI device, IDs IBM3780 PNP0f13 (active) +[ 0.207039] pnp 00:09: Plug and Play ACPI device, IDs PNP0c31 (active) +[ 0.207517] pnp: PnP ACPI: found 10 devices +[ 0.207564] ACPI: bus type PNP unregistered +[ 0.207612] PnPBIOS: Disabled by ACPI PNP +[ 0.244523] pci 0000:00:1c.0: bridge window [io 0x1000-0x0fff] to [bus 02] add_size 1000 +[ 0.244528] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 02] add_size 200000 +[ 0.244530] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff] to [bus 02] add_size 200000 +[ 0.244572] pci 0000:00:1c.0: res[14]=[mem 0x00100000-0x000fffff] get_res_add_size add_size 200000 +[ 0.244574] pci 0000:00:1c.0: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000 +[ 0.244577] pci 0000:00:1c.0: res[13]=[io 0x1000-0x0fff] get_res_add_size add_size 1000 +[ 0.244582] pci 0000:00:1c.0: BAR 14: assigned [mem 0xc0000000-0xc01fffff] +[ 0.244635] pci 0000:00:1c.0: BAR 15: assigned [mem 0xc0200000-0xc03fffff 64bit pref] +[ 0.244697] pci 0000:00:1c.0: BAR 13: assigned [io 0x8000-0x8fff] +[ 0.244747] pci 0000:00:1c.0: PCI bridge to [bus 02] +[ 0.244797] pci 0000:00:1c.0: bridge window [io 0x8000-0x8fff] +[ 0.244851] pci 0000:00:1c.0: bridge window [mem 0xc0000000-0xc01fffff] +[ 0.244904] pci 0000:00:1c.0: bridge window [mem 0xc0200000-0xc03fffff 64bit pref] +[ 0.244970] pci 0000:00:1c.3: PCI bridge to [bus 05-0c] +[ 0.245030] pci 0000:00:1c.3: bridge window [io 0x2000-0x2fff] +[ 0.245084] pci 0000:00:1c.3: bridge window [mem 0xf8000000-0xf9ffffff] +[ 0.245136] pci 0000:00:1c.3: bridge window [mem 0xf4000000-0xf40fffff 64bit pref] +[ 0.245203] pci 0000:00:1c.4: PCI bridge to [bus 0d-14] +[ 0.245252] pci 0000:00:1c.4: bridge window [io 0x3000-0x3fff] +[ 0.245305] pci 0000:00:1c.4: bridge window [mem 0xfa000000-0xfbffffff] +[ 0.245358] pci 0000:00:1c.4: bridge window [mem 0xf4100000-0xf41fffff 64bit pref] +[ 0.245426] pci 0000:15:00.0: res[15]=[mem 0x04000000-0x03ffffff pref] get_res_add_size add_size 4000000 +[ 0.245429] pci 0000:15:00.0: res[16]=[mem 0x04000000-0x03ffffff] get_res_add_size add_size 4000000 +[ 0.245431] pci 0000:15:00.0: res[13]=[io 0x0100-0x00ff] get_res_add_size add_size 100 +[ 0.245433] pci 0000:15:00.0: res[14]=[io 0x0100-0x00ff] get_res_add_size add_size 100 +[ 0.245436] pci 0000:15:00.0: BAR 15: assigned [mem 0xf0000000-0xf3ffffff pref] +[ 0.245499] pci 0000:15:00.0: BAR 16: assigned [mem 0xc4000000-0xc7ffffff] +[ 0.245549] pci 0000:15:00.0: BAR 13: assigned [io 0x4000-0x40ff] +[ 0.245599] pci 0000:15:00.0: BAR 14: assigned [io 0x4400-0x44ff] +[ 0.245649] pci 0000:15:00.0: CardBus bridge to [bus 16-17] +[ 0.245697] pci 0000:15:00.0: bridge window [io 0x4000-0x40ff] +[ 0.245750] pci 0000:15:00.0: bridge window [io 0x4400-0x44ff] +[ 0.245803] pci 0000:15:00.0: bridge window [mem 0xf0000000-0xf3ffffff pref] +[ 0.245867] pci 0000:15:00.0: bridge window [mem 0xc4000000-0xc7ffffff] +[ 0.245921] pci 0000:00:1e.0: PCI bridge to [bus 15-18] +[ 0.245970] pci 0000:00:1e.0: bridge window [io 0x4000-0x7fff] +[ 0.246034] pci 0000:00:1e.0: bridge window [mem 0xf4300000-0xf7ffffff] +[ 0.246087] pci 0000:00:1e.0: bridge window [mem 0xf0000000-0xf3ffffff 64bit pref] +[ 0.246154] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7] +[ 0.246156] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff] +[ 0.246158] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff] +[ 0.246160] pci_bus 0000:00: resource 7 [mem 0x000d4000-0x000d7fff] +[ 0.246162] pci_bus 0000:00: resource 8 [mem 0x000d8000-0x000dbfff] +[ 0.246164] pci_bus 0000:00: resource 9 [mem 0xc0000000-0xfebfffff] +[ 0.246167] pci_bus 0000:02: resource 0 [io 0x8000-0x8fff] +[ 0.246169] pci_bus 0000:02: resource 1 [mem 0xc0000000-0xc01fffff] +[ 0.246171] pci_bus 0000:02: resource 2 [mem 0xc0200000-0xc03fffff 64bit pref] +[ 0.246173] pci_bus 0000:05: resource 0 [io 0x2000-0x2fff] +[ 0.246175] pci_bus 0000:05: resource 1 [mem 0xf8000000-0xf9ffffff] +[ 0.246178] pci_bus 0000:05: resource 2 [mem 0xf4000000-0xf40fffff 64bit pref] +[ 0.246180] pci_bus 0000:0d: resource 0 [io 0x3000-0x3fff] +[ 0.246182] pci_bus 0000:0d: resource 1 [mem 0xfa000000-0xfbffffff] +[ 0.246184] pci_bus 0000:0d: resource 2 [mem 0xf4100000-0xf41fffff 64bit pref] +[ 0.246186] pci_bus 0000:15: resource 0 [io 0x4000-0x7fff] +[ 0.246188] pci_bus 0000:15: resource 1 [mem 0xf4300000-0xf7ffffff] +[ 0.246191] pci_bus 0000:15: resource 2 [mem 0xf0000000-0xf3ffffff 64bit pref] +[ 0.246193] pci_bus 0000:15: resource 4 [io 0x0000-0x0cf7] +[ 0.246195] pci_bus 0000:15: resource 5 [io 0x0d00-0xffff] +[ 0.246197] pci_bus 0000:15: resource 6 [mem 0x000a0000-0x000bffff] +[ 0.246199] pci_bus 0000:15: resource 7 [mem 0x000d4000-0x000d7fff] +[ 0.246201] pci_bus 0000:15: resource 8 [mem 0x000d8000-0x000dbfff] +[ 0.246203] pci_bus 0000:15: resource 9 [mem 0xc0000000-0xfebfffff] +[ 0.246205] pci_bus 0000:16: resource 0 [io 0x4000-0x40ff] +[ 0.246207] pci_bus 0000:16: resource 1 [io 0x4400-0x44ff] +[ 0.246209] pci_bus 0000:16: resource 2 [mem 0xf0000000-0xf3ffffff pref] +[ 0.246212] pci_bus 0000:16: resource 3 [mem 0xc4000000-0xc7ffffff] +[ 0.246249] NET: Registered protocol family 2 +[ 0.246495] TCP established hash table entries: 8192 (order: 3, 32768 bytes) +[ 0.246559] TCP bind hash table entries: 8192 (order: 4, 65536 bytes) +[ 0.246630] TCP: Hash tables configured (established 8192 bind 8192) +[ 0.246707] TCP: reno registered +[ 0.246753] UDP hash table entries: 512 (order: 2, 16384 bytes) +[ 0.246808] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes) +[ 0.246916] NET: Registered protocol family 1 +[ 0.246974] pci 0000:00:02.0: Boot video device +[ 0.248116] PCI: CLS 64 bytes, default 64 +[ 0.248159] Trying to unpack rootfs image as initramfs... +[ 0.684192] Freeing initrd memory: 21860K (f553e000 - f6a97000) +[ 0.684342] Simple Boot Flag at 0x35 set to 0x1 +[ 0.684544] microcode: CPU0 sig=0x1067a, pf=0x80, revision=0xa07 +[ 0.684599] microcode: CPU1 sig=0x1067a, pf=0x80, revision=0xa07 +[ 0.684721] microcode: Microcode Update Driver: v2.00 , Peter Oruba +[ 0.684784] Scanning for low memory corruption every 60 seconds +[ 0.685127] Initialise system trusted keyring +[ 0.685217] audit: initializing netlink socket (disabled) +[ 0.685277] type=2000 audit(1430654717.684:1): initialized +[ 0.700910] bounce pool size: 64 pages +[ 0.700966] HugeTLB registered 2 MB page size, pre-allocated 0 pages +[ 0.702589] zbud: loaded +[ 0.702704] VFS: Disk quotas dquot_6.5.2 +[ 0.702800] Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) +[ 0.703367] fuse init (API version 7.22) +[ 0.703503] msgmni has been set to 1659 +[ 0.703617] Key type big_key registered +[ 0.704163] Key type asymmetric registered +[ 0.704211] Asymmetric key parser 'x509' registered +[ 0.704292] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252) +[ 0.704386] io scheduler noop registered +[ 0.704435] io scheduler deadline registered +[ 0.704513] io scheduler cfq registered +[ 0.704562] io scheduler bfq registered (default) +[ 0.704609] BFQ I/O-scheduler version: v7r5 +[ 0.704883] pcieport 0000:00:1c.0: irq 40 for MSI/MSI-X +[ 0.705125] pcieport 0000:00:1c.3: irq 41 for MSI/MSI-X +[ 0.705309] pcieport 0000:00:1c.4: irq 42 for MSI/MSI-X +[ 0.705477] pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt +[ 0.705532] pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded +[ 0.705591] pcieport 0000:00:1c.3: Signaling PME through PCIe PME interrupt +[ 0.705645] pcie_pme 0000:00:1c.3:pcie01: service driver pcie_pme loaded +[ 0.705703] pcieport 0000:00:1c.4: Signaling PME through PCIe PME interrupt +[ 0.705756] pcie_pme 0000:00:1c.4:pcie01: service driver pcie_pme loaded +[ 0.705776] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 +[ 0.705880] pciehp 0000:00:1c.0:pcie04: HPC vendor_id 8086 device_id 2940 ss_vid 17aa ss_did 20f3 +[ 0.706016] pciehp 0000:00:1c.0:pcie04: service driver pciehp loaded +[ 0.706032] pciehp 0000:00:1c.3:pcie04: HPC vendor_id 8086 device_id 2946 ss_vid 17aa ss_did 20f3 +[ 0.706154] pciehp 0000:00:1c.3:pcie04: service driver pciehp loaded +[ 0.706169] pciehp 0000:00:1c.4:pcie04: HPC vendor_id 8086 device_id 2948 ss_vid 17aa ss_did 20f3 +[ 0.706291] pciehp 0000:00:1c.4:pcie04: service driver pciehp loaded +[ 0.706298] pciehp: PCI Express Hot Plug Controller Driver version: 0.4 +[ 0.706409] intel_idle: does not run on family 6 model 23 +[ 0.706417] ipmi message handler version 39.2 +[ 0.706620] ACPI: Deprecated procfs I/F for AC is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +[ 0.706852] ACPI: AC Adapter [AC] (on-line) +[ 0.706996] input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0C0D:00/input/input0 +[ 0.707373] ACPI: Lid Switch [LID] +[ 0.707458] input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input1 +[ 0.707521] ACPI: Sleep Button [SLPB] +[ 0.707612] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 +[ 0.707674] ACPI: Power Button [PWRF] +[ 0.709269] Monitor-Mwait will be used to enter C-1 state +[ 0.709274] Monitor-Mwait will be used to enter C-2 state +[ 0.709278] Monitor-Mwait will be used to enter C-3 state +[ 0.709281] tsc: Marking TSC unstable due to TSC halts in idle +[ 0.709337] ACPI: acpi_idle registered with cpuidle +[ 0.711717] thermal LNXTHERM:00: registered as thermal_zone0 +[ 0.711771] ACPI: Thermal Zone [THM0] (48 C) +[ 0.729046] thermal LNXTHERM:01: registered as thermal_zone1 +[ 0.729095] ACPI: Thermal Zone [THM1] (50 C) +[ 0.729177] GHES: HEST is not enabled! +[ 0.729318] isapnp: Scanning for PnP cards... +[ 0.729400] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +[ 0.729409] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled +[ 0.729519] ACPI: Battery Slot [BAT0] (battery absent) +[ 0.730776] Linux agpgart interface v0.103 +[ 0.730923] agpgart-intel 0000:00:00.0: Intel GM45 Chipset +[ 0.731056] agpgart-intel 0000:00:00.0: detected gtt size: 2097152K total, 262144K mappable +[ 0.732082] agpgart-intel 0000:00:00.0: detected 32768K stolen memory +[ 0.732225] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xd0000000 +[ 0.738049] tpm_tis 00:09: 1.2 TPM (device-id 0x1020, rev-id 6) +[ 0.738099] tpm_tis 00:09: Intel iTPM workaround enabled +[ 0.810044] tpm_tis 00:09: TPM is disabled/deactivated (0x6) +[ 0.811502] brd: module loaded +[ 0.812298] loop: module loaded +[ 0.812879] libphy: Fixed MDIO Bus: probed +[ 0.813069] tun: Universal TUN/TAP device driver, 1.6 +[ 0.813118] tun: (C) 1999-2004 Max Krasnyansky +[ 0.813201] PPP generic driver version 2.4.2 +[ 0.813289] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver +[ 0.813340] ehci-pci: EHCI PCI platform driver +[ 0.813508] ehci-pci 0000:00:1a.7: EHCI Host Controller +[ 0.813561] ehci-pci 0000:00:1a.7: new USB bus registered, assigned bus number 1 +[ 0.813636] ehci-pci 0000:00:1a.7: debug port 1 +[ 0.817590] ehci-pci 0000:00:1a.7: cache line size of 64 is not supported +[ 0.817660] ehci-pci 0000:00:1a.7: irq 23, io mem 0xfc625c00 +[ 0.824040] ehci-pci 0000:00:1a.7: USB 2.0 started, EHCI 1.00 +[ 0.824127] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 +[ 0.824178] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.824238] usb usb1: Product: EHCI Host Controller +[ 0.824286] usb usb1: Manufacturer: Linux 3.13.0-39-lowlatency ehci_hcd +[ 0.824336] usb usb1: SerialNumber: 0000:00:1a.7 +[ 0.824479] hub 1-0:1.0: USB hub found +[ 0.824531] hub 1-0:1.0: 6 ports detected +[ 0.824916] ehci-pci 0000:00:1d.7: EHCI Host Controller +[ 0.824969] ehci-pci 0000:00:1d.7: new USB bus registered, assigned bus number 2 +[ 0.825060] ehci-pci 0000:00:1d.7: debug port 1 +[ 0.829012] ehci-pci 0000:00:1d.7: cache line size of 64 is not supported +[ 0.829056] ehci-pci 0000:00:1d.7: irq 19, io mem 0xfc626000 +[ 0.835018] ehci-pci 0000:00:1d.7: USB 2.0 started, EHCI 1.00 +[ 0.835135] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002 +[ 0.835186] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.835246] usb usb2: Product: EHCI Host Controller +[ 0.835294] usb usb2: Manufacturer: Linux 3.13.0-39-lowlatency ehci_hcd +[ 0.835345] usb usb2: SerialNumber: 0000:00:1d.7 +[ 0.839276] Monitor-Mwait will be used to enter C-3 state +[ 0.839280] hub 2-0:1.0: USB hub found +[ 0.839336] hub 2-0:1.0: 6 ports detected +[ 0.839956] ehci-platform: EHCI generic platform driver +[ 0.840024] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver +[ 0.840073] ohci-pci: OHCI PCI platform driver +[ 0.840131] ohci-platform: OHCI generic platform driver +[ 0.840186] uhci_hcd: USB Universal Host Controller Interface driver +[ 0.840318] uhci_hcd 0000:00:1a.0: UHCI Host Controller +[ 0.840369] uhci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 3 +[ 0.840491] uhci_hcd 0000:00:1a.0: irq 20, io base 0x00001840 +[ 0.840590] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.840641] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.840702] usb usb3: Product: UHCI Host Controller +[ 0.840750] usb usb3: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.840800] usb usb3: SerialNumber: 0000:00:1a.0 +[ 0.840938] hub 3-0:1.0: USB hub found +[ 0.840990] hub 3-0:1.0: 2 ports detected +[ 0.841231] uhci_hcd 0000:00:1a.1: UHCI Host Controller +[ 0.841283] uhci_hcd 0000:00:1a.1: new USB bus registered, assigned bus number 4 +[ 0.841397] uhci_hcd 0000:00:1a.1: irq 21, io base 0x00001860 +[ 0.841499] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.841550] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.841610] usb usb4: Product: UHCI Host Controller +[ 0.841658] usb usb4: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.842320] usb usb4: SerialNumber: 0000:00:1a.1 +[ 0.842458] hub 4-0:1.0: USB hub found +[ 0.842510] hub 4-0:1.0: 2 ports detected +[ 0.842736] uhci_hcd 0000:00:1a.2: UHCI Host Controller +[ 0.842787] uhci_hcd 0000:00:1a.2: new USB bus registered, assigned bus number 5 +[ 0.842901] uhci_hcd 0000:00:1a.2: irq 22, io base 0x00001880 +[ 0.843012] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.843063] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.843123] usb usb5: Product: UHCI Host Controller +[ 0.843171] usb usb5: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.843222] usb usb5: SerialNumber: 0000:00:1a.2 +[ 0.843359] hub 5-0:1.0: USB hub found +[ 0.843411] hub 5-0:1.0: 2 ports detected +[ 0.843644] uhci_hcd 0000:00:1d.0: UHCI Host Controller +[ 0.843695] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 6 +[ 0.843809] uhci_hcd 0000:00:1d.0: irq 16, io base 0x000018a0 +[ 0.843909] usb usb6: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.843962] usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.844034] usb usb6: Product: UHCI Host Controller +[ 0.844082] usb usb6: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.844132] usb usb6: SerialNumber: 0000:00:1d.0 +[ 0.844271] hub 6-0:1.0: USB hub found +[ 0.844323] hub 6-0:1.0: 2 ports detected +[ 0.844553] uhci_hcd 0000:00:1d.1: UHCI Host Controller +[ 0.844605] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 7 +[ 0.844717] uhci_hcd 0000:00:1d.1: irq 17, io base 0x000018c0 +[ 0.844816] usb usb7: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.844867] usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.844927] usb usb7: Product: UHCI Host Controller +[ 0.844976] usb usb7: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.845037] usb usb7: SerialNumber: 0000:00:1d.1 +[ 0.845176] hub 7-0:1.0: USB hub found +[ 0.845229] hub 7-0:1.0: 2 ports detected +[ 0.845458] uhci_hcd 0000:00:1d.2: UHCI Host Controller +[ 0.845510] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 8 +[ 0.845625] uhci_hcd 0000:00:1d.2: irq 18, io base 0x000018e0 +[ 0.845727] usb usb8: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.845777] usb usb8: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.845837] usb usb8: Product: UHCI Host Controller +[ 0.845885] usb usb8: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.845935] usb usb8: SerialNumber: 0000:00:1d.2 +[ 0.846093] hub 8-0:1.0: USB hub found +[ 0.846146] hub 8-0:1.0: 2 ports detected +[ 0.846371] i8042: PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12 +[ 0.854811] serio: i8042 KBD port at 0x60,0x64 irq 1 +[ 0.854862] serio: i8042 AUX port at 0x60,0x64 irq 12 +[ 0.855027] mousedev: PS/2 mouse device common for all mice +[ 0.855218] rtc_cmos 00:06: RTC can wake from S4 +[ 0.855389] rtc_cmos 00:06: rtc core: registered rtc_cmos as rtc0 +[ 0.855484] rtc_cmos 00:06: alarms up to one month, y3k, 114 bytes nvram, hpet irqs +[ 0.855618] device-mapper: uevent: version 1.0.3 +[ 0.855725] device-mapper: ioctl: 4.27.0-ioctl (2013-10-30) initialised: dm-devel@redhat.com +[ 0.855808] platform eisa.0: Probing EISA bus 0 +[ 0.855857] platform eisa.0: EISA: Cannot allocate resource for mainboard +[ 0.855907] platform eisa.0: Cannot allocate resource for EISA slot 1 +[ 0.855958] platform eisa.0: Cannot allocate resource for EISA slot 2 +[ 0.856019] platform eisa.0: Cannot allocate resource for EISA slot 3 +[ 0.856070] platform eisa.0: Cannot allocate resource for EISA slot 4 +[ 0.856120] platform eisa.0: Cannot allocate resource for EISA slot 5 +[ 0.856170] platform eisa.0: Cannot allocate resource for EISA slot 6 +[ 0.856220] platform eisa.0: Cannot allocate resource for EISA slot 7 +[ 0.856282] platform eisa.0: Cannot allocate resource for EISA slot 8 +[ 0.856332] platform eisa.0: EISA: Detected 0 cards +[ 0.856384] cpufreq-nforce2: No nForce2 chipset. +[ 0.856432] ledtrig-cpu: registered to indicate activity on CPUs +[ 0.856626] TCP: cubic registered +[ 0.856776] NET: Registered protocol family 10 +[ 0.857052] NET: Registered protocol family 17 +[ 0.857107] Key type dns_resolver registered +[ 0.857329] Using IPI No-Shortcut mode +[ 0.857448] Loading compiled-in X.509 certificates +[ 0.860267] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3 +[ 0.861508] Loaded X.509 cert 'Magrathea: Glacier signing key: 680cb30646cc91d1b36b663dc44e87808b042a52' +[ 0.861583] registered taskstats version 1 +[ 0.863893] Key type trusted registered +[ 0.865792] Key type encrypted registered +[ 0.867715] AppArmor: AppArmor sha1 policy hashing enabled +[ 0.885045] tpm_tis 00:09: A TPM error (6) occurred attempting to read a pcr value +[ 0.885107] IMA: No TPM chip found, activating TPM-bypass! +[ 0.885507] regulator-dummy: disabling +[ 0.885577] Magic number: 15:3:76 +[ 0.885705] rtc_cmos 00:06: setting system clock to 2015-05-03 12:05:18 UTC (1430654718) +[ 0.901299] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found +[ 0.901352] EDD information not available. +[ 0.901503] PM: Hibernation image not present or could not be loaded. +[ 1.087749] isapnp: No Plug & Play device found +[ 1.088240] Freeing unused kernel memory: 868K (c19c3000 - c1a9c000) +[ 1.088350] Write protecting the kernel text: 6580k +[ 1.088525] Write protecting the kernel read-only data: 2776k +[ 1.088577] NX-protecting the kernel data: 5708k +[ 1.110287] systemd-udevd[116]: starting version 204 +[ 1.141089] usb 2-2: new high-speed USB device number 2 using ehci-pci +[ 1.166650] [drm] Initialized drm 1.1.0 20060810 +[ 1.176744] pps_core: LinuxPPS API ver. 1 registered +[ 1.176797] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti +[ 1.190035] wmi: Mapper loaded +[ 1.225811] PTP clock support registered +[ 1.232326] ahci 0000:00:1f.2: version 3.0 +[ 1.232520] ahci 0000:00:1f.2: irq 43 for MSI/MSI-X +[ 1.232572] ahci 0000:00:1f.2: SSS flag set, parallel bus scan disabled +[ 1.232655] ahci 0000:00:1f.2: AHCI 0001.0200 32 slots 4 ports 3 Gbps 0x3 impl SATA mode +[ 1.232721] ahci 0000:00:1f.2: flags: 64bit ncq sntf stag pm led clo pio slum part ccc sxs +[ 1.237032] scsi0 : ahci +[ 1.238024] scsi1 : ahci +[ 1.241034] scsi2 : ahci +[ 1.241728] sdhci: Secure Digital Host Controller Interface driver +[ 1.241782] sdhci: Copyright(c) Pierre Ossman +[ 1.242020] scsi3 : ahci +[ 1.242138] ata1: SATA max UDMA/133 abar m2048@0xfc625000 port 0xfc625100 irq 43 +[ 1.242204] ata2: SATA max UDMA/133 abar m2048@0xfc625000 port 0xfc625180 irq 43 +[ 1.242267] ata3: DUMMY +[ 1.242314] ata4: DUMMY +[ 1.261164] usb 2-2: New USB device found, idVendor=0b95, idProduct=1790 +[ 1.261223] usb 2-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3 +[ 1.261278] usb 2-2: Product: AX88179 +[ 1.261329] usb 2-2: Manufacturer: ASIX Elec. +[ 1.261381] usb 2-2: SerialNumber: 00803F5D087AE3 +[ 1.290396] sdhci-pci 0000:15:00.2: SDHCI controller found [1180:0822] (rev 21) +[ 1.292641] sdhci-pci 0000:15:00.2: Will use DMA mode even though HW doesn't fully claim to support it. +[ 1.292719] sdhci-pci 0000:15:00.2: dummy supplies not allowed +[ 1.292771] mmc0: no vqmmc regulator found +[ 1.292821] sdhci-pci 0000:15:00.2: dummy supplies not allowed +[ 1.292872] mmc0: no vmmc regulator found +[ 1.293927] sdhci-pci 0000:15:00.2: Will use DMA mode even though HW doesn't fully claim to support it. +[ 1.296964] mmc0: SDHCI controller on PCI [0000:15:00.2] using DMA +[ 1.315167] [drm] Memory usable by graphics device = 2048M +[ 1.323106] i915 0000:00:02.0: irq 44 for MSI/MSI-X +[ 1.323122] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). +[ 1.323176] [drm] Driver supports precise vblank timestamp query. +[ 1.325610] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem +[ 1.327406] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k +[ 1.327457] e1000e: Copyright(c) 1999 - 2013 Intel Corporation. +[ 1.360077] firewire_ohci 0000:15:00.1: added OHCI v1.10 device as card 0, 4 IR + 4 IT contexts, quirks 0x11 +[ 1.404196] fbcon: inteldrmfb (fb0) is primary device +[ 1.547135] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300) +[ 1.548423] ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.548427] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out +[ 1.548539] ata1.00: ACPI cmd ef/5f:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.548541] ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out +[ 1.589778] ata1.00: ATA-8: WDC WD2500BEVS-08VAT2, 14.01A14, max UDMA/133 +[ 1.589781] ata1.00: 488397168 sectors, multi 16: LBA48 NCQ (depth 31/32), AA +[ 1.591940] ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.591944] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out +[ 1.592061] ata1.00: ACPI cmd ef/5f:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.592064] ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out +[ 1.594016] ata1.00: configured for UDMA/133 +[ 1.594229] scsi 0:0:0:0: Direct-Access ATA WDC WD2500BEVS-0 14.0 PQ: 0 ANSI: 5 +[ 1.594501] sd 0:0:0:0: [sda] 488397168 512-byte logical blocks: (250 GB/232 GiB) +[ 1.594518] sd 0:0:0:0: Attached scsi generic sg0 type 0 +[ 1.594607] sd 0:0:0:0: [sda] Write Protect is off +[ 1.594610] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 +[ 1.594652] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA +[ 1.629835] sda: sda1 sda2 < sda5 sda6 > +[ 1.630551] sd 0:0:0:0: [sda] Attached SCSI disk +[ 1.677260] psmouse serio1: alps: Unknown ALPS touchpad: E7=10 00 64, EC=10 00 64 +[ 1.861220] firewire_core 0000:15:00.1: created device fw0: GUID 00016c2000b8125f, S400 +[ 1.899114] ata2: SATA link up 1.5 Gbps (SStatus 113 SControl 300) +[ 1.906682] ata2.00: ACPI cmd e3/00:1f:00:00:00:a0 (IDLE) succeeded +[ 1.911726] ata2.00: ACPI cmd e3/00:02:00:00:00:a0 (IDLE) succeeded +[ 1.911730] ata2.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out +[ 1.913488] ata2.00: ATAPI: Optiarc DVD RW AD-7930H, 1.D0, max UDMA/100 +[ 1.925908] ata2.00: ACPI cmd e3/00:1f:00:00:00:a0 (IDLE) succeeded +[ 1.930132] Console: switching to colour frame buffer device 128x48 +[ 1.930934] ata2.00: ACPI cmd e3/00:02:00:00:00:a0 (IDLE) succeeded +[ 1.930938] ata2.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out +[ 1.932628] ata2.00: configured for UDMA/100 +[ 1.939201] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device +[ 1.941707] i915 0000:00:02.0: registered panic notifier +[ 1.950136] scsi 1:0:0:0: CD-ROM Optiarc DVD RW AD-7930H 1.D0 PQ: 0 ANSI: 5 +[ 1.969550] sr0: scsi3-mmc drive: 24x/24x writer dvd-ram cd/rw xa/form2 cdda tray +[ 1.972132] cdrom: Uniform CD-ROM driver Revision: 3.20 +[ 1.974846] sr 1:0:0:0: Attached scsi CD-ROM sr0 +[ 1.974939] sr 1:0:0:0: Attached scsi generic sg1 type 5 +[ 1.978931] ACPI: Video Device [VID] (multi-head: yes rom: no post: no) +[ 1.989556] acpi device:02: registered as cooling_device2 +[ 1.992260] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input6 +[ 1.995024] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0 +[ 1.997875] e1000e 0000:00:19.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode +[ 2.000740] e1000e 0000:00:19.0: irq 45 for MSI/MSI-X +[ 2.028044] psmouse serio1: trackpoint: IBM TrackPoint firmware: 0x0e, buttons: 3/3 +[ 2.045577] input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/input/input5 +[ 2.197236] e1000e 0000:00:19.0 eth0: (PCI Express:2.5GT/s:Width x1) 00:22:68:1d:5f:c1 +[ 2.199930] e1000e 0000:00:19.0 eth0: Intel(R) PRO/1000 Network Connection +[ 2.202618] e1000e 0000:00:19.0 eth0: MAC: 7, PHY: 8, PBA No: 1008FF-0FF +[ 2.467919] md: linear personality registered for level -1 +[ 2.476368] md: multipath personality registered for level -4 +[ 2.484981] md: raid0 personality registered for level 0 +[ 2.494883] md: raid1 personality registered for level 1 +[ 2.523049] raid6: mmxx1 1988 MB/s +[ 2.540029] raid6: mmxx2 2339 MB/s +[ 2.557056] raid6: sse1x1 1410 MB/s +[ 2.574038] raid6: sse1x2 1792 MB/s +[ 2.591037] raid6: sse2x1 2605 MB/s +[ 2.608037] raid6: sse2x2 3210 MB/s +[ 2.608076] raid6: using algorithm sse2x2 (3210 MB/s) +[ 2.608125] raid6: using ssse3x1 recovery algorithm +[ 2.615066] xor: measuring software checksum speed +[ 2.625030] pIII_sse : 5932.000 MB/sec +[ 2.635031] prefetch64-sse: 6756.000 MB/sec +[ 2.635078] xor: using function: prefetch64-sse (6756.000 MB/sec) +[ 2.641070] async_tx: api initialized (async) +[ 2.676429] md: raid6 personality registered for level 6 +[ 2.676484] md: raid5 personality registered for level 5 +[ 2.676662] md: raid4 personality registered for level 4 +[ 2.691632] md: raid10 personality registered for level 10 +[ 2.805016] random: nonblocking pool is initialized +[ 2.920817] bio: create slab at 1 +[ 2.921930] Btrfs loaded +[ 3.201253] EXT4-fs (sda1): mounted filesystem with ordered data mode. Opts: (null) +[ 11.687514] Adding 6894588k swap on /dev/sda5. Priority:-1 extents:1 across:6894588k FS +[ 11.740261] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +[ 11.856982] systemd-udevd[391]: starting version 204 +[ 11.988698] lp: driver loaded but no devices found +[ 12.017169] ppdev: user-space parallel port driver +[ 12.240415] Non-volatile memory driver v1.3 +[ 12.279756] thinkpad_acpi: ThinkPad ACPI Extras v0.25 +[ 12.279761] thinkpad_acpi: http://ibm-acpi.sf.net/ +[ 12.279763] thinkpad_acpi: ThinkPad BIOS 7VET83WW (3.13 ), EC 7VHT16WW-1.06 +[ 12.279766] thinkpad_acpi: Lenovo ThinkPad T500, model 224397G +[ 12.307500] type=1400 audit(1430651129.921:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/sbin/dhclient" pid=462 comm="apparmor_parser" +[ 12.307510] type=1400 audit(1430651129.921:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=462 comm="apparmor_parser" +[ 12.307517] type=1400 audit(1430651129.921:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=462 comm="apparmor_parser" +[ 12.309315] type=1400 audit(1430651129.923:5): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=462 comm="apparmor_parser" +[ 12.309325] type=1400 audit(1430651129.923:6): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=462 comm="apparmor_parser" +[ 12.309718] type=1400 audit(1430651129.923:7): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=462 comm="apparmor_parser" +[ 12.327128] thinkpad_acpi: detected a 16-level brightness capable ThinkPad +[ 12.329873] thinkpad_acpi: radio switch found; radios are enabled +[ 12.329894] thinkpad_acpi: This ThinkPad has standard ACPI backlight brightness control, supported by the ACPI video driver +[ 12.329897] thinkpad_acpi: Disabling thinkpad-acpi brightness events by default... +[ 12.365868] thinkpad_acpi: Standard ACPI backlight interface available, not loading native one +[ 12.370496] thinkpad_acpi: Console audio control enabled, mode: monitor (read only) +[ 12.382976] input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input7 +[ 12.409233] r592: driver successfully loaded +[ 12.435744] yenta_cardbus 0000:15:00.0: CardBus bridge found [17aa:20c6] +[ 12.517664] ACPI Warning: 0x00001028-0x0000102f SystemIO conflicts with Region \_SB_.PCI0.LPC_.PMIO 1 (20131115/utaddress-251) +[ 12.517675] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 12.517680] ACPI Warning: 0x000011b0-0x000011bf SystemIO conflicts with Region \_SB_.PCI0.LPC_.LPIO 1 (20131115/utaddress-251) +[ 12.517686] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 12.517689] ACPI Warning: 0x00001180-0x000011af SystemIO conflicts with Region \_SB_.PCI0.LPC_.LPIO 1 (20131115/utaddress-251) +[ 12.517694] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 12.517696] lpc_ich: Resource conflict(s) found affecting gpio_ich +[ 12.537570] snd_hda_intel 0000:00:1b.0: irq 46 for MSI/MSI-X +[ 12.559824] yenta_cardbus 0000:15:00.0: ISA IRQ mask 0x0cb8, PCI irq 16 +[ 12.559831] yenta_cardbus 0000:15:00.0: Socket status: 30000006 +[ 12.559839] yenta_cardbus 0000:15:00.0: pcmcia: parent PCI bridge window: [io 0x4000-0x7fff] +[ 12.559844] pcmcia_socket pcmcia_socket0: cs: IO port probe 0x4000-0x7fff: +[ 12.570045] hda_codec: CX20561 (Hermosa): BIOS auto-probing. +[ 12.570487] autoconfig: line_outs=1 (0x1a/0x0/0x0/0x0/0x0) type:speaker +[ 12.570491] speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) +[ 12.570493] hp_outs=2 (0x19/0x16/0x0/0x0/0x0) +[ 12.570495] mono: mono_out=0x0 +[ 12.570498] dig-out=0x1c/0x0 +[ 12.570500] inputs: +[ 12.570503] Mic=0x18 +[ 12.570505] Internal Mic=0x1d +[ 12.570507] Dock Mic=0x17 +[ 12.571526] hda_codec: Enable sync_write for stable communication +[ 12.574407] input: HDA Intel Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input11 +[ 12.574615] input: HDA Intel Dock Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input10 +[ 12.574789] input: HDA Intel Dock Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9 +[ 12.574959] input: HDA Intel Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input8 +[ 12.575690] mei_me 0000:00:03.0: irq 47 for MSI/MSI-X +[ 12.585028] device-mapper: multipath: version 1.6.0 loaded +[ 12.561557] excluding 0x4000-0x40ff 0x4400-0x44ff +[ 12.658770] yenta_cardbus 0000:15:00.0: pcmcia: parent PCI bridge window: [mem 0xf4300000-0xf7ffffff] +[ 12.658777] pcmcia_socket pcmcia_socket0: cs: memory probe 0xf4300000-0xf7ffffff: +[ 12.658782] excluding 0xf4300000-0xf46cffff +[ 12.658800] yenta_cardbus 0000:15:00.0: pcmcia: parent PCI bridge window: [mem 0xf0000000-0xf3ffffff 64bit pref] +[ 12.658804] pcmcia_socket pcmcia_socket0: cs: memory probe 0xf0000000-0xf3ffffff: +[ 12.658826] excluding 0xf0000000-0xf3ffffff +[ 12.664392] r852: driver loaded successfully +[ 12.912402] kvm: disabled by bios +[ 12.940654] ax88179_178a 2-2:1.0 eth1: register 'ax88179_178a' at usb-0000:00:1d.7-2, ASIX AX88179 USB 3.0 Gigabit Ethernet, 80:3f:5d:08:7a:e3 +[ 12.943043] usbcore: registered new interface driver ax88179_178a +[ 12.979166] kvm: disabled by bios +[ 13.078215] systemd-udevd[413]: renamed network interface eth1 to eth2 +[ 13.117195] pcmcia_socket pcmcia_socket0: cs: IO port probe 0x100-0x3af: +[ 13.119548] clean. +[ 13.119578] pcmcia_socket pcmcia_socket0: cs: IO port probe 0x3e0-0x4ff: +[ 13.120473] excluding 0x4d0-0x4d7 +[ 13.120566] pcmcia_socket pcmcia_socket0: cs: IO port probe 0x820-0x8ff: +[ 13.121329] clean. +[ 13.121353] pcmcia_socket pcmcia_socket0: cs: IO port probe 0xc00-0xcf7: +[ 13.122201] clean. +[ 13.122229] pcmcia_socket pcmcia_socket0: cs: memory probe 0x0c0000-0x0fffff: +[ 13.122237] excluding 0xc0000-0xd3fff 0xdc000-0xfffff +[ 13.122272] pcmcia_socket pcmcia_socket0: cs: memory probe 0xa0000000-0xa0ffffff: +[ 13.122287] excluding 0xa0000000-0xa0ffffff +[ 13.122311] pcmcia_socket pcmcia_socket0: cs: memory probe 0x60000000-0x60ffffff: +[ 13.122326] excluding 0x60000000-0x60ffffff +[ 13.122350] pcmcia_socket pcmcia_socket0: cs: IO port probe 0xa00-0xaff: +[ 13.123217] clean. +[ 41.374397] EXT4-fs (sda1): warning: mounting fs with errors, running e2fsck is recommended +[ 41.374705] EXT4-fs (sda1): re-mounted. Opts: errors=remount-ro +[ 41.528699] SGI XFS with ACLs, security attributes, realtime, large block/inode numbers, no debug enabled +[ 41.559407] XFS (sda6): Mounting Filesystem +[ 41.747785] XFS (sda6): Ending clean mount +[ 42.167809] init: failsafe main process (721) killed by TERM signal +[ 42.703391] type=1400 audit(1430651160.316:8): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/cups/backend/cups-pdf" pid=854 comm="apparmor_parser" +[ 42.703403] type=1400 audit(1430651160.316:9): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/cupsd" pid=854 comm="apparmor_parser" +[ 42.704201] type=1400 audit(1430651160.317:10): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/sbin/cupsd" pid=854 comm="apparmor_parser" +[ 42.817805] Bluetooth: Core ver 2.17 +[ 42.817834] NET: Registered protocol family 31 +[ 42.817836] Bluetooth: HCI device and connection manager initialized +[ 42.817847] Bluetooth: HCI socket layer initialized +[ 42.817852] Bluetooth: L2CAP socket layer initialized +[ 42.817860] Bluetooth: SCO socket layer initialized +[ 42.830260] Bluetooth: RFCOMM TTY layer initialized +[ 42.830273] Bluetooth: RFCOMM socket layer initialized +[ 42.830281] Bluetooth: RFCOMM ver 1.11 +[ 42.858743] type=1400 audit(1430651160.471:11): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/sbin/dhclient" pid=874 comm="apparmor_parser" +[ 42.858755] type=1400 audit(1430651160.471:12): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=874 comm="apparmor_parser" +[ 42.858763] type=1400 audit(1430651160.471:13): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=874 comm="apparmor_parser" +[ 42.859570] type=1400 audit(1430651160.472:14): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=874 comm="apparmor_parser" +[ 42.859578] type=1400 audit(1430651160.472:15): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=874 comm="apparmor_parser" +[ 42.859939] type=1400 audit(1430651160.472:16): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/lightdm/lightdm-guest-session" pid=873 comm="apparmor_parser" +[ 42.859948] type=1400 audit(1430651160.472:17): apparmor="STATUS" operation="profile_load" profile="unconfined" name="chromium" pid=873 comm="apparmor_parser" +[ 42.953835] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 +[ 42.953840] Bluetooth: BNEP filters: protocol multicast +[ 42.953851] Bluetooth: BNEP socket layer initialized +[ 43.051816] init: cups main process (855) killed by HUP signal +[ 43.051835] init: cups main process ended, respawning +[ 44.468481] e1000e 0000:00:19.0: irq 45 for MSI/MSI-X +[ 44.569206] e1000e 0000:00:19.0: irq 45 for MSI/MSI-X +[ 44.569418] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +[ 44.569930] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +[ 44.712188] init: plymouth-upstart-bridge main process ended, respawning +[ 44.884246] IPv6: ADDRCONF(NETDEV_UP): eth2: link is not ready +[ 44.884774] IPv6: ADDRCONF(NETDEV_UP): eth2: link is not ready +[ 47.806197] ax88179_178a 2-2:1.0 eth2: ax88179 - Link status is: 1 +[ 47.808322] IPv6: ADDRCONF(NETDEV_CHANGE): eth2: link becomes ready +[ 72.805208] audit_printk_skb: 78 callbacks suppressed +[ 72.805214] type=1400 audit(1430651190.418:44): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/cups/backend/cups-pdf" pid=2240 comm="apparmor_parser" +[ 72.805224] type=1400 audit(1430651190.418:45): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/sbin/cupsd" pid=2240 comm="apparmor_parser" +[ 72.806335] type=1400 audit(1430651190.419:46): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/sbin/cupsd" pid=2240 comm="apparmor_parser" +[ 103.542583] i2c /dev entries driver +[ 140.117085] [drm] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6 +[ 572.914142] perf samples too long (2509 > 2500), lowering kernel.perf_event_max_sample_rate to 50000 +[ 2475.161644] perf samples too long (5018 > 5000), lowering kernel.perf_event_max_sample_rate to 25000 +[ 9967.166214] init: upstart-udev-bridge main process (385) terminated with status 1 +[ 9967.166237] init: upstart-udev-bridge main process ended, respawning +[ 9967.166497] init: upstart-socket-bridge main process (636) terminated with status 1 +[ 9967.166515] init: upstart-socket-bridge main process ended, respawning +[ 9967.166734] init: upstart-file-bridge main process (762) terminated with status 1 +[ 9967.166751] init: upstart-file-bridge main process ended, respawning diff --git a/i18n/fr_FR/docs/future/dumps/t500log/dmidecode.log b/i18n/fr_FR/docs/future/dumps/t500log/dmidecode.log new file mode 100644 index 00000000..f5452d03 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/t500log/dmidecode.log @@ -0,0 +1,651 @@ +# dmidecode 2.12 +SMBIOS 2.4 present. +80 structures occupying 2833 bytes. +Table at 0x000E0010. + +Handle 0x0000, DMI type 0, 24 bytes +BIOS Information + Vendor: LENOVO + Version: 7VET83WW (3.13 ) + Release Date: 03/12/2010 + Address: 0xE0000 + Runtime Size: 128 kB + ROM Size: 4096 kB + Characteristics: + PCI is supported + PC Card (PCMCIA) is supported + PNP is supported + BIOS is upgradeable + BIOS shadowing is allowed + ESCD support is available + Boot from CD is supported + Selectable boot is supported + BIOS ROM is socketed + EDD is supported + ACPI is supported + USB legacy is supported + BIOS boot specification is supported + Targeted content distribution is supported + BIOS Revision: 3.19 + Firmware Revision: 1.6 + +Handle 0x0001, DMI type 1, 27 bytes +System Information + Manufacturer: LENOVO + Product Name: 224397G + Version: ThinkPad T500 + Serial Number: R889Z75 + UUID: 2EA16981-4FBB-11CB-A739-DB6D463577E9 + Wake-up Type: Power Switch + SKU Number: Not Specified + Family: ThinkPad T500 + +Handle 0x0002, DMI type 2, 8 bytes +Base Board Information + Manufacturer: LENOVO + Product Name: 224397G + Version: Not Available + Serial Number: VQ11102N32T + +Handle 0x0003, DMI type 3, 13 bytes +Chassis Information + Manufacturer: LENOVO + Type: Notebook + Lock: Not Present + Version: Not Available + Serial Number: Not Available + Asset Tag: No Asset Information + Boot-up State: Unknown + Power Supply State: Unknown + Thermal State: Unknown + Security Status: Unknown + +Handle 0x0004, DMI type 126, 13 bytes +Inactive + +Handle 0x0005, DMI type 126, 13 bytes +Inactive + +Handle 0x0006, DMI type 4, 35 bytes +Processor Information + Socket Designation: None + Type: Central Processor + Family: Other + Manufacturer: GenuineIntel + ID: 7A 06 01 00 FF FB EB BF + Signature: Type 0, Family 6, Model 23, Stepping 10 + Flags: + FPU (Floating-point unit on-chip) + VME (Virtual mode extension) + DE (Debugging extension) + PSE (Page size extension) + TSC (Time stamp counter) + MSR (Model specific registers) + PAE (Physical address extension) + MCE (Machine check exception) + CX8 (CMPXCHG8 instruction supported) + APIC (On-chip APIC hardware supported) + SEP (Fast system call) + MTRR (Memory type range registers) + PGE (Page global enable) + MCA (Machine check architecture) + CMOV (Conditional move instruction supported) + PAT (Page attribute table) + PSE-36 (36-bit page size extension) + CLFSH (CLFLUSH instruction supported) + DS (Debug store) + ACPI (ACPI supported) + MMX (MMX technology supported) + FXSR (FXSAVE and FXSTOR instructions supported) + SSE (Streaming SIMD extensions) + SSE2 (Streaming SIMD extensions 2) + SS (Self-snoop) + HTT (Multi-threading) + TM (Thermal monitor supported) + PBE (Pending break enabled) + Version: Intel(R) Core(TM)2 Duo CPU P8700 @ 2.53GHz + Voltage: 1.3 V + External Clock: 266 MHz + Max Speed: 2530 MHz + Current Speed: 2530 MHz + Status: Populated, Enabled + Upgrade: None + L1 Cache Handle: 0x000A + L2 Cache Handle: 0x000C + L3 Cache Handle: Not Provided + Serial Number: Not Specified + Asset Tag: Not Specified + Part Number: Not Specified + +Handle 0x0007, DMI type 5, 20 bytes +Memory Controller Information + Error Detecting Method: None + Error Correcting Capabilities: + None + Supported Interleave: One-way Interleave + Current Interleave: One-way Interleave + Maximum Memory Module Size: 4096 MB + Maximum Total Memory Size: 8192 MB + Supported Speeds: + Other + Supported Memory Types: + DIMM + SDRAM + Memory Module Voltage: 2.9 V + Associated Memory Slots: 2 + 0x0008 + 0x0009 + Enabled Error Correcting Capabilities: + Unknown + +Handle 0x0008, DMI type 6, 12 bytes +Memory Module Information + Socket Designation: DIMM Slot 1 + Bank Connections: 0 1 + Current Speed: 42 ns + Type: DIMM SDRAM + Installed Size: 2048 MB (Double-bank Connection) + Enabled Size: 2048 MB (Double-bank Connection) + Error Status: OK + +Handle 0x0009, DMI type 6, 12 bytes +Memory Module Information + Socket Designation: DIMM Slot 2 + Bank Connections: 2 3 + Current Speed: 42 ns + Type: DIMM SDRAM + Installed Size: 2048 MB (Double-bank Connection) + Enabled Size: 2048 MB (Double-bank Connection) + Error Status: OK + +Handle 0x000A, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L1 Cache + Configuration: Enabled, Socketed, Level 1 + Operational Mode: Write Back + Location: Internal + Installed Size: 64 kB + Maximum Size: 64 kB + Supported SRAM Types: + Synchronous + Installed SRAM Type: Synchronous + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Instruction + Associativity: 8-way Set-associative + +Handle 0x000B, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L1 Cache + Configuration: Enabled, Socketed, Level 1 + Operational Mode: Write Back + Location: Internal + Installed Size: 64 kB + Maximum Size: 64 kB + Supported SRAM Types: + Synchronous + Installed SRAM Type: Synchronous + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Data + Associativity: 8-way Set-associative + +Handle 0x000C, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L2 Cache + Configuration: Enabled, Socketed, Level 2 + Operational Mode: Write Back + Location: Internal + Installed Size: 3072 kB + Maximum Size: 3072 kB + Supported SRAM Types: + Burst + Installed SRAM Type: Burst + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Unified + Associativity: 8-way Set-associative + +Handle 0x000D, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: External Monitor + External Connector Type: DB-15 female + Port Type: Video Port + +Handle 0x000E, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Microphone Jack + External Connector Type: Mini Jack (headphones) + Port Type: Audio Port + +Handle 0x000F, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Headphone Jack + External Connector Type: Mini Jack (headphones) + Port Type: Audio Port + +Handle 0x0010, DMI type 126, 9 bytes +Inactive + +Handle 0x0011, DMI type 126, 9 bytes +Inactive + +Handle 0x0012, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Modem + External Connector Type: RJ-11 + Port Type: Modem Port + +Handle 0x0013, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Ethernet + External Connector Type: RJ-45 + Port Type: Network Port + +Handle 0x0014, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 1 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0015, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 2 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0016, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 3 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0017, DMI type 126, 9 bytes +Inactive + +Handle 0x0018, DMI type 126, 9 bytes +Inactive + +Handle 0x0019, DMI type 126, 9 bytes +Inactive + +Handle 0x001A, DMI type 126, 9 bytes +Inactive + +Handle 0x001B, DMI type 126, 9 bytes +Inactive + +Handle 0x001C, DMI type 126, 9 bytes +Inactive + +Handle 0x001D, DMI type 126, 9 bytes +Inactive + +Handle 0x001E, DMI type 126, 9 bytes +Inactive + +Handle 0x001F, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: IEEE1394 + External Connector Type: IEEE 1394 + Port Type: Firewire (IEEE P1394) + +Handle 0x0020, DMI type 9, 13 bytes +System Slot Information + Designation: ExpressCard Slot 1 + Type: x1 PCI Express + Current Usage: Available + Length: Other + ID: 0 + Characteristics: + Hot-plug devices are supported + +Handle 0x0021, DMI type 9, 13 bytes +System Slot Information + Designation: CardBus Slot 1 + Type: 32-bit PC Card (PCMCIA) + Current Usage: Available + Length: Other + ID: Adapter 1, Socket 0 + Characteristics: + 5.0 V is provided + 3.3 V is provided + PC Card-16 is supported + Cardbus is supported + Zoom Video is supported + Modem ring resume is supported + PME signal is supported + Hot-plug devices are supported + +Handle 0x0022, DMI type 126, 13 bytes +Inactive + +Handle 0x0023, DMI type 126, 13 bytes +Inactive + +Handle 0x0024, DMI type 9, 13 bytes +System Slot Information + Designation: Media Card Slot 1 + Type: Other + Current Usage: Available + Length: Other + Characteristics: + Hot-plug devices are supported + +Handle 0x0025, DMI type 126, 13 bytes +Inactive + +Handle 0x0026, DMI type 126, 13 bytes +Inactive + +Handle 0x0027, DMI type 10, 6 bytes +On Board Device Information + Type: Other + Status: Disabled + Description: IBM Embedded Security hardware + +Handle 0x0028, DMI type 11, 5 bytes +OEM Strings + String 1: IBM ThinkPad Embedded Controller -[7VHT16WW-1.06 ]- + +Handle 0x0029, DMI type 13, 22 bytes +BIOS Language Information + Language Description Format: Abbreviated + Installable Languages: 1 + enUS + Currently Installed Language: enUS + +Handle 0x002A, DMI type 15, 25 bytes +System Event Log + Area Length: 0 bytes + Header Start Offset: 0x0000 + Header Length: 16 bytes + Data Start Offset: 0x0010 + Access Method: General-purpose non-volatile data functions + Access Address: 0x0000 + Status: Valid, Not Full + Change Token: 0x00000036 + Header Format: Type 1 + Supported Log Type Descriptors: 1 + Descriptor 1: POST error + Data Format 1: POST results bitmap + +Handle 0x002B, DMI type 16, 15 bytes +Physical Memory Array + Location: System Board Or Motherboard + Use: System Memory + Error Correction Type: None + Maximum Capacity: 8 GB + Error Information Handle: Not Provided + Number Of Devices: 2 + +Handle 0x002C, DMI type 17, 27 bytes +Memory Device + Array Handle: 0x002B + Error Information Handle: No Error + Total Width: 64 bits + Data Width: 64 bits + Size: 2048 MB + Form Factor: SODIMM + Set: None + Locator: DIMM 1 + Bank Locator: Bank 0/1 + Type: DDR3 + Type Detail: Synchronous + Speed: 1066 MHz + Manufacturer: 80CE + Serial Number: 62A2F4AA + Asset Tag: 1007 + Part Number: M471B5673FH0-CF8 + +Handle 0x002D, DMI type 17, 27 bytes +Memory Device + Array Handle: 0x002B + Error Information Handle: No Error + Total Width: 64 bits + Data Width: 64 bits + Size: 2048 MB + Form Factor: SODIMM + Set: None + Locator: DIMM 2 + Bank Locator: Bank 2/3 + Type: DDR3 + Type Detail: Synchronous + Speed: 1066 MHz + Manufacturer: 80CE + Serial Number: 674E4052 + Asset Tag: 1007 + Part Number: M471B5673FH0-CF8 + +Handle 0x002E, DMI type 18, 23 bytes +32-bit Memory Error Information + Type: OK + Granularity: Unknown + Operation: Unknown + Vendor Syndrome: Unknown + Memory Array Address: Unknown + Device Address: Unknown + Resolution: Unknown + +Handle 0x002F, DMI type 19, 15 bytes +Memory Array Mapped Address + Starting Address: 0x00000000000 + Ending Address: 0x000FFFFFFFF + Range Size: 4 GB + Physical Array Handle: 0x002B + Partition Width: 2 + +Handle 0x0030, DMI type 20, 19 bytes +Memory Device Mapped Address + Starting Address: 0x00000000000 + Ending Address: 0x0007FFFFFFF + Range Size: 2 GB + Physical Device Handle: 0x002C + Memory Array Mapped Address Handle: 0x002F + Partition Row Position: 1 + +Handle 0x0031, DMI type 20, 19 bytes +Memory Device Mapped Address + Starting Address: 0x00080000000 + Ending Address: 0x000FFFFFFFF + Range Size: 2 GB + Physical Device Handle: 0x002D + Memory Array Mapped Address Handle: 0x002F + Partition Row Position: 1 + +Handle 0x0032, DMI type 21, 7 bytes +Built-in Pointing Device + Type: Track Point + Interface: PS/2 + Buttons: 3 + +Handle 0x0033, DMI type 126, 7 bytes +Inactive + +Handle 0x0034, DMI type 126, 26 bytes +Inactive + +Handle 0x0035, DMI type 126, 26 bytes +Inactive + +Handle 0x0036, DMI type 24, 5 bytes +Hardware Security + Power-On Password Status: Disabled + Keyboard Password Status: Disabled + Administrator Password Status: Disabled + Front Panel Reset Status: Unknown + +Handle 0x0037, DMI type 32, 11 bytes +System Boot Information + Status: No errors detected + +Handle 0x0038, DMI type 131, 17 bytes +OEM-specific Type + Header and Data: + 83 11 38 00 01 02 03 FF FF 1F 00 00 00 00 00 02 + 00 + Strings: + BOOTINF 20h + BOOTDEV 21h + KEYPTRS 23h + +Handle 0x0039, DMI type 131, 22 bytes +OEM-specific Type + Header and Data: + 83 16 39 00 01 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 01 + Strings: + TVT-Enablement + +Handle 0x003A, DMI type 132, 7 bytes +OEM-specific Type + Header and Data: + 84 07 3A 00 02 D8 36 + +Handle 0x003B, DMI type 126, 5 bytes +Inactive + +Handle 0x003C, DMI type 134, 13 bytes +OEM-specific Type + Header and Data: + 86 0D 3C 00 12 03 10 20 00 00 00 00 00 + +Handle 0x003D, DMI type 134, 16 bytes +OEM-specific Type + Header and Data: + 86 10 3D 00 00 49 4E 54 43 01 01 00 00 02 01 02 + Strings: + TPM INFO + System Reserved + +Handle 0x003E, DMI type 135, 13 bytes +OEM-specific Type + Header and Data: + 87 0D 3E 00 54 50 07 00 01 00 00 00 00 + +Handle 0x003F, DMI type 135, 18 bytes +OEM-specific Type + Header and Data: + 87 12 3F 00 54 50 07 01 01 B8 0F 00 00 00 02 00 + 00 00 + +Handle 0x0040, DMI type 135, 35 bytes +OEM-specific Type + Header and Data: + 87 23 40 00 54 50 07 02 42 41 59 20 49 2F 4F 20 + 01 00 02 00 00 0B 00 18 18 0E 18 02 00 0B 00 10 + 18 0A 18 + +Handle 0x0041, DMI type 135, 34 bytes +OEM-specific Type + Header and Data: + 87 22 41 00 54 50 07 04 01 06 01 01 02 00 02 01 + 02 00 03 01 02 00 04 01 02 00 05 01 02 00 06 01 + 02 00 + +Handle 0x0042, DMI type 135, 10 bytes +OEM-specific Type + Header and Data: + 87 0A 42 00 54 50 07 03 01 0A + +Handle 0x0043, DMI type 136, 6 bytes +OEM-specific Type + Header and Data: + 88 06 43 00 5A 5A + +Handle 0x0044, DMI type 126, 28 bytes +Inactive + +Handle 0x0045, DMI type 138, 40 bytes +OEM-specific Type + Header and Data: + 8A 28 45 00 14 01 02 01 40 02 01 40 02 01 40 02 + 01 40 01 40 42 49 4F 53 20 50 61 73 73 77 6F 72 + 64 20 46 6F 72 6D 61 74 + +Handle 0x0046, DMI type 139, 37 bytes +OEM-specific Type + Header and Data: + 8B 25 46 00 11 01 0A 00 00 00 00 00 00 00 00 00 + 00 50 57 4D 53 20 4B 65 79 20 49 6E 66 6F 72 6D + 61 74 69 6F 6E + +Handle 0x0047, DMI type 140, 67 bytes +OEM-specific Type + Header and Data: + 8C 43 47 00 4C 45 4E 4F 56 4F 0B 00 01 F6 9A B9 + C7 4F F5 79 58 D0 EB 27 97 73 A3 8D B7 01 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 + +Handle 0x0048, DMI type 140, 47 bytes +OEM-specific Type + Header and Data: + 8C 2F 48 00 4C 45 4E 4F 56 4F 0B 01 01 08 00 24 + 57 62 D4 30 E5 43 D7 A6 83 9E 6C 7E 7A 70 43 00 + 00 00 00 10 00 10 00 10 01 D0 00 20 01 00 01 + +Handle 0x0049, DMI type 140, 63 bytes +OEM-specific Type + Header and Data: + 8C 3F 49 00 4C 45 4E 4F 56 4F 0B 02 01 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +Handle 0x004A, DMI type 140, 17 bytes +OEM-specific Type + Header and Data: + 8C 11 4A 00 4C 45 4E 4F 56 4F 0B 03 01 00 00 00 + 00 + +Handle 0x004B, DMI type 140, 19 bytes +OEM-specific Type + Header and Data: + 8C 13 4B 00 4C 45 4E 4F 56 4F 0B 04 01 B2 00 53 + 4D 20 00 + +Handle 0x004C, DMI type 129, 8 bytes +OEM-specific Type + Header and Data: + 81 08 4C 00 01 01 02 00 + Strings: + Intel_ASF + Intel_ASF_001 + +Handle 0x004D, DMI type 130, 20 bytes +OEM-specific Type + Header and Data: + 82 14 4D 00 24 41 4D 54 01 00 00 00 00 A5 00 00 + 00 00 00 00 + +Handle 0x004E, DMI type 131, 64 bytes +OEM-specific Type + Header and Data: + 83 40 4E 00 14 00 00 00 00 00 40 2A 00 00 00 00 + F8 00 19 29 00 00 00 00 21 00 00 00 02 00 04 00 + FC 03 00 00 01 00 01 15 C8 00 BF 10 00 00 00 00 + 00 00 00 00 07 00 00 00 76 50 72 6F 00 00 00 00 + +Handle 0x004F, DMI type 127, 4 bytes +End Of Table + diff --git a/i18n/fr_FR/docs/future/dumps/t500log/ectool.log b/i18n/fr_FR/docs/future/dumps/t500log/ectool.log new file mode 100644 index 00000000..6b67bb66 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/t500log/ectool.log @@ -0,0 +1,19 @@ +EC RAM: + +00: a6 05 a0 40 fe 96 00 00 1f 02 47 00 00 00 80 00 +10: 00 00 ff ff f4 3c 87 09 5b ff 83 00 ff ff 2d 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 +30: 07 00 02 00 30 04 00 00 00 00 00 10 00 50 00 00 +40: 00 00 00 00 00 00 14 00 42 01 00 00 00 00 00 00 +50: 00 c0 02 19 df 07 05 03 0c 05 08 04 04 d0 07 8c +60: 0a b8 0b 7a 0d 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 12 30 80 24 23 26 80 80 80 80 80 +80: 00 00 00 06 b4 07 03 00 00 00 00 00 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 27 28 27 80 80 80 80 80 11 41 00 0e 00 00 00 00 +d0: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e0: 00 00 00 00 00 00 00 00 10 60 52 07 24 6e 55 03 +f0: 37 56 48 54 31 36 57 57 13 72 68 ee 13 72 4e 50 + diff --git a/i18n/fr_FR/docs/future/dumps/t500log/flashrom_info.log b/i18n/fr_FR/docs/future/dumps/t500log/flashrom_info.log new file mode 100644 index 00000000..35d9e914 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/t500log/flashrom_info.log @@ -0,0 +1,118 @@ +flashrom v0.9.8-r1889 on Linux 3.13.0-39-lowlatency (i686) +flashrom is free software, get the source code at http://www.flashrom.org + +flashrom was built with libpci 3.2.1, GCC 4.8.2, little endian +Command line (5 args): flashrom -V -p internal:laptop=force_I_want_a_brick -c MX25L3205D/MX25L3208D +Calibrating delay loop... OS timer resolution is 2 usecs, 789M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1002 us, 10000 myus = 10008 us, 8 myus = 10 us, OK. +Initializing internal programmer +No coreboot table found. +Using Internal DMI decoder. +DMI string chassis-type: "Notebook" +Laptop detected via DMI. +DMI string system-manufacturer: "LENOVO" +DMI string system-product-name: "224397G" +DMI string system-version: "ThinkPad T500" +DMI string baseboard-manufacturer: "LENOVO" +DMI string baseboard-product-name: "224397G" +DMI string baseboard-version: "Not Available" +======================================================================== +WARNING! You seem to be running flashrom on an unsupported laptop. +Laptops, notebooks and netbooks are difficult to support and we +recommend to use the vendor flashing utility. The embedded controller +(EC) in these machines often interacts badly with flashing. +See the manpage and http://www.flashrom.org/Laptops for details. + +If flash is shared with the EC, erase is guaranteed to brick your laptop +and write may brick your laptop. +Read and probe may irritate your EC and cause fan failure, backlight +failure and sudden poweroff. +You have been warned. +======================================================================== +Proceeding anyway because user forced us to. +Found chipset "Intel ICH9M" with PCI ID 8086:2919. +Enabling flash write... Root Complex Register Block address = 0xfed1c000 +GCS = 0x380461: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x1 (SPI) +Top Swap: not enabled +0xfff80000/0xffb80000 FWH IDSEL: 0x0 +0xfff00000/0xffb00000 FWH IDSEL: 0x0 +0xffe80000/0xffa80000 FWH IDSEL: 0x0 +0xffe00000/0xffa00000 FWH IDSEL: 0x0 +0xffd80000/0xff980000 FWH IDSEL: 0x0 +0xffd00000/0xff900000 FWH IDSEL: 0x0 +0xffc80000/0xff880000 FWH IDSEL: 0x0 +0xffc00000/0xff800000 FWH IDSEL: 0x0 +0xff700000/0xff300000 FWH IDSEL: 0x4 +0xff600000/0xff200000 FWH IDSEL: 0x5 +0xff500000/0xff100000 FWH IDSEL: 0x6 +0xff400000/0xff000000 FWH IDSEL: 0x7 +0xfff80000/0xffb80000 FWH decode enabled +0xfff00000/0xffb00000 FWH decode enabled +0xffe80000/0xffa80000 FWH decode enabled +0xffe00000/0xffa00000 FWH decode enabled +0xffd80000/0xff980000 FWH decode enabled +0xffd00000/0xff900000 FWH decode enabled +0xffc80000/0xff880000 FWH decode enabled +0xffc00000/0xff800000 FWH decode enabled +0xff700000/0xff300000 FWH decode disabled +0xff600000/0xff200000 FWH decode disabled +0xff500000/0xff100000 FWH decode disabled +0xff400000/0xff000000 FWH decode disabled +Maximum FWH chip size: 0x400000 bytes +SPI Read Configuration: prefetching disabled, caching enabled, +BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled +SPIBAR = 0xb7727000 + 0x3800 +0x04: 0xe008 (HSFS) +HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 +Warning: SPI Configuration Lockdown activated. +Reading OPCODES... done +0x06: 0x3f04 (HSFC) +HSFC: FGO=0, FCYCLE=2, FDBC=63, SME=0 +0x50: 0x00001a1b (FRAP) +BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b +0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. +0x58: 0x03ff0200 FREG1: BIOS region (0x00200000-0x003fffff) is read-write. +0x5C: 0x01f50001 FREG2: Warning: Management Engine region (0x00001000-0x001f5fff) is locked. +0x60: 0x01f701f6 FREG3: Gigabit Ethernet region (0x001f6000-0x001f7fff) is read-write. +0x64: 0x01ff01f8 FREG4: Platform Data region (0x001f8000-0x001fffff) is read-write. +Not all flash regions are freely accessible by flashrom. This is most likely +due to an active ME. Please see http://flashrom.org/ME for details. +0x74: 0x9fff03e0 PR0: Warning: 0x003e0000-0x01ffffff is read-only. +0x84: 0x81ff81f8 PR4: Warning: 0x001f8000-0x001fffff is locked. +Writes have been disabled for safety reasons. You can enforce write +support with the ich_spi_force programmer option, but you will most likely +harm your hardware! If you force flashrom you will get no support if +something breaks. On a few mainboards it is possible to enable write +access by setting a jumper (see its documentation or the board itself). +0x90: 0x04 (SSFS) +SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 +0x91: 0x004240 (SSFC) +SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=2, SME=0, SCF=0 +0x94: 0x5006 (PREOP) +0x96: 0x143b (OPTYPE) +0x98: 0x05200302 (OPMENU) +0x9C: 0x0601209f (OPMENU+4) +0xA0: 0x00000000 (BBAR) +0xC4: 0x00002005 (LVSCC) +LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 +0xC8: 0x00002005 (UVSCC) +UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 +0xD0: 0x00000000 (FPB) +OK. +The following protocols are supported: FWH, SPI. +Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 +Found Macronix flash chip "MX25L3205D/MX25L3208D" (4096 kB, SPI) mapped at physical address 0xffc00000. +Chip status register is 0x00. +Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set +Chip status register: Bit 6 is not set +Chip status register: Block Protect 3 (BP3) is not set +Chip status register: Block Protect 2 (BP2) is not set +Chip status register: Block Protect 1 (BP1) is not set +Chip status register: Block Protect 0 (BP0) is not set +Chip status register: Write Enable Latch (WEL) is not set +Chip status register: Write In Progress (WIP/BUSY) is not set +This chip may contain one-time programmable memory. flashrom cannot read +and may never be able to write it, hence it may not be able to completely +clone the contents of this chip (see man page for details). +No operations were specified. +Restoring MMIO space at 0xb772a8a0 +Restoring PCI config space for 00:1f:0 reg 0xdc diff --git a/i18n/fr_FR/docs/future/dumps/t500log/flashrom_read.log b/i18n/fr_FR/docs/future/dumps/t500log/flashrom_read.log new file mode 100644 index 00000000..b3e3d6a2 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/t500log/flashrom_read.log @@ -0,0 +1,123 @@ +flashrom v0.9.8-r1889 on Linux 3.13.0-39-lowlatency (i686) +flashrom is free software, get the source code at http://www.flashrom.org + +flashrom was built with libpci 3.2.1, GCC 4.8.2, little endian +Command line (7 args): flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin -c MX25L3205D/MX25L3208D +Calibrating delay loop... OS timer resolution is 1 usecs, 790M loops per second, 10 myus = 26 us, 100 myus = 100 us, 1000 myus = 1003 us, 10000 myus = 10018 us, 4 myus = 5 us, OK. +Initializing internal programmer +No coreboot table found. +Using Internal DMI decoder. +DMI string chassis-type: "Notebook" +Laptop detected via DMI. +DMI string system-manufacturer: "LENOVO" +DMI string system-product-name: "224397G" +DMI string system-version: "ThinkPad T500" +DMI string baseboard-manufacturer: "LENOVO" +DMI string baseboard-product-name: "224397G" +DMI string baseboard-version: "Not Available" +======================================================================== +WARNING! You seem to be running flashrom on an unsupported laptop. +Laptops, notebooks and netbooks are difficult to support and we +recommend to use the vendor flashing utility. The embedded controller +(EC) in these machines often interacts badly with flashing. +See the manpage and http://www.flashrom.org/Laptops for details. + +If flash is shared with the EC, erase is guaranteed to brick your laptop +and write may brick your laptop. +Read and probe may irritate your EC and cause fan failure, backlight +failure and sudden poweroff. +You have been warned. +======================================================================== +Proceeding anyway because user forced us to. +Found chipset "Intel ICH9M" with PCI ID 8086:2919. +Enabling flash write... Root Complex Register Block address = 0xfed1c000 +GCS = 0x380461: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x1 (SPI) +Top Swap: not enabled +0xfff80000/0xffb80000 FWH IDSEL: 0x0 +0xfff00000/0xffb00000 FWH IDSEL: 0x0 +0xffe80000/0xffa80000 FWH IDSEL: 0x0 +0xffe00000/0xffa00000 FWH IDSEL: 0x0 +0xffd80000/0xff980000 FWH IDSEL: 0x0 +0xffd00000/0xff900000 FWH IDSEL: 0x0 +0xffc80000/0xff880000 FWH IDSEL: 0x0 +0xffc00000/0xff800000 FWH IDSEL: 0x0 +0xff700000/0xff300000 FWH IDSEL: 0x4 +0xff600000/0xff200000 FWH IDSEL: 0x5 +0xff500000/0xff100000 FWH IDSEL: 0x6 +0xff400000/0xff000000 FWH IDSEL: 0x7 +0xfff80000/0xffb80000 FWH decode enabled +0xfff00000/0xffb00000 FWH decode enabled +0xffe80000/0xffa80000 FWH decode enabled +0xffe00000/0xffa00000 FWH decode enabled +0xffd80000/0xff980000 FWH decode enabled +0xffd00000/0xff900000 FWH decode enabled +0xffc80000/0xff880000 FWH decode enabled +0xffc00000/0xff800000 FWH decode enabled +0xff700000/0xff300000 FWH decode disabled +0xff600000/0xff200000 FWH decode disabled +0xff500000/0xff100000 FWH decode disabled +0xff400000/0xff000000 FWH decode disabled +Maximum FWH chip size: 0x400000 bytes +SPI Read Configuration: prefetching disabled, caching enabled, +BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled +SPIBAR = 0xb7714000 + 0x3800 +0x04: 0xe008 (HSFS) +HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 +Warning: SPI Configuration Lockdown activated. +Reading OPCODES... done +0x06: 0x3f04 (HSFC) +HSFC: FGO=0, FCYCLE=2, FDBC=63, SME=0 +0x50: 0x00001a1b (FRAP) +BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b +0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. +0x58: 0x03ff0200 FREG1: BIOS region (0x00200000-0x003fffff) is read-write. +0x5C: 0x01f50001 FREG2: Warning: Management Engine region (0x00001000-0x001f5fff) is locked. +0x60: 0x01f701f6 FREG3: Gigabit Ethernet region (0x001f6000-0x001f7fff) is read-write. +0x64: 0x01ff01f8 FREG4: Platform Data region (0x001f8000-0x001fffff) is read-write. +Not all flash regions are freely accessible by flashrom. This is most likely +due to an active ME. Please see http://flashrom.org/ME for details. +0x74: 0x9fff03e0 PR0: Warning: 0x003e0000-0x01ffffff is read-only. +0x84: 0x81ff81f8 PR4: Warning: 0x001f8000-0x001fffff is locked. +Writes have been disabled for safety reasons. You can enforce write +support with the ich_spi_force programmer option, but you will most likely +harm your hardware! If you force flashrom you will get no support if +something breaks. On a few mainboards it is possible to enable write +access by setting a jumper (see its documentation or the board itself). +0x90: 0x04 (SSFS) +SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 +0x91: 0x004130 (SSFC) +SSFC: SCGO=0, ACS=0, SPOP=0, COP=3, DBC=1, SME=0, SCF=0 +0x94: 0x5006 (PREOP) +0x96: 0x143b (OPTYPE) +0x98: 0x05200302 (OPMENU) +0x9C: 0x0601209f (OPMENU+4) +0xA0: 0x00000000 (BBAR) +0xC4: 0x00002005 (LVSCC) +LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 +0xC8: 0x00002005 (UVSCC) +UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 +0xD0: 0x00000000 (FPB) +OK. +The following protocols are supported: FWH, SPI. +Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 +Found Macronix flash chip "MX25L3205D/MX25L3208D" (4096 kB, SPI) mapped at physical address 0xffc00000. +Chip status register is 0x00. +Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set +Chip status register: Bit 6 is not set +Chip status register: Block Protect 3 (BP3) is not set +Chip status register: Block Protect 2 (BP2) is not set +Chip status register: Block Protect 1 (BP1) is not set +Chip status register: Block Protect 0 (BP0) is not set +Chip status register: Write Enable Latch (WEL) is not set +Chip status register: Write In Progress (WIP/BUSY) is not set +This chip may contain one-time programmable memory. flashrom cannot read +and may never be able to write it, hence it may not be able to completely +clone the contents of this chip (see man page for details). +Reading flash... Transaction error! +SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 +SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 +Running OPCODE 0x03 failed at address 0x001000 (payload length was 64). +Read operation failed! +FAILED. +Restoring MMIO space at 0xb77178a0 +Restoring PCI config space for 00:1f:0 reg 0xdc diff --git a/i18n/fr_FR/docs/future/dumps/t500log/flashrom_write.log b/i18n/fr_FR/docs/future/dumps/t500log/flashrom_write.log new file mode 100644 index 00000000..d966ecb4 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/t500log/flashrom_write.log @@ -0,0 +1,119 @@ +flashrom v0.9.8-r1889 on Linux 3.13.0-39-lowlatency (i686) +flashrom is free software, get the source code at http://www.flashrom.org + +flashrom was built with libpci 3.2.1, GCC 4.8.2, little endian +Command line (7 args): flashrom -V -p internal:laptop=force_I_want_a_brick -w ../t500recipe.rom -c MX25L3205D/MX25L3208D +Calibrating delay loop... OS timer resolution is 1 usecs, 789M loops per second, 10 myus = 11 us, 100 myus = 100 us, 1000 myus = 1013 us, 10000 myus = 10017 us, 4 myus = 6 us, OK. +Initializing internal programmer +No coreboot table found. +Using Internal DMI decoder. +DMI string chassis-type: "Notebook" +Laptop detected via DMI. +DMI string system-manufacturer: "LENOVO" +DMI string system-product-name: "224397G" +DMI string system-version: "ThinkPad T500" +DMI string baseboard-manufacturer: "LENOVO" +DMI string baseboard-product-name: "224397G" +DMI string baseboard-version: "Not Available" +======================================================================== +WARNING! You seem to be running flashrom on an unsupported laptop. +Laptops, notebooks and netbooks are difficult to support and we +recommend to use the vendor flashing utility. The embedded controller +(EC) in these machines often interacts badly with flashing. +See the manpage and http://www.flashrom.org/Laptops for details. + +If flash is shared with the EC, erase is guaranteed to brick your laptop +and write may brick your laptop. +Read and probe may irritate your EC and cause fan failure, backlight +failure and sudden poweroff. +You have been warned. +======================================================================== +Proceeding anyway because user forced us to. +Found chipset "Intel ICH9M" with PCI ID 8086:2919. +Enabling flash write... Root Complex Register Block address = 0xfed1c000 +GCS = 0x380461: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x1 (SPI) +Top Swap: not enabled +0xfff80000/0xffb80000 FWH IDSEL: 0x0 +0xfff00000/0xffb00000 FWH IDSEL: 0x0 +0xffe80000/0xffa80000 FWH IDSEL: 0x0 +0xffe00000/0xffa00000 FWH IDSEL: 0x0 +0xffd80000/0xff980000 FWH IDSEL: 0x0 +0xffd00000/0xff900000 FWH IDSEL: 0x0 +0xffc80000/0xff880000 FWH IDSEL: 0x0 +0xffc00000/0xff800000 FWH IDSEL: 0x0 +0xff700000/0xff300000 FWH IDSEL: 0x4 +0xff600000/0xff200000 FWH IDSEL: 0x5 +0xff500000/0xff100000 FWH IDSEL: 0x6 +0xff400000/0xff000000 FWH IDSEL: 0x7 +0xfff80000/0xffb80000 FWH decode enabled +0xfff00000/0xffb00000 FWH decode enabled +0xffe80000/0xffa80000 FWH decode enabled +0xffe00000/0xffa00000 FWH decode enabled +0xffd80000/0xff980000 FWH decode enabled +0xffd00000/0xff900000 FWH decode enabled +0xffc80000/0xff880000 FWH decode enabled +0xffc00000/0xff800000 FWH decode enabled +0xff700000/0xff300000 FWH decode disabled +0xff600000/0xff200000 FWH decode disabled +0xff500000/0xff100000 FWH decode disabled +0xff400000/0xff000000 FWH decode disabled +Maximum FWH chip size: 0x400000 bytes +SPI Read Configuration: prefetching disabled, caching enabled, +BIOS_CNTL = 0x01: BIOS Lock Enable: disabled, BIOS Write Enable: enabled +SPIBAR = 0xb76e8000 + 0x3800 +0x04: 0xe008 (HSFS) +HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 +Warning: SPI Configuration Lockdown activated. +Reading OPCODES... done +0x06: 0x3f04 (HSFC) +HSFC: FGO=0, FCYCLE=2, FDBC=63, SME=0 +0x50: 0x00001a1b (FRAP) +BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b +0x54: 0x00000000 FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. +0x58: 0x03ff0200 FREG1: BIOS region (0x00200000-0x003fffff) is read-write. +0x5C: 0x01f50001 FREG2: Warning: Management Engine region (0x00001000-0x001f5fff) is locked. +0x60: 0x01f701f6 FREG3: Gigabit Ethernet region (0x001f6000-0x001f7fff) is read-write. +0x64: 0x01ff01f8 FREG4: Platform Data region (0x001f8000-0x001fffff) is read-write. +Not all flash regions are freely accessible by flashrom. This is most likely +due to an active ME. Please see http://flashrom.org/ME for details. +0x74: 0x9fff03e0 PR0: Warning: 0x003e0000-0x01ffffff is read-only. +0x84: 0x81ff81f8 PR4: Warning: 0x001f8000-0x001fffff is locked. +Writes have been disabled for safety reasons. You can enforce write +support with the ich_spi_force programmer option, but you will most likely +harm your hardware! If you force flashrom you will get no support if +something breaks. On a few mainboards it is possible to enable write +access by setting a jumper (see its documentation or the board itself). +0x90: 0x04 (SSFS) +SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 +0x91: 0x000000 (SSFC) +SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 +0x94: 0x5006 (PREOP) +0x96: 0x143b (OPTYPE) +0x98: 0x05200302 (OPMENU) +0x9C: 0x0601209f (OPMENU+4) +0xA0: 0x00000000 (BBAR) +0xC4: 0x00002005 (LVSCC) +LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 +0xC8: 0x00002005 (UVSCC) +UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20 +0xD0: 0x00000000 (FPB) +OK. +The following protocols are supported: FWH, SPI. +Probing for Macronix MX25L3205D/MX25L3208D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2016 +Found Macronix flash chip "MX25L3205D/MX25L3208D" (4096 kB, SPI) mapped at physical address 0xffc00000. +Chip status register is 0x00. +Chip status register: Status Register Write Disable (SRWD, SRP, ...) is not set +Chip status register: Bit 6 is not set +Chip status register: Block Protect 3 (BP3) is not set +Chip status register: Block Protect 2 (BP2) is not set +Chip status register: Block Protect 1 (BP1) is not set +Chip status register: Block Protect 0 (BP0) is not set +Chip status register: Write Enable Latch (WEL) is not set +Chip status register: Write In Progress (WIP/BUSY) is not set +This chip may contain one-time programmable memory. flashrom cannot read +and may never be able to write it, hence it may not be able to completely +clone the contents of this chip (see man page for details). +Write/erase is not working yet on your programmer in its current configuration. +Aborting. +Restoring MMIO space at 0xb76eb8a0 +Restoring PCI config space for 00:1f:0 reg 0xdc diff --git a/i18n/fr_FR/docs/future/dumps/t500log/inteltool.log b/i18n/fr_FR/docs/future/dumps/t500log/inteltool.log new file mode 100644 index 00000000..9529ab53 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/t500log/inteltool.log @@ -0,0 +1,3373 @@ +CPU: ID 0x1067a, Processor Type 0x0, Family 0x6, Model 0x17, Stepping 0xa +Northbridge: 8086:2a40 (GL40/GS40/GM45/GS45/PM45) +Southbridge: 8086:2919 (ICH9M) + +============= GPIOS ============= + +GPIOBASE = 0x1180 (IO) + +gpiobase+0x0000: 0x197e23fe (GPIO_USE_SEL) +gpiobase+0x0004: 0xe0a26dfe (GP_IO_SEL) +gpiobase+0x0008: 0x00000000 (RESERVED) +gpiobase+0x000c: 0xe3feef3b (GP_LVL) +gpiobase+0x0010: 0x00000000 (RESERVED) +gpiobase+0x0014: 0x00000000 (RESERVED) +gpiobase+0x0018: 0x00000000 (GPO_BLINK) +gpiobase+0x001c: 0x00000000 (GP_SER_BLINK) +gpiobase+0x0020: 0x00080000 (GP_SB_CMDSTS) +gpiobase+0x0024: 0x00000000 (GP_SB_DATA) +gpiobase+0x0028: 0x00000000 (RESERVED) +gpiobase+0x002c: 0x00000102 (GPI_INV) +gpiobase+0x0030: 0x030306f6 (GPIO_USE_SEL2) +gpiobase+0x0034: 0x1f55f9f1 (GP_IO_SEL2) +gpiobase+0x0038: 0x1dfffba3 (GP_LVL2) +gpiobase+0x003c: 0x00000000 (RESERVED) + + + +============= RCBA ============== + +RCBA = 0xfed1c000 (MEM) + +0x0000: 0x10010002 +0x0004: 0x00000801 +0x0008: 0x00000001 +0x0010: 0x00000001 +0x0014: 0x80000001 +0x001c: 0x03128011 +0x0020: 0x81080080 +0x0030: 0x0000000f +0x0034: 0x000f0000 +0x003c: 0x000000f0 +0x0040: 0x0f000000 +0x0048: 0x0000f000 +0x0050: 0x0000000f +0x0054: 0x000f0000 +0x005c: 0x000000f0 +0x0060: 0x0f000000 +0x0068: 0x0000f000 +0x0088: 0x00109000 +0x0090: 0x00002000 +0x0094: 0x00002000 +0x0100: 0x1a010005 +0x0104: 0x00020802 +0x0110: 0x01010001 +0x0118: 0xfed18000 +0x0120: 0x01020003 +0x0128: 0x000e0000 +0x0130: 0x02020002 +0x0138: 0x000e1000 +0x0140: 0x03020002 +0x0148: 0x000e2000 +0x0150: 0x04020003 +0x0158: 0x000e3000 +0x0160: 0x0f020003 +0x0168: 0x000d8000 +0x0170: 0x05020003 +0x0178: 0x000e4000 +0x0180: 0x06020002 +0x0188: 0x000e5000 +0x01a0: 0x00010006 +0x01a4: 0x00012c41 +0x01a8: 0x00410003 +0x01f0: 0x00000001 +0x01f4: 0x86000040 +0x01fc: 0x0000060b +0x0200: 0x01102008 +0x0208: 0x04210044 +0x0210: 0x0000f710 +0x0220: 0x00000045 +0x0228: 0x04124aaa +0x0230: 0x00010000 +0x0234: 0x00000003 +0x0238: 0x00543210 +0x023c: 0x00000800 +0x0240: 0x000c0299 +0x0244: 0x001202b1 +0x0248: 0x002f04c7 +0x024c: 0x00bd0000 +0x0250: 0x00c30000 +0x0254: 0x008a0424 +0x0258: 0x008a0d8b +0x0260: 0x00cd0b03 +0x0268: 0x00030018 +0x0270: 0x00030000 +0x0274: 0x00040010 +0x0278: 0x001f00e2 +0x027c: 0x002300f2 +0x0280: 0x00c90000 +0x0284: 0x00cf0000 +0x0288: 0x00d306b6 +0x0f20: 0xb2b577cc +0x0f24: 0x000000c3 +0x0f28: 0x00180000 +0x0f2c: 0x001fffff +0x0f30: 0x0000ff8f +0x1d3c: 0x0000000b +0x1d48: 0x00030000 +0x1e10: 0x00020800 +0x1e80: 0x000c0801 +0x1e84: 0x000200f0 +0x2010: 0x00080401 +0x2014: 0x14000016 +0x2018: 0xbc4abcb5 +0x2020: 0x00c9605b +0x2024: 0x0b203040 +0x2028: 0x04c8ff00 +0x202c: 0x0f6c0f00 +0x2030: 0x00004454 +0x2034: 0xb2b577cc +0x2044: 0x000000c3 +0x204c: 0x001ff800 +0x2050: 0x00100fff +0x2054: 0x00000787 +0x2060: 0x81000000 +0x2080: 0x18206006 +0x2088: 0x00000260 +0x208c: 0x0006000c +0x2090: 0x31000000 +0x20a0: 0x18206006 +0x20a8: 0x00000260 +0x20ac: 0x0006000c +0x20b0: 0x07000000 +0x20c0: 0x18206006 +0x20c8: 0x00000260 +0x20cc: 0x0006000c +0x20d0: 0x0c000000 +0x20e0: 0x18206006 +0x20e8: 0x00000260 +0x20ec: 0x0006000c +0x20f0: 0x0a000000 +0x3100: 0x04341200 +0x3108: 0x40000321 +0x310c: 0x00014321 +0x3110: 0x00000002 +0x3114: 0x40000321 +0x3118: 0x00000001 +0x3140: 0x00003107 +0x3144: 0x76543210 +0x3148: 0x00000010 +0x314c: 0x00007654 +0x3150: 0x00000004 +0x31fc: 0x03000000 +0x3400: 0x0000001c +0x3404: 0x00000080 +0x3410: 0x00380461 +0x3418: 0x03260001 +0x341c: 0xbf4f001f +0x3430: 0x00000001 +0x3500: 0x0fff0fff +0x3504: 0x1b6db6db +0x3508: 0x0000001b +0x350c: 0x08000020 +0x3510: 0x09008fb8 +0x3528: 0x16003f80 +0x352c: 0x000bc008 +0x3530: 0x1800ff4f +0x3800: 0x03ff0200 +0x3804: 0x3f04e008 +0x3808: 0x0020efc0 +0x384c: 0xb2000000 +0x3850: 0x00001a1b +0x3858: 0x03ff0200 +0x385c: 0x01f50001 +0x3860: 0x01f701f6 +0x3864: 0x01ff01f8 +0x3874: 0x9fff03e0 +0x3884: 0x81ff81f8 +0x3890: 0x00400000 +0x3894: 0x143b5006 +0x3898: 0x05200302 +0x389c: 0x0601209f +0x38b0: 0x00000004 +0x38b4: 0x04040001 +0x38c0: 0x00000007 +0x38c4: 0x00002005 +0x38c8: 0x00002005 +0x3e00: 0xffffffff +0x3e04: 0xffffffff +0x3e08: 0xffffffff +0x3e0c: 0xffffffff +0x3e10: 0xffffffff +0x3e14: 0xffffffff +0x3e18: 0xffffffff +0x3e1c: 0xffffffff +0x3e20: 0xffffffff +0x3e24: 0xffffffff +0x3e28: 0xffffffff +0x3e2c: 0xffffffff +0x3e30: 0xffffffff +0x3e34: 0xffffffff +0x3e38: 0xffffffff +0x3e3c: 0xffffffff +0x3e40: 0xffffffff +0x3e44: 0xffffffff +0x3e48: 0xffffffff +0x3e4c: 0xffffffff +0x3e50: 0xffffffff +0x3e54: 0xffffffff +0x3e58: 0xffffffff +0x3e5c: 0xffffffff +0x3e60: 0xffffffff +0x3e64: 0xffffffff +0x3e68: 0xffffffff +0x3e6c: 0xffffffff +0x3e70: 0xffffffff +0x3e74: 0xffffffff +0x3e78: 0xffffffff +0x3e7c: 0xffffffff +0x3f00: 0x0000000b + + + +============= PMBASE ============ + +PMBASE = 0x1000 (IO) + +pmbase+0x0000: 0x0001 (PM1_STS) +pmbase+0x0002: 0x0120 (PM1_EN) +pmbase+0x0004: 0x00001c03 (PM1_CNT) +pmbase+0x0008: 0x0033172e (PM1_TMR) +pmbase+0x000c: 0x00000000 (RESERVED) +pmbase+0x0010: 0x00000080 (PROC_CNT) +pmbase+0x0019: 0x00 (RESERVED) +pmbase+0x001a: 0x0000 (RESERVED) +pmbase+0x001c: 0x20000000 (RESERVED) +pmbase+0x0020: 0x6c380000 (GPE0_STS) + 0x00000000 +pmbase+0x0028: 0x01020046 (GPE0_EN) + 0x00000000 +pmbase+0x0030: 0x00062033 (SMI_EN) +pmbase+0x0034: 0x00004900 (SMI_STS) +pmbase+0x0038: 0x0000 (ALT_GP_SMI_EN) +pmbase+0x003a: 0x6c3a (ALT_GP_SMI_STS) +pmbase+0x003c: 0x00 (UPRWC) +pmbase+0x003d: 0x0000 (RESERVED) +pmbase+0x003f: 0x00 (RESERVED) +pmbase+0x0040: 0x0000 (RESERVED) +pmbase+0x0042: 0x00 (GPE_CNTL) +pmbase+0x0043: 0x00 (RESERVED) +pmbase+0x0044: 0x12a0 (DEVACT_STS) +pmbase+0x0046: 0x0000 (RESERVED) +pmbase+0x0048: 0x00000000 (RESERVED) +pmbase+0x004c: 0x00000000 (RESERVED) +pmbase+0x0050: 0x00 (PM2_CNT (Mobile)) +pmbase+0x0051: 0x00 (RESERVED) +pmbase+0x0052: 0x0000 (RESERVED) +pmbase+0x0054: 0x0074541d (C3_RES (Mobile)) +pmbase+0x0058: 0x00000000 (C5_RES (Mobile)) +pmbase+0x005c: 0x00000000 (RESERVED) +pmbase+0x0060: 0x0004 (TCO_RLD) +pmbase+0x0062: 0x00 (TCO_DAT_IN) +pmbase+0x0063: 0x00 (TCO_DAT_OUT) +pmbase+0x0064: 0x0000 (TCO1_STS) +pmbase+0x0066: 0x0000 (TCO2_STS) +pmbase+0x0068: 0x0800 (TCO1_CNT) +pmbase+0x006a: 0x0008 (TCO2_CNT) +pmbase+0x006c: 0x0000 (TCO_MESSAGE) +pmbase+0x006e: 0x00 (TCO_WDCNT) +pmbase+0x006f: 0x00 (RESERVED) +pmbase+0x0070: 0x03 (SW_IRQ_GEN) +pmbase+0x0071: 0x00 (RESERVED) +pmbase+0x0072: 0x03ff (TCO_TMR) +pmbase+0x0074: 0x00000000 (RESERVED) +pmbase+0x0078: 0x00000000 (RESERVED) +pmbase+0x007c: 0x00000000 (RESERVED) + + + +============= MCHBAR ============ + +MCHBAR = 0xfed10000 (MEM) + +0x0034: 0x00000002 +0x0040: 0x00202200 +0x0044: 0xc6200032 +0x0048: 0x808002a8 +0x004c: 0x00100000 +0x0050: 0x00800001 +0x0054: 0x00800102 +0x0070: 0x12200009 +0x0074: 0x17000200 +0x0090: 0x00005054 +0x0094: 0x20210880 +0x00a4: 0x00d00000 +0x00b0: 0x00d00000 +0x00bc: 0x00d00000 +0x00d0: 0x00000002 +0x00f4: 0x01804000 +0x0200: 0x000f0002 +0x0204: 0x00000010 +0x0208: 0x00810060 +0x020c: 0x00180006 +0x0218: 0x86008400 +0x0220: 0x00210264 +0x0224: 0x00000300 +0x0228: 0x30000000 +0x0230: 0x34028000 +0x0234: 0x00000009 +0x0238: 0x04bdb600 +0x023c: 0x003db600 +0x0240: 0xa8000000 +0x0400: 0x000e0022 +0x0404: 0x00002202 +0x040c: 0x0f800100 +0x0410: 0x2186a000 +0x041c: 0x22222099 +0x0420: 0x0000002d +0x0424: 0x0000002d +0x0428: 0x00000050 +0x042c: 0x00000050 +0x04d0: 0x24a00012 +0x0518: 0x24250a0a +0x0530: 0x0a0a0005 +0x0680: 0x08100f0e +0x0684: 0x08080808 +0x0688: 0x09090808 +0x068c: 0x0d0c0b0a +0x0698: 0x100e0d0c +0x069c: 0x08081612 +0x06a0: 0x09090808 +0x06a4: 0x0b0b0a0a +0x06b0: 0x1d000055 +0x06b4: 0x0000001a +0x06c0: 0x03030303 +0x06c4: 0x04040404 +0x06c8: 0x03050505 +0x06cc: 0x03030303 +0x06d8: 0x03030303 +0x06dc: 0x04040403 +0x06e0: 0x05050504 +0x06e4: 0x03030505 +0x06f0: 0x25000066 +0x06f4: 0x00000022 +0x0700: 0x08080808 +0x0704: 0x09090909 +0x0708: 0x080a0a0a +0x070c: 0x08080808 +0x0718: 0x08080808 +0x071c: 0x09090909 +0x0720: 0x0a0a0a0a +0x0724: 0x08080a0a +0x0730: 0x25000066 +0x0734: 0x00000022 +0x073c: 0x80000000 +0x0740: 0x08080808 +0x0744: 0x09090909 +0x0748: 0x080a0a0a +0x074c: 0x08080808 +0x0758: 0x08080808 +0x075c: 0x09090909 +0x0760: 0x0a0a0a0a +0x0764: 0x08080a0a +0x0770: 0x25000066 +0x0774: 0x00000022 +0x077c: 0x80000000 +0x0780: 0x0a090909 +0x0784: 0x0c0b0b0a +0x0788: 0x060e0d0c +0x078c: 0x09080707 +0x0798: 0x0c0b0a0a +0x079c: 0x0c0c0c0c +0x07a0: 0x0e0d0d0c +0x07a4: 0x09090f0e +0x07b0: 0x25000066 +0x07b4: 0x00000022 +0x07c0: 0x0a090909 +0x07c4: 0x0c0b0b0a +0x07c8: 0x060e0d0c +0x07cc: 0x09080707 +0x07d8: 0x0c0b0a0a +0x07dc: 0x0c0c0c0c +0x07e0: 0x0e0d0d0c +0x07e4: 0x09090f0e +0x07f0: 0x25000066 +0x07f4: 0x00000022 +0x0840: 0x08100f0e +0x0844: 0x08080808 +0x0848: 0x09090808 +0x084c: 0x0d0c0b0a +0x0858: 0x100e0d0c +0x085c: 0x08081612 +0x0860: 0x09090808 +0x0864: 0x0b0b0a0a +0x0870: 0x1d000055 +0x0874: 0x0000001a +0x0880: 0x03030303 +0x0884: 0x04040404 +0x0888: 0x03050505 +0x088c: 0x03030303 +0x0898: 0x03030303 +0x089c: 0x04040403 +0x08a0: 0x05050504 +0x08a4: 0x03030505 +0x08b0: 0x25000066 +0x08b4: 0x00000022 +0x08c0: 0x00003735 +0x08c4: 0x00000807 +0x08c8: 0x00001f1f +0x0a00: 0x00200010 +0x0a04: 0x00200020 +0x0a08: 0x00008686 +0x0a28: 0xe0000000 +0x0a2c: 0x03300000 +0x0a34: 0x00200010 +0x0a38: 0x00200020 +0x0a3c: 0x00008686 +0x0a5c: 0x00000190 +0x0ac0: 0x0000010f +0x0ae4: 0x00001111 +0x0aec: 0x00000201 +0x0af0: 0xdf7e3d68 +0x0af4: 0x68cabaf6 +0x0af8: 0x32de4393 +0x0afc: 0xf5ec9fe1 +0x0b00: 0x01400182 +0x0b28: 0x0186a000 +0x0b2c: 0x15211521 +0x0b30: 0x0e0c0e0c +0x0b34: 0x0e0c1521 +0x0b38: 0x0e0c1501 +0x0b3c: 0x0c020807 +0x0b40: 0x04030201 +0x0b44: 0x08070605 +0x0b48: 0x110f0c09 +0x0b4c: 0x1a171513 +0x0b50: 0x2723201d +0x0b54: 0x312f2d2a +0x0b58: 0x3a383633 +0x0b5c: 0x3f3f3e3c +0x0b60: 0x04040302 +0x0b64: 0x08070605 +0x0b68: 0x120e0b09 +0x0b6c: 0x211d1815 +0x0b70: 0x2b292724 +0x0b74: 0x31302f2d +0x0b78: 0x39373533 +0x0b7c: 0x3f3d3b3a +0x0b84: 0x00084aa1 +0x0b88: 0x0045030e +0x0b8c: 0x00222222 +0x0b90: 0x00800080 +0x0b94: 0x162f252b +0x0b9c: 0x00000008 +0x0ba0: 0x00000008 +0x0ba4: 0x00000008 +0x0ba8: 0x00000008 +0x0bac: 0x162f162f +0x0bb0: 0x14000000 +0x0bbc: 0x0f000000 +0x0bc8: 0x00200000 +0x0bcc: 0x594b0000 +0x0bd0: 0x5a222200 +0x0bd4: 0x0024005a +0x0bd8: 0x0000000c +0x0be0: 0x1b6decf3 +0x0be4: 0x367b6db6 +0x0c00: 0x00644066 +0x0c04: 0x01010101 +0x0c08: 0x00008000 +0x0c14: 0x30950002 +0x0c34: 0x00008000 +0x0c38: 0x17771777 +0x0c48: 0x3f000000 +0x0c50: 0x01010101 +0x0c60: 0x80000000 +0x0c64: 0x00004080 +0x0e10: 0x003d0098 +0x0e14: 0x00000004 +0x0e50: 0x00f003c0 +0x0e54: 0x000f03c0 +0x0e58: 0x00ff03c0 +0x0e5c: 0x3c0f03c0 +0x0e60: 0x3c0003c0 +0x0e70: 0x000000b9 +0x0e74: 0x9c000000 +0x0e78: 0x0214a6d6 +0x0e7c: 0x00470a04 +0x0e80: 0xa0000510 +0x0e84: 0xb55f0931 +0x0e88: 0x8100077e +0x0e8c: 0x00002080 +0x0ea8: 0x00c80000 +0x0eac: 0x00002000 +0x0eb0: 0x00010000 +0x0ee8: 0x00a60000 +0x0f00: 0x00000900 +0x0f04: 0x00002e80 +0x0f08: 0x0000730f +0x0f0c: 0x000010a4 +0x0f10: 0x000000a2 +0x0f20: 0x20000000 +0x0f60: 0x01030419 +0x0f80: 0x80000000 +0x0fb0: 0x00000003 +0x0fb8: 0x00000003 +0x0fc0: 0x061f08fd +0x0ffc: 0x000007c0 +0x1000: 0x0093007f +0x1004: 0x00ff0000 +0x1008: 0x400000ff +0x100c: 0x00000040 +0x1010: 0x80000009 +0x101c: 0x00008098 +0x1040: 0x0001007f +0x1044: 0x00ff0000 +0x1048: 0x000000ff +0x1050: 0x80000000 +0x105c: 0x00008098 +0x1070: 0x00000001 +0x1080: 0x00000006 +0x1100: 0x00000300 +0x1110: 0x17cd17ac +0x1114: 0x179b178a +0x1118: 0x17891778 +0x111c: 0x17671756 +0x1120: 0x10111213 +0x1124: 0x14151617 +0x1128: 0x18191a1b +0x112c: 0x1c1d1e1f +0x1130: 0x00010203 +0x1134: 0x04050607 +0x1138: 0x08090a0b +0x113c: 0x0c0d0e0f +0x1190: 0x00000007 +0x119c: 0xa8000000 +0x11b8: 0x4000333c +0x11c0: 0x03030100 +0x11c4: 0x0a030a03 +0x11c8: 0x00000020 +0x11cc: 0x00000017 +0x1200: 0x00400020 +0x1204: 0x00400040 +0x1208: 0x00090033 +0x120c: 0x00000003 +0x1210: 0x48e18c61 +0x1214: 0x128088a5 +0x1218: 0x22283313 +0x121c: 0x32088304 +0x1220: 0x68ba6035 +0x1224: 0x83590a54 +0x1228: 0x066a6804 +0x122c: 0x00000002 +0x1230: 0x43000208 +0x1234: 0x910c1800 +0x1238: 0x0c001001 +0x1248: 0x20802025 +0x124c: 0x60a47687 +0x1250: 0x000006c4 +0x1254: 0x871a066d +0x1258: 0x40100401 +0x1260: 0x0000000b +0x1264: 0x00982022 +0x1268: 0x00000006 +0x1274: 0x80000000 +0x12a0: 0x0000000a +0x12a4: 0x00000020 +0x1300: 0x00400020 +0x1304: 0x00400040 +0x1308: 0x00090033 +0x130c: 0x00000003 +0x1310: 0x48e18c61 +0x1314: 0x128088a5 +0x1318: 0x22283313 +0x131c: 0x32088304 +0x1320: 0x68ba6035 +0x1324: 0x83590a54 +0x1328: 0x066a6804 +0x132c: 0x00000002 +0x1330: 0x43000208 +0x1334: 0x910c1800 +0x1338: 0x0c001001 +0x1348: 0x20802025 +0x134c: 0x60a47687 +0x1350: 0x000006c4 +0x1354: 0x871a066d +0x1358: 0x40100401 +0x1360: 0x0000000b +0x1364: 0x00982022 +0x1368: 0x00000006 +0x1374: 0x80000000 +0x13a0: 0x0000000a +0x13a4: 0x00000020 +0x1400: 0x00113300 +0x1408: 0xf3ff8000 +0x140c: 0x80010880 +0x1410: 0x6000200e +0x1414: 0x24049800 +0x1420: 0x2222aa22 +0x1428: 0x00555801 +0x142c: 0x05330407 +0x1430: 0x02000300 +0x1434: 0x80000243 +0x1440: 0x00000044 +0x1444: 0x02000000 +0x1450: 0x0000000a +0x1470: 0x8628230f +0x1474: 0x5228b409 +0x1478: 0x94244108 +0x147c: 0xa6255008 +0x1490: 0x00e70067 +0x1494: 0x000d8000 +0x14a0: 0x80130002 +0x14a4: 0x25930002 +0x14a8: 0x83810000 +0x14ac: 0x43110000 +0x14b0: 0x0e461000 +0x14b4: 0x0e401800 +0x14b8: 0x0e451000 +0x14bc: 0x0e351800 +0x14c0: 0x0e420000 +0x14c4: 0x0e450800 +0x14c8: 0x0e460000 +0x14cc: 0x8e510800 +0x14e0: 0x55500000 +0x14f0: 0x00000600 +0x1570: 0x00840008 +0x1574: 0x00840008 +0x1578: 0x00840008 +0x157c: 0x008b0008 +0x1590: 0x00e70067 +0x1594: 0x000d8000 +0x15a0: 0x82130002 +0x15a4: 0x02930002 +0x15a8: 0x62810000 +0x15ac: 0x33110000 +0x15b0: 0x8e421000 +0x15b4: 0x0e431800 +0x15b8: 0x0e441000 +0x15bc: 0x8e421800 +0x15c0: 0x0e320000 +0x15c4: 0x8e410800 +0x15c8: 0x8e450000 +0x15cc: 0x0e450800 +0x15e0: 0x55500000 +0x15f0: 0x00000600 +0x16cc: 0x000000ff +0x16d4: 0x00000400 + + + +============= EPBAR ============= + +EPBAR = 0xfed19000 (MEM) + +0x0000: 0x04010002 +0x0004: 0x00000401 +0x0008: 0x00000001 +0x0010: 0x00000001 +0x0014: 0x80000001 +0x001c: 0x100a8010 +0x0020: 0x81080080 +0x0028: 0x0a0a0a0a +0x002c: 0x0000001a +0x0038: 0x01380138 +0x003c: 0x01380138 +0x0040: 0x00010005 +0x0044: 0x00010201 +0x0050: 0x01010001 +0x0058: 0xfed18000 +0x0060: 0x02000002 +0x0068: 0x00008000 +0x0100: 0x55555555 +0x0104: 0x55555555 +0x0108: 0x55555555 +0x010c: 0x55555555 +0x0110: 0x55555555 +0x0114: 0x55555555 +0x0118: 0x55555555 +0x011c: 0x00005555 + + + +============= DMIBAR ============ + +DMIBAR = 0xfed18000 (MEM) + +0x0000: 0x04010002 +0x0004: 0x00000001 +0x0008: 0x00000001 +0x0010: 0x00000001 +0x0014: 0x80000001 +0x001c: 0x00008001 +0x0020: 0x81000080 +0x0028: 0x00000001 +0x002c: 0x86000040 +0x0040: 0x08010005 +0x0044: 0x01010202 +0x0050: 0x00020001 +0x0058: 0xfed1c000 +0x0060: 0x00010001 +0x0068: 0xfed19000 +0x0080: 0x00010006 +0x0084: 0x00012c41 +0x0088: 0x00410003 +0x00f0: 0x03010000 +0x00f4: 0x00000005 +0x00fc: 0x00000013 +0x01cc: 0x00060010 +0x01d4: 0x00002000 +0x0200: 0x08006f24 +0x0204: 0x0000b13f +0x0208: 0x00007cb0 +0x0210: 0x00000100 +0x0214: 0x0008000f +0x0218: 0x0ee1026b +0x021c: 0x026c026c +0x0224: 0x00030007 +0x0230: 0x1400000c +0x0234: 0xbc4abcb5 +0x0300: 0x002f04c1 +0x0304: 0x003104c9 +0x0308: 0x00060018 +0x030c: 0x00690423 +0x0310: 0x006a0424 +0x0314: 0x00060000 +0x0318: 0x00c50ae3 +0x031c: 0x00cd0b03 +0x0324: 0x00030018 +0x0328: 0x00030000 +0x0334: 0x00040010 +0x0338: 0x00060000 +0x0e00: 0x000001fe +0x0e08: 0x000000c0 +0x0e0c: 0x000000bd +0x0e10: 0x00000010 +0x0e18: 0x00000010 +0x0e1c: 0x00000001 +0x0e20: 0x00000010 +0x0e24: 0x0000000e +0x0e28: 0x3a588887 +0x0e2c: 0x88d07333 +0x0e30: 0x00009000 +0x0f00: 0x0000033c +0x0f04: 0x07050880 +0x0f08: 0x00100052 +0x0f10: 0x00010012 +0x0f14: 0x30400000 +0x0f20: 0x3c000757 +0x0f30: 0x0e3b0808 +0x0f34: 0x000a0000 +0x0f44: 0x07050880 +0x0f48: 0x00100052 +0x0f50: 0x00010012 +0x0f54: 0x30400000 +0x0f60: 0x3c000757 +0x0f64: 0x00000100 +0x0f70: 0x0e370808 +0x0f74: 0x00020000 +0x0f80: 0x0000033c +0x0f84: 0x07050880 +0x0f88: 0x00100052 +0x0f90: 0x00010012 +0x0f94: 0x30400000 +0x0fa0: 0x3c000757 +0x0fa4: 0x00000100 +0x0fb0: 0x0e340808 +0x0fb4: 0x000a0000 +0x0fc4: 0x07050880 +0x0fc8: 0x00100052 +0x0fd0: 0x00010012 +0x0fd4: 0x30000000 +0x0fe0: 0x3c000757 +0x0fe4: 0x00000100 +0x0ff0: 0x0e380408 +0x0ff4: 0x000a0000 + + +========= PCIEXBAR ======== + +PCIEXBAR: 0xe0000000 + +PCIe 00:00.0 extended config space: +0000: 86 80 40 2a 06 01 90 20 07 00 00 06 00 00 00 00 +0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0020: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 e0 20 +0030: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +0040: 01 90 d1 fe 00 00 00 00 01 00 d1 fe 00 00 00 00 +0050: 00 00 50 03 59 00 00 00 00 00 00 00 00 00 00 00 +0060: 01 00 00 e0 00 00 00 00 01 80 d1 fe 00 00 00 00 +0070: 01 00 40 c0 00 00 00 00 01 10 00 00 00 00 00 00 +0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0090: 10 11 11 01 30 11 11 00 40 00 4e 00 00 1a 3b 00 +00a0: 20 00 c0 13 00 00 00 00 00 00 00 00 00 00 00 00 +00b0: 00 c0 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0af0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0b00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0b10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0b20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0b30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0b40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0b50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0b60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0b70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0b80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0b90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0ba0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0bb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0bc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0bd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0be0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0bf0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0c00: 00 00 00 00 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00 00 00 00 00 00 +0e50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0e60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0e70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0e80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0e90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0ea0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0eb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +PCIe 00:1f.2 extended config space: +0000: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0010: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0020: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0030: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0040: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0070: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0080: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0090: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +00a0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +00b0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +00c0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +00d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0100: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0110: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0120: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0130: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0140: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0170: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0180: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0190: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +01a0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +01b0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +01c0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +01d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +01e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +01f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0200: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0210: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0220: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0230: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0240: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0250: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0270: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0280: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0290: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +02a0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +02b0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +02c0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +02d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +02e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +02f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0300: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0310: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0320: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0330: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0340: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0350: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0370: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0380: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0390: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +03a0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +03b0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +03c0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +03d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +03e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +03f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0400: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0410: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0420: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0430: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0440: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0450: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0460: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0470: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0480: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0490: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +04a0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +04b0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +04c0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +04d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +04e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +04f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0500: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0510: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0520: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0530: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0540: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0550: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0560: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0570: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0580: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0590: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +05a0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +05b0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +05c0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +05d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +05e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +05f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0600: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0610: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0620: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0630: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0640: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0650: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0660: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0670: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0680: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0690: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +06a0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +06b0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +06c0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +06d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +06e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +06f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0700: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0710: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0720: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0730: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0740: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0750: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0760: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0770: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0780: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0790: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +07a0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +07b0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +07c0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +07d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +07e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +07f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0800: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0810: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0820: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0830: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0840: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0850: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0860: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0870: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0880: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0890: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +08a0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +08b0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +08c0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +08d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +08e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +08f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0900: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0910: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0920: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0930: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0940: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0950: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0960: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0970: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0980: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0990: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +09a0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +09b0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +09c0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +09d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +09e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +09f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0a00: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0a10: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0a20: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0a30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0a40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0a50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0a60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0a70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0a80: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0a90: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +0aa0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +0ab0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +0ac0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +0ad0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0ae0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0af0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0b00: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0b10: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0b20: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0b30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0b40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0b50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0b60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0b70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0b80: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0b90: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +0ba0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +0bb0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +0bc0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +0bd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0be0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0bf0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0c00: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0c10: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0c20: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0c30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0c40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0c50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0c60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0c70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0c80: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0c90: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +0ca0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +0cb0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +0cc0: 00 00 00 00 05 00 00 Error: Dumping AMBs on this MCH is not (yet) supported. +00 00 00 00 00 00 00 00 00 +0cd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0ce0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0cf0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0d00: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0d10: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0d20: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0d30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0d40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0d50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0d60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0d70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0d80: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0d90: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +0da0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +0db0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +0dc0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +0dd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0de0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0df0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0e00: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0e10: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0e20: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0e30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0e40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0e50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0e60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0e70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0e80: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0e90: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +0ea0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +0eb0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +0ec0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +0ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0ef0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 +0f00: 86 80 29 29 07 04 b0 02 03 01 06 01 00 00 00 00 +0f10: 19 18 00 00 0d 18 00 00 11 18 00 00 09 18 00 00 +0f20: 01 1c 00 00 00 50 62 fc 00 00 00 00 aa 17 f8 20 +0f30: 00 00 00 00 80 00 00 00 00 00 00 00 0b 02 00 00 +0f40: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 +0f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0f70: 01 a8 03 40 08 00 00 00 00 00 00 00 00 00 00 00 +0f80: 05 70 09 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +0f90: 60 0c 03 83 93 01 00 4c 00 00 00 00 0c 00 00 00 +0fa0: 00 00 00 00 00 00 00 00 12 b0 10 00 48 00 00 00 +0fb0: 13 00 06 03 00 00 00 00 00 00 00 00 00 00 00 00 +0fc0: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 +0fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +0ff0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 + + +Error: Dumping MSRs on this CPU (0x010670) is not (yet) supported. + + + +============= AMBs ============ + + +============= SPI / BIOS CNTL ============= + +Error: Dumping SPI on this southbridge is not (yet) supported. diff --git a/i18n/fr_FR/docs/future/dumps/t500log/lspci.log b/i18n/fr_FR/docs/future/dumps/t500log/lspci.log new file mode 100644 index 00000000..7b3d310a --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/t500log/lspci.log @@ -0,0 +1,2120 @@ +00:00.0 Host bridge [0600]: Intel Corporation Mobile 4 Series Chipset Memory Controller Hub [8086:2a40] (rev 07) + Subsystem: Lenovo Device [17aa:20e0] + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- + Kernel driver in use: agpgart-intel +00: 86 80 40 2a 06 01 90 20 07 00 00 06 00 00 00 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 e0 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 90 d1 fe 00 00 00 00 01 00 d1 fe 00 00 00 00 +50: 00 00 50 03 59 00 00 00 00 00 00 00 00 00 00 00 +60: 01 00 00 e0 00 00 00 00 01 80 d1 fe 00 00 00 00 +70: 01 00 40 c0 00 00 00 00 01 10 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:02.0 VGA compatible controller [0300]: Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a42] (rev 07) (prog-if 00 [VGA controller]) + Subsystem: Lenovo Device [17aa:20e4] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- [disabled] + Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 4142 + Capabilities: [d0] Power Management version 3 + Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Kernel driver in use: i915 +00: 86 80 42 2a 07 04 90 00 07 00 00 03 00 00 80 00 +10: 04 00 00 fc 00 00 00 00 0c 00 00 d0 00 00 00 00 +20: 01 18 00 00 00 00 00 00 00 00 00 00 aa 17 e4 20 +30: 00 00 00 00 90 00 00 00 00 00 00 00 0b 01 00 00 +40: 00 00 00 00 48 00 00 00 09 00 0a 11 88 64 00 1c +50: 01 00 50 03 19 00 00 00 00 00 00 00 00 00 00 be +60: 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 05 d0 01 00 0c 30 e0 fe 42 41 00 00 00 00 00 00 +a0: 00 00 00 00 09 00 06 20 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 40 01 00 00 +d0: 01 00 23 00 00 00 00 00 00 00 00 00 34 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 80 00 1a 41 20 00 00 +f0: 0d 1c 34 07 ff 00 00 00 a0 0f 07 00 fa b0 b6 bd + +00:02.1 Display controller [0380]: Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a43] (rev 07) + Subsystem: Lenovo Device [17aa:20e4] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #0, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- + Changed: MRL- PresDet- LinkState- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41c1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=01 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c000 + Kernel driver in use: pcieport +00: 86 80 40 29 07 05 10 00 03 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 02 02 00 80 80 00 00 +20: 00 c0 10 c0 21 c0 31 c0 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 04 00 +40: 10 80 41 01 00 80 00 00 00 00 10 00 11 4c 11 01 +50: 00 00 01 10 e0 a0 00 00 38 00 00 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 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+f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:1c.3 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 4 [8086:2946] (rev 03) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #3, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- + Changed: MRL- PresDet- LinkState- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41d1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=04 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c000 + Kernel driver in use: pcieport +00: 86 80 46 29 07 05 10 00 03 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 05 0c 00 20 20 00 00 +20: 00 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00 +f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:1c.4 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 5 [8086:2948] (rev 03) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #5, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #4, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- + Changed: MRL- PresDet- LinkState- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41e1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=05 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c000 + Kernel driver in use: pcieport +00: 86 80 48 29 07 05 10 00 03 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 0d 14 00 30 30 00 00 +20: 00 fa f0 fb 11 f4 11 f4 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 04 00 +40: 10 80 41 01 00 80 00 00 00 00 10 00 11 4c 11 05 +50: 03 00 01 10 e0 a0 20 00 38 00 00 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe e1 41 00 00 00 00 00 00 +90: 0d a0 00 00 aa 17 f3 20 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 11 08 00 00 00 00 +e0: 00 0f c7 00 06 07 08 00 33 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:1d.0 USB controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934] (rev 03) (prog-if 00 [UHCI]) + Subsystem: Lenovo Device [17aa:20f0] + Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [50] Subsystem: Lenovo Device [17aa:20f4] +00: 86 80 48 24 07 01 10 00 93 01 04 06 00 00 01 00 +10: 00 00 00 00 00 00 00 00 00 15 18 20 40 70 80 22 +20: 30 f4 f0 f7 01 f0 f1 f3 00 00 00 00 00 00 00 00 +30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 04 00 +40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00 +50: 0d 00 00 00 aa 17 f4 20 00 00 00 00 00 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 04 00 00 00 00 00 + +00:1f.0 ISA bridge [0601]: Intel Corporation ICH9M LPC Interface Controller [8086:2919] (rev 03) + Subsystem: Lenovo Device [17aa:20f6] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- + Kernel driver in use: lpc_ich +00: 86 80 19 29 07 00 10 02 03 00 01 06 00 00 80 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 f6 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 10 00 00 80 00 00 00 81 11 00 00 10 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 8b 8b 8b 8b 90 00 00 00 8b 8b 8b 8b f8 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 10 02 0e 3f 01 16 7c 00 e1 15 0c 00 81 16 1c 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 24 0a 00 00 39 00 80 00 2b 1c 0a 00 00 03 00 40 +b0: 00 00 f0 00 00 00 00 00 08 00 02 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 67 45 00 00 00 ff 00 00 00 00 00 00 +e0: 09 00 0c 10 20 02 24 03 64 00 00 00 00 00 00 00 +f0: 01 c0 d1 fe 00 00 00 00 86 0f 04 00 00 00 00 00 + +00:1f.2 SATA controller [0106]: Intel Corporation 82801IBM/IEM (ICH9M/ICH9M-E) 4 port SATA Controller [AHCI mode] [8086:2929] (rev 03) (prog-if 01 [AHCI 1.0]) + Subsystem: Lenovo Device [17aa:20f8] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- Reset- 16bInt+ PostWrite+ + 16-bit legacy interface ports at 0001 + Capabilities: [dc] Power Management version 2 + Flags: PMEClk+ DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=2 PME- + Bridge: PM- B3+ + Kernel driver in use: yenta_cardbus +00: 80 11 76 04 07 00 10 02 ba 00 07 06 10 a8 82 00 +10: 00 00 30 f4 dc 00 00 02 15 16 17 b0 00 00 00 f0 +20: 00 f0 ff f3 00 00 00 c4 00 f0 ff c7 00 40 00 00 +30: fc 40 00 00 00 44 00 00 fc 44 00 00 0b 01 80 05 +40: aa 17 c6 20 01 00 00 00 00 00 00 00 00 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 01 00 a0 04 00 03 00 00 63 04 63 04 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 09 00 00 f0 00 05 00 00 00 +b0: 00 00 00 00 00 00 00 62 00 30 00 00 00 00 00 00 +c0: aa 17 c6 20 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 0a fe +e0: 00 40 c0 24 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +15:00.1 FireWire (IEEE 1394) [0c00]: Ricoh Co Ltd R5C832 IEEE 1394 Controller [1180:0832] (rev 04) (prog-if 10 [OHCI]) + Subsystem: Lenovo ThinkPad R61 [17aa:20c7] + Physical Slot: 1 + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- I2C: 01:69 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled +scan_static_bus for PCI: 00:1f.3 done +PCI: pci_scan_bus returning with max=006 +scan_static_bus for Root Device done +done +BS: Exiting BS_DEV_ENUMERATE state. +BS: BS_DEV_ENUMERATE times (us): entry 0 run 529332 exit 0 +BS: Entering BS_DEV_RESOURCES state. +found VGA at PCI: 00:02.0 +Setting up VGA for PCI: 00:02.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +Adding PCIe enhanced config space BAR 0xf0000000-0xf4000000. +PCI: 00:1c.0 read_resources bus 1 link: 0 +PCI: 00:1c.0 read_resources bus 1 link: 0 done +PCI: 00:1c.1 read_resources bus 2 link: 0 +PCI: 00:1c.1 read_resources bus 2 link: 0 done +PCI: 00:1c.2 read_resources bus 3 link: 0 +PCI: 00:1c.2 read_resources bus 3 link: 0 done +PCI: 00:1c.3 read_resources bus 4 link: 0 +PCI: 00:1c.3 read_resources bus 4 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 +PCI: 05:00.0 read_resources bus 6 link: 0 done +PCI: 00:1e.0 read_resources bus 5 link: 0 done +PCI: 00:1f.0 read_resources bus 0 link: 0 +PNP: 00ff.1 missing read_resources +PNP: 00ff.2 missing read_resources +PCI: 00:1f.0 read_resources bus 0 link: 0 done +PCI: 00:1f.3 read_resources bus 1 link: 0 +PCI: 00:1f.3 read_resources bus 1 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 14 + PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffff flags 1200 index 18 + PCI: 00:02.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 80000 align 19 gran 19 limit ffffffff flags 200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 + PCI: 01:00.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 2c + PCI: 05:00.0 resource base 0 size 1000 align 2 gran 2 limit ffffffff flags 100 index 34 + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 1200 index 1c + PCI: 05:00.0 resource base 0 size 2000000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags c0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags c0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags c0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags c0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.1 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.1 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.2 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:1f.2 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 01:00.0 18 * [0x0 - 0x1f] io +PCI: 00:1c.0 compute_resources_io: base: 20 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 05:00.0 2c * [0x0 - 0xfff] io +PCI: 05:00.0 34 * [0x1000 - 0x1fff] io +PCI: 00:1e.0 compute_resources_io: base: 2000 size: 2000 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 1c * [0x0 - 0x1fff] io +PCI: 00:1c.0 1c * [0x2000 - 0x2fff] io +PCI: 00:1d.0 20 * [0x3000 - 0x301f] io +PCI: 00:1d.1 20 * [0x3020 - 0x303f] io +PCI: 00:1d.2 20 * [0x3040 - 0x305f] io +PCI: 00:1d.3 20 * [0x3060 - 0x307f] io +PCI: 00:1f.1 20 * [0x3080 - 0x308f] io +PCI: 00:1f.2 20 * [0x3090 - 0x309f] io +PCI: 00:02.0 14 * [0x30a0 - 0x30a7] io +PCI: 00:1f.1 10 * [0x30a8 - 0x30af] io +PCI: 00:1f.1 18 * [0x30b0 - 0x30b7] io +PCI: 00:1f.2 10 * [0x30b8 - 0x30bf] io +PCI: 00:1f.2 18 * [0x30c0 - 0x30c7] io +PCI: 00:1f.1 14 * [0x30c8 - 0x30cb] io +PCI: 00:1f.1 1c * [0x30cc - 0x30cf] io +PCI: 00:1f.2 14 * [0x30d0 - 0x30d3] io +PCI: 00:1f.2 1c * [0x30d4 - 0x30d7] io +DOMAIN: 0000 compute_resources_io: base: 30d8 size: 30d8 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:00.0 10 * [0x0 - 0x1ffff] mem +PCI: 00:1c.0 compute_resources_mem: base: 20000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 02:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:1c.1 compute_resources_mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 05:00.0 1c * [0x0 - 0x1ffffff] prefmem +PCI: 00:1e.0 compute_resources_prefmem: base: 2000000 size: 2000000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 05:00.0 24 * [0x0 - 0x1ffffff] mem +PCI: 05:00.0 10 * [0x2000000 - 0x2000fff] mem +PCI: 05:00.1 10 * [0x2001000 - 0x20017ff] mem +PCI: 05:00.2 10 * [0x2001800 - 0x20018ff] mem +PCI: 05:00.3 10 * [0x2001900 - 0x20019ff] mem +PCI: 00:1e.0 compute_resources_mem: base: 2001a00 size: 2100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem +PCI: 00:1e.0 20 * [0x10000000 - 0x120fffff] mem +PCI: 00:1e.0 24 * [0x12100000 - 0x140fffff] prefmem +PCI: 00:1c.0 20 * [0x14100000 - 0x141fffff] mem +PCI: 00:1c.1 20 * [0x14200000 - 0x142fffff] mem +PCI: 00:02.0 10 * [0x14300000 - 0x1437ffff] mem +PCI: 00:02.1 10 * [0x14380000 - 0x143fffff] mem +PCI: 00:02.0 1c * [0x14400000 - 0x1443ffff] mem +PCI: 00:1b.0 10 * [0x14440000 - 0x14443fff] mem +PCI: 00:1d.7 10 * [0x14444000 - 0x144443ff] mem +PCI: 00:1f.2 24 * [0x14444400 - 0x144447ff] mem +DOMAIN: 0000 compute_resources_mem: base: 14444800 size: 14444800 align: 28 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:02.0 +constrain_resources: PCI: 00:02.1 +constrain_resources: PCI: 00:1b.0 +constrain_resources: PCI: 00:1c.0 +constrain_resources: PCI: 01:00.0 +constrain_resources: PCI: 00:1c.1 +constrain_resources: PCI: 02:00.0 +constrain_resources: PCI: 00:1c.2 +constrain_resources: PCI: 00:1c.3 +constrain_resources: PCI: 00:1d.0 +constrain_resources: PCI: 00:1d.1 +constrain_resources: PCI: 00:1d.2 +constrain_resources: PCI: 00:1d.3 +constrain_resources: PCI: 00:1d.7 +constrain_resources: PCI: 00:1e.0 +constrain_resources: PCI: 05:00.0 +constrain_resources: PCI: 05:00.1 +constrain_resources: PCI: 05:00.2 +constrain_resources: PCI: 05:00.3 +constrain_resources: PCI: 00:1f.0 +constrain_resources: PNP: 00ff.1 +constrain_resources: PNP: 00ff.2 +skipping PNP: 00ff.2@60 fixed resource, size=0! +skipping PNP: 00ff.2@62 fixed resource, size=0! +skipping PNP: 00ff.2@64 fixed resource, size=0! +skipping PNP: 00ff.2@66 fixed resource, size=0! +constrain_resources: PNP: 164e.2 +constrain_resources: PNP: 164e.7 +constrain_resources: PNP: 164e.19 +constrain_resources: PNP: 002e.1 +constrain_resources: PNP: 002e.3 +constrain_resources: PNP: 002e.7 +constrain_resources: PCI: 00:1f.1 +constrain_resources: PCI: 00:1f.2 +constrain_resources: PCI: 00:1f.3 +constrain_resources: I2C: 01:69 +constrain_resources: I2C: 01:54 +constrain_resources: I2C: 01:55 +constrain_resources: I2C: 01:56 +constrain_resources: I2C: 01:57 +constrain_resources: I2C: 01:5c +constrain_resources: I2C: 01:5d +constrain_resources: I2C: 01:5e +constrain_resources: I2C: 01:5f +avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff + lim->base 00001690 lim->limit 0000ffff +avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff + lim->base 00000000 lim->limit efffffff +Setting resources... +DOMAIN: 0000 allocate_resources_io: base:1690 size:30d8 align:12 gran:0 limit:ffff +Assigned: PCI: 00:1e.0 1c * [0x2000 - 0x3fff] io +Assigned: PCI: 00:1c.0 1c * [0x4000 - 0x4fff] io +Assigned: PCI: 00:1d.0 20 * [0x5000 - 0x501f] io +Assigned: PCI: 00:1d.1 20 * [0x5020 - 0x503f] io +Assigned: PCI: 00:1d.2 20 * [0x5040 - 0x505f] io +Assigned: PCI: 00:1d.3 20 * [0x5060 - 0x507f] io +Assigned: PCI: 00:1f.1 20 * [0x5080 - 0x508f] io +Assigned: PCI: 00:1f.2 20 * [0x5090 - 0x509f] io +Assigned: PCI: 00:02.0 14 * [0x50a0 - 0x50a7] io +Assigned: PCI: 00:1f.1 10 * [0x50a8 - 0x50af] io +Assigned: PCI: 00:1f.1 18 * [0x50b0 - 0x50b7] io +Assigned: PCI: 00:1f.2 10 * [0x50b8 - 0x50bf] io +Assigned: PCI: 00:1f.2 18 * [0x50c0 - 0x50c7] io +Assigned: PCI: 00:1f.1 14 * [0x50c8 - 0x50cb] io +Assigned: PCI: 00:1f.1 1c * [0x50cc - 0x50cf] io +Assigned: PCI: 00:1f.2 14 * [0x50d0 - 0x50d3] io +Assigned: PCI: 00:1f.2 1c * [0x50d4 - 0x50d7] io +DOMAIN: 0000 allocate_resources_io: next_base: 50d8 size: 30d8 align: 12 gran: 0 done +PCI: 00:1c.0 allocate_resources_io: base:4000 size:1000 align:12 gran:12 limit:ffff +Assigned: PCI: 01:00.0 18 * [0x4000 - 0x401f] io +PCI: 00:1c.0 allocate_resources_io: next_base: 4020 size: 1000 align: 12 gran: 12 done +PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.3 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.3 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1e.0 allocate_resources_io: base:2000 size:2000 align:12 gran:12 limit:ffff +Assigned: PCI: 05:00.0 2c * [0x2000 - 0x2fff] io +Assigned: PCI: 05:00.0 34 * [0x3000 - 0x3fff] io +PCI: 00:1e.0 allocate_resources_io: next_base: 4000 size: 2000 align: 12 gran: 12 done +DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:14444800 align:28 gran:0 limit:efffffff +Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem +Assigned: PCI: 00:1e.0 20 * [0xe0000000 - 0xe20fffff] mem +Assigned: PCI: 00:1e.0 24 * [0xe2100000 - 0xe40fffff] prefmem +Assigned: PCI: 00:1c.0 20 * [0xe4100000 - 0xe41fffff] mem +Assigned: PCI: 00:1c.1 20 * [0xe4200000 - 0xe42fffff] mem +Assigned: PCI: 00:02.0 10 * [0xe4300000 - 0xe437ffff] mem +Assigned: PCI: 00:02.1 10 * [0xe4380000 - 0xe43fffff] mem +Assigned: PCI: 00:02.0 1c * [0xe4400000 - 0xe443ffff] mem +Assigned: PCI: 00:1b.0 10 * [0xe4440000 - 0xe4443fff] mem +Assigned: PCI: 00:1d.7 10 * [0xe4444000 - 0xe44443ff] mem +Assigned: PCI: 00:1f.2 24 * [0xe4444400 - 0xe44447ff] mem +DOMAIN: 0000 allocate_resources_mem: next_base: e4444800 size: 14444800 align: 28 gran: 0 done +PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 allocate_resources_mem: base:e4100000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 01:00.0 10 * [0xe4100000 - 0xe411ffff] mem +PCI: 00:1c.0 allocate_resources_mem: next_base: e4120000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_mem: base:e4200000 size:100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 02:00.0 10 * [0xe4200000 - 0xe420ffff] mem +PCI: 00:1c.1 allocate_resources_mem: next_base: e4210000 size: 100000 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.3 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_prefmem: base:e2100000 size:2000000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 1c * [0xe2100000 - 0xe40fffff] prefmem +PCI: 00:1e.0 allocate_resources_prefmem: next_base: e4100000 size: 2000000 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_mem: base:e0000000 size:2100000 align:20 gran:20 limit:efffffff +Assigned: PCI: 05:00.0 24 * [0xe0000000 - 0xe1ffffff] mem +Assigned: PCI: 05:00.0 10 * [0xe2000000 - 0xe2000fff] mem +Assigned: PCI: 05:00.1 10 * [0xe2001000 - 0xe20017ff] mem +Assigned: PCI: 05:00.2 10 * [0xe2001800 - 0xe20018ff] mem +Assigned: PCI: 05:00.3 10 * [0xe2001900 - 0xe20019ff] mem +PCI: 00:1e.0 allocate_resources_mem: next_base: e2001a00 size: 2100000 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +pci_tolm: 0xd0000000 +Base of stolen memory: 0xbf800000 +Top of Low Used DRAM: 0xc0000000 +IGD decoded, subtracting 8M UMA +Available memory: 3137536K (3064M) +Adding PCIe config bar +DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:00.0 cf <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem +PCI: 00:02.0 10 <- [0x00e4300000 - 0x00e437ffff] size 0x00080000 gran 0x13 mem +PCI: 00:02.0 14 <- [0x00000050a0 - 0x00000050a7] size 0x00000008 gran 0x03 io +PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem +PCI: 00:02.0 1c <- [0x00e4400000 - 0x00e443ffff] size 0x00040000 gran 0x12 mem +PCI: 00:02.1 10 <- [0x00e4380000 - 0x00e43fffff] size 0x00080000 gran 0x13 mem +PCI: 00:1b.0 10 <- [0x00e4440000 - 0x00e4443fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x0000004000 - 0x0000004fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem +PCI: 00:1c.0 20 <- [0x00e4100000 - 0x00e41fffff] size 0x00100000 gran 0x14 bus 01 mem +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 01:00.0 10 <- [0x00e4100000 - 0x00e411ffff] size 0x00020000 gran 0x11 mem +PCI: 01:00.0 18 <- [0x0000004000 - 0x000000401f] size 0x00000020 gran 0x05 io +PCI: 00:1c.0 assign_resources, bus 1 link: 0 +PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.1 20 <- [0x00e4200000 - 0x00e42fffff] size 0x00100000 gran 0x14 bus 02 mem +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 02:00.0 10 <- [0x00e4200000 - 0x00e420ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:1c.1 assign_resources, bus 2 link: 0 +PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem +PCI: 00:1c.3 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 04 io +PCI: 00:1c.3 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 prefmem +PCI: 00:1c.3 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 04 mem +PCI: 00:1d.0 20 <- [0x0000005000 - 0x000000501f] size 0x00000020 gran 0x05 io +PCI: 00:1d.1 20 <- [0x0000005020 - 0x000000503f] size 0x00000020 gran 0x05 io +PCI: 00:1d.2 20 <- [0x0000005040 - 0x000000505f] size 0x00000020 gran 0x05 io +PCI: 00:1d.3 20 <- [0x0000005060 - 0x000000507f] size 0x00000020 gran 0x05 io +PCI: 00:1d.7 10 <- [0x00e4444000 - 0x00e44443ff] size 0x00000400 gran 0x0a mem +PCI: 00:1e.0 1c <- [0x0000002000 - 0x0000003fff] size 0x00002000 gran 0x0c bus 05 io +PCI: 00:1e.0 24 <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x14 bus 05 prefmem +PCI: 00:1e.0 20 <- [0x00e0000000 - 0x00e20fffff] size 0x02100000 gran 0x14 bus 05 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 05:00.0 In set resources +PCI: 05:00.0 10 <- [0x00e2000000 - 0x00e2000fff] size 0x00001000 gran 0x0c mem +PCI: 05:00.0 2c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 34 <- [0x0000003000 - 0x0000003fff] size 0x00001000 gran 0x02 io +PCI: 05:00.0 1c <- [0x00e2100000 - 0x00e40fffff] size 0x02000000 gran 0x0c prefmem +PCI: 05:00.0 24 <- [0x00e0000000 - 0x00e1ffffff] size 0x02000000 gran 0x0c mem +PCI: 05:00.1 10 <- [0x00e2001000 - 0x00e20017ff] size 0x00000800 gran 0x0b mem +PCI: 05:00.2 10 <- [0x00e2001800 - 0x00e20018ff] size 0x00000100 gran 0x08 mem +PCI: 05:00.3 10 <- [0x00e2001900 - 0x00e20019ff] size 0x00000100 gran 0x08 mem +PCI: 00:1e.0 assign_resources, bus 5 link: 0 +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PNP: 00ff.1 missing set_resources +PNP: 00ff.2 missing set_resources +PNP: 164e.2 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io +ERROR: PNP: 164e.2 70 irq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 74 drq size: 0x0000000001 not assigned +ERROR: PNP: 164e.2 75 drq size: 0x0000000001 not assigned +PNP: 164e.7 60 <- [0x0000001680 - 0x000000168f] size 0x00000010 gran 0x04 io +ERROR: PNP: 164e.7 70 irq size: 0x0000000001 not assigned +PNP: 164e.19 60 <- [0x000000164c - 0x000000164d] size 0x00000002 gran 0x01 io +ERROR: PNP: 164e.19 70 irq size: 0x0000000001 not assigned +PNP: 002e.1 60 <- [0x00000003bc - 0x00000007bb] size 0x00000400 gran 0x0a io +PNP: 002e.1 70 <- [0x0000000007 - 0x0000000007] size 0x00000001 gran 0x00 irq +ERROR: PNP: 002e.1 74 drq size: 0x0000000001 not assigned +PNP: 002e.3 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io +PNP: 002e.3 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq +PNP: 002e.7 60 <- [0x0000001620 - 0x0000001627] size 0x00000008 gran 0x03 io +ERROR: PNP: 002e.7 70 irq size: 0x0000000001 not assigned +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PCI: 00:1f.1 10 <- [0x00000050a8 - 0x00000050af] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 14 <- [0x00000050c8 - 0x00000050cb] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 18 <- [0x00000050b0 - 0x00000050b7] size 0x00000008 gran 0x03 io +PCI: 00:1f.1 1c <- [0x00000050cc - 0x00000050cf] size 0x00000004 gran 0x02 io +PCI: 00:1f.1 20 <- [0x0000005080 - 0x000000508f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 10 <- [0x00000050b8 - 0x00000050bf] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x00000050d0 - 0x00000050d3] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x00000050c0 - 0x00000050c7] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x00000050d4 - 0x00000050d7] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x0000005090 - 0x000000509f] size 0x00000010 gran 0x04 io +PCI: 00:1f.2 24 <- [0x00e4444400 - 0x00e44447ff] size 0x00000400 gran 0x0a mem +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +CBMEM region bf6d0000-bf7fffff (cbmem_late_set_table) +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 1690 size 30d8 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base d0000000 size 14444800 align 28 gran 0 limit efffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base bf800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 5 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:00.0 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags e0000200 index cf + PCI: 00:02.0 + PCI: 00:02.0 resource base e4300000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:02.0 resource base 50a0 size 8 align 3 gran 3 limit ffff flags 60000100 index 14 + PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001200 index 18 + PCI: 00:02.0 resource base e4400000 size 40000 align 18 gran 18 limit efffffff flags 60000200 index 1c + PCI: 00:02.1 + PCI: 00:02.1 resource base e4380000 size 80000 align 19 gran 19 limit efffffff flags 60000200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base e4440000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10 + PCI: 00:1c.0 child on link 0 PCI: 01:00.0 + PCI: 00:1c.0 resource base 4000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.0 resource base e4100000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 01:00.0 + PCI: 01:00.0 resource base e4100000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10 + PCI: 01:00.0 resource base 4000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 + PCI: 00:1c.1 child on link 0 PCI: 02:00.0 + PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.1 resource base e4200000 size 100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base e4200000 size 10000 align 16 gran 16 limit efffffff flags 60000201 index 10 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.3 + PCI: 00:1c.3 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.3 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 5000 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 5020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 5040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.3 + PCI: 00:1d.3 resource base 5060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base e4444000 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1e.0 child on link 0 PCI: 05:00.0 + PCI: 00:1e.0 resource base 2000 size 2000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1e.0 resource base e2100000 size 2000000 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1e.0 resource base e0000000 size 2100000 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 05:00.0 + PCI: 05:00.0 resource base e2000000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 10 + PCI: 05:00.0 resource base 2000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 2c + PCI: 05:00.0 resource base 3000 size 1000 align 2 gran 2 limit ffff flags 60000100 index 34 + PCI: 05:00.0 resource base e2100000 size 2000000 align 12 gran 12 limit efffffff flags 60001200 index 1c + PCI: 05:00.0 resource base e0000000 size 2000000 align 12 gran 12 limit efffffff flags 60000200 index 24 + PCI: 05:00.1 + PCI: 05:00.1 resource base e2001000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 10 + PCI: 05:00.2 + PCI: 05:00.2 resource base e2001800 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 05:00.3 + PCI: 05:00.3 resource base e2001900 size 100 align 8 gran 8 limit efffffff flags 60000200 index 10 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PNP: 164e.2 + PNP: 164e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 164e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 164e.3 + PNP: 164e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 164e.3 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.7 + PNP: 164e.7 resource base 1680 size 10 align 4 gran 4 limit ffff flags e0000100 index 60 + PNP: 164e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 164e.19 + PNP: 164e.19 resource base 164c size 2 align 1 gran 1 limit ffff flags e0000100 index 60 + PNP: 164e.19 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 + PNP: 002e.0 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.0 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 3bc size 400 align 10 gran 10 limit 7ff flags e0000100 index 60 + PNP: 002e.1 resource base 7 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 75 + PNP: 002e.3 + PNP: 002e.3 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.7 + PNP: 002e.7 resource base 1620 size 8 align 3 gran 3 limit ffff flags e0000100 index 60 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.a + PNP: 002e.a resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 60 + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PCI: 00:1f.1 + PCI: 00:1f.1 resource base 50a8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.1 resource base 50c8 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.1 resource base 50b0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.1 resource base 50cc size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.1 resource base 5080 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 50b8 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.2 resource base 50d0 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.2 resource base 50c0 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.2 resource base 50d4 size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.2 resource base 5090 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 resource base e4444400 size 400 align 10 gran 10 limit efffffff flags 60000200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:69 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + I2C: 01:69 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f +Done allocating resources. +BS: Exiting BS_DEV_RESOURCES state. +BS: BS_DEV_RESOURCES times (us): entry 0 run 3353806 exit 0 +BS: Entering BS_DEV_ENABLE state. +Enabling resources... +PCI: 00:00.0 subsystem <- 17aa/2017 +PCI: 00:00.0 cmd <- 06 +PCI: 00:02.0 subsystem <- 17aa/201a +PCI: 00:02.0 cmd <- 03 +PCI: 00:02.1 subsystem <- 17aa/201a +PCI: 00:02.1 cmd <- 02 +PCI: 00:1b.0 subsystem <- 17aa/2010 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 0000/0000 +PCI: 00:1c.0 cmd <- 107 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 0000/0000 +PCI: 00:1c.1 cmd <- 106 +PCI: 00:1c.2 bridge ctrl <- 0003 +PCI: 00:1c.2 cmd <- 00 +PCI: 00:1c.3 bridge ctrl <- 0003 +PCI: 00:1c.3 cmd <- 00 +PCI: 00:1d.0 subsystem <- 17aa/200a +PCI: 00:1d.0 cmd <- 01 +PCI: 00:1d.1 subsystem <- 17aa/200a +PCI: 00:1d.1 cmd <- 01 +PCI: 00:1d.2 subsystem <- 17aa/200a +PCI: 00:1d.2 cmd <- 01 +PCI: 00:1d.3 subsystem <- 17aa/200a +PCI: 00:1d.3 cmd <- 01 +PCI: 00:1d.7 subsystem <- 17aa/200b +PCI: 00:1d.7 cmd <- 102 +PCI: 00:1e.0 bridge ctrl <- 0003 +PCI: 00:1e.0 cmd <- 07 (NOT WRITTEN!) +PCI: 00:1f.0 subsystem <- 17aa/2009 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.1 subsystem <- 17aa/200c +PCI: 00:1f.1 cmd <- 01 +PCI: 00:1f.2 subsystem <- 17aa/200d +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 17aa/200f +PCI: 00:1f.3 cmd <- 101 +PCI: 01:00.0 cmd <- 03 +PCI: 02:00.0 cmd <- 02 +PCI: 05:00.0 bridge ctrl <- 0503 +PCI: 05:00.0 cmd <- 03 +PCI: 05:00.1 cmd <- 02 +PCI: 05:00.2 cmd <- 06 +PCI: 05:00.3 cmd <- 06 +done. +BS: Exiting BS_DEV_ENABLE state. +BS: BS_DEV_ENABLE times (us): entry 0 run 124473 exit 0 +BS: Entering BS_DEV_INIT state. +Initializing devices... +Root Device init +recv_ec_data: 0x11 +recv_ec_data: 0x11 +Root Device init 5804 usecs +CPU_CLUSTER: 0 init +start_eip=0x00001000, code_size=0x00000031 +Initializing SMM handler... ... pmbase = 0x0500 + +SMI_STS: MCSMI PM1 +PM1_STS: WAK PWRBTN TMROF +GPE0_STS: GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 +ALT_GP_SMI_STS: GPI15 GPI14 GPI13 GPI12 GPI11 GPI10 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 +TCO_STS: INTRD_DET + ... raise SMI# +Initializing CPU #0 +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000bf800000 size 0xbf740000 type 6 +0x00000000bf800000 - 0x00000000d0000000 size 0x10800000 type 0 +0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 +0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 +MTRR addr 0x0-0x10 set to 6 type @ 0 +MTRR addr 0x10-0x20 set to 6 type @ 1 +MTRR addr 0x20-0x30 set to 6 type @ 2 +MTRR addr 0x30-0x40 set to 6 type @ 3 +MTRR addr 0x40-0x50 set to 6 type @ 4 +MTRR addr 0x50-0x60 set to 6 type @ 5 +MTRR addr 0x60-0x70 set to 6 type @ 6 +MTRR addr 0x70-0x80 set to 6 type @ 7 +MTRR addr 0x80-0x84 set to 6 type @ 8 +MTRR addr 0x84-0x88 set to 6 type @ 9 +MTRR addr 0x88-0x8c set to 6 type @ 10 +MTRR addr 0x8c-0x90 set to 6 type @ 11 +MTRR addr 0x90-0x94 set to 6 type @ 12 +MTRR addr 0x94-0x98 set to 6 type @ 13 +MTRR addr 0x98-0x9c set to 6 type @ 14 +MTRR addr 0x9c-0xa0 set to 6 type @ 15 +MTRR addr 0xa0-0xa4 set to 0 type @ 16 +MTRR addr 0xa4-0xa8 set to 0 type @ 17 +MTRR addr 0xa8-0xac set to 0 type @ 18 +MTRR addr 0xac-0xb0 set to 0 type @ 19 +MTRR addr 0xb0-0xb4 set to 0 type @ 20 +MTRR addr 0xb4-0xb8 set to 0 type @ 21 +MTRR addr 0xb8-0xbc set to 0 type @ 22 +MTRR addr 0xbc-0xc0 set to 0 type @ 23 +MTRR addr 0xc0-0xc1 set to 6 type @ 24 +MTRR addr 0xc1-0xc2 set to 6 type @ 25 +MTRR addr 0xc2-0xc3 set to 6 type @ 26 +MTRR addr 0xc3-0xc4 set to 6 type @ 27 +MTRR addr 0xc4-0xc5 set to 6 type @ 28 +MTRR addr 0xc5-0xc6 set to 6 type @ 29 +MTRR addr 0xc6-0xc7 set to 6 type @ 30 +MTRR addr 0xc7-0xc8 set to 6 type @ 31 +MTRR addr 0xc8-0xc9 set to 6 type @ 32 +MTRR addr 0xc9-0xca set to 6 type @ 33 +MTRR addr 0xca-0xcb set to 6 type @ 34 +MTRR addr 0xcb-0xcc set to 6 type @ 35 +MTRR addr 0xcc-0xcd set to 6 type @ 36 +MTRR addr 0xcd-0xce set to 6 type @ 37 +MTRR addr 0xce-0xcf set to 6 type @ 38 +MTRR addr 0xcf-0xd0 set to 6 type @ 39 +MTRR addr 0xd0-0xd1 set to 6 type @ 40 +MTRR addr 0xd1-0xd2 set to 6 type @ 41 +MTRR addr 0xd2-0xd3 set to 6 type @ 42 +MTRR addr 0xd3-0xd4 set to 6 type @ 43 +MTRR addr 0xd4-0xd5 set to 6 type @ 44 +MTRR addr 0xd5-0xd6 set to 6 type @ 45 +MTRR addr 0xd6-0xd7 set to 6 type @ 46 +MTRR addr 0xd7-0xd8 set to 6 type @ 47 +MTRR addr 0xd8-0xd9 set to 6 type @ 48 +MTRR addr 0xd9-0xda set to 6 type @ 49 +MTRR addr 0xda-0xdb set to 6 type @ 50 +MTRR addr 0xdb-0xdc set to 6 type @ 51 +MTRR addr 0xdc-0xdd set to 6 type @ 52 +MTRR addr 0xdd-0xde set to 6 type @ 53 +MTRR addr 0xde-0xdf set to 6 type @ 54 +MTRR addr 0xdf-0xe0 set to 6 type @ 55 +MTRR addr 0xe0-0xe1 set to 6 type @ 56 +MTRR addr 0xe1-0xe2 set to 6 type @ 57 +MTRR addr 0xe2-0xe3 set to 6 type @ 58 +MTRR addr 0xe3-0xe4 set to 6 type @ 59 +MTRR addr 0xe4-0xe5 set to 6 type @ 60 +MTRR addr 0xe5-0xe6 set to 6 type @ 61 +MTRR addr 0xe6-0xe7 set to 6 type @ 62 +MTRR addr 0xe7-0xe8 set to 6 type @ 63 +MTRR addr 0xe8-0xe9 set to 6 type @ 64 +MTRR addr 0xe9-0xea set to 6 type @ 65 +MTRR addr 0xea-0xeb set to 6 type @ 66 +MTRR addr 0xeb-0xec set to 6 type @ 67 +MTRR addr 0xec-0xed set to 6 type @ 68 +MTRR addr 0xed-0xee set to 6 type @ 69 +MTRR addr 0xee-0xef set to 6 type @ 70 +MTRR addr 0xef-0xf0 set to 6 type @ 71 +MTRR addr 0xf0-0xf1 set to 6 type @ 72 +MTRR addr 0xf1-0xf2 set to 6 type @ 73 +MTRR addr 0xf2-0xf3 set to 6 type @ 74 +MTRR addr 0xf3-0xf4 set to 6 type @ 75 +MTRR addr 0xf4-0xf5 set to 6 type @ 76 +MTRR addr 0xf5-0xf6 set to 6 type @ 77 +MTRR addr 0xf6-0xf7 set to 6 type @ 78 +MTRR addr 0xf7-0xf8 set to 6 type @ 79 +MTRR addr 0xf8-0xf9 set to 6 type @ 80 +MTRR addr 0xf9-0xfa set to 6 type @ 81 +MTRR addr 0xfa-0xfb set to 6 type @ 82 +MTRR addr 0xfb-0xfc set to 6 type @ 83 +MTRR addr 0xfc-0xfd set to 6 type @ 84 +MTRR addr 0xfd-0xfe set to 6 type @ 85 +MTRR addr 0xfe-0xff set to 6 type @ 86 +MTRR addr 0xff-0x100 set to 6 type @ 87 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: default type WB/UC MTRR counts: 4/4. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x00 done. +CPU: 0 2 siblings +CPU: 0 has sibling 1 +CPU #0 initialized +CPU1: stack_base 00160000, stack_end 00160ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++Sending STARTUP #2 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #1 +Waiting for 1 CPUS to stop +CPU: vendor Intel device 6ec +CPU: family 06, model 0e, stepping 0c +Enabling cache +microcode: sig=0x6ec pf=0x20 revision=0x0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +Microcode size field is 0 +microcode: updated to revision 0x54 date=2006-05-01 +CPU: Intel(R) Core(TM) Duo CPU L2400 @ 1.66GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 32 bits +MTRR: 0 base 0x0000000000000000 mask 0x0000000080000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x00000000c0000000 type 6 +MTRR: 2 base 0x00000000bf800000 mask 0x00000000ff800000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x00000000f0000000 type 1 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x01 done. +CPU: 1 2 siblings +CPU #1 initialized +CPU 1 going down... +All AP CPUs stopped (11641 loops) +CPU1: stack: 00160000 - 00161000, lowest used address 00160c68, stack used: 920 bytes +CPU_CLUSTER: 0 init 687708 usecs +PCI: 00:00.0 init +Normal boot. +PCI: 00:00.0 init 2905 usecs +PCI: 00:02.0 init +Initializing VGA without OPROM. +GMADR=0xd0000008 GTTADR=0xe4400000 +i915lightup: graphics d0020000 mmio e4300000 addrport 50a0 physbase bf800000 +Extracted contents: +header: 00 ff ff ff ff ff ff 00 +serial number: 30 ae 00 40 00 00 00 00 00 0f +version: 01 03 +basic params: 80 19 12 78 ea +chroma info: ed 75 91 57 4f 8b 26 21 50 54 +established: 21 08 00 +standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 +descriptor 1: 28 15 00 40 41 00 26 30 18 88 36 00 f6 b9 00 00 00 18 +descriptor 2: ed 10 00 40 41 00 26 30 18 88 36 00 f6 b9 00 00 00 18 +descriptor 3: 00 00 00 0f 00 61 43 32 61 43 28 0f 01 00 4c a3 58 4a +descriptor 4: 00 00 00 fe 00 4c 54 4e 31 32 31 58 4a 2d 4c 30 37 0a +extensions: 00 +checksum: 00 + +Manufacturer: LEN Model 4000 Serial Number 0 +EDID version: 1.3 +Digital display +Maximum image size: 25 cm x 18 cm +Gamma: 220% +Check DPMS levels +DPMS levels: Standby Suspend Off +Supported color formats: RGB 4:4:4, YCrCb 4:2:2 +First detailed timing is preferred timing +Established timings supported: + 640x480@60Hz + 800x600@60Hz + 1024x768@60Hz +Standard timings supported: +Detailed timings +Hex of detail: 281500404100263018883600f6b900000018 +Did detailed timing +Detailed mode (IN HEX): Clock 54160 KHz, f6 mm x b9 mm + 0400 0418 04a0 0540 hborder 0 + 0300 0303 0309 0326 vborder 0 + -hsync -vsync +Hex of detail: ed1000404100263018883600f6b900000018 +Detailed mode (IN HEX): Clock 54160 KHz, f6 mm x b9 mm + 0400 0418 04a0 0540 hborder 0 + 0300 0303 0309 0326 vborder 0 + -hsync -vsync +Hex of detail: 0000000f006143326143280f01004ca3584a +Manufacturer-specified data, tag 15 +Hex of detail: 000000fe004c544e313231584a2d4c30370a +ASCII string: LTN121XJ +Checksum +Checksum: 0x0 (valid) + +Unknown extension block + +EDID block does NOT conform to EDID 1.3! + Missing name descriptor + Missing monitor ranges + Detailed block string not properly terminated +EDID block does not conform at all! + Bad year of manufacture + Detailed blocks filled with garbage +I915_WRITE(HTOTAL(pipe), 053f03ff) +I915_WRITE(HBLANK(pipe),0x053f03ff) +I915_WRITE(HSYNC(pipe),0x049f0417) +I915_WRITE(VTOTAL(pipe), 032502ff) +I915_WRITE(VBLANK(pipe),0x032502ff) +I915_WRITE(VSYNC(pipe),0x03080302) +Table has 2247 elements +Change verbosity to 0 +run: return 2246 +Run returns 2247 +gtt_setup: GTT PGETLB_CTL register: 0x0 +gtt_setup: GTT PGETLB_CTL register: 0x1 +gtt_setup: GTT PGETLB_CTL register: 0xbf800001 +gtt_setup: GTT PGETLB_CTL register: 0xbf800003 +gtt_setup is enabled: GTT PGETLB_CTL register: 0x1 +setgtt(0,1600,0xbf800000,4096); +GTT PGETLB_CTL register: 0xbf800001 +GTT Enabled +memset d0020000 to 0x00 for 3145728 bytes +229929 microseconds +PCI: 00:02.0 init 265041 usecs +PCI: 00:02.1 init +PCI: 00:02.1 init 2382 usecs +PCI: 00:1b.0 init +Azalia: codec type: Azalia +Azalia: base = e4440000 +Azalia: codec_mask = 03 +Azalia: Initializing codec #1 +Azalia: codec viddid: 14f12bfa +Azalia: No verb! +Azalia: Initializing codec #0 +Azalia: codec viddid: 11d41981 +Azalia: No verb! +PCI: 00:1b.0 init 25808 usecs +PCI: 00:1c.0 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.0 init 4490 usecs +PCI: 00:1c.1 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.1 init 4490 usecs +PCI: 00:1c.2 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.2 init 4491 usecs +PCI: 00:1c.3 init +Initializing ICH7 PCIe bridge. +PCI: 00:1c.3 init 4489 usecs +PCI: 00:1d.0 init +UHCI: Setting up controller.. done. +PCI: 00:1d.0 init 4925 usecs +PCI: 00:1d.1 init +UHCI: Setting up controller.. done. +PCI: 00:1d.1 init 4926 usecs +PCI: 00:1d.2 init +UHCI: Setting up controller.. done. +PCI: 00:1d.2 init 4924 usecs +PCI: 00:1d.3 init +UHCI: Setting up controller.. done. +PCI: 00:1d.3 init 4925 usecs +PCI: 00:1d.7 init +EHCI: Setting up controller.. done. +PCI: 00:1d.7 init 4933 usecs +PCI: 00:1e.0 init +PCI: 00:1e.0 init 1683 usecs +PCI: 00:1f.0 init +i82801gx: lpc_init +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +IOAPIC: Dumping registers + reg 0x0000: 0x02000000 + reg 0x0001: 0x00170020 + reg 0x0002: 0x00170020 +WARNING: No CMOS option 'power_on_after_fail'. +Set power on after power failure. +NMI sources enabled. +rtc_failed = 0x0 +RTC Init +i8259_configure_irq_trigger: current interrupts are 0x0 +i8259_configure_irq_trigger: try to set interrupts 0x200 +Disabling ACPI via APMC: +done. +Locking SMM. +PCI: 00:1f.0 init 50455 usecs +PCI: 00:1f.1 init +i82801gx_ide: initializing... IDE0 +PCI: 00:1f.1 init 4942 usecs +PCI: 00:1f.2 init +i82801gx_sata: initializing... +SATA controller in AHCI mode. +PCI: 00:1f.2 init 7210 usecs +PCI: 01:00.0 init +PCI: 01:00.0 init 1669 usecs +PCI: 02:00.0 init +PCI: 02:00.0 init 1668 usecs +PCI: 05:00.0 init +Ricoh RL5c476: Initializing. +CF Base = 0 +CF boot not enabled. +PCI: 05:00.0 init 7377 usecs +PCI: 05:00.1 init +PCI: 05:00.1 init 1670 usecs +PCI: 05:00.2 init +PCI: 05:00.2 init 1670 usecs +PCI: 05:00.3 init +PCI: 05:00.3 init 1670 usecs +PNP: 164e.2 init +PNP: 164e.2 init 1582 usecs +PNP: 164e.7 init +PNP: 164e.7 init 1584 usecs +PNP: 164e.19 init +PNP: 164e.19 init 1670 usecs +PNP: 002e.1 init +PNP: 002e.1 init 1582 usecs +PNP: 002e.3 init +PNP: 002e.3 init 1584 usecs +PNP: 002e.7 init +PNP: 002e.7 init 1582 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:69 init +I2C: 01:69 init 16205 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:54 init +I2C: 01:54 init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:55 init +I2C: 01:55 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:56 init +I2C: 01:56 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:57 init +I2C: 01:57 init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5c init +Locking EEPROM RFID +init EEPROM done +I2C: 01:5c init 28615 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5d init +I2C: 01:5d init 3593 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5e init +I2C: 01:5e init 3592 usecs +smbus: PCI: 00:1f.3[0]->I2C: 01:5f init +I2C: 01:5f init 3593 usecs +Devices initialized +Show all devs...After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.3: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PNP: 164e.2: enabled 1 +PNP: 164e.3: enabled 0 +PNP: 164e.7: enabled 1 +PNP: 164e.19: enabled 1 +PNP: 002e.0: enabled 0 +PNP: 002e.1: enabled 1 +PNP: 002e.2: enabled 0 +PNP: 002e.3: enabled 1 +PNP: 002e.7: enabled 1 +PNP: 002e.a: enabled 0 +PCI: 00:1f.1: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 01:69: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:5c: enabled 1 +I2C: 01:5d: enabled 1 +I2C: 01:5e: enabled 1 +I2C: 01:5f: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 01:00.0: enabled 1 +PCI: 02:00.0: enabled 1 +PCI: 05:00.0: enabled 1 +PCI: 05:00.1: enabled 1 +PCI: 05:00.2: enabled 1 +PCI: 05:00.3: enabled 1 +APIC: 01: enabled 1 +BS: Exiting BS_DEV_INIT state. +BS: BS_DEV_INIT times (us): entry 0 run 1411225 exit 0 +BS: Entering BS_POST_DEVICE state. +CBMEM region bf6d0000-bf7fffff (cbmem_check_toc) +Adding CBMEM entry as no. 4 +Moving GDT to bf6e0600...ok +Finalize devices... +Devices finalized +BS: Exiting BS_POST_DEVICE state. +BS: BS_POST_DEVICE times (us): entry 9470 run 6558 exit 0 +BS: Entering BS_OS_RESUME_CHECK state. +BS: Exiting BS_OS_RESUME_CHECK state. +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 3401 exit 0 +BS: Entering BS_WRITE_TABLES state. +Copying Interrupt Routing Table to 0x000f0000... done. +Adding CBMEM entry as no. 5 +Copying Interrupt Routing Table to 0xbf6e0800... done. +PIRQ table: 272 bytes. +Wrote the mp table end at: 000f0410 - 000f05cc +Adding CBMEM entry as no. 6 +Wrote the mp tabl +6653 bytes lost diff --git a/i18n/fr_FR/docs/future/dumps/x60_5893_native.tar.gz b/i18n/fr_FR/docs/future/dumps/x60_5893_native.tar.gz new file mode 100644 index 00000000..59266f82 Binary files /dev/null and b/i18n/fr_FR/docs/future/dumps/x60_5893_native.tar.gz differ diff --git a/i18n/fr_FR/docs/future/dumps/x60_5893_native_crashdump b/i18n/fr_FR/docs/future/dumps/x60_5893_native_crashdump new file mode 100644 index 00000000..a3aedb64 --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/x60_5893_native_crashdump @@ -0,0 +1,77 @@ +Time: 1401660987 s 272232 us +Kernel: 3.14.4-gnuowen +PCI ID: 0x27a2 +EIR: 0x00000010 +IER: 0x00028053 +PGTBL_ER: 0x00000012 +FORCEWAKE: 0x00000000 +DERRMR: 0x00000000 +CCID: 0x00000000 +Missed interrupts: 0x00000000 + fence[0] = 00000000 + fence[1] = 00000000 + fence[2] = 00000000 + fence[3] = 00000000 + fence[4] = 00000000 + fence[5] = 00000000 + fence[6] = 00000000 + fence[7] = 00000000 + fence[8] = 00000000 + fence[9] = 00000000 + fence[10] = 00000000 + fence[11] = 00000000 + fence[12] = 00000000 + fence[13] = 00000000 + fence[14] = 00000000 + fence[15] = 00000000 + INSTDONE_0: 0x7fffffc0 + INSTDONE_1: 0x00000000 + INSTDONE_2: 0x00000000 + INSTDONE_3: 0x00000000 +Active [0]: +Pinned [0]: +Num Pipes: 2 +Pipe [0]: + Power: off + SRC: 00000000 +Plane [0]: + CNTR: 00000000 + STRIDE: 00000000 + SIZE: 00000000 + POS: 00000000 + ADDR: 00000000 +Cursor [0]: + CNTR: 00000000 + POS: 00000000 + BASE: 00000000 +Pipe [1]: + Power: off + SRC: 00000000 +Plane [1]: + CNTR: 00000000 + STRIDE: 00000000 + SIZE: 00000000 + POS: 00000000 + ADDR: 00000000 +Cursor [1]: + CNTR: 00000000 + POS: 00000000 + BASE: 00000000 +CPU transcoder: A + Power: off + CONF: 00000000 + HTOTAL: 00000000 + HBLANK: 00000000 + HSYNC: 00000000 + VTOTAL: 00000000 + VBLANK: 00000000 + VSYNC: 00000000 +CPU transcoder: A + Power: off + CONF: 00000000 + HTOTAL: 00000000 + HBLANK: 00000000 + HSYNC: 00000000 + VTOTAL: 00000000 + VBLANK: 00000000 + VSYNC: 00000000 diff --git a/i18n/fr_FR/docs/future/dumps/x60_5893_vbios.tar.gz b/i18n/fr_FR/docs/future/dumps/x60_5893_vbios.tar.gz new file mode 100644 index 00000000..4ff78404 Binary files /dev/null and b/i18n/fr_FR/docs/future/dumps/x60_5893_vbios.tar.gz differ diff --git a/i18n/fr_FR/docs/future/dumps/x60_lspcixxxvvnn_5927_19 b/i18n/fr_FR/docs/future/dumps/x60_lspcixxxvvnn_5927_19 new file mode 100644 index 00000000..5c524c9f --- /dev/null +++ b/i18n/fr_FR/docs/future/dumps/x60_lspcixxxvvnn_5927_19 @@ -0,0 +1,809 @@ +00:00.0 Host bridge [0600]: Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory Controller Hub [8086:27a0] (rev 03) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:2017] + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- + Kernel driver in use: agpgart-intel +00: 86 80 a0 27 06 00 90 20 03 00 00 06 00 00 00 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 17 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 90 d1 fe 01 40 d1 fe 05 00 00 f0 01 80 d1 fe +50: 00 00 30 00 19 00 00 00 00 00 00 00 00 00 00 00 +60: 01 30 d1 fe 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 30 33 33 33 33 33 33 00 ff 03 00 00 80 1a 38 00 +a0: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 be ba fe ca +e0: 09 00 09 51 02 04 0a 90 0e 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 05 00 10 00 00 00 + +00:02.0 VGA compatible controller [0300]: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller [8086:27a2] (rev 03) (prog-if 00 [VGA controller]) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:201a] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- [disabled] + Capabilities: [90] MSI: Enable- Count=1/1 Maskable- 64bit- + Address: 00000000 Data: 0000 + Capabilities: [d0] Power Management version 2 + Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Kernel driver in use: i915 +00: 86 80 a2 27 07 00 90 00 03 00 00 03 00 00 80 00 +10: 00 00 20 e4 a1 50 00 00 08 00 00 d0 00 00 30 e4 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 1a 20 +30: 00 00 00 00 90 00 00 00 00 00 00 00 0b 01 00 00 +40: 00 00 00 00 48 00 00 00 09 00 09 51 02 04 0a 90 +50: 0e 00 30 00 19 00 00 00 00 00 00 00 00 00 80 7f +60: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 05 d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 01 00 22 00 00 00 00 00 00 00 00 00 00 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 03 00 64 34 ff 00 00 00 86 0f 05 00 00 00 00 00 + +00:02.1 Display controller [0380]: Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller [8086:27a6] (rev 03) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:201a] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited + ExtTag- RBE- FLReset- + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #0, PowerLimit 0.000W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg+ + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- + Changed: MRL- PresDet- LinkState+ + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 4191 + Capabilities: [90] Subsystem: Intel Corporation NM10/ICH7 Family PCI Express Port 1 [8086:27d0] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=01 ComponentID=00 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c001 + Kernel driver in use: pcieport +00: 86 80 d0 27 07 05 10 00 02 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 01 01 00 40 40 00 00 +20: 10 e4 10 e4 01 80 11 80 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 06 00 +40: 10 80 41 01 c0 0f 00 00 00 00 10 00 11 2c 11 01 +50: 40 00 11 30 60 00 00 00 38 10 40 01 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe 91 41 00 00 00 00 00 00 +90: 0d a0 00 00 86 80 d0 27 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 80 00 11 00 00 00 00 00 +e0: 0e 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1c.1 PCI bridge [0604]: Intel Corporation NM10/ICH7 Family PCI Express Port 2 [8086:27d2] (rev 02) (prog-if 00 [Normal decode]) + Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot-), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited + ExtTag- RBE- FLReset- + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41b1 + Capabilities: [90] Subsystem: Intel Corporation NM10/ICH7 Family PCI Express Port 2 [8086:27d2] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=02 ComponentID=00 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c001 + Kernel driver in use: pcieport +00: 86 80 d2 27 04 05 10 00 02 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 02 02 00 f0 00 00 20 +20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 02 06 00 +40: 10 80 41 00 c0 0f 00 00 00 00 10 00 11 2c 11 02 +50: 40 00 01 10 60 00 00 00 00 00 40 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe b1 41 00 00 00 00 00 00 +90: 0d a0 00 00 86 80 d2 27 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 80 00 11 00 00 00 00 00 +e0: 0e 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1c.2 PCI bridge [0604]: Intel Corporation NM10/ICH7 Family PCI Express Port 3 [8086:27d4] (rev 02) (prog-if 00 [Normal decode]) + Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot-), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited + ExtTag- RBE- FLReset- + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #3, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41d1 + Capabilities: [90] Subsystem: Device [0000:0000] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=03 ComponentID=00 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c001 + Kernel driver in use: pcieport +00: 86 80 d4 27 04 04 10 00 02 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 03 03 00 f0 00 00 20 +20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 03 06 00 +40: 10 80 41 00 c0 0f 00 00 00 00 10 00 11 2c 11 03 +50: 40 00 01 10 60 00 00 00 00 00 40 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe d1 41 00 00 00 00 00 00 +90: 0d a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 80 00 11 00 00 00 00 00 +e0: 0e 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1c.3 PCI bridge [0604]: Intel Corporation NM10/ICH7 Family PCI Express Port 4 [8086:27d6] (rev 02) (prog-if 00 [Normal decode]) + Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot-), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited + ExtTag- RBE- FLReset- + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 4122 + Capabilities: [90] Subsystem: Device [0000:0000] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=04 ComponentID=00 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c001 + Kernel driver in use: pcieport +00: 86 80 d6 27 04 04 10 00 02 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 04 04 00 f0 00 00 20 +20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 06 00 +40: 10 80 41 00 c0 0f 00 00 00 00 10 00 11 2c 11 04 +50: 40 00 01 10 60 00 00 00 00 00 40 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +90: 0d a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 80 00 11 00 00 00 00 00 +e0: 0e 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1d.0 USB controller [0c03]: Intel Corporation NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8] (rev 02) (prog-if 00 [UHCI]) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:200a] + Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [50] Subsystem: Device [0000:0000] +00: 86 80 48 24 07 00 10 00 e2 01 04 06 00 00 01 00 +10: 00 00 00 00 00 00 00 00 00 05 06 20 20 30 80 22 +20: 00 e0 00 e2 11 e2 01 e4 00 00 00 00 00 00 00 00 +30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 06 00 +40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00 +50: 0d 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1f.0 ISA bridge [0601]: Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9] (rev 02) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:2009] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- + Kernel driver in use: lpc_ich +00: 86 80 b9 27 07 00 10 02 02 00 01 06 00 00 80 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 09 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 05 00 00 80 00 00 00 81 04 00 00 10 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 80 80 80 80 d0 00 00 00 80 80 80 80 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 10 02 0d 1f 01 16 7c 00 e1 15 0c 00 81 16 1c 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: ac 06 00 00 30 00 00 00 13 1c 0a 00 00 03 00 00 +b0: 00 00 f0 00 00 00 00 00 00 00 02 0a 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 33 22 11 00 67 45 00 00 cf ff 00 00 08 00 00 00 +e0: 09 00 0c 10 b4 02 24 17 00 00 00 00 00 00 00 00 +f0: 01 c0 d1 fe 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1f.1 IDE interface [0101]: Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df] (rev 02) (prog-if 8a [Master SecP PriP]) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:200c] + Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- Reset- 16bInt+ PostWrite+ + 16-bit legacy interface ports at 0001 + Kernel driver in use: yenta_cardbus +00: 80 11 76 04 07 00 10 02 b4 00 07 06 00 a8 82 00 +10: 00 00 00 e2 dc 00 00 02 05 06 06 b0 00 00 00 84 +20: 00 f0 ff 87 00 00 00 88 00 f0 ff 8b 00 20 00 00 +30: fc 20 00 00 00 24 00 00 fc 24 00 00 0b 01 83 05 +40: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 01 00 a0 00 00 03 00 00 63 04 63 04 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 b2 00 30 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 0a fe +e0: 00 40 c0 24 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +05:00.1 FireWire (IEEE 1394) [0c00]: Ricoh Co Ltd R5C552 IEEE 1394 Controller [1180:0552] (rev 09) (prog-if 10 [OHCI]) + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- + Kernel driver in use: agpgart-intel +00: 86 80 a0 27 06 00 90 20 03 00 00 06 00 00 00 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 17 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 90 d1 fe 01 40 d1 fe 05 00 00 f0 01 80 d1 fe +50: 00 00 30 00 19 00 00 00 00 00 00 00 00 00 00 00 +60: 01 30 d1 fe 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 30 33 33 33 33 33 33 00 ff 03 00 00 80 1a 38 00 +a0: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 be ba fe ca +e0: 09 00 09 51 02 04 0a 90 0e 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 05 00 10 00 00 00 + +00:02.0 VGA compatible controller [0300]: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller [8086:27a2] (rev 03) (prog-if 00 [VGA controller]) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:201a] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- [disabled] + Capabilities: [90] MSI: Enable- Count=1/1 Maskable- 64bit- + Address: 00000000 Data: 0000 + Capabilities: [d0] Power Management version 2 + Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Kernel driver in use: i915 +00: 86 80 a2 27 07 00 90 00 03 00 00 03 00 00 80 00 +10: 00 00 20 e4 a1 50 00 00 08 00 00 d0 00 00 30 e4 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 1a 20 +30: 00 00 00 00 90 00 00 00 00 00 00 00 0b 01 00 00 +40: 00 00 00 00 48 00 00 00 09 00 09 51 02 04 0a 90 +50: 0e 00 30 00 19 00 00 00 00 00 00 00 00 00 80 7f +60: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 05 d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 01 00 22 00 00 00 00 00 00 00 00 00 00 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 03 00 64 34 ff 00 00 00 86 0f 05 00 00 00 00 00 + +00:02.1 Display controller [0380]: Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller [8086:27a6] (rev 03) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:201a] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited + ExtTag- RBE- FLReset- + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #0, PowerLimit 0.000W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg+ + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- + Changed: MRL- PresDet- LinkState+ + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 4191 + Capabilities: [90] Subsystem: Intel Corporation NM10/ICH7 Family PCI Express Port 1 [8086:27d0] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=01 ComponentID=00 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c001 + Kernel driver in use: pcieport +00: 86 80 d0 27 07 05 10 00 02 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 01 01 00 40 40 00 00 +20: 10 e4 10 e4 01 80 11 80 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 06 00 +40: 10 80 41 01 c0 0f 00 00 00 00 10 00 11 2c 11 01 +50: 40 00 11 30 60 00 00 00 38 10 40 01 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe 91 41 00 00 00 00 00 00 +90: 0d a0 00 00 86 80 d0 27 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 80 00 11 00 00 00 00 00 +e0: 0e 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1c.1 PCI bridge [0604]: Intel Corporation NM10/ICH7 Family PCI Express Port 2 [8086:27d2] (rev 02) (prog-if 00 [Normal decode]) + Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot-), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited + ExtTag- RBE- FLReset- + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41b1 + Capabilities: [90] Subsystem: Intel Corporation NM10/ICH7 Family PCI Express Port 2 [8086:27d2] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=02 ComponentID=00 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c001 + Kernel driver in use: pcieport +00: 86 80 d2 27 04 05 10 00 02 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 02 02 00 f0 00 00 20 +20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 02 06 00 +40: 10 80 41 00 c0 0f 00 00 00 00 10 00 11 2c 11 02 +50: 40 00 01 10 60 00 00 00 00 00 40 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe b1 41 00 00 00 00 00 00 +90: 0d a0 00 00 86 80 d2 27 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 80 00 11 00 00 00 00 00 +e0: 0e 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1c.2 PCI bridge [0604]: Intel Corporation NM10/ICH7 Family PCI Express Port 3 [8086:27d4] (rev 02) (prog-if 00 [Normal decode]) + Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot-), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited + ExtTag- RBE- FLReset- + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #3, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41d1 + Capabilities: [90] Subsystem: Device [0000:0000] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=03 ComponentID=00 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c001 + Kernel driver in use: pcieport +00: 86 80 d4 27 04 04 10 00 02 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 03 03 00 f0 00 00 20 +20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 03 06 00 +40: 10 80 41 00 c0 0f 00 00 00 00 10 00 11 2c 11 03 +50: 40 00 01 10 60 00 00 00 00 00 40 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe d1 41 00 00 00 00 00 00 +90: 0d a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 80 00 11 00 00 00 00 00 +e0: 0e 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1c.3 PCI bridge [0604]: Intel Corporation NM10/ICH7 Family PCI Express Port 4 [8086:27d6] (rev 02) (prog-if 00 [Normal decode]) + Control: I/O- Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot-), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited + ExtTag- RBE- FLReset- + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 4122 + Capabilities: [90] Subsystem: Device [0000:0000] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=04 ComponentID=00 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=00 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c001 + Kernel driver in use: pcieport +00: 86 80 d6 27 04 04 10 00 02 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 04 04 00 f0 00 00 20 +20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 06 00 +40: 10 80 41 00 c0 0f 00 00 00 00 10 00 11 2c 11 04 +50: 40 00 01 10 60 00 00 00 00 00 40 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +90: 0d a0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 80 00 11 00 00 00 00 00 +e0: 0e 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1d.0 USB controller [0c03]: Intel Corporation NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8] (rev 02) (prog-if 00 [UHCI]) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:200a] + Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [50] Subsystem: Device [0000:0000] +00: 86 80 48 24 07 00 10 00 e2 01 04 06 00 00 01 00 +10: 00 00 00 00 00 00 00 00 00 05 06 20 20 30 80 22 +20: 00 e0 00 e2 11 e2 01 e4 00 00 00 00 00 00 00 00 +30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 06 00 +40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00 +50: 0d 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1f.0 ISA bridge [0601]: Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9] (rev 02) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:2009] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- + Kernel driver in use: lpc_ich +00: 86 80 b9 27 07 00 10 02 02 00 01 06 00 00 80 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 09 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 05 00 00 80 00 00 00 81 04 00 00 10 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 80 80 80 80 d0 00 00 00 80 80 80 80 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 10 02 0d 1f 01 16 7c 00 e1 15 0c 00 81 16 1c 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: ac 06 00 00 30 00 00 00 13 1c 0a 00 00 03 00 00 +b0: 00 00 f0 00 00 00 00 00 00 00 02 0a 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 33 22 11 00 67 45 00 00 cf ff 00 00 08 00 00 00 +e0: 09 00 0c 10 b4 02 24 17 00 00 00 00 00 00 00 00 +f0: 01 c0 d1 fe 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1f.1 IDE interface [0101]: Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df] (rev 02) (prog-if 8a [Master SecP PriP]) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:200c] + Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- Reset- 16bInt+ PostWrite+ + 16-bit legacy interface ports at 0001 + Kernel driver in use: yenta_cardbus +00: 80 11 76 04 07 00 10 02 b4 00 07 06 00 a8 82 00 +10: 00 00 00 e2 dc 00 00 02 05 06 06 b0 00 00 00 84 +20: 00 f0 ff 87 00 00 00 88 00 f0 ff 8b 00 20 00 00 +30: fc 20 00 00 00 24 00 00 fc 24 00 00 0b 01 83 05 +40: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 01 00 a0 00 00 03 00 00 63 04 63 04 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 b2 00 30 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 0a fe +e0: 00 40 c0 24 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +05:00.1 FireWire (IEEE 1394) [0c00]: Ricoh Co Ltd R5C552 IEEE 1394 Controller [1180:0552] (rev 09) (prog-if 10 [OHCI]) + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- + Kernel driver in use: agpgart-intel +00: 86 80 a0 27 06 01 90 20 03 00 00 06 00 00 00 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 17 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 90 d1 fe 01 40 d1 fe 05 00 00 f0 01 80 d1 fe +50: 00 00 30 00 19 00 00 00 00 00 00 00 00 00 00 00 +60: 01 00 20 80 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 10 11 11 01 30 11 11 00 ff 03 00 00 80 1a 39 00 +a0: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 04 01 00 00 +e0: 09 00 09 51 02 04 0a 90 0e 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 05 00 10 00 00 00 + +00:02.0 VGA compatible controller [0300]: Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller [8086:27a2] (rev 03) (prog-if 00 [VGA controller]) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:201a] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- [disabled] + Capabilities: [90] MSI: Enable- Count=1/1 Maskable- 64bit- + Address: 00000000 Data: 0000 + Capabilities: [d0] Power Management version 2 + Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Kernel driver in use: i915 +00: 86 80 a2 27 07 00 90 00 03 00 00 03 00 00 80 00 +10: 00 00 10 ee 01 18 00 00 08 00 00 d0 00 00 20 ee +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 1a 20 +30: 00 00 00 00 90 00 00 00 00 00 00 00 0b 01 00 00 +40: 00 00 00 00 48 00 00 00 09 00 09 51 02 04 0a 90 +50: 0e 00 30 00 19 00 00 00 00 00 00 00 00 00 80 7f +60: 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 05 d0 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 01 00 22 00 00 00 00 00 00 00 00 00 00 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 03 00 64 34 b2 00 00 00 86 0f 05 00 00 00 00 00 + +00:02.1 Display controller [0380]: Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller [8086:27a6] (rev 03) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:201a] + Control: I/O+ Mem+ BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited + ExtTag- RBE- FLReset- + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <256ns, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #2, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg+ + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- + Changed: MRL- PresDet- LinkState+ + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 4191 + Capabilities: [90] Subsystem: Lenovo Device [17aa:2011] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=01 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c001 + Kernel driver in use: pcieport +00: 86 80 d0 27 07 05 10 00 02 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 02 02 00 20 20 00 20 +20: 00 ee 00 ee 01 80 11 80 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 04 00 +40: 10 80 41 01 c0 0f 00 00 00 00 10 00 11 2c 11 01 +50: 40 00 11 30 e0 a0 10 00 38 10 40 01 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe 91 41 00 00 00 00 00 00 +90: 0d a0 00 00 aa 17 11 20 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 80 00 11 80 00 00 00 00 +e0: 00 0f c7 00 06 07 08 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1c.1 PCI bridge [0604]: Intel Corporation NM10/ICH7 Family PCI Express Port 2 [8086:27d2] (rev 02) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited + ExtTag- RBE- FLReset- + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #3, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg+ + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- + Changed: MRL- PresDet- LinkState- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41b1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:2011] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff + Status: NegoPending- InProgress- + VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=02 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c001 + Kernel driver in use: pcieport +00: 86 80 d2 27 07 05 10 00 02 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 03 03 00 30 40 00 20 +20: 00 e8 f0 e9 01 e4 01 e4 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 02 04 00 +40: 10 80 41 01 c0 0f 00 00 00 00 10 00 11 4c 11 02 +50: 00 00 01 10 e0 a0 18 00 38 10 00 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe b1 41 00 00 00 00 00 00 +90: 0d a0 00 00 aa 17 11 20 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 80 00 11 00 00 00 00 00 +e0: 00 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1c.2 PCI bridge [0604]: Intel Corporation NM10/ICH7 Family PCI Express Port 3 [8086:27d4] (rev 02) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited + ExtTag- RBE- FLReset- + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #3, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #4, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg+ + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- + Changed: MRL- PresDet- LinkState- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41d1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:2011] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff + Status: NegoPending- InProgress- + VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=03 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c001 + Kernel driver in use: pcieport +00: 86 80 d4 27 07 05 10 00 02 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 04 0b 00 50 60 00 20 +20: 00 ea f0 eb 11 e4 11 e4 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 03 04 00 +40: 10 80 41 01 c0 0f 00 00 00 00 10 00 11 4c 11 03 +50: 00 00 01 10 e0 a0 20 00 38 10 00 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe d1 41 00 00 00 00 00 00 +90: 0d a0 00 00 aa 17 11 20 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 80 00 11 00 00 00 00 00 +e0: 00 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1c.3 PCI bridge [0604]: Intel Corporation NM10/ICH7 Family PCI Express Port 4 [8086:27d6] (rev 02) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s unlimited, L1 unlimited + ExtTag- RBE- FLReset- + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Latency L0 <1us, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- Retrain- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #5, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg+ + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- + Changed: MRL- PresDet- LinkState- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 4122 + Capabilities: [90] Subsystem: Lenovo Device [17aa:2011] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff + Status: NegoPending- InProgress- + VC1: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable- ID=0 ArbSelect=Fixed TC/VC=00 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=04 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c001 + Kernel driver in use: pcieport +00: 86 80 d6 27 07 05 10 00 02 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 0c 13 00 70 80 00 20 +20: 00 ec f0 ed 21 e4 21 e4 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 04 00 +40: 10 80 41 01 c0 0f 00 00 00 00 10 00 11 4c 11 04 +50: 00 00 01 10 e0 a0 28 00 38 10 00 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe 22 41 00 00 00 00 00 00 +90: 0d a0 00 00 aa 17 11 20 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 80 00 11 00 00 00 00 00 +e0: 00 00 c7 00 06 07 08 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1d.0 USB controller [0c03]: Intel Corporation NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8] (rev 02) (prog-if 00 [UHCI]) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:200a] + Control: I/O+ Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [50] Subsystem: Lenovo Device [17aa:2013] +00: 86 80 48 24 07 00 10 00 e2 01 04 06 00 00 01 00 +10: 00 00 00 00 00 00 00 00 00 15 18 20 90 c0 80 22 +20: 30 e4 f0 e7 01 e0 f1 e3 00 00 00 00 00 00 00 00 +30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 00 00 +40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00 +50: 0d 00 00 00 aa 17 13 20 00 00 00 00 00 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1f.0 ISA bridge [0601]: Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9] (rev 02) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:2009] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- + Kernel driver in use: lpc_ich +00: 86 80 b9 27 07 00 10 02 02 00 01 06 00 00 80 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 09 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 10 00 00 80 00 00 00 81 11 00 00 10 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 8b 8b 8b 8b 92 00 00 00 8b 8b 8b 8b 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 10 02 0e 1f 01 16 7c 00 e1 15 0c 00 81 16 1c 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 24 02 00 00 30 00 00 00 13 1c 0a 02 00 03 00 00 +b0: 00 00 f0 00 00 00 00 00 00 00 02 0a 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 44 12 11 00 67 45 00 00 c0 ff 00 00 01 00 00 00 +e0: 09 00 0c 10 b4 02 24 17 00 00 00 00 00 00 00 00 +f0: 01 c0 d1 fe 00 00 00 00 86 0f 02 00 00 00 00 00 + +00:1f.1 IDE interface [0101]: Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df] (rev 02) (prog-if 8a [Master SecP PriP]) + Subsystem: Lenovo ThinkPad T60/R60 series [17aa:200c] + Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap- 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- Reset- 16bInt+ PostWrite+ + 16-bit legacy interface ports at 0001 + Kernel driver in use: yenta_cardbus +00: 80 11 76 04 07 00 10 02 b4 00 07 06 00 a8 82 00 +10: 00 00 30 e4 dc 00 00 02 15 16 17 b0 00 00 00 e0 +20: 00 f0 ff e3 00 00 00 f4 00 f0 ff f7 00 90 00 00 +30: fc 90 00 00 00 94 00 00 fc 94 00 00 0b 01 80 05 +40: aa 17 1c 20 01 00 00 00 00 00 00 00 00 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 01 00 a0 04 00 03 00 00 63 04 63 04 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 00 00 00 f0 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 b2 00 30 00 00 00 00 00 00 +c0: aa 17 1c 20 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 0a fe +e0: 00 40 c0 24 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +15:00.1 FireWire (IEEE 1394) [0c00]: Ricoh Co Ltd R5C552 IEEE 1394 Controller [1180:0552] (rev 09) (prog-if 10 [OHCI]) + Subsystem: Lenovo ThinkPad X60s [17aa:201e] + Physical Slot: 1 + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- I documented it + but I should update the page + somehow it works without any but one of my extra patches + but it has 1 small issue + GNUtoo-irssi: do you need review on those? I think that sth like it could save me countless external reflashs + phcoder-1creen: well, most of them are unnecessary now + 1 patch is usefull only for improving code readability of existing coreboot code + 1 patch is only changing the reboot count of the fallback mecanism + beside that I see nothing remaining + but I can check again + I have to do it now + The documentation is on the wiki + caveats: + 1) sometimes the x60 reboots twice, + for instance if you run poweroff, then let it power down, and as soon as it seems powered down, you press the power button + in that case it will do a reset + 2) suspend/resume and userspace needs some handling, I've systemd units for booting only, but not for suspend/resume + but you can do it by hand + config MAX_REBOOT_CNT + int + default 1 + that's what I added in src/mainboard/lenovo/x60/Kconfig + before I had a patch to make it selectable it in Kconfig, + that is to say the user enter the max reboot count he wants + I think the global default is 3 + Then I've some other interesting patches + I wonder if they're acceptable + one patch is for adding etc/grub.cfg from Kconfig + Use case: the user builds once, he do ./build/cbfstool ./build/coreboot.rom add -n etc/grub.cfg -f grub.cfg -t raw + but he re-do make + and forgett to re-add grub.cfg + it's just a convenience + (he could do it with a script too) + *he/she + I guess the user is a she in english? + en french it's a he + I've also a flashrom patch to submit + phcoder-1creen: "it could save me countless external reflashs" => that was exactly my use case + There are some other interesting stuff that could extend the use case: + there is a flash log for the chromebooks + example use case: you go to a conference in the USA, you are in the plane + you then continue developing there, you reflash etc... + but then you need the log of the failed boot somehow + the flash log (which is in coreboot but require CONFIG_CHROMEOS or something like that) could help with that second use case + Else the logs in RAM + a watchdog could also do the trick + *hardware watchdog + so that second approach of the second use case would just require some modifications related to cbmem + they may already be there, because I'm way out of the loop + I'll make a list of the interesting patches I have locally + and look at gerrit too + btw, is there some easy infrastructure work to do? + like something that can be done on the side +* ttyS3 has quit (Ping timeout: 264 seconds) + The x60[s/t], T60(with intel GPUs), are mostly complete, the main issue remaining is merging that improved GPU init code + fallback/ is mostly merged but that one patch I was talking about + then I guess the ACPI part was merged + I'm unsure about the IRDA + I mostly test on x60t nowadays + (my t60 has a nasty bug with ctrl+d, probably ec related) + I've also to look about the security of the I/Os + (like what's on the dock connector) + there is also the license issue of the microcodes inside the headers + I'll add all that in the wiki + GNUtoo-irssi: did you test digitizer? + yes + works well with libreboot 6 beta3 patches on top of coreboot git + I use it often + with xournal mainly + I've been in a local shop and I've found a compatilble wacom pen: it has: + touch, button(right click), eraser + all do work + the pen is not the x60 pen, but it does work fine + digitizer patches are already in + The screen's directional keys the its middle key work + yes + I'll update soon + I'll probably sumarize the patch I've left in the wiki + and update that fallback page + phcoder-1creen: is the IRDA supposed to work? + GNUtoo-irssi: 5243 + T60, rght? +* KidBeta has quit (Quit: My MacBook Pro has gone to sleep. ZZZzzz…) + x60 and x60t + oops + x60t and t60 + I'll test them together, I was trying lirc instead directlyt + 5242 for X60 + ok + thanks + GNUtoo-irssi: did you see x200 port? + yes + what CPU is it? + and what chipset? + gm45. Intel GPU + ok + I've looked at your new ports and related, + it probably cover the chipset I have in my N71JQ + but I probably don't have time to do the port anytime soon + gm45 was already covered by rk9 + yes + it's core 2 duo with the first AMT in the NICs, right? + and 64bit? + it's 64bit. I can't tell anything about AMT. + so I guess that if someone unsolder his nic firmware flash, the AMT is gone? + ok + if so that's probably a good tradeoff + you get more recent laptops at the cost of unsoldering or blanking the NIC's flash + ME firmware is in the flash chip. There is information that on gm45 you can remove ME firmware without any consequences but I din't really try + assuming it's like with the old i945 laptops + ok, wow, nice + how fast is it in between the T60's and the Nehalem's laptops(x201) + roda rk9 runs without ME firmware AFACIT + ok + about roda and so on, there isn't a lot of infos on the rugged laptops + I guess that nobody still test on them + No. But the list of connectors they have is truly impressive. As is battery capacity and heaviness. + indeed + it probably has lot of interesting peripherals too, like GPS, 3g modem(how is it connected?) and so on + for the heavyness, it's a way to make geeks become like rambo? + s/geeks/geeks and nerds + 3g modems are optional. I guess it's minipcie slot. + BTW x200 has 3 minipcie slots + wow + (not counting exprecsscard) + ok + that permits to have 2 wifi cards... + if driver can handle it, sure. When I tried with 2 intel cards, intel drivers and networkmanager got confused. + (ath9k/ath5k have some difficulties when creating multiples interfaces when WPA is involved) + ok + 3rd minipcie was intended for UWB. + well, I have multiples cards easily here + I never had a problem with non-intel cards + network manager will still get confused + example: ath9k + ath9k_htc => both interfaces appear in kde's network manager GUI + it was getting confused with intel cards and rfkill + (and I lacked the fimrware of the intel cards...so that added to the confusion) + Example use case: connect to 2 different AP on 2 different networks + yes network manager and multiple cards and rfkill resultsin confusion + my ath9k_htc is usb + so no hardware rfkill + btw, the mini-pcie connectors do export only pci? + do they export usb, and sata? + (and some other pins for rfkill, SIM card, and so on) + + + + + + + + ok + well, I must update the instructions + I was going trough the list of patches I had first + yes + but to a specific/personal page + could you link me to the updated instructions? (when done) + well, I'll update them first + I was going trough my patches list before that + so I'll do that now + So I gather that you basically reset the counter yourself after you boot (after typing grub password) + and so, if you boot and the counter is higher, you know if someone tried to use it + yes, my systemd unit does it + *resets it + so it works like that: + the bootblock switch from normal/ to fallback if the counter is > CONFIG_MAX_REBOOT_CNT + if no normal/ is there it also switch to fallback/ + and then it increments the counter + (it's badly explained by me but you get the idea) + then my systemd units reset the counter to 0 once it's fully booted + that way if it fails, let's say at booting any linux kernel, then the user won't have bricked the laptop + (and the developer will have saved lot of time) + the issue is that I didn't reset the counter at resume + I should look how + but at least that makes it developer friendly if the user don't have suspend-resume covered yet + testing images is then a lot faster + and for "production", only fallback/ populated, but with the mecanism in place + that way he can test normal/ easily + + + + + diff --git a/i18n/fr_FR/docs/git/index.md b/i18n/fr_FR/docs/git/index.md new file mode 100644 index 00000000..6aeb5d3b --- /dev/null +++ b/i18n/fr_FR/docs/git/index.md @@ -0,0 +1,320 @@ +--- +title: Instructions pour la compilation du code source +x-toc-enable: true +... + +Depthcharge est actuellement non documenté depuis qu'il est dans le nouveau système de construction. +Les instructions sur comment construire des cartes mères qui ont depthcharg sont incluses dans le fichier BUILD\_HOWTO sur libreboot.git ou \_src. + +Cette section concerne la construction de libreboot depuis la source, et travailler avec le répertoire git. + + +Installer les dépendances de construction +========================== + +Afin de faire quoi que soit, vous avez besoin des dépendances en premier. C'est vrai si vous voulez construire libreboot depuis la source, que ce soit avec libreboot\_src.tar.xz ou git. *Si vous utilisez libreboot\_util.tar.xz (archive binaire) alors vous pouvez ignorer celà, parce que les images ROM et les exécutables compilés statiquement pour les utilitaires sont inclus.* + +Pour Debian Stretch (pourrait aussi marcher avec Debian Jessie), vous pouvez exécuter la commande suivante: + + $ sudo ./oldbuild dependencies debian + +(celà marchera aussi dans Devuan) + +Pour Parabola, vous pouvez exécuter la commande suivante: + + $ sudo ./oldbuild dependencies parabola\ + +ou: + + # ./oldbuild dependencies parabola + +Pour les autres distributions GNU+Linux, vous pouvez adapter les scripts existants. + + +Récupérer le code source complet depuis les métadonnées (git clon) +================================================== + +Si vous avez téléchargé Libreboot depuis git, alors il y a quelques étapes pour télécharger et patcher le code source pour toutes les dépendances importantes. L'archive dans le répertoire git était disponible en tant qu'une tarball nommée 'libreboot\_meta.tar.gz'. +Elle contient des 'métadonnées' (scripts) qui définissent comment la source a été créée (d'où est-ce qu'elle est venue). + +Vous pouvez utiliser les scripts inclus pour tout télécharger. + +En premier, [installer les dépendances de constructions](#dependances_de_build). + +Depuis que libreboot fait une utilisation extensive, vous avez besoin de configurer git correctement. +Si vous n'avez pas encore configuré git, alors les exigences minimales sont: + + $ git config --global user.name "Your name" + $ git config --global user.email your@emailadress.com + +C'est ce qui apparaitra aussi dans les logs de git si jamais vous commitez vos propres changements dans un répertoire donné . Pour plus d'informations, regardez + +Une autre bonne config pour vous (optionnelle, mais recommandée) : + + $ git config --global core.editor nano + $ git config --global color.status auto + $ git config --global color.branch auto + $ git config --global color.interactive auto + $ git config --global color.diff + +Après cela, exécutez le script: + + $ ./download all + +Ce que cela a fait est de tout télécharger (grub, coreboot, memtest86+, bucts, flashrom) des versions dernièrement testé pour cette publication, et les patchs. Lisez le script dans un éditeur de texte pour en apprendre plus. + +Pour construire les images ROM, regardez [\#build](#build) + + +Comment construire des "bucts" (pour LenovoBIOS X60/X60S/X60T/T60) +========================================================= + +*Ceci est pour les utilisateurs du BIOS de Lenovo sur le ThinkPad X60/X60S, Tablette X60 et T60. Si vous exécutez déjà coreboot et libreboot, ignorez cela* + +BUC.TS n'est pas réellement spécifique à ces ordinateurs portables, mais c'est un bit dans le registre dans le jeu de puces (chipset) sur certains systèmes Intel. + +Bucts est nécessaire lors du flashage de logiciel sur la X60/X60S/X60T/T60 ROM pendant que le BIOS Lenovo s'exécute; hors de ça le flashage externe sera sans danger + +Chaque ROM contient des données identiques à l'intérieur des deux régions finales de 64K dans le fichier \*. Cela correspond aux deux regions finales de 64K dans la puce flash. +Le BIOS de Lenovo vous empêchera d'écrire la dernière région, donc exécuter `bucts 1` paramètrera le système pour démarrer sur l'autre bloc (qui est écrivable ainsi tout en dessous quand vous utilisez une flashrom patchée. Regardez [\#build\_flashrom](#build_flashrom )). +Après l'arrêt et le démarrage après le premier flash de lireboot, le bloc final de 64K est écrivable donc vous pouvez encore flasher la ROM avec une flashrom non patchée et exécuter `butcs 0` pour faire encore démarrer le système du bloc normal (le plus haut). + + +\*Les images de ROM Libreboot ont des données identiques dans ces deux régions de 64Ko car dd est utilisé pour faire ça par l'intermédiaire du système de construction. +Si vous contruisez depuis l'amont (coreboot), vous devez le faire manuellement. + +BUC.TS est soutenu (alimenté) par la batterie NVRAM (ou la batterie CMOS, comme certaines personnes l'appelent). +Sur les thinkpads, c'est typiquement dans un paquet en plastique jaune avec la batterie à l'intérieur, connecté via les lignes électriques à la carte mère. +Enlever cette batterie enlève l'alimentation au BUC.TS, réinitialisant le bit à 0 (si vous l'avez mis précédemment à 1). + +L'utilitaire BUC.TS est inclus dans libreboot\_src.tar.xz et libreboot\_util.tar.xz. + +Si vous avez téléchargé depuis git, suivez la [\#build\_meta](#build_meta) avant de procéder. + +*BUC* signifie "*B*ack*u*p *C*ontrol" (c'est un registre) et "TS" signifie *T*op *S*wap" (c'est un bit de status). +D'où le nom "bucts" (BUC.TS). TS 1 et TS 0 correspondent à bucts 1 et bucts 0. + + +If you downloaded from git, follow [\#build\_meta](#build_meta) before +you proceed. + +"BUC" means "*B*ack*u*p *C*ontrol" (it's a register) and +"TS" means "*T*op *S*wap" (it's a status bit). Hence "bucts" +(BUC.TS). TS 1 and TS 0 corresponds to bucts 1 and bucts 0. + +Si vous avez l'archive de publications des binaires, vous trouverez des exécutables en dessous ./bucts/. Sinon si vous avez besoin de construire depuis la source, continuez à lire. + +Premièrement, [installez les dépendances de constructions](#build_dependencies). + +Pour construire les ducts, faîtes ceci dans le répertoire principal: + + $ ./oldbuild module bucts + +Pour le compiler statiquement, faîtes ceci: + + $ ./oldbuild module bucts static + +Le script "builddeps" dans libreboot\_src fait aussi l'utlisation de builddeps-bucts. + + +How to build "flashrom" +========================= + +Flashrom is the utility for flashing/dumping ROM images. This is what +you will use to install libreboot. + +Flashrom source code is included in libreboot\_src.tar.xz and +libreboot\_util.tar.xz. + +*If you downloaded from git, follow [\#build\_meta](#build_meta) before +you proceed.* + +If you are using the binary release archive, then there are already +binaries included under ./flashrom/. The flashing scripts will try to +choose the correct one for you. Otherwise if you wish to re-build +flashrom from source, continue reading. + +First, [install the build dependencies](#build_dependencies). + +To build it, do the following in the main directory: + + $ ./oldbuild module flashrom + +To statically compile it, do the following in the main directory: + + $ ./oldbuild module flashrom static + +After you've done that, under ./flashrom/ you will find the following +executables: + +- `flashrom` + - For flashing while coreboot or libreboot is running. +- `flashrom_lenovobios_sst` + - This is patched for flashing while Lenovo BIOS is running on an + X60 or T60 with the SST25VF016B (SST) flash chip. +- `flashrom_lenovobios_macronix` + - This is patched for flashing while Lenovo BIOS is running on an + X60 or T60 with the MX25L1605D (Macronix) flash chip. + +The "builddeps" script in libreboot\_src also makes use of +builddeps-flashrom. + +How to build the ROM images +=========================== + +You don't need to do much, as there are scripts already written for you +that can build everything automatically. + +You can build libreboot from source on a 32-bit (i686) or 64-bit +(x86\_64) system. Recommended (if possible): x86\_64. ASUS KFSN4-DRE has +64-bit CPUs. On a ThinkPad T60, you can replace the CPU (Core 2 Duo +T5600, T7200 or T7600. T5600 recommended) for 64-bit support. On an +X60s, you can replace the board with one that has a Core 2 Duo L7400 +(you could also use an X60 Tablet board with the same CPU). On an X60, +you can replace the board with one that has a Core 2 Duo T5600 or T7200 +(T5600 is recommended). All MacBook2,1 laptops are 64-bit, as are all +ThinkPad X200, X200S, X200 Tablet, R400, T400 and T500 laptops. Warning: +MacBook1,1 laptops are all 32-bit only. + +First, [install the build dependencies](#build_dependencies). + +If you downloaded libreboot from git, refer to +[\#build\_meta](#build_meta). + +Build all of the components used in libreboot: + + $ ./oldbuild module all + +You can also build each modules separately, using *./oldbuild module +modulename*. To see the possible values for *modulename*, use: + + $ ./oldbuild module list + +After that, build the ROM images (for all boards): + + $ ./oldbuild roms withgrub + +Alternatively, you can build for a specific board or set of boards. For +example: + + $ ./oldbuild roms withgrub x60 + $ ./oldbuild roms withgrub x200_8mb + $ ./oldbuild roms withgrub x60 x200_8mb + +The list of board options can be found by looking at the directory names +in `resources/libreboot/config/grub/`. + +To clean (reverse) everything, do the following: + + $ ./oldbuild clean all + +The ROM images will be stored under `bin/payload/`, where `payload` +could be `grub`, `seabios`, or whatever other payload those images were +built for. + +Preparing release archives (optional) +------------------------------------- + +*This is only confirmed to work (tested) in Debian Stretch. Parabola fails at +this stage (for now). For all other distros, YMMV. This will also work in +Devuan.* + +This is mainly intended for use with the git repository. These commands +will work in the release archive (\_src), unless otherwise noted below. + +The archives will appear under *release/oldbuildsystem/\${version}/*; +\${version} will either be set using *git describe* or, if a *version* +file already exists (\_src release archive), then it will simply re-use +that. + +Tag the current commit, and that version will appear in both the +\${version} string on the directory under *release/oldbuildsystem/*, and +in the file names of the archives. Otherwise, whatever git uses for *git +describe --tags HEAD* will be used. + +Utilities (static executables): + + $ ./oldbuild release util + +Archive containing flashrom and bucts source code: + + $ ./oldbuild release tobuild + +Documentation archive (*does not work on \_src release archive, only +git*): + + $ ./oldbuild release docs + +ROM image archives: + + $ ./oldbuild release roms + +Source code archive: + + $ ./oldbuild release src + +SHA512 sums of all other release archives that have been generated: + + $ ./oldbuild release sha512sums + +If you are building on an i686 host, this will build statically linked +32-bit binaries in the binary release archive that you created, for: + + nvramtool, cbfstool, ich9deblob, cbmem + +If you are building on an x86\_64 host, this will build statically +linked 32- \*and\* 64-bit binaries for `cbmem`, `ich9deblob`, +`cbfstool` and `nvramtool`. + +*To include statically linked i686 and x86\_64 binaries for bucts and +flashrom, you will need to build them on a chroot, a virtual system or a +real system where the host uses each given architecture. These packages +are difficult to cross-compile, and the libreboot project is still +figuring out how to deal with them.* + +The same applies if you want to include statically linked flashrom +binaries for ARM. + +armv7l binaries (tested on a BeagleBone Black) are also included in +libreboot\_util, for: + +- cbfstool +- ich9gen +- ich9deblob +- flashrom + +If you are building binaries on a live system or chroot (for +flashrom/bucts), you can use the following to statically link them: + + $ ./oldbuild module flashrom static + $ ./oldbuild module bucts static + +The same conditions as above apply for ARM (except, building bucts on +ARM is pointless, and for flashrom you only need the normal executable +since the lenovobios\_sst and \_macronix executables are meant to run on +an X60/T60 while lenovo bios is present, working around the security +restrictions). + +The command that you used for generating the release archives will also +run the following command: + + $ ./oldbuild release tobuild + +The archive `tobuild.tar.xz` will have been created under +`release/oldbuildsystem/`, containing bucts, flashrom and all other +required resources for building them. + +You'll find that the files libreboot\_util.tar.xz and +libreboot\_src.tar.xz have been created, under +`release/oldbuildsystem/`. + +The ROM images will be stored in separate archives for each system, +under `release/oldbuildsystem/rom/`. + +Copyright © 2014, 2015, 2016 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/gnulinux/configuring_parabola.md b/i18n/fr_FR/docs/gnulinux/configuring_parabola.md new file mode 100644 index 00000000..935ff099 --- /dev/null +++ b/i18n/fr_FR/docs/gnulinux/configuring_parabola.md @@ -0,0 +1,526 @@ +--- +title: Configuring Parabola (Post-Install) +x-toc-enable: true +... + +This is the guide for setting up Parabola GNU+Linux-Libre, after completing +the installation steps outlined in [Installing Parabola or Arch GNU+Linux-Libre with Full-Disk Encryption (including /boot)](encrypted_parabola.md). +It will cover installing and configuring a graphical desktop environment, +as well as some applications that make the system more user friendly. + +For this example, we chose the *MATE Desktop Environment* as our graphical interface. + +*This guide was valid on 2017-06-02. If you see any changes that should +to be made at the present date, please get in touch with the Libreboot +project (or [make those changes yourself](https://libreboot.org/git.html#editing-the-website-and-documentation-wiki-style))!* + +While Parabola can seem daunting at first glance (especially for new GNU+Linux users), +with a simple guide, it can provide all the same usability +as any Debian-based GNU+Linux distribution (e.g., Trisquel, Debian, and Devuan), +without hiding any details from the user. + +Paradoxically, as you get more advanced, Parabola can actually become +*easier to use*, when you want to set up your system in a special way, +compared to what most distributions provide. You will find over time +that other distributions tend to *get in your way*. + +A lot of the steps in this guide will refer to ArchWiki. Arch is +the upstream distribution that Parabola uses. Most of this guide will +also tell you to read wiki articles, other pages, manuals, and so on. In +general, it tries to cherry-pick the most useful information, but +nonetheless, you are encouraged to learn as much as possible. + +**NOTE: It might take you a few days to fully install your system how you like, +depending on how much you need to read. Patience is key, especially for new users.** + +The ArchWiki will sometimes use bad language, such as calling the whole +system Linux, using the term **open-source**/**closed-source**, +and it will sometimes recommend the use of proprietary software. +You need to be careful about this when reading anything on ArchWiki. + +Some of these steps require internet access. To get initial access +for setting up the system (I'll go into networking later), +just connect your system to a router, via an ethernet cable, +and run the following command: + + # systemctl start dhcpcd.service + +You can stop it later (if needed), by using systemd's `stop` option: + + # systemctl stop dhcpcd.service + +For most people, this should be enough, but if you don't have DHCP enabled +on your network, then you should setup your network connection first: +[Set Up Network Connection in Parabola](#network). + +## Configure pacman +`pacman` (*pac*kage *man*ager) is the name of the package management system +in Arch, which Parabola (as a deblobbed, parallel effort) also uses. +Like with `apt-get` on Trisquel, Debian, or Devuan, this can be used to +add, remove, and update the software on your computer. + +For more information related to `pacman`, review the following articles on the Arch Wiki: + +* [Configuring pacman](https://wiki.parabolagnulinux.org/Installation_Guide#Configure_pacman) +* [Using pacman](https://wiki.archlinux.org/index.php/Pacman) +* [Additional Repositories](https://wiki.parabolagnulinux.org/Official_Repositories) + +## Updating Parabola +Parabola is kept up-to-date, using `pacman`. When you are updating Parabola, +make sure to refresh the package list, *before* installing any new updates: + + # pacman -Syy + +**NOTE: According to the Wiki,** `-Syy` **is better than** `-Sy` **, because it refreshes +the package list (even if it appears to be up-to-date), which can be useful +when switching to another mirror.** + +Then, actually update the system: + + # pacman -Syu + +**NOTE: Before installing packages with** `pacman -S`**, always update first, +using the two commands above.** + +Keep an eye out on the output, or read it in **/var/log/pacman.log**. +Sometimes, `pacman` will show messages about maintenance steps that you +will need to perform with certain files (typically configurations) after +the update. Also, you should check both the [Parabola home page](https://www.parabola.nu/) and [Arch home page](https://www.archlinux.org/), +to see if they mention any issues. If a new kernel is installed, you should also +update to be able to use it (the currently running kernel will also be fine). + +It's generally good enough to update Parabola once every week, or maybe twice. +As a rolling release distribution, it's a never a good idea to leave your installation +too outdated. This is simply because of the way the project works; +old packages are deleted from the repositories quickly, once they are updated. +A system that hasn't been updated for quite a while will mean potentially more +reading of previous posts through the website, and more maintenance work. + +The Arch forum can also be useful, if others have the same issue as you. +The *Parabola* IRC channel ([**\#parabola**](https://webchat.freenode.net/) on freenode) can also help you. + +Due to this, and the volatile nature of Parabola/Arch, you should only +update when you have at least a couple hours of spare time, in case of +issues that need to be resolved. You should never update, for example, +if you need your system for an important event, like a presentation, or +sending an email to an important person before an allocated deadline, +and so on. + +Relax! Packages are well-tested, when new updates are made to +the repositories; separate 'testing' repositories exist for this exact +reason. Despite what many people may tell you, Parabola is fairly +stable and trouble-free, so long as you are aware of how to check for +issues, and are willing to spend some time fixing issues, in the rare +event that they do occur (this is why Arch/Parabola provide such extensive documenatation). + +## Maintaining Parabola +Parabola is a very simple distro, in the sense that you are in full +control, and everything is made transparent to you. One consequence is +that you also need to know what you are doing, and what you have done +before. In general, keeping notes (such as what I have done with this +page) can be very useful as a reference in the future (e.g, if you wanted to +re-install it, or install the distro on another computer). + +You should also read the ArchWiki article on [System Maintenance](https://wiki.archlinux.org/index.php/System_maintenance), +before continuing. Also, read their article on [enhancing system stability](https://wiki.archlinux.org/index.php/Enhance_system_stability). +This is important, so make sure to read them both!* + +Install `smartmontools`; it can be used to check smart data. HDDs use +non-free firmware inside; it's transparent to you, but the smart +data comes from it. Therefore, don't rely on it too much), and then read +the ArchWiki [article](https://wiki.archlinux.org/index.php/S.M.A.R.T.) on it, to learn how to use it: + + # pacman -S smartmontools + +### Cleaning the Package Cache +*This section provides a brief overview of how to manage the directory that stores +a cache of all downloaded packages. For more information, +check out the Arch Wiki guide for [Cleaning the Package Cache](https://wiki.archlinux.org/index.php/Pacman#Cleaning_the_package_cache).* + +Here's how to use `pacman`, to clean out all old packages that are cached: + + # pacman -Sc + +The Wiki cautions that this should be used with care. For example, since +older packages are deleted from the repository, if you encounter issues +and want to revert back to an older package, then it's useful to have the +caches available. Only do this ,if you are sure that you won't need it. + +The Wiki also mentions this method for removing everything from the +cache, including currently installed packages that are cached: + + # pacman -Scc + +This is inadvisable, since it means re-downloading the package again, if +you wanted to quickly re-install it. This should only be used when disk +space is at a premium. + +### pacman Command Equivalents +If you are coming from another GNU+Linux distribution, you probably want to know +the command equivalents for the various `apt-get`-related commands that you often use. +For that information, refer to [Pacman/Rosetta](https://wiki.archlinux.org/index.php/Pacman/Rosetta), +so named, because it serves as a Rosetta Stone to the esoteric pacman language. + +## your-freedom +`your-freedom` is a package specific to Parabola, and it is installed by +default. What it does is conflict with packages from Arch that are known +to be non-free (proprietary) software. When migrating from Arch (there +is a guide on the Parabola wiki for migrating (i.e,. converting) an existing +Arch system to a Parabola system), installing it will also +fail, if these packages are installed, citing them as conflicts; the +recommended solution is then to delete the offending packages, and +continue installing `your-freedom`. + +## Add a User +This is based on the Arch Wiki guide to [Users and Groups](https://wiki.archlinux.org/index.php/Users_and_Groups). + +It is important (for security reasons) to create and use a non-root +(non-admin) user account for everyday use. The default **root** account +is intended only for critical administrative work, since it has complete +access to the entire operating system. + +Read the entire document linked to above, and then continue. + +Add your user with the `useradd` command (self explanatory): + + # useradd -m -G wheel -s /bin/bash *your_user_name* + +Set a password, using `passwd`: + + # passwd *your_user_name* + +Like with the installation of Parabola, use of the [*diceware method*](http://world.std.com/~reinhold/diceware.html) is recommended, +for generating secure passphrases. + +### Configure sudo +Now that we have a normal user account, we'll want to configure `sudo`, +so that user is able to run commands as **root** (e.g., installing software); +this will be necessary to flash the ROM later on. Refer to ArchWiki's [sudo](https://wiki.archlinux.org/index.php/Sudo) documentation. + +The first step is to install the `sudo` package: + + # pacman -S sudo + +After installation, we must configure it. To do so, we must modify **/etc/sudoers**. +This file must *always* be modified with the `visudo` command. `visudo` can be +difficult for beginners to use, so we'll want to edit the file with `nano`, +but the trick is that we just can't do this: + + # nano /etc/sudoers + +Because, this will cause us to edit the file directly, which is not the way +it was designed to be edited, and could lead to problems with the system. +Instead, to temporarily allow us to use `nano` to edit the file, +we need to type this into the terminal: + + # EDITOR=nano visudo + +This will open the **/etc/sudoers** file in `nano`, and we can now safely make changes to it. + +To give the user we created earlier to ability to use `sudo`, we need to navigate +to the end of the file, and add this line on the end: + + your_username ALL=(ALL) ALL + +Obviously, type in the name of the user you created, instead of **your_username**. +Save the file, and exit `nano`; your user now has the ability to use `sudo`. + +## systemd +`systemd` is the name of the program for managing services in Parabola; +It is a good idea to become familiar with it. Read the Arch Wiki article on [systemd](https://wiki.archlinux.org/index.php/systemd), +as well as their [Basic systemctl usage](https://wiki.archlinux.org/index.php/systemd#Basic_systemctl_usage) article, +to gain a full understanding. *This is very important! Make sure to read them.* + +An example of a **service** could be a VPN (allowing you to connect to an outside network), +an applet in the system tray that tells you the weather for your city, +a sound manager (to make sure you can hear sound through speakers or headphones), +or DHCP (which allows you to get an IP address, to connect to the internet). +These are just a few examples; there are countless others. + +`systemd` is a controversial init system; A [forum post](https://bbs.archlinux.org/viewtopic.php?pid=1149530#p1149530) +has an explanation behind the Arch development team's decision to use it. + +The **manpage** should also help: + + # man systemd + +The section on **unit types** is especially useful. + +According to the wiki, `systemd's` journal keeps logs of a size up to 10% of the +total size that your root partition takes up. On a 60GB root, this would mean 6GB. +That's not exactly practical, and can have performance implications later, +when the log gets too big. Based on instructions from the wiki, +I will reduce the total size of the journal to 50MiB (that's what the wiki recommends). + +Open **/etc/systemd/journald.conf**, and find this line: + + #SystemMaxUse= + +Change it to this: + + SystemMaxUse=50M + +Restart `journald`: + + # systemctl restart systemd-journald + +The wiki recommends that if the journal gets too large, you can also +simply delete (`rm -Rf`) everything inside **/var/log/journald**, but +recommends backing it up. This shouldn't be necessary, since you +already set the size limit above, and `systemd` will automatically start +to delete older records, when the journal size reaches it's limit (according to systemd developers). + +Finally, the wiki mentions **temporary files**, and the utility for +managing them. + + # man systemd-tmpfiles + +To delete the temporary files, you can use the `clean` option: + + # systemd-tmpfiles --clean + +According to the **manpage**, this *"cleans all files and directories with +an age parameter"*. According to ArchWiki, this reads information +in **/etc/tmpfiles.d** and **/usr/lib/tmpfiles.d**, to know what actions to perform. +Therefore, it is a good idea to read what's stored in these locations, to get a better understanding. + +I looked in **/etc/tmpfiles.d/** and found that it was empty on my system. +However, **/usr/lib/tmpfiles.d** contained some files. The first one was +**etc.conf**, containing information and a reference to this **manpage**: + + # man tmpfiles.d + +Read that **manpage**, and then continue studying all the files. + +The `systemd` developers tell me that it isn't usually necessary +to manually touch the `systemd-tmpfiles utility`, at all. + +## Interesting Repositories +In their [kernels](https://wiki.parabolagnulinux.org/Repositories#kernels) article, +the Parabola wiki mentions a repository called `\[kernels\]`, for custom kernels +that aren't in the default **base**. It might be worth looking into what is available there, +depending on your use case. + +I enabled it on my system, to see what was in it. Edit **/etc/pacman.conf**, +and below the **extra** section add: + + [kernels] + Include = /etc/pacman.d/mirrorlist* + +Now, sync with the newly-added repository: + + # pacman -Syy + +Lastly, list all available packages in this repository: + + # pacman -Sl kernels + +In the end, I decided not to install anything from it, +but I kept the repository enabled regardless. + +## Setup a Network Connection in Parabola +Read the ArchWiki guide to [Configuring the Network](https://wiki.archlinux.org/index.php/Configuring_Network). + +### Set the Hostname +This should be the same as the hostname that you set in **/etc/hostname**, +when installing Parabola. You should also do it with `systemd`. +If you chose the hostname *parabola*, do it this way: + + # hostnamectl set-hostname parabola + +This writes the specified hostname to **/etc/hostname**. +More information can be found in these **manpages**: + + # man hostname + # info hostname + # man hostnamectl + +Check **/etc/hosts**, to make sure that the hostname that you put in there +during installation is still on each line: + + 127.0.0.1 localhost.localdomain localhost parabola + ::1 localhost.localdomain localhost parabola + +You'll note that I set both lines; the second line is for IPv6. Since more and +more ISPs are providing this now, it's good to be have it enabled, just in case. + +The `hostname` utility is part of the `inetutils` package, and is in the **core** repository, +installed by default (as part of the **base** package). + +### Network Status +According to ArchWiki, [udev](https://wiki.archlinux.org/index.php/Udev) should already detect +the ethernet chipset, and automatically load the driver for it at boot time. +You can check this in the **Ethernet controller** section, when running the `lspci` command: + + # lspci -v + +Look at the remaining sections **Kernel driver in use** and **Kernel modules**. +In my case, it was as follows: + + Kernel driver in use: e1000e + Kernel modules: e1000e + +Check that the driver was loaded, by issuing `dmesg | grep module_name`. +In my case, I did: + + # dmesg | grep e1000e + +### Network Device Names +According to the ArchWiki guide on [Configuring Network Device Names](https://wiki.archlinux.org/index.php/Configuring_Network#Device_names), +it is important to note that the old interface names that you might be used to +(e.g., `eth0`, `wlan0`, `wwan0`, etc.), if you come from a distribution like Debian or Trisquel, +are no longer applicable. Instead, `systemd` creates device names +starting with `en` (for ethernet), `wl` (for wi-fi), and `ww` (for wwan), +with a fixed identifier that it automatically generates. +An example device name for your ethernet chipset would be `enp0s25`, +and is never supposed to change. + +If you want to enable the old names, ArchWiki recommends adding `net.ifnames=0` +to your kernel parameters (in Libreboot context, this would be accomplished by following +the instructions in [How to replace the default GRUB configuration file](grub_cbfs.md)). + +For background information, read [Predictable Network Interface Names](http://www.freedesktop.org/wiki/Software/systemd/PredictableNetworkInterfaceNames/). + +To show what the device names are for your system, run the following command: + + # ls /sys/class/net + +[Changing the device names](https://wiki.archlinux.org/index.php/Configuring_Network#Change_device_name) is possible, +but for the purposes of this guide, there is no reason to do it. + +### Network Setup +Aside from the steps mentioned above, I choose to ignore most of Networking section on the wiki; +this is because I will be installing the *MATE Desktop Environment*, and thus will +be using the `NetworkManger` client (with its accompanying applet) to manage the network. + +If you wish to choose a different program, here are some other +[network manager options](https://wiki.archlinux.org/index.php/List_of_applications/Internet#Network_managers) +that you could use. + +## Configuring the Graphical Desktop Environment +Since we are going with the *MATE Desktop Environment*, we will primarily be following +the instructions on the [Arch Linux Package Repository](https://wiki.mate-desktop.org/archlinux_custom_repo) page, +but will also refer to the [General Recommendations](https://wiki.archlinux.org/index.php/General_recommendations#Graphical_user_interface) +on ArchWiki. + +### Installing Xorg +The first step is to install [**Xorg**](https://wiki.archlinux.org/index.php/Xorg); +this provides an implementation of the `X Window System`, which is used to provide +a graphical intefrace in GNU+Linux: + + # pacman -S xorg-server + +We also need to install the driver for our hardware. Since I am using a Thinkpad X200, +I will use `xf86-video-intel`; it should be the same on the other Thinkpads, +as well as the Macbook 1,1 and 2,1. + + # pacman -S xf86-video-intel + +For other systems, you can try: + + # pacman -Ss xf86-video- | less + +When this is combined with looking at your `lspci` output, you can determine which +driver is needed. By default, `Xorg` will revert to `xf86-video-vesa`, +which is a generic driver, and doesn't provide true hardware acceleration. + +Other drivers (not just video) can be found by looking at the `xorg-drivers` group: + + # pacman -Sg xorg-drivers + +### Xorg Keyboard Layout +`xorg` uses a different configuration method for keyboard layouts than Parabola, +so you will notice that the layout you set in **/etc/vconsole.conf** earlier might +not actually be the same in `xorg`. + +Check ArchWiki's article on [Xorg's keyboard configuration](https://wiki.archlinux.org/index.php/Keyboard_configuration_in_Xorg), for more information. + +To see what layout you currently use, try this on a terminal emulator in `xorg`: + + # setxkbmap -print -verbose 10 + +I'm simply using the default Qwerty (US) keyboard, so there isn't anything I need +to change here; if you do need to make any changes, ArchWiki recommends two ways +of doing it: manually updating [configuration files](https://wiki.archlinux.org/index.php/Keyboard_configuration_in_Xorg#Using_X_configuration_files) or using the [localectl](https://wiki.archlinux.org/index.php/Keyboard_configuration_in_Xorg#Using_localectl) command. + +### Installing MATE +Now we have to install the desktop environment itself. According to the Arch Linux Package Repository, +if we want all of the MATE Desktop, we need to install two packages: + + # pacman -Syy mate mate-extra + +The last step is to install a Display Manager; for MATE, we will be using `lightdm` +(it's the recommended Display Manager for the MATE Desktop); for this, we'll folow the instructions [on the MATE wiki](https://wiki.mate-desktop.org/archlinux_custom_repo#display_manager_recommended), +with one small change: the `lightdm-gtk3-greeter` package doesn't exist in Parabola's repositories. +So, instead we will install the `lightdm-gtk-greeter` package; it performs the same function. + +We'll also need the `accountsservice` package, which gives us the login window itself: + + # pacman -Syy lightdm-gtk3-greeter accountsservice + +After installing all the required packages, we need to make it so that the MATE Desktop Environment +will start automatically, whenever we boot our computer; to do this, we have to enable the display manager, `lightdm`, +as well as the service that will prompt us with a login window, `accounts-daemon`: + + # systemctl enable lightdm + # systemctl enable accounts-daemon + +Now you have installed the *MATE Desktop Environment*,If you wanted +to install another desktop environment, check out some [other options](https://wiki.archlinux.org/index.php/Desktop_environment) on ArchWiki. + +### Configuring Network Manager in MATE +Now that we have installed the Mate Desktop environment, and booted into it, +we need to set up the network configuration in our graphical environment. + +The MATE Desktop wiki recommends that we use Network Manager; an +article about Network Manager can be found +[on ArchWiki](https://wiki.archlinux.org/index.php/NetworkManager). + +We need to install the NetworkManager package: + + # pacman -S networkmanager + +We will also need the Network Manager applet, which will allow us to manage our +networks from the system tray: + + # pacman -S network-manager-applet + +Finally, we need to start the service (if we want to use it now), or enable it, +(so that it will activate automatically, at startup). + + # systemctl enable NetworkManager.service + +If you need VPN support, you will also want to install the `networkmanager-openvpn` package. + +**NOTE: You do not want multiple networking services running at the same time; +they will conflict, so, if using Network Manager, you want to stop/disable any +others from running. Examples of other services that will probably intefere +with Network Manager are** `dhcpcd` **and** `wifi-menu`**.** + +You can see all currently-running services with this command: + + # systemctl --type=service + +And you can stop them using this command: + + # systemctl stop service_name.service + +If you want to disable those services, meaning that you no longer want them to start +when the computer boots up, you will need to use `systemctl's` `disable` option, +instead of `stop`. + +Now you have a fully-functional graphical environment for your Parabola installation, +including networking. All you have to do is reboot, and you will be prompted to log in, +with a familiar graphical login prompt. You can also now, more easily [modify the GRUB configuration](grub_cbfs.md), +install new applications, and/or make whatever other changes you want to your system. + +Copyright © 2014, 2015 Leah Rowe + +Copyright © 2017 Elijah Smith + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) + diff --git a/i18n/fr_FR/docs/gnulinux/encrypted_debian.md b/i18n/fr_FR/docs/gnulinux/encrypted_debian.md new file mode 100644 index 00000000..23b4503f --- /dev/null +++ b/i18n/fr_FR/docs/gnulinux/encrypted_debian.md @@ -0,0 +1,318 @@ +--- +title: Installing Debian or Devuan GNU+Linux with full disk encryption (including /boot) +... + +This guide is written for the Debian distribution, but it should also +work for Devuan with the net installer. + +Gigabyte GA-G41M-ES2L +===================== + +To boot the Trisquel net installer, make sure to specify fb=false on the linux +kernel parameters in GRUB. This will boot the installer in text mode instead +of using a framebuffer. + +Moving on... +============ + +Libreboot on x86 uses the GRUB +[payload](http://www.coreboot.org/Payloads#GRUB_2) by default, which +means that the GRUB configuration file (where your GRUB menu comes from) +is stored directly alongside libreboot and its GRUB payload executable, +inside the flash chip. In context, this means that installing +distributions and managing them is handled slightly differently compared +to traditional BIOS systems. + +On most systems, the /boot partition has to be left unencrypted while +the others are encrypted. This is so that GRUB, and therefore the +kernel, can be loaded and executed since the firmware can't open a LUKS +volume. Not so with libreboot! Since GRUB is already included directly +as a payload, even /boot can be encrypted. This protects /boot from +tampering by someone with physical access to the system. + +This guide is written for Debian net installer. You can download the ISO +from the homepage on [debian.org](https://www.debian.org/). Use this on +the GRUB terminal to boot it from USB (for 64-bit Intel or AMD): + + set root='usb0' + linux /install.amd/vmlinuz + initrd /install.amd/initrd.gz + boot + +If you are on a 32-bit system (e.g. X60): + + set root='usb0' + linux /install.386/vmlinuz + initrd /install.386/initrd.gz + boot + +[This guide](grub_boot_installer.md) shows how to create a boot USB +drive with the Debian ISO image. + +*This guide is only for the GRUB payload. If you use the depthcharge payload, +ignore this section entirely.* + +Note: on some thinkpads, a faulty DVD drive can cause the cryptomount -a step +during boot to fail. If this happens to you, try removing the drive. + +Set a strong user password (lots of lowercase/uppercase, numbers and symbols). + +Use of the *diceware method* is recommended, for generating secure passphrases +(instead of passwords). + +When the installer asks you to set up encryption (ecryptfs) for your home +directory, select 'Yes' if you want to: *LUKS is already secure and performs +well. Having ecryptfs on top of it will add noticeable performance penalty, for +little security gain in most use cases. This is therefore optional, and not +recommended. Choose 'no'.* + +*Your user password should be different from the LUKS password which +you will set later on. Your LUKS password should, like the user +password, be secure.* + +Partitioning +============ + +Choose 'Manual' partitioning: + +- Select drive and create new partition table +- Single large partition. The following are mostly defaults: + - Use as: physical volume for encryption + - Encryption: aes + - key size: whatever default is given to you + - IV algorithm: whatever default is given to you + - Encryption key: passphrase + - erase data: Yes (only choose 'No' if it's a new drive that + doesn't contain your private data) + +- Select 'configure encrypted volumes' + - Create encrypted volumes + - Select your partition + - Finish + - Really erase: Yes + - (erase will take a long time. be patient) + - (if your old system was encrypted, just let this run for about a + minute to make sure that the LUKS header is wiped out) +- Select encrypted space: + - use as: physical volume for LVM + - Choose 'done setting up the partition' +- Configure the logical volume manager: + - Keep settings: Yes +- Create volume group: + - Name: `matrix` (use this exact name) + - Select crypto partition +- Create logical volume + - select `matrix` (use this exact name) + - name: `rootvol` (use this exact name) + - size: default, minus 2048 MB +- Create logical volume + - select `matrix` (use this exact name) + - name: `swap` (user this exact name) + - size: press enter + +Further partitioning +==================== + +Now you are back at the main partitioning screen. You will simply set +mountpoints and filesystems to use. + +- LVM LV rootvol + - use as: btrfs + - mount point: / + - done setting up partition +- LVM LV swap + - use as: swap area + - done setting up partition +- Now you select 'Finished partitioning and write changes to disk'. + +Kernel +====== + +Installation will ask what kernel you want to use. linux-generic is +fine. + +Tasksel +======= + +For Debian, use the *MATE* option, or one of the others if you want. The +libreboot project recommends MATE, unless you're saavy enough to choose +something else. + +If you want debian-testing, then you should only select barebones +options here and change the entries in /etc/apt/sources.list after +install to point to the new distro, and then run `apt-get update` and +`apt-get dist-upgrade` as root, then reboot and run `tasksel` as +root. This is to avoid downloading large packages twice. + +NOTE: If you want the latest up to date version of the Linux kernel, +Debian's kernel is sometimes outdated, even in the testing distro. You +might consider using [this repository](https://jxself.org/linux-libre/) +instead, which contains the most up to date versions of the Linux +kernel. These kernels are also deblobbed, like Debian's kernels, so you +can be sure that no binary blobs are present. + +Postfix configuration +===================== + +If asked, choose *"No Configuration"* here (or maybe you want to +select something else. It's up to you.) + +Install the GRUB boot loader to the master boot record +====================================================== + +Choose 'Yes'. It will fail, but don't worry. Then at the main menu, +choose 'Continue without a bootloader'. You could also choose 'No'. +Choice is irrelevant here. + +*Don't forget to have grub-coreboot package installed, even though installing grub to MBR is irrelevant +on libreboot system, grub tools are still needed to eg. generate config (`grub-mkconfig`)* + +Clock UTC +========= + +Just say 'Yes'. + +Booting your system +=================== + +At this point, you will have finished the installation. At your GRUB +payload, press C to get to the command line, and enter: + + grub> cryptomount -a + grub> set root='lvm/matrix-rootvol' + grub> linux /vmlinuz root=/dev/mapper/matrix-rootvol cryptdevice=/dev/mapper/matrix-rootvol:root + grub> initrd /initrd.img + grub> boot + +ecryptfs +======== + +If you didn't encrypt your home directory, then you can safely ignore +this section. + +Immediately after logging in, do that: + + $ sudo ecryptfs-unwrap-passphrase + +This will be needed in the future if you ever need to recover your home +directory from another system, so write it down and keep the note +somewhere secret. Ideally, you should memorize it and then burn the note +(or not even write it down, and memorize it still)> + +Modify grub.cfg (CBFS) +====================== + +Now you need to set it up so that the system will automatically boot, +without having to type a bunch of commands. + +Modify your grub.cfg (in the firmware) [using this +tutorial](grub_cbfs.md); just change the default menu entry 'Load +Operating System' to say this inside: + + cryptomount -a + set root='lvm/matrix-rootvol' + linux /vmlinuz root=/dev/mapper/matrix-rootvol cryptdevice=/dev/mapper/matrix-rootvol:root + initrd /initrd.img + +Without specifying a device, the *-a* parameter tries to unlock all +detected LUKS volumes. You can also specify -u UUID or -a (device). + +[Refer to this guide](grub_hardening.md) for further guidance on +hardening your GRUB configuration, for security purposes. + +Flash the modified ROM using [this tutorial](../install/#flashrom). + +Troubleshooting +=============== + +A user reported issues when booting with a docking station attached on +an X200, when decrypting the disk in GRUB. The error *AHCI transfer +timed out* was observed. The workaround was to remove the docking +station. + +Further investigation revealed that it was the DVD drive causing +problems. Removing that worked around the issue. + + "sudo wodim -prcap" shows information about the drive: + Device was not specified. Trying to find an appropriate drive... + Detected CD-R drive: /dev/sr0 + Using /dev/cdrom of unknown capabilities + Device type : Removable CD-ROM + Version : 5 + Response Format: 2 + Capabilities : + Vendor_info : 'HL-DT-ST' + Identification : 'DVDRAM GU10N ' + Revision : 'MX05' + Device seems to be: Generic mmc2 DVD-R/DVD-RW. + + Drive capabilities, per MMC-3 page 2A: + + Does read CD-R media + Does write CD-R media + Does read CD-RW media + Does write CD-RW media + Does read DVD-ROM media + Does read DVD-R media + Does write DVD-R media + Does read DVD-RAM media + Does write DVD-RAM media + Does support test writing + + Does read Mode 2 Form 1 blocks + Does read Mode 2 Form 2 blocks + Does read digital audio blocks + Does restart non-streamed digital audio reads accurately + Does support Buffer-Underrun-Free recording + Does read multi-session CDs + Does read fixed-packet CD media using Method 2 + Does not read CD bar code + Does not read R-W subcode information + Does read raw P-W subcode data from lead in + Does return CD media catalog number + Does return CD ISRC information + Does support C2 error pointers + Does not deliver composite A/V data + + Does play audio CDs + Number of volume control levels: 256 + Does support individual volume control setting for each channel + Does support independent mute setting for each channel + Does not support digital output on port 1 + Does not support digital output on port 2 + + Loading mechanism type: tray + Does support ejection of CD via START/STOP command + Does not lock media on power up via prevent jumper + Does allow media to be locked in the drive via PREVENT/ALLOW command + Is not currently in a media-locked state + Does not support changing side of disk + Does not have load-empty-slot-in-changer feature + Does not support Individual Disk Present feature + + Maximum read speed: 4234 kB/s (CD 24x, DVD 3x) + Current read speed: 4234 kB/s (CD 24x, DVD 3x) + Maximum write speed: 4234 kB/s (CD 24x, DVD 3x) + Current write speed: 4234 kB/s (CD 24x, DVD 3x) + Rotational control selected: CLV/PCAV + Buffer size in KB: 1024 + Copy management revision supported: 1 + Number of supported write speeds: 4 + Write speed # 0: 4234 kB/s CLV/PCAV (CD 24x, DVD 3x) + Write speed # 1: 2822 kB/s CLV/PCAV (CD 16x, DVD 2x) + Write speed # 2: 1764 kB/s CLV/PCAV (CD 10x, DVD 1x) + Write speed # 3: 706 kB/s CLV/PCAV (CD 4x, DVD 0x) + + Supported CD-RW media types according to MMC-4 feature 0x37: + Does write multi speed CD-RW media + Does write high speed CD-RW media + Does write ultra high speed CD-RW media + Does not write ultra high speed+ CD-RW media + +Copyright © 2014, 2015, 2016 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/gnulinux/encrypted_parabola.md b/i18n/fr_FR/docs/gnulinux/encrypted_parabola.md new file mode 100644 index 00000000..9424ec3b --- /dev/null +++ b/i18n/fr_FR/docs/gnulinux/encrypted_parabola.md @@ -0,0 +1,507 @@ +--- +title: Installing Parabola or Arch GNU+Linux-Libre, with Full-Disk Encryption (including /boot) +x-toc-enable: true +... + +Also see: +[Installing Hyperbola GNU+Linux, with Full-Disk Encryption (including /boot)](https://wiki.hyperbola.info/en:guide:encrypted_installation) + +This guide covers how to install Parabola GNU+Linux-Libre, with full disk encryption, +including **/boot** (the boot directory). On most systems, **/boot** has +to be left unencrypted, while the other partition(s) are encrypted. +This is so that GRUB (and therefore the kernel) can be loaded and executed, +because most firmware can’t open a LUKS volume; however, with libreboot, +GRUB is already included as a [payload](http://www.coreboot.org/Payloads#GRUB_2), +so even **/boot** can be encrypted; this protects **/boot** from tampering +by someone with physical access to the system. + +**NOTE: This guide is *only* for the GRUB payload. +If you use the depthcharge payload, ignore this section entirely.** + +This guide borrows heavily from the Parabola wiki, and will constantly link to it. +For those new to Parabola GNU+Linux-Libre, check their [Beginner section](https://wiki.parabola.nu/Beginners%27_guide#Beginners) for an overview. + +## Minumum Requirements +You can find the minimum requirements to run Parabola GNU+Linux +[on the Parabola wiki](https://wiki.parabola.nu/Beginners%27_guide#Minimum_system_requirements). + +## Preparation + +### Download the latest ISO +For this guide, I used the *2016.11.03* ISO; the most current image is +available on Parabola's +[downloads page](https://wiki.parabola.nu/Get_Parabola#Main_live_ISO). + +If you are a complete beginner with GNU+Linux, choose the *Mate Desktop ISO*. +it is easier to install Parabola with this version, because it allows you +access to a web browser, so you can copy and paste commands right into the terminal, +without worrying about typos. + +**NOTE: You should never blindly copy-and-paste any commands. In this guide, +copying and pasting is to ensure that no errors are made when entering the commands, +so that you don't effectively "brick" your installation, and have to start over. +It's important to understand what each command does before you use it, +so be sure to read the Parabola/Archi Wiki documentation on the command, +as well as its** `man` **page.** + +If you are not a beginner, choose the *Main Live ISO*. + +Only choose the *TalkingParabola ISO*, if you are blind or visually impaired. + +### Choose the Installation Device +Refer to the Parabola wiki, for finding and choosing the proper installation device, +whether you are using an [Optical Disk](https://wiki.parabola.nu/Beginners%27_guide#Optical_Disks), +or a [USB drive](https://wiki.parabola.nu/Beginners%27_guide#USB_flash_drive). + +### Boot Parabola's Install Environment +After downloading the ISO, and creating some kind of bootable media, +you will need to boot into the Live image. If you are unsure of how to do so, +see [How to boot a GNU+Linux installer](grub_boot_installer.md), +and move on to the next step; otherwise, just go to the next step. + +Once booted into the environment, either open the **`MATE Terminal`** application +(if using the MATE Desktop ISO), or simply just enter the commands listed below +(if using any of the other ISO's). + +## Setting Up Keyboard Layout +To begin the installation, you must first select the proper [keyboard layout](https://wiki.parabola.nu/Beginners%27_guide#Changing_Keyboard). + +## Establish an Internet Connection +You will also need to [set up a network connection](https://wiki.parabola.nu/Beginners%27_guide#Establish_an_internet_connection), +to install packages. + +## Preparing the Storage Device for Installation + +You need to prepare the storage device that we will use to install the operating system. +You can use same [device name](https://wiki.parabola.nu/Beginners%27_guide#USB_flash_drive) +that you used earlier, to determine the installation device for the ISO. + +### Wipe Storage Device +You want to make sure that the device you're using doesn't contain any plaintext +copies of your personal data. If the drive is new, then you can skip the rest of this section; +if it's not new, then there are two ways to handle it: + +1. If the drive were not previously encrypted, securely wipe it with the `dd` command; +you can either choose to fill it with zeroes or random data; I chose random data (e.g., `urandom`), +because it's more secure. Depending on the size of the drive, this could take a while to complete: + + ~~~ + # dd if=/dev/urandom of=/dev/sdX; sync + ~~~ + +2. If the drive were previously encrypted, all you need to do is wipe the LUKS header. +The size of the header depends upon the specific model of the hard drive; +you can find this information by doing some research online. +Refer to this [article](https://www.lisenet.com/2013/luks-add-keys-backup-and-restore-volume-header/), for more information about LUKS headers. +You can either fill the header with zeroes, or with random data; again, I chose random data, using `urandom`: + + ~~~ + # head -c 3145728 /dev/urandom > /dev/sdX; sync + ~~~ + +Also, if you're using an SSD, there are a two things you should keep in mind: + +- There are issues with TRIM; it's not enabled by default through LUKS, +and there are security issues, if you do enable it. See [this page](https://wiki.archlinux.org/index.php/Dm-crypt#Specialties) for more info. +- Make sure to read [this article](https://wiki.archlinux.org/index.php/Solid_State_Drives), +for information on managing SSD's in Arch Linux (the information applies to Parabola, as well). + +### Formatting the Storage Device +Now that all the personal data has been deleted from the disk, it's time to format it. +We'll begin by creating a single, large partition on it, and then encrypting it using LUKS. + +#### Create the LUKS partition +You will need the `device-mapper` kernel module during the installation; +this will enable us to set up our encrypted disk. To load it, use the following command: + + # modprobe dm_mod + +We then need to select the **device name** of the drive we're installing the operating system on; +see the above method, if needed, for figuring out device names. + +Now that we have the name of the correct device, we need to create the partition on it. +For this, we will use the `cfdisk` command: + + # cfdisk /dev/sdX + +1. Use the arrow keys to select your partition, and if there is already a partition +on the drive, select **Delete**, and then **New**. +2. For the partition size, leave it as the default, which will be the entire drive. +3. You will see an option for **Primary** or **Logical**; choose **Primary**, +and make sure that the partition type is **Linux (83)**. +4. Select **Write**; it will ask you if you are sure that you want to overwrite the drive. +5. Type **yes**, and press enter. A message at the bottom will appear, telling you that +the partition table has been altered. +6. Select **Quit**, to return you to the main terminal. + +Now that you have created the partition, it's time to create the encrypted volume on it, +using the `cryptsetup` command, like this: + + # cryptsetup -v --cipher serpent-xts-plain64 --key-size 512 --hash whirlpool \ + --iter-time 500 --use-random --verify-passphrase --type luks1 luksFormat /dev/sdXY + +These are just recommended defaults; if you want to use anything else, +or to find out what options there are, run `man cryptsetup`. + +>**NOTE: the default iteration time is 2000ms (2 seconds), +>if not specified when running the cryptsetup command. You should set a lower time than this; +>otherwise, there will be an approximately 20-second delay when booting your +>system. We recommend 500ms (0.5 seconds), and this is included in the +>prepared** `cryptsetup` **command above. Keep in mind that the iteration time +>is for security purposes (it mitigates brute force attacks), so anything lower +>than 0.5 seconds is probably not very secure.** + +You will now be prompted to enter a passphrase; be sure to make it *secure*. +For passphrase security, length is more important than complexity +(e.g., **correct-horse-battery-staple** is more secure than **bf20$3Jhy3**), +but it's helpful to include several different types of characters +(e.g., uppercase/lowercase letters, numbers, special characters). +The password length should be as long as you are able to remember, +without having to write it down, or store it anywhere. + +Use of the [**diceware**](http://world.std.com/~reinhold/diceware.html) method +is recommended, for generating secure passphrases (rather than passwords). + +#### Create the Volume Group and Logical Volumes +The next step is to create two Logical Volumes within the LUKS-encrypted partition: +one will contain your main installation, and the other will contain your swap space. + +We will create this using, the [Logical Volume Manager (LVM)](https://wiki.archlinux.org/index.php/LVM). + +First, we need to open the LUKS partition, at **/dev/mapper/lvm**: + + # cryptsetup luksOpen /dev/sdXY lvm + +Then, we create LVM partition: + + # pvcreate /dev/mapper/lvm + +Check to make sure tha the partition was created: + + # pvdisplay + +Next, we create the volume group, inside of which the logical volumes will +be created. In libreboot's case, we will call this group **matrix**. +If you want to have it work via *Load Operating System (incl. fully +encrypted disks) [o]* it needs to be called **matrix** (as it is harcoded +in libreboot's grub.cfg on the flash) + + # vgcreate matrix /dev/mapper/lvm + +Check to make sure that the group was created: + + # vgdisplay + +Lastly, we need to create the logical volumes themselves, inside the volume group; +one will be our swap, cleverly named **swapvol**, and the other will be our root partition, +equally cleverly named as **rootvol**. + +1. We will create the **swapvol** first (again, choose your own name, if you like). +Also, make sure to [choose an appropriate swap size](http://www.linux.com/news/software/applications/8208-all-about-linux-swap-space) +(e.g., **2G** refers to two gigabytes; change this however you see fit): + + ~~~ + # lvcreate -L 2G matrix -n swapvol + ~~~ + +2. Now, we will create a single, large partition in the rest of the space, for **rootvol**: + + ~~~ + # lvcreate -l +100%FREE matrix -n rootvol + ~~~ + +You can also be flexible here, for example you can specify a **/boot**, a **/**, +a **/home**, a **/var**, or a **/usr** volume. For example, if you will be running a +web/mail server then you want **/var** (where logs are stored) in its own partition, +so that if it fills up with logs, it won't crash your system. +For a home/laptop system (typical use case), just a root and a swap will do. + +Verify that the logical volumes were created correctly: + + # lvdisplay + +#### Make the rootvol and swapvol Partitions Ready for Installation +The last steps of setting up the drive for installation are turning **swapvol** +into an active swap partition, and formatting **rootvol**. + +To make **swapvol** into a swap partition, we run the `mkswap` (i.e., make swap) command: + + # mkswap /dev/mapper/matrix-swapvol + +Activate the **swapvol**, allowing it to now be used as swap, +using `swapon` (i.e., turn swap on) command: + + # swapon /dev/matrix/swapvol + +Now I have to format **rootvol**, to make it ready for installation; +I do this with the `mkfs` (i.e., make file system) command. +I choose the **ext4** filesystem, but you could use a different one, +depending on your use case: + + # mkfs.ext4 /dev/mapper/matrix-rootvol + +Lastly, I need to mount **rootvol**. Fortunately, GNU+Linux has a directory +for this very purpose: **/mnt**: + + # mount /dev/matrix/rootvol /mnt + +#### Separate boot and home logical volumes +You could also create two separate logical volumes for **/boot** and **/home**, +but such a setup would be for advanced users, +and is thus not covered in this guide. +If separate boot logical volume is used, it has to be named **boot** +in order for libreboot to use it. + +The setup of the drive and partitions is now complete; it's time to actually install Parabola. + +## Select a Mirror +The first step of the actual installation is to choose the server from where +we will need to download the packages; for this, we will again refer to the [Parabola Wiki](https://wiki.parabola.nu/Beginners%27_guide#Select_a_mirror). +For beginners, I recommend that the edit the file using `nano` (a command-line text editor); +you can learn more about it on [their website](https://www.nano-editor.org/); for non-beginners, +simply edit it with your favorite text editor. + +## Install the Base System +We need to install the essential applications needed for your Parabola installation to run; +refer to [Install the Base System](https://wiki.parabola.nu/Beginners%27_guide#Install_the_base_system), on the Parabola wiki. + +## Generate an fstab +The next step in the process is to generate a file known as an **fstab**; +the purpose of this file is for the operating system to identify the storage device +used by your installation. [On the Parabola beginner's guide](https://wiki.parabola.nu/Beginners%27_guide#Generate_an_fstab) are the instructions to generate that file. + +## Chroot into and Configure the System +Now, you need to `chroot` into your new installation, to complete the setup +and installation process. **Chrooting** refers to changing the root directory +of an operating system to a different one; in this instance, it means changing your root +directory to the one you created in the previous steps, so that you can modify files +and install software onto it, as if it were the host operating system. + +To `chroot` into your installation, follow the instructions [on the +Parabola beginner's guide](https://wiki.parabola.nu/Beginners%27_guide#Chroot_and_configure_the_base_system). + +### Setting up the Locale +Locale refers to the language that your operating system will use, as well as some +other considerations related to the region in which you live. To set this up, +follow the instructions [in the Parabola beginner's guide](https://wiki.parabola.nu/Beginners%27_guide#Locale). + +### Setting up the Consolefont and Keymap +This will determine the keyboard layout of your new installation; follow the instructions [in the Parabola beginner's guide](https://wiki.parabola.nu/Beginners%27_guide#Console_font_and_keymap). + +### Setting up the Time Zone +You'll need to set your current time zone in the operating system; this will enable applications +that require accurate time to work properly (e.g., the web browser). +To do this, follow the instructions [in the Parabola beginner's guide](https://wiki.parabola.nu/Beginners%27_guide#Time_zone). + +### Setting up the Hardware Clock +To make sure that your computer has the right time, you'll have to set the time in your computer's internal clock. +Follow the instructions [in the Parabola beginner's guide](https://wiki.parabola.nu/Beginners%27_guide#Hardware_clock) to do that. + +### Setting up the Kernel Modules +Now we need to make sure that the kernel has all the modules that it needs +to boot the operating system. To do this, we need to edit a file called **mkinitcpio.conf**. +More information about this file can be found [in the Parabola beginner's guide](https://wiki.parabola.nu/Mkinitcpio), +but for the sake of this guide, you simply need to run the following command. + + # nano /etc/mkinitcpio.conf + +There are several modifications that we need to make to the file: + +1. Change the value of the uncommented `MODULES` line to `i915`. + + * This forces the driver to load earlier, so that the console font you selected earlier + isn’t wiped out after getting to login. + * If you are using a **Macbook 2,1** you will also need to add `hid-generic`, + `hid`, and `hid-apple` inside the quotation marks, in order to have + a working keyboard when asked to enter the LUKS password. + Make sure to separate each module by one space. + +2. Change the value of the uncommented `HOOKS` line to the following: + + ~~~ + base udev autodetect modconf block keyboard keymap consolefont encrypt lvm2 filesystems fsck shutdown + ~~~ + + here's what each module does: + + * `keymap` adds to *initramfs* the keymap that you specified in **/etc/vconsole.conf** + * `consolefont` adds to *initramfs* the font that you specified in **/etc/vconsole.conf** + * `encrypt` adds LUKS support to the initramfs - needed to unlock your disks at boot time + * `lvm2` adds LVM support to the initramfs - needed to mount the LVM partitions at boot time + * `shutdown` is needed according to Parabola wiki, for unmounting devices (such as LUKS/LVM) during shutdown + +After modifying the file and saving it, we need to update the kernel(s) with the new settings. +Before doing this, we want to install a Long-Term Support (LTS) kernel as a backup, in the event +that we encounter problems with the default Linux-Libre kernel (which is continually updated). + +We will also install the `grub` package, which we will need later, +to make our modifications to the GRUB configuration file: + + # pacman -S linux-libre-lts grub + +Then, we update both kernels like this, using the `mkinitcpio` command: + + # mkinitcpio -p linux-libre + # mkinitcpio -p linux-libre-lts + +### Setting up the Hostname +Now we need to set up the hostname for the system; this is so that our device +can be identified by the network. Refer to [the hostname section](https://wiki.parabola.nu/Beginners%27_guide#Hostname) +of the Parabola wiki's Beginner's Guide. You can make the hostname anything you like; +for example, if you wanted to choose the hostname **parabola**, +you would run the `echo` command, like this: + + # echo parabola > /etc/hostname + +And then you would modify **/etc/hosts** like this, adding the hostname to it: + + # nano /etc/hosts + + # + 127.0.0.1 localhost.localdomain localhost parabola + ::1 localhost.localdomain localhost parabola + +### Configure the Network +Now that we have a hostname, we need to configure the settings for the rest of the network. +Instructions for setting up a wired connection are [in the Parabola beginner's guide](https://wiki.parabola.nu/Beginners%27_guide#Wired), +and instructions for setting up a wireless connection are [in the Parabola beginner's guide](https://wiki.parabola.nu/Beginners%27_guide#Wireless_2). + +### Set the root Password +The **root** account has control over all the files in the computer; for security, +we want to protect it with a password. The password requirements given above, +for the LUKS passphrase, apply here as well. You will set this password with the `passwd` command: + + # passwd + +### Extra Security Tweaks +There are some final changes that we can make to the installation, to make it +significantly more secure; these are based on the [Security](https://wiki.archlinux.org/index.php/Security) section of the Arch wiki. + +#### Key Strengthening +We will want to open the configuration file for password settings, and increase +the strength of our **root** password: + + # nano /etc/pam.d/passwd + +Add `rounds=65536` at the end of the uncommented 'password' line; in simple terms, +this will force an attacker to take more time with each password guess, mitigating +the threat of brute force attacks. + +#### Restrict Access to Important Directories +You can prevent any user, other than the root user, from accessing the most important +directories in the system, using the `chmod` command; to learn more about this command, +run `man chmod`: + + # chmod 700 /boot /etc/{iptables,arptables} + +#### Lockout User After Three Failed Login Attempts +We can also setup the system to lock a user's account, after three failed login attempts. + +To do this, we will need to edit the file **/etc/pam.d/system-login**, +and comment out this line: + + auth required pam\_tally.so onerr=succeed file=/var/log/faillog*\ + +You could also just delete it. Above it, put the following line: + + auth required pam\_tally.so deny=2 unlock\_time=600 onerr=succeed file=/var/log/faillog + +This configuration will lock the user out for ten minutes. +You can unlock a user's account manually, using the **root** account, with this command: + + # pam_tally --user *theusername* --reset + +#### Generate grub.cfg +Edit configuration in `/etc/default/grub`, remembering to use UUID when poitning to mbr/gpt partition. +Use `blkid` to get list of devices with their respective UUIDs. +For details see [parabola wiki.](https://wiki.parabola.nu/Dm-crypt/Encrypting_an_entire_system#Configuring_the_boot_loader_5) + +Next generate grub.cfg with: + + # grub-mkconfig -o /boot/grub/grub.cfg + +If you have separate `/boot` partition, don't forget to add `boot` symlink inside that points to current directory + + # cd /boot; ln -s . boot + +## Unmount All Partitions and Reboot +Congratulations! You have finished the installation of Parabola GNU+Linux-Libre. +Now it is time to reboot the system, but first, there are several preliminary steps: + +Exit from `chroot`, using the `exit` command: + + # exit + +Unmount all of the partitions from **/mnt**, and "turn off" the swap volume: + + # umount -R /mnt + # swapoff -a + +Deactivate the **rootvol** and **swapvol** logical volumes: + + # lvchange -an /dev/matrix/rootvol + # lvchange -an /dev/matrix/swapvol + +Lock the encrypted partition (i.e., close it): + + # cryptsetup luksClose lvm + +Shutdown the machine: + + # shutdown -h now + +After the machine is off, remove the installation media, and turn it on. + +## Booting the installation manually from GRUB +When you forget to configure or misconfigure grub on your hdd, you have to manually boot +the system by entering a series of commands into the GRUB command line. + + +After the computer starts, Press `C` to bring up the GRUB command line. +You can either boot the normal kernel, or the LTS kernel we installed; +here are the commands for the normal kernel: + + grub> cryptomount -a + grub> set root='lvm/matrix-rootvol' + grub> linux /boot/vmlinuz-linux-libre root=/dev/matrix/rootvol cryptdevice=/dev/sda1:root + grub> initrd /boot/initramfs-linux-libre.img + grub> boot + +If you're trying to boot the LTS kernel, simply add **-lts** to the end +of each command that contains the kernel (e.g., **/boot/vmlinuz-linux-libre** +would be **/boot/vmlinuz/linux-libre-lts**). + +**NOTE: on machines with native sata, during boot a (faulty) optical disc drive (like dvd) can cause +the** `cryptomount -a` **command to fail/hang, as well as the error** `AHCI transfer timed out` +**The workaround was to remove the DVD drive.** + +## Follow-Up Tutorial: Configuring Parabola +The next step of the setup process is to modify the configuration file that +GRUB uses, so that we don't have to manually type in those commands above, each time we want +to boot our system. + +To make this process much easier, we need to install a graphical interface, +as well as install some other packages that will make the system more user-friendly. +These additions will also sharply reduce the probability of "bricking" our computer. + +[Configuring Parabola (Post-Install)](configuring_parabola.md) provides an example setup, but don't feel +as if you must follow it verbatim (of course, you can, if you want to); +Parabola is user-centric and very customizable, which means that you have maximum control +of the system, and a near-limitless number of options for setting it up. For more information, +read [The Arch Way](https://wiki.archlinux.org/index.php/The_Arch_Way) (Parabola also follows it). + +After setting up the graphical interface, refer to [How to Modify GRUB Configuration](grub_cbfs.md), +for instructions on doing just that, as well as flashing the ROM (if necessary). + +Copyright © 2014, 2015, 2016 Leah Rowe + +Copyright © 2015 Jeroen Quint + +Copyright © 2017 Elijah Smith + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) + diff --git a/i18n/fr_FR/docs/gnulinux/encrypted_trisquel.md b/i18n/fr_FR/docs/gnulinux/encrypted_trisquel.md new file mode 100644 index 00000000..32ff87f6 --- /dev/null +++ b/i18n/fr_FR/docs/gnulinux/encrypted_trisquel.md @@ -0,0 +1,190 @@ +--- +title: Installing Trisquel GNU+Linux with Full-Disk Encryption (including /boot) +x-toc enable: true +... + +This guide is written for the Trisquel 7.0 (Belenos) GNU+Linux distribution, but it should also work for Trisquel 6.0 (Toutatis). + +## Gigabyte GA-G41M-ES2L + +To boot the Trisquel net installer, make sure to specify fb=false on the linux +kernel parameters in GRUB. This will boot the installer in text mode instead +of using a framebuffer. + +## Boot the Installation Media +Boot your operating system, with the installation media. If you don't know how to do so, refer to [How to Prepare and Boot a USB Installer in Libreboot Systems](grub_boot_installer.md). + +When the Trisquel GRUB screen appears, select the `Install Trisquel in Text Mode` option. + +## Select a Language +The first part of the installation is to select your system's language; I chose `English`. + +## Select Your Location +You will need to select your location; I choose `United States`. + +## Configure the Keyboard +You need to select the right layout for your keyboard; if you want to installer to do it automatically, choose `Yes`, and it will ask you whether or not a series of keys are present on your keyboard. Simply choose `Yes` or `No`, accordingly. + +If you don't want the installer to automatically detect your keyboard layout, choose `No`, and simply select it from a list. + +## Configure the Network + +### Choose the Network Inteface +You will need to select the network interface to be used for the installation. If you have an ethernet (i.e., wired) connection, choose `etho0`; otherwise, choose `wlan0` (for wireless). + +If you choose `wlan0`, enter the passphrase that corresponds to your wireless network's WPA/WPA2 key (Your wireless network should have a password, and no modern router should be using the [WEP protocol](https://en.wikipedia.org/wiki/Wired_Equivalent_Privacy)). + +### Choose Your Hostname +You will need to choose a hostname for the system, which identifies your computer to the network; it can be anything, but it must only consist of numbers, uppercase and lowercase letters, and dashes `-`. + +### Choose a Mirror of the Trisquel Archive +Choose the server from where you will download the Trisquel packages needed for the installation. The choices are separated by country; simply select the one that is closest to where you are. + +After you select the country, you will be taken to a list of different individual servers. If there is more than one option, choose the one that is closest to you; otherwise, select whichever one is available. + +The last step of setting up the network will be entering an HTTP proxy (if you need one to access the network). If you have one, type it here; otherwise, press `Tab`, and then choose `Continue` (using the arrow keys). + +## Loading Additional Components +Now the installer needs to download some more packages, to continue the installation. Depending on your network bandwidth, this could take up to a few minutes to complete. + +## Set Up Users and Passwords +Enter the full name of the user here. You can use your real name, or just a pseudonym; then, choose `Continue`. + +Then it will ask you to enter a *username*. Pick whatever you like, and enter it here. Select `Continue`. + +Choose a passphrase (better than a password). The [diceware](http://world.std.com/~reinhold/diceware.html) method is highly recommended for coming up with one. + +I recommend combining the *diceware* method with something personal about yourself. An example of this would be to choose four words from the *diceware* list, and then come up with a fifth "word" (i.e., a combination of characters that is unique to you, like some name plus a number/special character); this combination dramatically increases the security of a *diceware* passphrase (i.e., even if someone had the entire *diceware* word list, they couldn't figure out your passphrase through brute force). + +**NOTE: This would be difficult for a person to do, even if you *only* used words from the list**. + +For example, say that your cat's name is **Max**, and he is three years old; you could do something like this: + + diceware_word_1 diceware_word_2 diceware_word_3 diceware_word_4 Max=3old + +This has a large degree of randomness (due to the usage of the *diceware* method), and also contains a unique piece of personal information that someone would need to know you, in order to guess; it's a very potent combination. + +After entering this password twice, choose `Continue`. + +It will now ask you if you want to encrypt your home directory. Remember, this is *NOT* to be confused with encrypting your entire disk (the purpose of this guide); it will just be the files that reside in `~`, and it uses a different encryption protocol (`ecryptfs`). If you want to encrypt your home directory here, choose `Yes`; however, since we are going to encrypt the entire installation, that would not only be redundant, but it would also add a noticeable performance penalty, for little security gain in most use cases. This is therefore optional, and *NOT* recommended. Choose `No`. + +## Configure the Clock +The installer will try to auto-detect your time zone; if it chooses correctly, select `Yes`; otherwise, choose `No`, and it will prompt you to select the correct one. + +## Partition Disks +Now it's time to partition the disk; you will be shown several options; choose `Manual` partitioning. + +1. Use the arrow keys to select the drive (look for a matching size and manufacturer name in the description), and press `Enter`. It will ask you if you want to create a new, empty partition table on the device; choose `Yes`. + +2. Your drive will now show as having a single partition, labeled `#1`; select it (it will say `FREE SPACE` beside it), and press `Enter`. + +3. Choose `Create a new partition`. By default, the partition size will be the whole drive; leave it as-is, and select `Continue`. + +4. When it asks for partition type, go with `Primary`; you'll be taken to a screen with a list of information about your new partition; make sure to fill out each field as follows (using the up and down arrows to navigate, and `Enter` to modify an option): + + * Use as: `physical volume for encryption` + * Encryption method: `Device-mapper (dm-crypt)` + * Encryption: `aes` + * key size: `256` + * IV algorithm: `xts-plain64` + * Encryption key: `passphrase` + * Erase data: `Yes` + + For the `Erase data` field, only choose `No`, if this is either a new drive that doesn't have any of your plaintext data, or else if it previously had full-disk encryption. + +5. Choose `Done setting up the partition`. It will take you back to the main partitioning menu. + +6. Choose `Configure encrypted volumes`; the installer will ask if you want to write the changes to disk, and configure the encrypted volumes; choose `Yes`. + +7. Select `Create encrypted volumes`. + +8. Select your partition with the arrow keys (pressing `Spacebar` will make an `*` appear between the brackets; that's how you know it's been selected). Press `Tab`, and choose `Continue`. + +9. Select `Finish`. You will be asked if you really want to erase the drive; choose `Yes` (Erase will take a long time, so be patient. If your old system were encrypted, just let this run for about a minute, and then choose `Cancel`; this will make sure that the LUKS header is completely wiped out). + +10. Now you need to enter a passphrase for encrypting the entire disk. Make sure that this is different from your user password that you created earlier, but still use the [diceware](http://world.std.com/~reinhold/diceware.html) method to create it. You will have to enter the password twice; afterwards, you will be returned to the main partitioning menu. + +11. You will now see your encrypted device at the top of the device list. It will begin with something like this: `Encrypted volume (sdXY_crypt)`. Choose the partition labeled `#1`. + +12. Change the value of `Use as` to `physical volume for LVM`. Then choose `Done setting up the partition`; you will be taken back to the main partitioning menu. + +13. Choose `Configure the Logical Volume Manager`. You will be asked if you want to `Keep current partition layout and configure LVM`; choose `Yes`. + +14. Choose `Create volume group`. You will have to enter a name for the group; use **grubcrypt**. Select the encrypted partition as the device (by pressing `Spacebar`, which will make an `*` appear between the brackets; that's how you know it's been selected). Press `Tab`, and choose `Continue`. + +15. Choose `Create logical volume`. Select the volume group you created in the previous step (i.e., **grubcrypt**), and name it **trisquel**; make the size the entire drive minus 2048 MB (for the swap space). Press `Enter`. + +16. Choose `Create logical volume` again, and select **grubcrypt**. Name this one **swap**, and make the size the default value (it should be about 2048MB). Press `Enter`, and then choose `Finish`. + +17. Now you are back at the main partitioning screen. You will simply set the mount points and filesystems to use for each partition you just created. Under `LVM VG grubcrypt, LV trisquel`, select the first partition: `#1`. Change the values in this section to reflect the following; then choose `Done setting up partition`: + + * use as: `ext4` + * mount point: `/` + +18. Under `LVM VG grubcrypt, LV swap`, select the first partition: `#1`. Change the value of `use as` to `swap area`. Choose `Done setting up partition`. + +19. Finally, when back at the main partitioning screen, choose `Finish partitioning and write changes to disk`. It will ask you to verify that you want to do this; choose `Yes`. + +## Installing the Base System +The hardest part of the installation is done; the installer will now download and install the packages necessary for your system to boot/run. The rest of the process will be mostly automated, but there will be a few things that you have to do yourself. + +### Choose a Kernel +It will ask you which kernel you want to use; choose `linux-generic`. + +**NOTE: After installation, if you want the most up-to-date version of the Linux kernel (Trisquel's kernel is sometimes outdated, even in the testing distro), you might consider using [this repository](https://jxself.org/linux-libre/) instead. These kernels are also deblobbed, like Trisquel's (meaning there are no binary blobs present).** + +### Update Policy +You have to select a policy for installing security updates; I recommend that you choose `Install security updates automatically`, but you can choose not to, if you prefer. + +### Choose a Desktop Environment +When prompted to choose a desktop environment, use the arrow keys to navigate the choices, and press `Spacebar` to choose an option; here are some guidelines: + +* If you want *GNOME*, choose **Trisquel Desktop Environment** +* If you want *LDXE*, choose **Trisquel-mini Desktop Environment** +* If you want *KDE*, choose **Triskel Desktop Environment** + +You might also want to choose some of the other package groups (or none of them, if you want a basic shell); it's up to you. Once you've chosen the option you want, press `Tab`, and then choose `Continue`. + +## Install the GRUB boot loader to the master boot record +The installer will ask you if you want to install the GRUB bootloader to the master boot record; choose `No`. You do not need to install GRUB at all, since in Libreboot, you are using the GRUB payload on the ROM to boot your system. + +The next window will prompt you to enter a `Device for boot loader installation`. Leave the line blank; press `Tab`, and choose `Continue`. + +## System Clock +The installer will ask if your system clock is set to UTC; choose `Yes`. + +## Finishing the Installation +The installer will now give you a message that the installation is complete. Choose `Continue`, remove the installation media, and the system will automatically reboot. + +## Booting your system +At this point, you will have finished the installation. At your GRUB boot screen, press `C` to get to the command line, and enter the following commands at the `grub>` prompt: + + grub> cryptomount -a + grub> set root='lvm/grubcrypt-trisquel' + grub> linux /vmlinuz root=/dev/mapper/grubcrypt-trisquel \ + >cryptdevice=/dev/mapper/grubcrypt-trisquel:root + grub> initrd /initrd.img + grub> boot + +Without specifying a device, **cryptomount's** `-a` parameter tries to unlock *all* detected LUKS volumes (i.e., any LUKS-encrypted device that is connected to the system). You can also specify `-u` (for a UUID). Once logged into the operating system, you can find the UUID by using the `blkid` command: + + $ sudo blkid + +## ecryptfs +If you didn't encrypt your home directory, then you can safely ignore this section; if you did choose to encrypt it, then after you log in, you'll need to run this command: + + $ sudo ecryptfs-unwrap-passphrase + +This will be needed in the future, if you ever need to recover your home directory from another system. Write it down, or (preferably) store it using a password manager (I recommend `keepass`,`keepasX`, or `keepassXC`). + +## Modify grub.cfg (CBFS) +The last step of the proccess is to modify your **grub.cfg** file (in the firmware), and flash the new configuration, [using this tutorial](grub_cbfs.md); this is so that you don't have to manually type in the commands above, every single time you want to boot your computer. You can also make your GRUB configuration much more secure, by following [this guide](grub_hardening.md). + +## Troubleshooting +During boot, some Thinkpads have a faulty DVD drive, which can cause the `cryptomount -a` command to fail, as well as the error `AHCI transfer timed out` (when the Thinkpad X200 is connected to an UltraBase). For both issues, the workaround was to remove the DVD drive (if using the UltraBase, then the whole device must be removed). + +Copyright © 2014, 2015 Leah Rowe + +Copyright © 2017 Elijah Smith + +Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License Version 1.3 or any later version published by the Free Software Foundation with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/gnulinux/grub_boot_installer.md b/i18n/fr_FR/docs/gnulinux/grub_boot_installer.md new file mode 100644 index 00000000..48ecaa37 --- /dev/null +++ b/i18n/fr_FR/docs/gnulinux/grub_boot_installer.md @@ -0,0 +1,144 @@ +--- +title: How to Prepare and Boot a USB Installer on Libreboot Systems +x-toc-enable: true +... + +This guide explains how to prepare a bootable USB for Libreboot systems that can be used to install several GNU+Linux distributions. For this guide, you will only need a USB flash drive and the `dd` utility (it's installed into all GNU+Linux distributions, by default). + +For information on actually installing specific GNU+Linux distributions, refer to [this page](index.md). + +## Prepare the USB Drive in GNU+Linux +If you downloaded your ISO while on an existing GNU+Linux system, here is how to create the bootable GNU+Linux USB drive: + +Connect the USB drive. Check `lsblk`, to confirm its device name (e.g., **/dev/sdX**): + + $ lsblk + +For this example, let's assume that our drive's name is `sdb`. Make sure that it's not mounted: + + $ sudo umount /dev/sdb + +Overwrite the drive, writing your distro ISO to it with `dd`. For example, if we are installing Trisquel 7.0 64-bit, and it's located in our Downloads folder, this is the command we would run: + + $ sudo dd if=~/Downloads/trisquel_7.0_amd64.iso of=/dev/sdb bs=8M; sync + +That's it! You should now be able to boot the installer from your USB drive (the instructions for doing so will be given later). + +## Prepare the USB drive in NetBSD +[This page](https://wiki.netbsd.org/tutorials/how_to_install_netbsd_from_an_usb_memory_stick/) on the NetBSD website shows how to create a NetBSD bootable USB drive, from within NetBSD itself. You should the `dd` method documented there. This will work with any GNU+Linux ISO image. + +## Prepare the USB drive in FreeBSD +[This page](https://www.freebsd.org/doc/handbook/bsdinstall-pre.html) on the FreeBSD website shows how to create a bootable USB drive for installing FreeBSD. Use the `dd` method documented. This will work with any GNU+Linux ISO image. + +## Prepare the USB drive in LibertyBSD or OpenBSD +If you downloaded your ISO on a LibertyBSD or OpenBSD system, here is +how to create the bootable GNU+Linux USB drive: + +Connect the USB drive. Run `lsblk` to determine which drive it is: + + $ lsblk + +To confirm that you have the correct drive, use `disklabel`. For example, if you thought the correct drive were **sd3**, run this command: + + $ disklabel sd3 + +Make sure that the device isn't mounted, with `doas`; if it is, this command will unmount it: + + $ doas umount /dev/sd3i + +`lsblk` told you what device it is. Overwrite the drive, writing the OpenBSD installer to it with `dd`. Here's an example: + + $ doas dd if=gnulinux.iso of=/dev/rsdXc bs=1M; sync + +That's it! You should now be able to boot the installer from your USB drive (the instructions for doing so will be given later). + +## Debian or Devuan net install +Download the Debian or Devuan net installer. You can download the Debian ISO +from [the Debian homepage](https://www.debian.org/), or the Devuan ISO from +[the Devuan homepage](https://www.devuan.org/). + +Secondly, create a bootable USB drive using the commands in +[#prepare-the-usb-drive-in-gnulinux](#prepare-the-usb-drive-in-gnulinux). + +Thirdly, boot the USB and enter these commands in the GRUB terminal +(for 64-bit Intel or AMD): + + grub> set root='usb0' + grub> linux /install.amd/vmlinuz + grub> initrd /install.amd/initrd.gz + grub> boot + +If you are on a 32-bit system (e.g. some Thinkpad X60's) then you will need to +use these commands (this is also true for 32-bit running on 64-bit machines): + + grub> set root='usb0' + grub> linux /install.386/vmlinuz + grub> initrd /install.386/initrd.gz + grub> boot + +NOTE FOR G41M USERS (32 bit, 64 bit): On the *linux* line, specify fb=false to +boot in text mode or the installer won't have a display on your monitor. + +## Booting ISOLINUX Images (Automatic Method) +Boot it in GRUB using the `Parse ISOLINUX config (USB)` option. A new menu should appear in GRUB, showing the boot options for that distro; this is a GRUB menu, converted from the usual ISOLINUX menu provided by that distro. + +## Booting ISOLINUX Images (Manual Method) +These are generic instructions. They may or may not be correct for your distribution. You must adapt them appropriately, for whatever GNU+Linux distribution it is that you are trying to install. + +If the `ISOLINUX parser` or `Search for GRUB configuration` options won't work, then press `C` in GRUB to access the command line, then run the `ls` command: + + grub> ls + +Get the device name from the above output (e.g., `usb0`). Here's an example: + + grub> cat (usb0)/isolinux/isolinux.cfg + +Either the output of this command will be the ISOLINUX menuentries for that ISO, or link to other `.cfg` files (e.g, **/isolinux/foo.cfg**). For example, if the file found were **foo.cfg**, you would use this command: + + grub> cat (usb0)/isolinux/foo.cfg + +And so on, until you find the correct menuentries for ISOLINUX. + +For Debian-based distros (e.g., Trisquel, Devuan), there are typically menuentries listed in **/isolinux/txt.cfg** or **/isolinux/gtk.cfg**. For dual-architecture ISO images (i686 and x86\_64), there may be separate files directories for each architecture. Just keep searching through the image, until you find the correct ISOLINUX configuration file. + +**NOTE: Debian 8.6 ISO only lists 32-bit boot options in txt.cfg. This is important, if you want 64-bit booting on your system. Devuan versions based on Debian 8.x may also have the same issue.** + +Now, look at the ISOLINUX menuentry; it'll look like this: + + kernel /path/to/kernel append PARAMETERS initrd=/path/to/initrd ... + +GRUB works similarly; here are some example GRUB commands: + + grub> set root='usb0' + grub> linux /path/to/kernel PARAMETERS MAYBE\_MORE\_PARAMETERS + grub> initrd /path/to/initrd + grub> boot + +Note: `usb0` may be incorrect. Check the output of the `ls` command (in GRUB), to see a list of USB devices/partitions. Of course, this will vary from distro to distro. If you did all of that correctly, then it should now be booting your USB drive in the way that you specified. + +## Troubleshooting +Most of these issues occur when using Libreboot with Coreboot's `text-mode`, instead of the Coreboot framebuffer. This mode is useful for booting payloads, like `MemTest86+`, which expect `text-mode`, but for GNU+Linux distributions, it can be problematic when they are trying to switch to a framebuffer, because it doesn't exist. + +In most cases, you should use the **vesafb** ROM images. An example filename would be **libreboot\_ukdvorak\_vesafb.rom**. + +### Parabola Won't Boot in Text-Mode +Use one of the ROM images with `vesafb` in the filename (uses Coreboot framebuffer, instead of `text-mode`). + +### debian-installer Graphical Corruption in Text-Mode (Debian and Devuan) +When using the ROM images that use Coreboot's `text mode`, instead of the Coreboot framebuffer, booting the Debian or Devuan net installer results in graphical corruption, because it is trying to switch to a framebuffer, which doesn't exist. Use that kernel parameter on the `linux` line, when booting it: + + vga=normal fb=false + +This forces debian-installer to start in `text-mode`, instead of trying to switch to a framebuffer. + +If selecting `text-mode` from a GRUB menu created using the ISOLINUX parser, you can press `E` on the menu entry to add this. Or, if you are booting manually (from GRUB terminal), then just add the parameters. + +This workaround was found on the [Debian site](https://www.debian.org/releases/stable/i386/ch05s04.html). It should also work for Devuan, and any other `apt-get` distro that provides the debian-installer (i.e., text-mode) net install method. + +Copyright © 2014, 2015, 2016 Leah Rowe + +Copyright © 2016 Scott Bonds + +Copyright © 2017 Elijah Smith + +Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License Version 1.3 or any later version published by the Free Software Foundation with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/gnulinux/grub_cbfs.md b/i18n/fr_FR/docs/gnulinux/grub_cbfs.md new file mode 100644 index 00000000..f6c99332 --- /dev/null +++ b/i18n/fr_FR/docs/gnulinux/grub_cbfs.md @@ -0,0 +1,398 @@ +--- +title: Modifying the GRUB Configuration in Libreboot Systems +x-toc enable: true +... + + +This guide will go through all the steps to modify a GRUB configuration file +in Libreboot; this is so that the user doesn't have to manually boot +their operating system each time, by typing in commands at the GRUB command line. + +For the purposes of this guide, you can either modify the GRUB configuration file +that resides in the computer's ROM, or else you could modify the version that +exists within the operating system itself; both options will be explained here. + +## How to Get the GRUB Configuration File +The first step of the process is to actually get a hold of the GRUB configuration file +that we need to modify. There are two ways to do this: + +1. We can extract the one that already exists within the ROM +2. We can use one of the pre-compiled ROMS supplied by the Libreboot project + +However, both ways will require us to download the Libreboot Utility Archive. + +### Download the Libreboot Utility Archive +The Libreboot Utility Archive contains the programs that we'll need +to get our **grubtest.cfg** file. The latest release of the Libreboot Utility Archive +can be downloaded [from libreboot.org](https://www.mirrorservice.org/sites/libreboot.org/release/stable/20160907/libreboot_r20160907_util.tar.xz). +The quickest way to download it would be to use the `wget` program, +which (if you don't know) allows you to download files from the internet. + +If you don't already have it installed, you can install it, +using the `apt-get` command (in Debian-based distributions): + + $ sudo apt-get install wget + +You can install it in Arch-based systems, using `pacman`: + + $ sudo pacman -S wget + +Once you've installed `wget`, use it to download the file, +simply by passing it the URL as an argument; you can save the file anywhere, +but for the purpose of this guide, save it in **~/Downloads** +(your **Home** directory's downloads folder). +First, change the current working directory to **~/Downloads**: + + $ cd ~/Downloads + +This guide assumes you are using the **20160907** version of Libreboot; +if using a different version, modify the following commands accordingly: + + $ wget https://www.mirrorservice.org/sites/libreboot.org/release/stable/20160907/\ + >libreboot_r20160907_util.tar.xz + +After the file is downloaded, use the `tar` command to extract its contents: + + $ tar -xf libreboot_r20160907_util.tar.xz + +After extraction, the folder will have the same name as the archive: in this case, +**libreboot\_r20160907\_util**. For simplicity's sake, we'll rename it **libreboot\_util**, +using the `mv` command: + + $ mv "libreboot_r20160907_util" "libreboot_util" + +Now you have the folder with all the utilities necessary to read and modify the contents of the ROM. + +### Get the Necessary Utilities +Once you have the **libreboot\_util** archive, you can find the `cbfstool` and `flashrom` +utilities in **libreboot\_util/cbfstools/x86\_64/cbfstool**, +and **libreboot\_util/flashrom/x86\_64/flashrom**, respectively. + +**NOTE: This guide assumes that you are using a device with the** x86\_64 **architecture; +if you are using a device with a different architecture (e.g.,** i686 **or** armv7l**), +the proper version of** `cbfstool` **and** `flashrom` **will be in that folder, +inside their respective directories.** + +You could also compile both of these utilities; see [How to Build flashrom](../git/#build_flashrom). + +`flashrom` is also available from the repositories; if using an Arch-based distribution, +use `pacman`: + + $ sudo pacman -S flashrom + +Or, if you have a Debian-based distribution, use `apt-get`: + + $ sudo apt-get install flashrom + +### Get the ROM Image +You can either work directly with one of the ROM images already included +in the libreboot ROM archives, or re-use the ROM that you have currently +flashed. For the purpose of this tutorial, it is assumed that your ROM +image file is named **libreboot.rom**, so please make sure to adapt. + +There are two ways to get a pre-compiled ROM image: + +#### 1. Download a Pre-Compiled Image from the Libreboot Website +For the current release, **20160907**, they can be found [on a Libreboot mirror](https://www.mirrorservice.org/sites/libreboot.org/release/stable/20160907/rom/grub/); +please adopt this guide, if using a different version of Libreboot. + +You also need to make sure that you select both the correct ROM for the device you're using, +as well as the correct flash chip size (if applicable): **4mb**, **8mb**, or **16mb**; +variable flash chip sizes only apply for the Thinkpads that Libreboot supports (excluding the X60 and T60). + +You can find the flash chip size, by running the following command: + + # flashrom -p internal + +Look for a line like this: + + Found Macronix flash chip "MX25L6406E/MX25L6408E" (8192 kB, SPI) \ + mapped at physical address 0x00000000ff800000. + +Running this command on my Thinkpad X200 gives me the above result, so I know that +my flash chip size is **8mb**. + +Once you've determined the correct ROMs and flash chip size, download them from the website. +Since I'm currently using an X200 to write this guide, I'll demonstrate how +to download the correct ROM images for that model. + +First, we're going to navigate to the **libreboot\_util** folder: + + $ cd ~/Downloads/libreboot_util/ + +Then, we will download the ROM images, using `wget`: + + $ wget https://www.mirrorservice.org/sites/libreboot.org/release/stable/\ + >20160907/rom/grub/libreboot_r20160907_grub_x200_8mb.tar.xz + +Extract the archive, using `tar`: + + $ tar -xf libreboot_r20160907_grub_x200_8mb.tar.xz + +Navigate to the directory that you just created: + + $ cd libreboot_r20160907_grub_x200_8mb + +Now that we are in the archive, we must choose the correct ROM image. +To figure out the correct image, we must first parse the filenames for each ROM. +For example, for the file named **x200_8mb_usqwerty_vesafb.rom**: + + Model Name: x200 + Flash Chip Size: 8mb + Country: us + Keyboard Layout: qwerty + ROM Type: vesafb or txtmode + +Since I am using a QWERTY keyboard, I will ignore all the non-QWERTY options. +Note that there are two types of ROMs: **vesafb** and **txtmode**; +The **vesafb** ROM images are recommended, in most cases; **txtmode** ROM images +come with `MemTest86+`, which requires text-mode, instead of the usual framebuffer +used by coreboot native graphics initialization. + +I'll choose **x200_8mb_usqwerty_vesafb.rom**; I'll copy the file (to the `cbfstool` directory), +and rename it with one command: + + $ mv "x200_8mb_usqwerty_vesafb.rom" ../cbfstool/x86_64/libreboot.rom + +#### 2. Create an Image from the Current ROM +The simpler way to get a ROM image is to just create it from your current ROM, +using `flashrom`, making sure to save it in the `cbfstool` folder, inside **libreboot\_util**: + + $ sudo flashrom -p internal -r ~/Downloads/libreboot_util/cbfstool/x86_64/libreboot.rom + +If you are told to specify the chip, add the option `-c {your chip}` to the command, like this: + + $ sudo flashrom -c MX25L6405 -p internal -r ~/Downloads/libreboot_util/cbfstool/x86_64/libreboot.rom + +Now you are ready to extract the GRUB configuration files from the ROM, and modify them the way you want. + + +### Copy grubtest.cfg from the ROM Image +You can check the contents of the ROM image, inside CBFS, using `cbfstool`. +First, navigate to the cbfstool folder: + + $ cd ~/Downloads/libreboot_util/cbfstool/x86_64/ + +Then, run the `cbfstool` commmand, with the `print` option; this will display +a list of all the files located in the ROM: + + $ ./cbfstool libreboot.rom print + +You should see **grub.cfg** and **grubtest.cfg** in the list. **grub.cfg** is +loaded by default, with a menu entry for switching to **grubtest.cfg**. In +this tutorial, you will first modify and test **grubtest.cfg**. This is to +reduce the possibility of bricking your device, so *DO NOT SKIP THIS!* + +Extract (i.e., get a copy of ) **grubtest.cfg** from the ROM image: + + $ ./cbfstool libreboot.rom extract -n grubtest.cfg -f grubtest.cfg + +By default `cbfstool` will extract files to the current working directory; +so, **grubtest.cfg** should appear in the same folder as **libreboot.rom**. + +## How to Modify the GRUB Configuration File +This section will instruct the user *how* to modify their GRUB configuration file; +whether they decide to use the version located in their operating system's **/** folder, +or the one located in the ROM, the modifications will be the same. + +Once the file is open, look for the following line (it will be towards the bottom of the file): + + menuentry 'Load Operating System [o]' --hotkey='o' --unrestricted + +After this line, there will be an opening bracket **{**, followed by a several lines +of code, and then a closing bracket **}**; delete everything that is between those two brackets, +and replace it with the following code, if you're using an Arch-based disribution (e.g., Parabola GNU+Linux-Libre): + + cryptomount -a + set root='lvm/matrix-root' + linux /boot/vmlinuz-linux-libre root=/dev/matrix/root cryptdevice=/dev/sda1:root \ + cryptkey=rootfs:/etc/mykeyfile + initrd /boot/initramfs-linux-libre.img + +Or, replace it with this, if you are using a Debian-based distribution (e.g., Trisquel GNU+Linux): + + cryptomount -a + set root='lvm/matrix-rootvol' + linux /vmlinuz root=/dev/mapper/matrix-rootvol cryptdevice=/dev/mapper/matrix-rootvol:root + initrd /initrd.img + +Remember, that these names come from the instructions to install GNU+Linux +on Libreboot systems, located [in the docs](index.md). If you followed different instructions, +(or for some other reason, used different names), simply put the names +of your **root** and **swap** volumes, in place of the ones used here. + +This covers the basic changes that we can make to GRUB; however, there are some more +changes that you could make, to increase the security of your GRUB configuration. +If you are interested in those modifications, see the Libreboot guide on [Hardening GRUB](grub_hardening.md). + +That's it for the modifications! Now all you need to do is follow the instructions below, +in order to use this new configuration to boot your system. + +## Change the GRUB Configuration File that the Operating System Uses +Now that we have explained *how* to modify the file itself, we need to explain +how to actually make our system *use* the new GRUB configuration file to boot. + +### Without Re-Flashing the ROM +To change the GRUB Configuration that our system uses, without having to re-flash the ROM, +we need to take our **grubest.cfg** file, rename it to **libreboot\_grub**; +this is because that, by default, GRUB in Libreboot is configured to scan all partitions on +the main storage for **/boot/grub/libreboot\_grub.cfg** or **/grub/libreboot\_grub.cfg** +(for systems where **/boot** is on a dedicated partition), and then use it automatically. + +Therefore, we need to either copy **libreboot\_grub.cfg** to **/grub**, or to **/boot/grub**: + + $ sudo cp ~/Downloads/libreboot_util/cbfstool/x86_64/libreboot_grub.cfg /boot/grub # or /grub + +Now, the next time we boot our computer, GRUB (in Libreboot) will automatically switch +to this configuration file. *This means that you do not have to re-flash, +recompile, or otherwise modify Libreboot at all!* + +### With Re-Flashing the ROM +Changing the GRUB configuration that resides in ROM is a bit more complicated +that the one in **/**, but most of the hard work is already done. + +#### Change grubtest.cfg in ROM +Now that you have the modified **grubtest.cfg**, we need to remove +the old **grubtest.cfg** from the ROM, and put in our new one. To remove +the old one, we will use `cbfstool`: + + $ ./cbfstool libreboot.rom remove -n grubtest.cfg + +Then, add the new one to the ROM: + + $ ./cbfstool libreboot.rom add -n grubtest.cfg -f grubtest.cfg -t raw + +#### Change MAC address in ROM {#changeMAC} +The last step before flashing the new ROM, is to change the MAC address inside it. +Every libreboot ROM image contains a generic MAC address; you want to make sure +that your ROM image contains yours, so as to not create any problems on your network +(say, for example, that multiple family members had libreboot computers, and used +the same ROM image to flash those computers). + +To do this, we will use the `ich9gen` utility, also located in **libreboot_util**. + +First, you need to find the current MAC address of your computer; there are +two ways to do this: + +1. Read the white label on the bottom of the case (however, this will only work, +if your motherboard has never been replaced). +2. Run `ifconfig`; look for your ethernet device (e.g., **enpXXX** +in Arch-based distributions, or **eth0** in Debian-based distributions), +and look for a set of characters like this: `00:f3:f0:45:91:fe`. + +Next, you need to move **libreboot.rom** to the following folder; this is where +the executable for `ich9gen` is located: + + $ mv libreboot.rom ~/Downloads/libreboot_r20160907_util/ich9deblob/x86_64 + +Once there, run the following command, making sure to use your own MAC address, +instead of what's written below: + + $ ./ich9gen --macaddress XX:XX:XX:XX:XX:XX + +Three new files will be created: + +* **ich9fdgbe_4m.bin**: this is for GM45 laptops with the 4MB flash chip. +* **ich9fdgbe_8m.bin**: this is for GM45 laptops with the 8MB flash chip. +* **ich9fdgbe_16m.bin**: this is for GM45 laptops with the 16MB flash chip. + +Look for the one that corresponds to the size of your ROM image; for example, +if your flash chip size is **8mb**, you'll want to use **ich9fdgbe_8m.bin**. + +Now, insert this file (called the `descriptor+gbe`) into the ROM image, using `dd`: + + $ dd if=ich9fdgbe_8m.bin of=libreboot.rom bs=1 count=12k conv=notrunc + +Move **libreboot.rom** back to the **libreboot\_util** directory: + + $ mv libreboot.rom ~/Downloads/libreboot_util + +You are finally ready to flash the ROM! + +#### Flash Updated ROM Image +The last step of flashing the ROM requires us to change our current working directory +to **libreboot\_util**: + + $ cd ~/Downloads/libreboot_util + +Now, all we have to do is use the `flash` script in this directory, +with the `update` option, using **libreboot.rom** as the argument: + + $ sudo ./flash update libreboot.rom + +Ocassionally, coreboot changes the name of a given board. If `flashrom` +complains about a board mismatch, but you are sure that you chose the +correct ROM image, then run this alternative command: + + $ sudo ./flash forceupdate libreboot.rom + +You will see the `flashrom` program running for a little while, and you might see errors, +but if it says `Verifying flash... VERIFIED` at the end, then it’s flashed, +and should boot. If you see errors, try again (and again, and again). +The message, `Chip content is identical to the requested image` is also +an indication of a successful installation. + +#### Reboot the Computer +Now that you have flashed the image, reboot the computer. Keep pressing `spacebar` +right after you turn it on, until you see the GRUB menu, to prevent libreboot +from automatically trying to load the operating system. + +Scroll down with the arrow keys, and choose the `Load test configuration (grubtest.cfg) inside of CBFS` option; +this will switch the GRUB configuration to your test version. If all goes well, +it should prompt you for a GRUB username and password, and then your LUKS password. + +Once the operating system starts loading, it will prompt you for your LUKS password again. +If it continues, and loads into the OS without errors, then that means your flashing +attempt was a success. + +#### Final Steps +When you are satisfied booting from **grubtest.cfg**, you can create a copy +of **grubtest.cfg**, called **grub.cfg**. + +First, go to the `cbfstool` directory: + + $ cd ~/Downloads/libreboot_util/cbfstool/x86_64/ + +Then, create a copy of **grubest.cfg**, named **grub.cfg**: + + $ cp grubtest.cfg ./grub.cfg + +Now you will use the `sed` command to make several changes to the file: +the menu entry `'Switch to grub.cfg'` will be changed to `Switch to grubtest.cfg`, +and inside it, all instances of **grub.cfg** to **grubtest.cfg**. +This is so that the main configuration still links (in the menu) to **grubtest.cfg**, +so that you don't have to manually switch to it, in case you ever want to follow +this guide again in the future (modifying the already modified config).: + + $ sed -e 's:(cbfsdisk)/grub.cfg:(cbfsdisk)/grubtest.cfg:g' -e \ + >'s:Switch to grub.cfg:Switch to grubtest.cfg:g' < grubtest.cfg > \ + >grub.cfg + +Move **libreboot.rom** from **libreboot\_util** to your current directory: + + $ mv ~/Downloads/libreboot_util/libreboot.rom . + +Delete the **grub.cfg** that's already inside the ROM: + + $ ./cbfstool libreboot.rom remove -n grub.cfg + +Add your modified **grub.cfg** to the ROM: + + $ ./cbfstool libreboot.rom add -n grub.cfg -f grub.cfg -t raw + +Move **libreboot.rom** back to **libreboot\_util**: + + $ mv libreboot.rom ../.. + +If you don't remember how to flash it, refer back to the *Flash Updated ROM Image*, above; it's the same method as you used before. Afterwards, reboot the machine with your new configuration. + +Copyright © 2014, 2015, 2016 Leah Rowe + +Copyright © 2017 Elijah Smith + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) + diff --git a/i18n/fr_FR/docs/gnulinux/grub_hardening.md b/i18n/fr_FR/docs/gnulinux/grub_hardening.md new file mode 100644 index 00000000..e1329f21 --- /dev/null +++ b/i18n/fr_FR/docs/gnulinux/grub_hardening.md @@ -0,0 +1,185 @@ +--- +title: GRUB hardening +... + +This guide deals with various ways in which you can harden your GRUB +configuration, for security purposes. These steps are optional, but +highly recommended by the Libreboot project. + +GRUB secure boot with GPG +========================= + +This uses the free implementation of the GPG standard for encryption and +signing/verifying data. We will be using this for checking the signature +of a Linux kernel at boot time. More information about GPG can be found +on the [GPG project website](https://www.gnu.org/software/gnupg/). GRUB +has some GPG support built in, for checking signatures. + +This tutorial assumes you have a libreboot image (rom) that you wish to +modify, to which we shall henceforth refer to as "my.rom". This +tutorial modifies grubtest.cfg, this means signing and password +protection will work after switching to it in the main boot menu and +bricking due to incorrect configuration will be impossible. After you +are satisfied with the setup, you should transfer the new settings to +grub.cfg to make your machine actually secure. + +First extract the old grubtest.cfg and remove it from the libreboot +image: + + cbfstool my.rom extract -n grubtest.cfg -f my.grubtest.cfg + cbfstool my.rom remove -n grubtest.cfg + +Helpful links: + +- [GRUB manual](https://www.gnu.org/software/grub/manual/html_node/Security.html#Security) +- [GRUB info pages](http://git.savannah.gnu.org/cgit/grub.git/tree/docs/grub.texi) +- [SATA connected storage considered dangerous.](../../faq.md#hddssd-firmware) +- [Coreboot GRUB security howto](https://www.coreboot.org/GRUB2#Security) + +GRUB Password +============= + +The security of this setup depends on a good GRUB password as GPG +signature checking can be disabled through the interactive console: + + set check_signatures=no + +This is good in that it allows you to occasionally boot unsigned liveCDs +and such. You may think of supplying signatures on an usb key, but the +signature checking code currently looks for +.sig when verifying +and as such it is not possible to supply signatures in an alternate +location. + +Note that this is not your LUKS password, but it's a password that you +have to enter in order to use "restricted" functionality (such as +console). This protects your system from an attacker simply booting a +live USB and re-flashing your firmware. *This should be different than +your LUKS passphrase and user password.* + +Use of the *diceware method* is recommended, for generating secure +passphrases (as opposed to passwords). Diceware method involves using +dice to generate random numbers, which are then used as an index to pick +a random word from a large dictionary of words. You can use any language +(e.g. English, German). Look it up on a search engine. Diceware method +is a way to generate secure passphrases that are very hard (almost +impossible, with enough words) to crack, while being easy enough to +remember. On the other hand, most kinds of secure passwords are hard to +remember and easier to crack. Diceware passphrases are harder to crack +because of far higher entropy (there are many words available to use, +but only about 50 commonly used symbols in pass*words*). + +--> +The GRUB password can be entered in two ways: + +- plaintext +- protected with [PBKDF2](https://en.wikipedia.org/wiki/Pbkdf2) + +We will (obviously) use the later. Generating the PBKDF2 derived key is +done using the `grub-mkpasswd-pbkdf2` utility. You can get it by +installing GRUB version 2. Generate a key by giving it a password: + grub-mkpasswd-pbkdf2 + +Its output will be a string of the following form: + + grub.pbkdf2.sha512.10000.HEXDIGITS.MOREHEXDIGITS + +Now open my.grubtest.cfg and put the following before the menu entries +(prefered above the functions and after other directives). Of course use +the pbdkf string that you had generated yourself: + + set superusers="root" + password_pbkdf2 root grub.pbkdf2.sha512.10000.711F186347156BC105CD83A2ED7AF1EB971AA2B1EB2640172F34B0DEFFC97E654AF48E5F0C3B7622502B76458DA494270CC0EA6504411D676E6752FD1651E749.8DD11178EB8D1F633308FD8FCC64D0B243F949B9B99CCEADE2ECA11657A757D22025986B0FA116F1D5191E0A22677674C994EDBFADE62240E9D161688266A711 + +Obviously, replace it with the correct hash that you actually got for +the password that you entered. Meaning, not the hash that you see above! + +As enabling password protection as above means that you have to input it +on every single boot, we will make one menu entry work without it. +Remember that we will have GPG signing active, thus a potential attacker +will not be able to boot an arbitrary operating system. We do this by +adding option `--unrestricted` to a menuentry definition: + + menuentry 'Load Operating System (incl. fully encrypted disks) [o]' --hotkey='o' --unrestricted { + ... + +Another good thing to do, if we chose to load signed on-disk GRUB +configurations, is to remove (or comment out) `unset superusers` in +function try\_user\_config: + + function try_user_config { + set root="${1}" + for dir in boot grub grub2 boot/grub boot/grub2; do + for name in '' autoboot_ libreboot_ coreboot_; do + if [ -f /"${dir}"/"${name}"grub.cfg ]; then + #unset superusers + configfile /"${dir}"/"${name}"grub.cfg + fi + done + done + } + +Why? We allowed booting normally without entering a password above. When +we unset superusers and then load a signed GRUB configuration file, we +can easily use the command line as password protection will be +completely disabled. Disabling signature checking and booting whatever +an attacker wants is then just a few GRUB commands away. + +As far as basic password setup is concerned we are done and we can now +move on to signing. + +GPG keys +======== + +First generate a GPG keypair to use for signing. Option RSA (sign only) +is ok. + +Warning: GRUB does not read ASCII armored keys. When attempting to +trust ... a key filename it will print error: bad signature + + mkdir --mode 0700 keys + gpg --homedir keys --gen-key + gpg --homedir keys --export-secret-keys --armor > boot.secret.key # backup + gpg --homedir keys --export > boot.key + +Now that we have a key, we can sign some files with it. We have to sign: + +- a kernel +- (if we have one) an initramfs +- (if we wish to transfer control to it) an on-disk grub.cfg +- grubtest.cfg (this is so one can go back to grubtest.cfg after + signature checking is enforced. You can always get back to grub.cfg + by pressing ESC, but afterwards grubtest.cfg is not signed and it + will not load. + +Suppose that we have a pair of `my.kernel` and `my.initramfs` and an +on-disk `libreboot_grub.cfg`. We sign them by issuing the following +commands: + + gpg --homedir keys --detach-sign my.initramfs + gpg --homedir keys --detach-sign my.kernel + gpg --homedir keys --detach-sign libreboot_grub.cfg + gpg --homedir keys --detach-sign my.grubtest.cfg + +Of course some further modifications to my.grubtest.cfg will be +required. We have to trust the key and enable signature enforcement (put +this before menu entries): + + trust (cbfsdisk)/boot.key + set check_signatures=enforce + +What remains now is to include the modifications into the image (rom): + + cbfstool my.rom add -n boot.key -f boot.key -t raw + cbfstool my.rom add -n grubtest.cfg -f my.grubtest.cfg -t raw + cbfstool my.rom add -n grubtest.cfg.sig -f my.grubtest.cfg.sig -t raw + +... and flashing it. + +Copyright © 2017 Fedja Beader \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/gnulinux/guix_system.md b/i18n/fr_FR/docs/gnulinux/guix_system.md new file mode 100644 index 00000000..2fad5d99 --- /dev/null +++ b/i18n/fr_FR/docs/gnulinux/guix_system.md @@ -0,0 +1,383 @@ +--- +title: Guix System with Full Disk Encryption on Libreboot +... + +Objective +========= + +To provide step-by-step guide for setting up guix system (stand-alone guix) +with full disk encryption (including /boot) on devices powered by libreboot. + +Scope +===== + +Any users, for their generalised use cases, need not stumble away from this +guide to accomplish the setup. + +Advanced users, for deviant use cases, will have to explore outside this +guide for customisation; although this guide provides information that is +of paramount use. + +Process +======= + +Preparation +----------- + +In your current GNU/Linux System, open terminal as root user. + +Insert USB drive and get the USB device name /dev/sdX, where “X” is the +variable to make a note of. + +`lsblk` + +Unmount the USB drive just in case if it’s auto-mounted. + +`umount /dev/sdX` + +Download the latest (a.b.c) Guix System ISO Installer Package (sss) and +it’s GPG Signature; where “a.b.c” is the variable for version number and +“sss” is the variable for system architecture. + +`wget https://ftp.gnu.org/gnu/guix/guix-system-install-a.b.c.sss-linux.iso.xz` + +`wget https://ftp.gnu.org/gnu/guix/guix-system-install-a.b.c.sss-linux.iso.xz.sig` + +Import required public key. + +`gpg --keyserver pool.sks-keyservers.net --recv-keys 3CE464558A84FDC69DB40CFB090B11993D9AEBB5` + +Verify the GPG Signature of the downloaded package. + +`gpg --verify guix-system-install-a.b.c.sss-linux.iso.xz.sig` + +Extract the ISO Image from the downloaded package. + +`xz -d guix-system-install-a.b.c.sss-linux.iso.xz` + +Write the extracted ISO Image to the USB drive. + +`dd if=guix-system-install-a.b.c.sss-linux.iso of=/dev/sdX; sync` + +Reboot the device. + +`reboot` + +Pre-Installation +---------------- + +On reboot, as soon as you see the Libreboot Graphic Art, press arrow keys +to change the menu entry. + +Choose “Search for GRUB2 configuration on external media [s]” and wait +for the Guix System from USB drive to load. + +Set your keyboard layout lo, where “lo” is the two-letter keyboard layout +code (example: us or uk). + +`loadkeys lo` + +Unblock network interfaces (if any). + +`rfkill unblock all` + +Get the names of your network interfaces. + +`ifconfig -a` + +Bring your required network interface nwif (wired or wireless) up, where +“nwif” is the variable for interface name. For wired connections, +this should be enough. + +`ifconfig nwif up` + +For wireless connection, create a configuration file using text editor, +where “fname” is the variable for any desired filename. + +`nano fname.conf` + +Choose, type and save ONE of the following snippets, where ‘nm’ is the +name of the network you want to connect, ‘pw’ is the corresponding +network’s password or passphrase and ‘un’ is user identity. + +For most private networks: +``` +network={ + ssid="nm" + key_mgmt=WPA-PSK + psk="pw" +} +``` + +(or) + +For most public networks: +``` +network={ + ssid="nm" + key_mgmt=NONE +} +``` + +(or) + +For most organisational networks: +``` +network={ + ssid="nm" + scan_ssid=1 + key_mgmt=WPA-EAP + identity="un" + password="pw" + eap=PEAP + phase1="peaplabel=0" + phase2="auth=MSCHAPV2" +} +``` + +Connect to the configured network, where “fname” is the filename and +“nwif” is the network interface name. + +`wpa_supplicant -c fname.conf -i nwif -B` + +Assign an IP address to your network interface, where “nwif” is the +network interface name. + +`dhclient -v nwif` + +Obtain the device name /dev/sdX in which you would like to deploy and +install Guix System, where “X” is the variable to make a note of. + +`lsblk` + +Wipe the respective device. Wait for the command operation to finish. + +`dd if=/dev/urandom of=/dev/sdX; sync` + +Load device-mapper module in the current kernel. + +`modprobe dm_mod` + +Partition the respective device. Just do, GPT --> New --> Write --> Quit; +defaults will be set. + +`cfdisk /dev/sdX` + +Encrypt the respective partition. + +`cryptsetup -v --cipher serpent-xts-plain64 --key-size 512 --hash whirlpool --iter-time 500 --use-random --verify-passphrase luksFormat /dev/sdX1` + +Obtain and note down the “LUKS UUID”. + +`cryptsetup luksUUID /dev/sdX1` + +Open the respective encrypted partition, where “partname” is any +desired partition name. + +`cryptsetup luksOpen /dev/sdX1 partname` + +Make filesystem on the respective partition, where “fsname” is any +desired filesystem name. + +`mkfs.btrfs -L fsname /dev/mapper/partname` + +Mount the respective filesystem under the current system. + +`mount LABEL=fsname /mnt` + +Create a swap file and make it readable cum writable only by root. + +`dd if=/dev/zero of=/mnt/swapfile bs=1MiB count=2048` + +`chmod 600 /mnt/swapfile` + +`mkswap /mnt/swapfile` + +`swapon /mnt/swapfile` + +Installation +------------ + +Make the installation packages to be written on the respective +mounted filesystem. + +`herd start cow-store /mnt` + +Create the required directory. + +`mkdir /mnt/etc` + +Create, edit and save the configuration file by typing the following +code snippet. WATCH-OUT for variables in the code snippet and +replace them with your relevant values. + +`nano /mnt/etc/config.scm` + +Snippet: + +``` +(use-modules + (gnu) + (gnu system nss)) +(use-service-modules + xorg + desktop) +(use-package-modules + certs + gnome) +(operating-system + (host-name "hostname") + (timezone "Zone/SubZone") + (locale "ab_XY.1234") + (keyboard-layout + (keyboard-layout + "xy" + "altgr-intl")) + (bootloader + (bootloader-configuration + (bootloader + (bootloader + (inherit grub-bootloader) + (installer #~(const #t)))) + (keyboard-layout keyboard-layout))) + (mapped-devices + (list + (mapped-device + (source + (uuid "luks-uuid")) + (target "partname") + (type luks-device-mapping)))) + (file-systems + (append + (list + (file-system + (device + (file-system-label "fsname")) + (mount-point "/") + (type "btrfs") + (dependencies mapped-devices))) + %base-file-systems)) + (users + (append + (list + (user-account + (name "username") + (comment "Full Name") + (group "users") + (supplementary-groups '("wheel" "netdev" "audio" "video" "lp" "cdrom" "tape" "kvm")))) + %base-user-accounts)) + (packages + (append + (list + nss-certs) + %base-packages)) + (services + (append + (list + (extra-special-file "/usr/bin/env" + (file-append coreutils "/bin/env")) + (set-xorg-configuration + (xorg-configuration + (keyboard-layout keyboard-layout))) + (service gnome-desktop-service-type)) + %desktop-services)) + (name-service-switch %mdns-host-lookup-nss)) +``` + +Initialise new Guix System. + +`guix system init /mnt/etc/config.scm /mnt` + +Reboot the device. + +`reboot` + +Post-Installation +------------ + +On reboot, as soon as you see the Libreboot Graphic Art, choose +the option 'Load Operating System [o]' + +Enter LUKS Key, for libreboot's grub, as prompted. + +You may have to go through warning prompts by repeatedly +pressing the "enter/return" key. + +You will now see guix's grub menu from which you can go with the +default option. + +Enter LUKS Key again, for kernel, as prompted. + +Upon GNOME Login Screen, login as "root" with password field empty. + +Open terminal from the GNOME Dash. + +Set passkey for "root" user. Follow the prompts. + +`passwd root` + +Set passkey for "username" user. Follow the prompts. + +`passwd username` + +Update the guix distribution. Wait for the process to finish. + +`guix pull` + +Update the search paths. + +`export PATH="$HOME/.config/guix/current/bin:$PATH"` + +`export INFOPATH="$HOME/.config/guix/current/share/info:$INFOPATH"` + +Update the guix system. Wait for the process to finish. + +`guix system reconfigure /etc/config.scm` + +Reboot the device. + +`reboot` + +Conclusion +========== + +Everything should be stream-lined from now. You can follow your +regular boot steps without requiring manual intervention. You can +start logging in as regualar user with the respective "username". + +You will have to periodically (at your convenient time) login as root +and do the update/upgrade part of post-installation section, to keep your +guix distribution and guix system updated. + +That is it! You have now setup guix system with full-disk encryption +on your device powered by libreboot. Enjoy! + +References +========== + +[1] Guix Manual (http://guix.gnu.org/manual/en/). + +[2] Libreboot Documentation (https://libreboot.org/docs/). + +Acknowledgements +================ + +[1] Thanks to Guix Developer, Clement Lassieur (clement@lassieur.org), +for helping me with the Guile Scheme Code for the Bootloader Configuration. + +[2] Thanks to Libreboot Founder and Developer, +Leah Rowe (leah@libreboot.org), for helping me to understand the +libreboot’s functionalities better. + +License +======= + +Copyright (C) 2019 RAGHAV "RG" GURURAJAN (raghavgururajan@disroot.org). + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License, Version 1.3 +or any later version published by the Free Software Foundation; +with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. + +A copy of the license can be found at +"https://www.gnu.org/licenses/fdl-1.3.en.html". \ No newline at end of file diff --git a/i18n/fr_FR/docs/gnulinux/index.md b/i18n/fr_FR/docs/gnulinux/index.md new file mode 100644 index 00000000..c5da22e9 --- /dev/null +++ b/i18n/fr_FR/docs/gnulinux/index.md @@ -0,0 +1,60 @@ +--- +title: Instructions d'installations de distributions GNU+Linux +... + +Cette sections explique comment se débrouiller avec des systèmes d'exploitations variés (GNU+Linux and non-GNU+Linux) dans Libreboot (e.g. Créer des clef USB démarrables, Installer des systèmes d'exploitations, Changer le menu par défaut de GRUB, etc.). + +**NOTE: Cette section est seulement pour la charge utile GRUB. Pour la charge utile depthcharge (utilisée sur les appareils CrOS, comme le Chromebook ASUS C201), des instructions sont encore à écrire.** + +Libreboot utilise la charge utile GRUB par défaut, ce qui veut dire que le fichier de configuration GRUB (d'où le menu GRUB apparait) est stocké directement aux côtés de Libreboot et sa charge utile exécutable GRUB, dans la puce de flashage. +Dans le contexte, celà veut dire qu'installer des distributions et les administrer est légérement différent comparé à un système BIOS traditionnel. + +Dans la majorité des systèmes, **/boot** (le dossier qui contient tout les fichiers nécessaires pour le démarrage de votre système d'exploitation) doit être sur sa propre partition et non chiffré (alors que les autres partitions sont chiffrées); c'est pour celà que GRUB (et donc le kernel) peut être chargé et exécuté puisque un micrologiciel traditionnel ne peut pas ouvrir un volume LUKS. + +Cependant avec Libreboot, GRUB est déjà inclus en tant que charge utile donc même *boot* peut être chiffré : celà protège **/boot** des altérations apportés par quelqu'un qui aurait un accès physique à la machine. + +- [Comment préparer et démarrer un installateur USB dans les systèmes Libreboot](grub_boot_installer.md) + +- [Modifier la configuration GRUB dans les systèmes Libreboot](grub_cbfs.md) + +- [Distribution Guix avec chiffrement du disque en entier sur Libreboot](guix_system.md) + +- [Installer Parabola ou Arch GNU+Linux-libre, avec chiffrement du disque en entier (incluant /boot)](encrypted_parabola.md) + + - Tutoriel suivant [Configurer Parabola (Après l'installation)](configuring_parabola.md) + +- [Installer Hyperbola GNU+Linux, avec chiffrement du disque en entier (incluant /boot)](https://wiki.hyperbola.info/en:guide:encrypted_installation) + +- [Installer Trisquel GNU+Linux-Libre, avec chiffrement du disque en entier (incluant /boot)](encrypted_trisquel.md) + +- [Installer Debian ou Devuan GNU+Linux-Libre, avec chiffrement du disque en entier (incluant /boot)](encrypted_debian.md) + +- [Comment renforcer en sécurité votre configuration GRUB](grub_hardening.md) + + +Fedora ne veut pas démarrer ? +------------------ + +Ce qui suit peut s'appliquer aussi à CentOS ou Redhat. +Quand vous utilisez la configuration GRUB par défaut de Libreboot, et que libreboot-grub utilise +le grub.cfg (dans /boot/grub2/grub.cfg) de Fedora, Fedora utilise par défaut la commande +`linux16`, alors que ça devrait être `linux` + +Faites ceci dans Fedora: + +- Ouvrez `/etc/grub.d/10_linux` + +- Mettez la variable `sixteenbit` à jour avec une chaîne de charactères vide puis exécutez : + + grub2-mkconfig -o /boot/grub2/grub.cfg + + +Copyright © 2014, 2015 Leah Rowe + +Copyright © 2017 Elijah Smith + +Permission est donnée de copier, distribuer et/ou modifier ce document +sous les termes de la Licence de documentation libre GNU version 1.3 ou +quelconque autre versions publiées plus tard par la Free Software Foundation +sans Sections Invariantes, Textes de Page de Garde, et Textes de Dernière de Couverture. +Une copie de cette license peut être trouvé dans [fdl-1.3.md](fdl-1.3.md). diff --git a/i18n/fr_FR/docs/grub/grubeditor.md b/i18n/fr_FR/docs/grub/grubeditor.md new file mode 100644 index 00000000..628d184f --- /dev/null +++ b/i18n/fr_FR/docs/grub/grubeditor.md @@ -0,0 +1,121 @@ +# GRUB EDITOR + +Libreboot ROM images now support fluid _grub.cfg_ and _grubtest.cfg_ +configuration editing with the grubeditor.sh script! Instead of manually running +cbfstool to manipulate these configuration files, this script will handle the +work for you so you can focus on actually modifying your GRUB configuration +files to your setup's needs. + +At the time of this writing, grubeditor.sh supports extracting and editing +either the grub.cfg or grubtest.cfg file in any cbfstool-compatible Libreboot +ROM image that contains these files, even ones that have been previously +modified. It can also swap these configuration files in an existing ROM image, +handy if you have a working grubtest.cfg and want to make it the default or if +you broke the main grub.cfg and know that your grubtest.cfg still works. Lastly, +it can also run diff on these two configuration files to show you how they +differ. + +## Requirements + +grubeditor.sh requires an x86, x86\_64, or armv7l environment, since these are +the environments for which cbfstools binaries are provided. Additionally, +grubeditor.sh needs a Bash environment with extended getopt functionality that +can run the **diff** command and write to /tmp. Lastly, the script expects to +live in the top directory of the Libreboot utilities package so it can properly +call cbfstool. + +Chances are that you already meet these requirements if you are on a Linux +environment of the listed architectures and downloaded the Libreboot utilities +package from an official source. If not, it shouldn't be too hard to use a +Linux LiveCD of your choice which provides these essentials. + +Optionally, you should make sure your EDITOR variable is set. Otherwise, +grubeditor.sh will default to using vi, which may not exist on your system. You +can override this default or the contents of your EDITOR variable using the +**-e** or **--editor** command. + +## Usage help + +grubeditor.sh takes a number of options, the only one which is required being a +valid Libreboot ROM image that uses the GRUB2 payload and contains both +_grub.cfg_ and _grubtest.cfg_ files. Additional options should come _before_ the +ROM image file on the command line. + +grubeditor.sh supports combining several short options with a single hyphen +like **-ris**, but you can also list them separately like **-r -i -s**. Long +options must always be written as standalone arguments. + +You can use the **-h** or **--help** option to view a brief summary of the +options available. Consider this guide a more extensive version of this screen. + +Lastly, you can check which version of grubeditor.sh you are using with the +**-v** or **--version** option. + +## Editing configuration files + +Invoked without any arguments except for the ROM image, grubeditor.sh will +attempt to extract the _grubtest.cfg_ file from the provided ROM image and +launch it in your editor of choice. If you make changes to the file, +grubeditor.sh will incorporate your changes into a new ROM image with the same +name in the same directory, except that the new ROM file will end with +".modified". You can then flash this ROM image to your platform's BIOS chip. + +If you would prefer to edit the actual _grub.cfg_ configuration file, use the +**-r** or the **--realcfg** option. Everything else will work the same except +that your editor will open the _grub.cfg_ instead. + +If you would prefer to overwrite your existing ROM image instead of creating a +new one ending in ".modified" use the **-i** or **--inplace** option. +Naturally, you can combine this option with the **-r/--realcfg** option +described above. + +## Swapping grub.cfg and grubtest.cfg + +grubeditor.sh supports swapping the _grub.cfg_ and _grubtest.cfg_ configuration +files with the **-s** or **--swap** option. This will create a new ROM image +alongside the existing ROM image ending with ".modified" which has these files +swapped. Naturally, you can request this operation overwrite the existing file +instead using the **-i/--inplace** option. + +Note that the script will automatically modify the "Load test configuration +(grubtest.cfg)" menu entry in both configuration files during this operation. +If this was not done, these entries would end up being self-referential after +the rename, breaking their intended functionality of changing between the +configuration files. + +For best results, please do not modify this section without studying the source +code of _grubeditor.sh_ and making sure your edits do not impact the script's +ability to perform this modification + +## Swapping grub.cfg and grubtest.cfg + +grubeditor.sh supports comparing _grub.cfg_ and _grubtest.cfg_ files for +differences with the **-d** or **--diffcfg** option. This uses the diff command +by default, but if you want to use another program (e.g. vimdiff), you can +specify it with the **-D** or **--differ** option. Note that this mode is only +intended to show differences in the files and does not support updating the +configs themselves, so any changes you make in an interactive differ will be +ignored. + +## Extracting a configuration file + +You can simply extract a configuration file using the **-x** or **--extract** +option. This option is responsive to the **-r/--realcfg** option for choosing +between grubtest.cfg and grub.cfg. + +## Pending development + +TODO: +- allow injecting configuration files to complement the extractor. +- detect potentially devastating corner cases, however rare they may actually be +- i can't specify a quoted command line with arguments to -e or -D, why? +- support editing both config files if using an interactive differ +- work with other types of files besides the grub configuration files. + +## Conclusion + +I hope that grubeditor.sh will significantly ease modifying your configuration +files in your Libreboot ROM files. + +Should you find any bugs or want any feature requests, please don't hesitate to +email me or bug me on IRC. diff --git a/i18n/fr_FR/docs/grub/index.md b/i18n/fr_FR/docs/grub/index.md new file mode 100644 index 00000000..65d4863f --- /dev/null +++ b/i18n/fr_FR/docs/grub/index.md @@ -0,0 +1,103 @@ +--- +title: GRUB payload +x-toc-enable: true +... + +This section relates to the GRUB payload used in libreboot. + +Changing the background image in GRUB +===================================== + +Use cbfstool from libreboot\_util, or +libreboot\_src/coreboot/util/cbfstool/ if you want to build from source. + + $ ./cbfstool yourrom.rom remove background.png -n background.png + $ ./cbfstool yourrom.rom add -f background.png -n background.png -t raw + +When you've done this, re-flash your ROM and you should have a new +background at boot time. + +Setting font in GRUB (for reference) +==================================== + +You don't need to do this unless you would like to change the default +font yourself. (this is just for reference. It has already been done for +you) + +The old font used was Unifont, and this had some missing characters: for +instance, the border showed ??? characters instead of lines. + +I tried DeJavu Sans Mono from this website: +[dejavu-fonts.org](http://dejavu-fonts.org/wiki/Download) + +Specifically, the version that I chose was the latest at the time of +writing (Saturday 21 June 2014): [this +one](http://sourceforge.net/projects/dejavu/files/dejavu/2.34/dejavu-fonts-ttf-2.34.tar.bz2) + +This is a free font that is also contained in GNU+Linux distributions +like Debian, Devuan or Parabola. + + $ cd libreboot\_src/grub + +compile grub (the build scripts info on how to do this)\ +come back out into libreboot\_src/resources/grub: + + $ cd ../libreboot\_src/resources/grub/font + +I took Dejavu Sans Mono from dejavu (included in this version of +libreboot) and did: + + $ ../../../grub/grub-mkfont -o dejavusansmono.pf2 dejavu-fonts-ttf-2.34/ttf/DejaVuSansMono.ttf + +I then added the instructions to 'gen.sh' script in grub-assemble to +include resources/grub/dejavusansmono.pf2 in all of the ROM images, at +the root of the GRUB memdisk.\ +I then added that instructions to the grub.cfg files (to load the +font): + + loadfont (memdisk)/dejavusansmono.pf2 + +GRUB keyboard layouts (for reference) +===================================== + +Custom keyboard layout in GRUB (for reference) +---------------------------------------------- + +Keymaps are stored in resources/utilities/grub-assemble/keymap/. + +Example (French Azerty): + + $ ckbcomp fr > frazerty + +Go in grub directory: + + $ cat frazerty | ./grub/grub-mklayout -o frazerty.gkb + +You must make sure that the files are named keymap and keymap.gkb (where +'keymap' can be whatever you want). + +Then from the above example, you would put `frazerty` in +`resources/utilities/grub-assemble/keymap/original/` and the +`frazerty.gkb` file goes under +`resources/utilities/grub-assemble/keymap/` + +The build scripts will automatically see this, and automatically build +ROM images with your custom layout (given the name) and include them +under bin. Example: `libreboot_frazerty.rom`. + +UK Dvorak keyboard layout in GRUB (for reference) +------------------------------------------------- + +ukdvorak had to be created manually, based on usdvorak. diff them (under +resources/utilities/grub-assemble/keymap/original) to see how ukdvorak +file was created + + $ cat ukdvorak | ./grub/grub-mklayout -o ukdvorak.gkb + +Copyright © 2014 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/c201.md b/i18n/fr_FR/docs/hardware/c201.md new file mode 100644 index 00000000..2fd9b973 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/c201.md @@ -0,0 +1,183 @@ +--- +title: ASUS Chromebook C201 +x-toc-enable: true +... + +This is a Chromebook, using the Rockchip RK3288 SoC. It uses an ARM CPU, +and has free EC firmware (unlike some other laptops). More RK3288-based +laptops will be added to libreboot at a later date. + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +Google's intent with CrOS devices +================================== + +CrOS (Chromium OS/Chrome OS) devices, such as Chromebooks, were not +designed with the intent of bringing more freedom to users. However, +they run with a lot of free software at the boot software and embedded +controller levels, since free software gives Google enough flexibility +to optimize various aspects such as boot time and most importantly, to +implement the CrOS security system, that involves various aspects of the +software. Google does hire a lot of Coreboot developers, who are +generally friendly to the free software movement and try to be good +members of the free software community, by contributing code back. + +CrOS devices are designed (from the factory) to actually coax the user +into using proprietary web services (SaaSS) that invade the user's +privacy (ChromeOS is literally just the Google Chrome browser when you +boot up, itself proprietary and comes with proprietary add-ons like +flash. It's only intended for SaaSS, not actual, real computing). +Google is even a member of the *PRISM* program, as outlined by Edward +Snowden. See notes about ChromeOS below. The libreboot project +recommends that the user replace the default *ChromeOS* with a +distribution that can be used in freedom, without invading the user's +privacy. + +We also use a similar argument for the MacBook and the ThinkPads that +are supported in libreboot. Those laptops are supported, in spite of +Apple and Lenovo, companies which are actually *hostile* to the free +software movement. + +Considerations about ChromeOS and free operating systems +======================================================== + +This laptop comes preinstalled (from the factory) with Google ChromeOS. +This is a GNU+Linux distribution, but it's not general purpose and it +comes with proprietary software. It's designed for SaaSS. Libreboot +recommends that users of this laptop replace it with another +distribution. + +Debian GNU+Linux +---------------- + + shows how to +install Debian. + +Devuan GNU+Linux +---------------- + + produces bootable and installable +Devuan images. + +Parabola GNU+Linux +------------------ + +See: + + +In this discussion thread (on the old GNU Libreboot mailing lists), there are +instructions for installing Parabola on C201 and other rockchip chromebooks +supported by Libreboot. + +Caution: Video acceleration requires a non-free blob, software rendering can be used instead. +============================================================================================= + +The C201 has a Mali T GPU, which requires a non-free blob. A driver, +Tamil, was written, but its source code has not been released. The +developer has so-far [withheld +it](http://libv.livejournal.com/27461.html). Use software rendering to +avoid the blob instead. Most tasks can still be performed without video +acceleration, without any noticeable performance penalty. + +In practise, this means that certain things like games, blender and +GNOME shell (or other fancy desktops) won't work well. The libreboot +project recommends a lightweight desktop which does not need video +acceleration, such as *XFCE* or *LXDE*. + +As it is unlikely that Tamil will be released, the +[chai](https://notabug.org/cafe/chai) project is writing a driver as +well. Ask on IRC if you think you can contribute. + +Caution: WiFi requires a non-free blob, a USB dongle can be used instead. +========================================================================= + +These laptops have non-removeable (soldered on) M.2 Type 1216 card +with WiFi+Bluetooth, which requires non-free firmware to be loaded by +the Linux kernel in order to work. + +The libreboot project recommends using an external USB wifi dongle that +works with free software. See +[\#recommended\_wifi](./#recommended_wifi). + +There are 2 companies (endorsed by Free Software Foundation, under their +*Respects your Freedom* guidelines), that sell USB WiFi dongles +guaranteed to work with free software (i.e. linux-libre kernel): + +- [ThinkPenguin sells + them](https://www.thinkpenguin.com/gnu-linux/penguin-wireless-n-usb-adapter-gnu-linux-tpe-n150usb) + (company based in USA) +- [Tehnoetic sells + them](https://tehnoetic.com/tehnoetic-wireless-adapter-gnu-linux-libre-tet-n150) + (company based in Europe) + +These wifi dongles use the AR9271 (atheros) chipset, supported by the +free *ath9k\_htc* driver in the Linux kernel. They work in *linux-libre* +too. + +EC firmware is free software! +============================= + +It's free software. Google provides the source. Build scripts will be +added later, with EC sources provided in libreboot, and builds of the EC +firmware. + +This is unlike the other current libreboot laptops (Intel based). In +practise, you can (if you do without the video/wifi blobs, and replace +ChromeOS with a distribution that respects your freedom) be more free +when using one of these laptops. + +The libreboot FAQ briefly describes what an *EC* is: +[../../faq.md#firmware-ec](../../faq.md#firmware-ec) + +No microcode! +============= + +Unlike x86 (e.g. Intel/AMD) CPUs, ARM CPUs do not use microcode, not +even built in. On the Intel/AMD based libreboot systems, there is still +microcode in the CPU (not considered problematic by the FSF, provided +that it is reasonably trusted to not be malicious, since it's part of +the hardware and read-only), but we exclude microcode updates (volatile +updates which are uploaded at boot time by the boot firmware, if +present), which are proprietary software. + +On ARM CPUs, the instruction set is implemented in circuitry, without +microcode. + +Depthcharge payload +=================== + +These systems do not use the GRUB payload. Instead, they use a payload +called depthcharge, which is common on CrOS devices. This is free +software, maintained by Google. + +Flash chip write protection: the screw +====================================== + +It's next to the flash chip. Unscrew it, and the flash chip is +read-write. Screw it back in, and the flash chip is read-only. It's +called the screw. + +*The screw* is accessible by removing other screws and gently prying off +the upper shell, where the flash chip and the screw are then directly +accessible. User flashing from software is possible, without having to +externally re-flash, but the flash chip is SPI (SOIC-8 form factor) so +you can also externally re-flash if you want to. In practise, you only +need to externally re-flash if you brick the laptop; read +[../install/bbb\_setup.md](../install/bbb_setup.md) for an example +of how to set up an SPI programmer. + +Write protection is useful, because it prevents the firmware from being +re-flashed by any malicious software that might become executed on your +GNU+Linux system, as root. In other words, it can prevent a +firmware-level *evil maid* attack. It's possible to write protect on +all current libreboot systems, but CrOS devices make it easy. The screw +is such a stupidly simple idea, which all designs should implement. + +Copyright © 2015, 2017 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/d510mo.md b/i18n/fr_FR/docs/hardware/d510mo.md new file mode 100644 index 00000000..b2e85b0a --- /dev/null +++ b/i18n/fr_FR/docs/hardware/d510mo.md @@ -0,0 +1,22 @@ +--- +title: Intel D510MO desktop board +... + +This is a desktop board using intel hardware (circa \~2009, ICH7 +southbridge, similar performance-wise to the Libreboot X200. It can make +for quite a nifty desktop. Powered by libreboot. + +NOTE: This board has a working framebuffer in Grub, but in GNU+Linux in +native resolution the display is unusable due to some raminit issues. +This board can however be used for building a headless server. + +Flashing instructions can be found at +[../install/d510mo.md](../install/d510mo.md) + +Copyright © 2016 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/d945gclf.md b/i18n/fr_FR/docs/hardware/d945gclf.md new file mode 100644 index 00000000..f464e4bd --- /dev/null +++ b/i18n/fr_FR/docs/hardware/d945gclf.md @@ -0,0 +1,83 @@ +--- +title: Intel D945GCLF desktop board +... + +If you just want flashing instructions, go to +[../install/d945gclf.md](../install/d945gclf.md) + +This board is a mini-itx desktop board for 2008. It uses an atom 230, +which is a singe core CPU but it is hyperthreaded so it appears to have +2 thread to the OS. The flash chip is very small, 512KiB, so grub2 does +not fit, which is why libreboot has to use seabios on this target. Full +disk encryption like on other supported targets will not be possible, so +plan accordingly. + +This board has a 945gc chipset which is the desktop equivalent of 945gm +which can be found in the Lenovo x60/t60 or macbook2,1. This chipset +features an ICH7 southbridge. It has 1 DIMM slot that can accommodate up +to 2G of DDR2 RAM. + +Connectivity-wise it has 1 PCI slot, a 10/100 ethernet port, 4 usb slot +and 4 usb ports, with one internal header and 2 SATA ports. + +The D945GCLF2 is an upgraded version of this board. The differences are: +1 more USB header, 10/100/1000 ethernet and a dual core cpu (also +hyperthreaded). Since the board is almost identical (and coreboot code +seem to indicate that it works, since MAX\_CPU=4 is set), it is believed +that it should also work but this is untested. + +Remarks about vendor bios: +-------------------------- + +- Without coreboot/libreboot this board is utery useless, since the + vendor bios is very bad. It cannot boot from any HDD whether it is + connected to the SATA port or USB. With libreboot it works just + fine. + +- The vendor bios write protects the flash so it requires external + flashing to install libreboot on this device. Once libreboot is + flashed there is no problem to update the firmware internally + +Here is an image of the board:\ +![](../images/d945gclf/d945gclf.jpg)\ +Here is an image of the D945GCLF2 board:\ +![](../images/d945gclf/20160923_141521.jpg){width="80%" height="80%"}\ +And SPI SOIC8 flash chip\ +![](../images/d945gclf/20160923_141550.jpg){width="50%" height="50%"} + +How to replace thermal paste and fan +------------------------------------ + +This board comes with very crappy disposable loud fan, that one has no +bearings, which can not be repaired or oiled properly, do not waste your +time trying to fix it, just buy one chinese same size fan\ +![](../images/d945gclf/20160923_141620.jpg){width="50%" height="50%"} +![](../images/d945gclf/20160923_141614.jpg){width="50%" height="50%"}\ +Make sure that new one has same wiring\ +![](../images/d945gclf/20160923_142618.jpg){width="50%" height="50%"}\ +This is a new one, with bearing and maintenable\ +![](../images/d945gclf/20160923_141738.jpg){width="50%" height="50%"} +![](../images/d945gclf/20160923_141814.jpg){width="50%" height="50%"}\ +Now remove the both coolers rotating them a bit, slowly, then clean both +silicons and both coolers (removing cmos battery first is recommended)\ +![](../images/d945gclf/20160923_141601.jpg){width="50%" height="50%"}\ +Put a little bit of non conductive thermal paste on both silicons (only +cpu silicon iis shown on that image)\ +![](../images/d945gclf/20160923_142031.jpg){width="50%" height="50%"}\ + +Before assembling new fan, some need new longer screws, make sure having +these (on the left is original one, too short for new fan)\ +![](../images/d945gclf/20160923_141659.jpg){width="50%" height="50%"}\ +After that, assemble your new fan into CPU cooler\ +![](../images/d945gclf/20160923_141635.jpg){width="50%" height="50%"}\ +Finally assemle both coolers on both chips, do not forget put in the CPU +fan connector back, and you are done. + +Copyright © 2016 Arthur Heymans \ +Copyright © 2016 Vitaly Castaño Solana \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/ga-g41m-es2l.md b/i18n/fr_FR/docs/hardware/ga-g41m-es2l.md new file mode 100644 index 00000000..fbcf2132 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/ga-g41m-es2l.md @@ -0,0 +1,26 @@ +--- +title: Gigabyte GA-G41M-ES2L desktop board +... + +This is a desktop board using intel hardware (circa \~2009, ICH7 +southbridge, similar performance-wise to the Libreboot X200. It can make +for quite a nifty desktop. Powered by libreboot. + +IDE on the board is untested, but it might be possible to use a SATA HDD +using an IDE SATA adapter. The SATA ports do work. + +You need to set a custom MAC address in GNU+Linux for the NIC to work. +In /etc/network/interfaces on debian-based systems like Debian or +Devuan, this would be in the entry for your NIC:\ +hwaddress ether macaddressgoeshere + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +Copyright © 2016 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/gm45_remove_me.md b/i18n/fr_FR/docs/hardware/gm45_remove_me.md new file mode 100644 index 00000000..26e5f9f6 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/gm45_remove_me.md @@ -0,0 +1,526 @@ +--- +title: "GM45 chipsets: remove the ME (manageability engine)" +... + +This sections relates to disabling and removing the ME (Intel +*M*anagement *E*ngine) on GM45. This was originally done on the +ThinkPad X200, and later adapted for the ThinkPad R400/T400/T500. It can +in principle be done on any GM45 or GS45 system. + +The ME is a blob that typically must be left inside the flash chip (in +the ME region, as outlined by the default descriptor). On GM45, it is +possible to remove it without any ill effects. All other parts of +coreboot on GM45 systems (provided GMA MHD4500 / Intel graphics) can be +blob-free, so removing the ME was the last obstacle to make GM45 a +feasible target in libreboot (the systems can also work without the +microcode blobs). + +The ME is removed and disabled in libreboot by modifying the descriptor. +More info about this can be found in the ich9deblob/ich9gen source code +in resources/utilities/ich9deblob/ in libreboot, or more generally on +this page. + +More information about the ME can be found at + and +. + +Another project recently found: + +ICH9 gen utility {#ich9gen} +================ + +It is no longer necessary to use [ich9deblob](#ich9deblob) to generate a +deblobbed descriptor+gbe image for GM45 targets. ich9gen is a small +utility within ich9deblob that can generate them from scratch, without a +factory.bin dump. + +ich9gen executables can be found under ./ich9deblob/ statically compiled +in libreboot\_util. If you are using src or git, build ich9gen from +source with: + + $ ./oldbuild module ich9deblob + +The executable will appear under resources/utilities/ich9deblob/ + +Run: + + $ ./ich9gen + +Running ich9gen this way (without any arguments) generates a default +descriptor+gbe image with a generic MAC address. You probably don't +want to use the generic one; the ROM images in libreboot contain a +descriptor+gbe image by default (already inserted) just to prevent or +mitigate the risk of bricking your laptop, but with the generic MAC +address (the libreboot project does not know what your real MAC address +is). + +You can find out your MAC address from `ip addr` or `ifconfig` in +GNU+Linux. Alternatively, if you are running libreboot already (with the +correct MAC address in your ROM), dump it (flashrom -r) and read the +first 6 bytes from position 0x1000 (or 0x2000) in a hex editor (or, +rename it to factory.rom and run it in ich9deblob: in the newly created +mkgbe.c will be the individual bytes of your MAC address). If you are +currently running the stock firmware and haven't installed libreboot +yet, you can also run that through ich9deblob to get the mac address. + +An even simpler way to get the MAC address would be to read what's on +the little sticker on the bottom/base of the laptop. + +On GM45 laptops that use flash descriptors, the MAC address or the +onboard ethernet chipset is flashed (inside the ROM image). You should +generate a descriptor+gbe image with your own MAC address inside (with +the Gbe checksum updated to match). Run: + + $ ./ich9gen --macaddress XX:XX:XX:XX:XX:XX + +(replace the XX chars with the hexadecimal chars in the MAC address that +you want) + +Two new files will be created: + +- `ich9fdgbe_4m.bin`: this is for GM45 laptops with the 4MB flash + chip. +- `ich9fdgbe_8m.bin`: this is for GM45 laptops with the 8MB flash + chip. +- `ich9fdgbe_16m.bin`: this is for GM45 laptops with the 16MB flash + chip. + +Assuming that your libreboot image is named **libreboot.rom**, copy the +file to where **libreboot.rom** is located and then insert the +descriptor+gbe file into the ROM image.\ +For 16MiB flash chips: + + # dd if=ich9fdgbe_16m.bin of=libreboot.rom bs=12k count=1 conv=notrunc + +For 8MiB flash chips: + + # dd if=ich9fdgbe_8m.bin of=libreboot.rom bs=12k count=1 conv=notrunc + +For 4MiB flash chips: + + # dd if=ich9fdgbe_4m.bin of=libreboot.rom bs=12k count=1 conv=notrunc + +Your libreboot.rom image is now ready to be flashed on the system. Refer +back to [../install/\#flashrom](../install/#flashrom) for how to flash +it. + +Write-protecting the flash chip +------------------------------- + +Look in *resources/utilities/ich9deblob/src/descriptor/descriptor.c* for +the following lines in the *descriptorHostRegionsUnlocked* function: + + descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x1; + descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x1; + +Also look in *resources/utilities/ich9deblob/src/ich9gen/mkdescriptor.c* +for the following lines: + + descriptorStruct.masterAccessSection.flMstr1.fdRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.biosRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.meRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.gbeRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + descriptorStruct.masterAccessSection.flMstr1.pdRegionWriteAccess = 0x1; /* see ../descriptor/descriptor.c */ + +NOTE: When you write-protect the flash chip, re-flashing is no longer +possible unless you use dedicated external equipment, which also means +disassembling the laptop. The same equipment can also be used to remove +the write-protection later on, if you choose to do so. \*Only\* +write-protect the chip if you have the right equipment for external +flashing later on; for example, see +[../install/bbb\_setup.md](../install/bbb_setup.md). + +Change them all to 0x0, then re-compile ich9gen. After you have done +that, follow the notes in [\#ich9gen](#ich9gen) to generate a new +descriptor+gbe image and insert that into your ROM image, then flash it. +The next time you boot, the flash chip will be read-only in software +(hardware re-flashing will still work, which you will need for +re-flashing the chip after write-protecting it, to clear the write +protection or to flash yet another ROM image with write protection set +in the descriptor). + +Flashrom will tell you that you can still forcefully re-flash, using *-p +internal:ich\_spi\_force=yes* but this won't actually work; it'll just +brick your laptop. + +For external flashing guides, refer to [../install/](../install/). + +ICH9 deblob utility {#ich9deblob} +=================== + +**This is no longer strictly necessary. Libreboot ROM images for GM45 +systems now contain the 12KiB descriptor+gbe generated from ich9gen, by +default.** + +This was the tool originally used to disable the ME on X200 (later +adapted for other systems that use the GM45 chipset). +[ich9gen](#ich9gen) now supersedes it; ich9gen is better because it does +not rely on dumping the factory.rom image (whereas, ich9deblob does). + +This is what you will use to generate the deblobbed descriptor+gbe +regions for your libreboot ROM image. + +If you are working with libreboot\_src (or git), you can find the source +under resources/utilities/ich9deblob/ and will already be compiled if +you ran **./oldbuild module all** or **./oldbuild module ich9deblob** +from the main directory (./), otherwise you can build it like so: + + $ ./oldbuild module ich9deblob + +An executable file named **ich9deblob** will now appear under +resources/utilities/ich9deblob/ + +If you are working with libreboot\_util release archive, you can find +the utility included, statically compiled (for i686 and x86\_64 on +GNU+Linux) under ./ich9deblob/. + +Place the factory.rom from your system (can be obtained using the +external flashing guides for GM45 targets linked +[../install/](../install/)) in the directory where you have your +ich9deblob executable, then run the tool: + + $ ./ich9deblob + +A 12kiB file named **deblobbed\_descriptor.bin** will now appear. **Keep +this and the factory.rom stored in a safe location!** The first 4KiB +contains the descriptor data region for your system, and the next 8KiB +contains the gbe region (config data for your gigabit NIC). These 2 +regions could actually be separate files, but they are joined into 1 +file in this case. + +A 4KiB file named **deblobbed\_4kdescriptor.bin** will alternatively +appear, if no GbE region was detected inside the ROM image. This is +usually the case, when a discrete NIC is used (eg Broadcom) instead of +Intel. Only the Intel NICs need a GbE region in the flash chip. + +Assuming that your libreboot image is named **libreboot.rom**, copy the +**deblobbed\_descriptor.bin** file to where **libreboot.rom** is located +and then run: + + # dd if=deblobbed_descriptor.bin of=libreboot.rom bs=12k count=1 conv=notrunc + +Alternatively, if you got a the **deblobbed\_4kdescriptor.bin** file (no +GbE defined), do this: + + # dd if=deblobbed_4kdescriptor.bin of=libreboot.rom bs=4k count=1 conv=notrunc + +The utility will also generate 4 additional files: + +- mkdescriptor.c +- mkdescriptor.h +- mkgbe.c +- mkgbe.h + +These are C source files that can re-generate the very same Gbe and +Descriptor structs (from ich9deblob/ich9gen). To use these, place them +in src/ich9gen/ in ich9deblob, then re-build. The newly built +**ich9gen** executable will be able to re-create the very same 12KiB +file from scratch, based on the C structs, this time **without** the +need for a factory.rom dump! + +You should now have a **libreboot.rom** image containing the correct 4K +descriptor and 8K gbe regions, which will then be safe to flash. Refer +back to [../install/\#flashrom](../install/#flashrom) for how to flash +it. + +demefactory utility {#demefactory} +=================== + +This takes a factory.rom dump and disables the ME/TPM, but leaves the +region intact. It also sets all regions read-write. + +The ME interferes with flash read/write in flashrom, and the default +descriptor locks some regions. The idea is that doing this will remove +all of those restrictions. + +Simply run (with factory.rom in the same directory): + + $ ./demefactory + +It will generate a 4KiB descriptor file (only the descriptor, no GbE). +Insert that into a factory.rom image (NOTE: do this on a copy of it. +Keep the original factory.rom stored safely somewhere): + + # dd if=demefactory_4kdescriptor.bin of=factory_nome.rom bs=4k count=1 conv=notrunc + +TODO: test this.\ +TODO: lenovobios (GM45 thinkpads) still write-protects parts of the +flash. Modify the assembly code inside. Note: the factory.rom (BIOS +region) from lenovobios is in a compressed format, which you have to +extract. bios\_extract upstream won't work, but the following was said +in \#coreboot on freenode IRC: + + vimuser: try bios_extract with ffv patch http://patchwork.coreboot.org/patch/3444/ + or https://github.com/coreboot/bios_extract/blob/master/phoenix_extract.py + what are you looking for specifically, btw? + + 0x74: 0x9fff03e0 PR0: Warning: 0x003e0000-0x01ffffff is read-only. + 0x84: 0x81ff81f8 PR4: Warning: 0x001f8000-0x001fffff is locked. + +Use-case: a factory.rom image modified in this way would theoretically +have no flash protections whatsoever, making it easy to quickly switch +between factory/libreboot in software, without ever having to +disassemble and re-flash externally unless you brick the device. + +demefactory is part of the ich9deblob src, found at +*resources/utilities/ich9deblob/* + +The sections below are adapted from (mostly) IRC logs related to early +development getting the ME removed on GM45. They are useful for +background information. This could not have been done without sgsit's +help. + +Early notes {#early_notes} +----------- + +- + page 230 mentions about descriptor and non-descriptor mode (which + wipes out gbe and ME/AMT). +- ~~**See reference to HDA\_SDO (disable descriptor security)**~~ + strap connected GPIO33 pin is it on ICH9-M (X200). HDA\_SDO applies + to later chipsets (series 6 or higher). Disabling descriptor + security also disables the ethernet according to sgsit. sgsit's + method involves use of 'soft straps' (see IRC logs below) instead + of disabling the descriptor. +- **and the location of GPIO33 on the x200s: (was an external link. + Putting it here instead)** + [images/x200/gpio33\_location.jpg](images/x200/gpio33_location.jpg) - + it's above the number 7 on TP37 (which is above the big intel chip + at the bottom) +- The ME datasheet may not be for the mobile chipsets but it doesn't + vary that much. This one gives some detail and covers QM67 which is + what the X201 uses: + + +Flash chips {#flashchips} +----------- +- X200 laptop (Mocha-1): + ICH9-M overrides ifd permissions with a strap connected to GPIO33 pin (see IRC notes below) + + - The X200 can be found with any of the following flash + chips: + - ATMEL AT26DF321-SU 72.26321.A01 - this is a 32Mb (4MiB) chip + - MXIC (Macronix?) MX25L3205DM2I-12G 72.25325.A01 - another 32Mb + (4MiB) chip + - MXIC (Macronix?) MX25L6405DMI-12G 41R0820AA - this is a 64Mb + (8MiB) chip + - Winbond W25X64VSFIG 41R0820BA - another 64Mb (8MiB) chip + + sgsit says that the X200s (Pecan-1) with the 64Mb flash chips are (probably) + the ones with AMT (alongside the ME), whereas the 32Mb chips contain + only the ME. + +Early development notes {#early_development_notes} +----------------------- + + Start (hex) End (hex) Length (hex) Area Name + ----------- --------- ------------ --------- + 00000000 003FFFFF 00400000 Flash Image + + 00000000 00000FFF 00001000 Descriptor Region + 00000004 0000000F 0000000C Descriptor Map + 00000010 0000001B 0000000C Component Section + 00000040 0000004F 00000010 Region Section + 00000060 0000006B 0000000C Master Access Section + 00000060 00000063 00000004 CPU/BIOS + 00000064 00000067 00000004 Manageability Engine (ME) + 00000068 0000006B 00000004 GbE LAN + 00000100 00000103 00000004 ICH Strap 0 + 00000104 00000107 00000004 ICH Strap 1 + 00000200 00000203 00000004 MCH Strap 0 + 00000EFC 00000EFF 00000004 Descriptor Map 2 + 00000ED0 00000EF7 00000028 ME VSCC Table + 00000ED0 00000ED7 00000008 Flash device 1 + 00000ED8 00000EDF 00000008 Flash device 2 + 00000EE0 00000EE7 00000008 Flash device 3 + 00000EE8 00000EEF 00000008 Flash device 4 + 00000EF0 00000EF7 00000008 Flash device 5 + 00000F00 00000FFF 00000100 OEM Section + 00001000 001F5FFF 001F5000 ME Region + 001F6000 001F7FFF 00002000 GbE Region + 001F8000 001FFFFF 00008000 PDR Region + 00200000 003FFFFF 00200000 BIOS Region + + Start (hex) End (hex) Length (hex) Area Name + ----------- --------- ------------ --------- + 00000000 003FFFFF 00400000 Flash Image + + 00000000 00000FFF 00001000 Descriptor Region + 00000004 0000000F 0000000C Descriptor Map + 00000010 0000001B 0000000C Component Section + 00000040 0000004F 00000010 Region Section + 00000060 0000006B 0000000C Master Access Section + 00000060 00000063 00000004 CPU/BIOS + 00000064 00000067 00000004 Manageability Engine (ME) + 00000068 0000006B 00000004 GbE LAN + 00000100 00000103 00000004 ICH Strap 0 + 00000104 00000107 00000004 ICH Strap 1 + 00000200 00000203 00000004 MCH Strap 0 + 00000ED0 00000EF7 00000028 ME VSCC Table + 00000ED0 00000ED7 00000008 Flash device 1 + 00000ED8 00000EDF 00000008 Flash device 2 + 00000EE0 00000EE7 00000008 Flash device 3 + 00000EE8 00000EEF 00000008 Flash device 4 + 00000EF0 00000EF7 00000008 Flash device 5 + 00000EFC 00000EFF 00000004 Descriptor Map 2 + 00000F00 00000FFF 00000100 OEM Section + 00001000 00002FFF 00002000 GbE Region + 00003000 00202FFF 00200000 BIOS Region + + Build Settings + -------------- + Flash Erase Size = 0x1000 + +It's a utility called 'Flash Image Tool' for ME 4.x that was used for +this. You drag a complete image into in and the utility decomposes the +various components, allowing you to set soft straps. + +This tool is proprietary, for Windows only, but was used to deblob the +X200. End justified means, and the utility is no longer needed since the +ich9deblob utility (documented on this page) can now be used to create +deblobbed descriptors. + +GBE (gigabit ethernet) region in SPI flash {#gbe_region} +------------------------------------------ + +Of the 8K, about 95% is 0xFF. The data is the gbe region is fully +documented in this public datasheet: + + +The only actual content found was: + + 00 1F 1F 1F 1F 1F 00 08 FF FF 83 10 FF FF FF FF + 08 10 FF FF C3 10 EE 20 AA 17 F5 10 86 80 00 00 + 01 0D 00 00 00 00 05 06 20 30 00 0A 00 00 8B 8D + 02 06 40 2B 43 00 00 00 F5 10 AD BA F5 10 BF 10 + AD BA CB 10 AD BA AD BA 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 01 00 40 28 12 07 40 FF FF FF FF FF FF FF FF + FF FF FF FF FF FF FF FF FF FF FF FF FF FF D9 F0 + 20 60 1F 00 02 00 13 00 00 80 1D 00 FF 00 16 00 + DD CC 18 00 11 20 17 00 DD DD 18 00 12 20 17 00 + 00 80 1D 00 00 00 1F + +The first part is the MAC address set to all 0x1F. It's repeated haly +way through the 8K area, and the rest is all 0xFF. This is all +documented in the datasheet. + +The GBe region starts at 0x20A000 bytes from the \*end\* of a factory +image and is 0x2000 bytes long. In libreboot (deblobbed) the descriptor +is set to put gbe directly after the initial 4K flash descriptor. So the +first 4K of the ROM is the descriptor, and then the next 8K is the gbe +region. + +### GBE region: change MAC address {#gbe_region_changemacaddress} + +According to the datasheet, it's supposed to add up to 0xBABA but can +actually be others on the X200. + + +*"One of those engineers loves classic rock music, so they selected +0xBABA"* + +In honour of the song *Baba O'Reilly* by *The Who* apparently. We're +not making this stuff up... + +0x3ABA, 0x34BA, 0x40BA and more have been observed in the main Gbe +regions on the X200 factory.rom dumps. The checksums of the backup +regions match BABA, however. + +By default, the X200 (as shipped by Lenovo) actually has an invalid main +gbe checksum. The backup gbe region is correct, and is what these +systems default to. Basically, you should do what you need on the +\*backup\* gbe region, and then correct the main one by copying from the +backup. + +Look at resources/utilities/ich9deblob/ich9deblob.c. + +- Add the first 0x3F 16bit numbers (unsigned) of the GBe descriptor + together (this includes the checksum value) and that has to add up + to 0xBABA. In other words, the checksum is 0xBABA minus the total of + the first 0x3E 16bit numbers (unsigned), ignoring any overflow. + +Flash descriptor region {#flash_descriptor_region} +----------------------- + + +from page 850 onwards. This explains everything that is in the flash +descriptor, which can be used to understand what libreboot is doing +about modifying it. + +How to deblob: + +- patch the number of regions present in the descriptor from 5 - 3 +- originally descriptor + bios + me + gbe + platform +- modified = descriptor + bios + gbe +- the next stage is to patch the part of the descriptor which defines + the start and end point of each section +- then cut out the gbe region and insert it just after the region +- all this can be substantiated with public docs (ICH9 datasheet) +- the final part is flipping 2 bits. Halting the ME via 1 MCH soft + strap and 1 ICH soft strap +- the part of the descriptor described there gives the base address + and length of each region (bits 12:24 of each address) +- to disable a region, you set the base address to 0xFFF and the + length to 0 +- and you change the number of regions from 4 (zero based) to 2 + +There's an interesting parameter called 'ME Alternate disable', which +allows the ME to only handle hardware errata in the southbridge, but +disables any other functionality. This is similar to the 'ignition' in +the 5 series and higher but using the standard firmware instead of a +small 128K version. Useless for libreboot, though. + +To deblob GM45, you chop out the platform and ME regions and correct the +addresses in flReg1-4. Then you set meDisable to 1 in ICHSTRAP0 and +MCHSTRAP0. + +How to patch the descriptor from the factory.rom dump + +- map the first 4k into the struct (minus the gbe region) +- set NR in FLMAP0 to 2 (from 4) +- adjust BASE and LIMIT in flReg1,2,3,4 to reflect the new location of + each region (or remove them in the case of Platform and ME) +- set meDisable to 1/true in ICHSTRAP0 and MCHSTRAP0 +- extract the 8k GBe region and append that to the end of the 4k + descriptor +- output the 12k concatenated chunk +- Then it can be dd'd into the first 12K part of a coreboot image. +- the GBe region always starts 0x20A000 bytes from the end of the ROM + +This means that libreboot's descriptor region will simply define the +following regions: + +- descriptor (4K) +- gbe (8K) +- bios (rest of flash chip. CBFS also set to occupy this whole size) + +The data in the descriptor region is little endian, and it represents +bits 24:12 of the address (bits 12-24, written this way since bit 24 is +nearer to left than bit 12 in the binary representation). + +So, *x << 12 = address* + +If it's in descriptor mode, then the first 4 bytes will be 5A A5 F0 0F. + +platform data partition in boot flash (factory.rom / lenovo bios) {#platform_data_region} +----------------------------------------------------------------- + +Basically useless for libreboot, since it appears to be a blob. Removing +it didn't cause any issues in libreboot. + +This is a 32K region from the factory image. It could be data +(non-functional) that the original Lenovo BIOS used, but we don't know. + +It has only a 448 byte fragment different from 0x00 or 0xFF. + +Copyright © 2014, 2015 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/biosdecode.err.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/biosdecode.err.log new file mode 100644 index 00000000..e69de29b diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/biosdecode.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/biosdecode.log new file mode 100644 index 00000000..bfeaba39 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/biosdecode.log @@ -0,0 +1,24 @@ +# biosdecode 2.12 +VPD present. + BIOS Build ID: 6DET65WW + Box Serial Number: L3AAR0B + Motherboard Serial Number: 1ZFDS89N4DD + Machine Type/Model: 7459GW4 +SMBIOS 2.4 present. + Structure Table Length: 2464 bytes + Structure Table Address: 0x000E0010 + Number Of Structures: 68 + Maximum Structure Size: 120 bytes +BIOS32 Service Directory present. + Revision: 0 + Calling Interface Address: 0x000FDC80 +ACPI 2.0 present. + OEM Identifier: LENOVO + RSD Table 32-bit Address: 0x79B5B843 + XSD Table 64-bit Address: 0x0000000079B5B8AB +PNP BIOS 1.0 present. + Event Notification: Not Supported + Real Mode 16-bit Code Address: E2CA:1868 + Real Mode 16-bit Data Address: 0040:0000 + 16-bit Protected Mode Code Address: 0x000F97BD + 16-bit Protected Mode Data Address: 0x00000400 diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/codec#0 b/i18n/fr_FR/docs/hardware/hwdumps/x200/codec#0 new file mode 100644 index 00000000..2b9d6f35 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/codec#0 @@ -0,0 +1,208 @@ +Codec: Conexant CX20561 (Hermosa) +Address: 0 +AFG Function Id: 0x1 (unsol 1) +MFG Function Id: 0x2 (unsol 1) +Vendor Id: 0x14f15051 +Subsystem Id: 0x17aa20ff +Revision Id: 0x100000 +Modem Function Group: 0x2 +Default PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM +Default Amp-In caps: N/A +Default Amp-Out caps: N/A +State of AFG node 0x01: + Power states: D0 D1 D2 D3 CLKSTOP + Power: setting=D0, actual=D0 +GPIO: io=4, o=0, i=0, unsolicited=1, wake=0 + IO[0]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[1]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[2]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 + IO[3]: enable=0, dir=0, wake=0, sticky=0, data=0, unsol=0 +Node 0x10 [Audio Output] wcaps 0xc1d: Stereo Amp-Out R/L + Control: name="Speaker Playback Volume", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Control: name="Speaker Playback Switch", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Device: name="CX20561 Analog", type="Audio", device=0 + Amp-Out caps: ofs=0x4a, nsteps=0x4a, stepsize=0x03, mute=0 + Amp-Out vals: [0x4a 0x4a] + Converter: stream=8, channel=0 + PCM: + rates [0x560]: 44100 48000 96000 192000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x11 [Audio Output] wcaps 0xc1d: Stereo Amp-Out R/L + Control: name="Headphone Playback Volume", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Control: name="Headphone Playback Switch", index=0, device=0 + ControlAmp: chs=3, dir=Out, idx=0, ofs=0 + Amp-Out caps: ofs=0x4a, nsteps=0x4a, stepsize=0x03, mute=0 + Amp-Out vals: [0x4a 0x4a] + Converter: stream=8, channel=0 + PCM: + rates [0x560]: 44100 48000 96000 192000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x12 [Audio Output] wcaps 0x211: Stereo Digital + Control: name="IEC958 Playback Con Mask", index=0, device=0 + Control: name="IEC958 Playback Pro Mask", index=0, device=0 + Control: name="IEC958 Playback Default", index=0, device=0 + Control: name="IEC958 Playback Switch", index=0, device=0 + Control: name="IEC958 Default PCM Playback Switch", index=0, device=0 + Device: name="CX20561 Digital", type="SPDIF", device=1 + Converter: stream=8, channel=0 + Digital: + Digital category: 0x0 + IEC Coding Type: 0x0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x5]: PCM AC3 +Node 0x13 [Beep Generator Widget] wcaps 0x70000c: Mono Amp-Out + Control: name="Beep Playback Volume", index=0, device=0 + ControlAmp: chs=1, dir=Out, idx=0, ofs=0 + Control: name="Beep Playback Switch", index=0, device=0 + ControlAmp: chs=1, dir=Out, idx=0, ofs=0 + Amp-Out caps: ofs=0x03, nsteps=0x03, stepsize=0x17, mute=0 + Amp-Out vals: [0x00] +Node 0x14 [Audio Input] wcaps 0x100d1b: Stereo Amp-In R/L + Device: name="CX20561 Analog", type="Audio", device=0 + Amp-In caps: ofs=0x4a, nsteps=0x50, stepsize=0x03, mute=0 + Amp-In vals: [0x50 0x50] [0x50 0x50] + Converter: stream=4, channel=0 + SDI-Select: 0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x1d* 0x17 +Node 0x15 [Audio Input] wcaps 0x100d1b: Stereo Amp-In R/L + Control: name="Capture Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=1, ofs=0 + Amp-In caps: ofs=0x4a, nsteps=0x50, stepsize=0x03, mute=0 + Amp-In vals: [0x50 0x50] + Converter: stream=0, channel=0 + SDI-Select: 0 + PCM: + rates [0x160]: 44100 48000 96000 + bits [0xe]: 16 20 24 + formats [0x1]: PCM + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 1 + 0x18 +Node 0x16 [Pin Complex] wcaps 0x400581: Stereo + Control: name="Headphone Jack", index=0, device=0 + Pincap 0x0000001c: OUT HP Detect + Pin Default 0x042140f0: [Jack] HP Out at Ext Right + Conn = 1/8, Color = Green + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0xc0: OUT HP + Unsolicited: tag=02, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10 0x11* +Node 0x17 [Pin Complex] wcaps 0x40048b: Stereo Amp-In + Control: name="Dock Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Dock Mic Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x27, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00001224: IN Detect + Vref caps: 50 80 + Pin Default 0x61a190f0: [N/A] Mic at Sep Rear + Conn = 1/8, Color = Pink + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x24: IN VREF_80 + Unsolicited: tag=03, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x18 [Pin Complex] wcaps 0x40048b: Stereo Amp-In + Control: name="Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Mic Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x27, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00001224: IN Detect + Vref caps: 50 80 + Pin Default 0x04a190f0: [Jack] Mic at Ext Right + Conn = 1/8, Color = Pink + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x24: IN VREF_80 + Unsolicited: tag=04, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x19 [Pin Complex] wcaps 0x400581: Stereo + Control: name="Dock Headphone Jack", index=0, device=0 + Pincap 0x00000014: OUT Detect + Pin Default 0x612140f0: [N/A] HP Out at Sep Rear + Conn = 1/8, Color = Green + DefAssociation = 0xf, Sequence = 0x0 + Pin-ctls: 0x40: OUT + Unsolicited: tag=01, enabled=1 + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10 0x11* +Node 0x1a [Pin Complex] wcaps 0x400501: Stereo + Control: name="Speaker Phantom Jack", index=0, device=0 + Pincap 0x00010010: OUT EAPD + EAPD 0x2: EAPD + Pin Default 0x901701f0: [Fixed] Speaker at Int N/A + Conn = Analog, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10* 0x11 +Node 0x1b [Pin Complex] wcaps 0x400500: Mono + Pincap 0x00010010: OUT EAPD + EAPD 0x2: EAPD + Pin Default 0x40f001f0: [N/A] Other at Ext N/A + Conn = Unknown, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 2 + 0x10* 0x11 +Node 0x1c [Pin Complex] wcaps 0x400701: Stereo Digital + Control: name="SPDIF Phantom Jack", index=0, device=0 + Pincap 0x00000010: OUT + Pin Default 0x40f001f0: [N/A] Other at Ext N/A + Conn = Unknown, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x40: OUT + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 + Connection: 1 + 0x12 +Node 0x1d [Pin Complex] wcaps 0x40040b: Stereo Amp-In + Control: name="Internal Mic Boost Volume", index=0, device=0 + ControlAmp: chs=3, dir=In, idx=0, ofs=0 + Control: name="Internal Mic Phantom Jack", index=0, device=0 + Amp-In caps: ofs=0x00, nsteps=0x04, stepsize=0x2f, mute=0 + Amp-In vals: [0x00 0x00] + Pincap 0x00000020: IN + Pin Default 0x90a601f0: [Fixed] Mic at Int N/A + Conn = Digital, Color = Unknown + DefAssociation = 0xf, Sequence = 0x0 + Misc = NO_PRESENCE + Pin-ctls: 0x20: IN + Power states: D0 D1 D2 D3 + Power: setting=D0, actual=D0 +Node 0x1e [Vendor Defined Widget] wcaps 0xf00000: Mono diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/cpuinfo.err.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/cpuinfo.err.log new file mode 100644 index 00000000..e69de29b diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/cpuinfo.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/cpuinfo.log new file mode 100644 index 00000000..8b01059e --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/cpuinfo.log @@ -0,0 +1,52 @@ +processor : 0 +vendor_id : GenuineIntel +cpu family : 6 +model : 23 +model name : Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz +stepping : 6 +microcode : 0x60c +cpu MHz : 800.000 +cache size : 3072 KB +physical id : 0 +siblings : 2 +core id : 0 +cpu cores : 2 +apicid : 0 +initial apicid : 0 +fpu : yes +fpu_exception : yes +cpuid level : 10 +wp : yes +flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts nopl aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 lahf_lm dtherm tpr_shadow vnmi flexpriority +bogomips : 4787.97 +clflush size : 64 +cache_alignment : 64 +address sizes : 36 bits physical, 48 bits virtual +power management: + +processor : 1 +vendor_id : GenuineIntel +cpu family : 6 +model : 23 +model name : Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz +stepping : 6 +microcode : 0x60c +cpu MHz : 1600.000 +cache size : 3072 KB +physical id : 0 +siblings : 2 +core id : 1 +cpu cores : 2 +apicid : 1 +initial apicid : 1 +fpu : yes +fpu_exception : yes +cpuid level : 10 +wp : yes +flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts nopl aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 lahf_lm dtherm tpr_shadow vnmi flexpriority +bogomips : 4787.97 +clflush size : 64 +cache_alignment : 64 +address sizes : 36 bits physical, 48 bits virtual +power management: + diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/dmesg.err.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/dmesg.err.log new file mode 100644 index 00000000..e69de29b diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/dmesg.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/dmesg.log new file mode 100644 index 00000000..64eb5805 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/dmesg.log @@ -0,0 +1,1066 @@ +[ 0.000000] Initializing cgroup subsys cpuset +[ 0.000000] Initializing cgroup subsys cpu +[ 0.000000] Initializing cgroup subsys cpuacct +[ 0.000000] Linux version 3.13.0-39-lowlatency (root@devel.trisquel.info) (gcc version 4.8.2 (Ubuntu 4.8.2-19ubuntu1) ) #66+7.0trisquel2 SMP PREEMPT Wed Oct 29 17:10:10 UTC 2014 (Ubuntu 3.13.0-39.66+7.0trisquel2-lowlatency 3.13.11.8-gnu) +[ 0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-3.13.0-39-lowlatency root=UUID=097336a2-7389-4897-a7e8-1f43e91aae96 ro nomdmonddf nomdmonisw nomdmonddf nomdmonisw +[ 0.000000] KERNEL supported cpus: +[ 0.000000] Intel GenuineIntel +[ 0.000000] AMD AuthenticAMD +[ 0.000000] Centaur CentaurHauls +[ 0.000000] Disabled fast string operations +[ 0.000000] e820: BIOS-provided physical RAM map: +[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009ebff] usable +[ 0.000000] BIOS-e820: [mem 0x000000000009ec00-0x000000000009ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000000dc000-0x00000000000fffff] reserved +[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000796a0fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000796a1000-0x00000000796a6fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000796a7000-0x00000000797b6fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000797b7000-0x000000007980efff] reserved +[ 0.000000] BIOS-e820: [mem 0x000000007980f000-0x00000000798c6fff] usable +[ 0.000000] BIOS-e820: [mem 0x00000000798c7000-0x00000000798d1fff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000798d2000-0x00000000798d4fff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x00000000798d5000-0x00000000798d8fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000798d9000-0x00000000798dcfff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x00000000798dd000-0x00000000798dffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000798e0000-0x0000000079906fff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x0000000079907000-0x0000000079907fff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x0000000079908000-0x0000000079b0efff] reserved +[ 0.000000] BIOS-e820: [mem 0x0000000079b0f000-0x0000000079b9efff] ACPI NVS +[ 0.000000] BIOS-e820: [mem 0x0000000079b9f000-0x0000000079bfefff] ACPI data +[ 0.000000] BIOS-e820: [mem 0x0000000079bff000-0x0000000079bfffff] usable +[ 0.000000] BIOS-e820: [mem 0x0000000079c00000-0x000000007bffffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000e0000000-0x00000000efffffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fec00000-0x00000000fec0ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed00000-0x00000000fed003ff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed10000-0x00000000fed13fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed18000-0x00000000fed19fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fed1c000-0x00000000fed8ffff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000fee00000-0x00000000fee00fff] reserved +[ 0.000000] BIOS-e820: [mem 0x00000000ff800000-0x00000000ffffffff] reserved +[ 0.000000] NX (Execute Disable) protection: active +[ 0.000000] SMBIOS 2.4 present. +[ 0.000000] DMI: LENOVO 7459GW4/7459GW4, BIOS 6DET65WW (3.15 ) 08/24/2010 +[ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved +[ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable +[ 0.000000] No AGP bridge found +[ 0.000000] e820: last_pfn = 0x79c00 max_arch_pfn = 0x400000000 +[ 0.000000] MTRR default type: uncachable +[ 0.000000] MTRR fixed ranges enabled: +[ 0.000000] 00000-9FFFF write-back +[ 0.000000] A0000-BFFFF uncachable +[ 0.000000] C0000-D3FFF write-protect +[ 0.000000] D4000-DBFFF uncachable +[ 0.000000] DC000-FFFFF write-protect +[ 0.000000] MTRR variable ranges enabled: +[ 0.000000] 0 base 07D000000 mask FFF000000 uncachable +[ 0.000000] 1 base 07E000000 mask FFE000000 uncachable +[ 0.000000] 2 base 000000000 mask F80000000 write-back +[ 0.000000] 3 base 079E00000 mask FFFE00000 uncachable +[ 0.000000] 4 disabled +[ 0.000000] 5 disabled +[ 0.000000] 6 disabled +[ 0.000000] x86 PAT enabled: cpu 0, old 0x7040600070406, new 0x7010600070106 +[ 0.000000] original variable MTRRs +[ 0.000000] reg 0, base: 2000MB, range: 16MB, type UC +[ 0.000000] reg 1, base: 2016MB, range: 32MB, type UC +[ 0.000000] reg 2, base: 0GB, range: 2GB, type WB +[ 0.000000] reg 3, base: 1950MB, range: 2MB, type UC +[ 0.000000] total RAM covered: 1998M +[ 0.000000] gran_size: 64K chunk_size: 64K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 128K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 256K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 512K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 1M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 2M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 4M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 64K chunk_size: 8M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 64K chunk_size: 16M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 64K chunk_size: 32M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 64K chunk_size: 64M num_reg: 7 lose cover RAM: 0G +[ 0.000000] gran_size: 64K chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 64K chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 128K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 256K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 512K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 1M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 2M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 4M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 128K chunk_size: 8M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 128K chunk_size: 16M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 128K chunk_size: 32M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 128K chunk_size: 64M num_reg: 7 lose cover RAM: 0G +[ 0.000000] gran_size: 128K chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 128K chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 256K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 512K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 1M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 2M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 4M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 256K chunk_size: 8M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 256K chunk_size: 16M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 256K chunk_size: 32M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 256K chunk_size: 64M num_reg: 7 lose cover RAM: 0G +[ 0.000000] gran_size: 256K chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 256K chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 512K num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 1M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 2M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 4M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 512K chunk_size: 8M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 512K chunk_size: 16M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 512K chunk_size: 32M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 512K chunk_size: 64M num_reg: 7 lose cover RAM: 0G +[ 0.000000] gran_size: 512K chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 512K chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 1M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 2M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 4M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 1M chunk_size: 8M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 1M chunk_size: 16M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 1M chunk_size: 32M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 1M chunk_size: 64M num_reg: 7 lose cover RAM: 0G +[ 0.000000] gran_size: 1M chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 1M chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 2M chunk_size: 2M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 2M chunk_size: 4M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 2M chunk_size: 8M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 2M chunk_size: 16M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 2M chunk_size: 32M num_reg: 7 lose cover RAM: 16M +[ 0.000000] gran_size: 2M chunk_size: 64M num_reg: 7 lose cover RAM: 0G +[ 0.000000] gran_size: 2M chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 2M chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 2M chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 2M chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 2M chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 4M chunk_size: 4M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 4M chunk_size: 8M num_reg: 7 lose cover RAM: 18M +[ 0.000000] gran_size: 4M chunk_size: 16M num_reg: 7 lose cover RAM: 18M +[ 0.000000] gran_size: 4M chunk_size: 32M num_reg: 7 lose cover RAM: 18M +[ 0.000000] gran_size: 4M chunk_size: 64M num_reg: 7 lose cover RAM: 2M +[ 0.000000] gran_size: 4M chunk_size: 128M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 4M chunk_size: 256M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 4M chunk_size: 512M num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 4M chunk_size: 1G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 4M chunk_size: 2G num_reg: 7 lose cover RAM: 50M +[ 0.000000] gran_size: 8M chunk_size: 8M num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 16M num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 32M num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 64M num_reg: 7 lose cover RAM: 6M +[ 0.000000] gran_size: 8M chunk_size: 128M num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 256M num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 512M num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 1G num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 8M chunk_size: 2G num_reg: 7 lose cover RAM: 22M +[ 0.000000] gran_size: 16M chunk_size: 16M num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 16M chunk_size: 32M num_reg: 7 lose cover RAM: 30M +[ 0.000000] gran_size: 16M chunk_size: 64M num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 16M chunk_size: 128M num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 16M chunk_size: 256M num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 16M chunk_size: 512M num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 16M chunk_size: 1G num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 16M chunk_size: 2G num_reg: 7 lose cover RAM: 14M +[ 0.000000] gran_size: 32M chunk_size: 32M num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 32M chunk_size: 64M num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 32M chunk_size: 128M num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 32M chunk_size: 256M num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 32M chunk_size: 512M num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 32M chunk_size: 1G num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 32M chunk_size: 2G num_reg: 5 lose cover RAM: 46M +[ 0.000000] gran_size: 64M chunk_size: 64M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 64M chunk_size: 128M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 64M chunk_size: 256M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 64M chunk_size: 512M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 64M chunk_size: 1G num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 64M chunk_size: 2G num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 128M chunk_size: 128M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 128M chunk_size: 256M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 128M chunk_size: 512M num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 128M chunk_size: 1G num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 128M chunk_size: 2G num_reg: 4 lose cover RAM: 78M +[ 0.000000] gran_size: 256M chunk_size: 256M num_reg: 3 lose cover RAM: 206M +[ 0.000000] gran_size: 256M chunk_size: 512M num_reg: 3 lose cover RAM: 206M +[ 0.000000] gran_size: 256M chunk_size: 1G num_reg: 3 lose cover RAM: 206M +[ 0.000000] gran_size: 256M chunk_size: 2G num_reg: 3 lose cover RAM: 206M +[ 0.000000] gran_size: 512M chunk_size: 512M num_reg: 2 lose cover RAM: 462M +[ 0.000000] gran_size: 512M chunk_size: 1G num_reg: 2 lose cover RAM: 462M +[ 0.000000] gran_size: 512M chunk_size: 2G num_reg: 2 lose cover RAM: 462M +[ 0.000000] gran_size: 1G chunk_size: 1G num_reg: 1 lose cover RAM: 974M +[ 0.000000] gran_size: 1G chunk_size: 2G num_reg: 1 lose cover RAM: 974M +[ 0.000000] gran_size: 2G chunk_size: 2G num_reg: 0 lose cover RAM: 1998M +[ 0.000000] mtrr_cleanup: can not find optimal value +[ 0.000000] please specify mtrr_gran_size/mtrr_chunk_size +[ 0.000000] e820: update [mem 0x79e00000-0x79ffffff] usable ==> reserved +[ 0.000000] found SMP MP-table at [mem 0x000f72d0-0x000f72df] mapped at [ffff8800000f72d0] +[ 0.000000] Scanning 1 areas for low memory corruption +[ 0.000000] Base memory trampoline at [ffff880000098000] 98000 size 24576 +[ 0.000000] init_memory_mapping: [mem 0x00000000-0x000fffff] +[ 0.000000] [mem 0x00000000-0x000fffff] page 4k +[ 0.000000] BRK [0x01fd9000, 0x01fd9fff] PGTABLE +[ 0.000000] BRK [0x01fda000, 0x01fdafff] PGTABLE +[ 0.000000] BRK [0x01fdb000, 0x01fdbfff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0x79400000-0x795fffff] +[ 0.000000] [mem 0x79400000-0x795fffff] page 2M +[ 0.000000] BRK [0x01fdc000, 0x01fdcfff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0x78000000-0x793fffff] +[ 0.000000] [mem 0x78000000-0x793fffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0x00100000-0x77ffffff] +[ 0.000000] [mem 0x00100000-0x001fffff] page 4k +[ 0.000000] [mem 0x00200000-0x77ffffff] page 2M +[ 0.000000] init_memory_mapping: [mem 0x79600000-0x796a0fff] +[ 0.000000] [mem 0x79600000-0x796a0fff] page 4k +[ 0.000000] BRK [0x01fdd000, 0x01fddfff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0x796a7000-0x797b6fff] +[ 0.000000] [mem 0x796a7000-0x797b6fff] page 4k +[ 0.000000] init_memory_mapping: [mem 0x7980f000-0x798c6fff] +[ 0.000000] [mem 0x7980f000-0x798c6fff] page 4k +[ 0.000000] BRK [0x01fde000, 0x01fdefff] PGTABLE +[ 0.000000] init_memory_mapping: [mem 0x79bff000-0x79bfffff] +[ 0.000000] [mem 0x79bff000-0x79bfffff] page 4k +[ 0.000000] RAMDISK: [mem 0x35314000-0x36981fff] +[ 0.000000] ACPI: RSDP 00000000000f7290 000024 (v02 LENOVO) +[ 0.000000] ACPI: XSDT 0000000079b5b8ab 00008C (v01 LENOVO TP-6D 00003150 LTP 00000000) +[ 0.000000] ACPI: FACP 0000000079b5ba00 0000F4 (v03 LENOVO TP-6D 00003150 LNVO 00000001) +[ 0.000000] ACPI: DSDT 0000000079b5bdf4 00DF28 (v01 LENOVO TP-6D 00003150 MSFT 03000000) +[ 0.000000] ACPI: FACS 0000000079b8e000 000040 +[ 0.000000] ACPI: SSDT 0000000079b5bbb4 000240 (v01 LENOVO TP-6D 00003150 MSFT 03000000) +[ 0.000000] ACPI: ECDT 0000000079b69d1c 000052 (v01 LENOVO TP-6D 00003150 LNVO 00000001) +[ 0.000000] ACPI: APIC 0000000079b69d6e 000078 (v01 LENOVO TP-6D 00003150 LNVO 00000001) +[ 0.000000] ACPI: MCFG 0000000079b69de6 00003C (v01 LENOVO TP-6D 00003150 LNVO 00000001) +[ 0.000000] ACPI: HPET 0000000079b69e22 000038 (v01 LENOVO TP-6D 00003150 LNVO 00000001) +[ 0.000000] ACPI: BOOT 0000000079b69f38 000028 (v01 LENOVO TP-6D 00003150 LTP 00000001) +[ 0.000000] ACPI: ASF! 0000000079b69f60 0000A0 (v16 LENOVO TP-6D 00003150 PTL 00000001) +[ 0.000000] ACPI: SSDT 0000000079b8d1ea 000578 (v01 LENOVO TP-6D 00003150 INTL 20050513) +[ 0.000000] ACPI: TCPA 0000000079907000 000032 (v00 00000000 00000000) +[ 0.000000] ACPI: SSDT 00000000798d4000 000655 (v01 PmRef CpuPm 00003000 INTL 20050624) +[ 0.000000] ACPI: SSDT 00000000798d3000 000274 (v01 PmRef Cpu0Tst 00003000 INTL 20050624) +[ 0.000000] ACPI: SSDT 00000000798d2000 000242 (v01 PmRef ApTst 00003000 INTL 20050624) +[ 0.000000] ACPI: Local APIC address 0xfee00000 +[ 0.000000] No NUMA configuration found +[ 0.000000] Faking a node at [mem 0x0000000000000000-0x0000000079bfffff] +[ 0.000000] Initmem setup node 0 [mem 0x00000000-0x79bfffff] +[ 0.000000] NODE_DATA [mem 0x798c1000-0x798c5fff] +[ 0.000000] [ffffea0000000000-ffffea0001ffffff] PMD -> [ffff880076e00000-ffff880078dfffff] on node 0 +[ 0.000000] Zone ranges: +[ 0.000000] DMA [mem 0x00001000-0x00ffffff] +[ 0.000000] DMA32 [mem 0x01000000-0xffffffff] +[ 0.000000] Normal empty +[ 0.000000] Movable zone start for each node +[ 0.000000] Early memory node ranges +[ 0.000000] node 0: [mem 0x00001000-0x0009dfff] +[ 0.000000] node 0: [mem 0x00100000-0x796a0fff] +[ 0.000000] node 0: [mem 0x796a7000-0x797b6fff] +[ 0.000000] node 0: [mem 0x7980f000-0x798c6fff] +[ 0.000000] node 0: [mem 0x79bff000-0x79bfffff] +[ 0.000000] On node 0 totalpages: 497671 +[ 0.000000] DMA zone: 64 pages used for memmap +[ 0.000000] DMA zone: 21 pages reserved +[ 0.000000] DMA zone: 3997 pages, LIFO batch:0 +[ 0.000000] DMA32 zone: 7728 pages used for memmap +[ 0.000000] DMA32 zone: 493674 pages, LIFO batch:31 +[ 0.000000] ACPI: PM-Timer IO Port: 0x1008 +[ 0.000000] ACPI: Local APIC address 0xfee00000 +[ 0.000000] ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x01] enabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x02] lapic_id[0x02] disabled) +[ 0.000000] ACPI: LAPIC (acpi_id[0x03] lapic_id[0x03] disabled) +[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1]) +[ 0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1]) +[ 0.000000] ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0]) +[ 0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-23 +[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) +[ 0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level) +[ 0.000000] ACPI: IRQ0 used by override. +[ 0.000000] ACPI: IRQ2 used by override. +[ 0.000000] ACPI: IRQ9 used by override. +[ 0.000000] Using ACPI (MADT) for SMP configuration information +[ 0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000 +[ 0.000000] smpboot: Allowing 4 CPUs, 2 hotplug CPUs +[ 0.000000] nr_irqs_gsi: 40 +[ 0.000000] PM: Registered nosave memory: [mem 0x0009e000-0x0009efff] +[ 0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff] +[ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000dbfff] +[ 0.000000] PM: Registered nosave memory: [mem 0x000dc000-0x000fffff] +[ 0.000000] PM: Registered nosave memory: [mem 0x796a1000-0x796a6fff] +[ 0.000000] PM: Registered nosave memory: [mem 0x797b7000-0x7980efff] +[ 0.000000] PM: Registered nosave memory: [mem 0x798c7000-0x798d1fff] +[ 0.000000] PM: Registered nosave memory: [mem 0x798d2000-0x798d4fff] +[ 0.000000] PM: Registered nosave memory: [mem 0x798d5000-0x798d8fff] +[ 0.000000] PM: Registered nosave memory: [mem 0x798d9000-0x798dcfff] +[ 0.000000] PM: Registered nosave memory: [mem 0x798dd000-0x798dffff] +[ 0.000000] PM: Registered nosave memory: [mem 0x798e0000-0x79906fff] +[ 0.000000] PM: Registered nosave memory: [mem 0x79907000-0x79907fff] +[ 0.000000] PM: Registered nosave memory: [mem 0x79908000-0x79b0efff] +[ 0.000000] PM: Registered nosave memory: [mem 0x79b0f000-0x79b9efff] +[ 0.000000] PM: Registered nosave memory: [mem 0x79b9f000-0x79bfefff] +[ 0.000000] e820: [mem 0x7c000000-0xdfffffff] available for PCI devices +[ 0.000000] Booting paravirtualized kernel on bare hardware +[ 0.000000] setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:4 nr_node_ids:1 +[ 0.000000] PERCPU: Embedded 29 pages/cpu @ffff880079400000 s86848 r8192 d23744 u524288 +[ 0.000000] pcpu-alloc: s86848 r8192 d23744 u524288 alloc=1*2097152 +[ 0.000000] pcpu-alloc: [0] 0 1 2 3 +[ 0.000000] Built 1 zonelists in Node order, mobility grouping on. Total pages: 489858 +[ 0.000000] Policy zone: DMA32 +[ 0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-3.13.0-39-lowlatency root=UUID=097336a2-7389-4897-a7e8-1f43e91aae96 ro nomdmonddf nomdmonisw nomdmonddf nomdmonisw +[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes) +[ 0.000000] Checking aperture... +[ 0.000000] No AGP bridge found +[ 0.000000] Calgary: detecting Calgary via BIOS EBDA area +[ 0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing! +[ 0.000000] Memory: 1917872K/1990684K available (7418K kernel code, 1135K rwdata, 3420K rodata, 1324K init, 1444K bss, 72812K reserved) +[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1 +[ 0.000000] Preemptible hierarchical RCU implementation. +[ 0.000000] RCU dyntick-idle grace-period acceleration is enabled. +[ 0.000000] Dump stacks of tasks blocking RCU-preempt GP. +[ 0.000000] RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=4. +[ 0.000000] Offload RCU callbacks from all CPUs +[ 0.000000] Offload RCU callbacks from CPUs: 0-3. +[ 0.000000] NR_IRQS:16640 nr_irqs:712 16 +[ 0.000000] Console: colour VGA+ 80x25 +[ 0.000000] console [tty0] enabled +[ 0.000000] allocated 8388608 bytes of page_cgroup +[ 0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups +[ 0.000000] hpet clockevent registered +[ 0.000000] tsc: Fast TSC calibration using PIT +[ 0.000000] tsc: Detected 2393.987 MHz processor +[ 0.001004] Calibrating delay loop (skipped), value calculated using timer frequency.. 4787.97 BogoMIPS (lpj=2393987) +[ 0.001099] pid_max: default: 32768 minimum: 301 +[ 0.001179] Security Framework initialized +[ 0.001251] AppArmor: AppArmor initialized +[ 0.001296] Yama: becoming mindful. +[ 0.001557] Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes) +[ 0.002848] Inode-cache hash table entries: 131072 (order: 8, 1048576 bytes) +[ 0.003415] Mount-cache hash table entries: 4096 (order: 3, 32768 bytes) +[ 0.003468] Mountpoint-cache hash table entries: 4096 (order: 3, 32768 bytes) +[ 0.003789] Initializing cgroup subsys memory +[ 0.003844] Initializing cgroup subsys devices +[ 0.003891] Initializing cgroup subsys freezer +[ 0.003939] Initializing cgroup subsys blkio +[ 0.003986] Initializing cgroup subsys bfqio +[ 0.004005] Initializing cgroup subsys perf_event +[ 0.004053] Initializing cgroup subsys hugetlb +[ 0.004120] Disabled fast string operations +[ 0.004170] CPU: Physical Processor ID: 0 +[ 0.004216] CPU: Processor Core ID: 0 +[ 0.004262] mce: CPU supports 6 MCE banks +[ 0.004312] CPU0: Thermal monitoring enabled (TM2) +[ 0.004366] Last level iTLB entries: 4KB 128, 2MB 4, 4MB 4 +[ 0.004366] Last level dTLB entries: 4KB 256, 2MB 0, 4MB 32 +[ 0.004366] tlb_flushall_shift: -1 +[ 0.004516] Freeing SMP alternatives memory: 24K (ffffffff81e68000 - ffffffff81e6e000) +[ 0.006138] ACPI: Core revision 20131115 +[ 0.012497] ACPI: All ACPI Tables successfully acquired +[ 0.013011] ftrace: allocating 28647 entries in 112 pages +[ 0.022461] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1 +[ 0.032521] smpboot: CPU0: Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz (fam: 06, model: 17, stepping: 06) +[ 0.033000] Performance Events: PEBS fmt0+, 4-deep LBR, Core2 events, Intel PMU driver. +[ 0.033000] ... version: 2 +[ 0.033000] ... bit width: 40 +[ 0.033000] ... generic registers: 2 +[ 0.033000] ... value mask: 000000ffffffffff +[ 0.033000] ... max period: 000000007fffffff +[ 0.033000] ... fixed-purpose events: 3 +[ 0.033000] ... event mask: 0000000700000003 +[ 0.041071] x86: Booting SMP configuration: +[ 0.039030] Disabled fast string operations +[ 0.053119] NMI watchdog: enabled on all CPUs, permanently consumes one hw-PMU counter. +[ 0.041119] .... node #0, CPUs: #1 +[ 0.053279] x86: Booted up 1 node, 2 CPUs +[ 0.053366] smpboot: Total of 2 processors activated (9575.94 BogoMIPS) +[ 0.054131] devtmpfs: initialized +[ 0.057653] EVM: security.selinux +[ 0.057699] EVM: security.SMACK64 +[ 0.057744] EVM: security.ima +[ 0.057788] EVM: security.capability +[ 0.058036] PM: Registering ACPI NVS region [mem 0x798c7000-0x798d1fff] (45056 bytes) +[ 0.058098] PM: Registering ACPI NVS region [mem 0x798d9000-0x798dcfff] (16384 bytes) +[ 0.058098] PM: Registering ACPI NVS region [mem 0x798e0000-0x79906fff] (159744 bytes) +[ 0.058098] PM: Registering ACPI NVS region [mem 0x79b0f000-0x79b9efff] (589824 bytes) +[ 0.059097] pinctrl core: initialized pinctrl subsystem +[ 0.059220] regulator-dummy: no parameters +[ 0.059299] RTC time: 6:48:55, date: 08/30/15 +[ 0.059386] NET: Registered protocol family 16 +[ 0.059557] cpuidle: using governor ladder +[ 0.059604] cpuidle: using governor menu +[ 0.059697] ACPI FADT declares the system doesn't support PCIe ASPM, so disable it +[ 0.059758] ACPI: bus type PCI registered +[ 0.059805] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5 +[ 0.059912] PCI: MMCONFIG for domain 0000 [bus 00-3f] at [mem 0xe0000000-0xe3ffffff] (base 0xe0000000) +[ 0.059976] PCI: MMCONFIG at [mem 0xe0000000-0xe3ffffff] reserved in E820 +[ 0.067547] PCI: Using configuration type 1 for base access +[ 0.067698] mtrr: your CPUs had inconsistent variable MTRR settings +[ 0.067747] mtrr: probably your BIOS does not setup all CPUs. +[ 0.067795] mtrr: corrected configuration. +[ 0.069011] bio: create slab at 0 +[ 0.069081] ACPI: Added _OSI(Module Device) +[ 0.069129] ACPI: Added _OSI(Processor Device) +[ 0.069176] ACPI: Added _OSI(3.0 _SCP Extensions) +[ 0.069176] ACPI: Added _OSI(Processor Aggregator Device) +[ 0.071018] ACPI : EC: EC description table is found, configuring boot EC +[ 0.075408] [Firmware Bug]: ACPI: BIOS _OSI(Linux) query ignored +[ 0.082370] ACPI: SSDT 00000000798d7c20 0002C8 (v01 PmRef Cpu0Ist 00003000 INTL 20050624) +[ 0.083085] ACPI: Dynamic OEM Table Load: +[ 0.083193] ACPI: SSDT (null) 0002C8 (v01 PmRef Cpu0Ist 00003000 INTL 20050624) +[ 0.083433] ACPI: SSDT 00000000798d5020 00087A (v01 PmRef Cpu0Cst 00003001 INTL 20050624) +[ 0.083951] ACPI: Dynamic OEM Table Load: +[ 0.084045] ACPI: SSDT (null) 00087A (v01 PmRef Cpu0Cst 00003001 INTL 20050624) +[ 0.087198] ACPI: SSDT 00000000798d6ca0 0001CF (v01 PmRef ApIst 00003000 INTL 20050624) +[ 0.088064] ACPI: Dynamic OEM Table Load: +[ 0.088171] ACPI: SSDT (null) 0001CF (v01 PmRef ApIst 00003000 INTL 20050624) +[ 0.089066] ACPI: SSDT 00000000798d6f20 00008D (v01 PmRef ApCst 00003000 INTL 20050624) +[ 0.089562] ACPI: Dynamic OEM Table Load: +[ 0.090005] ACPI: SSDT (null) 00008D (v01 PmRef ApCst 00003000 INTL 20050624) +[ 0.092138] ACPI: Interpreter enabled +[ 0.092190] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S1_] (20131115/hwxface-580) +[ 0.092315] ACPI Exception: AE_NOT_FOUND, While evaluating Sleep State [\_S2_] (20131115/hwxface-580) +[ 0.092449] ACPI: (supports S0 S3 S4 S5) +[ 0.092496] ACPI: Using IOAPIC for interrupt routing +[ 0.092565] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug +[ 0.093465] ACPI: ACPI Dock Station Driver: 3 docks/bays found +[ 0.103102] ACPI: Power Resource [PUBS] (on) +[ 0.108348] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.108789] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.109225] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.109664] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.110091] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.110528] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.110966] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.111407] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 10 *11) +[ 0.111809] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) +[ 0.111863] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] +[ 0.112338] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability] +[ 0.112429] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-3f] only partially covers this bridge +[ 0.112651] PCI host bridge to bus 0000:00 +[ 0.112699] pci_bus 0000:00: root bus resource [bus 00-ff] +[ 0.112748] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7] +[ 0.112797] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff] +[ 0.112847] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] +[ 0.112897] pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff] +[ 0.112947] pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff] +[ 0.112997] pci_bus 0000:00: root bus resource [mem 0x7c000000-0xfebfffff] +[ 0.113013] pci 0000:00:00.0: [8086:2a40] type 00 class 0x060000 +[ 0.113033] DMAR: Forcing write-buffer flush capability +[ 0.113081] DMAR: Disabling IOMMU for graphics on this chipset +[ 0.113196] pci 0000:00:02.0: [8086:2a42] type 00 class 0x030000 +[ 0.113209] pci 0000:00:02.0: reg 0x10: [mem 0xf2000000-0xf23fffff 64bit] +[ 0.113216] pci 0000:00:02.0: reg 0x18: [mem 0xd0000000-0xdfffffff 64bit pref] +[ 0.113222] pci 0000:00:02.0: reg 0x20: [io 0x1800-0x1807] +[ 0.113301] pci 0000:00:02.1: [8086:2a43] type 00 class 0x038000 +[ 0.113311] pci 0000:00:02.1: reg 0x10: [mem 0xf2400000-0xf24fffff 64bit] +[ 0.113403] pci 0000:00:03.0: [8086:2a44] type 00 class 0x078000 +[ 0.113419] pci 0000:00:03.0: reg 0x10: [mem 0xf2826800-0xf282680f 64bit] +[ 0.113469] pci 0000:00:03.0: PME# supported from D0 D3hot D3cold +[ 0.113534] pci 0000:00:03.3: [8086:2a47] type 00 class 0x070002 +[ 0.113548] pci 0000:00:03.3: reg 0x10: [io 0x1830-0x1837] +[ 0.113555] pci 0000:00:03.3: reg 0x14: [mem 0xf2624000-0xf2624fff] +[ 0.113704] pci 0000:00:19.0: [8086:10f5] type 00 class 0x020000 +[ 0.113729] pci 0000:00:19.0: reg 0x10: [mem 0xf2600000-0xf261ffff] +[ 0.113740] pci 0000:00:19.0: reg 0x14: [mem 0xf2625000-0xf2625fff] +[ 0.113751] pci 0000:00:19.0: reg 0x18: [io 0x1840-0x185f] +[ 0.113839] pci 0000:00:19.0: PME# supported from D0 D3hot D3cold +[ 0.113882] pci 0000:00:19.0: System wakeup disabled by ACPI +[ 0.114019] pci 0000:00:1a.0: [8086:2937] type 00 class 0x0c0300 +[ 0.114075] pci 0000:00:1a.0: reg 0x20: [io 0x1860-0x187f] +[ 0.114173] pci 0000:00:1a.0: System wakeup disabled by ACPI +[ 0.114259] pci 0000:00:1a.1: [8086:2938] type 00 class 0x0c0300 +[ 0.114315] pci 0000:00:1a.1: reg 0x20: [io 0x1880-0x189f] +[ 0.114427] pci 0000:00:1a.2: [8086:2939] type 00 class 0x0c0300 +[ 0.114483] pci 0000:00:1a.2: reg 0x20: [io 0x18a0-0x18bf] +[ 0.114579] pci 0000:00:1a.2: System wakeup disabled by ACPI +[ 0.114674] pci 0000:00:1a.7: [8086:293c] type 00 class 0x0c0320 +[ 0.114700] pci 0000:00:1a.7: reg 0x10: [mem 0xf2826c00-0xf2826fff] +[ 0.114810] pci 0000:00:1a.7: PME# supported from D0 D3hot D3cold +[ 0.114854] pci 0000:00:1a.7: System wakeup disabled by ACPI +[ 0.114944] pci 0000:00:1b.0: [8086:293e] type 00 class 0x040300 +[ 0.114964] pci 0000:00:1b.0: reg 0x10: [mem 0xf2620000-0xf2623fff 64bit] +[ 0.115066] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold +[ 0.115120] pci 0000:00:1b.0: System wakeup disabled by ACPI +[ 0.115204] pci 0000:00:1c.0: [8086:2940] type 01 class 0x060400 +[ 0.115305] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold +[ 0.115352] pci 0000:00:1c.0: System wakeup disabled by ACPI +[ 0.115436] pci 0000:00:1c.1: [8086:2942] type 01 class 0x060400 +[ 0.115536] pci 0000:00:1c.1: PME# supported from D0 D3hot D3cold +[ 0.115584] pci 0000:00:1c.1: System wakeup disabled by ACPI +[ 0.115669] pci 0000:00:1c.3: [8086:2946] type 01 class 0x060400 +[ 0.115769] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold +[ 0.115816] pci 0000:00:1c.3: System wakeup disabled by ACPI +[ 0.115906] pci 0000:00:1d.0: [8086:2934] type 00 class 0x0c0300 +[ 0.115962] pci 0000:00:1d.0: reg 0x20: [io 0x18c0-0x18df] +[ 0.116067] pci 0000:00:1d.0: System wakeup disabled by ACPI +[ 0.116153] pci 0000:00:1d.1: [8086:2935] type 00 class 0x0c0300 +[ 0.116209] pci 0000:00:1d.1: reg 0x20: [io 0x18e0-0x18ff] +[ 0.116320] pci 0000:00:1d.2: [8086:2936] type 00 class 0x0c0300 +[ 0.116376] pci 0000:00:1d.2: reg 0x20: [io 0x1c00-0x1c1f] +[ 0.116498] pci 0000:00:1d.7: [8086:293a] type 00 class 0x0c0320 +[ 0.116523] pci 0000:00:1d.7: reg 0x10: [mem 0xf2827000-0xf28273ff] +[ 0.116632] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold +[ 0.116678] pci 0000:00:1d.7: System wakeup disabled by ACPI +[ 0.116764] pci 0000:00:1e.0: [8086:2448] type 01 class 0x060401 +[ 0.116898] pci 0000:00:1f.0: [8086:2917] type 00 class 0x060100 +[ 0.117115] pci 0000:00:1f.2: [8086:2929] type 00 class 0x010601 +[ 0.117142] pci 0000:00:1f.2: reg 0x10: [io 0x1c48-0x1c4f] +[ 0.117153] pci 0000:00:1f.2: reg 0x14: [io 0x183c-0x183f] +[ 0.117164] pci 0000:00:1f.2: reg 0x18: [io 0x1c40-0x1c47] +[ 0.117175] pci 0000:00:1f.2: reg 0x1c: [io 0x1838-0x183b] +[ 0.117186] pci 0000:00:1f.2: reg 0x20: [io 0x1c20-0x1c3f] +[ 0.117197] pci 0000:00:1f.2: reg 0x24: [mem 0xf2826000-0xf28267ff] +[ 0.117265] pci 0000:00:1f.2: PME# supported from D3hot +[ 0.117338] pci 0000:00:1f.3: [8086:2930] type 00 class 0x0c0500 +[ 0.117359] pci 0000:00:1f.3: reg 0x10: [mem 0xf2827400-0xf28274ff 64bit] +[ 0.117388] pci 0000:00:1f.3: reg 0x20: [io 0x1c60-0x1c7f] +[ 0.117535] pci 0000:00:1c.0: PCI bridge to [bus 02] +[ 0.117690] pci 0000:03:00.0: [8086:4237] type 00 class 0x028000 +[ 0.117730] pci 0000:03:00.0: reg 0x10: [mem 0xf2500000-0xf2501fff 64bit] +[ 0.117924] pci 0000:03:00.0: PME# supported from D0 D3hot D3cold +[ 0.119021] pci 0000:00:1c.1: PCI bridge to [bus 03] +[ 0.119076] pci 0000:00:1c.1: bridge window [mem 0xf2500000-0xf25fffff] +[ 0.119155] pci 0000:00:1c.3: PCI bridge to [bus 05-0c] +[ 0.119207] pci 0000:00:1c.3: bridge window [io 0x2000-0x2fff] +[ 0.119211] pci 0000:00:1c.3: bridge window [mem 0xf0000000-0xf1ffffff] +[ 0.119219] pci 0000:00:1c.3: bridge window [mem 0xf2900000-0xf29fffff 64bit pref] +[ 0.119318] pci 0000:00:1e.0: PCI bridge to [bus 0d] (subtractive decode) +[ 0.119318] pci 0000:00:1e.0: bridge window [io 0x0000-0x0cf7] (subtractive decode) +[ 0.119318] pci 0000:00:1e.0: bridge window [io 0x0d00-0xffff] (subtractive decode) +[ 0.119318] pci 0000:00:1e.0: bridge window [mem 0x000a0000-0x000bffff] (subtractive decode) +[ 0.119318] pci 0000:00:1e.0: bridge window [mem 0x000d4000-0x000d7fff] (subtractive decode) +[ 0.119318] pci 0000:00:1e.0: bridge window [mem 0x000d8000-0x000dbfff] (subtractive decode) +[ 0.119318] pci 0000:00:1e.0: bridge window [mem 0x7c000000-0xfebfffff] (subtractive decode) +[ 0.119318] acpi PNP0A08:00: Disabling ASPM (FADT indicates it is unsupported) +[ 0.121307] ACPI: Enabled 3 GPEs in block 00 to 3F +[ 0.121425] ACPI: \_SB_.PCI0: notify handler is installed +[ 0.121469] Found 1 acpi root devices +[ 0.121543] ACPI : EC: GPE = 0x11, I/O: command/status = 0x66, data = 0x62 +[ 0.121671] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none +[ 0.121671] vgaarb: loaded +[ 0.121671] vgaarb: bridge control possible 0000:00:02.0 +[ 0.122188] SCSI subsystem initialized +[ 0.122251] libata version 3.00 loaded. +[ 0.122251] ACPI: bus type USB registered +[ 0.122251] usbcore: registered new interface driver usbfs +[ 0.122251] usbcore: registered new interface driver hub +[ 0.122251] usbcore: registered new device driver usb +[ 0.123053] PCI: Using ACPI for IRQ routing +[ 0.125422] PCI: pci_cache_line_size set to 64 bytes +[ 0.125494] e820: reserve RAM buffer [mem 0x0009ec00-0x0009ffff] +[ 0.125496] e820: reserve RAM buffer [mem 0x796a1000-0x7bffffff] +[ 0.125498] e820: reserve RAM buffer [mem 0x797b7000-0x7bffffff] +[ 0.125500] e820: reserve RAM buffer [mem 0x798c7000-0x7bffffff] +[ 0.125503] e820: reserve RAM buffer [mem 0x79c00000-0x7bffffff] +[ 0.125588] NetLabel: Initializing +[ 0.125634] NetLabel: domain hash size = 128 +[ 0.125680] NetLabel: protocols = UNLABELED CIPSOv4 +[ 0.125737] NetLabel: unlabeled traffic allowed by default +[ 0.125795] HPET: 4 timers in total, 0 timers will be used for per-cpu timer +[ 0.125795] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0 +[ 0.126107] hpet0: 4 comparators, 64-bit 14.318180 MHz counter +[ 0.128030] Switched to clocksource hpet +[ 0.134288] AppArmor: AppArmor Filesystem Enabled +[ 0.134388] pnp: PnP ACPI init +[ 0.134450] ACPI: bus type PNP registered +[ 0.154864] system 00:00: [mem 0x00000000-0x0009ffff] could not be reserved +[ 0.154916] system 00:00: [mem 0x000c0000-0x000c3fff] could not be reserved +[ 0.154967] system 00:00: [mem 0x000c4000-0x000c7fff] could not be reserved +[ 0.155029] system 00:00: [mem 0x000c8000-0x000cbfff] has been reserved +[ 0.155080] system 00:00: [mem 0x000cc000-0x000cffff] has been reserved +[ 0.155130] system 00:00: [mem 0x000d0000-0x000d3fff] could not be reserved +[ 0.155181] system 00:00: [mem 0x000dc000-0x000dffff] could not be reserved +[ 0.155231] system 00:00: [mem 0x000e0000-0x000e3fff] could not be reserved +[ 0.155282] system 00:00: [mem 0x000e4000-0x000e7fff] could not be reserved +[ 0.155332] system 00:00: [mem 0x000e8000-0x000ebfff] could not be reserved +[ 0.155383] system 00:00: [mem 0x000ec000-0x000effff] could not be reserved +[ 0.155433] system 00:00: [mem 0x000f0000-0x000fffff] could not be reserved +[ 0.155484] system 00:00: [mem 0x00100000-0x7bffffff] could not be reserved +[ 0.155535] system 00:00: [mem 0xfec00000-0xfed3ffff] could not be reserved +[ 0.155585] system 00:00: [mem 0xfed4c000-0xffffffff] could not be reserved +[ 0.155638] system 00:00: Plug and Play ACPI device, IDs PNP0c01 (active) +[ 0.175625] system 00:01: [io 0x1000-0x107f] could not be reserved +[ 0.175676] system 00:01: [io 0x1180-0x11ff] has been reserved +[ 0.175726] system 00:01: [io 0x0800-0x080f] has been reserved +[ 0.175775] system 00:01: [io 0x15e0-0x15ef] has been reserved +[ 0.175825] system 00:01: [io 0x1600-0x167f] has been reserved +[ 0.175874] system 00:01: [io 0x1680-0x169f] has been reserved +[ 0.175923] system 00:01: [mem 0xe0000000-0xefffffff] has been reserved +[ 0.175974] system 00:01: [mem 0xfed1c000-0xfed1ffff] has been reserved +[ 0.176035] system 00:01: [mem 0xfed10000-0xfed13fff] has been reserved +[ 0.176086] system 00:01: [mem 0xfed18000-0xfed18fff] has been reserved +[ 0.176136] system 00:01: [mem 0xfed19000-0xfed19fff] has been reserved +[ 0.176187] system 00:01: [mem 0xfed45000-0xfed4bfff] has been reserved +[ 0.176238] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active) +[ 0.176291] pnp 00:02: Plug and Play ACPI device, IDs PNP0103 (active) +[ 0.176300] pnp 00:03: [dma 4] +[ 0.176318] pnp 00:03: Plug and Play ACPI device, IDs PNP0200 (active) +[ 0.176344] pnp 00:04: Plug and Play ACPI device, IDs PNP0800 (active) +[ 0.176381] pnp 00:05: Plug and Play ACPI device, IDs PNP0c04 (active) +[ 0.176413] pnp 00:06: Plug and Play ACPI device, IDs PNP0b00 (active) +[ 0.176441] pnp 00:07: Plug and Play ACPI device, IDs PNP0303 (active) +[ 0.176472] pnp 00:08: Plug and Play ACPI device, IDs IBM3780 PNP0f13 (active) +[ 0.196442] pnp 00:09: Plug and Play ACPI device, IDs PNP0c31 (active) +[ 0.196872] pnp: PnP ACPI: found 10 devices +[ 0.196919] ACPI: bus type PNP unregistered +[ 0.203744] pci 0000:00:1c.0: bridge window [io 0x1000-0x0fff] to [bus 02] add_size 1000 +[ 0.203748] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 02] add_size 200000 +[ 0.203751] pci 0000:00:1c.0: bridge window [mem 0x00100000-0x000fffff] to [bus 02] add_size 200000 +[ 0.203761] pci 0000:00:1c.1: bridge window [io 0x1000-0x0fff] to [bus 03] add_size 1000 +[ 0.203764] pci 0000:00:1c.1: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 03] add_size 200000 +[ 0.203790] pci 0000:00:1c.0: res[14]=[mem 0x00100000-0x000fffff] get_res_add_size add_size 200000 +[ 0.203792] pci 0000:00:1c.0: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000 +[ 0.203794] pci 0000:00:1c.1: res[15]=[mem 0x00100000-0x000fffff 64bit pref] get_res_add_size add_size 200000 +[ 0.203797] pci 0000:00:1c.0: res[13]=[io 0x1000-0x0fff] get_res_add_size add_size 1000 +[ 0.203799] pci 0000:00:1c.1: res[13]=[io 0x1000-0x0fff] get_res_add_size add_size 1000 +[ 0.203803] pci 0000:00:1c.0: BAR 14: assigned [mem 0x7c000000-0x7c1fffff] +[ 0.203855] pci 0000:00:1c.0: BAR 15: assigned [mem 0x7c200000-0x7c3fffff 64bit pref] +[ 0.203917] pci 0000:00:1c.1: BAR 15: assigned [mem 0x7c400000-0x7c5fffff 64bit pref] +[ 0.203979] pci 0000:00:1c.0: BAR 13: assigned [io 0x3000-0x3fff] +[ 0.204040] pci 0000:00:1c.1: BAR 13: assigned [io 0x4000-0x4fff] +[ 0.204091] pci 0000:00:1c.0: PCI bridge to [bus 02] +[ 0.204141] pci 0000:00:1c.0: bridge window [io 0x3000-0x3fff] +[ 0.204194] pci 0000:00:1c.0: bridge window [mem 0x7c000000-0x7c1fffff] +[ 0.204247] pci 0000:00:1c.0: bridge window [mem 0x7c200000-0x7c3fffff 64bit pref] +[ 0.204313] pci 0000:00:1c.1: PCI bridge to [bus 03] +[ 0.204362] pci 0000:00:1c.1: bridge window [io 0x4000-0x4fff] +[ 0.204415] pci 0000:00:1c.1: bridge window [mem 0xf2500000-0xf25fffff] +[ 0.204468] pci 0000:00:1c.1: bridge window [mem 0x7c400000-0x7c5fffff 64bit pref] +[ 0.204534] pci 0000:00:1c.3: PCI bridge to [bus 05-0c] +[ 0.204583] pci 0000:00:1c.3: bridge window [io 0x2000-0x2fff] +[ 0.204636] pci 0000:00:1c.3: bridge window [mem 0xf0000000-0xf1ffffff] +[ 0.204689] pci 0000:00:1c.3: bridge window [mem 0xf2900000-0xf29fffff 64bit pref] +[ 0.204755] pci 0000:00:1e.0: PCI bridge to [bus 0d] +[ 0.204815] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7] +[ 0.204817] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff] +[ 0.204819] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff] +[ 0.204821] pci_bus 0000:00: resource 7 [mem 0x000d4000-0x000d7fff] +[ 0.204823] pci_bus 0000:00: resource 8 [mem 0x000d8000-0x000dbfff] +[ 0.204824] pci_bus 0000:00: resource 9 [mem 0x7c000000-0xfebfffff] +[ 0.204827] pci_bus 0000:02: resource 0 [io 0x3000-0x3fff] +[ 0.204828] pci_bus 0000:02: resource 1 [mem 0x7c000000-0x7c1fffff] +[ 0.204830] pci_bus 0000:02: resource 2 [mem 0x7c200000-0x7c3fffff 64bit pref] +[ 0.204832] pci_bus 0000:03: resource 0 [io 0x4000-0x4fff] +[ 0.204834] pci_bus 0000:03: resource 1 [mem 0xf2500000-0xf25fffff] +[ 0.204836] pci_bus 0000:03: resource 2 [mem 0x7c400000-0x7c5fffff 64bit pref] +[ 0.204838] pci_bus 0000:05: resource 0 [io 0x2000-0x2fff] +[ 0.204840] pci_bus 0000:05: resource 1 [mem 0xf0000000-0xf1ffffff] +[ 0.204842] pci_bus 0000:05: resource 2 [mem 0xf2900000-0xf29fffff 64bit pref] +[ 0.204844] pci_bus 0000:0d: resource 4 [io 0x0000-0x0cf7] +[ 0.204846] pci_bus 0000:0d: resource 5 [io 0x0d00-0xffff] +[ 0.204848] pci_bus 0000:0d: resource 6 [mem 0x000a0000-0x000bffff] +[ 0.204850] pci_bus 0000:0d: resource 7 [mem 0x000d4000-0x000d7fff] +[ 0.204852] pci_bus 0000:0d: resource 8 [mem 0x000d8000-0x000dbfff] +[ 0.204853] pci_bus 0000:0d: resource 9 [mem 0x7c000000-0xfebfffff] +[ 0.204887] NET: Registered protocol family 2 +[ 0.205147] TCP established hash table entries: 16384 (order: 5, 131072 bytes) +[ 0.205279] TCP bind hash table entries: 16384 (order: 6, 262144 bytes) +[ 0.205428] TCP: Hash tables configured (established 16384 bind 16384) +[ 0.205529] TCP: reno registered +[ 0.205578] UDP hash table entries: 1024 (order: 3, 32768 bytes) +[ 0.205641] UDP-Lite hash table entries: 1024 (order: 3, 32768 bytes) +[ 0.205757] NET: Registered protocol family 1 +[ 0.205816] pci 0000:00:02.0: Boot video device +[ 0.206766] PCI: CLS 64 bytes, default 64 +[ 0.206828] Trying to unpack rootfs image as initramfs... +[ 0.654139] Freeing initrd memory: 22968K (ffff880035314000 - ffff880036982000) +[ 0.654271] Simple Boot Flag at 0x35 set to 0x1 +[ 0.654472] microcode: CPU0 sig=0x10676, pf=0x80, revision=0x60c +[ 0.654527] microcode: CPU1 sig=0x10676, pf=0x80, revision=0x60c +[ 0.654675] microcode: Microcode Update Driver: v2.00 , Peter Oruba +[ 0.654738] Scanning for low memory corruption every 60 seconds +[ 0.655070] Initialise system trusted keyring +[ 0.655166] audit: initializing netlink socket (disabled) +[ 0.655228] type=2000 audit(1440917335.654:1): initialized +[ 0.677686] HugeTLB registered 2 MB page size, pre-allocated 0 pages +[ 0.678936] zbud: loaded +[ 0.679129] VFS: Disk quotas dquot_6.5.2 +[ 0.679222] Dquot-cache hash table entries: 512 (order 0, 4096 bytes) +[ 0.679760] fuse init (API version 7.22) +[ 0.679888] msgmni has been set to 3790 +[ 0.679992] Key type big_key registered +[ 0.680581] Key type asymmetric registered +[ 0.680630] Asymmetric key parser 'x509' registered +[ 0.680708] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 252) +[ 0.680805] io scheduler noop registered +[ 0.680854] io scheduler deadline registered +[ 0.680926] io scheduler cfq registered +[ 0.680975] io scheduler bfq registered (default) +[ 0.681033] BFQ I/O-scheduler version: v7r5 +[ 0.681277] pcieport 0000:00:1c.0: irq 40 for MSI/MSI-X +[ 0.681485] pcieport 0000:00:1c.1: irq 41 for MSI/MSI-X +[ 0.681648] pcieport 0000:00:1c.3: irq 42 for MSI/MSI-X +[ 0.681801] pcieport 0000:00:1c.0: Signaling PME through PCIe PME interrupt +[ 0.681856] pcie_pme 0000:00:1c.0:pcie01: service driver pcie_pme loaded +[ 0.681914] pcieport 0000:00:1c.1: Signaling PME through PCIe PME interrupt +[ 0.681967] pci 0000:03:00.0: Signaling PME through PCIe PME interrupt +[ 0.682032] pcie_pme 0000:00:1c.1:pcie01: service driver pcie_pme loaded +[ 0.682086] pcieport 0000:00:1c.3: Signaling PME through PCIe PME interrupt +[ 0.682140] pcie_pme 0000:00:1c.3:pcie01: service driver pcie_pme loaded +[ 0.682156] pci_hotplug: PCI Hot Plug PCI Core version: 0.5 +[ 0.682263] pciehp 0000:00:1c.0:pcie04: HPC vendor_id 8086 device_id 2940 ss_vid 17aa ss_did 20f3 +[ 0.682387] pciehp 0000:00:1c.0:pcie04: service driver pciehp loaded +[ 0.682402] pciehp 0000:00:1c.1:pcie04: HPC vendor_id 8086 device_id 2942 ss_vid 17aa ss_did 20f3 +[ 0.682519] pciehp 0000:00:1c.1:pcie04: service driver pciehp loaded +[ 0.682533] pciehp 0000:00:1c.3:pcie04: HPC vendor_id 8086 device_id 2946 ss_vid 17aa ss_did 20f3 +[ 0.682653] pciehp 0000:00:1c.3:pcie04: service driver pciehp loaded +[ 0.682659] pciehp: PCI Express Hot Plug Controller Driver version: 0.4 +[ 0.682755] intel_idle: does not run on family 6 model 23 +[ 0.682764] ipmi message handler version 39.2 +[ 0.682977] ACPI: Deprecated procfs I/F for AC is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +[ 0.683222] ACPI: AC Adapter [AC] (on-line) +[ 0.683362] input: Lid Switch as /devices/LNXSYSTM:00/device:00/PNP0C0D:00/input/input0 +[ 0.683702] ACPI: Lid Switch [LID] +[ 0.683781] input: Sleep Button as /devices/LNXSYSTM:00/device:00/PNP0C0E:00/input/input1 +[ 0.683844] ACPI: Sleep Button [SLPB] +[ 0.683929] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2 +[ 0.683991] ACPI: Power Button [PWRF] +[ 0.685432] Monitor-Mwait will be used to enter C-1 state +[ 0.685438] Monitor-Mwait will be used to enter C-2 state +[ 0.685441] Monitor-Mwait will be used to enter C-3 state +[ 0.685444] tsc: Marking TSC unstable due to TSC halts in idle +[ 0.685502] ACPI: acpi_idle registered with cpuidle +[ 0.687967] thermal LNXTHERM:00: registered as thermal_zone0 +[ 0.688045] ACPI: Thermal Zone [THM0] (56 C) +[ 0.689472] thermal LNXTHERM:01: registered as thermal_zone1 +[ 0.689527] ACPI: Thermal Zone [THM1] (55 C) +[ 0.689603] GHES: HEST is not enabled! +[ 0.689793] ACPI: Deprecated procfs I/F for battery is loaded, please retry with CONFIG_ACPI_PROCFS_POWER cleared +[ 0.689861] ACPI: Battery Slot [BAT0] (battery absent) +[ 0.689943] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled +[ 0.712208] 0000:00:03.3: ttyS4 at I/O 0x1830 (irq = 17, base_baud = 115200) is a 16550A +[ 0.712544] Linux agpgart interface v0.103 +[ 0.712661] agpgart-intel 0000:00:00.0: Intel GM45 Chipset +[ 0.712794] agpgart-intel 0000:00:00.0: detected gtt size: 2097152K total, 262144K mappable +[ 0.713914] agpgart-intel 0000:00:00.0: detected 32768K stolen memory +[ 0.714136] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xd0000000 +[ 0.720051] tpm_tis 00:09: 1.2 TPM (device-id 0x1020, rev-id 6) +[ 0.720104] tpm_tis 00:09: Intel iTPM workaround enabled +[ 0.792118] tpm_tis 00:09: TPM is disabled/deactivated (0x6) +[ 0.793802] brd: module loaded +[ 0.794673] loop: module loaded +[ 0.795114] libphy: Fixed MDIO Bus: probed +[ 0.795245] tun: Universal TUN/TAP device driver, 1.6 +[ 0.795292] tun: (C) 1999-2004 Max Krasnyansky +[ 0.795389] PPP generic driver version 2.4.2 +[ 0.795505] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver +[ 0.795557] ehci-pci: EHCI PCI platform driver +[ 0.795729] ehci-pci 0000:00:1a.7: EHCI Host Controller +[ 0.795781] ehci-pci 0000:00:1a.7: new USB bus registered, assigned bus number 1 +[ 0.795855] ehci-pci 0000:00:1a.7: debug port 1 +[ 0.799819] ehci-pci 0000:00:1a.7: cache line size of 64 is not supported +[ 0.799914] ehci-pci 0000:00:1a.7: irq 23, io mem 0xf2826c00 +[ 0.806055] ehci-pci 0000:00:1a.7: USB 2.0 started, EHCI 1.00 +[ 0.806198] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002 +[ 0.806249] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.806309] usb usb1: Product: EHCI Host Controller +[ 0.806356] usb usb1: Manufacturer: Linux 3.13.0-39-lowlatency ehci_hcd +[ 0.806406] usb usb1: SerialNumber: 0000:00:1a.7 +[ 0.806572] hub 1-0:1.0: USB hub found +[ 0.806625] hub 1-0:1.0: 6 ports detected +[ 0.806964] ehci-pci 0000:00:1d.7: EHCI Host Controller +[ 0.807027] ehci-pci 0000:00:1d.7: new USB bus registered, assigned bus number 2 +[ 0.807102] ehci-pci 0000:00:1d.7: debug port 1 +[ 0.811047] ehci-pci 0000:00:1d.7: cache line size of 64 is not supported +[ 0.811128] ehci-pci 0000:00:1d.7: irq 19, io mem 0xf2827000 +[ 0.817124] ehci-pci 0000:00:1d.7: USB 2.0 started, EHCI 1.00 +[ 0.817761] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002 +[ 0.817811] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.817871] usb usb2: Product: EHCI Host Controller +[ 0.817919] usb usb2: Manufacturer: Linux 3.13.0-39-lowlatency ehci_hcd +[ 0.817968] usb usb2: SerialNumber: 0000:00:1d.7 +[ 0.818141] hub 2-0:1.0: USB hub found +[ 0.818192] hub 2-0:1.0: 6 ports detected +[ 0.818460] ehci-platform: EHCI generic platform driver +[ 0.818515] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver +[ 0.818986] ohci-pci: OHCI PCI platform driver +[ 0.819056] ohci-platform: OHCI generic platform driver +[ 0.819118] uhci_hcd: USB Universal Host Controller Interface driver +[ 0.819235] uhci_hcd 0000:00:1a.0: UHCI Host Controller +[ 0.819286] uhci_hcd 0000:00:1a.0: new USB bus registered, assigned bus number 3 +[ 0.819442] uhci_hcd 0000:00:1a.0: irq 20, io base 0x00001860 +[ 0.819539] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.819590] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.819651] usb usb3: Product: UHCI Host Controller +[ 0.819698] usb usb3: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.819748] usb usb3: SerialNumber: 0000:00:1a.0 +[ 0.819903] hub 3-0:1.0: USB hub found +[ 0.819962] hub 3-0:1.0: 2 ports detected +[ 0.820186] uhci_hcd 0000:00:1a.1: UHCI Host Controller +[ 0.820237] uhci_hcd 0000:00:1a.1: new USB bus registered, assigned bus number 4 +[ 0.820407] uhci_hcd 0000:00:1a.1: irq 21, io base 0x00001880 +[ 0.820506] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.820557] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.820617] usb usb4: Product: UHCI Host Controller +[ 0.820665] usb usb4: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.820714] usb usb4: SerialNumber: 0000:00:1a.1 +[ 0.820868] hub 4-0:1.0: USB hub found +[ 0.820930] hub 4-0:1.0: 2 ports detected +[ 0.821160] uhci_hcd 0000:00:1a.2: UHCI Host Controller +[ 0.821212] uhci_hcd 0000:00:1a.2: new USB bus registered, assigned bus number 5 +[ 0.821367] uhci_hcd 0000:00:1a.2: irq 22, io base 0x000018a0 +[ 0.821465] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.821516] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.821577] usb usb5: Product: UHCI Host Controller +[ 0.821624] usb usb5: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.821674] usb usb5: SerialNumber: 0000:00:1a.2 +[ 0.821836] hub 5-0:1.0: USB hub found +[ 0.821893] hub 5-0:1.0: 2 ports detected +[ 0.822114] uhci_hcd 0000:00:1d.0: UHCI Host Controller +[ 0.822166] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 6 +[ 0.822323] uhci_hcd 0000:00:1d.0: irq 16, io base 0x000018c0 +[ 0.822435] usb usb6: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.822486] usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.822552] usb usb6: Product: UHCI Host Controller +[ 0.822599] usb usb6: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.822649] usb usb6: SerialNumber: 0000:00:1d.0 +[ 0.822816] hub 6-0:1.0: USB hub found +[ 0.822867] hub 6-0:1.0: 2 ports detected +[ 0.823088] uhci_hcd 0000:00:1d.1: UHCI Host Controller +[ 0.823139] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 7 +[ 0.823297] uhci_hcd 0000:00:1d.1: irq 17, io base 0x000018e0 +[ 0.823398] usb usb7: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.823449] usb usb7: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.823509] usb usb7: Product: UHCI Host Controller +[ 0.823557] usb usb7: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.823607] usb usb7: SerialNumber: 0000:00:1d.1 +[ 0.823765] hub 7-0:1.0: USB hub found +[ 0.823816] hub 7-0:1.0: 2 ports detected +[ 0.824045] uhci_hcd 0000:00:1d.2: UHCI Host Controller +[ 0.824097] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 8 +[ 0.824267] uhci_hcd 0000:00:1d.2: irq 18, io base 0x00001c00 +[ 0.824365] usb usb8: New USB device found, idVendor=1d6b, idProduct=0001 +[ 0.824415] usb usb8: New USB device strings: Mfr=3, Product=2, SerialNumber=1 +[ 0.824476] usb usb8: Product: UHCI Host Controller +[ 0.824524] usb usb8: Manufacturer: Linux 3.13.0-39-lowlatency uhci_hcd +[ 0.824573] usb usb8: SerialNumber: 0000:00:1d.2 +[ 0.824732] hub 8-0:1.0: USB hub found +[ 0.824784] hub 8-0:1.0: 2 ports detected +[ 0.824974] i8042: PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12 +[ 0.835273] serio: i8042 KBD port at 0x60,0x64 irq 1 +[ 0.835347] serio: i8042 AUX port at 0x60,0x64 irq 12 +[ 0.835524] mousedev: PS/2 mouse device common for all mice +[ 0.835806] rtc_cmos 00:06: RTC can wake from S4 +[ 0.835996] rtc_cmos 00:06: rtc core: registered rtc_cmos as rtc0 +[ 0.836163] rtc_cmos 00:06: alarms up to one month, y3k, 114 bytes nvram, hpet irqs +[ 0.836291] device-mapper: uevent: version 1.0.3 +[ 0.836409] device-mapper: ioctl: 4.27.0-ioctl (2013-10-30) initialised: dm-devel@redhat.com +[ 0.836476] ledtrig-cpu: registered to indicate activity on CPUs +[ 0.836624] TCP: cubic registered +[ 0.836776] NET: Registered protocol family 10 +[ 0.837000] NET: Registered protocol family 17 +[ 0.837068] Key type dns_resolver registered +[ 0.837424] Loading compiled-in X.509 certificates +[ 0.838592] Loaded X.509 cert 'Magrathea: Glacier signing key: a7171335f18ca6131c1947ca87d46fb662317fa6' +[ 0.838684] registered taskstats version 1 +[ 0.841129] Key type trusted registered +[ 0.843261] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3 +[ 0.843344] Key type encrypted registered +[ 0.845402] AppArmor: AppArmor sha1 policy hashing enabled +[ 0.863122] tpm_tis 00:09: A TPM error (6) occurred attempting to read a pcr value +[ 0.863186] IMA: No TPM chip found, activating TPM-bypass! +[ 0.863533] regulator-dummy: disabling +[ 0.863620] Magic number: 11:688:823 +[ 0.863809] rtc_cmos 00:06: setting system clock to 2015-08-30 06:48:56 UTC (1440917336) +[ 0.866119] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found +[ 0.866172] EDD information not available. +[ 0.866304] PM: Hibernation image not present or could not be loaded. +[ 0.868348] Freeing unused kernel memory: 1324K (ffffffff81d1d000 - ffffffff81e68000) +[ 0.868413] Write protecting the kernel read-only data: 12288k +[ 0.872016] Freeing unused kernel memory: 764K (ffff880001741000 - ffff880001800000) +[ 0.875110] Freeing unused kernel memory: 676K (ffff880001b57000 - ffff880001c00000) +[ 0.894972] systemd-udevd[126]: starting version 204 +[ 0.928980] pps_core: LinuxPPS API ver. 1 registered +[ 0.930015] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti +[ 0.934247] PTP clock support registered +[ 0.940925] [drm] Initialized drm 1.1.0 20060810 +[ 0.948317] e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k +[ 0.948333] wmi: Mapper loaded +[ 0.949020] e1000e: Copyright(c) 1999 - 2013 Intel Corporation. +[ 0.949310] e1000e 0000:00:19.0: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode +[ 0.949407] e1000e 0000:00:19.0: irq 43 for MSI/MSI-X +[ 1.143351] e1000e 0000:00:19.0 eth0: (PCI Express:2.5GT/s:Width x1) 00:1f:16:0b:4d:8c +[ 1.143422] e1000e 0000:00:19.0 eth0: Intel(R) PRO/1000 Network Connection +[ 1.143503] e1000e 0000:00:19.0 eth0: MAC: 7, PHY: 8, PBA No: 1008FF-0FF +[ 1.143581] ahci 0000:00:1f.2: version 3.0 +[ 1.143759] ahci 0000:00:1f.2: irq 44 for MSI/MSI-X +[ 1.143807] ahci 0000:00:1f.2: SSS flag set, parallel bus scan disabled +[ 1.143886] ahci 0000:00:1f.2: AHCI 0001.0200 32 slots 4 ports 3 Gbps 0x3 impl SATA mode +[ 1.143952] ahci 0000:00:1f.2: flags: 64bit ncq sntf stag pm led clo pio slum part ccc sxs +[ 1.144931] scsi0 : ahci +[ 1.145135] scsi1 : ahci +[ 1.145511] scsi2 : ahci +[ 1.145741] scsi3 : ahci +[ 1.145851] ata1: SATA max UDMA/133 abar m2048@0xf2826000 port 0xf2826100 irq 44 +[ 1.145924] ata2: SATA max UDMA/133 abar m2048@0xf2826000 port 0xf2826180 irq 44 +[ 1.145987] ata3: DUMMY +[ 1.146051] ata4: DUMMY +[ 1.146776] [drm] Memory usable by graphics device = 2048M +[ 1.211100] i915 0000:00:02.0: irq 45 for MSI/MSI-X +[ 1.211112] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013). +[ 1.211164] [drm] Driver supports precise vblank timestamp query. +[ 1.211360] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem +[ 1.356901] fbcon: inteldrmfb (fb0) is primary device +[ 1.429783] psmouse serio1: alps: Unknown ALPS touchpad: E7=10 00 64, EC=10 00 64 +[ 1.451120] ata1: SATA link up 1.5 Gbps (SStatus 113 SControl 300) +[ 1.452184] ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.452187] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out +[ 1.452301] ata1.00: ACPI cmd ef/5f:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.452303] ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out +[ 1.464094] usb 4-2: new full-speed USB device number 2 using uhci_hcd +[ 1.498665] ata1.00: ATA-8: WDC WD1600BEVS-08VAT2, 14.01A14, max UDMA/133 +[ 1.498667] ata1.00: 312581808 sectors, multi 16: LBA48 NCQ (depth 31/32), AA +[ 1.500316] ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.500319] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out +[ 1.500465] ata1.00: ACPI cmd ef/5f:00:00:00:00:a0 (SET FEATURES) succeeded +[ 1.500467] ata1.00: ACPI cmd ef/10:03:00:00:00:a0 (SET FEATURES) filtered out +[ 1.502270] ata1.00: configured for UDMA/133 +[ 1.502467] scsi 0:0:0:0: Direct-Access ATA WDC WD1600BEVS-0 14.0 PQ: 0 ANSI: 5 +[ 1.502651] sd 0:0:0:0: [sda] 312581808 512-byte logical blocks: (160 GB/149 GiB) +[ 1.502695] sd 0:0:0:0: Attached scsi generic sg0 type 0 +[ 1.502732] sd 0:0:0:0: [sda] Write Protect is off +[ 1.502734] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 +[ 1.502774] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA +[ 1.537914] sda: sda1 sda2 < sda5 sda6 > +[ 1.538544] sd 0:0:0:0: [sda] Attached SCSI disk +[ 1.618541] usb 4-2: New USB device found, idVendor=0a5c, idProduct=2145 +[ 1.618544] usb 4-2: New USB device strings: Mfr=1, Product=2, SerialNumber=0 +[ 1.618546] usb 4-2: Product: ThinkPad Bluetooth with Enhanced Data Rate II +[ 1.618547] usb 4-2: Manufacturer: Lenovo Computer Corp +[ 1.796484] psmouse serio1: trackpoint: IBM TrackPoint firmware: 0x0e, buttons: 3/3 +[ 1.807121] ata2: SATA link down (SStatus 0 SControl 300) +[ 1.814662] input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/input/input5 +[ 1.894282] Console: switching to colour frame buffer device 160x50 +[ 1.901135] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device +[ 1.902865] i915 0000:00:02.0: registered panic notifier +[ 1.907397] ACPI: Video Device [VID] (multi-head: yes rom: no post: no) +[ 1.916101] acpi device:02: registered as cooling_device2 +[ 1.917970] input: Video Bus as /devices/LNXSYSTM:00/device:00/PNP0A08:00/LNXVIDEO:00/input/input6 +[ 1.919867] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0 +[ 2.603154] md: linear personality registered for level -1 +[ 2.607184] md: multipath personality registered for level -4 +[ 2.611208] md: raid0 personality registered for level 0 +[ 2.615754] md: raid1 personality registered for level 1 +[ 2.637037] raid6: sse2x1 2871 MB/s +[ 2.654032] raid6: sse2x2 3125 MB/s +[ 2.671029] raid6: sse2x4 4628 MB/s +[ 2.671057] raid6: using algorithm sse2x4 (4628 MB/s) +[ 2.671090] raid6: using ssse3x2 recovery algorithm +[ 2.673224] xor: measuring software checksum speed +[ 2.683030] prefetch64-sse: 6432.000 MB/sec +[ 2.693030] generic_sse: 5720.000 MB/sec +[ 2.693061] xor: using function: prefetch64-sse (6432.000 MB/sec) +[ 2.695037] async_tx: api initialized (async) +[ 2.706535] md: raid6 personality registered for level 6 +[ 2.706574] md: raid5 personality registered for level 5 +[ 2.706609] md: raid4 personality registered for level 4 +[ 2.715477] md: raid10 personality registered for level 10 +[ 2.777351] random: nonblocking pool is initialized +[ 2.912964] bio: create slab at 1 +[ 2.914076] Btrfs loaded +[ 3.142639] EXT4-fs (sda1): mounted filesystem with ordered data mode. Opts: (null) +[ 13.257389] Adding 4230140k swap on /dev/sda5. Priority:-1 extents:1 across:4230140k FS +[ 13.348717] IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready +[ 13.512598] systemd-udevd[410]: starting version 204 +[ 13.698475] lp: driver loaded but no devices found +[ 13.718842] ppdev: user-space parallel port driver +[ 13.888756] Bluetooth: Core ver 2.17 +[ 13.888782] NET: Registered protocol family 31 +[ 13.888785] Bluetooth: HCI device and connection manager initialized +[ 13.888797] Bluetooth: HCI socket layer initialized +[ 13.888801] Bluetooth: L2CAP socket layer initialized +[ 13.888807] Bluetooth: SCO socket layer initialized +[ 13.902331] usbcore: registered new interface driver btusb +[ 13.909756] ACPI Warning: 0x0000000000001028-0x000000000000102f SystemIO conflicts with Region \_SB_.PCI0.LPC_.PMIO 1 (20131115/utaddress-251) +[ 13.909766] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 13.909772] ACPI Warning: 0x00000000000011b0-0x00000000000011bf SystemIO conflicts with Region \_SB_.PCI0.LPC_.LPIO 1 (20131115/utaddress-251) +[ 13.909777] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 13.909779] ACPI Warning: 0x0000000000001180-0x00000000000011af SystemIO conflicts with Region \_SB_.PCI0.LPC_.LPIO 1 (20131115/utaddress-251) +[ 13.909783] ACPI: If an ACPI driver is available for this device, you should use it instead of the native driver +[ 13.909785] lpc_ich: Resource conflict(s) found affecting gpio_ich +[ 13.924585] EXT4-fs (sda1): re-mounted. Opts: errors=remount-ro +[ 13.962851] Non-volatile memory driver v1.3 +[ 14.000898] thinkpad_acpi: ThinkPad ACPI Extras v0.25 +[ 14.000903] thinkpad_acpi: http://ibm-acpi.sf.net/ +[ 14.000905] thinkpad_acpi: ThinkPad BIOS 6DET65WW (3.15 ), EC 7XHT24WW-1.06 +[ 14.000907] thinkpad_acpi: Lenovo ThinkPad X200, model 7459GW4 +[ 14.023348] thinkpad_acpi: detected a 16-level brightness capable ThinkPad +[ 14.023562] thinkpad_acpi: radio switch found; radios are enabled +[ 14.023579] thinkpad_acpi: This ThinkPad has standard ACPI backlight brightness control, supported by the ACPI video driver +[ 14.023581] thinkpad_acpi: Disabling thinkpad-acpi brightness events by default... +[ 14.027716] thinkpad_acpi: rfkill switch tpacpi_bluetooth_sw: radio is unblocked +[ 14.033143] thinkpad_acpi: Standard ACPI backlight interface available, not loading native one +[ 14.033423] thinkpad_acpi: Console audio control enabled, mode: monitor (read only) +[ 14.037967] input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input7 +[ 14.094334] snd_hda_intel 0000:00:1b.0: irq 46 for MSI/MSI-X +[ 14.117123] hda_codec: CX20561 (Hermosa): BIOS auto-probing. +[ 14.117573] autoconfig: line_outs=1 (0x1a/0x0/0x0/0x0/0x0) type:speaker +[ 14.117576] speaker_outs=0 (0x0/0x0/0x0/0x0/0x0) +[ 14.117578] hp_outs=2 (0x19/0x16/0x0/0x0/0x0) +[ 14.117580] mono: mono_out=0x0 +[ 14.117582] dig-out=0x1c/0x0 +[ 14.117583] inputs: +[ 14.117585] Mic=0x18 +[ 14.117587] Internal Mic=0x1d +[ 14.117589] Dock Mic=0x17 +[ 14.118587] hda_codec: Enable sync_write for stable communication +[ 14.121304] input: HDA Intel Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input11 +[ 14.121403] input: HDA Intel Dock Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card0/input10 +[ 14.121491] input: HDA Intel Dock Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input9 +[ 14.121572] input: HDA Intel Mic as /devices/pci0000:00/0000:00:1b.0/sound/card0/input8 +[ 14.141178] device-mapper: multipath: version 1.6.0 loaded +[ 14.154949] kvm: disabled by bios +[ 14.165173] kvm: disabled by bios +[ 14.310307] mei_me 0000:00:03.0: irq 47 for MSI/MSI-X +[ 14.401058] cfg80211: Calling CRDA to update world regulatory domain +[ 14.440429] Intel(R) Wireless WiFi driver for Linux, in-tree: +[ 14.440433] Copyright(c) 2003-2013 Intel Corporation +[ 14.440762] iwlwifi 0000:03:00.0: can't disable ASPM; OS doesn't have ASPM control +[ 14.440834] iwlwifi 0000:03:00.0: irq 48 for MSI/MSI-X +[ 14.441053] 0000:03:00.0: Missing Free firmware +[ 14.441095] iwlwifi 0000:03:00.0: Couldn't request the fw +[ 14.442753] iwlwifi: probe of 0000:03:00.0 failed with error -22 +[ 14.514047] pci 0000:03:00.0: Direct firmware load failed with error -2 +[ 14.514052] pci 0000:03:00.0: Falling back to user helper +[ 14.519440] type=1400 audit(1440917350.154:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/sbin/dhclient" pid=569 comm="apparmor_parser" +[ 14.519450] type=1400 audit(1440917350.154:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=569 comm="apparmor_parser" +[ 14.519457] type=1400 audit(1440917350.154:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=569 comm="apparmor_parser" +[ 14.520174] systemd-udevd[425]: renamed network interface eth0 to eth4 +[ 14.520232] type=1400 audit(1440917350.155:5): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=569 comm="apparmor_parser" +[ 14.520241] type=1400 audit(1440917350.155:6): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=569 comm="apparmor_parser" +[ 14.520582] type=1400 audit(1440917350.155:7): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=569 comm="apparmor_parser" +[ 15.055767] SGI XFS with ACLs, security attributes, realtime, large block/inode numbers, no debug enabled +[ 15.119824] XFS (sda6): Mounting Filesystem +[ 15.569603] XFS (sda6): Ending clean mount +[ 15.844338] init: failsafe main process (725) killed by TERM signal +[ 16.170233] type=1400 audit(1440917351.805:8): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/sbin/dhclient" pid=831 comm="apparmor_parser" +[ 16.170245] type=1400 audit(1440917351.805:9): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=831 comm="apparmor_parser" +[ 16.170252] type=1400 audit(1440917351.805:10): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/connman/scripts/dhclient-script" pid=831 comm="apparmor_parser" +[ 16.170906] type=1400 audit(1440917351.805:11): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/NetworkManager/nm-dhcp-client.action" pid=831 comm="apparmor_parser" +[ 16.548278] Bluetooth: RFCOMM TTY layer initialized +[ 16.548295] Bluetooth: RFCOMM socket layer initialized +[ 16.548303] Bluetooth: RFCOMM ver 1.11 +[ 16.702630] init: cups main process (887) killed by HUP signal +[ 16.702645] init: cups main process ended, respawning +[ 16.717535] Bluetooth: BNEP (Ethernet Emulation) ver 1.3 +[ 16.717540] Bluetooth: BNEP filters: protocol multicast +[ 16.717552] Bluetooth: BNEP socket layer initialized +[ 18.798586] init: plymouth-upstart-bridge main process ended, respawning +[ 19.246364] e1000e 0000:00:19.0: irq 43 for MSI/MSI-X +[ 19.347188] e1000e 0000:00:19.0: irq 43 for MSI/MSI-X +[ 19.347386] IPv6: ADDRCONF(NETDEV_UP): eth4: link is not ready +[ 19.347784] IPv6: ADDRCONF(NETDEV_UP): eth4: link is not ready +[ 22.755913] e1000e: eth4 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: Rx/Tx +[ 22.756058] IPv6: ADDRCONF(NETDEV_CHANGE): eth4: link becomes ready +[ 46.558282] audit_printk_skb: 96 callbacks suppressed +[ 46.558287] type=1400 audit(1440913378.392:44): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/lib/cups/backend/cups-pdf" pid=2159 comm="apparmor_parser" +[ 46.558298] type=1400 audit(1440913378.392:45): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/sbin/cupsd" pid=2159 comm="apparmor_parser" +[ 46.558959] type=1400 audit(1440913378.392:46): apparmor="STATUS" operation="profile_replace" profile="unconfined" name="/usr/sbin/cupsd" pid=2159 comm="apparmor_parser" diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/dmidecode.err.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/dmidecode.err.log new file mode 100644 index 00000000..e69de29b diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/dmidecode.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/dmidecode.log new file mode 100644 index 00000000..a5a19616 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/dmidecode.log @@ -0,0 +1,587 @@ +# dmidecode 2.12 +SMBIOS 2.4 present. +68 structures occupying 2464 bytes. +Table at 0x000E0010. + +Handle 0x0000, DMI type 0, 24 bytes +BIOS Information + Vendor: LENOVO + Version: 6DET65WW (3.15 ) + Release Date: 08/24/2010 + Address: 0xE0000 + Runtime Size: 128 kB + ROM Size: 8192 kB + Characteristics: + PCI is supported + PC Card (PCMCIA) is supported + PNP is supported + BIOS is upgradeable + BIOS shadowing is allowed + ESCD support is available + Boot from CD is supported + Selectable boot is supported + BIOS ROM is socketed + EDD is supported + ACPI is supported + USB legacy is supported + BIOS boot specification is supported + Targeted content distribution is supported + BIOS Revision: 3.21 + Firmware Revision: 1.6 + +Handle 0x0001, DMI type 1, 27 bytes +System Information + Manufacturer: LENOVO + Product Name: 7459GW4 + Version: ThinkPad X200 + Serial Number: L3AAR0B + UUID: 93861E01-4A15-11CB-8F2C-D4BC407E0839 + Wake-up Type: Power Switch + SKU Number: Not Specified + Family: ThinkPad X200 + +Handle 0x0002, DMI type 2, 8 bytes +Base Board Information + Manufacturer: LENOVO + Product Name: 7459GW4 + Version: Not Available + Serial Number: 1ZFDS89N4DD + +Handle 0x0003, DMI type 3, 13 bytes +Chassis Information + Manufacturer: LENOVO + Type: Notebook + Lock: Not Present + Version: Not Available + Serial Number: Not Available + Asset Tag: 1S7459GW4L3AAR0B + Boot-up State: Unknown + Power Supply State: Unknown + Thermal State: Unknown + Security Status: Unknown + +Handle 0x0004, DMI type 126, 13 bytes +Inactive + +Handle 0x0005, DMI type 126, 13 bytes +Inactive + +Handle 0x0006, DMI type 4, 35 bytes +Processor Information + Socket Designation: None + Type: Central Processor + Family: Other + Manufacturer: GenuineIntel + ID: 76 06 01 00 FF FB EB BF + Signature: Type 0, Family 6, Model 23, Stepping 6 + Flags: + FPU (Floating-point unit on-chip) + VME (Virtual mode extension) + DE (Debugging extension) + PSE (Page size extension) + TSC (Time stamp counter) + MSR (Model specific registers) + PAE (Physical address extension) + MCE (Machine check exception) + CX8 (CMPXCHG8 instruction supported) + APIC (On-chip APIC hardware supported) + SEP (Fast system call) + MTRR (Memory type range registers) + PGE (Page global enable) + MCA (Machine check architecture) + CMOV (Conditional move instruction supported) + PAT (Page attribute table) + PSE-36 (36-bit page size extension) + CLFSH (CLFLUSH instruction supported) + DS (Debug store) + ACPI (ACPI supported) + MMX (MMX technology supported) + FXSR (FXSAVE and FXSTOR instructions supported) + SSE (Streaming SIMD extensions) + SSE2 (Streaming SIMD extensions 2) + SS (Self-snoop) + HTT (Multi-threading) + TM (Thermal monitor supported) + PBE (Pending break enabled) + Version: Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz + Voltage: 1.2 V + External Clock: 266 MHz + Max Speed: 2400 MHz + Current Speed: 2400 MHz + Status: Populated, Enabled + Upgrade: None + L1 Cache Handle: 0x000A + L2 Cache Handle: 0x000C + L3 Cache Handle: Not Provided + Serial Number: Not Specified + Asset Tag: Not Specified + Part Number: Not Specified + +Handle 0x0007, DMI type 5, 20 bytes +Memory Controller Information + Error Detecting Method: None + Error Correcting Capabilities: + None + Supported Interleave: One-way Interleave + Current Interleave: One-way Interleave + Maximum Memory Module Size: 4096 MB + Maximum Total Memory Size: 8192 MB + Supported Speeds: + Other + Supported Memory Types: + DIMM + SDRAM + Memory Module Voltage: 2.9 V + Associated Memory Slots: 2 + 0x0008 + 0x0009 + Enabled Error Correcting Capabilities: + Unknown + +Handle 0x0008, DMI type 6, 12 bytes +Memory Module Information + Socket Designation: DIMM Slot 1 + Bank Connections: 0 1 + Current Speed: 42 ns + Type: DIMM SDRAM + Installed Size: 2048 MB (Double-bank Connection) + Enabled Size: 2048 MB (Double-bank Connection) + Error Status: OK + +Handle 0x0009, DMI type 6, 12 bytes +Memory Module Information + Socket Designation: DIMM Slot 2 + Bank Connections: 2 3 + Current Speed: 42 ns + Type: DIMM SDRAM + Installed Size: Not Installed + Enabled Size: Not Installed + Error Status: OK + +Handle 0x000A, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L1 Cache + Configuration: Enabled, Socketed, Level 1 + Operational Mode: Write Back + Location: Internal + Installed Size: 64 kB + Maximum Size: 64 kB + Supported SRAM Types: + Synchronous + Installed SRAM Type: Synchronous + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Instruction + Associativity: 8-way Set-associative + +Handle 0x000B, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L1 Cache + Configuration: Enabled, Socketed, Level 1 + Operational Mode: Write Back + Location: Internal + Installed Size: 64 kB + Maximum Size: 64 kB + Supported SRAM Types: + Synchronous + Installed SRAM Type: Synchronous + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Data + Associativity: 8-way Set-associative + +Handle 0x000C, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L2 Cache + Configuration: Enabled, Socketed, Level 2 + Operational Mode: Write Back + Location: Internal + Installed Size: 3072 kB + Maximum Size: 3072 kB + Supported SRAM Types: + Burst + Installed SRAM Type: Burst + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Unified + Associativity: 8-way Set-associative + +Handle 0x000D, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: External Monitor + External Connector Type: DB-15 female + Port Type: Video Port + +Handle 0x000E, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Microphone Jack + External Connector Type: Mini Jack (headphones) + Port Type: Audio Port + +Handle 0x000F, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Headphone Jack + External Connector Type: Mini Jack (headphones) + Port Type: Audio Port + +Handle 0x0010, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Modem + External Connector Type: RJ-11 + Port Type: Modem Port + +Handle 0x0011, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Ethernet + External Connector Type: RJ-45 + Port Type: Network Port + +Handle 0x0012, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 1 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0013, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 2 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0014, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 3 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0015, DMI type 126, 9 bytes +Inactive + +Handle 0x0016, DMI type 126, 9 bytes +Inactive + +Handle 0x0017, DMI type 126, 9 bytes +Inactive + +Handle 0x0018, DMI type 126, 9 bytes +Inactive + +Handle 0x0019, DMI type 126, 9 bytes +Inactive + +Handle 0x001A, DMI type 126, 9 bytes +Inactive + +Handle 0x001B, DMI type 126, 13 bytes +Inactive + +Handle 0x001C, DMI type 10, 6 bytes +On Board Device Information + Type: Other + Status: Disabled + Description: IBM Embedded Security hardware + +Handle 0x001D, DMI type 11, 5 bytes +OEM Strings + String 1: IBM ThinkPad Embedded Controller -[7XHT24WW-1.06 ]- + +Handle 0x001E, DMI type 13, 22 bytes +BIOS Language Information + Language Description Format: Abbreviated + Installable Languages: 1 + enUS + Currently Installed Language: enUS + +Handle 0x001F, DMI type 15, 25 bytes +System Event Log + Area Length: 0 bytes + Header Start Offset: 0x0000 + Header Length: 16 bytes + Data Start Offset: 0x0010 + Access Method: General-purpose non-volatile data functions + Access Address: 0x0000 + Status: Valid, Not Full + Change Token: 0x000000FC + Header Format: Type 1 + Supported Log Type Descriptors: 1 + Descriptor 1: POST error + Data Format 1: POST results bitmap + +Handle 0x0020, DMI type 16, 15 bytes +Physical Memory Array + Location: System Board Or Motherboard + Use: System Memory + Error Correction Type: None + Maximum Capacity: 4 GB + Error Information Handle: Not Provided + Number Of Devices: 2 + +Handle 0x0021, DMI type 17, 27 bytes +Memory Device + Array Handle: 0x0020 + Error Information Handle: No Error + Total Width: 64 bits + Data Width: 64 bits + Size: 2048 MB + Form Factor: SODIMM + Set: None + Locator: DIMM 1 + Bank Locator: Bank 0/1 + Type: DDR3 + Type Detail: Synchronous + Speed: 1066 MHz + Manufacturer: 02FE + Serial Number: F4BB7CA2 + Asset Tag: 0839 + Part Number: EBJ21UE8BASA-AE-E + +Handle 0x0022, DMI type 17, 27 bytes +Memory Device + Array Handle: 0x0020 + Error Information Handle: No Error + Total Width: Unknown + Data Width: Unknown + Size: No Module Installed + Form Factor: SODIMM + Set: None + Locator: DIMM 2 + Bank Locator: Bank 2/3 + Type: DDR2 + Type Detail: Synchronous + Speed: 1066 MHz + Manufacturer: + Serial Number: + Asset Tag: + Part Number: + +Handle 0x0023, DMI type 18, 23 bytes +32-bit Memory Error Information + Type: OK + Granularity: Unknown + Operation: Unknown + Vendor Syndrome: Unknown + Memory Array Address: Unknown + Device Address: Unknown + Resolution: Unknown + +Handle 0x0024, DMI type 19, 15 bytes +Memory Array Mapped Address + Starting Address: 0x00000000000 + Ending Address: 0x0007FFFFFFF + Range Size: 2 GB + Physical Array Handle: 0x0020 + Partition Width: 2 + +Handle 0x0025, DMI type 20, 19 bytes +Memory Device Mapped Address + Starting Address: 0x00000000000 + Ending Address: 0x0007FFFFFFF + Range Size: 2 GB + Physical Device Handle: 0x0021 + Memory Array Mapped Address Handle: 0x0024 + Partition Row Position: 1 + +Handle 0x0026, DMI type 20, 19 bytes +Memory Device Mapped Address + Starting Address: 0x0007FFFFC00 + Ending Address: 0x0007FFFFFFF + Range Size: 1 kB + Physical Device Handle: 0x0022 + Memory Array Mapped Address Handle: 0x0024 + Partition Row Position: 1 + +Handle 0x0027, DMI type 21, 7 bytes +Built-in Pointing Device + Type: Track Point + Interface: PS/2 + Buttons: 3 + +Handle 0x0028, DMI type 126, 26 bytes +Inactive + +Handle 0x0029, DMI type 126, 26 bytes +Inactive + +Handle 0x002A, DMI type 24, 5 bytes +Hardware Security + Power-On Password Status: Disabled + Keyboard Password Status: Disabled + Administrator Password Status: Disabled + Front Panel Reset Status: Unknown + +Handle 0x002B, DMI type 32, 11 bytes +System Boot Information + Status: No errors detected + +Handle 0x002C, DMI type 131, 17 bytes +OEM-specific Type + Header and Data: + 83 11 2C 00 01 02 03 FF FF 1F 00 00 00 00 00 02 + 00 + Strings: + BOOTINF 20h + BOOTDEV 21h + KEYPTRS 23h + +Handle 0x002D, DMI type 131, 22 bytes +OEM-specific Type + Header and Data: + 83 16 2D 00 01 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 01 + Strings: + TVT-Enablement + +Handle 0x002E, DMI type 132, 7 bytes +OEM-specific Type + Header and Data: + 84 07 2E 00 02 D8 36 + +Handle 0x002F, DMI type 133, 5 bytes +OEM-specific Type + Header and Data: + 85 05 2F 00 01 + Strings: + KHOIHGIUCCHHII + +Handle 0x0030, DMI type 134, 13 bytes +OEM-specific Type + Header and Data: + 86 0D 30 00 30 10 08 20 00 00 00 00 00 + +Handle 0x0031, DMI type 134, 16 bytes +OEM-specific Type + Header and Data: + 86 10 31 00 00 49 4E 54 43 01 01 00 00 02 01 02 + Strings: + TPM INFO + System Reserved + +Handle 0x0032, DMI type 135, 13 bytes +OEM-specific Type + Header and Data: + 87 0D 32 00 54 50 07 00 01 00 00 00 00 + +Handle 0x0033, DMI type 135, 18 bytes +OEM-specific Type + Header and Data: + 87 12 33 00 54 50 07 01 01 B9 05 00 00 00 00 00 + 00 00 + +Handle 0x0034, DMI type 135, 35 bytes +OEM-specific Type + Header and Data: + 87 23 34 00 54 50 07 02 42 41 59 20 49 2F 4F 20 + 01 00 02 00 00 0B 00 48 1C 3E 18 02 00 0B 00 40 + 1C 3A 18 + +Handle 0x0035, DMI type 135, 34 bytes +OEM-specific Type + Header and Data: + 87 22 35 00 54 50 07 04 01 06 01 01 02 00 02 01 + 02 00 03 01 02 00 04 01 02 00 05 01 02 00 06 01 + 02 00 + +Handle 0x0036, DMI type 135, 10 bytes +OEM-specific Type + Header and Data: + 87 0A 36 00 54 50 07 03 01 0A + +Handle 0x0037, DMI type 136, 6 bytes +OEM-specific Type + Header and Data: + 88 06 37 00 5A 5A + +Handle 0x0038, DMI type 126, 28 bytes +Inactive + +Handle 0x0039, DMI type 138, 40 bytes +OEM-specific Type + Header and Data: + 8A 28 39 00 14 01 02 01 40 02 01 40 02 01 40 02 + 01 40 01 40 42 49 4F 53 20 50 61 73 73 77 6F 72 + 64 20 46 6F 72 6D 61 74 + +Handle 0x003A, DMI type 139, 37 bytes +OEM-specific Type + Header and Data: + 8B 25 3A 00 11 01 0A 00 00 00 00 00 00 00 00 00 + 00 50 57 4D 53 20 4B 65 79 20 49 6E 66 6F 72 6D + 61 74 69 6F 6E + +Handle 0x003B, DMI type 140, 67 bytes +OEM-specific Type + Header and Data: + 8C 43 3B 00 4C 45 4E 4F 56 4F 0B 00 01 9A 13 CD + C4 7A 2A 8E 76 C3 C4 4E B9 B1 DD 4E 7C 01 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 + +Handle 0x003C, DMI type 140, 47 bytes +OEM-specific Type + Header and Data: + 8C 2F 3C 00 4C 45 4E 4F 56 4F 0B 01 01 08 00 BF + DA 3C 04 5C 72 D9 7D 0D 79 DE 46 98 23 10 B1 00 + 00 00 00 10 00 10 00 10 01 D0 00 20 01 00 01 + +Handle 0x003D, DMI type 140, 63 bytes +OEM-specific Type + Header and Data: + 8C 3F 3D 00 4C 45 4E 4F 56 4F 0B 02 01 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +Handle 0x003E, DMI type 140, 17 bytes +OEM-specific Type + Header and Data: + 8C 11 3E 00 4C 45 4E 4F 56 4F 0B 03 01 00 00 00 + 00 + +Handle 0x003F, DMI type 140, 19 bytes +OEM-specific Type + Header and Data: + 8C 13 3F 00 4C 45 4E 4F 56 4F 0B 04 01 B2 00 53 + 4D 20 00 + +Handle 0x0040, DMI type 129, 8 bytes +OEM-specific Type + Header and Data: + 81 08 40 00 01 01 02 01 + Strings: + Intel_ASF + Intel_ASF_001 + +Handle 0x0041, DMI type 130, 20 bytes +OEM-specific Type + Header and Data: + 82 14 41 00 24 41 4D 54 01 01 01 01 01 A5 0B 04 + 00 00 00 00 + +Handle 0x0042, DMI type 131, 64 bytes +OEM-specific Type + Header and Data: + 83 40 42 00 14 00 00 00 00 00 40 2A 00 00 00 00 + F8 00 17 29 00 00 00 00 2D 00 00 00 00 00 04 00 + 64 04 03 00 01 00 01 15 C8 00 F5 10 00 00 00 00 + 00 00 00 00 07 00 00 00 76 50 72 6F 00 00 00 00 + +Handle 0x0043, DMI type 127, 4 bytes +End Of Table + diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/ectool.err.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/ectool.err.log new file mode 100644 index 00000000..452503e5 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/ectool.err.log @@ -0,0 +1 @@ +bash: ectool: command not found diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/ectool.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/ectool.log new file mode 100644 index 00000000..e69de29b diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/flashrom_info.err.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/flashrom_info.err.log new file mode 100644 index 00000000..933ac573 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/flashrom_info.err.log @@ -0,0 +1,14 @@ +======================================================================== +WARNING! You seem to be running flashrom on an unsupported laptop. +Laptops, notebooks and netbooks are difficult to support and we +recommend to use the vendor flashing utility. The embedded controller +(EC) in these machines often interacts badly with flashing. +See http://www.flashrom.org/Laptops for details. + +If flash is shared with the EC, erase is guaranteed to brick your laptop +and write may brick your laptop. +Read and probe may irritate your EC and cause fan failure, backlight +failure and sudden poweroff. +You have been warned. +======================================================================== +Proceeding anyway because user forced us to. diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/flashrom_info.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/flashrom_info.log new file mode 100644 index 00000000..d9a82f8b --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/flashrom_info.log @@ -0,0 +1,289 @@ +flashrom v0.9.6.1-r1563 on Linux 3.13.0-39-lowlatency (x86_64) +flashrom is free software, get the source code at http://www.flashrom.org + +flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian +Command line (3 args): flashrom -V -p internal:laptop=force_I_want_a_brick +Calibrating delay loop... OS timer resolution is 1 usecs, 1578M loops per second, 10 myus = 11 us, 100 myus = 114 us, 1000 myus = 1002 us, 10000 myus = 10004 us, 4 myus = 5 us, OK. +Initializing internal programmer +No coreboot table found. +DMI string system-manufacturer: "LENOVO" +DMI string system-product-name: "7459GW4" +DMI string system-version: "ThinkPad X200" +DMI string baseboard-manufacturer: "LENOVO" +DMI string baseboard-product-name: "7459GW4" +DMI string baseboard-version: "Not Available" +DMI string chassis-type: "Notebook" +Laptop detected via DMI. +Found chipset "Intel ICH9M-E" with PCI ID 8086:2917. Enabling flash write... +0xfff80000/0xffb80000 FWH IDSEL: 0x0 +0xfff00000/0xffb00000 FWH IDSEL: 0x0 +0xffe80000/0xffa80000 FWH IDSEL: 0x0 +0xffe00000/0xffa00000 FWH IDSEL: 0x0 +0xffd80000/0xff980000 FWH IDSEL: 0x0 +0xffd00000/0xff900000 FWH IDSEL: 0x0 +0xffc80000/0xff880000 FWH IDSEL: 0x0 +0xffc00000/0xff800000 FWH IDSEL: 0x0 +0xff700000/0xff300000 FWH IDSEL: 0x4 +0xff600000/0xff200000 FWH IDSEL: 0x5 +0xff500000/0xff100000 FWH IDSEL: 0x6 +0xff400000/0xff000000 FWH IDSEL: 0x7 +0xfff80000/0xffb80000 FWH decode enabled +0xfff00000/0xffb00000 FWH decode enabled +0xffe80000/0xffa80000 FWH decode enabled +0xffe00000/0xffa00000 FWH decode enabled +0xffd80000/0xff980000 FWH decode enabled +0xffd00000/0xff900000 FWH decode enabled +0xffc80000/0xff880000 FWH decode enabled +0xffc00000/0xff800000 FWH decode enabled +0xff700000/0xff300000 FWH decode disabled +0xff600000/0xff200000 FWH decode disabled +0xff500000/0xff100000 FWH decode disabled +0xff400000/0xff000000 FWH decode disabled +Maximum FWH chip size: 0x400000 bytes +BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 +Root Complex Register Block address = 0xfed1c000 +GCS = 0x7b0461: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x1 (SPI) +Top Swap : not enabled +SPIBAR = 0xfed1c000 + 0x3800 +0x04: 0xe008 (HSFS) +HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 +WARNING: SPI Configuration Lockdown activated. +Reading OPCODES... done +0x06: 0x3f04 (HSFC) +HSFC: FGO=0, FCYCLE=2, FDBC=63, SME=0 +0x08: 0x00001000 (FADDR) +0x50: 0x00001a1b (FRAP) +BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b +0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. +0x58: 0x07ff0600 FREG1: BIOS region (0x00600000-0x007fffff) is read-write. +0x5C: 0x05f50001 FREG2: WARNING: Management Engine region (0x00001000-0x005f5fff) is locked. +0x60: 0x05f705f6 FREG3: Gigabit Ethernet region (0x005f6000-0x005f7fff) is read-write. +0x64: 0x05ff05f8 FREG4: Platform Data region (0x005f8000-0x005fffff) is read-write. +0x74: 0x9fff07e0 PR0: WARNING: 0x007e0000-0x01ffffff is read-only. +0x84: 0x85ff85f8 PR4: WARNING: 0x005f8000-0x005fffff is locked. +Please send a verbose log to flashrom@flashrom.org if this board is not listed on +http://flashrom.org/Supported_hardware#Supported_mainboards yet. +Writes have been disabled. You can enforce write support with the +ich_spi_force programmer option, but it will most likely harm your hardware! +If you force flashrom you will get no support if something breaks. +0x90: 0x04 (SSFS) +SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 +0x91: 0x000000 (SSFC) +SSFC: SCGO=0, ACS=0, SPOP=0, COP=0, DBC=0, SME=0, SCF=0 +0x94: 0x5006 (PREOP) +0x96: 0x143b (OPTYPE) +0x98: 0x05200302 (OPMENU) +0x9C: 0x0601209f (OPMENU+4) +0xA0: 0x00000000 (BBAR) +0xC4: 0x00002005 (LVSCC) +LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 +0xC8: 0x00002005 (UVSCC) +UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 +0xD0: 0x00000000 (FPB) + +SPI Read Configuration: prefetching disabled, caching enabled, OK. +The following protocols are supported: FWH, SPI. +Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Chip status register is 00 +Chip status register: Status Register Write Disable (SRWD) is not set +Chip status register: Bit 6 is not set +Chip status register: Block Protect 3 (BP3) is not set +Chip status register: Block Protect 2 (BP2) is not set +Chip status register: Block Protect 1 (BP1) is not set +Chip status register: Block Protect 0 (BP0) is not set +Chip status register: Write Enable Latch (WEL) is not set +Chip status register: Write In Progress (WIP/BUSY) is not set +Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000. +Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. +Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. +Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not execute. +Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. +Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. +Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. +Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. +Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. +Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. +Receiving SFDP signature failed. +Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. +Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x0a, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Found Macronix flash chip "MX25L6405" (8192 kB, SPI). +No operations were specified. +Restoring MMIO space at 0x7f9c951da8a0 +Restoring PCI config space for 00:1f:0 reg 0xdc diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/flashrom_read.err.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/flashrom_read.err.log new file mode 100644 index 00000000..0a7925d7 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/flashrom_read.err.log @@ -0,0 +1,16 @@ +======================================================================== +WARNING! You seem to be running flashrom on an unsupported laptop. +Laptops, notebooks and netbooks are difficult to support and we +recommend to use the vendor flashing utility. The embedded controller +(EC) in these machines often interacts badly with flashing. +See http://www.flashrom.org/Laptops for details. + +If flash is shared with the EC, erase is guaranteed to brick your laptop +and write may brick your laptop. +Read and probe may irritate your EC and cause fan failure, backlight +failure and sudden poweroff. +You have been warned. +======================================================================== +Proceeding anyway because user forced us to. +Transaction error! +Read operation failed! diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/flashrom_read.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/flashrom_read.log new file mode 100644 index 00000000..0c78c81c --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/flashrom_read.log @@ -0,0 +1,292 @@ +flashrom v0.9.6.1-r1563 on Linux 3.13.0-39-lowlatency (x86_64) +flashrom is free software, get the source code at http://www.flashrom.org + +flashrom was built with libpci 3.1.9, GCC 4.7.1, little endian +Command line (5 args): flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin +Calibrating delay loop... OS timer resolution is 2 usecs, 1579M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1004 us, 10000 myus = 10014 us, 8 myus = 9 us, OK. +Initializing internal programmer +No coreboot table found. +DMI string system-manufacturer: "LENOVO" +DMI string system-product-name: "7459GW4" +DMI string system-version: "ThinkPad X200" +DMI string baseboard-manufacturer: "LENOVO" +DMI string baseboard-product-name: "7459GW4" +DMI string baseboard-version: "Not Available" +DMI string chassis-type: "Notebook" +Laptop detected via DMI. +Found chipset "Intel ICH9M-E" with PCI ID 8086:2917. Enabling flash write... +0xfff80000/0xffb80000 FWH IDSEL: 0x0 +0xfff00000/0xffb00000 FWH IDSEL: 0x0 +0xffe80000/0xffa80000 FWH IDSEL: 0x0 +0xffe00000/0xffa00000 FWH IDSEL: 0x0 +0xffd80000/0xff980000 FWH IDSEL: 0x0 +0xffd00000/0xff900000 FWH IDSEL: 0x0 +0xffc80000/0xff880000 FWH IDSEL: 0x0 +0xffc00000/0xff800000 FWH IDSEL: 0x0 +0xff700000/0xff300000 FWH IDSEL: 0x4 +0xff600000/0xff200000 FWH IDSEL: 0x5 +0xff500000/0xff100000 FWH IDSEL: 0x6 +0xff400000/0xff000000 FWH IDSEL: 0x7 +0xfff80000/0xffb80000 FWH decode enabled +0xfff00000/0xffb00000 FWH decode enabled +0xffe80000/0xffa80000 FWH decode enabled +0xffe00000/0xffa00000 FWH decode enabled +0xffd80000/0xff980000 FWH decode enabled +0xffd00000/0xff900000 FWH decode enabled +0xffc80000/0xff880000 FWH decode enabled +0xffc00000/0xff800000 FWH decode enabled +0xff700000/0xff300000 FWH decode disabled +0xff600000/0xff200000 FWH decode disabled +0xff500000/0xff100000 FWH decode disabled +0xff400000/0xff000000 FWH decode disabled +Maximum FWH chip size: 0x400000 bytes +BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 +Root Complex Register Block address = 0xfed1c000 +GCS = 0x7b0461: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x1 (SPI) +Top Swap : not enabled +SPIBAR = 0xfed1c000 + 0x3800 +0x04: 0xe008 (HSFS) +HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1 +WARNING: SPI Configuration Lockdown activated. +Reading OPCODES... done +0x06: 0x3f04 (HSFC) +HSFC: FGO=0, FCYCLE=2, FDBC=63, SME=0 +0x08: 0x00000000 (FADDR) +0x50: 0x00001a1b (FRAP) +BMWAG 0x00, BMRAG 0x00, BRWA 0x1a, BRRA 0x1b +0x54: 0x00000000 FREG0: WARNING: Flash Descriptor region (0x00000000-0x00000fff) is read-only. +0x58: 0x07ff0600 FREG1: BIOS region (0x00600000-0x007fffff) is read-write. +0x5C: 0x05f50001 FREG2: WARNING: Management Engine region (0x00001000-0x005f5fff) is locked. +0x60: 0x05f705f6 FREG3: Gigabit Ethernet region (0x005f6000-0x005f7fff) is read-write. +0x64: 0x05ff05f8 FREG4: Platform Data region (0x005f8000-0x005fffff) is read-write. +0x74: 0x9fff07e0 PR0: WARNING: 0x007e0000-0x01ffffff is read-only. +0x84: 0x85ff85f8 PR4: WARNING: 0x005f8000-0x005fffff is locked. +Please send a verbose log to flashrom@flashrom.org if this board is not listed on +http://flashrom.org/Supported_hardware#Supported_mainboards yet. +Writes have been disabled. You can enforce write support with the +ich_spi_force programmer option, but it will most likely harm your hardware! +If you force flashrom you will get no support if something breaks. +0x90: 0x04 (SSFS) +SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0 +0x91: 0x004240 (SSFC) +SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=2, SME=0, SCF=0 +0x94: 0x5006 (PREOP) +0x96: 0x143b (OPTYPE) +0x98: 0x05200302 (OPMENU) +0x9C: 0x0601209f (OPMENU+4) +0xA0: 0x00000000 (BBAR) +0xC4: 0x00002005 (LVSCC) +LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 +0xC8: 0x00002005 (UVSCC) +UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=0 +0xD0: 0x00000000 (FPB) + +SPI Read Configuration: prefetching disabled, caching enabled, OK. +The following protocols are supported: FWH, SPI. +Probing for AMIC A25L05PT, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L05PU, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L10PT, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L10PU, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L20PT, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L20PU, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L40PT, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L40PU, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L80P, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L16PT, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L16PU, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L080, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L016, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25L032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for AMIC A25LQ032, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF021, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF041A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF081, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF321, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF321A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DF641(A), 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25DQ161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25F512B, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25FS010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT25FS040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF041, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF081A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF161, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26DF161A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT26F004, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45CS1282, 16896 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB011D, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB021D, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB041D, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB081D, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB161D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB321C, 4224 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB321D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel AT45DB642D, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for EMST F25L008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B05T, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B10T, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B20T, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B40T, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B80T, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B16T, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B32T, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25B64T, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F05, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25F32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q80(A), 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q32(A/B), 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25QH16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon EN25QH32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for GigaDevice GD25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1005, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L2005, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L4005, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L8005, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1605, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1635D, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L1635E, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L3205, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L3235D, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix MX25L6405, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Chip status register is 00 +Chip status register: Status Register Write Disable (SRWD) is not set +Chip status register: Bit 6 is not set +Chip status register: Block Protect 3 (BP3) is not set +Chip status register: Block Protect 2 (BP2) is not set +Chip status register: Block Protect 1 (BP1) is not set +Chip status register: Block Protect 0 (BP0) is not set +Chip status register: Write Enable Latch (WEL) is not set +Chip status register: Write In Progress (WIP/BUSY) is not set +Found Macronix flash chip "MX25L6405" (8192 kB, SPI) at physical address 0xff800000. +Probing for Macronix MX25L12805, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx M25PE16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Numonyx N25Q064, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV010, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV020, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV040, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC Pm25LV512, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Sanyo LF25FW203A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL004A, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL008A, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL016A, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL032A, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Spansion S25FL064A, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25LF040A, 512 kB: Invalid OPCODE 0xab, will not execute. +Probing for SST SST25LF080A, 1024 kB: Invalid OPCODE 0xab, will not execute. +Probing for SST SST25VF010, 128 kB: Invalid OPCODE 0x90, will not execute. +Probing for SST SST25VF016B, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF032B, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF064C, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF040, 512 kB: Invalid OPCODE 0x90, will not execute. +Probing for SST SST25VF040B, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST SST25VF040B.REMS, 512 kB: Invalid OPCODE 0x90, will not execute. +Probing for SST SST25VF080B, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P05-A, 64 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P05, 64 kB: Ignoring RES in favour of RDID. +Probing for ST M25P10-A, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P10, 128 kB: Ignoring RES in favour of RDID. +Probing for ST M25P20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P40-old, 512 kB: Ignoring RES in favour of RDID. +Probing for ST M25P80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25P128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25PX16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25PX32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST M25PX64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25Q128, 16384 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X10, 128 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X20, 256 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X40, 512 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X80, 1024 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X16, 2048 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X32, 4096 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Winbond W25X64, 8192 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Unknown SFDP-capable chip, 0 kB: Invalid OPCODE 0x5a, will not execute. +Receiving SFDP signature failed. +Probing for AMIC unknown AMIC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Atmel unknown Atmel SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Eon unknown Eon SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Macronix unknown Macronix SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for PMC unknown PMC SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for SST unknown SST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for ST unknown ST SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Sanyo unknown Sanyo SPI chip, 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Generic unknown SPI chip (RDID), 0 kB: probe_spi_rdid_generic: id1 0xc2, id2 0x2017 +Probing for Generic unknown SPI chip (REMS), 0 kB: Invalid OPCODE 0x90, will not execute. +Probing for Atmel AT49LH002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 82802AB, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Intel 82802AC, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm49FL002, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for PMC Pm49FL004, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Sharp LHF00L04, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF002A/B, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF003A/B, 384 kB: probe_jedec_common: id1 0x0a, id2 0xce, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF004A/B, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF004C, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF008A, 1024 kB: probe_jedec_common: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF008C, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for SST SST49LF016C, 2048 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW040A, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW040B, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW080A, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FLW080B, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW002, 256 kB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW016, 2048 kB: probe_82802ab: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW040, 512 kB: probe_82802ab: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for ST M50FW080, 1024 kB: probe_82802ab: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FA, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FB, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V040FC, 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W49V002FA, 256 kB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V080FA, 1024 kB: probe_jedec_common: id1 0xba, id2 0x8e, id1 is normal flash content, id2 is normal flash content +Probing for Winbond W39V080FA (dual mode), 512 kB: probe_jedec_common: id1 0x50, id2 0x09, id1 parity violation, id1 is normal flash content, id2 is normal flash content +Found Macronix flash chip "MX25L6405" (8192 kB, SPI). +Reading flash... SSFS: SCIP=0, FDONE=1, FCERR=1, AEL=0 +SSFC: SCGO=0, ACS=0, SPOP=0, COP=1, DBC=63, SME=0, SCF=0 +Running OPCODE 0x03 failed at address 0x001000 (payload length was 64). +FAILED. +Restoring MMIO space at 0x7f53b721c8a0 +Restoring PCI config space for 00:1f:0 reg 0xdc diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/input_bustypes.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/input_bustypes.log new file mode 100644 index 00000000..ebce5d5b --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/input_bustypes.log @@ -0,0 +1,11 @@ +0019 +0000 +0000 +0019 +0019 +0011 +0011 +0019 +0019 +0000 +0000 diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/inteltool.err.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/inteltool.err.log new file mode 100644 index 00000000..b192da99 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/inteltool.err.log @@ -0,0 +1 @@ +bash: inteltool: command not found diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/inteltool.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/inteltool.log new file mode 100644 index 00000000..e69de29b diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/ioports.err.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/ioports.err.log new file mode 100644 index 00000000..e69de29b diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/ioports.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/ioports.log new file mode 100644 index 00000000..54e3a06a --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/ioports.log @@ -0,0 +1,60 @@ +0000-0cf7 : PCI Bus 0000:00 + 0000-001f : dma1 + 0020-0021 : pic1 + 0040-0043 : timer0 + 0050-0053 : timer1 + 0060-0060 : keyboard + 0062-0062 : EC data + 0064-0064 : keyboard + 0066-0066 : EC cmd + 0070-0071 : rtc0 + 0080-008f : dma page reg + 00a0-00a1 : pic2 + 00c0-00df : dma2 + 00f0-00ff : fpu + 03c0-03df : vga+ + 0800-080f : pnp 00:01 +0cf8-0cff : PCI conf1 +0d00-ffff : PCI Bus 0000:00 + 1000-1003 : ACPI PM1a_EVT_BLK + 1004-1005 : ACPI PM1a_CNT_BLK + 1008-100b : ACPI PM_TMR + 1010-1015 : ACPI CPU throttle + 1020-102f : ACPI GPE0_BLK + 1030-1033 : iTCO_wdt + 1050-1050 : ACPI PM2_CNT_BLK + 1060-107f : iTCO_wdt + 1180-11ff : pnp 00:01 + 15e0-15ef : pnp 00:01 + 1600-167f : pnp 00:01 + 1680-169f : pnp 00:01 + 1800-1807 : 0000:00:02.0 + 1830-1837 : 0000:00:03.3 + 1830-1837 : serial + 1838-183b : 0000:00:1f.2 + 1838-183b : ahci + 183c-183f : 0000:00:1f.2 + 183c-183f : ahci + 1840-185f : 0000:00:19.0 + 1860-187f : 0000:00:1a.0 + 1860-187f : uhci_hcd + 1880-189f : 0000:00:1a.1 + 1880-189f : uhci_hcd + 18a0-18bf : 0000:00:1a.2 + 18a0-18bf : uhci_hcd + 18c0-18df : 0000:00:1d.0 + 18c0-18df : uhci_hcd + 18e0-18ff : 0000:00:1d.1 + 18e0-18ff : uhci_hcd + 1c00-1c1f : 0000:00:1d.2 + 1c00-1c1f : uhci_hcd + 1c20-1c3f : 0000:00:1f.2 + 1c20-1c3f : ahci + 1c40-1c47 : 0000:00:1f.2 + 1c40-1c47 : ahci + 1c48-1c4f : 0000:00:1f.2 + 1c48-1c4f : ahci + 1c60-1c7f : 0000:00:1f.3 + 2000-2fff : PCI Bus 0000:05 + 3000-3fff : PCI Bus 0000:02 + 4000-4fff : PCI Bus 0000:03 diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/lspci.err.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/lspci.err.log new file mode 100644 index 00000000..e69de29b diff --git a/i18n/fr_FR/docs/hardware/hwdumps/x200/lspci.log b/i18n/fr_FR/docs/hardware/hwdumps/x200/lspci.log new file mode 100644 index 00000000..df6b6ccd --- /dev/null +++ b/i18n/fr_FR/docs/hardware/hwdumps/x200/lspci.log @@ -0,0 +1,2287 @@ +00:00.0 Host bridge [0600]: Intel Corporation Mobile 4 Series Chipset Memory Controller Hub [8086:2a40] (rev 07) + Subsystem: Lenovo Device [17aa:20e0] + Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- + Kernel driver in use: agpgart-intel +00: 86 80 40 2a 06 01 90 20 07 00 00 06 00 00 00 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 e0 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 90 d1 fe 00 00 00 00 01 00 d1 fe 00 00 00 00 +50: 00 00 50 03 59 02 00 00 00 00 00 00 00 00 00 00 +60: 01 00 00 e0 00 00 00 00 01 80 d1 fe 00 00 00 00 +70: 01 00 60 7c 00 00 00 00 01 10 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 10 11 11 01 30 11 11 00 ff 03 00 00 00 1a 3b 00 +a0: 10 00 f0 07 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 7c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 91 02 00 00 +e0: 09 00 0a 11 88 64 00 1c 01 00 00 00 00 00 00 00 +f0: 01 00 00 00 00 00 00 00 a0 0f 07 00 00 00 00 00 +100: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +130: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +170: 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:02.0 VGA compatible controller [0300]: Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a42] (rev 07) (prog-if 00 [VGA controller]) + Subsystem: Lenovo Device [17aa:20e4] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- [disabled] + Capabilities: [90] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 4152 + Capabilities: [d0] Power Management version 3 + Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Kernel driver in use: i915 +00: 86 80 42 2a 07 04 90 00 07 00 00 03 00 00 80 00 +10: 04 00 00 f2 00 00 00 00 0c 00 00 d0 00 00 00 00 +20: 01 18 00 00 00 00 00 00 00 00 00 00 aa 17 e4 20 +30: 00 00 00 00 90 00 00 00 00 00 00 00 0b 01 00 00 +40: 00 00 00 00 48 00 00 00 09 00 0a 11 88 64 00 1c +50: 01 00 50 03 19 00 00 00 00 00 00 00 00 00 00 7a +60: 00 00 00 00 00 00 02 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 05 d0 01 00 0c 30 e0 fe 52 41 00 00 00 00 00 00 +a0: 00 00 00 00 09 00 06 20 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 40 01 00 00 +d0: 01 00 23 00 00 00 00 00 00 00 00 00 34 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 80 00 1a 41 20 00 00 +f0: 0d 1c 34 07 eb 00 00 00 a0 0f 07 00 ea b0 b6 79 + +00:02.1 Display controller [0380]: Intel Corporation Mobile 4 Series Chipset Integrated Graphics Controller [8086:2a43] (rev 07) + Subsystem: Lenovo Device [17aa:20e4] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=fast >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #1, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #0, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- + Changed: MRL- PresDet- LinkState- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41c1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=ff + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=01 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c000 + Kernel driver in use: pcieport +00: 86 80 40 29 07 05 10 00 03 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 02 02 00 30 30 00 00 +20: 00 7c 10 7c 21 7c 31 7c 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 01 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00 00 00 00 00 00 00 +f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:1c.1 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 2 [8086:2942] (rev 03) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #2, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <256ns, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+ + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive+ BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #1, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock- + Changed: MRL- PresDet- LinkState+ + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41d1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=02 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c000 + Kernel driver in use: pcieport +00: 86 80 42 29 07 05 10 00 03 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 03 03 00 40 40 00 00 +20: 50 f2 50 f2 41 7c 51 7c 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 02 04 00 +40: 10 80 41 01 00 80 00 00 00 00 10 00 11 2c 11 02 +50: 40 00 11 30 e0 a0 08 00 38 00 40 01 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe d1 41 00 00 00 00 00 00 +90: 0d a0 00 00 aa 17 f3 20 00 00 00 00 00 00 00 00 +a0: 01 00 02 c8 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 11 08 00 00 00 00 +e0: 00 0f c7 00 06 07 08 00 33 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 03 00 00 00 00 00 +100: 02 00 01 18 00 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00 00 00 00 00 00 00 00 00 00 00 +ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:1c.3 PCI bridge [0604]: Intel Corporation 82801I (ICH9 Family) PCI Express Port 4 [8086:2946] (rev 03) (prog-if 00 [Normal decode]) + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx+ + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [40] Express (v1) Root Port (Slot+), MSI 00 + DevCap: MaxPayload 128 bytes, PhantFunc 0 + ExtTag- RBE+ + DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- + RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- + MaxPayload 128 bytes, MaxReadReq 128 bytes + DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr+ TransPend- + LnkCap: Port #4, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <1us, L1 <4us + ClockPM- Surprise- LLActRep+ BwNot- + LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- CommClk- + ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- + LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt- + SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ + Slot #3, PowerLimit 6.500W; Interlock- NoCompl- + SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt+ HPIrq+ LinkChg- + Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock- + SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet- Interlock- + Changed: MRL- PresDet- LinkState- + RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna+ CRSVisible- + RootCap: CRSVisible- + RootSta: PME ReqID 0000, PMEStatus- PMEPending- + Capabilities: [80] MSI: Enable+ Count=1/1 Maskable- 64bit- + Address: fee0300c Data: 41e1 + Capabilities: [90] Subsystem: Lenovo Device [17aa:20f3] + Capabilities: [a0] Power Management version 2 + Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0+,D1-,D2-,D3hot+,D3cold+) + Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- + Capabilities: [100 v1] Virtual Channel + Caps: LPEVC=0 RefClk=100ns PATEntryBits=1 + Arb: Fixed+ WRR32- WRR64- WRR128- + Ctrl: ArbSelect=Fixed + Status: InProgress- + VC0: Caps: PATOffset=00 MaxTimeSlots=1 RejSnoopTrans- + Arb: Fixed+ WRR32- WRR64- WRR128- TWRR128- WRR256- + Ctrl: Enable+ ID=0 ArbSelect=Fixed TC/VC=01 + Status: NegoPending- InProgress- + Capabilities: [180 v1] Root Complex Link + Desc: PortNumber=04 ComponentID=02 EltType=Config + Link0: Desc: TargetPort=00 TargetComponent=02 AssocRCRB- LinkType=MemMapped LinkValid+ + Addr: 00000000fed1c000 + Kernel driver in use: pcieport +00: 86 80 46 29 07 05 10 00 03 00 04 06 10 00 81 00 +10: 00 00 00 00 00 00 00 00 00 05 0c 00 20 20 00 00 +20: 00 f0 f0 f1 91 f2 91 f2 00 00 00 00 00 00 00 00 +30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 04 00 +40: 10 80 41 01 00 80 00 00 00 00 10 00 11 4c 11 04 +50: 03 00 01 10 e0 a0 18 00 38 00 00 00 08 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 05 90 01 00 0c 30 e0 fe e1 41 00 00 00 00 00 00 +90: 0d a0 00 00 aa 17 f3 20 00 00 00 00 00 00 00 00 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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ea0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +eb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ec0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ed0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ee0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ef0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fa0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + +00:1d.0 USB controller [0c03]: Intel Corporation 82801I (ICH9 Family) USB UHCI Controller #1 [8086:2934] (rev 03) (prog-if 00 [UHCI]) + Subsystem: Lenovo Device [17aa:20f0] + Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- SERR- TAbort- Reset- FastB2B- + PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- + Capabilities: [50] Subsystem: Lenovo Device [17aa:20f4] +00: 86 80 48 24 07 01 10 00 93 01 04 06 00 00 01 00 +10: 00 00 00 00 00 00 00 00 00 0d 0d 00 f0 00 80 22 +20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 +30: 00 00 00 00 50 00 00 00 00 00 00 00 ff 00 04 00 +40: 00 00 00 00 00 00 00 00 00 00 00 00 00 12 00 00 +50: 0d 00 00 00 aa 17 f4 20 00 00 00 00 00 00 00 00 +60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +f0: 00 00 00 00 00 00 00 00 86 0f 03 00 00 00 00 00 + +00:1f.0 ISA bridge [0601]: Intel Corporation ICH9M-E LPC Interface Controller [8086:2917] (rev 03) + Subsystem: Lenovo Device [17aa:20f5] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- + Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- + Kernel driver in use: lpc_ich +00: 86 80 17 29 07 00 10 02 03 00 01 06 00 00 80 00 +10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +20: 00 00 00 00 00 00 00 00 00 00 00 00 aa 17 f5 20 +30: 00 00 00 00 e0 00 00 00 00 00 00 00 00 00 00 00 +40: 01 10 00 00 80 00 00 00 81 11 00 00 10 00 00 00 +50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +60: 8b 8b 8b 8b 90 00 00 00 8b 8b 8b 8b f8 00 00 00 +70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80: 10 00 0f 3f 01 16 7c 00 e1 15 0c 00 81 16 1c 00 +90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +a0: 24 0a 00 00 39 00 80 00 2b 1c 0a 00 00 03 00 c0 +b0: 00 00 f0 00 00 00 00 00 08 00 02 00 00 00 00 00 +c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +d0: 00 00 00 00 67 45 00 00 00 ff 00 00 00 00 00 00 +e0: 09 00 0c 10 00 02 c4 03 04 00 00 00 00 00 00 00 +f0: 01 c0 d1 fe 00 00 00 00 86 0f 03 00 00 00 00 00 + +00:1f.2 SATA controller [0106]: Intel Corporation 82801IBM/IEM (ICH9M/ICH9M-E) 4 port SATA Controller [AHCI mode] [8086:2929] (rev 03) (prog-if 01 [AHCI 1.0]) + Subsystem: Lenovo Device [17aa:20f8] + Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx+ + Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- TAbort- SERR- \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/images/x200/gpio33_location.jpg b/i18n/fr_FR/docs/hardware/images/x200/gpio33_location.jpg new file mode 100644 index 00000000..2f36bda8 Binary files /dev/null and b/i18n/fr_FR/docs/hardware/images/x200/gpio33_location.jpg differ diff --git a/i18n/fr_FR/docs/hardware/index.md b/i18n/fr_FR/docs/hardware/index.md new file mode 100644 index 00000000..d939fad6 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/index.md @@ -0,0 +1,544 @@ +--- +title: Hardware compatibility list +x-toc-enable: true +... + +This sections relates to known hardware compatibility in libreboot. + +For installatation instructions, refer to [../install/](../install/). + +List of supported hardware +-------------------------- + +Libreboot supports the following systems in this release: + +### Desktops (AMD, Intel, x86) + +- [Gigabyte GA-G41M-ES2L motherboard](ga-g41m-es2l.md) +- [Intel D510MO motherboard](d510mo.md) +- [ASUS KCMA-D8 motherboard](kcma-d8.md) +- [Intel D945GCLF](d945gclf.md) +- [Apple iMac 5,2](imac52.md) + +### Servers/workstations (AMD, x86) + +- [ASUS KFSN4-DRE motherboard](kfsn4-dre.md) +- [ASUS KGPE-D16 motherboard](kgpe-d16.md) + +### Laptops (ARM) + +- [ASUS Chromebook C201](c201.md) + +### Laptops (Intel, x86) + +- [Lenovo ThinkPad X60/X60s](#list-of-supported-thinkpad-x60s) +- [Lenovo ThinkPad X60 Tablet](#list-of-supported-thinkpad-x60-tablets) +- [Lenovo ThinkPad T60](#supported-t60-list) (some exceptions) +- [Lenovo ThinkPad X200](x200.md) +- [Lenovo ThinkPad R400](r400.md) +- [Lenovo ThinkPad T400](t400.md) +- [Lenovo ThinkPad T500](t500.md) +- [Lenovo ThinkPad W500](t500.md) +- [Apple MacBook1,1](#information-about-the-macbook11) +- [Apple MacBook2,1](#information-about-the-macbook21) + +'Supported' means that the build scripts know how to build ROM images +for these systems, and that the systems have been tested (confirmed +working). There may be exceptions; in other words, this is a list of +'officially' supported systems. + +It is also possible to build ROM images (from source) for other systems +(and virtual systems, e.g. QEMU). + +EC update on i945 (X60, T60) and GM45 (X200, T400, T500, R400, W500) +============================================================== + +It is recommended that you update to the latest EC firmware version. The +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from +libreboot, so we don't actually provide that, but if you still have +Lenovo BIOS then you can just run the Lenovo BIOS update utility, which +will update both the BIOS and EC version. See: + +- [../install/#flashrom](../install/#flashrom) +- + +NOTE: this can only be done when you are using Lenovo BIOS. How to +update the EC firmware while running libreboot is unknown. Libreboot +only replaces the BIOS firmware, not EC. + +Updated EC firmware has several advantages e.g. bettery battery +handling. + +How to find what EC version you have (i945/GM45) +================================================ + +In GNU+Linux, you can try this: + + $ grep 'at EC' /proc/asound/cards + +Sample output: + + ThinkPad Console Audio Control at EC reg 0x30, fw 7WHT19WW-3.6 + +7WHT19WW is the version in different notation, use search engine to find +out regular version - in this case it's a 1.06 for x200 tablet + +Recommended wifi chipsets +------------------------- + +The following are known to work well: + +- mini PCI express cards using the Atheros AR9285 chipset (e.g. + Atheros AR5B95) - 802.11n +- USB dongles using the AR9271 chipset (e.g. Unex DNuA 93-F) - 802.11n +- Any of the chipsets listed at + + +The following was mentioned (on IRC), but it's unknown to the libreboot +project if these work with linux-libre kernel (TODO: test): + +- ar5bhb116 ar9382 ABGN +- \[0200\]: Qualcomm Atheros AR242x / AR542x Wireless Network Adapter + (PCI-Express) \[168c:001c\] + +List of supported ThinkPad X60s +------------------------------- + +Native gpu initialization ('native graphics') which replaces the +proprietary VGA Option ROM ('[Video +BIOS](https://en.wikipedia.org/wiki/Video_BIOS)' or 'VBIOS'), all +known LCD panels are currently compatible: + +To find what LCD panel you have, see: +[../misc/\#get\_edid\_panelname](../misc/#get_edid_panelname). + +- TMD-Toshiba LTD121ECHB: \# +- CMO N121X5-L06: \# +- Samsung LTN121XJ-L07: \# +- BOE-Hydis HT121X01-101: \# + +You can remove an X61/X61s motherboard from the chassis and install an +X60/X60s motherboard in it's place (for flashing libreboot). The +chassis is mostly identical and the motherboards are the same +shape/size. + +The X60 typically comes with an Intel wifi chipset which does not work +at all without proprietary firmware, and while Lenovo BIOS is running +the system will refuse to boot if you replace the card. Fortunately it +is very easily replaced; just remove the card and install another one +*after* libreboot is installed. See +[\#recommended\_wifi](#recommended_wifi) for replacements. + +List of supported ThinkPad X60 Tablets +-------------------------------------- + +Native gpu initialization ('native graphics') which replaces the +proprietary VGA Option ROM ('[Video +BIOS](https://en.wikipedia.org/wiki/Video_BIOS)' or 'VBIOS'). + +To find what LCD panel you have, see: +[../misc/\#get\_edid\_panelname](../misc/#get_edid_panelname). + +There are 6 known LCD panels for the X60 Tablet: + +- *X60T XGA (1024x768):* + - BOE-Hydis HV121X03-100 (works) + - Toshiba Matsushita LTD121KC9B (works) + - Samsung LTN121XP01 (does not work. blank screen) + - BOE-Hydis HT12X21-351 (does not work. blank screen) +- *X60T SXGA+ (1400x1050):* + - BOE-Hydis HV121P01-100 (works) + - BOE-Hydis HV121P01-101 (works) + +Most X60Ts only have digitizer (pen), but some have finger (touch) +aswell as pen; finger/multitouch doesn't work, only digitizer (pen) +does. + +You can remove an X61/X61s motherboard from the chassis and install an +X60/X60s motherboard in its place (for flashing libreboot). The chassis +is mostly identical and the motherboards are the same shape/size. *It +is unknown if the same applies between the X60 Tablet and the X61 +Tablet*. + +The X60 Tablet typically comes with an Intel wifi chipset which does not +work at all without proprietary firmware, and while Lenovo BIOS is +running the system will refuse to boot if you replace the card. +Fortunately it is very easily replaced; just remove the card and install +another one *after* libreboot is installed. See +[\#recommended\_wifi](#recommended_wifi) for replacements. + +A user with a X60T that has digitizer+finger support, reported that they +could get finger input working. They used linuxwacom at git tag +0.25.99.2 and had the following in their xorg.conf: + + # Now, for some reason (probably a bug in linuxwacom), + # the 'Touch=on' directive gets reset to 'off'. + # So you'll need to do + # $ xsetwacom --set WTouch Touch on + # + # tested with linuxwacom git 42a42b2a8636abc9e105559e5dea467163499de7 + + Section "Monitor" + Identifier "" + DisplaySize 245 184 + EndSection + + Section "Screen" + Identifier "Default Screen Section" + Monitor ".\ +In fact, lack of free VBIOS in general is a big problem in coreboot, and +is one reason (among others) why many ports for coreboot are unsuitable +for libreboot's purpose. + +Theoretically, the ThinkPad T60 with ATI GPU can work with libreboot and +have ROM images compiled for it, however in practise it would not be +usable as a laptop because there would be no visual display at all. That +being said, such a configuration is acceptable for use in a 'headless' +server setup (with serial and/or ssh console as the display). + +Information about the macbook1,1 +-------------------------------- + +There is an Apple laptop called the macbook1,1 from 2006 which uses the +same i945 chipset as the ThinkPad X60/T60. A developer ported the +[MacBook2,1](#information-about-the-macbook21) to coreboot, the ROM images also work on the +macbook1,1. + +You can refer to [\#information-about-the-macbook21](#information-about-the-macbook21) +for most of this. Macbook2,1 laptops come with Core 2 Duo processors +which support 64-bit operating systems (and 32-bit). The MacBook1,1 +uses Core Duo processors (supports 32-bit OS but not 64-bit), and it is +believed that this is the only difference. + +It is believed that all models are compatible, listed here: + +- + +### Compatible models + +Specifically (Order No. / Model No. / CPU): + +- MA255LL/A / A1181 (EMC 2092) / Core Duo T2500 *(tested - working)* +- MA254LL/A / A1181 (EMC 2092) / Core Duo T2400 *(tested - working)* +- MA472LL/A / A1181 (EMC 2092) / Core Duo T2500 (untested) + +Unbricking: [this page shows disassembly +guides](https://www.ifixit.com/Device/MacBook_Core_2_Duo) and mono's +page (see [\#information-about-the-macbook21](#information-about-the-macbook21)) +shows the location of the SPI flash chip on the motherboard. [How to remove the motherboard](https://www.ifixit.com/Guide/MacBook+Core+2+Duo+PRAM+Battery+Replacement/529). + +No method is yet known for flashing in GNU+Linux while the Apple +firmware is running. You will need to disassemble the system and flash +externally. Reading from flash seems to work. For external flashing, +refer to [../install/bbb\_setup.md](../install/bbb_setup.md). + +Information about the macbook2,1 +-------------------------------- + +There is an Apple laptop called the macbook2,1 from late 2006 or early +2007 that uses the same i945 chipset as the ThinkPad X60 and ThinkPad +T60. A developer ported coreboot to their macbook2,1, and now libreboot +can run on it. + +Mono Moosbart is the person who wrote the port for macbook2,1. +Referenced below are copies (up to date at the time of writing, +20140630) of the pages that this person wrote when porting coreboot to +the macbook2,1. They are included here in case the main site goes down +for whatever reason, since they include a lot of useful information. + +Backups created using wget: + + $ wget -m -p -E -k -K -np http://macbook.donderklumpen.de/ + $ wget -m -p -E -k -K -np http://macbook.donderklumpen.de/coreboot/ + +Use `-e robots=off` if using this trick for other sites and the site restricts +using robots.txt + +### Installing GNU+Linux distributions (on Apple EFI firmware) + +How to boot an ISO: burn it to a CD (like you would normally) and hold +down the Alt/Control key while booting. The bootloader will detect the +GNU+Linux CD as 'Windows' (because Apple doesn't think GNU+Linux +exists). Install it like you normally would. When you boot up again, +hold Alt/Control once more. The installation (on the HDD) will once +again be seen as 'Windows'. (it's not actually Windows, but Apple +likes to think that Apple and Microsoft are all that exist.) Now to +install libreboot, follow +[../install/\#flashrom\_macbook21](../install/#flashrom_macbook21). + +### Coreboot wiki page + +- + +### Compatible models + +It is believed that all models are compatible, listed here: + +- + +Specifically (Order No. / Model No. / CPU): + +- MA699LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T5600 *(tested - + working)* +- MA701LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T7200 *(tested - + working)* +- MB061LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7200 (untested) +- MA700LL/A / A1181 (EMC 2121) / Intel Core 2 Duo T7200 *(tested - + working)* +- MB063LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7400 (works) +- MB062LL/A / A1181 (EMC 2139) / Intel Core 2 Duo T7400 *(tested - + working)* + +Also of interest: +[../git/\#config\_macbook21](../git/#config_macbook21). + +Unbricking: [this page shows disassembly +guides](https://www.ifixit.com/Device/MacBook_Core_2_Duo) and mono's +page (see above) shows the location of the SPI flash chip on the +motherboard. [How to remove the +motherboard](https://www.ifixit.com/Guide/MacBook+Core+2+Duo+PRAM+Battery+Replacement/529). + +For external flashing, refer to +[../install/bbb\_setup.md](../install/bbb_setup.md). + +You need to replace OS X with GNU+Linux before flashing libreboot. (OSX +won't run at all in libreboot). + +### Issues and solutions + +There is one mouse button only, however multiple finger tapping +works. Battery life is poor compared to X60/T60. The Apple logo on the +back is a hole, exposing the backlight, which means that it glows. You +should [cover it up](http://cweiske.de/tagebuch/tuxbook.htm). + +*The MacBook2,1 comes with a webcam which does not work with free +software. Webcams are a privacy and security risk; cover it up! Or +remove it.* + +Further issues do have solutions: + +#### Enable AltGr + +The keyboard has a keypad enter instead of an AltGr. The first key on +the right side of the spacebar is the Apple "command" key. On its +right is the keypad enter. We can make it act as an AltGr. + +If your operating system is Trisquel or other dpkg-based distribution, +there is an easy solution. Under root (or sudo) run + + # dpkg-reconfigure keyboard-configuration + +and select the option "apple laptop", leave other settings as their +defaults until you are given the option "Use Keypad Enter as +AltGr". Select this. The keypad enter key will then act as an AltGr +everywhere. + + +For Parabola or other systemd-based distributions you can enable AltGr +manually. Simply add the line + + KEYMAP_TOGGLE=lv3:enter_switch + +to the file /etc/vconsole.conf and then restart the computer. + + +#### Enable 3-finger tap + +A user submitted a utility to enable 3-finger tap on this laptop. It's +available at *resources/utilities/macbook21-three-finger-tap* in the +libreboot git repository. + + +#### Make touchpad more responsive + +Linux kernels of version 3.15 or lower might make the touchpad +extremely sluggish. A user reported that they could get better +response from the touchpad with the following in their xorg.conf: + + Section "InputClass" + Identifier "Synaptics Touchpad" + Driver "synaptics" + MatchIsTouchpad "on" + MatchDevicePath "/dev/input/event*" + Driver "synaptics" + # The next two values determine how much pressure one needs + # for tapping, moving the cursor and other events. + Option "FingerLow" "10" + Option "FingerHigh" "15" + # Do not emulate mouse buttons in the touchpad corners. + Option "RTCornerButton" "0" + Option "RBCornerButton" "0" + Option "LTCornerButton" "0" + Option "LBCornerButton" "0" + # One finger tap = left-click + Option "TapButton1" "1" + # Two fingers tap = right-click + Option "TapButton2" "3" + # Three fingers tap = middle-mouse + Option "TapButton3" "2" + # Try to not count the palm of the hand landing on the touchpad + # as a tap. Not sure if helps. + Option "PalmDetect" "1" + # The following modifies how long and how fast scrolling continues + # after lifting the finger when scrolling + Option "CoastingSpeed" "20" + Option "CoastingFriction" "200" + # Smaller number means that the finger has to travel less distance + # for it to count as cursor movement. Larger number prevents cursor + # shaking. + Option "HorizHysteresis" "10" + Option "VertHysteresis" "10" + # Prevent two-finger scrolling. Very jerky movement + Option "HorizTwoFingerScroll" "0" + Option "VertTwoFingerScroll" "0" + # Use edge scrolling + Option "HorizEdgeScroll" "1" + Option "VertEdgeScroll" "1" + EndSection + + +Copyright © 2014, 2015, 2016 Leah Rowe \ +Copyright © 2017 Eemeli Blåsten \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/kcma-d8.md b/i18n/fr_FR/docs/hardware/kcma-d8.md new file mode 100644 index 00000000..fb7e6eed --- /dev/null +++ b/i18n/fr_FR/docs/hardware/kcma-d8.md @@ -0,0 +1,104 @@ +--- +title: ASUS KCMA-D8 desktop/workstation board +... + +This is a desktop board using AMD hardware (Fam10h *and Fam15h* CPUs +available). It can also be used for building a high-powered workstation. +Powered by libreboot. The coreboot port was done by Timothy Pearson of +Raptor Engineering Inc. and, working with them, merged into libreboot. + +*Memory initialization is still problematic, for some modules. We +recommend avoiding Kingston modules.* + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) - note that external +flashing is required (e.g. BBB), if the proprietary (ASUS) firmware is +currently installed. If you already have libreboot, by default it is +possible to re-flash using software running in GNU+Linux on the kcma-d8, +without using external hardware. + +CPU compatibility +================= + +*Use Opteron 4200 series (works without microcode updates, including hw +virt).* 4300 series needs microcode updates, so avoid those CPUs. 4100 +series is too old, and mostly untested. + +Board status (compatibility) {#boardstatus} +============================ + +See . + +Form factor {#formfactor} +=========== + +This board is ATX form factor. While the [ATX standard, version 2.2](https://web.archive.org/web/20120725150314/http://www.formfactors.org/developer/specs/atx2_2.pdf) +specifies board dimensions 305mm x 244mm, this board measures 305mm x 253mm; +ensure your case supports this extra ~centimeter in width. + +IPMI iKVM module add-on {#ipmi} +======================= + +Don't use it. It uses proprietary firmware and adds a backdoor (remote +out-of-band management chip, similar to the [Intel Management +Engine](../../faq.md#intelme). Fortunately, the firmware is +unsigned (possibly to replace) and physically separate from the +mainboard since it's on the add-on module, which you don't have to +install. + +Flash chips {#flashchips} +=========== + +2MiB flash chips are included by default, on these boards. It's on a +P-DIP 8 slot (SPI chip). The flash chip can be upgraded to higher sizes: +4MiB, 8MiB or 16MiB. With at least 8MiB, you could feasibly fit a +compressed linux+initramfs image (BusyBox+Linux system) into CBFS and +boot that, loading it into memory. + +Libreboot has configs for 2, 4, 8 and 16 MiB flash chip sizes (default +flash chip is 2MiB). + +*DO NOT hot-swap the chip with your bare hands. Use a P-DIP 8 chip +extractor. These can be found online. See +* + +Native graphics initialization {#graphics} +============================== + +Only text-mode is known to work, but linux(kernel) can initialize the +framebuffer display (if it has KMS - kernel mode setting). + +Current issues {#issues} +============== + +- LRDIMM memory modules are currently incompatible +- SAS (via PIKE 2008 module) requires non-free option ROM (and + SeaBIOS) to boot from it (theoretically possible to replace, but you + can put a kernel in CBFS or on SATA and use that to boot GNU, which + can be on a SAS drive. The linux kernel can use those SAS drives + (via PIKE module) without an option ROM). + +- IPMI iKVM module (optional add-on card) uses proprietary firmware. + Since it's for remote out-of-band management, it's theoretically a + backdoor similar to the Intel Management Engine. Fortunately, unlike + the ME, this firmware is unsigned which means that a free + replacement is theoretically possible. For now, the libreboot + project recommends not installing the module. [This + project](https://github.com/facebook/openbmc) might be interesting + to derive from, for those who want to work on a free replacement. In + practise, out-of-band management isn't very useful anyway (or at + the very least, it's not a major inconvenience to not have it). +- Graphics: only text-mode works. See [\#graphics](#graphics) + +Hardware specifications {#specifications} +----------------------- + +Check the ASUS website. + +Copyright © 2016 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/kfsn4-dre.md b/i18n/fr_FR/docs/hardware/kfsn4-dre.md new file mode 100644 index 00000000..02b4dbcb --- /dev/null +++ b/i18n/fr_FR/docs/hardware/kfsn4-dre.md @@ -0,0 +1,113 @@ +--- +title: ASUS KFSN4-DRE server/workstation board +... + +This is a server board using AMD hardware (Fam10h). It can also be used +for building a high-powered workstation. Powered by libreboot. + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +Form factor {#formfactor} +=========== + +These boards use the SSI EEB 3.61 form factor; make sure that your case +supports this. This form factor is similar to E-ATX in that the size is +identical, but the position of the screws are different. + +Flash chips {#flashchips} +=========== + +These boards use LPC flash (not SPI), in a PLCC socket. The default +flash size 1MiB (8Mbits), and can be upgraded to 2MiB (16Mbits). +SST49LF080A is the default that the board uses. SST49LF016C is an +example of a 2MiB (16Mbits) chip, which might work. It is believed that +2MiB (16Mbits) is the maximum size available for the flash chip. + +*DO NOT hot-swap the chip with your bare hands. Use a PLCC chip +extractor. These can be found online. See +* + +Native graphics initialization {#graphics} +============================== + +Native graphics initialization exists (XGI Z9s) for this board. +Framebuffer- and text-mode both work. A serial port is also available. + +Memory +====== + +DDR2 533/667 Registered ECC. 16 slots. Total capacity up to 64GiB. + +Hex-core CPUs {#hexcore} +============= + +PCB revision 1.05G is the latest version of this board and the best one +(the revision number is be printed on the board), if you want to use +dual hex-core CPUs (Opteron 2400/8400 series), though only two board +configurations are believed to support them. Other revisions are +believed to only support dual quad-core CPUs. + +To be sure your board supports a CPU check the official ASUS website here: +. Note: not all CPUs are listed. + +If you are running a Hex-Core CPU on any board version, please contact us. + +Board configurations {#configurations} +============== +There are 7 different configurations of this board: "standard", 2S, iKVM, +iKVM/IST, SAS, SAS/iKVM and SAS/iKVM/IST. + +The 2S boards have two PCI-E slots with the numbers of lanes shared, +making each slot have 8 lanes. + +The iKVM boards are so called because they offer a remote real-time access +to the machine through a removable PCI management card, their hardware is +the same as the non-iKVM ones. + +The SAS versions have a 4-port SAS controller and a four 7-pin SAS connectors +instead of the PCI-E 8x slot which is present in all the other board configurations. +Note: the SAS functionality is **not supported** by libreboot. + +The IST versions with PCB revision 1.05G are the ones who are believed to +support the six core Opteron Istanbul processors (2400 and 8400 series). + +Current issues {#issues} +============== + +- There seems to be a 30 second bootblock delay (observed by + tpearson); the system otherwise boots and works as expected. See + [text/kfsn4-dre/bootlog.txt](text/kfsn4-dre/bootlog.txt) - this uses + the 'simple' bootblock, while tpearson uses the 'normal' + bootblock, which tpearson suspects may be a possible cause. This + person says that they will look into it. [This + config](http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asus/kfsn4-dre/4.0-10101-g039edeb/2015-06-27T03:59:16Z/config.txt;h=4742905c185a93fbda8eb14322dd82c70641aef0;hb=055f5df4e000a97453dfad6c91c2d06ea22b8545) + doesn't have the issue. + +- Text-mode is jittery and it may not be usable, so it's recommended + to flash the BIOS with the coreboot frame-buffer image (kfsn4-dre_vesafb.rom). + The jitter disappears if using KMS once the kernel starts, but it will + remain, if booting the kernel in text-mode. + +- Booting from USB mass storage devices is not possible; neither GRUB + nor SeaBIOS detect USB drives when present. USB keyboards function + under both GRUB and SeaBIOS, albeit slowly under GRUB (several seconds per + character typed). + +- To install an operating system you will need a hard disk + with a pre-installed OS otherwise you have to plug in another hard disk or + a CD/DVD reader in order to boot a copy of the installer of your OS, since + the USB booting doesn't work. + +Other information +================= + +[specifications](https://web.archive.org/web/20181212180051/http://ftp.tekwind.co.jp/pub/asustw/mb/Socket%20F/KFSN4-DRE/Manual/e3335_kfsn4-dre.pdf) + +Copyright © 2015 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/kgpe-d16.md b/i18n/fr_FR/docs/hardware/kgpe-d16.md new file mode 100644 index 00000000..45b1ae6c --- /dev/null +++ b/i18n/fr_FR/docs/hardware/kgpe-d16.md @@ -0,0 +1,219 @@ +--- +title: ASUS KGPE-D16 server/workstation board +... + +This is a server board using AMD hardware (Fam10h *and Fam15h* CPUs +available). It can also be used for building a high-powered workstation. +Powered by libreboot. The coreboot port was done by Timothy Pearson of +Raptor Engineering Inc. and, working with them (and sponsoring the +work), merged into libreboot. + +*Memory initialization is still problematic, for some modules. We +recommend avoiding Kingston modules.* +*For working configurations see .* + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) - note that external +flashing is required (e.g. BBB), if the proprietary (ASUS) firmware is +currently installed. If you already have libreboot, by default it is +possible to re-flash using software running in GNU+Linux on the +KGPE-D16, without using external hardware. + +CPU compatibility +================= + +*Use Opteron 6200 series (works without microcode updates, including hw +virt).* 6300 series needs microcode updates, so avoid those CPUs. 6100 +series is too old, and mostly untested. + +Board status (compatibility) {#boardstatus} +============================ + +See . + +Form factor {#formfactor} +=========== + +These boards use the SSI EEB 3.61 form factor; make sure that your case +supports this. This form factor is similar to E-ATX in that the size is +identical, but the position of the screws are different. + +IPMI iKVM module add-on {#ipmi} +======================= + +Don't use it. It uses proprietary firmware and adds a backdoor (remote +out-of-band management chip, similar to the [Intel Management +Engine](../../faq.md#intelme). Fortunately, the firmware is +unsigned (possibly to replace) and physically separate from the +mainboard since it's on the add-on module, which you don't have to +install. + +Flash chips {#flashchips} +=========== + +2MiB flash chips are included by default, on these boards. It's on a +P-DIP 8 slot (SPI chip). The flash chip can be upgraded to higher sizes: +4MiB, 8MiB or 16MiB. With at least 8MiB, you could feasibly fit a +compressed linux+initramfs image (BusyBox+Linux system) into CBFS and +boot that, loading it into memory. + +Libreboot has configs for 2, 4, 8 and 16 MiB flash chip sizes (default +flash chip is 2MiB). + +*DO NOT hot-swap the chip with your bare hands. Use a P-DIP 8 chip +extractor. These can be found online. See +* + +Native graphics initialization {#graphics} +============================== + +Only text-mode is known to work, but linux(kernel) can initialize the +framebuffer display (if it has KMS - kernel mode setting). + +Current issues {#issues} +============== + +- LRDIMM memory modules are currently incompatible +- SAS (via PIKE 2008 module) requires non-free option ROM (and + SeaBIOS) to boot from it (theoretically possible to replace, but you + can put a kernel in CBFS or on SATA and use that to boot GNU, which + can be on a SAS drive. The linux kernel can use those SAS drives + (via PIKE module) without an option ROM). + +- IPMI iKVM module (optional add-on card) uses proprietary firmware. + Since it's for remote out-of-band management, it's theoretically a + backdoor similar to the Intel Management Engine. Fortunately, unlike + the ME, this firmware is unsigned which means that a free + replacement is theoretically possible. For now, the libreboot + project recommends not installing the module. [This + project](https://github.com/facebook/openbmc) might be interesting + to derive from, for those who want to work on a free replacement. In + practise, out-of-band management isn't very useful anyway (or at + the very least, it's not a major inconvenience to not have it). +- Graphics: only text-mode works. See [\#graphics](#graphics) + +Hardware specifications {#specifications} +----------------------- + +The information here is adapted, from the ASUS website. + +### Processor / system bus + +- 2 CPU sockets (G34 compatible) +- HyperTransport™ Technology 3.0 +- CPUs supported: + - AMD Opteron 6100 series (Fam10h. No IOMMU support. *Not* + recommended - old. View errata datasheet here: + ) + - AMD Opteron 6200 series (Fam15h, with full IOMMU support in + libreboot - *highly recommended - fast, and works well without + microcode updates, including virtualization*) + - AMD Opteron 6300 series (Fam15h, with full IOMMU support in + libreboot. *AVOID LIKE THE PLAGUE - virtualization is broken + without microcode updates.* + - NOTE: 6300 series CPUs have buggy microcode built-in, and + libreboot recommends avoiding the updates. The 6200 series CPUs + have more reliable microcode. Look at this errata datasheet: + + (see Errata 734 - this is what kills the 6300 series) +- 6.4 GT/s per link (triple link) + +### Core logic + +- AMD SR5690 +- AMD SP5100 + +### Memory compatibility (with libreboot) + +- *Total Slots:* 16 (4-channel per CPU, 8 DIMM per CPU), ECC +- *Capacity:* Maximum up to 256GB RDIMM (Tested max 128GB) +- *Memory Type that is compatible:* + - DDR3 1600/1333/1066/800 UDIMM\* + - DDR3 1600/1333/1066/800 RDIMM\* +- *Compatible sizes per memory module:* + - 16GB, 8GB, 4GB, 3GB, 2GB, 1GB RDIMM + - 8GB, 4GB, 2GB, 1GB UDIMM + +### Expansion slots + +- *Total slot:* 6 +- *Slot Location 1:* PCI 32bit/33MHz +- *Slot Location 2:* PCI-E x16 (Gen2 X8 Link) +- *Slot Location 3:* PCI-E x16 (Gen2 X16 Link), Auto switch to x8 + link if slot 2 is occupied +- *Slot Location 4:* PCI-E x8 (Gen2 X4 Link) +- *Slot Location 5:* PCI-E x16 (Gen2 X16 Link) +- *Slot Location 6:* PCI-E x16 (Gen2 X16 Link), Auto turn off if + slot 5 is occupied, For 1U FH/FL Card, MIO supported +- *Additional Slot 1:* PIKE slot (for SAS drives. See notes above) +- Follow SSI Location\# + +### Form factor {#form-factor} + +- SSI EEB 3.61 (12"x13") + +### ASUS features + +- Fan Speed Control +- Rack Ready (Rack and Pedestal dual use) + +### Storage + +- *SATA controller:* + - AMD SP5100 + - 6 x SATA2 300MB/s +- *SAS/SATA Controller:* + - ASUS PIKE2008 3Gbps 8-port SAS card included + +### Networking + +- 2 x Intel® 82574L + 1 x Mgmt LAN + +### Graphics + +- Aspeed AST2050 with 8MB VRAM + +### On board I/O + +- 1 x PSU Power Connector (24-pin SSI power connector + 8-pin SSI + 12V + 8-pin SSI 12V power connector) +- 1 x Management Connector , Onboard socket for management card +- 3 x USB pin header , Up to 6 Devices +- 1 x Internal A Type USB Port +- 8 x Fan Header , 4pin (3pin/4pin fan dual support) +- 2 x SMBus +- 1 x Serial Port Header +- 1 x TPM header +- 1 x PS/2 KB/MS port + +### Back I/O ports + +- 1 x External Serial Port +- 2 x External USB Port +- 1 x VGA Port +- 2 x RJ-45 +- 1 x PS/2 KB/Mouse + +### Environment + +- *Operation temperature:* 10C \~ 35C +- *Non operation temperature:* -40C \~ 70C +- *Non operation humidity:* 20% \~ 90% ( Non condensing) + +### Monitoring + +- CPU temperatures +- Fan speed (RPM) + +### Note: + +- \* DDR3 1600 can only be supported with AMD Opteron 6300/6200 series + processor + +Copyright © 2015 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/mac_address.md b/i18n/fr_FR/docs/hardware/mac_address.md new file mode 100644 index 00000000..0a0d3621 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/mac_address.md @@ -0,0 +1,107 @@ +--- +title: Changing the MAC address +... + +Introduction (GM45+e1000) +========================= + +This section is applicable to all Libreboot-supported laptops with the +mobile 4 series chipset (as shown in `$ lspci`) +that use the e1000 ethernet controller (e.g. T400, X200). +The R500 is an exception to this as it does not use the built-in e1000. + +On all these laptops, the +[MAC address](https://en.wikipedia.org/wiki/MAC_address) +for the built-in gigabit ethernet controller is stored inside the flash chip, +along with Libreboot and other configuration data. Therefore, installing +Libreboot will overwrite it. + +Thus, for these laptops, prebuilt Libreboot already contains a generic +MAC address in the configuration section. This address is `00:f5:f0:40:71:fe` +in builds before 2018-01-16 and `00:4c:69:62:72:65` (see the ascii character +set) afterwards. +Unless you change it, your computer will boot and use it. This can lead +to network problems if you have more than one Libreboot computer on +the same layer2 network (e.g. on the same network switch). The switch +(postman) will simply not know who to deliver to as the MAC (house) addresses +will be the same. + +To prevent these address clashes, you can either modify prebuilt Libreboot +to use an address of your own choosing or you can change the address in your +operating system's boot scripts. + +In either case, it is a good idea to write down the address that your +computer originally had. + +Obtaining the existing MAC address +================================== + +The existing MAC address may be obtained by the following methods: + +1. Run `ip link` or `ifconfig` in a terminal/console/shell; + find your ethernet device (e.g., **enpXXX** or **ethXXX**), + and look for a set of 12 colon-delimited + [hexadecimal digits](https://en.wikipedia.org/wiki/Hexadecimal). + For example: `00:f3:f0:45:91:fe`. + + * `$ ip link` + + `... link/ether ??:??:??:??:??:?? brd ...` + + * Alternatively: + + `$ ifconfig` + + `... ether ??:??:??:??:??:?? txqueuelen ...` + + +2. Otherwise you can read the white label that is often found on the + motherboard under the memory sticks: + ![](../install/images/t400/macaddress1.jpg) + +3. The MAC address is usually listed on the laptop chassis as well. This one + will be incorrect if the motherboard was changed and the stickers were not + updated. + +Changing the MAC address in the operating system +================================================ + +There are three portable ways of doing so: + +1. Using the new iproute2 package: + + `# ip link set down` + + `# ip link set dev address 00:4c:69:62:72:65` + + `# ip link set up` + + +2. Using the old `ifconfig` command: + + `# ifconfig hw ether 00:4c:69:62:72:65` + + +3. Using the macchanger package. + +You can use use of these three methods in your operating system's +init scripts or you can use your operating system's own networking +configuration. Refer to your operating system's documentation for +how to do this. + +Changing the MAC address in Libreboot +===================================== + +See [here](../gnulinux/grub_cbfs.md#changeMAC). + + + +Copyright © 2017 Fedja Beader + +Copyright © 2014, 2015 Leah Rowe + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/r400.md b/i18n/fr_FR/docs/hardware/r400.md new file mode 100644 index 00000000..ae22c50f --- /dev/null +++ b/i18n/fr_FR/docs/hardware/r400.md @@ -0,0 +1,70 @@ +--- +title: ThinkPad R400 +... + +It is believed that all or most R400 laptops are compatible. See notes +about [CPU +compatibility](../install/r400_external.html#cpu_compatibility) for +potential incompatibilities. + +There are two possible flash chip sizes for the R400: 4MiB (32Mbit) or +8MiB (64Mbit). This can be identified by the type of flash chip below +the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. + +*The R400 laptops come with the ME (and sometimes AMT in addition) +before flashing libreboot. Libreboot disables and removes it by using a +modified descriptor: see [gm45\_remove\_me.md](gm45_remove_me.md)* +(contains notes, plus instructions) + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +EC update {#ecupdate} +========= + +It is recommended that you update to the latest EC firmware version. The +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from +libreboot, so we don't actually provide that, but if you still have +Lenovo BIOS then you can just run the Lenovo BIOS update utility, which +will update both the BIOS and EC version. See: + +- [../install/#flashrom](../install/#flashrom) +- + +NOTE: this can only be done when you are using Lenovo BIOS. How to +update the EC firmware while running libreboot is unknown. Libreboot +only replaces the BIOS firmware, not EC. + +Updated EC firmware has several advantages e.g. bettery battery +handling. + +Compatibility (without blobs) {#compatibility_noblobs} +----------------------------- + +### Hardware virtualization (vt-x) {#hwvirt} + +The R400, when run without CPU microcode updates in coreboot, currently +kernel panics if running QEMU with vt-x enabled on 2 cores for the +guest. With a single core enabled for the guest, the guest panics (but +the host is fine). Working around this in QEMU might be possible; if +not, software virtualization should work fine (it's just slower). + +On GM45 hardware (with libreboot), make sure that the *kvm* and +*kvm\_intel* kernel modules are not loaded, when using QEMU. + +The following errata datasheet from Intel might help with investigation: + + +The R400 is almost identical to the X200, code-wise. See +[x200.md](x200.md). + +TODO: put hardware register logs here like on the [X200](x200.md) and +[T400](t400.md) page. + +Copyright © 2014, 2015 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/t400.md b/i18n/fr_FR/docs/hardware/t400.md new file mode 100644 index 00000000..f7c4d437 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/t400.md @@ -0,0 +1,82 @@ +--- +title: ThinkPad T400 +... + +It is believed that all or most laptops of the model T400 are compatible. See notes +about [CPU +compatibility](../install/t400_external.html#cpu_compatibility) for +potential incompatibilities. + +There are two possible flash chip sizes for the T400: 4MiB (32Mbit) or +8MiB (64Mbit). This can be identified by the type of flash chip below +the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. + +*The T400 laptops come with the ME (and sometimes AMT in addition) +before flashing libreboot. Libreboot disables and removes it by using a +modified descriptor: see [gm45\_remove\_me.md](gm45_remove_me.md)* +(contains notes, plus instructions) + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +EC update {#ecupdate} +========= + +It is recommended that you update to the latest EC firmware version. The +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from +libreboot, so we don't actually provide that, but if you still have +Lenovo BIOS then you can just run the Lenovo BIOS update utility, which +will update both the BIOS and EC version. See: + +- [../install/#flashrom](../install/#flashrom) +- + +NOTE: this can only be done when you are using Lenovo BIOS. How to +update the EC firmware while running libreboot is unknown. Libreboot +only replaces the BIOS firmware, not EC. + +Updated EC firmware has several advantages e.g. bettery battery +handling. + +Compatibility (without blobs) {#compatibility_noblobs} +----------------------------- + +### Hardware virtualization (vt-x) {#hwvirt} + +The T400, when run without CPU microcode updates in coreboot, currently +kernel panics if running QEMU with vt-x enabled on 2 cores for the +guest. With a single core enabled for the guest, the guest panics (but +the host is fine). Working around this in QEMU might be possible; if +not, software virtualization should work fine (it's just slower). + +On GM45 hardware (with libreboot), make sure that the *kvm* and +*kvm\_intel* kernel modules are not loaded, when using QEMU. + +The following errata datasheet from Intel might help with investigation: + + +The T400 is almost identical to the X200, code-wise. See +[x200.md](x200.md). + +Hardware register dumps {#regdumps} +----------------------- + +The coreboot wiki +[shows](http://www.coreboot.org/Motherboard_Porting_Guide) how to +collect various logs useful in porting to new boards. Following are +outputs from the T400: + +- T400 with *Winbond W25X64* flash chip (8MiB, SOIC-16) and Lenovo + BIOS 2.02 (EC firmware 1.01): + - [../future/dumps/logs-t400-bios2.02-ec1.01/](../future/dumps/logs-t400-bios2.02-ec1.01/) + +- Version of flashrom used for the external flashing/reading logs is + the one that libreboot git revision c164960 uses. + +Copyright © 2015 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/t500.md b/i18n/fr_FR/docs/hardware/t500.md new file mode 100644 index 00000000..3973346c --- /dev/null +++ b/i18n/fr_FR/docs/hardware/t500.md @@ -0,0 +1,104 @@ +--- +title: ThinkPad T500 +... + +It is believed that all or most T500 laptops are compatible. See notes +about [CPU +compatibility](../install/t500_external.html#cpu_compatibility) for +potential incompatibilities. + +W500 is also compatible, and mostly the same design as T500. + +There are two possible flash chip sizes for the T500: 4MiB (32Mbit) or +8MiB (64Mbit). This can be identified by the type of flash chip below +the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. + +*The T500 laptops come with the ME (and sometimes AMT in addition) +before flashing libreboot. Libreboot disables and removes it by using a +modified descriptor: see [gm45\_remove\_me.md](gm45_remove_me.md)* +(contains notes, plus instructions) + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +EC update {#ecupdate} +========= + +It is recommended that you update to the latest EC firmware version. The +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from +libreboot, so we don't actually provide that, but if you still have +Lenovo BIOS then you can just run the Lenovo BIOS update utility, which +will update both the BIOS and EC version. See: + +- [../install/#flashrom](../install/#flashrom) +- + +NOTE: this can only be done when you are using Lenovo BIOS. How to +update the EC firmware while running libreboot is unknown. Libreboot +only replaces the BIOS firmware, not EC. + +Updated EC firmware has several advantages e.g. bettery battery +handling. + +Compatibility (without blobs) {#compatibility_noblobs} +----------------------------- + +### Hardware virtualization (vt-x) {#hwvirt} + +The T500, when run without CPU microcode updates in coreboot, currently +kernel panics if running QEMU with vt-x enabled on 2 cores for the +guest. With a single core enabled for the guest, the guest panics (but +the host is fine). Working around this in QEMU might be possible; if +not, software virtualization should work fine (it's just slower). + +On GM45 hardware (with libreboot), make sure that the *kvm* and +*kvm\_intel* kernel modules are not loaded, when using QEMU. + +The following errata datasheet from Intel might help with investigation: + + +The T500 is almost identical to the X200, code-wise. See +[x200.md](x200.md). + +Descriptor and Gbe differences {#descriptor_difference} +------------------------------ + +See +[../future/dumps/t500\_x200\_descriptor/descriptor\_diff\_t500\_x200.txt](../future/dumps/t500_x200_descriptor/descriptor_diff_t500_x200.txt) +and +[../future/dumps/t500\_x200\_descriptor/gbe\_diff\_t500\_x200.txt](../future/dumps/t500_x200_descriptor/gbe_diff_t500_x200.txt) + +The patches above are based on the output from ich9deblob on a +factory.rom image dumped from the T500 with a SOIC-8 4MiB flash chip. +The patch re-creates the X200 descriptor/gbe source, so the commands +were something like: + + $ diff -u t500gbe x200gbe + $ diff -u t500descriptor x200descriptor + +ME VSCC table is in a different place and a different size on the T500. +Libreboot disables and removes the ME anyway, so it doesn't matter. + +The very same descriptor/gbe used on the X200 (generated by +[ich9gen](gm45_remove_me.html#ich9gen)) was re-used on the T500, and it +still worked. + +Hardware register dumps {#regdumps} +----------------------- + +The coreboot wiki +[shows](http://www.coreboot.org/Motherboard_Porting_Guide) how to +collect various logs useful in porting to new boards. Following are +outputs from the T500: + +- T500 with *Macronix MX25L3205D* flash chip (4MiB, SOIC-8) and + Lenovo BIOS 3.13 7VET83WW (EC firmware 1.06): + - [../future/dumps/t500log/](../future/dumps/t500log/) + +Copyright © 2015 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/hardware/text/kfsn4-dre/bootlog.txt b/i18n/fr_FR/docs/hardware/text/kfsn4-dre/bootlog.txt new file mode 100644 index 00000000..ea6722d8 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/text/kfsn4-dre/bootlog.txt @@ -0,0 +1,3871 @@ +*****TEXT MODE ROM IMAGE***** + + + +coreboot-4.0 Fri Jun 26 20:19:07 UTC 2015 romstage starting... +BSP Family_Model: 00100f21 +*sysinfo range: [000c4000,000c6899] +bsp_apicid = 00 +cpu_init_detectedx = 00000000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: 'cpu_microcode_blob.bin' not found. +[microcode] microcode file not found. Skipping updates. +cpuSetAMDMSR done +Enter amd_ht_init() +AMD_CB_EventNotify() + event class: 05 + event: 1004 + data: 04 00 00 01 +AMD_CB_EventNotify() + event class: 05 + event: 2006 + data: 04 00 01 00 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Exit amd_ht_init() +cpuSetAMDPCI 00 done +cpuSetAMDPCI 01 done +Prep FID/VID Node:00 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f23 + F3xD8: 03001c14 + F3xDC: 00005428 +Prep FID/VID Node:01 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f23 + F3xD8: 03001c14 + F3xDC: 00005428 +setup_remote_node: 01 done +Start node 01 done. +core0 started: 01 + +Begin FIDVID MSR 0xc0010071 0x20a600e4 0x38045044 +FIDVID on BSP, APIC_id: 00 +BSP fid = 10400 +Wait for AP stage 1: ap_apicid = 1 +init_fidvid_bsp_stage1: timed out reading from ap 01 +Wait for AP stage 1: ap_apicid = 2 +init_fidvid_bsp_stage1: timed out reading from ap 02 +Wait for AP stage 1: ap_apicid = 3 +init_fidvid_bsp_stage1: timed out reading from ap 03 +Wait for AP stage 1: ap_apicid = 4 + readback = 4010401 + common_fid(packed) = 10400 +Wait for AP stage 1: ap_apicid = 5 +init_fidvid_bsp_stage1: timed out reading from ap 05 +Wait for AP stage 1: ap_apicid = 6 +init_fidvid_bsp_stage1: timed out reading from ap 06 +Wait for AP stage 1: ap_apicid = 7 +init_fidvid_bsp_stage1: timed out reading from ap 07 +common_fid = 10400 +FID Change Node:00, F3xD4: c3310f24 +FID Change Node:01, F3xD4: c3310f24 +End FIDVIDMSR 0xc0010071 0x20a600e4 0x38005044 +start_other_cores() +init node: 00 cores: 03 +Start other core - nodeid: 00 cores: 03 +init node: 01 cores: 03 +Start other core - nodeid: 01 cores: 03 +started ap apicid: * AP 01started +* AP 02started +* AP 03started +* AP 05started +* AP 06started +* AP 07started + +set_ck804_base_unit_id() +...WARM RESET... + + + + +coreboot-4.0 Fri Jun 26 20:19:07 UTC 2015 romstage starting... +BSP Family_Model: 00100f21 +*sysinfo range: [000c4000,000c6899] +bsp_apicid = 00 +cpu_init_detectedx = 00000000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: 'cpu_microcode_blob.bin' not found. +[microcode] microcode file not found. Skipping updates. +cpuSetAMDMSR done +Enter amd_ht_init() +AMD_CB_EventNotify() + event class: 05 + event: 1004 + data: 04 00 00 01 +AMD_CB_EventNotify() + event class: 05 + event: 2006 + data: 04 00 01 00 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Exit amd_ht_init() +cpuSetAMDPCI 00 done +cpuSetAMDPCI 01 done +Prep FID/VID Node:00 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f24 + F3xD8: 03001c14 + F3xDC: 00005428 +Prep FID/VID Node:01 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f24 + F3xD8: 03001c14 + F3xDC: 00005428 +setup_remote_node: 01 done +Start node 01 done. +core0 started: 01 + +Begin FIDVID MSR 0xc0010071 0x20a600e4 0x38005044 +End FIDVIDMSR 0xc0010071 0x20a600e4 0x38003803 +start_other_cores() +init node: 00 cores: 03 +Start other core - nodeid: 00 cores: 03 +init node: 01 cores: 03 +Start other core - nodeid: 01 cores: 03 +started ap apicid: * AP 01started +* AP 02started +* AP 03started +* AP 05started +* AP 06started +* AP 07started + +set_ck804_base_unit_id() +fill_mem_ctrl() +enable_smbus() +SMBus controller enabled +raminit_amdmct() +raminit_amdmct begin: +activate_spd_rom() for node 00 +enable_spd_node0() +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +activate_spd_rom() for node 01 +enable_spd_node1() +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 + Node: 00 base: 00 limit: ffffff BottomIO: c00000 + Node: 01 base: 1400000 limit: 17fffff BottomIO: c00000 + Copy dram map from Node 0 to Node 01 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +raminit_amdmct end: +CBMEM: +IMD: root @ bffff000 254 entries. +IMD: root @ bfffec00 62 entries. +amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +disable_spd() +enable_msi_mapping() +Prepare CAR migration and stack regions... Fill [003fd000-003fffff] ... Done +Copying data from cache to RAM... Copy [000c4000-000c693f] to [003fd6c0 - 003fffff] ... Done +Switching to use RAM as stack... Top about 003fd6ac ... Done +Disabling cache as ram now +Prepare ramstage memory region... Fill [00000000-003fcfff] ... Done +CBFS provider active. +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/ramstage' +CBFS: Found @ offset 15440 size 147e1 +'fallback/ramstage' located at offset: 15478 size: 147e1 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Capability: type 0x0a @ 0x44 + + +coreboot-4.0 Fri Jun 26 20:19:07 UTC 2015 ramstage starting... +Moving GDT to bfffe980...ok +BS: BS_PRE_DEVICE times (us): entry 0 run 1 exit 0 +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0 +Enumerating buses... +Show all devs... Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:18.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:01.0: enabled 1 +PNP: 002e.0: enabled 1 +PNP: 002e.1: enabled 0 +PNP: 002e.2: enabled 1 +PNP: 002e.3: enabled 1 +PNP: 002e.5: enabled 1 +PNP: 002e.7: enabled 0 +PNP: 002e.8: enabled 0 +PNP: 002e.9: enabled 1 +PNP: 002e.a: enabled 0 +PNP: 002e.b: enabled 1 +PCI: 00:01.1: enabled 1 +I2C: 00:50: enabled 1 +I2C: 00:51: enabled 1 +I2C: 00:52: enabled 1 +I2C: 00:53: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:2f: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:04.0: enabled 0 +PCI: 00:04.1: enabled 0 +PCI: 00:06.0: enabled 1 +PCI: 00:07.0: enabled 1 +PCI: 00:08.0: enabled 1 +PCI: 00:09.0: enabled 1 +PCI: 00:04.0: enabled 1 +PCI: 00:0a.0: enabled 0 +PCI: 00:0b.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:0c.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:0d.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:0e.0: enabled 1 +PCI: 00:0f.0: enabled 0 +PCI: 00:18.1: enabled 1 +PCI: 00:18.2: enabled 1 +PCI: 00:18.3: enabled 1 +PCI: 00:18.4: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:19.1: enabled 1 +PCI: 00:19.2: enabled 1 +PCI: 00:19.3: enabled 1 +PCI: 00:19.4: enabled 1 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + DOMAIN: 0000: enabled 1 + PCI: 00:18.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:01.0: enabled 1 + PNP: 002e.0: enabled 1 + PNP: 002e.1: enabled 0 + PNP: 002e.2: enabled 1 + PNP: 002e.3: enabled 1 + PNP: 002e.5: enabled 1 + PNP: 002e.7: enabled 0 + PNP: 002e.8: enabled 0 + PNP: 002e.9: enabled 1 + PNP: 002e.a: enabled 0 + PNP: 002e.b: enabled 1 + PCI: 00:01.1: enabled 1 + I2C: 00:50: enabled 1 + I2C: 00:51: enabled 1 + I2C: 00:52: enabled 1 + I2C: 00:53: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:2f: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:04.0: enabled 0 + PCI: 00:04.1: enabled 0 + PCI: 00:06.0: enabled 1 + PCI: 00:07.0: enabled 1 + PCI: 00:08.0: enabled 1 + PCI: 00:09.0: enabled 1 + PCI: 00:04.0: enabled 1 + PCI: 00:0a.0: enabled 0 + PCI: 00:0b.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:0c.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:0d.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:0e.0: enabled 1 + PCI: 00:0f.0: enabled 0 + PCI: 00:18.1: enabled 1 + PCI: 00:18.2: enabled 1 + PCI: 00:18.3: enabled 1 + PCI: 00:18.4: enabled 1 + PCI: 00:19.0: enabled 1 + PCI: 00:19.1: enabled 1 + PCI: 00:19.2: enabled 1 + PCI: 00:19.3: enabled 1 + PCI: 00:19.4: enabled 1 +Root Device scanning... +root_dev_scan_bus for Root Device +setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000 +setup_bsp_ramtop, TOP MEM2: msr.lo = 0x80000000, msr.hi = 0x00000001 +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +CPU_CLUSTER: 0 scanning... +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 + PCI: 00:18.3 siblings=3 +CPU: APIC: 00 enabled +CPU: APIC: 01 enabled +CPU: APIC: 02 enabled +CPU: APIC: 03 enabled + PCI: 00:19.3 siblings=3 +CPU: APIC: 04 enabled +CPU: APIC: 05 enabled +CPU: APIC: 06 enabled +CPU: APIC: 07 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:18.0 [1022/1200] bus ops +PCI: 00:18.0 [1022/1200] enabled +PCI: 00:18.1 [1022/1201] enabled +PCI: 00:18.2 [1022/1202] enabled +PCI: 00:18.3 [1022/1203] ops +PCI: 00:18.3 [1022/1203] enabled +PCI: 00:18.4 [1022/1204] enabled +PCI: 00:19.0 [1022/1200] bus ops +PCI: 00:19.0 [1022/1200] enabled +PCI: 00:19.1 [1022/1201] enabled +PCI: 00:19.2 [1022/1202] enabled +PCI: 00:19.3 [1022/1203] ops +PCI: 00:19.3 [1022/1203] enabled +PCI: 00:19.4 [1022/1204] enabled +PCI: 00:18.0 scanning... +PCI: 00:00.0 [10de/005e] ops +PCI: 00:00.0 [10de/005e] enabled +Capability: type 0x08 @ 0x44 +flags: 0x01e0 +PCI: 00:00.0 count: 000f static_count: 0010 +PCI: 00:00.0 [10de/005e] enabled next_unitid: 0010 +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [10de/005e] enabled +PCI: 00:01.0 [10de/0051] bus ops +PCI: 00:01.0 [10de/0051] enabled +PCI: 00:01.1 [10de/0052] bus ops +PCI: 00:01.1 [10de/0052] enabled +PCI: 00:02.0 [10de/005a] ops +PCI: 00:02.0 [10de/005a] enabled +PCI: 00:02.1 [10de/005b] ops +PCI: 00:02.1 [10de/005b] enabled +PCI: 00:04.0 [10de/0059] ops +PCI: 00:04.0 [10de/0059] disabled +PCI: 00:04.1 [10de/0058] ops +PCI: 00:04.1 [10de/0058] disabled +PCI: 00:06.0 [10de/0053] ops +PCI: 00:06.0 [10de/0053] enabled +PCI: 00:07.0 [10de/0054] ops +PCI: 00:07.0 [10de/0054] enabled +PCI: 00:08.0 [10de/0055] ops +PCI: 00:08.0 [10de/0055] enabled +PCI: 00:09.0 [10de/005c] bus ops +PCI: 00:09.0 [10de/005c] enabled +PCI: 00:0b.0 [10de/005d] bus ops +PCI: 00:0b.0 [10de/005d] enabled +PCI: 00:0c.0 [10de/005d] bus ops +PCI: 00:0c.0 [10de/005d] enabled +PCI: 00:0d.0 [10de/005d] bus ops +PCI: 00:0d.0 [10de/005d] enabled +PCI: 00:0e.0 [10de/005d] bus ops +PCI: 00:0e.0 [10de/005d] enabled +PCI: 00:01.0 scanning... +scan_lpc_bus for PCI: 00:01.0 +PNP: 002e.0 enabled +PNP: 002e.1 disabled +PNP: 002e.2 enabled +PNP: 002e.3 enabled +PNP: 002e.5 enabled +PNP: 002e.7 disabled +PNP: 002e.8 disabled +PNP: 002e.9 enabled +PNP: 002e.a disabled +PNP: 002e.b enabled +scan_lpc_bus for PCI: 00:01.0 done +PCI: 00:01.1 scanning... +scan_smbus for PCI: 00:01.1 +smbus: PCI: 00:01.1[0]->I2C: 01:50 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:51 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:52 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:53 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:54 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:55 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:56 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:57 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:2f enabled +scan_smbus for PCI: 00:01.1 done +PCI: 00:09.0 scanning... +do_pci_scan_bridge for PCI: 00:09.0 +PCI: pci_scan_bus for bus 01 +PCI: 01:04.0 [18ca/0020] ops +PCI: 01:04.0 [18ca/0020] enabled +PCI: 00:0b.0 scanning... +do_pci_scan_bridge for PCI: 00:0b.0 +PCI: pci_scan_bus for bus 02 +PCI: 02:00.0 [14e4/1659] enabled +PCI: 00:0c.0 scanning... +do_pci_scan_bridge for PCI: 00:0c.0 +PCI: pci_scan_bus for bus 03 +PCI: 03:00.0 [14e4/1659] enabled +PCI: 00:0d.0 scanning... +do_pci_scan_bridge for PCI: 00:0d.0 +PCI: pci_scan_bus for bus 04 +PCI: Static device PCI: 04:00.0 not found, disabling it. +PCI: 00:0e.0 scanning... +do_pci_scan_bridge for PCI: 00:0e.0 +PCI: pci_scan_bus for bus 05 +PCI: 00:19.0 scanning... +DOMAIN: 0000 passpw: enabled +DOMAIN: 0000 passpw: enabled +root_dev_scan_bus for Root Device done +done +BS: BS_DEV_ENUMERATE times (us): entry 0 run 598152 exit 0 +found VGA at PCI: 01:04.0 +Setting up VGA for PCI: 01:04.0 +Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:09.0 +Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +APIC: 01 missing read_resources +APIC: 02 missing read_resources +APIC: 03 missing read_resources +APIC: 04 missing read_resources +APIC: 05 missing read_resources +APIC: 06 missing read_resources +APIC: 07 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +PCI: 00:18.0 read_resources bus 0 link: 1 +PCI: 00:01.0 read_resources bus 0 link: 0 +PCI: 00:01.0 read_resources bus 0 link: 0 done +PCI: 00:01.1 read_resources bus 1 link: 0 +I2C: 01:50 missing read_resources +I2C: 01:51 missing read_resources +I2C: 01:52 missing read_resources +I2C: 01:53 missing read_resources +I2C: 01:54 missing read_resources +I2C: 01:55 missing read_resources +I2C: 01:56 missing read_resources +I2C: 01:57 missing read_resources +PCI: 00:01.1 read_resources bus 1 link: 0 done +PCI: 00:01.1 read_resources bus 2 link: 1 +PCI: 00:01.1 read_resources bus 2 link: 1 done +PCI: 00:09.0 read_resources bus 1 link: 0 +PCI: 00:09.0 read_resources bus 1 link: 0 done +PCI: 00:0b.0 read_resources bus 2 link: 0 +PCI: 00:0b.0 read_resources bus 2 link: 0 done +PCI: 00:0c.0 read_resources bus 3 link: 0 +PCI: 00:0c.0 read_resources bus 3 link: 0 done +PCI: 00:0d.0 read_resources bus 4 link: 0 +PCI: 00:0d.0 read_resources bus 4 link: 0 done +PCI: 00:0e.0 read_resources bus 5 link: 0 +PCI: 00:0e.0 read_resources bus 5 link: 0 done +PCI: 00:18.0 read_resources bus 0 link: 1 done +PCI: 00:18.0 read_resources bus 0 link: 0 +PCI: 00:18.0 read_resources bus 0 link: 0 done +PCI: 00:18.0 read_resources bus 0 link: 2 +PCI: 00:18.0 read_resources bus 0 link: 2 done +PCI: 00:18.0 read_resources bus 0 link: 3 +PCI: 00:18.0 read_resources bus 0 link: 3 done +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +PCI: 00:18.4 read_resources bus 0 link: 0 +PCI: 00:18.4 read_resources bus 0 link: 0 done +PCI: 00:18.4 read_resources bus 0 link: 1 +PCI: 00:18.4 read_resources bus 0 link: 1 done +PCI: 00:18.4 read_resources bus 0 link: 2 +PCI: 00:18.4 read_resources bus 0 link: 2 done +PCI: 00:18.4 read_resources bus 0 link: 3 +PCI: 00:18.4 read_resources bus 0 link: 3 done +PCI: 00:19.0 read_resources bus 0 link: 0 +PCI: 00:19.0 read_resources bus 0 link: 0 done +PCI: 00:19.0 read_resources bus 0 link: 1 +PCI: 00:19.0 read_resources bus 0 link: 1 done +PCI: 00:19.0 read_resources bus 0 link: 2 +PCI: 00:19.0 read_resources bus 0 link: 2 done +PCI: 00:19.0 read_resources bus 0 link: 3 +PCI: 00:19.0 read_resources bus 0 link: 3 done +PCI: 00:19.4 read_resources bus 0 link: 0 +PCI: 00:19.4 read_resources bus 0 link: 0 done +PCI: 00:19.4 read_resources bus 0 link: 1 +PCI: 00:19.4 read_resources bus 0 link: 1 done +PCI: 00:19.4 read_resources bus 0 link: 2 +PCI: 00:19.4 read_resources bus 0 link: 2 done +PCI: 00:19.4 read_resources bus 0 link: 3 +PCI: 00:19.4 read_resources bus 0 link: 3 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: 01 + APIC: 02 + APIC: 03 + APIC: 04 + APIC: 05 + APIC: 06 + APIC: 07 + DOMAIN: 0000 child on link 0 PCI: 00:18.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 + DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 + PCI: 00:18.0 child on link 0 PCI: 00:00.0 + PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d8 + PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110b8 + PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110b0 + PCI: 00:00.0 + PCI: 00:01.0 child on link 0 PNP: 002e.0 + PCI: 00:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10 + PCI: 00:01.0 resource base fec00000 size 1000 align 12 gran 12 limit ffffffff flags c0000200 index 14 + PCI: 00:01.0 resource base fed00000 size 1000 align 12 gran 12 limit ffffffff flags c0000200 index 44 + PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 60 + PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 64 + PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 68 + PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PNP: 002e.0 + PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.3 + PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000500 index f1 + PNP: 002e.5 + PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 + PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 + PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 + PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.7 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 + PNP: 002e.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.8 + PNP: 002e.9 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 30 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f1 + PNP: 002e.a + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.b + PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60 + PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PCI: 00:01.1 child on link 0 I2C: 01:50 + PCI: 00:01.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 10 + PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 + PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24 + I2C: 01:50 + I2C: 01:51 + I2C: 01:52 + I2C: 01:53 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:2f + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:04.0 + PCI: 00:04.1 + PCI: 00:06.0 + PCI: 00:06.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:07.0 + PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:07.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:07.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 00:08.0 + PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:08.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 00:09.0 child on link 0 PCI: 01:04.0 + PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 + PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 01:04.0 + PCI: 01:04.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 + PCI: 01:04.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 14 + PCI: 01:04.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18 + PCI: 00:0a.0 + PCI: 00:0b.0 child on link 0 PCI: 02:00.0 + PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:0c.0 child on link 0 PCI: 03:00.0 + PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 03:00.0 + PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:0d.0 child on link 0 PCI: 04:00.0 + PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 04:00.0 + PCI: 00:0e.0 + PCI: 00:0e.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:0f.0 + PCI: 00:18.1 + PCI: 00:18.2 + PCI: 00:18.3 + PCI: 00:18.4 + PCI: 00:19.0 + PCI: 00:19.1 + PCI: 00:19.2 + PCI: 00:19.3 + PCI: 00:19.4 +DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 01:04.0 18 * [0x0 - 0x7f] io +PCI: 00:09.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:0e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:09.0 1c * [0x0 - 0xfff] io +PCI: 00:01.0 60 * [0x1000 - 0x10ff] io +PCI: 00:01.0 64 * [0x1400 - 0x14ff] io +PCI: 00:01.0 68 * [0x1800 - 0x18ff] io +PCI: 00:01.0 10 * [0x1c00 - 0x1c7f] io +PCI: 00:01.1 20 * [0x1c80 - 0x1cbf] io +PCI: 00:01.1 24 * [0x1cc0 - 0x1cff] io +PCI: 00:01.1 10 * [0x2000 - 0x201f] io +PCI: 00:06.0 20 * [0x2020 - 0x202f] io +PCI: 00:07.0 20 * [0x2030 - 0x203f] io +PCI: 00:08.0 20 * [0x2040 - 0x204f] io +PCI: 00:07.0 10 * [0x2050 - 0x2057] io +PCI: 00:07.0 18 * [0x2058 - 0x205f] io +PCI: 00:08.0 10 * [0x2060 - 0x2067] io +PCI: 00:08.0 18 * [0x2068 - 0x206f] io +PCI: 00:07.0 14 * [0x2070 - 0x2073] io +PCI: 00:07.0 1c * [0x2074 - 0x2077] io +PCI: 00:08.0 14 * [0x2078 - 0x207b] io +PCI: 00:08.0 1c * [0x207c - 0x207f] io +PCI: 00:18.0 io: base: 2080 size: 3000 align: 12 gran: 12 limit: ffff done +PCI: 00:18.0 110d8 * [0x0 - 0x2fff] io +DOMAIN: 0000 io: base: 3000 size: 3000 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff +PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:04.0 10 * [0x0 - 0x3ffffff] prefmem +PCI: 00:09.0 prefmem: base: 4000000 size: 4000000 align: 26 gran: 20 limit: ffffffff done +PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:0e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:09.0 24 * [0x0 - 0x3ffffff] prefmem +PCI: 00:18.0 prefmem: base: 4000000 size: 4000000 align: 26 gran: 20 limit: ffffffff done +PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff +PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:04.0 14 * [0x0 - 0x3ffff] mem +PCI: 00:09.0 mem: base: 40000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 02:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:0b.0 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 03:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:0c.0 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:0e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:09.0 20 * [0x0 - 0xfffff] mem +PCI: 00:0b.0 20 * [0x100000 - 0x1fffff] mem +PCI: 00:0c.0 20 * [0x200000 - 0x2fffff] mem +PCI: 00:02.0 10 * [0x300000 - 0x300fff] mem +PCI: 00:07.0 24 * [0x301000 - 0x301fff] mem +PCI: 00:08.0 24 * [0x302000 - 0x302fff] mem +PCI: 00:02.1 10 * [0x303000 - 0x3030ff] mem +PCI: 00:18.0 mem: base: 303100 size: 400000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:18.0 110b8 * [0x0 - 0x3ffffff] prefmem +PCI: 00:18.0 110b0 * [0x4000000 - 0x43fffff] mem +DOMAIN: 0000 mem: base: 4400000 size: 4400000 align: 26 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed) +constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed) +constrain_resources: PCI: 00:01.0 14 base fec00000 limit fec00fff mem (fixed) +constrain_resources: PCI: 00:01.0 10000000 base 00000000 limit 00000fff io (fixed) +avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 base f8000000 limit febfffff +Setting resources... +DOMAIN: 0000 io: base:1000 size:3000 align:12 gran:0 limit:ffff +PCI: 00:18.0 110d8 * [0x1000 - 0x3fff] io +DOMAIN: 0000 io: next_base: 4000 size: 3000 align: 12 gran: 0 done +PCI: 00:18.0 io: base:1000 size:3000 align:12 gran:12 limit:3fff +PCI: 00:09.0 1c * [0x1000 - 0x1fff] io +PCI: 00:01.0 60 * [0x2000 - 0x20ff] io +PCI: 00:01.0 64 * [0x2400 - 0x24ff] io +PCI: 00:01.0 68 * [0x2800 - 0x28ff] io +PCI: 00:01.0 10 * [0x2c00 - 0x2c7f] io +PCI: 00:01.1 20 * [0x2c80 - 0x2cbf] io +PCI: 00:01.1 24 * [0x2cc0 - 0x2cff] io +PCI: 00:01.1 10 * [0x3000 - 0x301f] io +PCI: 00:06.0 20 * [0x3020 - 0x302f] io +PCI: 00:07.0 20 * [0x3030 - 0x303f] io +PCI: 00:08.0 20 * [0x3040 - 0x304f] io +PCI: 00:07.0 10 * [0x3050 - 0x3057] io +PCI: 00:07.0 18 * [0x3058 - 0x305f] io +PCI: 00:08.0 10 * [0x3060 - 0x3067] io +PCI: 00:08.0 18 * [0x3068 - 0x306f] io +PCI: 00:07.0 14 * [0x3070 - 0x3073] io +PCI: 00:07.0 1c * [0x3074 - 0x3077] io +PCI: 00:08.0 14 * [0x3078 - 0x307b] io +PCI: 00:08.0 1c * [0x307c - 0x307f] io +PCI: 00:18.0 io: next_base: 3080 size: 3000 align: 12 gran: 12 done +PCI: 00:09.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff +PCI: 01:04.0 18 * [0x1000 - 0x107f] io +PCI: 00:09.0 io: next_base: 1080 size: 1000 align: 12 gran: 12 done +PCI: 00:0b.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0b.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +PCI: 00:0c.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0c.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +PCI: 00:0d.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0d.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +PCI: 00:0e.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0e.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +DOMAIN: 0000 mem: base:f8000000 size:4400000 align:26 gran:0 limit:febfffff +PCI: 00:18.0 110b8 * [0xf8000000 - 0xfbffffff] prefmem +PCI: 00:18.0 110b0 * [0xfc000000 - 0xfc3fffff] mem +DOMAIN: 0000 mem: next_base: fc400000 size: 4400000 align: 26 gran: 0 done +PCI: 00:18.0 prefmem: base:f8000000 size:4000000 align:26 gran:20 limit:fbffffff +PCI: 00:09.0 24 * [0xf8000000 - 0xfbffffff] prefmem +PCI: 00:18.0 prefmem: next_base: fc000000 size: 4000000 align: 26 gran: 20 done +PCI: 00:09.0 prefmem: base:f8000000 size:4000000 align:26 gran:20 limit:fbffffff +PCI: 01:04.0 10 * [0xf8000000 - 0xfbffffff] prefmem +PCI: 00:09.0 prefmem: next_base: fc000000 size: 4000000 align: 26 gran: 20 done +PCI: 00:0b.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0b.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:0c.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0c.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:0d.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0d.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:0e.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0e.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:18.0 mem: base:fc000000 size:400000 align:20 gran:20 limit:fc3fffff +PCI: 00:09.0 20 * [0xfc000000 - 0xfc0fffff] mem +PCI: 00:0b.0 20 * [0xfc100000 - 0xfc1fffff] mem +PCI: 00:0c.0 20 * [0xfc200000 - 0xfc2fffff] mem +PCI: 00:02.0 10 * [0xfc300000 - 0xfc300fff] mem +PCI: 00:07.0 24 * [0xfc301000 - 0xfc301fff] mem +PCI: 00:08.0 24 * [0xfc302000 - 0xfc302fff] mem +PCI: 00:02.1 10 * [0xfc303000 - 0xfc3030ff] mem +PCI: 00:18.0 mem: next_base: fc303100 size: 400000 align: 20 gran: 20 done +PCI: 00:09.0 mem: base:fc000000 size:100000 align:20 gran:20 limit:fc0fffff +PCI: 01:04.0 14 * [0xfc000000 - 0xfc03ffff] mem +PCI: 00:09.0 mem: next_base: fc040000 size: 100000 align: 20 gran: 20 done +PCI: 00:0b.0 mem: base:fc100000 size:100000 align:20 gran:20 limit:fc1fffff +PCI: 02:00.0 10 * [0xfc100000 - 0xfc10ffff] mem +PCI: 00:0b.0 mem: next_base: fc110000 size: 100000 align: 20 gran: 20 done +PCI: 00:0c.0 mem: base:fc200000 size:100000 align:20 gran:20 limit:fc2fffff +PCI: 03:00.0 10 * [0xfc200000 - 0xfc20ffff] mem +PCI: 00:0c.0 mem: next_base: fc210000 size: 100000 align: 20 gran: 20 done +PCI: 00:0d.0 mem: base:fc3fffff size:0 align:20 gran:20 limit:fc3fffff +PCI: 00:0d.0 mem: next_base: fc3fffff size: 0 align: 20 gran: 20 done +PCI: 00:0e.0 mem: base:fc3fffff size:0 align:20 gran:20 limit:fc3fffff +PCI: 00:0e.0 mem: next_base: fc3fffff size: 0 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +0: mmio_basek=00300000, basek=00400000, limitk=00500000 +1: mmio_basek=00300000, basek=00500000, limitk=00600000 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device +PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io +PCI: 00:18.0 110b8 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x14 prefmem +PCI: 00:18.0 110b0 <- [0x00fc000000 - 0x00fc3fffff] size 0x00400000 gran 0x14 mem +PCI: 00:18.0 assign_resources, bus 0 link: 1 +PCI: 00:01.0 10 <- [0x0000002c00 - 0x0000002c7f] size 0x00000080 gran 0x07 io +PCI: 00:01.0 60 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io +PCI: 00:01.0 64 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io +PCI: 00:01.0 68 <- [0x0000002800 - 0x00000028ff] size 0x00000100 gran 0x08 io +PCI: 00:01.0 assign_resources, bus 0 link: 0 +PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io +PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq +PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq +PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io +PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq +PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io +PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq +PNP: 002e.3 f1 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 io +PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io +PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io +PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq +PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq +ERROR: PNP: 002e.5 f0 irq size: 0x0000000001 not assigned +ERROR: PNP: 002e.9 30 irq size: 0x0000000001 not assigned +ERROR: PNP: 002e.9 f0 irq size: 0x0000000001 not assigned +ERROR: PNP: 002e.9 f1 irq size: 0x0000000001 not assigned +PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io +PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq +PCI: 00:01.0 assign_resources, bus 0 link: 0 +PCI: 00:01.0 14 <- [0x00fec00000 - 0x00fec00fff] size 0x00001000 gran 0x0c mem +PCI: 00:01.0 44 <- [0x00fed00000 - 0x00fed00fff] size 0x00001000 gran 0x0c mem +PCI: 00:01.1 10 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io +PCI: 00:01.1 20 <- [0x0000002c80 - 0x0000002cbf] size 0x00000040 gran 0x06 io +PCI: 00:01.1 24 <- [0x0000002cc0 - 0x0000002cff] size 0x00000040 gran 0x06 io +PCI: 00:01.1 assign_resources, bus 1 link: 0 +PCI: 00:01.1 assign_resources, bus 1 link: 0 +PCI: 00:02.0 10 <- [0x00fc300000 - 0x00fc300fff] size 0x00001000 gran 0x0c mem +PCI: 00:02.1 10 <- [0x00fc303000 - 0x00fc3030ff] size 0x00000100 gran 0x08 mem +PCI: 00:06.0 20 <- [0x0000003020 - 0x000000302f] size 0x00000010 gran 0x04 io +PCI: 00:07.0 10 <- [0x0000003050 - 0x0000003057] size 0x00000008 gran 0x03 io +PCI: 00:07.0 14 <- [0x0000003070 - 0x0000003073] size 0x00000004 gran 0x02 io +PCI: 00:07.0 18 <- [0x0000003058 - 0x000000305f] size 0x00000008 gran 0x03 io +PCI: 00:07.0 1c <- [0x0000003074 - 0x0000003077] size 0x00000004 gran 0x02 io +PCI: 00:07.0 20 <- [0x0000003030 - 0x000000303f] size 0x00000010 gran 0x04 io +PCI: 00:07.0 24 <- [0x00fc301000 - 0x00fc301fff] size 0x00001000 gran 0x0c mem +PCI: 00:08.0 10 <- [0x0000003060 - 0x0000003067] size 0x00000008 gran 0x03 io +PCI: 00:08.0 14 <- [0x0000003078 - 0x000000307b] size 0x00000004 gran 0x02 io +PCI: 00:08.0 18 <- [0x0000003068 - 0x000000306f] size 0x00000008 gran 0x03 io +PCI: 00:08.0 1c <- [0x000000307c - 0x000000307f] size 0x00000004 gran 0x02 io +PCI: 00:08.0 20 <- [0x0000003040 - 0x000000304f] size 0x00000010 gran 0x04 io +PCI: 00:08.0 24 <- [0x00fc302000 - 0x00fc302fff] size 0x00001000 gran 0x0c mem +PCI: 00:09.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:09.0 24 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x14 bus 01 prefmem +PCI: 00:09.0 20 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 bus 01 mem +PCI: 00:09.0 assign_resources, bus 1 link: 0 +PCI: 01:04.0 10 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a prefmem +PCI: 01:04.0 14 <- [0x00fc000000 - 0x00fc03ffff] size 0x00040000 gran 0x12 mem +PCI: 01:04.0 18 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io +PCI: 00:09.0 assign_resources, bus 1 link: 0 +PCI: 00:0b.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:0b.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:0b.0 20 <- [0x00fc100000 - 0x00fc1fffff] size 0x00100000 gran 0x14 bus 02 mem +PCI: 00:0b.0 assign_resources, bus 2 link: 0 +PCI: 02:00.0 10 <- [0x00fc100000 - 0x00fc10ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:0b.0 assign_resources, bus 2 link: 0 +PCI: 00:0c.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:0c.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:0c.0 20 <- [0x00fc200000 - 0x00fc2fffff] size 0x00100000 gran 0x14 bus 03 mem +PCI: 00:0c.0 assign_resources, bus 3 link: 0 +PCI: 03:00.0 10 <- [0x00fc200000 - 0x00fc20ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:0c.0 assign_resources, bus 3 link: 0 +PCI: 00:0d.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 04 io +PCI: 00:0d.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 04 prefmem +PCI: 00:0d.0 20 <- [0x00fc3fffff - 0x00fc3ffffe] size 0x00000000 gran 0x14 bus 04 mem +PCI: 00:0d.0 assign_resources, bus 4 link: 0 +PCI: 00:0d.0 assign_resources, bus 4 link: 0 +PCI: 00:0e.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 05 io +PCI: 00:0e.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 05 prefmem +PCI: 00:0e.0 20 <- [0x00fc3fffff - 0x00fc3ffffe] size 0x00000000 gran 0x14 bus 05 mem +PCI: 00:18.0 assign_resources, bus 0 link: 1 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: 01 + APIC: 02 + APIC: 03 + APIC: 04 + APIC: 05 + APIC: 06 + APIC: 07 + DOMAIN: 0000 child on link 0 PCI: 00:18.0 + DOMAIN: 0000 resource base 1000 size 3000 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base f8000000 size 4400000 align 26 gran 0 limit febfffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 + DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 + DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 + DOMAIN: 0000 resource base 100000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 30 + DOMAIN: 0000 resource base 140000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 41 + PCI: 00:18.0 child on link 0 PCI: 00:00.0 + PCI: 00:18.0 resource base 1000 size 3000 align 12 gran 12 limit 3fff flags 60080100 index 110d8 + PCI: 00:18.0 resource base f8000000 size 4000000 align 26 gran 20 limit fbffffff flags 60081200 index 110b8 + PCI: 00:18.0 resource base fc000000 size 400000 align 20 gran 20 limit fc3fffff flags 60080200 index 110b0 + PCI: 00:00.0 + PCI: 00:01.0 child on link 0 PNP: 002e.0 + PCI: 00:01.0 resource base 2c00 size 80 align 7 gran 7 limit 2c7f flags 60000100 index 10 + PCI: 00:01.0 resource base fec00000 size 1000 align 12 gran 12 limit ffffffff flags e0000200 index 14 + PCI: 00:01.0 resource base fed00000 size 1000 align 12 gran 12 limit ffffffff flags e0000200 index 44 + PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 60 + PCI: 00:01.0 resource base 2400 size 100 align 8 gran 8 limit 24ff flags 60000100 index 64 + PCI: 00:01.0 resource base 2800 size 100 align 8 gran 8 limit 28ff flags 60000100 index 68 + PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PNP: 002e.0 + PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.3 + PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000500 index f1 + PNP: 002e.5 + PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 + PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 + PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 + PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.7 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 + PNP: 002e.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.8 + PNP: 002e.9 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 30 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f1 + PNP: 002e.a + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.b + PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags e0000100 index 60 + PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PCI: 00:01.1 child on link 0 I2C: 01:50 + PCI: 00:01.1 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 10 + PCI: 00:01.1 resource base 2c80 size 40 align 6 gran 6 limit 2cbf flags 60000100 index 20 + PCI: 00:01.1 resource base 2cc0 size 40 align 6 gran 6 limit 2cff flags 60000100 index 24 + I2C: 01:50 + I2C: 01:51 + I2C: 01:52 + I2C: 01:53 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:2f + PCI: 00:02.0 + PCI: 00:02.0 resource base fc300000 size 1000 align 12 gran 12 limit fc300fff flags 60000200 index 10 + PCI: 00:02.1 + PCI: 00:02.1 resource base fc303000 size 100 align 8 gran 8 limit fc3030ff flags 60000200 index 10 + PCI: 00:04.0 + PCI: 00:04.1 + PCI: 00:06.0 + PCI: 00:06.0 resource base 3020 size 10 align 4 gran 4 limit 302f flags 60000100 index 20 + PCI: 00:07.0 + PCI: 00:07.0 resource base 3050 size 8 align 3 gran 3 limit 3057 flags 60000100 index 10 + PCI: 00:07.0 resource base 3070 size 4 align 2 gran 2 limit 3073 flags 60000100 index 14 + PCI: 00:07.0 resource base 3058 size 8 align 3 gran 3 limit 305f flags 60000100 index 18 + PCI: 00:07.0 resource base 3074 size 4 align 2 gran 2 limit 3077 flags 60000100 index 1c + PCI: 00:07.0 resource base 3030 size 10 align 4 gran 4 limit 303f flags 60000100 index 20 + PCI: 00:07.0 resource base fc301000 size 1000 align 12 gran 12 limit fc301fff flags 60000200 index 24 + PCI: 00:08.0 + PCI: 00:08.0 resource base 3060 size 8 align 3 gran 3 limit 3067 flags 60000100 index 10 + PCI: 00:08.0 resource base 3078 size 4 align 2 gran 2 limit 307b flags 60000100 index 14 + PCI: 00:08.0 resource base 3068 size 8 align 3 gran 3 limit 306f flags 60000100 index 18 + PCI: 00:08.0 resource base 307c size 4 align 2 gran 2 limit 307f flags 60000100 index 1c + PCI: 00:08.0 resource base 3040 size 10 align 4 gran 4 limit 304f flags 60000100 index 20 + PCI: 00:08.0 resource base fc302000 size 1000 align 12 gran 12 limit fc302fff flags 60000200 index 24 + PCI: 00:09.0 child on link 0 PCI: 01:04.0 + PCI: 00:09.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c + PCI: 00:09.0 resource base f8000000 size 4000000 align 26 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:09.0 resource base fc000000 size 100000 align 20 gran 20 limit fc0fffff flags 60080202 index 20 + PCI: 01:04.0 + PCI: 01:04.0 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60001200 index 10 + PCI: 01:04.0 resource base fc000000 size 40000 align 18 gran 18 limit fc03ffff flags 60000200 index 14 + PCI: 01:04.0 resource base 1000 size 80 align 7 gran 7 limit 107f flags 60000100 index 18 + PCI: 01:04.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3 + PCI: 00:0a.0 + PCI: 00:0b.0 child on link 0 PCI: 02:00.0 + PCI: 00:0b.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0b.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0b.0 resource base fc100000 size 100000 align 20 gran 20 limit fc1fffff flags 60080202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base fc100000 size 10000 align 16 gran 16 limit fc10ffff flags 60000201 index 10 + PCI: 00:0c.0 child on link 0 PCI: 03:00.0 + PCI: 00:0c.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0c.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0c.0 resource base fc200000 size 100000 align 20 gran 20 limit fc2fffff flags 60080202 index 20 + PCI: 03:00.0 + PCI: 03:00.0 resource base fc200000 size 10000 align 16 gran 16 limit fc20ffff flags 60000201 index 10 + PCI: 00:0d.0 child on link 0 PCI: 04:00.0 + PCI: 00:0d.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0d.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0d.0 resource base fc3fffff size 0 align 20 gran 20 limit fc3fffff flags 60080202 index 20 + PCI: 04:00.0 + PCI: 00:0e.0 + PCI: 00:0e.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0e.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0e.0 resource base fc3fffff size 0 align 20 gran 20 limit fc3fffff flags 60080202 index 20 + PCI: 00:0f.0 + PCI: 00:18.1 + PCI: 00:18.2 + PCI: 00:18.3 + PCI: 00:18.4 + PCI: 00:19.0 + PCI: 00:19.1 + PCI: 00:19.2 + PCI: 00:19.3 + PCI: 00:19.4 +Done allocating resources. +BS: BS_DEV_RESOURCES times (us): entry 0 run 3267943 exit 0 +Enabling resources... +PCI: 00:18.0 cmd <- 00 +PCI: 00:18.1 subsystem <- 1043/8162 +PCI: 00:18.1 cmd <- 00 +PCI: 00:18.2 subsystem <- 1043/8162 +PCI: 00:18.2 cmd <- 00 +PCI: 00:18.3 cmd <- 00 +PCI: 00:18.4 subsystem <- 1043/8162 +PCI: 00:18.4 cmd <- 00 +PCI: 00:19.0 cmd <- 00 +PCI: 00:19.1 subsystem <- 1043/8162 +PCI: 00:19.1 cmd <- 00 +PCI: 00:19.2 subsystem <- 1043/8162 +PCI: 00:19.2 cmd <- 00 +PCI: 00:19.3 cmd <- 00 +PCI: 00:19.4 subsystem <- 1043/8162 +PCI: 00:19.4 cmd <- 00 +PCI: 00:00.0 subsystem <- 1043/8162 +PCI: 00:00.0 cmd <- 06 +PCI: 00:01.0 subsystem <- 1043/8162 +PCI: 00:01.0 cmd <- 0f +ck804 lpc decode:PNP: 002e.0, base=0x000003f0, end=0x000003f7 +ck804 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff +ck804 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff +ck804 lpc decode:PNP: 002e.3, base=0x00000004, end=0x00000004 +ck804 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060 +ck804 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064 +ck804 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000297 +PCI: 00:01.1 subsystem <- 1043/8162 +PCI: 00:01.1 cmd <- 01 +PCI: 00:02.0 subsystem <- 1043/8162 +PCI: 00:02.0 cmd <- 02 +PCI: 00:02.1 subsystem <- 1043/8162 +PCI: 00:02.1 cmd <- 02 +PCI: 00:06.0 subsystem <- 1043/8162 +PCI: 00:06.0 cmd <- 01 +PCI: 00:07.0 subsystem <- 1043/8162 +PCI: 00:07.0 cmd <- 03 +PCI: 00:08.0 subsystem <- 1043/8162 +PCI: 00:08.0 cmd <- 03 +PCI: 00:09.0 bridge ctrl <- 000b +PCI: 00:09.0 cmd <- 07 +PCI: 00:0b.0 bridge ctrl <- 0003 +PCI: 00:0b.0 cmd <- 06 +PCI: 00:0c.0 bridge ctrl <- 0003 +PCI: 00:0c.0 cmd <- 06 +PCI: 00:0d.0 bridge ctrl <- 0003 +PCI: 00:0d.0 cmd <- 00 +PCI: 00:0e.0 bridge ctrl <- 0003 +PCI: 00:0e.0 cmd <- 00 +PCI: 01:04.0 cmd <- 03 +PCI: 02:00.0 subsystem <- 1043/8162 +PCI: 02:00.0 cmd <- 02 +PCI: 03:00.0 subsystem <- 1043/8162 +PCI: 03:00.0 cmd <- 02 +done. +BS: BS_DEV_ENABLE times (us): entry 0 run 162779 exit 0 +Initializing devices... +Root Device init ... +Root Device init finished in 1931 usecs +CPU_CLUSTER: 0 init ... +start_eip=0x00001000, code_size=0x00000031 +CPU1: stack_base 00138000, stack_end 00138ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Initializing CPU #1 +Startup point 1. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +Sending STARTUP #2 to 1. +After apic_write. +CPU: family 10, model 02, stepping 01 +Startup point 1. +Waiting for send to finish... ++nodeid = 00, coreid = 01 +After Startup. +CPU2: stack_base 00137000, stack_end 00137ff8 +Enabling cache +Asserting INIT. +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Waiting for send to finish... ++MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6 +0x00000000c0000000 - 0x00000000f8000000 size 0x38000000 type 0 +0x00000000f8000000 - 0x00000000fc000000 size 0x04000000 type 1 +0x00000000fc000000 - 0x0000000100000000 size 0x04000000 type 0 +0x0000000100000000 - 0x0000000180000000 size 0x80000000 type 6 +Deasserting INIT. +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +Waiting for send to finish... ++MTRR: default type WB/UC MTRR counts: 5/3. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 +MTRR: 2 base 0x00000000f8000000 mask 0x0000fffffc000000 type 1 +#startup loops: 2. +Sending STARTUP #1 to 2. +After apic_write. + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Startup point 1. +Waiting for send to finish... ++Setting up local apic...Sending STARTUP #2 to 2. +After apic_write. + apic_id: 0x01 done. +Startup point 1. +Waiting for send to finish... ++CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +Initializing CPU #2 +After Startup. +siblings = 03, CPU3: stack_base 00136000, stack_end 00136ff8 +CPU #1 initialized +Asserting INIT. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +Deasserting INIT. +Waiting for send to finish... ++CPU: family 10, model 02, stepping 01 +#startup loops: 2. +Sending STARTUP #1 to 3. +After apic_write. +nodeid = 00, coreid = 02 +Startup point 1. +Waiting for send to finish... ++Initializing CPU #3 +Sending STARTUP #2 to 3. +After apic_write. +Enabling cache +Startup point 1. +Waiting for send to finish... ++CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +After Startup. +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU4: stack_base 00135000, stack_end 00135ff8 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Asserting INIT. +Setting up local apic...Waiting for send to finish... ++ apic_id: 0x02 done. +Deasserting INIT. +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +Waiting for send to finish... ++siblings = 03, #startup loops: 2. +Sending STARTUP #1 to 4. +After apic_write. +CPU #2 initialized +Startup point 1. +Waiting for send to finish... ++Initializing CPU #4 +Sending STARTUP #2 to 4. +After apic_write. +CPU: vendor AMD device 100f21 +Startup point 1. +Waiting for send to finish... ++CPU: family 10, model 02, stepping 01 +After Startup. +CPU5: stack_base 00134000, stack_end 00134ff8 +nodeid = 00, coreid = 03 +Asserting INIT. +Waiting for send to finish... ++Enabling cache +Deasserting INIT. +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Waiting for send to finish... ++MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +#startup loops: 2. +Sending STARTUP #1 to 5. +After apic_write. + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Startup point 1. +Waiting for send to finish... ++Setting up local apic...Sending STARTUP #2 to 5. +After apic_write. + apic_id: 0x03 done. +Startup point 1. +Waiting for send to finish... ++CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +After Startup. +siblings = 03, CPU6: stack_base 00133000, stack_end 00133ff8 +CPU #3 initialized +Asserting INIT. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +Deasserting INIT. +Waiting for send to finish... ++Initializing CPU #5 +#startup loops: 2. +Sending STARTUP #1 to 6. +After apic_write. +CPU: family 10, model 02, stepping 01 +Startup point 1. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +Sending STARTUP #2 to 6. +After apic_write. +Initializing CPU #6 +Startup point 1. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +After Startup. +CPU7: stack_base 00132000, stack_end 00132ff8 +nodeid = 01, coreid = 00 +Asserting INIT. +Waiting for send to finish... ++CPU: family 10, model 02, stepping 01 +Deasserting INIT. +Waiting for send to finish... ++nodeid = 01, coreid = 01 +#startup loops: 2. +Sending STARTUP #1 to 7. +After apic_write. +CPU: family 10, model 02, stepping 01 +Startup point 1. +Waiting for send to finish... ++Enabling cache +Sending STARTUP #2 to 7. +After apic_write. +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Startup point 1. +Waiting for send to finish... ++MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +After Startup. +Initializing CPU #0 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +CPU: vendor AMD device 100f21 +CPU: family 10, model 02, stepping 01 +Setting up local apic...nodeid = 00, coreid = 00 + apic_id: 0x05 done. +Enabling cache +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +siblings = 03, MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU #5 initialized + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Enabling cache +Setting up local apic...CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB + apic_id: 0x00 done. +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +siblings = 03, Setting up local apic...CPU #0 initialized + apic_id: 0x04 done. +Waiting for 3 CPUS to stop +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +siblings = 03, nodeid = 01, coreid = 02 +CPU #4 initialized +Enabling cache +Waiting for 2 CPUS to stop +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Initializing CPU #7 +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU: vendor AMD device 100f21 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +CPU: family 10, model 02, stepping 01 +Setting up local apic...nodeid = 01, coreid = 03 + apic_id: 0x06 done. +Enabling cache +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +siblings = 03, MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU #6 initialized + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Waiting for 1 CPUS to stop +Setting up local apic... apic_id: 0x07 done. +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +siblings = 03, CPU #7 initialized +All AP CPUs stopped (14884 loops) +CPU1: stack: 00138000 - 00139000, lowest used address 00138c8c, stack used: 884 bytes +CPU2: stack: 00137000 - 00138000, lowest used address 00137cd4, stack used: 812 bytes +CPU3: stack: 00136000 - 00137000, lowest used address 00136cd4, stack used: 812 bytes +CPU4: stack: 00135000 - 00136000, lowest used address 00135cd4, stack used: 812 bytes +CPU5: stack: 00134000 - 00135000, lowest used address 00134cd4, stack used: 812 bytes +CPU6: stack: 00133000 - 00134000, lowest used address 00133cd4, stack used: 812 bytes +CPU7: stack: 00132000 - 00133000, lowest used address 00132cd4, stack used: 812 bytes +CPU_CLUSTER: 0 init finished in 995136 usecs +PCI: 00:18.0 init ... +PCI: 00:18.0 init finished in 2030 usecs +PCI: 00:18.1 init ... +PCI: 00:18.1 init finished in 2027 usecs +PCI: 00:18.2 init ... +PCI: 00:18.2 init finished in 2018 usecs +PCI: 00:18.3 init ... +NB: Function 3 Misc Control.. done. +PCI: 00:18.3 init finished in 5293 usecs +PCI: 00:18.4 init ... +PCI: 00:18.4 init finished in 2018 usecs +PCI: 00:19.0 init ... +PCI: 00:19.0 init finished in 2019 usecs +PCI: 00:19.1 init ... +PCI: 00:19.1 init finished in 2018 usecs +PCI: 00:19.2 init ... +PCI: 00:19.2 init finished in 2017 usecs +PCI: 00:19.3 init ... +NB: Function 3 Misc Control.. done. +PCI: 00:19.3 init finished in 5268 usecs +PCI: 00:19.4 init ... +PCI: 00:19.4 init finished in 2017 usecs +PCI: 00:00.0 init ... +PCI: 00:00.0 init finished in 2028 usecs +PCI: 00:01.0 init ... +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: Dumping registers + reg 0x0000: 0x00000000 + reg 0x0001: 0x00170011 + reg 0x0002: 0x00000000 +IOAPIC: 24 interrupts +IOAPIC: Enabling interrupts on FSB +IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 +IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 +IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 +lpc_init: pm_base = 2000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +set power on after power fail +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +RTC Init +PCI: 00:01.0 init finished in 164685 usecs +PCI: 00:02.0 init ... +PCI: 00:02.0 init finished in 2026 usecs +PCI: 00:02.1 init ... +PCI: 00:02.1 init finished in 2018 usecs +PCI: 00:06.0 init ... +IDE1 IDE0 +PCI: 00:06.0 init finished in 3105 usecs +PCI: 00:07.0 init ... +SATA S SATA P +PCI: 00:07.0 init finished in 3534 usecs +PCI: 00:08.0 init ... +SATA S SATA P +PCI: 00:08.0 init finished in 3517 usecs +PCI: 00:09.0 init ... +PCI DOMAIN mem base = 0x00f8000000 +[0x50] <-- 0xf8000000 +PCI: 00:09.0 init finished in 7192 usecs +PCI: 00:0b.0 init ... +PCI: 00:0b.0 init finished in 2017 usecs +PCI: 00:0c.0 init ... +PCI: 00:0c.0 init finished in 2019 usecs +PCI: 00:0d.0 init ... +PCI: 00:0d.0 init finished in 2019 usecs +PCI: 00:0e.0 init ... +PCI: 00:0e.0 init finished in 2018 usecs +PNP: 002e.0 init ... +PNP: 002e.0 init finished in 1939 usecs +PNP: 002e.2 init ... +PNP: 002e.2 init finished in 1930 usecs +PNP: 002e.3 init ... +PNP: 002e.3 init finished in 1931 usecs +PNP: 002e.5 init ... +Keyboard init... +PNP: 002e.5 init finished in 352042 usecs +PNP: 002e.9 init ... +PNP: 002e.9 init finished in 1928 usecs +PNP: 002e.b init ... +PNP: 002e.b init finished in 1929 usecs +smbus: PCI: 00:01.1[0]->I2C: 01:2f init ... +ID: 5ca3 +I2C: 01:2f init finished in 101140 usecs +PCI: 01:04.0 init ... +XGI Z9s: initializing video device +XGI VGA: Relocate IO address: 1000 [00001030] +XGI VGA: chipid = 31 +XGI VGA: Framebuffer at 0xf8000000, mapped to 0xf8000000, size 16384k +XGI VGA: MMIO at 0xfc000000, mapped to 0xfc000000, size 256k +XGI VGA: No or unknown bridge type detected +XGI VGA: Default mode is 800x600x16 (60Hz) +XGI VGA: Set new mode: 800x600x16-60 +PCI: 01:04.0 init finished in 42544 usecs +PCI: 02:00.0 init ... +PCI: 02:00.0 init finished in 2018 usecs +PCI: 03:00.0 init ... +PCI: 03:00.0 init finished in 2018 usecs +Devices initialized +Show all devs... After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:18.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:01.0: enabled 1 +PNP: 002e.0: enabled 1 +PNP: 002e.1: enabled 0 +PNP: 002e.2: enabled 1 +PNP: 002e.3: enabled 1 +PNP: 002e.5: enabled 1 +PNP: 002e.7: enabled 0 +PNP: 002e.8: enabled 0 +PNP: 002e.9: enabled 1 +PNP: 002e.a: enabled 0 +PNP: 002e.b: enabled 1 +PCI: 00:01.1: enabled 1 +I2C: 01:50: enabled 1 +I2C: 01:51: enabled 1 +I2C: 01:52: enabled 1 +I2C: 01:53: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:2f: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:04.0: enabled 0 +PCI: 00:04.1: enabled 0 +PCI: 00:06.0: enabled 1 +PCI: 00:07.0: enabled 1 +PCI: 00:08.0: enabled 1 +PCI: 00:09.0: enabled 1 +PCI: 01:04.0: enabled 1 +PCI: 00:0a.0: enabled 0 +PCI: 00:0b.0: enabled 1 +PCI: 02:00.0: enabled 1 +PCI: 00:0c.0: enabled 1 +PCI: 03:00.0: enabled 1 +PCI: 00:0d.0: enabled 1 +PCI: 04:00.0: enabled 0 +PCI: 00:0e.0: enabled 1 +PCI: 00:0f.0: enabled 0 +PCI: 00:18.1: enabled 1 +PCI: 00:18.2: enabled 1 +PCI: 00:18.3: enabled 1 +PCI: 00:18.4: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:19.1: enabled 1 +PCI: 00:19.2: enabled 1 +PCI: 00:19.3: enabled 1 +PCI: 00:19.4: enabled 1 +APIC: 01: enabled 1 +APIC: 02: enabled 1 +APIC: 03: enabled 1 +APIC: 04: enabled 1 +APIC: 05: enabled 1 +APIC: 06: enabled 1 +APIC: 07: enabled 1 +BS: BS_DEV_INIT times (us): entry 0 run 1990325 exit 0 +Finalize devices... +Devices finalized +BS: BS_POST_DEVICE times (us): entry 0 run 3526 exit 0 +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CONFIG_LOGICAL_CPUS==1: apicid_base: 00000001 +Writing IRQ routing tables to 0xf0000...done. +Writing IRQ routing tables to 0xbffd8000...done. +PIRQ table: 224 bytes. +Wrote the mp table end at: 000f0410 - 000f05cc +Wrote the mp table end at: bffd7010 - bffd71cc +MP table: 460 bytes. +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/dsdt.aml' +CBFS: Found @ offset c00 size 2644 +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/slic' +CBFS: 'fallback/slic' not found. +ACPI: Writing ACPI tables at bffb3000. +ACPI: * FACS +ACPI: * DSDT +ACPI: * FADT +pm_base: 0x2000 +ACPI: added table 1/32, length now 40 +ACPI: * SSDT +processor_brand=Quad-Core AMD Opteron(tm) Processor 8347 +Pstates algorithm ... +Pstate_freq[0] = 1900MHz Pstate_power[0] = 23040mw +Pstate_latency[0] = 5us +Pstate_freq[1] = 1700MHz Pstate_power[1] = 21385mw +Pstate_latency[1] = 5us +Pstate_freq[2] = 1400MHz Pstate_power[2] = 18787mw +Pstate_latency[2] = 5us +Pstate_freq[3] = 1200MHz Pstate_power[3] = 16770mw +Pstate_latency[3] = 5us +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +ACPI: added table 2/32, length now 44 +ACPI: * MCFG +ACPI: * TCPA +TCPA log created at bffa3000 +ACPI: added table 3/32, length now 48 +ACPI: * MADT +ACPI: added table 4/32, length now 52 +current = bffb6910 +ACPI: * SRAT at bffb6910 +SRAT: lapic cpu_index=00, node_id=00, apic_id=00 +SRAT: lapic cpu_index=01, node_id=00, apic_id=01 +SRAT: lapic cpu_index=02, node_id=00, apic_id=02 +SRAT: lapic cpu_index=03, node_id=00, apic_id=03 +SRAT: lapic cpu_index=04, node_id=01, apic_id=04 +SRAT: lapic cpu_index=05, node_id=01, apic_id=05 +SRAT: lapic cpu_index=06, node_id=01, apic_id=06 +SRAT: lapic cpu_index=07, node_id=01, apic_id=07 +set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 +set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 +set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 +set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00100000 +set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=00500000, sizek=00100000 +ACPI: added table 5/32, length now 56 +ACPI: * SLIT at bffb6a88 +ACPI: added table 6/32, length now 60 +ACPI: * HPET +ACPI: added table 7/32, length now 64 +ACPI: * SRAT at bffb6b00 +SRAT: lapic cpu_index=00, node_id=00, apic_id=00 +SRAT: lapic cpu_index=01, node_id=00, apic_id=01 +SRAT: lapic cpu_index=02, node_id=00, apic_id=02 +SRAT: lapic cpu_index=03, node_id=00, apic_id=03 +SRAT: lapic cpu_index=04, node_id=01, apic_id=04 +SRAT: lapic cpu_index=05, node_id=01, apic_id=05 +SRAT: lapic cpu_index=06, node_id=01, apic_id=06 +SRAT: lapic cpu_index=07, node_id=01, apic_id=07 +set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 +set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 +set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 +set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00100000 +set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=00500000, sizek=00100000 +ACPI: added table 8/32, length now 68 +ACPI: * SLIT at bffb6c78 +ACPI: added table 9/32, length now 72 +ACPI: done. +ACPI tables: 15536 bytes. +smbios_write_tables: bffa2000 +Root Device (ASUS KFSN4-DRE) +CPU_CLUSTER: 0 (AMD FAM10 Root Complex) +APIC: 00 (unknown) +DOMAIN: 0000 (AMD FAM10 Root Complex) +PCI: 00:18.0 (AMD FAM10 Northbridge) +PCI: 00:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:01.0 (NVIDIA CK804 Southbridge) +PNP: 002e.0 (Winbond W83627THG Super I/O) +PNP: 002e.1 (Winbond W83627THG Super I/O) +PNP: 002e.2 (Winbond W83627THG Super I/O) +PNP: 002e.3 (Winbond W83627THG Super I/O) +PNP: 002e.5 (Winbond W83627THG Super I/O) +PNP: 002e.7 (Winbond W83627THG Super I/O) +PNP: 002e.8 (Winbond W83627THG Super I/O) +PNP: 002e.9 (Winbond W83627THG Super I/O) +PNP: 002e.a (Winbond W83627THG Super I/O) +PNP: 002e.b (Winbond W83627THG Super I/O) +PCI: 00:01.1 (NVIDIA CK804 Southbridge) +I2C: 01:50 (unknown) +I2C: 01:51 (unknown) +I2C: 01:52 (unknown) +I2C: 01:53 (unknown) +I2C: 01:54 (unknown) +I2C: 01:55 (unknown) +I2C: 01:56 (unknown) +I2C: 01:57 (unknown) +I2C: 01:2f (Nuvoton W83793 Hardware Monitor) +PCI: 00:02.0 (NVIDIA CK804 Southbridge) +PCI: 00:02.1 (NVIDIA CK804 Southbridge) +PCI: 00:04.0 (NVIDIA CK804 Southbridge) +PCI: 00:04.1 (NVIDIA CK804 Southbridge) +PCI: 00:06.0 (NVIDIA CK804 Southbridge) +PCI: 00:07.0 (NVIDIA CK804 Southbridge) +PCI: 00:08.0 (NVIDIA CK804 Southbridge) +PCI: 00:09.0 (NVIDIA CK804 Southbridge) +PCI: 01:04.0 (NVIDIA CK804 Southbridge) +PCI: 00:0a.0 (NVIDIA CK804 Southbridge) +PCI: 00:0b.0 (NVIDIA CK804 Southbridge) +PCI: 02:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:0c.0 (NVIDIA CK804 Southbridge) +PCI: 03:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:0d.0 (NVIDIA CK804 Southbridge) +PCI: 04:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:0e.0 (NVIDIA CK804 Southbridge) +PCI: 00:0f.0 (NVIDIA CK804 Southbridge) +PCI: 00:18.1 (AMD FAM10 Northbridge) +PCI: 00:18.2 (AMD FAM10 Northbridge) +PCI: 00:18.3 (AMD FAM10 Northbridge) +PCI: 00:18.4 (AMD FAM10 Northbridge) +PCI: 00:19.0 (AMD FAM10 Northbridge) +PCI: 00:19.1 (AMD FAM10 Northbridge) +PCI: 00:19.2 (AMD FAM10 Northbridge) +PCI: 00:19.3 (AMD FAM10 Northbridge) +PCI: 00:19.4 (AMD FAM10 Northbridge) +APIC: 01 (unknown) +APIC: 02 (unknown) +APIC: 03 (unknown) +APIC: 04 (unknown) +APIC: 05 (unknown) +APIC: 06 (unknown) +APIC: 07 (unknown) +SMBIOS tables: 553 bytes. +Writing table forward entry at 0x00000500 +Wrote coreboot table at: 00000500, 0x10 bytes, checksum 9fe4 +Table forward entry ends at 0x00000528. +... aligned to 0x00001000 +Writing coreboot table at 0xbff9a000 +rom_table_end = 0xbff9a000 +... aligned to 0xbffa0000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 + 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES + 1. 0000000000001000-000000000009ffff: RAM + 2. 00000000000a0000-00000000000bffff: RESERVED + 3. 00000000000c0000-00000000bff99fff: RAM + 4. 00000000bff9a000-00000000bfffffff: CONFIGURATION TABLES + 5. 00000000c0000000-00000000cfffffff: RESERVED + 6. 0000000100000000-000000017fffffff: RAM +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Wrote coreboot table at: bff9a000, 0xc08 bytes, checksum 440a +coreboot table: 3104 bytes. +IMD ROOT 0. bffff000 00001000 +IMD SMALL 1. bfffe000 00001000 +CAR GLOBALS 2. bfffb000 0000291c +CONSOLE 3. bffdb000 00020000 +AMDMEM INFO 4. bffd9000 0000172c +IRQ TABLE 5. bffd8000 00001000 +SMP TABLE 6. bffd7000 00001000 +ACPI 7. bffb3000 00024000 +54435041 8. bffa3000 00010000 +SMBIOS 9. bffa2000 00000800 +COREBOOT 10. bff9a000 00008000 +IMD small region: + IMD ROOT 0. bfffec00 00000400 + USBDEBUG 1. bfffeba0 00000058 + ROMSTAGE 2. bfffeb80 00000004 + GDT 3. bfffe980 00000200 +BS: BS_WRITE_TABLES times (us): entry 0 run 759226 exit 0 +CBFS provider active. +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/payload' +CBFS: Found @ offset 29c80 size 92b41 +'fallback/payload' located at offset: 29cb8 size: 92b41 +Loading segment from rom address 0xfff29cb8 + code (compression=1) + New segment dstaddr 0x8200 memsize 0x17420 srcaddr 0xfff29d0c filesize 0x8215 +Loading segment from rom address 0xfff29cd4 + code (compression=1) + New segment dstaddr 0x100000 memsize 0x23f9f0 srcaddr 0xfff31f21 filesize 0x8a8d8 +Loading segment from rom address 0xfff29cf0 + Entry Point 0x00008200 +Bounce Buffer at bfc5b000, 3401660 bytes +Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017420 filesz: 0x0000000000008215 +lb: [0x0000000000100000, 0x00000000001fedcc) +Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017420 filesz: 0x0000000000008215 +using LZMA +[ 0x00008200, 00017ce3, 0x0001f620) <- fff29d0c +Clearing Segment: addr: 0x0000000000017ce3 memsz: 0x000000000000793d +dest 00008200, end 0001f620, bouncebuffer bfc5b000 +Loading Segment: addr: 0x0000000000100000 memsz: 0x000000000023f9f0 filesz: 0x000000000008a8d8 +lb: [0x0000000000100000, 0x00000000001fedcc) +segment: [0x0000000000100000, 0x000000000018a8d8, 0x000000000033f9f0) + bounce: [0x00000000bfc5b000, 0x00000000bfce58d8, 0x00000000bfe9a9f0) +Post relocation: addr: 0x00000000bfc5b000 memsz: 0x000000000023f9f0 filesz: 0x000000000008a8d8 +using LZMA +[ 0xbfc5b000, bfe9a9f0, 0xbfe9a9f0) <- fff31f21 +dest bfc5b000, end bfe9a9f0, bouncebuffer bfc5b000 +move suffix around: from bfd59dcc, to 1fedcc, amount: 140c24 +Loaded segments +BS: BS_PAYLOAD_LOAD times (us): entry 0 run 781450 exit 0 +Jumping to boot code at 00008200(bff9a000) +CPU0: stack: 00139000 - 0013a000, lowest used address 00139ae0, stack used: 1312 bytes +entry = 0x00008200 +lb_start = 0x00100000 +lb_size = 0x000fedcc +buffer = 0xbfc5b000 +[?25lFREE AS IN FREEDOM + + ++----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. + + Press enter to boot the selected OS, `e' to edit the commands + + before booting or `c' for a command-line.  *Load Operating System  Parse ISOLINUX menu (ahci0)  Parse ISOLINUX menu (USB)  Parse ISOLINUX menu (CD/DVD)  Switch to grubtest.cfg  Search for GRUB configuration (grub.cfg) outside of CBFS  Load MemTest86+        The highlighted entry will be executed automatically in 1s.  The highlighted entry will be executed automatically in 0s. [?25h Booting `Load Operating System' + + + + Failed to boot both default and fallback entries. + + +Press any key to continue... + +[?25lFREE AS IN FREEDOM + + ++----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. + + Press enter to boot the selected OS, `e' to edit the commands + + before booting or `c' for a command-line.  *Load Operating System  Parse ISOLINUX menu (ahci0)  Parse ISOLINUX menu (USB)  Parse ISOLINUX menu (CD/DVD)  Switch to grubtest.cfg  Search for GRUB configuration (grub.cfg) outside of CBFS  Load MemTest86+          Load Operating System *Parse ISOLINUX menu (ahci0)  Parse ISOLINUX menu (ahci0) *Parse ISOLINUX menu (USB)  Parse ISOLINUX menu (USB) *Parse ISOLINUX menu (CD/DVD)  Parse ISOLINUX menu (CD/DVD) *Switch to grubtest.cfg  ��ޒ���������� + +*****GRAPHICAL FRAMEBUFFER ROM IMAGE***** + + + +coreboot-4.0 Fri Jun 26 20:19:42 UTC 2015 romstage starting... +BSP Family_Model: 00100f21 +*sysinfo range: [000c4000,000c6899] +bsp_apicid = 00 +cpu_init_detectedx = 00000000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: 'cpu_microcode_blob.bin' not found. +[microcode] microcode file not found. Skipping updates. +cpuSetAMDMSR done +Enter amd_ht_init() +AMD_CB_EventNotify() + event class: 05 + event: 1004 + data: 04 00 00 01 +AMD_CB_EventNotify() + event class: 05 + event: 2006 + data: 04 00 01 00 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Exit amd_ht_init() +cpuSetAMDPCI 00 done +cpuSetAMDPCI 01 done +Prep FID/VID Node:00 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f23 + F3xD8: 03001c14 + F3xDC: 00005428 +Prep FID/VID Node:01 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f23 + F3xD8: 03001c14 + F3xDC: 00005428 +setup_remote_node: 01 done +Start node 01 done. +core0 started: 01 + +Begin FIDVID MSR 0xc0010071 0x20a600e4 0x38045044 +FIDVID on BSP, APIC_id: 00 +BSP fid = 10400 +Wait for AP stage 1: ap_apicid = 1 +init_fidvid_bsp_stage1: timed out reading from ap 01 +Wait for AP stage 1: ap_apicid = 2 +init_fidvid_bsp_stage1: timed out reading from ap 02 +Wait for AP stage 1: ap_apicid = 3 +init_fidvid_bsp_stage1: timed out reading from ap 03 +Wait for AP stage 1: ap_apicid = 4 + readback = 4010401 + common_fid(packed) = 10400 +Wait for AP stage 1: ap_apicid = 5 +init_fidvid_bsp_stage1: timed out reading from ap 05 +Wait for AP stage 1: ap_apicid = 6 +init_fidvid_bsp_stage1: timed out reading from ap 06 +Wait for AP stage 1: ap_apicid = 7 +init_fidvid_bsp_stage1: timed out reading from ap 07 +common_fid = 10400 +FID Change Node:00, F3xD4: c3310f24 +FID Change Node:01, F3xD4: c3310f24 +End FIDVIDMSR 0xc0010071 0x20a600e4 0x38005044 +start_other_cores() +init node: 00 cores: 03 +Start other core - nodeid: 00 cores: 03 +init node: 01 cores: 03 +Start other core - nodeid: 01 cores: 03 +started ap apicid: 01start + +coreboot-4.0 Fri Jun 26 20:19:42 UTC 2015 romstage starting... +BSP Family_Model: 00100f21 +*sysinfo range: [000c4000,000c6899] +bsp_apicid = 00 +cpu_init_detectedx = 00000000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cpu_microcode_blob.bin' +CBFS: 'cpu_microcode_blob.bin' not found. +[microcode] microcode file not found. Skipping updates. +cpuSetAMDMSR done +Enter amd_ht_init() +AMD_CB_EventNotify() + event class: 05 + event: 1004 + data: 04 00 00 01 +AMD_CB_EventNotify() + event class: 05 + event: 2006 + data: 04 00 01 00 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Exit amd_ht_init() +cpuSetAMDPCI 00 done +cpuSetAMDPCI 01 done +Prep FID/VID Node:00 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f24 + F3xD8: 03001c14 + F3xDC: 00005428 +Prep FID/VID Node:01 + F3x80: e600a681 + F3x84: a0e641e6 + F3xD4: c3310f24 + F3xD8: 03001c14 + F3xDC: 00005428 +setup_remote_node: 01 done +Start node 01 done. +core0 started: 01 + +Begin FIDVID MSR 0xc0010071 0x20a600e4 0x38005044 +End FIDVIDMSR 0xc0010071 0x20a600e4 0x38003803 +start_other_cores() +init node: 00 cores: 03 +Start other core - nodeid: 00 cores: 03 +init node: 01 cores: 03 +Start other core - nodeid: 01 cores: 03 +started ap apicid: * AP 01started +* AP 02started +* AP 03started +* AP 05started +* AP 06started +* AP 07started + +set_ck804_base_unit_id() +fill_mem_ctrl() +enable_smbus() +SMBus controller enabled +raminit_amdmct() +raminit_amdmct begin: +activate_spd_rom() for node 00 +enable_spd_node0() +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +activate_spd_rom() for node 01 +enable_spd_node1() +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 + Node: 00 base: 00 limit: ffffff BottomIO: c00000 + Node: 01 base: 1400000 limit: 17fffff BottomIO: c00000 + Copy dram map from Node 0 to Node 01 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +raminit_amdmct end: +CBMEM: +IMD: root @ bffff000 254 entries. +IMD: root @ bfffec00 62 entries. +amdmct_cbmem_store_info: Storing AMDMCT configuration in CBMEM +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +disable_spd() +enable_msi_mapping() +Prepare CAR migration and stack regions... Fill [003fd000-003fffff] ... Done +Copying data from cache to RAM... Copy [000c4000-000c693f] to [003fd6c0 - 003fffff] ... Done +Switching to use RAM as stack... Top about 003fd6ac ... Done +Disabling cache as ram now +Prepare ramstage memory region... Fill [00000000-003fcfff] ... Done +CBFS provider active. +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/ramstage' +CBFS: Found @ offset 15440 size 147e1 +'fallback/ramstage' located at offset: 15478 size: 147e1 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Capability: type 0x0a @ 0x44 + +coreboot-4.0 Fri Jun 26 20:19:42 UTC 2015 ramstage starting... +Moving GDT to bfffe980...ok +BS: BS_PRE_DEVICE times (us): entry 0 run 1 exit 0 +BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 3 exit 0 +Enumerating buses... +Show all devs... Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:18.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:01.0: enabled 1 +PNP: 002e.0: enabled 1 +PNP: 002e.1: enabled 0 +PNP: 002e.2: enabled 1 +PNP: 002e.3: enabled 1 +PNP: 002e.5: enabled 1 +PNP: 002e.7: enabled 0 +PNP: 002e.8: enabled 0 +PNP: 002e.9: enabled 1 +PNP: 002e.a: enabled 0 +PNP: 002e.b: enabled 1 +PCI: 00:01.1: enabled 1 +I2C: 00:50: enabled 1 +I2C: 00:51: enabled 1 +I2C: 00:52: enabled 1 +I2C: 00:53: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:2f: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:04.0: enabled 0 +PCI: 00:04.1: enabled 0 +PCI: 00:06.0: enabled 1 +PCI: 00:07.0: enabled 1 +PCI: 00:08.0: enabled 1 +PCI: 00:09.0: enabled 1 +PCI: 00:04.0: enabled 1 +PCI: 00:0a.0: enabled 0 +PCI: 00:0b.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:0c.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:0d.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:0e.0: enabled 1 +PCI: 00:0f.0: enabled 0 +PCI: 00:18.1: enabled 1 +PCI: 00:18.2: enabled 1 +PCI: 00:18.3: enabled 1 +PCI: 00:18.4: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:19.1: enabled 1 +PCI: 00:19.2: enabled 1 +PCI: 00:19.3: enabled 1 +PCI: 00:19.4: enabled 1 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + DOMAIN: 0000: enabled 1 + PCI: 00:18.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:01.0: enabled 1 + PNP: 002e.0: enabled 1 + PNP: 002e.1: enabled 0 + PNP: 002e.2: enabled 1 + PNP: 002e.3: enabled 1 + PNP: 002e.5: enabled 1 + PNP: 002e.7: enabled 0 + PNP: 002e.8: enabled 0 + PNP: 002e.9: enabled 1 + PNP: 002e.a: enabled 0 + PNP: 002e.b: enabled 1 + PCI: 00:01.1: enabled 1 + I2C: 00:50: enabled 1 + I2C: 00:51: enabled 1 + I2C: 00:52: enabled 1 + I2C: 00:53: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:2f: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:04.0: enabled 0 + PCI: 00:04.1: enabled 0 + PCI: 00:06.0: enabled 1 + PCI: 00:07.0: enabled 1 + PCI: 00:08.0: enabled 1 + PCI: 00:09.0: enabled 1 + PCI: 00:04.0: enabled 1 + PCI: 00:0a.0: enabled 0 + PCI: 00:0b.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:0c.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:0d.0: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:0e.0: enabled 1 + PCI: 00:0f.0: enabled 0 + PCI: 00:18.1: enabled 1 + PCI: 00:18.2: enabled 1 + PCI: 00:18.3: enabled 1 + PCI: 00:18.4: enabled 1 + PCI: 00:19.0: enabled 1 + PCI: 00:19.1: enabled 1 + PCI: 00:19.2: enabled 1 + PCI: 00:19.3: enabled 1 + PCI: 00:19.4: enabled 1 +Root Device scanning... +root_dev_scan_bus for Root Device +setup_bsp_ramtop, TOP MEM: msr.lo = 0xc0000000, msr.hi = 0x00000000 +setup_bsp_ramtop, TOP MEM2: msr.lo = 0x80000000, msr.hi = 0x00000001 +CPU_CLUSTER: 0 enabled +DOMAIN: 0000 enabled +CPU_CLUSTER: 0 scanning... +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 + PCI: 00:18.3 siblings=3 +CPU: APIC: 00 enabled +CPU: APIC: 01 enabled +CPU: APIC: 02 enabled +CPU: APIC: 03 enabled + PCI: 00:19.3 siblings=3 +CPU: APIC: 04 enabled +CPU: APIC: 05 enabled +CPU: APIC: 06 enabled +CPU: APIC: 07 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:18.0 [1022/1200] bus ops +PCI: 00:18.0 [1022/1200] enabled +PCI: 00:18.1 [1022/1201] enabled +PCI: 00:18.2 [1022/1202] enabled +PCI: 00:18.3 [1022/1203] ops +PCI: 00:18.3 [1022/1203] enabled +PCI: 00:18.4 [1022/1204] enabled +PCI: 00:19.0 [1022/1200] bus ops +PCI: 00:19.0 [1022/1200] enabled +PCI: 00:19.1 [1022/1201] enabled +PCI: 00:19.2 [1022/1202] enabled +PCI: 00:19.3 [1022/1203] ops +PCI: 00:19.3 [1022/1203] enabled +PCI: 00:19.4 [1022/1204] enabled +PCI: 00:18.0 scanning... +PCI: 00:00.0 [10de/005e] ops +PCI: 00:00.0 [10de/005e] enabled +Capability: type 0x08 @ 0x44 +flags: 0x01e0 +PCI: 00:00.0 count: 000f static_count: 0010 +PCI: 00:00.0 [10de/005e] enabled next_unitid: 0010 +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [10de/005e] enabled +PCI: 00:01.0 [10de/0051] bus ops +PCI: 00:01.0 [10de/0051] enabled +PCI: 00:01.1 [10de/0052] bus ops +PCI: 00:01.1 [10de/0052] enabled +PCI: 00:02.0 [10de/005a] ops +PCI: 00:02.0 [10de/005a] enabled +PCI: 00:02.1 [10de/005b] ops +PCI: 00:02.1 [10de/005b] enabled +PCI: 00:04.0 [10de/0059] ops +PCI: 00:04.0 [10de/0059] disabled +PCI: 00:04.1 [10de/0058] ops +PCI: 00:04.1 [10de/0058] disabled +PCI: 00:06.0 [10de/0053] ops +PCI: 00:06.0 [10de/0053] enabled +PCI: 00:07.0 [10de/0054] ops +PCI: 00:07.0 [10de/0054] enabled +PCI: 00:08.0 [10de/0055] ops +PCI: 00:08.0 [10de/0055] enabled +PCI: 00:09.0 [10de/005c] bus ops +PCI: 00:09.0 [10de/005c] enabled +PCI: 00:0b.0 [10de/005d] bus ops +PCI: 00:0b.0 [10de/005d] enabled +PCI: 00:0c.0 [10de/005d] bus ops +PCI: 00:0c.0 [10de/005d] enabled +PCI: 00:0d.0 [10de/005d] bus ops +PCI: 00:0d.0 [10de/005d] enabled +PCI: 00:0e.0 [10de/005d] bus ops +PCI: 00:0e.0 [10de/005d] enabled +PCI: 00:01.0 scanning... +scan_lpc_bus for PCI: 00:01.0 +PNP: 002e.0 enabled +PNP: 002e.1 disabled +PNP: 002e.2 enabled +PNP: 002e.3 enabled +PNP: 002e.5 enabled +PNP: 002e.7 disabled +PNP: 002e.8 disabled +PNP: 002e.9 enabled +PNP: 002e.a disabled +PNP: 002e.b enabled +scan_lpc_bus for PCI: 00:01.0 done +PCI: 00:01.1 scanning... +scan_smbus for PCI: 00:01.1 +smbus: PCI: 00:01.1[0]->I2C: 01:50 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:51 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:52 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:53 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:54 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:55 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:56 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:57 enabled +smbus: PCI: 00:01.1[0]->I2C: 01:2f enabled +scan_smbus for PCI: 00:01.1 done +PCI: 00:09.0 scanning... +do_pci_scan_bridge for PCI: 00:09.0 +PCI: pci_scan_bus for bus 01 +PCI: 01:04.0 [18ca/0020] ops +PCI: 01:04.0 [18ca/0020] enabled +PCI: 00:0b.0 scanning... +do_pci_scan_bridge for PCI: 00:0b.0 +PCI: pci_scan_bus for bus 02 +PCI: 02:00.0 [14e4/1659] enabled +PCI: 00:0c.0 scanning... +do_pci_scan_bridge for PCI: 00:0c.0 +PCI: pci_scan_bus for bus 03 +PCI: 03:00.0 [14e4/1659] enabled +PCI: 00:0d.0 scanning... +do_pci_scan_bridge for PCI: 00:0d.0 +PCI: pci_scan_bus for bus 04 +PCI: Static device PCI: 04:00.0 not found, disabling it. +PCI: 00:0e.0 scanning... +do_pci_scan_bridge for PCI: 00:0e.0 +PCI: pci_scan_bus for bus 05 +PCI: 00:19.0 scanning... +DOMAIN: 0000 passpw: enabled +DOMAIN: 0000 passpw: enabled +root_dev_scan_bus for Root Device done +done +BS: BS_DEV_ENUMERATE times (us): entry 0 run 598144 exit 0 +found VGA at PCI: 01:04.0 +Setting up VGA for PCI: 01:04.0 +Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:09.0 +Setting PCI_BRIDGE_CTL_VGA for bridge PCI: 00:18.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +APIC: 01 missing read_resources +APIC: 02 missing read_resources +APIC: 03 missing read_resources +APIC: 04 missing read_resources +APIC: 05 missing read_resources +APIC: 06 missing read_resources +APIC: 07 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 +PCI: 00:18.0 read_resources bus 0 link: 1 +PCI: 00:01.0 read_resources bus 0 link: 0 +PCI: 00:01.0 read_resources bus 0 link: 0 done +PCI: 00:01.1 read_resources bus 1 link: 0 +I2C: 01:50 missing read_resources +I2C: 01:51 missing read_resources +I2C: 01:52 missing read_resources +I2C: 01:53 missing read_resources +I2C: 01:54 missing read_resources +I2C: 01:55 missing read_resources +I2C: 01:56 missing read_resources +I2C: 01:57 missing read_resources +PCI: 00:01.1 read_resources bus 1 link: 0 done +PCI: 00:01.1 read_resources bus 2 link: 1 +PCI: 00:01.1 read_resources bus 2 link: 1 done +PCI: 00:09.0 read_resources bus 1 link: 0 +PCI: 00:09.0 read_resources bus 1 link: 0 done +PCI: 00:0b.0 read_resources bus 2 link: 0 +PCI: 00:0b.0 read_resources bus 2 link: 0 done +PCI: 00:0c.0 read_resources bus 3 link: 0 +PCI: 00:0c.0 read_resources bus 3 link: 0 done +PCI: 00:0d.0 read_resources bus 4 link: 0 +PCI: 00:0d.0 read_resources bus 4 link: 0 done +PCI: 00:0e.0 read_resources bus 5 link: 0 +PCI: 00:0e.0 read_resources bus 5 link: 0 done +PCI: 00:18.0 read_resources bus 0 link: 1 done +PCI: 00:18.0 read_resources bus 0 link: 0 +PCI: 00:18.0 read_resources bus 0 link: 0 done +PCI: 00:18.0 read_resources bus 0 link: 2 +PCI: 00:18.0 read_resources bus 0 link: 2 done +PCI: 00:18.0 read_resources bus 0 link: 3 +PCI: 00:18.0 read_resources bus 0 link: 3 done +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +PCI: 00:18.4 read_resources bus 0 link: 0 +PCI: 00:18.4 read_resources bus 0 link: 0 done +PCI: 00:18.4 read_resources bus 0 link: 1 +PCI: 00:18.4 read_resources bus 0 link: 1 done +PCI: 00:18.4 read_resources bus 0 link: 2 +PCI: 00:18.4 read_resources bus 0 link: 2 done +PCI: 00:18.4 read_resources bus 0 link: 3 +PCI: 00:18.4 read_resources bus 0 link: 3 done +PCI: 00:19.0 read_resources bus 0 link: 0 +PCI: 00:19.0 read_resources bus 0 link: 0 done +PCI: 00:19.0 read_resources bus 0 link: 1 +PCI: 00:19.0 read_resources bus 0 link: 1 done +PCI: 00:19.0 read_resources bus 0 link: 2 +PCI: 00:19.0 read_resources bus 0 link: 2 done +PCI: 00:19.0 read_resources bus 0 link: 3 +PCI: 00:19.0 read_resources bus 0 link: 3 done +PCI: 00:19.4 read_resources bus 0 link: 0 +PCI: 00:19.4 read_resources bus 0 link: 0 done +PCI: 00:19.4 read_resources bus 0 link: 1 +PCI: 00:19.4 read_resources bus 0 link: 1 done +PCI: 00:19.4 read_resources bus 0 link: 2 +PCI: 00:19.4 read_resources bus 0 link: 2 done +PCI: 00:19.4 read_resources bus 0 link: 3 +PCI: 00:19.4 read_resources bus 0 link: 3 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: 01 + APIC: 02 + APIC: 03 + APIC: 04 + APIC: 05 + APIC: 06 + APIC: 07 + DOMAIN: 0000 child on link 0 PCI: 00:18.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 + DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 + PCI: 00:18.0 child on link 0 PCI: 00:00.0 + PCI: 00:18.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80100 index 110d8 + PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 81200 index 110b8 + PCI: 00:18.0 resource base 0 size 0 align 20 gran 20 limit ffffffffff flags 80200 index 110b0 + PCI: 00:00.0 + PCI: 00:01.0 child on link 0 PNP: 002e.0 + PCI: 00:01.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 10 + PCI: 00:01.0 resource base fec00000 size 1000 align 12 gran 12 limit ffffffff flags c0000200 index 14 + PCI: 00:01.0 resource base fed00000 size 1000 align 12 gran 12 limit ffffffff flags c0000200 index 44 + PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 60 + PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 64 + PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 68 + PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PNP: 002e.0 + PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags c0000800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.3 + PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags c0000100 index 60 + PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags c0000500 index f1 + PNP: 002e.5 + PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 60 + PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags c0000100 index 62 + PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags c0000400 index 72 + PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.7 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 + PNP: 002e.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.8 + PNP: 002e.9 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 30 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f1 + PNP: 002e.a + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.b + PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags c0000100 index 60 + PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags c0000400 index 70 + PCI: 00:01.1 child on link 0 I2C: 01:50 + PCI: 00:01.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 10 + PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 + PCI: 00:01.1 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 24 + I2C: 01:50 + I2C: 01:51 + I2C: 01:52 + I2C: 01:53 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:2f + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 100 align 8 gran 8 limit ffffffff flags 200 index 10 + PCI: 00:04.0 + PCI: 00:04.1 + PCI: 00:06.0 + PCI: 00:06.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:07.0 + PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:07.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:07.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:07.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:07.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 00:08.0 + PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:08.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:08.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:08.0 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 + PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 24 + PCI: 00:09.0 child on link 0 PCI: 01:04.0 + PCI: 00:09.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 81202 index 24 + PCI: 00:09.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 01:04.0 + PCI: 01:04.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffff flags 1200 index 10 + PCI: 01:04.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 14 + PCI: 01:04.0 resource base 0 size 80 align 7 gran 7 limit ffff flags 100 index 18 + PCI: 00:0a.0 + PCI: 00:0b.0 child on link 0 PCI: 02:00.0 + PCI: 00:0b.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0b.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:0c.0 child on link 0 PCI: 03:00.0 + PCI: 00:0c.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 03:00.0 + PCI: 03:00.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 + PCI: 00:0d.0 child on link 0 PCI: 04:00.0 + PCI: 00:0d.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 04:00.0 + PCI: 00:0e.0 + PCI: 00:0e.0 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c + PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:0e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:0f.0 + PCI: 00:18.1 + PCI: 00:18.2 + PCI: 00:18.3 + PCI: 00:18.4 + PCI: 00:19.0 + PCI: 00:19.1 + PCI: 00:19.2 + PCI: 00:19.3 + PCI: 00:19.4 +DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:18.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:09.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 01:04.0 18 * [0x0 - 0x7f] io +PCI: 00:09.0 io: base: 80 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0b.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0c.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:0e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff +PCI: 00:0e.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done +PCI: 00:09.0 1c * [0x0 - 0xfff] io +PCI: 00:01.0 60 * [0x1000 - 0x10ff] io +PCI: 00:01.0 64 * [0x1400 - 0x14ff] io +PCI: 00:01.0 68 * [0x1800 - 0x18ff] io +PCI: 00:01.0 10 * [0x1c00 - 0x1c7f] io +PCI: 00:01.1 20 * [0x1c80 - 0x1cbf] io +PCI: 00:01.1 24 * [0x1cc0 - 0x1cff] io +PCI: 00:01.1 10 * [0x2000 - 0x201f] io +PCI: 00:06.0 20 * [0x2020 - 0x202f] io +PCI: 00:07.0 20 * [0x2030 - 0x203f] io +PCI: 00:08.0 20 * [0x2040 - 0x204f] io +PCI: 00:07.0 10 * [0x2050 - 0x2057] io +PCI: 00:07.0 18 * [0x2058 - 0x205f] io +PCI: 00:08.0 10 * [0x2060 - 0x2067] io +PCI: 00:08.0 18 * [0x2068 - 0x206f] io +PCI: 00:07.0 14 * [0x2070 - 0x2073] io +PCI: 00:07.0 1c * [0x2074 - 0x2077] io +PCI: 00:08.0 14 * [0x2078 - 0x207b] io +PCI: 00:08.0 1c * [0x207c - 0x207f] io +PCI: 00:18.0 io: base: 2080 size: 3000 align: 12 gran: 12 limit: ffff done +PCI: 00:18.0 110d8 * [0x0 - 0x2fff] io +DOMAIN: 0000 io: base: 3000 size: 3000 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:18.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff +PCI: 00:09.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:04.0 10 * [0x0 - 0x3ffffff] prefmem +PCI: 00:09.0 prefmem: base: 4000000 size: 4000000 align: 26 gran: 20 limit: ffffffff done +PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0b.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0c.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:0e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:0e.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:09.0 24 * [0x0 - 0x3ffffff] prefmem +PCI: 00:18.0 prefmem: base: 4000000 size: 4000000 align: 26 gran: 20 limit: ffffffff done +PCI: 00:18.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffff +PCI: 00:09.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 01:04.0 14 * [0x0 - 0x3ffff] mem +PCI: 00:09.0 mem: base: 40000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0b.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 02:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:0b.0 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0c.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 03:00.0 10 * [0x0 - 0xffff] mem +PCI: 00:0c.0 mem: base: 10000 size: 100000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:0d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:0e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:0e.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:09.0 20 * [0x0 - 0xfffff] mem +PCI: 00:0b.0 20 * [0x100000 - 0x1fffff] mem +PCI: 00:0c.0 20 * [0x200000 - 0x2fffff] mem +PCI: 00:02.0 10 * [0x300000 - 0x300fff] mem +PCI: 00:07.0 24 * [0x301000 - 0x301fff] mem +PCI: 00:08.0 24 * [0x302000 - 0x302fff] mem +PCI: 00:02.1 10 * [0x303000 - 0x3030ff] mem +PCI: 00:18.0 mem: base: 303100 size: 400000 align: 20 gran: 20 limit: ffffffff done +PCI: 00:18.0 110b8 * [0x0 - 0x3ffffff] prefmem +PCI: 00:18.0 110b0 * [0x4000000 - 0x43fffff] mem +DOMAIN: 0000 mem: base: 4400000 size: 4400000 align: 26 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 c0010058 base c0000000 limit cfffffff mem (fixed) +constrain_resources: DOMAIN: 0000 07 base 00000000 limit bfffffff mem (fixed) +constrain_resources: PCI: 00:01.0 14 base fec00000 limit fec00fff mem (fixed) +constrain_resources: PCI: 00:01.0 10000000 base 00000000 limit 00000fff io (fixed) +avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 base f8000000 limit febfffff +Setting resources... +DOMAIN: 0000 io: base:1000 size:3000 align:12 gran:0 limit:ffff +PCI: 00:18.0 110d8 * [0x1000 - 0x3fff] io +DOMAIN: 0000 io: next_base: 4000 size: 3000 align: 12 gran: 0 done +PCI: 00:18.0 io: base:1000 size:3000 align:12 gran:12 limit:3fff +PCI: 00:09.0 1c * [0x1000 - 0x1fff] io +PCI: 00:01.0 60 * [0x2000 - 0x20ff] io +PCI: 00:01.0 64 * [0x2400 - 0x24ff] io +PCI: 00:01.0 68 * [0x2800 - 0x28ff] io +PCI: 00:01.0 10 * [0x2c00 - 0x2c7f] io +PCI: 00:01.1 20 * [0x2c80 - 0x2cbf] io +PCI: 00:01.1 24 * [0x2cc0 - 0x2cff] io +PCI: 00:01.1 10 * [0x3000 - 0x301f] io +PCI: 00:06.0 20 * [0x3020 - 0x302f] io +PCI: 00:07.0 20 * [0x3030 - 0x303f] io +PCI: 00:08.0 20 * [0x3040 - 0x304f] io +PCI: 00:07.0 10 * [0x3050 - 0x3057] io +PCI: 00:07.0 18 * [0x3058 - 0x305f] io +PCI: 00:08.0 10 * [0x3060 - 0x3067] io +PCI: 00:08.0 18 * [0x3068 - 0x306f] io +PCI: 00:07.0 14 * [0x3070 - 0x3073] io +PCI: 00:07.0 1c * [0x3074 - 0x3077] io +PCI: 00:08.0 14 * [0x3078 - 0x307b] io +PCI: 00:08.0 1c * [0x307c - 0x307f] io +PCI: 00:18.0 io: next_base: 3080 size: 3000 align: 12 gran: 12 done +PCI: 00:09.0 io: base:1000 size:1000 align:12 gran:12 limit:1fff +PCI: 01:04.0 18 * [0x1000 - 0x107f] io +PCI: 00:09.0 io: next_base: 1080 size: 1000 align: 12 gran: 12 done +PCI: 00:0b.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0b.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +PCI: 00:0c.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0c.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +PCI: 00:0d.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0d.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +PCI: 00:0e.0 io: base:3fff size:0 align:12 gran:12 limit:3fff +PCI: 00:0e.0 io: next_base: 3fff size: 0 align: 12 gran: 12 done +DOMAIN: 0000 mem: base:f8000000 size:4400000 align:26 gran:0 limit:febfffff +PCI: 00:18.0 110b8 * [0xf8000000 - 0xfbffffff] prefmem +PCI: 00:18.0 110b0 * [0xfc000000 - 0xfc3fffff] mem +DOMAIN: 0000 mem: next_base: fc400000 size: 4400000 align: 26 gran: 0 done +PCI: 00:18.0 prefmem: base:f8000000 size:4000000 align:26 gran:20 limit:fbffffff +PCI: 00:09.0 24 * [0xf8000000 - 0xfbffffff] prefmem +PCI: 00:18.0 prefmem: next_base: fc000000 size: 4000000 align: 26 gran: 20 done +PCI: 00:09.0 prefmem: base:f8000000 size:4000000 align:26 gran:20 limit:fbffffff +PCI: 01:04.0 10 * [0xf8000000 - 0xfbffffff] prefmem +PCI: 00:09.0 prefmem: next_base: fc000000 size: 4000000 align: 26 gran: 20 done +PCI: 00:0b.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0b.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:0c.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0c.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:0d.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0d.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:0e.0 prefmem: base:fbffffff size:0 align:20 gran:20 limit:fbffffff +PCI: 00:0e.0 prefmem: next_base: fbffffff size: 0 align: 20 gran: 20 done +PCI: 00:18.0 mem: base:fc000000 size:400000 align:20 gran:20 limit:fc3fffff +PCI: 00:09.0 20 * [0xfc000000 - 0xfc0fffff] mem +PCI: 00:0b.0 20 * [0xfc100000 - 0xfc1fffff] mem +PCI: 00:0c.0 20 * [0xfc200000 - 0xfc2fffff] mem +PCI: 00:02.0 10 * [0xfc300000 - 0xfc300fff] mem +PCI: 00:07.0 24 * [0xfc301000 - 0xfc301fff] mem +PCI: 00:08.0 24 * [0xfc302000 - 0xfc302fff] mem +PCI: 00:02.1 10 * [0xfc303000 - 0xfc3030ff] mem +PCI: 00:18.0 mem: next_base: fc303100 size: 400000 align: 20 gran: 20 done +PCI: 00:09.0 mem: base:fc000000 size:100000 align:20 gran:20 limit:fc0fffff +PCI: 01:04.0 14 * [0xfc000000 - 0xfc03ffff] mem +PCI: 00:09.0 mem: next_base: fc040000 size: 100000 align: 20 gran: 20 done +PCI: 00:0b.0 mem: base:fc100000 size:100000 align:20 gran:20 limit:fc1fffff +PCI: 02:00.0 10 * [0xfc100000 - 0xfc10ffff] mem +PCI: 00:0b.0 mem: next_base: fc110000 size: 100000 align: 20 gran: 20 done +PCI: 00:0c.0 mem: base:fc200000 size:100000 align:20 gran:20 limit:fc2fffff +PCI: 03:00.0 10 * [0xfc200000 - 0xfc20ffff] mem +PCI: 00:0c.0 mem: next_base: fc210000 size: 100000 align: 20 gran: 20 done +PCI: 00:0d.0 mem: base:fc3fffff size:0 align:20 gran:20 limit:fc3fffff +PCI: 00:0d.0 mem: next_base: fc3fffff size: 0 align: 20 gran: 20 done +PCI: 00:0e.0 mem: base:fc3fffff size:0 align:20 gran:20 limit:fc3fffff +PCI: 00:0e.0 mem: next_base: fc3fffff size: 0 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +0: mmio_basek=00300000, basek=00400000, limitk=00500000 +1: mmio_basek=00300000, basek=00500000, limitk=00600000 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +VGA: PCI: 00:18.0 (aka node 0) link 1 has VGA device +PCI: 00:18.0 110d8 <- [0x0000001000 - 0x0000003fff] size 0x00003000 gran 0x0c io +PCI: 00:18.0 110b8 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x14 prefmem +PCI: 00:18.0 110b0 <- [0x00fc000000 - 0x00fc3fffff] size 0x00400000 gran 0x14 mem +PCI: 00:18.0 assign_resources, bus 0 link: 1 +PCI: 00:01.0 10 <- [0x0000002c00 - 0x0000002c7f] size 0x00000080 gran 0x07 io +PCI: 00:01.0 60 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io +PCI: 00:01.0 64 <- [0x0000002400 - 0x00000024ff] size 0x00000100 gran 0x08 io +PCI: 00:01.0 68 <- [0x0000002800 - 0x00000028ff] size 0x00000100 gran 0x08 io +PCI: 00:01.0 assign_resources, bus 0 link: 0 +PNP: 002e.0 60 <- [0x00000003f0 - 0x00000003f7] size 0x00000008 gran 0x03 io +PNP: 002e.0 70 <- [0x0000000006 - 0x0000000006] size 0x00000001 gran 0x00 irq +PNP: 002e.0 74 <- [0x0000000002 - 0x0000000002] size 0x00000001 gran 0x00 drq +PNP: 002e.2 60 <- [0x00000003f8 - 0x00000003ff] size 0x00000008 gran 0x03 io +PNP: 002e.2 70 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 irq +PNP: 002e.3 60 <- [0x00000002f8 - 0x00000002ff] size 0x00000008 gran 0x03 io +PNP: 002e.3 70 <- [0x0000000003 - 0x0000000003] size 0x00000001 gran 0x00 irq +PNP: 002e.3 f1 <- [0x0000000004 - 0x0000000004] size 0x00000001 gran 0x00 io +PNP: 002e.5 60 <- [0x0000000060 - 0x0000000060] size 0x00000001 gran 0x00 io +PNP: 002e.5 62 <- [0x0000000064 - 0x0000000064] size 0x00000001 gran 0x00 io +PNP: 002e.5 70 <- [0x0000000001 - 0x0000000001] size 0x00000001 gran 0x00 irq +PNP: 002e.5 72 <- [0x000000000c - 0x000000000c] size 0x00000001 gran 0x00 irq +ERROR: PNP: 002e.5 f0 irq size: 0x0000000001 not assigned +ERROR: PNP: 002e.9 30 irq size: 0x0000000001 not assigned +ERROR: PNP: 002e.9 f0 irq size: 0x0000000001 not assigned +ERROR: PNP: 002e.9 f1 irq size: 0x0000000001 not assigned +PNP: 002e.b 60 <- [0x0000000290 - 0x0000000297] size 0x00000008 gran 0x03 io +PNP: 002e.b 70 <- [0x0000000005 - 0x0000000005] size 0x00000001 gran 0x00 irq +PCI: 00:01.0 assign_resources, bus 0 link: 0 +PCI: 00:01.0 14 <- [0x00fec00000 - 0x00fec00fff] size 0x00001000 gran 0x0c mem +PCI: 00:01.0 44 <- [0x00fed00000 - 0x00fed00fff] size 0x00001000 gran 0x0c mem +PCI: 00:01.1 10 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io +PCI: 00:01.1 20 <- [0x0000002c80 - 0x0000002cbf] size 0x00000040 gran 0x06 io +PCI: 00:01.1 24 <- [0x0000002cc0 - 0x0000002cff] size 0x00000040 gran 0x06 io +PCI: 00:01.1 assign_resources, bus 1 link: 0 +PCI: 00:01.1 assign_resources, bus 1 link: 0 +PCI: 00:02.0 10 <- [0x00fc300000 - 0x00fc300fff] size 0x00001000 gran 0x0c mem +PCI: 00:02.1 10 <- [0x00fc303000 - 0x00fc3030ff] size 0x00000100 gran 0x08 mem +PCI: 00:06.0 20 <- [0x0000003020 - 0x000000302f] size 0x00000010 gran 0x04 io +PCI: 00:07.0 10 <- [0x0000003050 - 0x0000003057] size 0x00000008 gran 0x03 io +PCI: 00:07.0 14 <- [0x0000003070 - 0x0000003073] size 0x00000004 gran 0x02 io +PCI: 00:07.0 18 <- [0x0000003058 - 0x000000305f] size 0x00000008 gran 0x03 io +PCI: 00:07.0 1c <- [0x0000003074 - 0x0000003077] size 0x00000004 gran 0x02 io +PCI: 00:07.0 20 <- [0x0000003030 - 0x000000303f] size 0x00000010 gran 0x04 io +PCI: 00:07.0 24 <- [0x00fc301000 - 0x00fc301fff] size 0x00001000 gran 0x0c mem +PCI: 00:08.0 10 <- [0x0000003060 - 0x0000003067] size 0x00000008 gran 0x03 io +PCI: 00:08.0 14 <- [0x0000003078 - 0x000000307b] size 0x00000004 gran 0x02 io +PCI: 00:08.0 18 <- [0x0000003068 - 0x000000306f] size 0x00000008 gran 0x03 io +PCI: 00:08.0 1c <- [0x000000307c - 0x000000307f] size 0x00000004 gran 0x02 io +PCI: 00:08.0 20 <- [0x0000003040 - 0x000000304f] size 0x00000010 gran 0x04 io +PCI: 00:08.0 24 <- [0x00fc302000 - 0x00fc302fff] size 0x00001000 gran 0x0c mem +PCI: 00:09.0 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io +PCI: 00:09.0 24 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x14 bus 01 prefmem +PCI: 00:09.0 20 <- [0x00fc000000 - 0x00fc0fffff] size 0x00100000 gran 0x14 bus 01 mem +PCI: 00:09.0 assign_resources, bus 1 link: 0 +PCI: 01:04.0 10 <- [0x00f8000000 - 0x00fbffffff] size 0x04000000 gran 0x1a prefmem +PCI: 01:04.0 14 <- [0x00fc000000 - 0x00fc03ffff] size 0x00040000 gran 0x12 mem +PCI: 01:04.0 18 <- [0x0000001000 - 0x000000107f] size 0x00000080 gran 0x07 io +PCI: 00:09.0 assign_resources, bus 1 link: 0 +PCI: 00:0b.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:0b.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:0b.0 20 <- [0x00fc100000 - 0x00fc1fffff] size 0x00100000 gran 0x14 bus 02 mem +PCI: 00:0b.0 assign_resources, bus 2 link: 0 +PCI: 02:00.0 10 <- [0x00fc100000 - 0x00fc10ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:0b.0 assign_resources, bus 2 link: 0 +PCI: 00:0c.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:0c.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:0c.0 20 <- [0x00fc200000 - 0x00fc2fffff] size 0x00100000 gran 0x14 bus 03 mem +PCI: 00:0c.0 assign_resources, bus 3 link: 0 +PCI: 03:00.0 10 <- [0x00fc200000 - 0x00fc20ffff] size 0x00010000 gran 0x10 mem64 +PCI: 00:0c.0 assign_resources, bus 3 link: 0 +PCI: 00:0d.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 04 io +PCI: 00:0d.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 04 prefmem +PCI: 00:0d.0 20 <- [0x00fc3fffff - 0x00fc3ffffe] size 0x00000000 gran 0x14 bus 04 mem +PCI: 00:0d.0 assign_resources, bus 4 link: 0 +PCI: 00:0d.0 assign_resources, bus 4 link: 0 +PCI: 00:0e.0 1c <- [0x0000003fff - 0x0000003ffe] size 0x00000000 gran 0x0c bus 05 io +PCI: 00:0e.0 24 <- [0x00fbffffff - 0x00fbfffffe] size 0x00000000 gran 0x14 bus 05 prefmem +PCI: 00:0e.0 20 <- [0x00fc3fffff - 0x00fc3ffffe] size 0x00000000 gran 0x14 bus 05 mem +PCI: 00:18.0 assign_resources, bus 0 link: 1 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: 01 + APIC: 02 + APIC: 03 + APIC: 04 + APIC: 05 + APIC: 06 + APIC: 07 + DOMAIN: 0000 child on link 0 PCI: 00:18.0 + DOMAIN: 0000 resource base 1000 size 3000 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base f8000000 size 4400000 align 26 gran 0 limit febfffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 + DOMAIN: 0000 resource base 0 size c0000000 align 0 gran 0 limit 0 flags e0004200 index 7 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 + DOMAIN: 0000 resource base c0000 size bff40000 align 0 gran 0 limit 0 flags e0004200 index 20 + DOMAIN: 0000 resource base 100000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 30 + DOMAIN: 0000 resource base 140000000 size 40000000 align 0 gran 0 limit 0 flags e0004200 index 41 + PCI: 00:18.0 child on link 0 PCI: 00:00.0 + PCI: 00:18.0 resource base 1000 size 3000 align 12 gran 12 limit 3fff flags 60080100 index 110d8 + PCI: 00:18.0 resource base f8000000 size 4000000 align 26 gran 20 limit fbffffff flags 60081200 index 110b8 + PCI: 00:18.0 resource base fc000000 size 400000 align 20 gran 20 limit fc3fffff flags 60080200 index 110b0 + PCI: 00:00.0 + PCI: 00:01.0 child on link 0 PNP: 002e.0 + PCI: 00:01.0 resource base 2c00 size 80 align 7 gran 7 limit 2c7f flags 60000100 index 10 + PCI: 00:01.0 resource base fec00000 size 1000 align 12 gran 12 limit ffffffff flags e0000200 index 14 + PCI: 00:01.0 resource base fed00000 size 1000 align 12 gran 12 limit ffffffff flags e0000200 index 44 + PCI: 00:01.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 60 + PCI: 00:01.0 resource base 2400 size 100 align 8 gran 8 limit 24ff flags 60000100 index 64 + PCI: 00:01.0 resource base 2800 size 100 align 8 gran 8 limit 28ff flags 60000100 index 68 + PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PNP: 002e.0 + PNP: 002e.0 resource base 3f0 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.0 resource base 6 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.0 resource base 2 size 1 align 0 gran 0 limit 0 flags e0000800 index 74 + PNP: 002e.1 + PNP: 002e.1 resource base 0 size 8 align 3 gran 3 limit 7ff flags 100 index 60 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.1 resource base 0 size 1 align 0 gran 0 limit 0 flags 800 index 74 + PNP: 002e.2 + PNP: 002e.2 resource base 3f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.2 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.3 + PNP: 002e.3 resource base 2f8 size 8 align 3 gran 3 limit 7ff flags e0000100 index 60 + PNP: 002e.3 resource base 3 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.3 resource base 4 size 1 align 0 gran 0 limit 0 flags e0000500 index f1 + PNP: 002e.5 + PNP: 002e.5 resource base 60 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 60 + PNP: 002e.5 resource base 64 size 1 align 0 gran 0 limit ffffffff flags e0000100 index 62 + PNP: 002e.5 resource base 1 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PNP: 002e.5 resource base c size 1 align 0 gran 0 limit 0 flags e0000400 index 72 + PNP: 002e.5 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.7 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit ffffffff flags 100 index 60 + PNP: 002e.7 resource base 0 size 2 align 1 gran 1 limit 7ff flags 100 index 62 + PNP: 002e.7 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.8 + PNP: 002e.9 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 30 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f0 + PNP: 002e.9 resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index f1 + PNP: 002e.a + PNP: 002e.a resource base 0 size 1 align 0 gran 0 limit 0 flags 400 index 70 + PNP: 002e.b + PNP: 002e.b resource base 290 size 8 align 3 gran 3 limit fff flags e0000100 index 60 + PNP: 002e.b resource base 5 size 1 align 0 gran 0 limit 0 flags e0000400 index 70 + PCI: 00:01.1 child on link 0 I2C: 01:50 + PCI: 00:01.1 resource base 3000 size 20 align 5 gran 5 limit 301f flags 60000100 index 10 + PCI: 00:01.1 resource base 2c80 size 40 align 6 gran 6 limit 2cbf flags 60000100 index 20 + PCI: 00:01.1 resource base 2cc0 size 40 align 6 gran 6 limit 2cff flags 60000100 index 24 + I2C: 01:50 + I2C: 01:51 + I2C: 01:52 + I2C: 01:53 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:2f + PCI: 00:02.0 + PCI: 00:02.0 resource base fc300000 size 1000 align 12 gran 12 limit fc300fff flags 60000200 index 10 + PCI: 00:02.1 + PCI: 00:02.1 resource base fc303000 size 100 align 8 gran 8 limit fc3030ff flags 60000200 index 10 + PCI: 00:04.0 + PCI: 00:04.1 + PCI: 00:06.0 + PCI: 00:06.0 resource base 3020 size 10 align 4 gran 4 limit 302f flags 60000100 index 20 + PCI: 00:07.0 + PCI: 00:07.0 resource base 3050 size 8 align 3 gran 3 limit 3057 flags 60000100 index 10 + PCI: 00:07.0 resource base 3070 size 4 align 2 gran 2 limit 3073 flags 60000100 index 14 + PCI: 00:07.0 resource base 3058 size 8 align 3 gran 3 limit 305f flags 60000100 index 18 + PCI: 00:07.0 resource base 3074 size 4 align 2 gran 2 limit 3077 flags 60000100 index 1c + PCI: 00:07.0 resource base 3030 size 10 align 4 gran 4 limit 303f flags 60000100 index 20 + PCI: 00:07.0 resource base fc301000 size 1000 align 12 gran 12 limit fc301fff flags 60000200 index 24 + PCI: 00:08.0 + PCI: 00:08.0 resource base 3060 size 8 align 3 gran 3 limit 3067 flags 60000100 index 10 + PCI: 00:08.0 resource base 3078 size 4 align 2 gran 2 limit 307b flags 60000100 index 14 + PCI: 00:08.0 resource base 3068 size 8 align 3 gran 3 limit 306f flags 60000100 index 18 + PCI: 00:08.0 resource base 307c size 4 align 2 gran 2 limit 307f flags 60000100 index 1c + PCI: 00:08.0 resource base 3040 size 10 align 4 gran 4 limit 304f flags 60000100 index 20 + PCI: 00:08.0 resource base fc302000 size 1000 align 12 gran 12 limit fc302fff flags 60000200 index 24 + PCI: 00:09.0 child on link 0 PCI: 01:04.0 + PCI: 00:09.0 resource base 1000 size 1000 align 12 gran 12 limit 1fff flags 60080102 index 1c + PCI: 00:09.0 resource base f8000000 size 4000000 align 26 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:09.0 resource base fc000000 size 100000 align 20 gran 20 limit fc0fffff flags 60080202 index 20 + PCI: 01:04.0 + PCI: 01:04.0 resource base f8000000 size 4000000 align 26 gran 26 limit fbffffff flags 60001200 index 10 + PCI: 01:04.0 resource base fc000000 size 40000 align 18 gran 18 limit fc03ffff flags 60000200 index 14 + PCI: 01:04.0 resource base 1000 size 80 align 7 gran 7 limit 107f flags 60000100 index 18 + PCI: 01:04.0 resource base a0000 size 1fc00 align 0 gran 0 limit 0 flags f0000200 index 3 + PCI: 00:0a.0 + PCI: 00:0b.0 child on link 0 PCI: 02:00.0 + PCI: 00:0b.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0b.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0b.0 resource base fc100000 size 100000 align 20 gran 20 limit fc1fffff flags 60080202 index 20 + PCI: 02:00.0 + PCI: 02:00.0 resource base fc100000 size 10000 align 16 gran 16 limit fc10ffff flags 60000201 index 10 + PCI: 00:0c.0 child on link 0 PCI: 03:00.0 + PCI: 00:0c.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0c.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0c.0 resource base fc200000 size 100000 align 20 gran 20 limit fc2fffff flags 60080202 index 20 + PCI: 03:00.0 + PCI: 03:00.0 resource base fc200000 size 10000 align 16 gran 16 limit fc20ffff flags 60000201 index 10 + PCI: 00:0d.0 child on link 0 PCI: 04:00.0 + PCI: 00:0d.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0d.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0d.0 resource base fc3fffff size 0 align 20 gran 20 limit fc3fffff flags 60080202 index 20 + PCI: 04:00.0 + PCI: 00:0e.0 + PCI: 00:0e.0 resource base 3fff size 0 align 12 gran 12 limit 3fff flags 60080102 index 1c + PCI: 00:0e.0 resource base fbffffff size 0 align 20 gran 20 limit fbffffff flags 60081202 index 24 + PCI: 00:0e.0 resource base fc3fffff size 0 align 20 gran 20 limit fc3fffff flags 60080202 index 20 + PCI: 00:0f.0 + PCI: 00:18.1 + PCI: 00:18.2 + PCI: 00:18.3 + PCI: 00:18.4 + PCI: 00:19.0 + PCI: 00:19.1 + PCI: 00:19.2 + PCI: 00:19.3 + PCI: 00:19.4 +Done allocating resources. +BS: BS_DEV_RESOURCES times (us): entry 0 run 3268064 exit 0 +Enabling resources... +PCI: 00:18.0 cmd <- 00 +PCI: 00:18.1 subsystem <- 1043/8162 +PCI: 00:18.1 cmd <- 00 +PCI: 00:18.2 subsystem <- 1043/8162 +PCI: 00:18.2 cmd <- 00 +PCI: 00:18.3 cmd <- 00 +PCI: 00:18.4 subsystem <- 1043/8162 +PCI: 00:18.4 cmd <- 00 +PCI: 00:19.0 cmd <- 00 +PCI: 00:19.1 subsystem <- 1043/8162 +PCI: 00:19.1 cmd <- 00 +PCI: 00:19.2 subsystem <- 1043/8162 +PCI: 00:19.2 cmd <- 00 +PCI: 00:19.3 cmd <- 00 +PCI: 00:19.4 subsystem <- 1043/8162 +PCI: 00:19.4 cmd <- 00 +PCI: 00:00.0 subsystem <- 1043/8162 +PCI: 00:00.0 cmd <- 06 +PCI: 00:01.0 subsystem <- 1043/8162 +PCI: 00:01.0 cmd <- 0f +ck804 lpc decode:PNP: 002e.0, base=0x000003f0, end=0x000003f7 +ck804 lpc decode:PNP: 002e.2, base=0x000003f8, end=0x000003ff +ck804 lpc decode:PNP: 002e.3, base=0x000002f8, end=0x000002ff +ck804 lpc decode:PNP: 002e.3, base=0x00000004, end=0x00000004 +ck804 lpc decode:PNP: 002e.5, base=0x00000060, end=0x00000060 +ck804 lpc decode:PNP: 002e.5, base=0x00000064, end=0x00000064 +ck804 lpc decode:PNP: 002e.b, base=0x00000290, end=0x00000297 +PCI: 00:01.1 subsystem <- 1043/8162 +PCI: 00:01.1 cmd <- 01 +PCI: 00:02.0 subsystem <- 1043/8162 +PCI: 00:02.0 cmd <- 02 +PCI: 00:02.1 subsystem <- 1043/8162 +PCI: 00:02.1 cmd <- 02 +PCI: 00:06.0 subsystem <- 1043/8162 +PCI: 00:06.0 cmd <- 01 +PCI: 00:07.0 subsystem <- 1043/8162 +PCI: 00:07.0 cmd <- 03 +PCI: 00:08.0 subsystem <- 1043/8162 +PCI: 00:08.0 cmd <- 03 +PCI: 00:09.0 bridge ctrl <- 000b +PCI: 00:09.0 cmd <- 07 +PCI: 00:0b.0 bridge ctrl <- 0003 +PCI: 00:0b.0 cmd <- 06 +PCI: 00:0c.0 bridge ctrl <- 0003 +PCI: 00:0c.0 cmd <- 06 +PCI: 00:0d.0 bridge ctrl <- 0003 +PCI: 00:0d.0 cmd <- 00 +PCI: 00:0e.0 bridge ctrl <- 0003 +PCI: 00:0e.0 cmd <- 00 +PCI: 01:04.0 cmd <- 03 +PCI: 02:00.0 subsystem <- 1043/8162 +PCI: 02:00.0 cmd <- 02 +PCI: 03:00.0 subsystem <- 1043/8162 +PCI: 03:00.0 cmd <- 02 +done. +BS: BS_DEV_ENABLE times (us): entry 0 run 162780 exit 0 +Initializing devices... +Root Device init ... +Root Device init finished in 1931 usecs +CPU_CLUSTER: 0 init ... +start_eip=0x00001000, code_size=0x00000031 +CPU1: stack_base 00138000, stack_end 00138ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Initializing CPU #1 +Startup point 1. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +Sending STARTUP #2 to 1. +After apic_write. +CPU: family 10, model 02, stepping 01 +Startup point 1. +Waiting for send to finish... ++nodeid = 00, coreid = 01 +After Startup. +CPU2: stack_base 00137000, stack_end 00137ff8 +Enabling cache +Asserting INIT. +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Waiting for send to finish... ++MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000c0000000 size 0xbff40000 type 6 +0x00000000c0000000 - 0x00000000f8000000 size 0x38000000 type 0 +0x00000000f8000000 - 0x00000000fc000000 size 0x04000000 type 1 +0x00000000fc000000 - 0x0000000100000000 size 0x04000000 type 0 +0x0000000100000000 - 0x0000000180000000 size 0x80000000 type 6 +Deasserting INIT. +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +Waiting for send to finish... ++MTRR: default type WB/UC MTRR counts: 5/3. +MTRR: UC selected as default type. +MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 +MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 +MTRR: 2 base 0x00000000f8000000 mask 0x0000fffffc000000 type 1 +#startup loops: 2. +Sending STARTUP #1 to 2. +After apic_write. + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Startup point 1. +Waiting for send to finish... ++Setting up local apic...Sending STARTUP #2 to 2. +After apic_write. + apic_id: 0x01 done. +Startup point 1. +Waiting for send to finish... ++CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +After Startup. +siblings = 03, CPU3: stack_base 00136000, stack_end 00136ff8 +CPU #1 initialized +Asserting INIT. +Waiting for send to finish... ++Initializing CPU #2 +Deasserting INIT. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +#startup loops: 2. +Sending STARTUP #1 to 3. +After apic_write. +CPU: family 10, model 02, stepping 01 +Startup point 1. +Waiting for send to finish... ++nodeid = 00, coreid = 02 +Sending STARTUP #2 to 3. +After apic_write. +Enabling cache +Startup point 1. +Waiting for send to finish... ++CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +After Startup. +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU4: stack_base 00135000, stack_end 00135ff8 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Asserting INIT. +Setting up local apic...Waiting for send to finish... ++ apic_id: 0x02 done. +Deasserting INIT. +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +Waiting for send to finish... ++siblings = 03, #startup loops: 2. +Sending STARTUP #1 to 4. +After apic_write. +CPU #2 initialized +Startup point 1. +Waiting for send to finish... ++Initializing CPU #3 +Sending STARTUP #2 to 4. +After apic_write. +CPU: vendor AMD device 100f21 +Startup point 1. +Waiting for send to finish... ++Initializing CPU #4 +After Startup. +CPU5: stack_base 00134000, stack_end 00134ff8 +CPU: vendor AMD device 100f21 +Asserting INIT. +Waiting for send to finish... ++CPU: family 10, model 02, stepping 01 +Deasserting INIT. +Waiting for send to finish... ++nodeid = 01, coreid = 00 +#startup loops: 2. +Sending STARTUP #1 to 5. +After apic_write. +CPU: family 10, model 02, stepping 01 +Startup point 1. +Waiting for send to finish... ++Enabling cache +Sending STARTUP #2 to 5. +After apic_write. +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Startup point 1. +Waiting for send to finish... ++MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +After Startup. +CPU6: stack_base 00133000, stack_end 00133ff8 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Asserting INIT. +Setting up local apic...Waiting for send to finish... ++ apic_id: 0x04 done. +Deasserting INIT. +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +Waiting for send to finish... ++siblings = 03, #startup loops: 2. +Sending STARTUP #1 to 6. +After apic_write. +CPU #4 initialized +Startup point 1. +Waiting for send to finish... ++nodeid = 00, coreid = 03 +Sending STARTUP #2 to 6. +After apic_write. +Initializing CPU #6 +Startup point 1. +Waiting for send to finish... ++Enabling cache +After Startup. +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +CPU7: stack_base 00132000, stack_end 00132ff8 +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +Asserting INIT. +Waiting for send to finish... ++ +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Deasserting INIT. +Setting up local apic...Waiting for send to finish... ++ apic_id: 0x03 done. +#startup loops: 2. +Sending STARTUP #1 to 7. +After apic_write. +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +Startup point 1. +Waiting for send to finish... ++siblings = 03, Sending STARTUP #2 to 7. +After apic_write. +CPU #3 initialized +Startup point 1. +Waiting for send to finish... ++CPU: vendor AMD device 100f21 +After Startup. +Initializing CPU #0 +Initializing CPU #5 +CPU: vendor AMD device 100f21 +CPU: family 10, model 02, stepping 01 +nodeid = 00, coreid = 00 +Enabling cache +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +Initializing CPU #7 +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU: vendor AMD device 100f21 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +CPU: family 10, model 02, stepping 01 +Setting up local apic...nodeid = 01, coreid = 02 + apic_id: 0x00 done. +CPU: family 10, model 02, stepping 01 +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +siblings = 03, CPU: vendor AMD device 100f21 +CPU #0 initialized +Waiting for 3 CPUS to stop +Enabling cache +CPU: family 10, model 02, stepping 01 +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +nodeid = 01, coreid = 01 +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +Enabling cache +nodeid = 01, coreid = 03 +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +Setting up local apic... +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + + apic_id: 0x06 done. +Setting up local apic...CPU model: Quad-Core AMD Opteron(tm) Processor 8347 + apic_id: 0x05 done. +siblings = 03, Enabling cache +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +CPU #6 initialized +CPU ID 0x80000001: 100f21 +CPU is Fam 0Fh rev.F or later. We can use TOM2WB for any memory above 4GB +siblings = 03, MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e +MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e +CPU #5 initialized + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Waiting for 2 CPUS to stop +Setting up local apic...Waiting for 1 CPUS to stop + apic_id: 0x07 done. +CPU model: Quad-Core AMD Opteron(tm) Processor 8347 +siblings = 03, CPU #7 initialized +All AP CPUs stopped (15172 loops) +CPU1: stack: 00138000 - 00139000, lowest used address 00138c8c, stack used: 884 bytes +CPU2: stack: 00137000 - 00138000, lowest used address 00137cd4, stack used: 812 bytes +CPU3: stack: 00136000 - 00137000, lowest used address 00136cd4, stack used: 812 bytes +CPU4: stack: 00135000 - 00136000, lowest used address 00135cd4, stack used: 812 bytes +CPU5: stack: 00134000 - 00135000, lowest used address 00134cd4, stack used: 812 bytes +CPU6: stack: 00133000 - 00134000, lowest used address 00133cd4, stack used: 812 bytes +CPU7: stack: 00132000 - 00133000, lowest used address 00132cd4, stack used: 812 bytes +CPU_CLUSTER: 0 init finished in 995136 usecs +PCI: 00:18.0 init ... +PCI: 00:18.0 init finished in 2028 usecs +PCI: 00:18.1 init ... +PCI: 00:18.1 init finished in 2027 usecs +PCI: 00:18.2 init ... +PCI: 00:18.2 init finished in 2018 usecs +PCI: 00:18.3 init ... +NB: Function 3 Misc Control.. done. +PCI: 00:18.3 init finished in 5294 usecs +PCI: 00:18.4 init ... +PCI: 00:18.4 init finished in 2018 usecs +PCI: 00:19.0 init ... +PCI: 00:19.0 init finished in 2018 usecs +PCI: 00:19.1 init ... +PCI: 00:19.1 init finished in 2018 usecs +PCI: 00:19.2 init ... +PCI: 00:19.2 init finished in 2019 usecs +PCI: 00:19.3 init ... +NB: Function 3 Misc Control.. done. +PCI: 00:19.3 init finished in 5277 usecs +PCI: 00:19.4 init ... +PCI: 00:19.4 init finished in 2017 usecs +PCI: 00:00.0 init ... +PCI: 00:00.0 init finished in 2028 usecs +PCI: 00:01.0 init ... +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: Dumping registers + reg 0x0000: 0x00000000 + reg 0x0001: 0x00170011 + reg 0x0002: 0x00000000 +IOAPIC: 24 interrupts +IOAPIC: Enabling interrupts on FSB +IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 +IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 +IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 +lpc_init: pm_base = 2000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +set power on after power fail +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +RTC Init +PCI: 00:01.0 init finished in 164771 usecs +PCI: 00:02.0 init ... +PCI: 00:02.0 init finished in 2026 usecs +PCI: 00:02.1 init ... +PCI: 00:02.1 init finished in 2018 usecs +PCI: 00:06.0 init ... +IDE1 IDE0 +PCI: 00:06.0 init finished in 3096 usecs +PCI: 00:07.0 init ... +SATA S SATA P +PCI: 00:07.0 init finished in 3535 usecs +PCI: 00:08.0 init ... +SATA S SATA P +PCI: 00:08.0 init finished in 3526 usecs +PCI: 00:09.0 init ... +PCI DOMAIN mem base = 0x00f8000000 +[0x50] <-- 0xf8000000 +PCI: 00:09.0 init finished in 7192 usecs +PCI: 00:0b.0 init ... +PCI: 00:0b.0 init finished in 2018 usecs +PCI: 00:0c.0 init ... +PCI: 00:0c.0 init finished in 2019 usecs +PCI: 00:0d.0 init ... +PCI: 00:0d.0 init finished in 2019 usecs +PCI: 00:0e.0 init ... +PCI: 00:0e.0 init finished in 2019 usecs +PNP: 002e.0 init ... +PNP: 002e.0 init finished in 1939 usecs +PNP: 002e.2 init ... +PNP: 002e.2 init finished in 1929 usecs +PNP: 002e.3 init ... +PNP: 002e.3 init finished in 1930 usecs +PNP: 002e.5 init ... +Keyboard init... +PNP: 002e.5 init finished in 351037 usecs +PNP: 002e.9 init ... +PNP: 002e.9 init finished in 1928 usecs +PNP: 002e.b init ... +PNP: 002e.b init finished in 1930 usecs +smbus: PCI: 00:01.1[0]->I2C: 01:2f init ... +ID: 5ca3 +I2C: 01:2f init finished in 101155 usecs +PCI: 01:04.0 init ... +XGI Z9s: initializing video device +XGI VGA: Relocate IO address: 1000 [00001030] +XGI VGA: chipid = 31 +XGI VGA: Framebuffer at 0xf8000000, mapped to 0xf8000000, size 16384k +XGI VGA: MMIO at 0xfc000000, mapped to 0xfc000000, size 256k +XGI VGA: No or unknown bridge type detected +XGI VGA: Default mode is 800x600x16 (60Hz) +XGI VGA: Set new mode: 800x600x16-60 +PCI: 01:04.0 init finished in 42560 usecs +PCI: 02:00.0 init ... +PCI: 02:00.0 init finished in 2017 usecs +PCI: 03:00.0 init ... +PCI: 03:00.0 init finished in 2018 usecs +Devices initialized +Show all devs... After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +DOMAIN: 0000: enabled 1 +PCI: 00:18.0: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:01.0: enabled 1 +PNP: 002e.0: enabled 1 +PNP: 002e.1: enabled 0 +PNP: 002e.2: enabled 1 +PNP: 002e.3: enabled 1 +PNP: 002e.5: enabled 1 +PNP: 002e.7: enabled 0 +PNP: 002e.8: enabled 0 +PNP: 002e.9: enabled 1 +PNP: 002e.a: enabled 0 +PNP: 002e.b: enabled 1 +PCI: 00:01.1: enabled 1 +I2C: 01:50: enabled 1 +I2C: 01:51: enabled 1 +I2C: 01:52: enabled 1 +I2C: 01:53: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:2f: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:04.0: enabled 0 +PCI: 00:04.1: enabled 0 +PCI: 00:06.0: enabled 1 +PCI: 00:07.0: enabled 1 +PCI: 00:08.0: enabled 1 +PCI: 00:09.0: enabled 1 +PCI: 01:04.0: enabled 1 +PCI: 00:0a.0: enabled 0 +PCI: 00:0b.0: enabled 1 +PCI: 02:00.0: enabled 1 +PCI: 00:0c.0: enabled 1 +PCI: 03:00.0: enabled 1 +PCI: 00:0d.0: enabled 1 +PCI: 04:00.0: enabled 0 +PCI: 00:0e.0: enabled 1 +PCI: 00:0f.0: enabled 0 +PCI: 00:18.1: enabled 1 +PCI: 00:18.2: enabled 1 +PCI: 00:18.3: enabled 1 +PCI: 00:18.4: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:19.1: enabled 1 +PCI: 00:19.2: enabled 1 +PCI: 00:19.3: enabled 1 +PCI: 00:19.4: enabled 1 +APIC: 01: enabled 1 +APIC: 02: enabled 1 +APIC: 03: enabled 1 +APIC: 04: enabled 1 +APIC: 05: enabled 1 +APIC: 06: enabled 1 +APIC: 07: enabled 1 +BS: BS_DEV_INIT times (us): entry 0 run 1989467 exit 0 +Finalize devices... +Devices finalized +BS: BS_POST_DEVICE times (us): entry 0 run 3526 exit 0 +BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1 exit 0 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +CONFIG_LOGICAL_CPUS==1: apicid_base: 00000001 +Writing IRQ routing tables to 0xf0000...done. +Writing IRQ routing tables to 0xbffd8000...done. +PIRQ table: 224 bytes. +Wrote the mp table end at: 000f0410 - 000f05cc +Wrote the mp table end at: bffd7010 - bffd71cc +MP table: 460 bytes. +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/dsdt.aml' +CBFS: Found @ offset c00 size 2644 +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/slic' +CBFS: 'fallback/slic' not found. +ACPI: Writing ACPI tables at bffb3000. +ACPI: * FACS +ACPI: * DSDT +ACPI: * FADT +pm_base: 0x2000 +ACPI: added table 1/32, length now 40 +ACPI: * SSDT +processor_brand=Quad-Core AMD Opteron(tm) Processor 8347 +Pstates algorithm ... +Pstate_freq[0] = 1900MHz Pstate_power[0] = 23040mw +Pstate_latency[0] = 5us +Pstate_freq[1] = 1700MHz Pstate_power[1] = 21385mw +Pstate_latency[1] = 5us +Pstate_freq[2] = 1400MHz Pstate_power[2] = 18787mw +Pstate_latency[2] = 5us +Pstate_freq[3] = 1200MHz Pstate_power[3] = 16770mw +Pstate_latency[3] = 5us +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +l 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +PSS: 1900MHz power 23040 control 0x0 status 0x0 +PSS: 1700MHz power 21385 control 0x1 status 0x1 +PSS: 1400MHz power 18787 control 0x2 status 0x2 +PSS: 1200MHz power 16770 control 0x3 status 0x3 +ACPI: added table 2/32, length now 44 +ACPI: * MCFG +ACPI: * TCPA +TCPA log created at bffa3000 +ACPI: added table 3/32, length now 48 +ACPI: * MADT +ACPI: added table 4/32, length now 52 +current = bffb6910 +ACPI: * SRAT at bffb6910 +SRAT: lapic cpu_index=00, node_id=00, apic_id=00 +SRAT: lapic cpu_index=01, node_id=00, apic_id=01 +SRAT: lapic cpu_index=02, node_id=00, apic_id=02 +SRAT: lapic cpu_index=03, node_id=00, apic_id=03 +SRAT: lapic cpu_index=04, node_id=01, apic_id=04 +SRAT: lapic cpu_index=05, node_id=01, apic_id=05 +SRAT: lapic cpu_index=06, node_id=01, apic_id=06 +SRAT: lapic cpu_index=07, node_id=01, apic_id=07 +set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 +set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 +set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 +set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00100000 +set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=00500000, sizek=00100000 +ACPI: added table 5/32, length now 56 +ACPI: * SLIT at bffb6a88 +ACPI: added table 6/32, length now 60 +ACPI: * HPET +ACPI: added table 7/32, length now 64 +ACPI: * SRAT at bffb6b00 +SRAT: lapic cpu_index=00, node_id=00, apic_id=00 +SRAT: lapic cpu_index=01, node_id=00, apic_id=01 +SRAT: lapic cpu_index=02, node_id=00, apic_id=02 +SRAT: lapic cpu_index=03, node_id=00, apic_id=03 +SRAT: lapic cpu_index=04, node_id=01, apic_id=04 +SRAT: lapic cpu_index=05, node_id=01, apic_id=05 +SRAT: lapic cpu_index=06, node_id=01, apic_id=06 +SRAT: lapic cpu_index=07, node_id=01, apic_id=07 +set_srat_mem: dev DOMAIN: 0000, res->index=0007 startk=00000000, sizek=00300000 +set_srat_mem: dev DOMAIN: 0000, res->index=0010 startk=00000000, sizek=00000280 +set_srat_mem: dev DOMAIN: 0000, res->index=0020 startk=00000300, sizek=002ffd00 +set_srat_mem: dev DOMAIN: 0000, res->index=0030 startk=00400000, sizek=00100000 +set_srat_mem: dev DOMAIN: 0000, res->index=0041 startk=00500000, sizek=00100000 +ACPI: added table 8/32, length now 68 +ACPI: * SLIT at bffb6c78 +ACPI: added table 9/32, length now 72 +ACPI: done. +ACPI tables: 15536 bytes. +smbios_write_tables: bffa2000 +Root Device (ASUS KFSN4-DRE) +CPU_CLUSTER: 0 (AMD FAM10 Root Complex) +APIC: 00 (unknown) +DOMAIN: 0000 (AMD FAM10 Root Complex) +PCI: 00:18.0 (AMD FAM10 Northbridge) +PCI: 00:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:01.0 (NVIDIA CK804 Southbridge) +PNP: 002e.0 (Winbond W83627THG Super I/O) +PNP: 002e.1 (Winbond W83627THG Super I/O) +PNP: 002e.2 (Winbond W83627THG Super I/O) +PNP: 002e.3 (Winbond W83627THG Super I/O) +PNP: 002e.5 (Winbond W83627THG Super I/O) +PNP: 002e.7 (Winbond W83627THG Super I/O) +PNP: 002e.8 (Winbond W83627THG Super I/O) +PNP: 002e.9 (Winbond W83627THG Super I/O) +PNP: 002e.a (Winbond W83627THG Super I/O) +PNP: 002e.b (Winbond W83627THG Super I/O) +PCI: 00:01.1 (NVIDIA CK804 Southbridge) +I2C: 01:50 (unknown) +I2C: 01:51 (unknown) +I2C: 01:52 (unknown) +I2C: 01:53 (unknown) +I2C: 01:54 (unknown) +I2C: 01:55 (unknown) +I2C: 01:56 (unknown) +I2C: 01:57 (unknown) +I2C: 01:2f (Nuvoton W83793 Hardware Monitor) +PCI: 00:02.0 (NVIDIA CK804 Southbridge) +PCI: 00:02.1 (NVIDIA CK804 Southbridge) +PCI: 00:04.0 (NVIDIA CK804 Southbridge) +PCI: 00:04.1 (NVIDIA CK804 Southbridge) +PCI: 00:06.0 (NVIDIA CK804 Southbridge) +PCI: 00:07.0 (NVIDIA CK804 Southbridge) +PCI: 00:08.0 (NVIDIA CK804 Southbridge) +PCI: 00:09.0 (NVIDIA CK804 Southbridge) +PCI: 01:04.0 (NVIDIA CK804 Southbridge) +PCI: 00:0a.0 (NVIDIA CK804 Southbridge) +PCI: 00:0b.0 (NVIDIA CK804 Southbridge) +PCI: 02:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:0c.0 (NVIDIA CK804 Southbridge) +PCI: 03:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:0d.0 (NVIDIA CK804 Southbridge) +PCI: 04:00.0 (NVIDIA CK804 Southbridge) +PCI: 00:0e.0 (NVIDIA CK804 Southbridge) +PCI: 00:0f.0 (NVIDIA CK804 Southbridge) +PCI: 00:18.1 (AMD FAM10 Northbridge) +PCI: 00:18.2 (AMD FAM10 Northbridge) +PCI: 00:18.3 (AMD FAM10 Northbridge) +PCI: 00:18.4 (AMD FAM10 Northbridge) +PCI: 00:19.0 (AMD FAM10 Northbridge) +PCI: 00:19.1 (AMD FAM10 Northbridge) +PCI: 00:19.2 (AMD FAM10 Northbridge) +PCI: 00:19.3 (AMD FAM10 Northbridge) +PCI: 00:19.4 (AMD FAM10 Northbridge) +APIC: 01 (unknown) +APIC: 02 (unknown) +APIC: 03 (unknown) +APIC: 04 (unknown) +APIC: 05 (unknown) +APIC: 06 (unknown) +APIC: 07 (unknown) +SMBIOS tables: 553 bytes. +Writing table forward entry at 0x00000500 +Wrote coreboot table at: 00000500, 0x10 bytes, checksum 9fe4 +Table forward entry ends at 0x00000528. +... aligned to 0x00001000 +Writing coreboot table at 0xbff9a000 +rom_table_end = 0xbff9a000 +... aligned to 0xbffa0000 +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 + 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES + 1. 0000000000001000-000000000009ffff: RAM + 2. 00000000000a0000-00000000000bffff: RESERVED + 3. 00000000000c0000-00000000bff99fff: RAM + 4. 00000000bff9a000-00000000bfffffff: CONFIGURATION TABLES + 5. 00000000c0000000-00000000cfffffff: RESERVED + 6. 0000000100000000-000000017fffffff: RAM +CBFS @ 0 size ff8c0 +CBFS: Locating 'cmos_layout.bin' +CBFS: Found @ offset 140 size a90 +Wrote coreboot table at: bff9a000, 0xc08 bytes, checksum 44e8 +coreboot table: 3104 bytes. +IMD ROOT 0. bffff000 00001000 +IMD SMALL 1. bfffe000 00001000 +CAR GLOBALS 2. bfffb000 0000291c +CONSOLE 3. bffdb000 00020000 +AMDMEM INFO 4. bffd9000 0000172c +IRQ TABLE 5. bffd8000 00001000 +SMP TABLE 6. bffd7000 00001000 +ACPI 7. bffb3000 00024000 +54435041 8. bffa3000 00010000 +SMBIOS 9. bffa2000 00000800 +COREBOOT 10. bff9a000 00008000 +IMD small region: + IMD ROOT 0. bfffec00 00000400 + USBDEBUG 1. bfffeba0 00000058 + ROMSTAGE 2. bfffeb80 00000004 + GDT 3. bfffe980 00000200 +BS: BS_WRITE_TABLES times (us): entry 0 run 760427 exit 0 +CBFS provider active. +CBFS @ 0 size ff8c0 +CBFS: Locating 'fallback/payload' +CBFS: Found @ offset 29c80 size 8f395 +'fallback/payload' located at offset: 29cb8 size: 8f395 +Loading segment from rom address 0xfff29cb8 + code (compression=1) + New segment dstaddr 0x8200 memsize 0x17420 srcaddr 0xfff29d0c filesize 0x8215 +Loading segment from rom address 0xfff29cd4 + code (compression=1) + New segment dstaddr 0x100000 memsize 0x2213f0 srcaddr 0xfff31f21 filesize 0x8712c +Loading segment from rom address 0xfff29cf0 + Entry Point 0x00008200 +Bounce Buffer at bfc79000, 3277244 bytes +Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017420 filesz: 0x0000000000008215 +lb: [0x0000000000100000, 0x00000000001fedcc) +Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017420 filesz: 0x0000000000008215 +using LZMA +[ 0x00008200, 00017ce3, 0x0001f620) <- fff29d0c +Clearing Segment: addr: 0x0000000000017ce3 memsz: 0x000000000000793d +dest 00008200, end 0001f620, bouncebuffer bfc79000 +Loading Segment: addr: 0x0000000000100000 memsz: 0x00000000002213f0 filesz: 0x000000000008712c +lb: [0x0000000000100000, 0x00000000001fedcc) +segment: [0x0000000000100000, 0x000000000018712c, 0x00000000003213f0) + bounce: [0x00000000bfc79000, 0x00000000bfd0012c, 0x00000000bfe9a3f0) +Post relocation: addr: 0x00000000bfc79000 memsz: 0x00000000002213f0 filesz: 0x000000000008712c +using LZMA +[ 0xbfc79000, bfe9a3f0, 0xbfe9a3f0) <- fff31f21 +dest bfc79000, end bfe9a3f0, bouncebuffer bfc79000 +move suffix around: from bfd77dcc, to 1fedcc, amount: 122624 +Loaded segments +BS: BS_PAYLOAD_LOAD times (us): entry 0 run 819203 exit 0 +Jumping to boot code at 00008200(bff9a000) +CPU0: stack: 00139000 - 0013a000, lowest used address 00139ae0, stack used: 1312 bytes +entry = 0x00008200 +lb_start = 0x00100000 +lb_size = 0x000fedcc +buffer = 0xbfc79000 +[?25lFREE AS IN FREEDOM + + ++----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. + + Press enter to boot the selected OS, `e' to edit the commands + + before booting or `c' for a command-line.  *Load Operating System  Parse ISOLINUX menu (ahci0)  Parse ISOLINUX menu (USB)  Parse ISOLINUX menu (CD/DVD)  Switch to grubtest.cfg  Search for GRUB configuration (grub.cfg) outside of CBFS         The highlighted entry will be executed automatically in 1s.  The highlighted entry will be executed automatically in 0s. [?25h Booting `Load Operating System' + + + + Failed to boot both default and fallback entries. + + +Press any key to continue... + +[?25lFREE AS IN FREEDOM + + ++----------------------------------------------------------------------------+||||||||||||||||||||||||+----------------------------------------------------------------------------+ Use the ^ and v keys to select which entry is highlighted. + + Press enter to boot the selected OS, `e' to edit the commands + + before booting or `c' for a command-line.  *Load Operating System  Parse ISOLINUX menu (ahci0) diff --git a/i18n/fr_FR/docs/hardware/text/x200s/cblog00.txt b/i18n/fr_FR/docs/hardware/text/x200s/cblog00.txt new file mode 100644 index 00000000..331cb643 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/text/x200s/cblog00.txt @@ -0,0 +1,196 @@ +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +WARNING: Ignoring S4-assertion-width violation. +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using low power mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 14 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 15 + Max clock: 533 MHz + CAS: 0x01c0 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +SFF platform unsupported in RCOMP initialization. +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +Interrupted RAM init, reset required. +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using low power mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 14 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 15 + Max clock: 533 MHz + CAS: 0x01c0 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +SFF platform unsupported in RCOMP initialization. +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +Interrupted RAM init, reset required. +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using low power mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 14 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 15 + Max clock: 533 MHz + CAS: 0x01c0 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +SFF platform unsupported in RCOMP initialization. diff --git a/i18n/fr_FR/docs/hardware/text/x200s/cblog01.txt b/i18n/fr_FR/docs/hardware/text/x200s/cblog01.txt new file mode 100644 index 00000000..afad2fed --- /dev/null +++ b/i18n/fr_FR/docs/hardware/text/x200s/cblog01.txt @@ -0,0 +1,1569 @@ +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +WARNING: Ignoring S4-assertion-width violation. +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using high performance mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Bank 1 populated: + Raw card type: F + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +DIMMs support 666 MHz, but chipset only runs at up to 533. Limiting... +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +Memory configured in dual-channel assymetric mode. +Memory map: +TOM = 512MB +TOLUD = 512MB +TOUUD = 512MB +REMAP: base = 65535MB + limit = 0MB +usedMEsize: 0MB +Performing Jedec initialization at address 0x00000000. +Performing Jedec initialization at address 0x08000000. +Performing Jedec initialization at address 0x10000000. +Performing Jedec initialization at address 0x18000000. +Final timings for group 0 on channel 0: 6.1.0.2.2 +Final timings for group 1 on channel 0: 6.0.2.6.1 +Final timings for group 2 on channel 0: 6.1.0.8.7 +Final timings for group 3 on channel 0: 6.1.0.7.1 +Final timings for group 0 on channel 1: 6.1.0.0.6 +Final timings for group 1 on channel 1: 6.0.2.3.4 +Final timings for group 2 on channel 1: 6.1.0.6.6 +Final timings for group 3 on channel 1: 6.1.0.3.6 +Lower bound for byte lane 0 on channel 0: 0.0 +Upper bound for byte lane 0 on channel 0: 10.1 +Final timings for byte lane 0 on channel 0: 5.0 +Lower bound for byte lane 1 on channel 0: 0.0 +Upper bound for byte lane 1 on channel 0: 11.1 +Final timings for byte lane 1 on channel 0: 5.4 +Lower bound for byte lane 2 on channel 0: 0.0 +Upper bound for byte lane 2 on channel 0: 11.3 +Final timings for byte lane 2 on channel 0: 5.5 +Lower bound for byte lane 3 on channel 0: 0.0 +Upper bound for byte lane 3 on channel 0: 10.2 +Final timings for byte lane 3 on channel 0: 5.1 +Lower bound for byte lane 4 on channel 0: 0.0 +Upper bound for byte lane 4 on channel 0: 10.2 +Final timings for byte lane 4 on channel 0: 5.1 +Lower bound for byte lane 5 on channel 0: 0.0 +Upper bound for byte lane 5 on channel 0: 8.6 +Final timings for byte lane 5 on channel 0: 4.3 +Lower bound for byte lane 6 on channel 0: 0.0 +Upper bound for byte lane 6 on channel 0: 11.2 +Final timings for byte lane 6 on channel 0: 5.5 +Lower bound for byte lane 7 on channel 0: 0.0 +Upper bound for byte lane 7 on channel 0: 9.3 +Final timings for byte lane 7 on channel 0: 4.5 +Lower bound for byte lane 0 on channel 1: 0.0 +Upper bound for byte lane 0 on channel 1: 10.0 +Final timings for byte lane 0 on channel 1: 5.0 +Lower bound for byte lane 1 on channel 1: 0.0 +Upper bound for byte lane 1 on channel 1: 11.2 +Final timings for byte lane 1 on channel 1: 5.5 +Lower bound for byte lane 2 on channel 1: 0.0 +Upper bound for byte lane 2 on channel 1: 10.3 +Final timings for byte lane 2 on channel 1: 5.1 +Lower bound for byte lane 3 on channel 1: 0.0 +Upper bound for byte lane 3 on channel 1: 9.6 +Final timings for byte lane 3 on channel 1: 4.7 +Lower bound for byte lane 4 on channel 1: 0.0 +Upper bound for byte lane 4 on channel 1: 11.3 +Final timings for byte lane 4 on channel 1: 5.5 +Lower bound for byte lane 5 on channel 1: 0.0 +Upper bound for byte lane 5 on channel 1: 8.4 +Final timings for byte lane 5 on channel 1: 4.2 +Lower bound for byte lane 6 on channel 1: 0.0 +Upper bound for byte lane 6 on channel 1: 11.2 +Final timings for byte lane 6 on channel 1: 5.5 +Lower bound for byte lane 7 on channel 1: 0.0 +Upper bound for byte lane 7 on channel 1: 9.4 +Final timings for byte lane 7 on channel 1: 4.6 +Lower bound for group 0 on channel 0: 1.6.3 +Upper bound for group 0 on channel 0: 2.2.7 +Final timings for group 0 on channel 0: 1.10.5 +Lower bound for group 1 on channel 0: 1.5.5 +Upper bound for group 1 on channel 0: 2.1.6 +Final timings for group 1 on channel 0: 1.9.5 +Lower bound for group 2 on channel 0: 2.0.0 +Upper bound for group 2 on channel 0: 2.8.7 +Final timings for group 2 on channel 0: 2.4.3 +Lower bound for group 3 on channel 0: 2.4.2 +Upper bound for group 3 on channel 0: 3.0.4 +Final timings for group 3 on channel 0: 2.8.3 +IGD decoded, subtracting 32M UMA and 4M GTT +Memory configured in dual-channel interleaved mode. +Memory map: +TOM = 8192MB +TOLUD = 3072MB +TOUUD = 9216MB +REMAP: base = 8192MB + limit = 9152MB +usedMEsize: 0MB +Enabling IGD. +Finally disabling PEG in favor of IGD. +PEG x1 disabled, SDVO disabled +ICH9 waits for VC1 negotiation... done. +ICH9 waits for port arbitration table update... done. +CBMEM: root @ bdbff000 254 entries. +exit main() +Trying CBFS ramstage loader. +CBFS: loading stage fallback/ramstage @ 0x100000 (290876 bytes), entry @ 0x100000 +EHCI debug port found in CBMEM. +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 booting... +BS: Entering BS_PRE_DEVICE state. +CBMEM: recovering 6/254 entries from root @ bdbff000 +Moving GDT to bdbda000...ok +BS: Exiting BS_PRE_DEVICE state. +BS: Entering BS_DEV_INIT_CHIPS state. +Initializing i82801ix southbridge... +BS: Exiting BS_DEV_INIT_CHIPS state. +BS: Entering BS_DEV_ENUMERATE state. +Enumerating buses... +Show all devs...Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +APIC: acac: enabled 0 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:03.0: enabled 1 +PCI: 00:03.1: enabled 0 +PCI: 00:03.2: enabled 0 +PCI: 00:03.3: enabled 0 +IOAPIC: 02: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:1a.0: enabled 1 +PCI: 00:1a.1: enabled 1 +PCI: 00:1a.2: enabled 1 +PCI: 00:1a.7: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1c.4: enabled 0 +PCI: 00:1c.5: enabled 0 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:5c: enabled 1 +I2C: 00:5d: enabled 1 +I2C: 00:5e: enabled 1 +I2C: 00:5f: enabled 1 +PCI: 00:1f.5: enabled 0 +PCI: 00:1f.6: enabled 0 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + APIC: acac: enabled 0 + DOMAIN: 0000: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:03.0: enabled 1 + PCI: 00:03.1: enabled 0 + PCI: 00:03.2: enabled 0 + PCI: 00:03.3: enabled 0 + IOAPIC: 02: enabled 1 + PCI: 00:19.0: enabled 1 + PCI: 00:1a.0: enabled 1 + PCI: 00:1a.1: enabled 1 + PCI: 00:1a.2: enabled 1 + PCI: 00:1a.7: enabled 1 + PCI: 00:1b.0: enabled 1 + PCI: 00:1c.0: enabled 1 + PCI: 00:1c.1: enabled 1 + PCI: 00:1c.2: enabled 1 + PCI: 00:1c.3: enabled 1 + PCI: 00:1c.4: enabled 0 + PCI: 00:1c.5: enabled 0 + PCI: 00:1d.0: enabled 1 + PCI: 00:1d.1: enabled 1 + PCI: 00:1d.2: enabled 1 + PCI: 00:1d.7: enabled 1 + PCI: 00:1e.0: enabled 1 + PCI: 00:1f.0: enabled 1 + PNP: 00ff.1: enabled 1 + PNP: 00ff.2: enabled 1 + PCI: 00:1f.2: enabled 1 + PCI: 00:1f.3: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:5c: enabled 1 + I2C: 00:5d: enabled 1 + I2C: 00:5e: enabled 1 + I2C: 00:5f: enabled 1 + PCI: 00:1f.5: enabled 0 + PCI: 00:1f.6: enabled 0 +scan_static_bus for Root Device +CPU_CLUSTER: 0 enabled +Normal boot. +DOMAIN: 0000 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/2a40] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:02.0 [8086/0000] ops +PCI: 00:02.0 [8086/2a42] enabled +PCI: 00:02.1 [8086/2a43] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: Static device PCI: 00:03.0 not found, disabling it. +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:19.0 [8086/10f5] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1a.0 [8086/2937] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1a.1 [8086/2938] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1a.2 [8086/2939] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:1a.7 [8086/0000] ops +PCI: 00:1a.7 [8086/293c] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1b.0 [8086/293e] ops +PCI: 00:1b.0 [8086/293e] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1c.0 [8086/0000] bus ops +PCI: 00:1c.0 [8086/2940] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1c.1 [8086/0000] bus ops +PCI: 00:1c.1 [8086/2942] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1c.2 [8086/0000] bus ops +PCI: 00:1c.2 [8086/2944] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1c.3 [8086/0000] bus ops +PCI: 00:1c.3 [8086/2946] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:1d.0 [8086/2934] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1d.1 [8086/2935] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1d.2 [8086/2936] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:1d.7 [8086/0000] ops +PCI: 00:1d.7 [8086/293a] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1e.0 [8086/0000] bus ops +PCI: 00:1e.0 [8086/2448] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1f.0 [8086/0000] bus ops +PCI: 00:1f.0 [8086/2917] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:1f.2 [8086/0000] ops +PCI: 00:1f.2 [8086/2928] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1f.3 [8086/0000] bus ops +PCI: 00:1f.3 [8086/2930] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: Left over static devices: +IOAPIC: 02 +PCI: Check your devicetree.cb. +do_pci_scan_bridge for PCI: 00:1c.0 +PCI: pci_scan_bus for bus 01 +PCI: pci_scan_bus returning with max=001 +do_pci_scan_bridge returns max 1 +do_pci_scan_bridge for PCI: 00:1c.1 +PCI: pci_scan_bus for bus 02 +PCI: pci_scan_bus returning with max=002 +do_pci_scan_bridge returns max 2 +do_pci_scan_bridge for PCI: 00:1c.2 +PCI: pci_scan_bus for bus 03 +PCI: pci_scan_bus returning with max=003 +do_pci_scan_bridge returns max 3 +do_pci_scan_bridge for PCI: 00:1c.3 +PCI: pci_scan_bus for bus 04 +PCI: pci_scan_bus returning with max=004 +do_pci_scan_bridge returns max 4 +do_pci_scan_bridge for PCI: 00:1e.0 +PCI: pci_scan_bus for bus 05 +PCI: pci_scan_bus returning with max=005 +do_pci_scan_bridge returns max 5 +scan_static_bus for PCI: 00:1f.0 +WARNING: No CMOS option 'touchpad'. +PNP: 00ff.1 enabled +recv_ec_data: 0x37 +recv_ec_data: 0x58 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x32 +recv_ec_data: 0x32 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x06 +recv_ec_data: 0x03 +recv_ec_data: 0x40 +recv_ec_data: 0x10 +EC Firmware ID 7XHT22WW-3.6, Version 4.01A +recv_ec_data: 0x00 +recv_ec_data: 0x10 +recv_ec_data: 0x20 +recv_ec_data: 0x30 +recv_ec_data: 0x00 +recv_ec_data: 0x00 +recv_ec_data: 0xa6 +recv_ec_data: 0x01 +recv_ec_data: 0x70 +dock is not connected +PNP: 00ff.2 enabled +scan_static_bus for PCI: 00:1f.0 done +scan_static_bus for PCI: 00:1f.3 +smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled +scan_static_bus for PCI: 00:1f.3 done +PCI: pci_scan_bus returning with max=005 +scan_static_bus for Root Device done +done +BS: Exiting BS_DEV_ENUMERATE state. +BS: Entering BS_DEV_RESOURCES state. +found VGA at PCI: 00:02.0 +Setting up VGA for PCI: 00:02.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +TOUUD 0x240000000 TOLUD 0xc0000000 TOM 0x200000000 +IGD decoded, subtracting 32M UMA and 4M GTT +Available memory below 4GB: 3036M +Available memory above 4GB: 5120M +Adding UMA memory area base=0xbdc00000 size=0x2400000 +Adding PCIe config bar base=0xf0000000 size=0x4000000 +DOMAIN: 0000 read_resources bus 0 link: 0 +More than one caller of pci_ehci_read_resources from PCI: 00:1a.7 +PCI: 00:1c.0 read_resources bus 1 link: 0 +PCI: 00:1c.0 read_resources bus 1 link: 0 done +PCI: 00:1c.1 read_resources bus 2 link: 0 +PCI: 00:1c.1 read_resources bus 2 link: 0 done +PCI: 00:1c.2 read_resources bus 3 link: 0 +PCI: 00:1c.2 read_resources bus 3 link: 0 done +PCI: 00:1c.3 read_resources bus 4 link: 0 +PCI: 00:1c.3 read_resources bus 4 link: 0 done +PCI: 00:1d.7 EHCI BAR hook registered +PCI: 00:1e.0 read_resources bus 5 link: 0 +PCI: 00:1e.0 read_resources bus 5 link: 0 done +PCI: 00:1f.0 read_resources bus 0 link: 0 +PNP: 00ff.1 missing read_resources +PNP: 00ff.2 missing read_resources +PCI: 00:1f.0 read_resources bus 0 link: 0 done +PCI: 00:1f.3 read_resources bus 1 link: 0 +PCI: 00:1f.3 read_resources bus 1 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: acac + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bdb40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base 100000000 size 140000000 align 0 gran 0 limit 0 flags e0004200 index 5 + DOMAIN: 0000 resource base bdc00000 size 2400000 align 0 gran 0 limit 0 flags f0000200 index 6 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 + PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 + PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 20 + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 10 + PCI: 00:03.0 + PCI: 00:03.1 + PCI: 00:03.2 + PCI: 00:03.3 + PCI: 00:19.0 + PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 + PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 + PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 + PCI: 00:1a.0 + PCI: 00:1a.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1a.1 + PCI: 00:1a.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1a.2 + PCI: 00:1a.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1a.7 + PCI: 00:1a.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.0 + PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.1 + PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.3Unknown device path type: 0 + child on link 0 + PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 +Unknown device path type: 0 + +Unknown device path type: 0 + resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10 +Unknown device path type: 0 + resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14 +Unknown device path type: 0 + resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18 + PCI: 00:1c.4 + PCI: 00:1c.5 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1e.0 + PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:54 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f + PCI: 00:1f.5 + PCI: 00:1f.6 +DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +Unknown device path type: 0 + 18 * [0x0 - 0xfff] io +PCI: 00:1c.3 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 1c * [0x0 - 0xfff] io +PCI: 00:19.0 18 * [0x1000 - 0x101f] io +PCI: 00:1a.0 20 * [0x1020 - 0x103f] io +PCI: 00:1a.1 20 * [0x1040 - 0x105f] io +PCI: 00:1a.2 20 * [0x1060 - 0x107f] io +PCI: 00:1d.0 20 * [0x1080 - 0x109f] io +PCI: 00:1d.1 20 * [0x10a0 - 0x10bf] io +PCI: 00:1d.2 20 * [0x10c0 - 0x10df] io +PCI: 00:1f.2 20 * [0x10e0 - 0x10ff] io +PCI: 00:02.0 20 * [0x1400 - 0x1407] io +PCI: 00:1f.2 10 * [0x1408 - 0x140f] io +PCI: 00:1f.2 18 * [0x1410 - 0x1417] io +PCI: 00:1f.2 14 * [0x1418 - 0x141b] io +PCI: 00:1f.2 1c * [0x141c - 0x141f] io +DOMAIN: 0000 compute_resources_io: base: 1420 size: 1420 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +Unknown device path type: 0 + 14 * [0x0 - 0x7fffff] prefmem +PCI: 00:1c.3 compute_resources_prefmem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +Unknown device path type: 0 + 10 * [0x0 - 0x7fffff] mem +PCI: 00:1c.3 compute_resources_mem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem +PCI: 00:1c.3 24 * [0x10000000 - 0x107fffff] prefmem +PCI: 00:1c.3 20 * [0x10800000 - 0x10ffffff] mem +PCI: 00:02.0 10 * [0x11000000 - 0x113fffff] mem +PCI: 00:02.1 10 * [0x11400000 - 0x114fffff] mem +PCI: 00:19.0 10 * [0x11500000 - 0x1151ffff] mem +PCI: 00:1b.0 10 * [0x11520000 - 0x11523fff] mem +PCI: 00:19.0 14 * [0x11524000 - 0x11524fff] mem +PCI: 00:1f.2 24 * [0x11525000 - 0x115257ff] mem +PCI: 00:1a.7 10 * [0x11525800 - 0x11525bff] mem +PCI: 00:1d.7 10 * [0x11525c00 - 0x11525fff] mem +PCI: 00:1f.3 10 * [0x11526000 - 0x115260ff] mem +DOMAIN: 0000 compute_resources_mem: base: 11526100 size: 11526100 align: 28 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:02.0 +constrain_resources: PCI: 00:02.1 +constrain_resources: PCI: 00:19.0 +constrain_resources: PCI: 00:1a.0 +constrain_resources: PCI: 00:1a.1 +constrain_resources: PCI: 00:1a.2 +constrain_resources: PCI: 00:1a.7 +constrain_resources: PCI: 00:1b.0 +constrain_resources: PCI: 00:1c.0 +constrain_resources: PCI: 00:1c.1 +constrain_resources: PCI: 00:1c.2 +constrain_resources: PCI: 00:1c.3 +Unknown device path type: 0 +constrain_resources: +constrain_resources: PCI: 00:1d.0 +constrain_resources: PCI: 00:1d.1 +constrain_resources: PCI: 00:1d.2 +constrain_resources: PCI: 00:1d.7 +constrain_resources: PCI: 00:1e.0 +constrain_resources: PCI: 00:1f.0 +constrain_resources: PNP: 00ff.1 +constrain_resources: PNP: 00ff.2 +skipping PNP: 00ff.2@60 fixed resource, size=0! +skipping PNP: 00ff.2@62 fixed resource, size=0! +skipping PNP: 00ff.2@64 fixed resource, size=0! +skipping PNP: 00ff.2@66 fixed resource, size=0! +constrain_resources: PCI: 00:1f.2 +constrain_resources: PCI: 00:1f.3 +constrain_resources: I2C: 01:54 +constrain_resources: I2C: 01:55 +constrain_resources: I2C: 01:56 +constrain_resources: I2C: 01:57 +constrain_resources: I2C: 01:5c +constrain_resources: I2C: 01:5d +constrain_resources: I2C: 01:5e +constrain_resources: I2C: 01:5f +avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff + lim->base 000015f0 lim->limit 0000ffff +avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff + lim->base c0000000 lim->limit efffffff +Setting resources... +DOMAIN: 0000 allocate_resources_io: base:15f0 size:1420 align:12 gran:0 limit:ffff +Assigned: PCI: 00:1c.3 1c * [0x2000 - 0x2fff] io +Assigned: PCI: 00:19.0 18 * [0x3000 - 0x301f] io +Assigned: PCI: 00:1a.0 20 * [0x3020 - 0x303f] io +Assigned: PCI: 00:1a.1 20 * [0x3040 - 0x305f] io +Assigned: PCI: 00:1a.2 20 * [0x3060 - 0x307f] io +Assigned: PCI: 00:1d.0 20 * [0x3080 - 0x309f] io +Assigned: PCI: 00:1d.1 20 * [0x30a0 - 0x30bf] io +Assigned: PCI: 00:1d.2 20 * [0x30c0 - 0x30df] io +Assigned: PCI: 00:1f.2 20 * [0x30e0 - 0x30ff] io +Assigned: PCI: 00:02.0 20 * [0x3400 - 0x3407] io +Assigned: PCI: 00:1f.2 10 * [0x3408 - 0x340f] io +Assigned: PCI: 00:1f.2 18 * [0x3410 - 0x3417] io +Assigned: PCI: 00:1f.2 14 * [0x3418 - 0x341b] io +Assigned: PCI: 00:1f.2 1c * [0x341c - 0x341f] io +DOMAIN: 0000 allocate_resources_io: next_base: 3420 size: 1420 align: 12 gran: 0 done +PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.3 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ffff +Unknown device path type: 0 +Assigned: 18 * [0x2000 - 0x2fff] io +PCI: 00:1c.3 allocate_resources_io: next_base: 3000 size: 1000 align: 12 gran: 12 done +PCI: 00:1e.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1e.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:11526100 align:28 gran:0 limit:efffffff +Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem +Assigned: PCI: 00:1c.3 24 * [0xe0000000 - 0xe07fffff] prefmem +Assigned: PCI: 00:1c.3 20 * [0xe0800000 - 0xe0ffffff] mem +Assigned: PCI: 00:02.0 10 * [0xe1000000 - 0xe13fffff] mem +Assigned: PCI: 00:02.1 10 * [0xe1400000 - 0xe14fffff] mem +Assigned: PCI: 00:19.0 10 * [0xe1500000 - 0xe151ffff] mem +Assigned: PCI: 00:1b.0 10 * [0xe1520000 - 0xe1523fff] mem +Assigned: PCI: 00:19.0 14 * [0xe1524000 - 0xe1524fff] mem +Assigned: PCI: 00:1f.2 24 * [0xe1525000 - 0xe15257ff] mem +Assigned: PCI: 00:1a.7 10 * [0xe1525800 - 0xe1525bff] mem +Assigned: PCI: 00:1d.7 10 * [0xe1525c00 - 0xe1525fff] mem +Assigned: PCI: 00:1f.3 10 * [0xe1526000 - 0xe15260ff] mem +DOMAIN: 0000 allocate_resources_mem: next_base: e1526100 size: 11526100 align: 28 gran: 0 done +PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_prefmem: base:e0000000 size:800000 align:22 gran:20 limit:efffffff +Unknown device path type: 0 +Assigned: 14 * [0xe0000000 - 0xe07fffff] prefmem +PCI: 00:1c.3 allocate_resources_prefmem: next_base: e0800000 size: 800000 align: 22 gran: 20 done +PCI: 00:1c.3 allocate_resources_mem: base:e0800000 size:800000 align:22 gran:20 limit:efffffff +Unknown device path type: 0 +Assigned: 10 * [0xe0800000 - 0xe0ffffff] mem +PCI: 00:1c.3 allocate_resources_mem: next_base: e1000000 size: 800000 align: 22 gran: 20 done +PCI: 00:1e.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1e.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1e.0 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +DOMAIN: 0000 03 <- [0x0000000000 - 0x000009ffff] size 0x000a0000 gran 0x00 mem +DOMAIN: 0000 04 <- [0x00000c0000 - 0x00bdbfffff] size 0xbdb40000 gran 0x00 mem +DOMAIN: 0000 05 <- [0x0100000000 - 0x023fffffff] size 0x140000000 gran 0x00 mem +DOMAIN: 0000 06 <- [0x00bdc00000 - 0x00bfffffff] size 0x02400000 gran 0x00 mem +DOMAIN: 0000 07 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem +DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:02.0 10 <- [0x00e1000000 - 0x00e13fffff] size 0x00400000 gran 0x16 mem64 +PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 +PCI: 00:02.0 20 <- [0x0000003400 - 0x0000003407] size 0x00000008 gran 0x03 io +PCI: 00:02.1 10 <- [0x00e1400000 - 0x00e14fffff] size 0x00100000 gran 0x14 mem64 +PCI: 00:19.0 10 <- [0x00e1500000 - 0x00e151ffff] size 0x00020000 gran 0x11 mem +PCI: 00:19.0 14 <- [0x00e1524000 - 0x00e1524fff] size 0x00001000 gran 0x0c mem +PCI: 00:19.0 18 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io +PCI: 00:1a.0 20 <- [0x0000003020 - 0x000000303f] size 0x00000020 gran 0x05 io +PCI: 00:1a.1 20 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io +PCI: 00:1a.2 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io +PCI: 00:1a.7 10 <- [0x00e1525800 - 0x00e1525bff] size 0x00000400 gran 0x0a mem +PCI: 00:1b.0 10 <- [0x00e1520000 - 0x00e1523fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io +PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem +PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 mem +PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.1 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 mem +PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem +PCI: 00:1c.3 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io +PCI: 00:1c.3 24 <- [0x00e0000000 - 0x00e07fffff] size 0x00800000 gran 0x14 bus 04 prefmem +PCI: 00:1c.3 20 <- [0x00e0800000 - 0x00e0ffffff] size 0x00800000 gran 0x14 bus 04 mem +PCI: 00:1c.3 assign_resources, bus 4 link: 0 +Unknown device path type: 0 + missing set_resources +PCI: 00:1c.3 assign_resources, bus 4 link: 0 +PCI: 00:1d.0 20 <- [0x0000003080 - 0x000000309f] size 0x00000020 gran 0x05 io +PCI: 00:1d.1 20 <- [0x00000030a0 - 0x00000030bf] size 0x00000020 gran 0x05 io +PCI: 00:1d.2 20 <- [0x00000030c0 - 0x00000030df] size 0x00000020 gran 0x05 io +PCI: 00:1d.7 EHCI Debug Port hook triggered +PCI: 00:1d.7 10 <- [0x00e1525c00 - 0x00e1525fff] size 0x00000400 gran 0x0a mem +PCI: 00:1d.7 EHCI Debug Port relocated +PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io +PCI: 00:1e.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 05 prefmem +PCI: 00:1e.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 05 mem +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PNP: 00ff.1 missing set_resources +PNP: 00ff.2 missing set_resources +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PCI: 00:1f.2 10 <- [0x0000003408 - 0x000000340f] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x0000003418 - 0x000000341b] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x0000003410 - 0x0000003417] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x000000341c - 0x000000341f] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x00000030e0 - 0x00000030ff] size 0x00000020 gran 0x05 io +PCI: 00:1f.2 24 <- [0x00e1525000 - 0x00e15257ff] size 0x00000800 gran 0x0b mem +PCI: 00:1f.3 10 <- [0x00e1526000 - 0x00e15260ff] size 0x00000100 gran 0x08 mem64 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: acac + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 15f0 size 1420 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base d0000000 size 11526100 align 28 gran 0 limit efffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bdb40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base 100000000 size 140000000 align 0 gran 0 limit 0 flags e0004200 index 5 + DOMAIN: 0000 resource base bdc00000 size 2400000 align 0 gran 0 limit 0 flags f0000200 index 6 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:02.0 + PCI: 00:02.0 resource base e1000000 size 400000 align 22 gran 22 limit efffffff flags 60000201 index 10 + PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18 + PCI: 00:02.0 resource base 3400 size 8 align 3 gran 3 limit ffff flags 60000100 index 20 + PCI: 00:02.1 + PCI: 00:02.1 resource base e1400000 size 100000 align 20 gran 20 limit efffffff flags 60000201 index 10 + PCI: 00:03.0 + PCI: 00:03.1 + PCI: 00:03.2 + PCI: 00:03.3 + PCI: 00:19.0 + PCI: 00:19.0 resource base e1500000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10 + PCI: 00:19.0 resource base e1524000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 14 + PCI: 00:19.0 resource base 3000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 + PCI: 00:1a.0 + PCI: 00:1a.0 resource base 3020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1a.1 + PCI: 00:1a.1 resource base 3040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1a.2 + PCI: 00:1a.2 resource base 3060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1a.7 + PCI: 00:1a.7 resource base e1525800 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base e1520000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10 + PCI: 00:1c.0 + PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.1 + PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.3Unknown device path type: 0 + child on link 0 + PCI: 00:1c.3 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.3 resource base e0000000 size 800000 align 22 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.3 resource base e0800000 size 800000 align 22 gran 20 limit efffffff flags 60080202 index 20 +Unknown device path type: 0 + +Unknown device path type: 0 + resource base e0800000 size 800000 align 22 gran 22 limit efffffff flags 40000200 index 10 +Unknown device path type: 0 + resource base e0000000 size 800000 align 22 gran 22 limit efffffff flags 40001200 index 14 +Unknown device path type: 0 + resource base 2000 size 1000 align 12 gran 12 limit ffff flags 40000100 index 18 + PCI: 00:1c.4 + PCI: 00:1c.5 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 3080 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 30a0 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 30c0 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base e1525c00 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1e.0 + PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1e.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1e.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 3408 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.2 resource base 3418 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.2 resource base 3410 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.2 resource base 341c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.2 resource base 30e0 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 resource base e1525000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:54 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + PCI: 00:1f.3 resource base e1526000 size 100 align 8 gran 8 limit efffffff flags 60000201 index 10 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f + PCI: 00:1f.5 + PCI: 00:1f.6 +Done allocating resources. +BS: Exiting BS_DEV_RESOURCES state. +BS: Entering BS_DEV_ENABLE state. +Enabling resources... +PCI: 00:00.0 subsystem <- 17aa/20e0 +PCI: 00:00.0 cmd <- 06 +PCI: 00:02.0 subsystem <- 17aa/20e4 +PCI: 00:02.0 cmd <- 03 +PCI: 00:02.1 subsystem <- 17aa/20e4 +PCI: 00:02.1 cmd <- 02 +PCI: 00:19.0 subsystem <- 0000/0000 +PCI: 00:19.0 cmd <- 103 +PCI: 00:1a.0 subsystem <- 17aa/20f0 +PCI: 00:1a.0 cmd <- 01 +PCI: 00:1a.1 subsystem <- 17aa/20f0 +PCI: 00:1a.1 cmd <- 01 +PCI: 00:1a.2 subsystem <- 17aa/20f0 +PCI: 00:1a.2 cmd <- 01 +PCI: 00:1a.7 subsystem <- 17aa/20f1 +PCI: 00:1a.7 cmd <- 102 +PCI: 00:1b.0 subsystem <- 17aa/20f2 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 17aa/20f3 +PCI: 00:1c.0 cmd <- 100 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 17aa/20f3 +PCI: 00:1c.1 cmd <- 100 +PCI: 00:1c.2 bridge ctrl <- 0003 +PCI: 00:1c.2 subsystem <- 17aa/20f3 +PCI: 00:1c.2 cmd <- 100 +PCI: 00:1c.3 bridge ctrl <- 0003 +PCI: 00:1c.3 subsystem <- 17aa/20f3 +PCI: 00:1c.3 cmd <- 107 +PCI: 00:1d.0 subsystem <- 17aa/20f0 +PCI: 00:1d.0 cmd <- 01 +PCI: 00:1d.1 subsystem <- 17aa/20f0 +PCI: 00:1d.1 cmd <- 01 +PCI: 00:1d.2 subsystem <- 17aa/20f0 +PCI: 00:1d.2 cmd <- 01 +PCI: 00:1d.7 subsystem <- 17aa/20f1 +PCI: 00:1d.7 cmd <- 102 +PCI: 00:1e.0 bridge ctrl <- 0003 +PCI: 00:1e.0 subsystem <- 17aa/20f4 +PCI: 00:1e.0 cmd <- 100 +PCI: 00:1f.0 subsystem <- 17aa/20f5 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.2 subsystem <- 17aa/20f8 +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 17aa/20f9 +PCI: 00:1f.3 cmd <- 103 +done. +BS: Exiting BS_DEV_ENABLE state. +BS: Entering BS_DEV_INIT state. +Initializing devices... +Root Device init +Keyboard init... +No PS/2 keyboard detected. +CPU_CLUSTER: 0 init +start_eip=0x00001000, code_size=0x00000031 +Initializing SMM handler... ... pmbase = 0x0600 + +SMI_STS: MCSMI +PM1_STS: +GPE0_STS: GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 +ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 +TCO_STS: + ... raise SMI# +Initializing CPU #0 +CPU: vendor Intel device 1067a +CPU: family 06, model 17, stepping 0a +Enabling cache +microcode: sig=0x1067a pf=0x80 revision=0x0 +microcode: updated to revision 0xa0b date=2010-09-28 +CPU: Intel(R) Core(TM)2 Duo CPU L9400 @ 1.86GHz. +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000bdc00000 size 0xbdb40000 type 6 +0x00000000bdc00000 - 0x00000000d0000000 size 0x12400000 type 0 +0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 +0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 +0x0000000100000000 - 0x0000000240000000 size 0x140000000 type 6 +MTRR addr 0x0-0x10 set to 6 type @ 0 +MTRR addr 0x10-0x20 set to 6 type @ 1 +MTRR addr 0x20-0x30 set to 6 type @ 2 +MTRR addr 0x30-0x40 set to 6 type @ 3 +MTRR addr 0x40-0x50 set to 6 type @ 4 +MTRR addr 0x50-0x60 set to 6 type @ 5 +MTRR addr 0x60-0x70 set to 6 type @ 6 +MTRR addr 0x70-0x80 set to 6 type @ 7 +MTRR addr 0x80-0x84 set to 6 type @ 8 +MTRR addr 0x84-0x88 set to 6 type @ 9 +MTRR addr 0x88-0x8c set to 6 type @ 10 +MTRR addr 0x8c-0x90 set to 6 type @ 11 +MTRR addr 0x90-0x94 set to 6 type @ 12 +MTRR addr 0x94-0x98 set to 6 type @ 13 +MTRR addr 0x98-0x9c set to 6 type @ 14 +MTRR addr 0x9c-0xa0 set to 6 type @ 15 +MTRR addr 0xa0-0xa4 set to 0 type @ 16 +MTRR addr 0xa4-0xa8 set to 0 type @ 17 +MTRR addr 0xa8-0xac set to 0 type @ 18 +MTRR addr 0xac-0xb0 set to 0 type @ 19 +MTRR addr 0xb0-0xb4 set to 0 type @ 20 +MTRR addr 0xb4-0xb8 set to 0 type @ 21 +MTRR addr 0xb8-0xbc set to 0 type @ 22 +MTRR addr 0xbc-0xc0 set to 0 type @ 23 +MTRR addr 0xc0-0xc1 set to 6 type @ 24 +MTRR addr 0xc1-0xc2 set to 6 type @ 25 +MTRR addr 0xc2-0xc3 set to 6 type @ 26 +MTRR addr 0xc3-0xc4 set to 6 type @ 27 +MTRR addr 0xc4-0xc5 set to 6 type @ 28 +MTRR addr 0xc5-0xc6 set to 6 type @ 29 +MTRR addr 0xc6-0xc7 set to 6 type @ 30 +MTRR addr 0xc7-0xc8 set to 6 type @ 31 +MTRR addr 0xc8-0xc9 set to 6 type @ 32 +MTRR addr 0xc9-0xca set to 6 type @ 33 +MTRR addr 0xca-0xcb set to 6 type @ 34 +MTRR addr 0xcb-0xcc set to 6 type @ 35 +MTRR addr 0xcc-0xcd set to 6 type @ 36 +MTRR addr 0xcd-0xce set to 6 type @ 37 +MTRR addr 0xce-0xcf set to 6 type @ 38 +MTRR addr 0xcf-0xd0 set to 6 type @ 39 +MTRR addr 0xd0-0xd1 set to 6 type @ 40 +MTRR addr 0xd1-0xd2 set to 6 type @ 41 +MTRR addr 0xd2-0xd3 set to 6 type @ 42 +MTRR addr 0xd3-0xd4 set to 6 type @ 43 +MTRR addr 0xd4-0xd5 set to 6 type @ 44 +MTRR addr 0xd5-0xd6 set to 6 type @ 45 +MTRR addr 0xd6-0xd7 set to 6 type @ 46 +MTRR addr 0xd7-0xd8 set to 6 type @ 47 +MTRR addr 0xd8-0xd9 set to 6 type @ 48 +MTRR addr 0xd9-0xda set to 6 type @ 49 +MTRR addr 0xda-0xdb set to 6 type @ 50 +MTRR addr 0xdb-0xdc set to 6 type @ 51 +MTRR addr 0xdc-0xdd set to 6 type @ 52 +MTRR addr 0xdd-0xde set to 6 type @ 53 +MTRR addr 0xde-0xdf set to 6 type @ 54 +MTRR addr 0xdf-0xe0 set to 6 type @ 55 +MTRR addr 0xe0-0xe1 set to 6 type @ 56 +MTRR addr 0xe1-0xe2 set to 6 type @ 57 +MTRR addr 0xe2-0xe3 set to 6 type @ 58 +MTRR addr 0xe3-0xe4 set to 6 type @ 59 +MTRR addr 0xe4-0xe5 set to 6 type @ 60 +MTRR addr 0xe5-0xe6 set to 6 type @ 61 +MTRR addr 0xe6-0xe7 set to 6 type @ 62 +MTRR addr 0xe7-0xe8 set to 6 type @ 63 +MTRR addr 0xe8-0xe9 set to 6 type @ 64 +MTRR addr 0xe9-0xea set to 6 type @ 65 +MTRR addr 0xea-0xeb set to 6 type @ 66 +MTRR addr 0xeb-0xec set to 6 type @ 67 +MTRR addr 0xec-0xed set to 6 type @ 68 +MTRR addr 0xed-0xee set to 6 type @ 69 +MTRR addr 0xee-0xef set to 6 type @ 70 +MTRR addr 0xef-0xf0 set to 6 type @ 71 +MTRR addr 0xf0-0xf1 set to 6 type @ 72 +MTRR addr 0xf1-0xf2 set to 6 type @ 73 +MTRR addr 0xf2-0xf3 set to 6 type @ 74 +MTRR addr 0xf3-0xf4 set to 6 type @ 75 +MTRR addr 0xf4-0xf5 set to 6 type @ 76 +MTRR addr 0xf5-0xf6 set to 6 type @ 77 +MTRR addr 0xf6-0xf7 set to 6 type @ 78 +MTRR addr 0xf7-0xf8 set to 6 type @ 79 +MTRR addr 0xf8-0xf9 set to 6 type @ 80 +MTRR addr 0xf9-0xfa set to 6 type @ 81 +MTRR addr 0xfa-0xfb set to 6 type @ 82 +MTRR addr 0xfb-0xfc set to 6 type @ 83 +MTRR addr 0xfc-0xfd set to 6 type @ 84 +MTRR addr 0xfd-0xfe set to 6 type @ 85 +MTRR addr 0xfe-0xff set to 6 type @ 86 +MTRR addr 0xff-0x100 set to 6 type @ 87 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 36 bits +MTRR: default type WB/UC MTRR counts: 5/7. +MTRR: WB selected as default type. +MTRR: 0 base 0x00000000bdc00000 mask 0x0000000fffc00000 type 0 +MTRR: 1 base 0x00000000be000000 mask 0x0000000ffe000000 type 0 +MTRR: 2 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 +MTRR: 4 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x00 done. +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 0: 0, 0, 7, 0x21, 35000; encoded: 0x0721 +WARNING: No CMOS option 'hyper_threading'. +CPU: 0 2 siblings +CPU: 0 has sibling 1 +CPU #0 initialized +CPU1: stack_base 00141000, stack_end 00141ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++Sending STARTUP #2 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #1 +Waiting for 1 CPUS to stop +CPU: vendor Intel device 1067a +CPU: family 06, model 17, stepping 0a +Enabling cache +microcode: sig=0x1067a pf=0x80 revision=0x0 +microcode: updated to revision 0xa0b date=2010-09-28 +CPU: Intel(R) Core(TM)2 Duo CPU L9400 @ 1.86GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 36 bits + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x01 done. +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 7, 0x21, 35000; encoded: 0x0721 +CPU: 1 2 siblings +CPU #1 initialized +All AP CPUs stopped (4540 loops) +CPU1: stack: 00141000 - 00142000, lowest used address 00141b6c, stack used: 1172 bytes +DOMAIN: 0000 init +PCI: 00:00.0 init +PCI: 00:02.0 init +Initializing VGA without OPROM. MMIO 0xe1000000 +EDID: +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +Extracted contents: +header: 00 00 00 00 00 00 00 00 +serial number: 00 00 00 00 00 00 00 00 00 00 +version: 00 00 +basic params: 00 00 00 00 00 +chroma info: 00 00 00 00 00 00 00 00 00 00 +established: 00 00 00 +standard: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +descriptor 1: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +descriptor 3: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +descriptor 4: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +extensions: 00 +checksum: 00 + +No header found +Couldn't find GFX clock divisors +PCI: 00:02.1 init +PCI: 00:19.0 init +PCI: 00:1a.0 init +PCI: 00:1a.1 init +PCI: 00:1a.2 init +PCI: 00:1a.7 init +EHCI: Setting up controller.. done. +PCI: 00:1b.0 init +Azalia: base = e1520000 +Azalia: No codec! +PCI: 00:1c.0 init +Initializing ICH9 PCIe root port. +PCI: 00:1c.1 init +Initializing ICH9 PCIe root port. +PCI: 00:1c.2 init +Initializing ICH9 PCIe root port. +PCI: 00:1c.3 init +Initializing ICH9 PCIe root port. +PCI: 00:1d.0 init +PCI: 00:1d.1 init +PCI: 00:1d.2 init +PCI: 00:1d.7 init +EHCI: Setting up controller.. done. +PCI: 00:1e.0 init +PCI: 00:1f.0 init +i82801ix: lpc_init +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +IOAPIC: Dumping registers + reg 0x0000: 0x02000000 + reg 0x0001: 0x00170020 + reg 0x0002: 0x00170020 +IOAPIC: 24 interrupts +IOAPIC: Enabling interrupts on FSB +IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 +IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 +IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 +WARNING: No CMOS option 'power_on_after_fail'. +Set power on after power failure. +WARNING: No CMOS option 'nmi'. +NMI sources disabled. +rtc_failed = 0x4 +RTC Init +RTC: Clear requested +Disabling ACPI via APMC: +done. +Locking SMM. +PCI: 00:1f.2 init +i82801ix_sata: initializing... +SATA controller in AHCI mode. +ABAR: E1525000 +PCI: 00:1f.3 init +smbus: PCI: 00:1f.3[0]->I2C: 01:54 init +smbus: PCI: 00:1f.3[0]->I2C: 01:55 init +smbus: PCI: 00:1f.3[0]->I2C: 01:56 init +smbus: PCI: 00:1f.3[0]->I2C: 01:57 init +smbus: PCI: 00:1f.3[0]->I2C: 01:5c init +Locking EEPROM RFID +init EEPROM done +smbus: PCI: 00:1f.3[0]->I2C: 01:5d init +smbus: PCI: 00:1f.3[0]->I2C: 01:5e init +smbus: PCI: 00:1f.3[0]->I2C: 01:5f init +Devices initialized +Show all devs...After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +APIC: acac: enabled 0 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:03.0: enabled 0 +PCI: 00:03.1: enabled 0 +PCI: 00:03.2: enabled 0 +PCI: 00:03.3: enabled 0 +IOAPIC: 02: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:1a.0: enabled 1 +PCI: 00:1a.1: enabled 1 +PCI: 00:1a.2: enabled 1 +PCI: 00:1a.7: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1c.4: enabled 0 +PCI: 00:1c.5: enabled 0 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:5c: enabled 1 +I2C: 01:5d: enabled 1 +I2C: 01:5e: enabled 1 +I2C: 01:5f: enabled 1 +PCI: 00:1f.5: enabled 0 +PCI: 00:1f.6: enabled 0 +Unknown device path type: 0 +: enabled 1 +APIC: 01: enabled 1 +BS: Exiting BS_DEV_INIT state. +BS: Entering BS_POST_DEVICE state. +Finalize devices... +Devices finalized +BS: Exiting BS_POST_DEVICE state. +BS: Entering BS_OS_RESUME_CHECK state. +BS: Exiting BS_OS_RESUME_CHECK state. +BS: Entering BS_WRITE_TABLES state. +Writing ISA IRQs +no IRQ found for PCI: 00:00.0 +fixed IRQ entry for: PCI: 00:02.0: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:02.1 +no IRQ found for PCI: 00:19.0 +fixed IRQ entry for: PCI: 00:1a.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1a.1: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1a.2: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1a.7: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1b.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1c.0: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:1c.1 +no IRQ found for PCI: 00:1c.2 +no IRQ found for PCI: 00:1c.3 +fixed IRQ entry for: PCI: 00:1d.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1d.1: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1d.2: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1d.7: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:1e.0 +no IRQ found for PCI: 00:1f.0 +fixed IRQ entry for: PCI: 00:1f.2: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1f.3: INTC# -> IOAPIC 2 PIN 18 +Wrote the mp table end at: 000f0010 - 000f0194 +MPTABLE len: 404 +Writing ISA IRQs +no IRQ found for PCI: 00:00.0 +fixed IRQ entry for: PCI: 00:02.0: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:02.1 +no IRQ found for PCI: 00:19.0 +fixed IRQ entry for: PCI: 00:1a.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1a.1: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1a.2: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1a.7: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1b.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1c.0: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:1c.1 +no IRQ found for PCI: 00:1c.2 +no IRQ found for PCI: 00:1c.3 +fixed IRQ entry for: PCI: 00:1d.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1d.1: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1d.2: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1d.7: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:1e.0 +no IRQ found for PCI: 00:1f.0 +fixed IRQ entry for: PCI: 00:1f.2: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1f.3: INTC# -> IOAPIC 2 PIN 18 +Wrote the mp table end at: bdad9010 - bdad9194 +MPTABLE len: 404 +MP table: 404 bytes. +ACPI: Writing ACPI tables at bdab5000. +ACPI: * FACS +ACPI: * DSDT +ACPI: * FADT +ACPI: added table 1/32, length now 40 +ACPI: * SSDT +Found 1 CPU(s) with 2 core(s) each. +clocks between 800 and 2133 MHz. +adding 4 P-States between busratio 6 and 8, incl. P0 +PSS: 1867MHz power 35000 control 0x829 status 0x829 +PSS: 1866MHz power 35000 control 0x721 status 0x721 +PSS: 1600MHz power 15000 control 0x617 status 0x617 +PSS: 800MHz power 12000 control 0x8611 status 0x8611 +clocks between 800 and 2133 MHz. +adding 4 P-States between busratio 6 and 8, incl. P0 +PSS: 1867MHz power 35000 control 0x829 status 0x829 +PSS: 1866MHz power 35000 control 0x721 status 0x721 +PSS: 1600MHz power 15000 control 0x617 status 0x617 +PSS: 800MHz power 12000 control 0x8611 status 0x8611 +ACPI: added table 2/32, length now 44 +ACPI: * MCFG +ACPI: added table 3/32, length now 48 +ACPI: * MADT +ACPI: added table 4/32, length now 52 +current = bdab8e40 +ACPI: * DMAR +ACPI: added table 5/32, length now 56 +current = bdab8ef0 +ACPI: * HPET +ACPI: added table 6/32, length now 60 +ACPI: done. +ACPI tables: 16176 bytes. +smbios_write_tables: bdab3000 +recv_ec_data: 0x37 +recv_ec_data: 0x58 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x32 +recv_ec_data: 0x32 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x06 +recv_ec_data: 0x03 +Root Device (LENOVO ThinkPad X200) +CPU_CLUSTER: 0 (Intel GM45 Northbridge) +APIC: 00 (Socket BGA956 CPU) +APIC: acac (Intel Penryn CPU) +DOMAIN: 0000 (Intel GM45 Northbridge) +PCI: 00:00.0 (Intel GM45 Northbridge) +PCI: 00:02.0 (Intel GM45 Northbridge) +PCI: 00:02.1 (Intel GM45 Northbridge) +PCI: 00:03.0 (Intel GM45 Northbridge) +PCI: 00:03.1 (Intel GM45 Northbridge) +PCI: 00:03.2 (Intel GM45 Northbridge) +PCI: 00:03.3 (Intel GM45 Northbridge) +IOAPIC: 02 (IOAPIC) +PCI: 00:19.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1a.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1a.1 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1a.2 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1a.7 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1b.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.1 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.2 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.3 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.4 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.5 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1d.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1d.1 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1d.2 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1d.7 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1e.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1f.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7) +PNP: 00ff.2 (Lenovo H8 EC) +PCI: 00:1f.2 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1f.3 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +I2C: 01:54 (AT24RF08C) +I2C: 01:55 (AT24RF08C) +I2C: 01:56 (AT24RF08C) +I2C: 01:57 (AT24RF08C) +I2C: 01:5c (AT24RF08C) +I2C: 01:5d (AT24RF08C) +I2C: 01:5e (AT24RF08C) +I2C: 01:5f (AT24RF08C) +PCI: 00:1f.5 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1f.6 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +Unknown device path type: 0 + (unknown) +APIC: 01 (unknown) +SMBIOS tables: 436 bytes. +Writing table forward entry at 0x00000500 +Wrote coreboot table at: 00000500, 0x10 bytes, checksum 9233 +Table forward entry ends at 0x00000528. +... aligned to 0x00001000 +Writing coreboot table at 0xbdaab000 +rom_table_end = 0xbdaab000 +... aligned to 0xbdab0000 + 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES + 1. 0000000000001000-000000000009ffff: RAM + 2. 00000000000c0000-00000000bdaaafff: RAM + 3. 00000000bdaab000-00000000bdbfffff: CONFIGURATION TABLES + 4. 00000000bdc00000-00000000bfffffff: RESERVED + 5. 00000000f0000000-00000000f3ffffff: RESERVED + 6. 0000000100000000-000000023fffffff: RAM +Wrote coreboot table at: bdaab000, 0x8c8 bytes, checksum f79a +coreboot table: 2272 bytes. +CBMEM ROOT 0. bdbff000 00001000 +CAR GLOBALS 1. bdbfe000 00001000 +USBDEBUG 2. bdbfd000 00001000 +CONSOLE 3. bdbdd000 00020000 +TIME STAMP 4. bdbdc000 00001000 +ROMSTAGE 5. bdbdb000 00001000 +GDT 6. bdbda000 00001000 +ACPI RESUME 7. bdada000 00100000 +SMP TABLE 8. bdad9000 00001000 +ACPI 9. bdab5000 00024000 +ACPI GNVS 10. bdab4000 00001000 +SMBIOS 11. bdab3000 00001000 +COREBOOT 12. bdaab000 00008000 +BS: Exiting BS_WRITE_TABLES state. +BS: Entering BS_PAYLOAD_LOAD state. +CBFS: located payload @ ff8341b8, 542448 bytes. +Loading segment from rom address 0xff8341b8 + code (compression=1) + New segment dstaddr 0x8200 memsize 0x17e48 srcaddr 0xff83420c filesize 0x83fc + (cleaned up) New segment addr 0x8200 size 0x17e48 offset 0xff83420c filesize 0x83fc +Loading segment from rom address 0xff8341d4 + code (compression=1) + New segment dstaddr 0x100000 memsize 0x201538 srcaddr 0xff83c608 filesize 0x7c2a0 + (cleaned up) New segment addr 0x100000 size 0x201538 offset 0xff83c608 filesize 0x7c2a0 +Loading segment from rom address 0xff8341f0 + Entry Point 0x00008200 +Bounce Buffer at bd862000, 2393460 bytes +Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017e48 filesz: 0x00000000000083fc +lb: [0x0000000000100000, 0x000000000014703c) +Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017e48 filesz: 0x00000000000083fc +using LZMA +[ 0x00008200, 00018717, 0x00020048) <- ff83420c +Clearing Segment: addr: 0x0000000000018717 memsz: 0x0000000000007931 +dest 00008200, end 00020048, bouncebuffer bd862000 +Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000201538 filesz: 0x000000000007c2a0 +lb: [0x0000000000100000, 0x000000000014703c) +segment: [0x0000000000100000, 0x000000000017c2a0, 0x0000000000301538) + bounce: [0x00000000bd862000, 0x00000000bd8de2a0, 0x00000000bda63538) +Post relocation: addr: 0x00000000bd862000 memsz: 0x0000000000201538 filesz: 0x000000000007c2a0 +using LZMA +[ 0xbd862000, bda63538, 0xbda63538) <- ff83c608 +dest bd862000, end bda63538, bouncebuffer bd862000 +move suffix around: from bd8a903c, to 14703c, amount: 1ba4fc +Loaded segments +BS: Exiting BS_PAYLOAD_LOAD state. +BS: Entering BS_PAYLOAD_BOOT state. +ICH7 watchdog disabled +Jumping to boot code at 00008200 +CPU0: stack: 00142000 - 00143000, lowest used address 00142a28, stack used: 1496 bytes +entry = 0x00008200 +lb_start = 0x00100000 +lb_size = 0x0004703c +buffer = 0xbd862000 diff --git a/i18n/fr_FR/docs/hardware/text/x200s/cblog02.txt b/i18n/fr_FR/docs/hardware/text/x200s/cblog02.txt new file mode 100644 index 00000000..3a590dc2 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/text/x200s/cblog02.txt @@ -0,0 +1,77 @@ +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +WARNING: Ignoring S4-assertion-width violation. +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using high performance mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 14 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 15 + Max clock: 533 MHz + CAS: 0x01c0 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +Memory configured in dual-channel assymetric mode. +Memory map: +TOM = 384MB +TOLUD = 384MB +TOUUD = 384MB +REMAP: base = 65535MB + limit = 0MB +usedMEsize: 0MB +Performing Jedec initialization at address 0x00000000. +Performing Jedec initialization at address 0x08000000. +Performing Jedec initialization at address 0x10000000. +Final timings for group 0 on channel 0: 6.1.0.3.2 +Final timings for group 1 on channel 0: 6.0.2.6.3 +Final timings for group 2 on channel 0: 6.1.2.0.1 +Final timings for group 3 on channel 0: 6.1.0.7.3 +Timing under-/overflow during receive-enable calibration. diff --git a/i18n/fr_FR/docs/hardware/text/x200s/cblog03.txt b/i18n/fr_FR/docs/hardware/text/x200s/cblog03.txt new file mode 100644 index 00000000..d078a48a --- /dev/null +++ b/i18n/fr_FR/docs/hardware/text/x200s/cblog03.txt @@ -0,0 +1,158 @@ +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +WARNING: Ignoring S4-assertion-width violation. +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using high performance mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:ff +2:51:b +DDR mask 4, DDR 3 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +DIMMs support 666 MHz, but chipset only runs at up to 533. Limiting... +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +Memory configured in single-channel mode. +Memory map: +TOM = 128MB +TOLUD = 128MB +TOUUD = 128MB +REMAP: base = 65535MB + limit = 0MB +usedMEsize: 0MB +Performing Jedec initialization at address 0x00000000. +Final timings for group 0 on channel 1: 6.0.2.6.4 +Final timings for group 1 on channel 1: 6.0.2.6.4 +Final timings for group 2 on channel 1: 6.0.2.8.3 +Final timings for group 3 on channel 1: 6.0.2.8.6 +Lower bound for byte lane 0 on channel 1: 0.0 +Upper bound for byte lane 0 on channel 1: 10.4 +Final timings for byte lane 0 on channel 1: 5.2 +Lower bound for byte lane 1 on channel 1: 0.0 +Upper bound for byte lane 1 on channel 1: 11.2 +Final timings for byte lane 1 on channel 1: 5.5 +Lower bound for byte lane 2 on channel 1: 0.0 +Upper bound for byte lane 2 on channel 1: 10.5 +Final timings for byte lane 2 on channel 1: 5.2 +Lower bound for byte lane 3 on channel 1: 0.0 +Upper bound for byte lane 3 on channel 1: 9.7 +Final timings for byte lane 3 on channel 1: 4.7 +Timing overflow during read training. +Read training failure: lower bound. +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +Interrupted RAM init, reset required. +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using high performance mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:ff +2:51:b +DDR mask 4, DDR 3 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +DIMMs support 666 MHz, but chipset only runs at up to 533. Limiting... +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Setting IGD memory frequencies for VCO #1. +Memory configured in single-channel mode. +Memory map: +TOM = 128MB +TOLUD = 128MB +TOUUD = 128MB +REMAP: base = 65535MB + limit = 0MB +usedMEsize: 0MB +Performing Jedec initialization at address 0x00000000. +Final timings for group 0 on channel 1: 6.0.2.7.6 +Final timings for group 1 on channel 1: 6.0.2.6.6 +Final timings for group 2 on channel 1: 6.0.2.8.7 +Final timings for group 3 on channel 1: 6.1.0.2.5 +Lower bound for byte lane 0 on channel 1: 0.0 +Upper bound for byte lane 0 on channel 1: 10.3 +Final timings for byte lane 0 on channel 1: 5.1 +Lower bound for byte lane 1 on channel 1: 0.0 +Upper bound for byte lane 1 on channel 1: 11.3 +Final timings for byte lane 1 on channel 1: 5.5 +Lower bound for byte lane 2 on channel 1: 0.0 +Upper bound for byte lane 2 on channel 1: 10.5 +Final timings for byte lane 2 on channel 1: 5.2 +Lower bound for byte lane 3 on channel 1: 0.0 +Upper bound for byte lane 3 on channel 1: 9.6 +Final timings for byte lane 3 on channel 1: 4.7 +Timing overflow during read training. +Read training failure: lower bound. diff --git a/i18n/fr_FR/docs/hardware/x200.md b/i18n/fr_FR/docs/hardware/x200.md new file mode 100644 index 00000000..99f9ff21 --- /dev/null +++ b/i18n/fr_FR/docs/hardware/x200.md @@ -0,0 +1,280 @@ +--- +title: ThinkPad X200 +... + +It is believed that all X200 laptops are compatible. X200S and X200 +Tablet will also work, [depending on the configuration](#x200s). + +It may be possible to put an X200 motherboard in an X201 chassis, though this +is currently untested by the libreboot project. The same may also apply between +X200S and X201S; again, this is untested. *It's most likely true.* + +There are two possible flash chip sizes for the X200: 4MiB (32Mbit) or +8MiB (64Mbit). This can be identified by the type of flash chip below +the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. + +*The X200 laptops come with the ME (and sometimes AMT in addition) +before flashing libreboot. Libreboot disables and removes it by using a +modified descriptor: see [gm45\_remove\_me.md](gm45_remove_me.md)* +(contains notes, plus instructions) + +Flashing instructions can be found at +[../install/\#flashrom](../install/#flashrom) + +EC update {#ecupdate} +========= + +It is recommended that you update to the latest EC firmware version. The +[EC firmware](../../faq.md#ec-embedded-controller-firmware) is separate from +libreboot, so we don't actually provide that, but if you still have +Lenovo BIOS then you can just run the Lenovo BIOS update utility, which +will update both the BIOS and EC version. See: + +- [../install/#flashrom](../install/#flashrom) +- +- [X200, X200s, X200si BIOS Update](http://pcsupport.lenovo.com/au/en/products/laptops-and-netbooks/thinkpad-x-series-laptops/thinkpad-x200/downloads/ds015007) +- [X200t BIOS Update](http://pcsupport.lenovo.com/au/en/products/laptops-and-netbooks/thinkpad-x-series-tablet-laptops/thinkpad-x200-tablet/downloads/ds018814) + +NOTE: this can only be done when you are using Lenovo BIOS. How to +update the EC firmware while running libreboot is unknown. Libreboot +only replaces the BIOS firmware, not EC. + +Updated EC firmware has several advantages e.g. better battery +handling. + +Battery Recall {#batteryrecall} +========= +[On 21 April 2015, Lenovo expanded a recall on Lenovo batteries found in some ThinkPad models, which includes the X200 and X200S.](https://pcsupport.lenovo.com/cr/en/solutions/hf004122) +To find out if you are affected, use [this Lenovo tool.](https://lenovobattery2014.orderz.com/) +Lenovo advises that owners of the recalled models "should turn off the system, remove the battery, +and only power your ThinkPad by plugging in the AC adapter and power cord." +Upon battery verification, Lenovo will replace recalled batteries free of charge. +Battery replacement instructions for the X200/X200s are found [on this page.](https://pcsupport.lenovo.com/cr/en/parts/pd003507/) + +Compatibility (without blobs) {#compatibility_noblobs} +----------------------------- + +### Hardware virtualization (vt-x) {#hwvirt} + +The X200, when run without CPU microcode updates in coreboot, currently +kernel panics if running QEMU with vt-x enabled on 2 cores for the +guest. With a single core enabled for the guest, the guest panics (but +the host is fine). Working around this in QEMU might be possible; if +not, software virtualization should work fine (it's just slower). + +On GM45 hardware (with libreboot), make sure that the *kvm* and +*kvm\_intel* kernel modules are not loaded, when using QEMU. + +The following errata datasheet from Intel might help with investigation: + + +Anecdotal reports from at least 1 user suggests that some models with +CPU microcode 1067a (on the CPU itself) might work with vt-x in +libreboot. + +X200S and X200 Tablet. {#x200s} +---------------------- + +X200S and X200 Tablet have raminit issues at the time of writing (GS45 +chipset. X200 uses GM45). + +X200S and X200 Tablet are known to work, but only with certain CPU+RAM +configurations. The current stumbling block is RCOMP and SFF, mentioned +in . + +The issues mostly relate to raminit (memory initialization). With an +unpatched coreboot, you get the following: +[text/x200s/cblog00.txt](text/x200s/cblog00.txt). No SODIMM combination +that was tested would work. At first glance, it looks like GS45 (chipset +that X200S uses. X200 uses GM45) is unsupported, but there is a +workaround that can be used to make certain models of the X200S work, +depending on the RAM. + +The datasheet for GS45 describes two modes: low-performance and +high-performance. Low performance uses the SU range of ultra-low voltage +procesors (SU9400, for example), and high-performance uses the SL range +of processors (SL9400, for example). According to datasheets, GS45 +behaves very similarly to GM45 when operating in high-performance mode. + +The theory then was that you could simply remove the checks in coreboot +and make it pass GS45 off as GM45; the idea is that, with a +high-performance mode CPU (SL9400, for example) it would just boot up +and work. + +This suspicion was confirmed with the following log: +[text/x200s/cblog01.txt](text/x200s/cblog01.txt). The memory modules in +this case are 2x4GB. ~~*However, not all configurations work: +[text/x200s/cblog02.txt](text/x200s/cblog02.txt) (2x2GB) and +[text/x200s/cblog03.txt](text/x200s/cblog03.txt) (1x2GB) show a failed +bootup.*~~ *False alarm. The modules were mixed (non-matching). X200S +with high-performance mode CPU will work so long as you use matching +memory modules (doesn't matter what size).* + +This was then pushed as a patch for coreboot, which can be found at + (libreboot merges this patch in +coreboot-libre now. Check the 'getcb' script in src or git). + +### Proper GS45 raminit {#x200s_raminit} + +A new northbridge gs45 should be added to coreboot, based on gm45, and a +new port x200st (X200S and X200T) should be added based on the x200 +port. + +This port would have proper raminit. Alternatively, gs45 (if raminit is +taken to be the only issue with it) can be part of gm45 northbridge +support (and X200S/Tablet being part of the X200 port) with conditional +checks in the raminit that make raminit work differently (as required) +for GS45. nico\_h and pgeorgi/patrickg in the coreboot IRC channel +should know more about raminit on gm45 and likely gs45. + +pgeorgi recommends to run SerialICE on the factory BIOS (for X200S), +comparing it with X200 (factory BIOS) and X200 (gm45 raminit code in +coreboot), to see what the differences are. Then tweak raminit code +based on that. + +LCD compatibility list {#lcd_supported_list} +---------------------- + +LCD panel list (X200 panels listed there): + + +All LCD panels for the X200, X200S and X200 Tablet are known to work. + +The X200 Tablet has a screen rotation button on its bezel. Depending +on the operating system it might or might not rotate the screen, the +digitizer (stylus), or the trackpoint accordingly. Utilities are +provided to fix this at *resources/utilities/x200t-screen-rotation* in +the libreboot git repository. + +### AFFS/IPS panels {#ips} + +#### X200 + +Adapted from + + +Look at wikipedia for difference between TN and IPS panels. IPS have +much better colour/contrast than a regular TN, and will typically have +good viewing angles. + +These seem to be from the X200 tablet. You need to find one without the +glass touchscreen protection on it (might be able to remove it, though). +It also must not have a digitizer on it (again, might be possible to +just simply remove the digitizer). + +- BOE-Hydis HV121WX4-120, HV121WX4-110 or HV121WX4-100 - cheap-ish, + might be hard to find + +- Samsung LTN121AP02-001 - common to find, cheap + +*If your X200 has an LED backlit panel in it, then you also need to get +an inverter and harness cable that is compatible with the CCFL panels. +To see which panel type you have, see +[\#led\_howtotell](#led_howtotell). If you need the inverter/cable, here +are part numbers: 44C9909 for CCFL LVDS cable with bluetooth and camera +connections, and 42W8009 or 42W8010 for the inverter.* + +There are glossy and matte versions of these. Matte means anti-glare, +which is what you want (in this authors opinion). + +Refer to the HMM (hardware maintenance manual) for how to replace the +screen. + +Sources: + +- [ThinkPad Forums - Matte AFFS Panel on + X200](http://forum.thinkpads.com/viewtopic.php?f=2&t=84941) +- [ThinkPad Forums - Parts for X200 AFFS + Mod](http://forum.thinkpads.com/viewtopic.php?p=660662#p660662) +- [ThinkWiki.de - X200 Displayumbau](http://thinkwiki.de/X200_Displayumbau) + +### X200S + + explains that the +X200S screens/assemblies are thinner. You need to replace the whole lid with +one from a normal X200/X201. + +How to tell if it has an LED or CCFL? {#led_howtotell} +------------------------------------- + +Some X200s have a CCFL backlight and some have an LED backlight, in their LCD +panel. This also means that the inverters will vary, so you must be careful if +ever replacing either the panel and/or inverter. (a CCFL inverter is +high-voltage and will destroy an LED backlit panel). + +CCFLs contain mercury. An X200 with a CCFL backlight will (unless it has been +changed to an LED, with the correct inverter. Check with your supplier!) say +the following: *"This product contains Lithium Ion Battery, Lithium Battery and +a lamp which contains mercury; dispose according to local, state or federal +laws"* (one with an LED backlit panel will say something different). + +Hardware register dumps {#regdumps} +----------------------- + +The coreboot wiki +[shows](http://www.coreboot.org/Motherboard_Porting_Guide) how to +collect various logs useful in porting to new boards. Following are +outputs from the X200: + +- BIOS 3.15, EC 1.06 + - [hwdumps/x200/](hwdumps/x200/) + +RAM, S3 and microcode updates {#ram_s3_microcode} +============================= + +Not all memory modules work. Most of the default ones do, but you have +to be careful when upgrading to 8GiB; some modules work, some don't. + +Someone on reddit also did their own research on RAM compatibility: [on +this +post](https://www.reddit.com/r/libreboot/comments/5ax17e/liberated_x200_is_really_picky_with_memory/) + +[This page](http://www.forum.thinkpads.com/viewtopic.php?p=760721) might +be useful for RAM compatibility info (note: coreboot raminit is +different, so this page might be BS) + +pehjota started collecting some steppings for different CPUs on several +X200 laptops. You can get the CPUID by running: + + # dmesg | sed -n 's/.*microcode:.*sig=\([^,]*\),.*$/\1/p' | uniq + +What pehjota wrote: The laptops that have issues resuming from suspend, +as well as a laptop that (as I mentioned earlier in \#libreboot) won't +boot with any Samsung DIMMs, all have CPUID 0x10676 (stepping M0). + +What pehjota wrote: Laptops with CPUID 0x167A (stepping R0) resume +properly every time and work with Samsung DIMMs. I'll need to do more +testing on more units to better confirm these trends, but it looks like +the M0 microcode is very buggy. That would also explain why I didn't +have issues with Samsung DIMMs with the Lenovo BIOS (which would have +microcode updates). I wonder if VT-x works on R0. + +What pehjota wrote: As I said, 10676 is M0 and 1067A is R0; those are +the two CPUIDs and steppings for Intel Core 2 Duo P8xxx CPUs with +factory microcode. (1067 is the family and model, and 6 or A is the +stepping ID.) + +*TODO: check the CPUIDs and test S3 resume and/or KVM on any C2D +systems (including non-P8xxx ones, which I don't have here) you have +available. I'd be curious if you could confirm these results.* + +It might not be coreboot that's buggy with raminit/S3; it might just be down to +the microcode updates. + +Unsorted notes {#unsorted} +-------------- + + do you know if it's possible to flash thinkpads over the LPC debug connector at the front edge? + that would make life much easier for systems like this + all the Wistron manufactured systems have this thing called a "golden finger", normally at the front edge of the board + you can plug a board in which gives diagnostic codes but i'm wondering whether it is capable of more + http://www.endeer.cz/bios.tools/bios.html + +Copyright © 2014, 2015 Leah Rowe \ +Copyright © 2015 Patrick "P. J." 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Documentation +... + +Les informations de versions de Libreboot peuvent être trouvée dans [release.md](release.md). +Vérifiez toujours [libreboot.org](/) pour les mises à jours. +Les nouvelles versions de Libreboot sont annoncées dans la [section actualités](../news/) du site web. + +[Réponses aux questions fréquemment posées à propos de Libreboot](../faq.md). + + +Installer Libreboot +=================== + +- [Sur quelles machines puis-je utiliser Libreboot ?](hardware/) +- [Comment installer Libreboot](install/) + + +Installer des systèmes d'exploitations +============================ + +- [Comment installer GNU+Linux sur une machine Libreboot](gnulinux/) +- [Comment installer BSD sur une machine Libreboot](bsd/) + + + +Informations pour les développeurs +================================= + +- [Comment compiler le code source de Libreboot](git/) +- [Charge utile (payload) Depthcharge](depthcharge/) +- [Charge utile GRUB](grub/) + + + +Autres informations +================ + +- [Divers](misc/) +- [Liste de nom de codes matériels](misc/codenames.md) + + +À propos du projet Libreboot +=========================== + +Libreboot est un remplacement [libre](https://www.gnu.org/philosophy/free-sw.html) +et au code source ouvert pour le BIOS ou l'UEFI, initialisant le matériel et démarrant votre système d'exploitation. +Nous sommes un membre du projet [Peers Community](https://peers.community), une organisation qui supporte le logiciel libre. + +Libreboot est une distribution (distro) de [coreboot](http://coreboot.org/) sans logiciel propriétaire, avec l'intention d'être un remplacement [libre](https://www.gnu.org/philosophy/free-sw.html) du BIOS pour votre ordinateur. Le projet se dirige vers les utilisateurs, tentant de rendre coreboot utilisable facilement autant que possible. + +Libreboot a de nombreux avantages pratiques par rapport aux micrologiciels de démarrage propriétaire, +tel que des vitesses de démarrage plus rapide et une meilleure sécurité. +Vous pouvez [installer GNU+Linux avec le /boot/ chiffré](gnulinux/), [vérifier les signatures GPG sur votre kernel](gnulinux/grub_hardening.md), mettre un kernel dans la puce de flash et plus encore. + + +Le projet libreboot a 3 buts principaux : +------------------------------------------- + +- *Recommander et distribuer seulement du logiciel libre*. +Coreboot distribue certaines pièces de logiciels propriétaires nécessaires dans quelques systèmes. +Des exemples peuvent inclure des choses comme les mises à jour du microcode du processeur (CPU), blobs d'initialisation mémoire et ainsi de suite. +Le projet Coreboot recommande parfois d'ajouter plus de blobs qu'ils ne distribuent pas, comme le Video BIOS ou le *Moteur de management* d'Intel (IME). +Cependant, beaucoup d'individus talentueux et dévoués dans Coreboot travaillent dur pour remplacer ces blobs quand cela est possible. +- *Supporter le plus de matériel possible* Libreboot supporte moins de matériels que coreboot, parce que la majorité des systèmes de coreboot ont besoin de certains logiciels propriétaires pour marcher proprement. +Libreboot est une tentative de supporter autant de matériel que possible, sans aucun logiciel propriétaire. +- *Rendre Coreboot facile à utiliser*. Coreboot est notable pour sa difficulté d'installation, dû à un manque global de documentation et support centrés sur l'utilisateur. +La majorité de gens abandonneront tout simplement avant de tenter d'installer coreboot. + +Libreboot tente de combler ces lacunes en fournissant un système de construction automatisant une bonne partie de la création d'image et de customisation de coreboot. +Deuxiémement, le projet produit de la documentation orientée vers les utilisateurs non-techniques. +Troisiémement, le projet tente de fournir un excellent support utilisateur via les listes de diffusions et IRC. + +Libreboot contient déjà une charge utile (GRUB), flashrom et autres parties nécessaires. +Tout est complétement intégré, d'une façon que la majorité des étapes compliqués qui sont autrement requises, sont déjà faites en avance pour l'utilisateur. + +Vous pouvez télécharger les images ROM pour votre système libreboot et les installer sans avoir à construire quoi que ce soit depuis la source. +Si, cependant, vous êtes intéressé dans le façonnage de votre propre image, le système de construction rend ceci relativement aisé. + + +Libreboot est une distribution de coreboot, pas un embranchement (fork) de coreboot. +--------------------------------------------------------- + +Libreboot est un embrachement de coreboot. De temps à temps, le projet se rebase sur la dernière version de coreboot, avec le nombre de patchs utilisés minimisés. + +Tout nouveau développement de coreboot devrait se faire dans coreboot (en amont), pas libreboot ! Libreboot est à propos du déblobage et empaquetage de coreboot d'une façon amicale à l'utilisateur, où la majorité du travail est déjà fait pour l'utilisateur. + +Par exemple, si vous voulez ajouter une nouvelle carte mère à libreboot, vous devriez l'ajouter d'abord en premier à coreboot. +Libreboot recevra automatiquement votre code plus tard, quand il se mettra à jour lui-même. + + +L'arborescence déblobée de coreboot utilisé dans libreboot est référée en tant que *coreboot-libre*, pour la distinguer comme un composant de *libreboot*. + + +Libreboot est une version 'stable' de coreboot +--------------------------------------------- + +- Coreboot utilise le modèle de la [publication continue](https://fr.wikipedia.org/wiki/Rolling_release), ce qui veut dire que ce n'est pas garantie d'être stable, ou même de marcher un jour donné. +Coreboot a un processus de revue de code strict, mais étant un si large projet avec tant de contributeurs, les régressions sont toujours possibles. +- Libreboot "gèle" sur une version particulière de coreboot, s'assure que tout marche correctement, fait des corrections par dessus et répète cela pour chaque dernière mise à jour de coreboot. +En faisant comme celà, ça fournit une garantie plus forte à l'utilisateur que le micrologiciel sera fiable, et ne cassera pas leur système. + + +Comment sais-je la version que je suis en train d'exécuter? {#version} +======================================== + +Si vous êtes au moins 127 commits après la version 20150518 (message de commit *build/roms/helper: add version information to CBFS*) (ou vous avez quelconque version stable de libreboot *en amont* après 20150518), alors vous pouvez presser C dans la console GRUB, et utilisez cette commande pour trouver quelle version de libreboot vous avez: + + cat (cbfsdisk)/lbversion + +Celà marchera aussi sur les images non versionnées (la chaîne de caractère de la version est générée automatiquement, en utilisant `git describe --tags HEAD`), contruitent à partir du répertoire git. Un fichier nommé `version` sera inclu dans les archives que vous avez téléchargées. + +Si ça existe, vous pouvez extraire ce fichier `lbversion` grâce à l'utilitaire `cbfstool` que libreboot inclut, depuis une image ROM que vous avez soit déchargée ou pas encore flashée. +Dans votre distribution, exécutez cbfstool sur votre image ROM (`libreboot.rom`, dans cet exemple): + + $ ./cbfstool libreboot.rom extract -n lbversion -f lbversion + +Vous aurez maintenant un fichier, nommé `lbversion`, que vous pourriez lire dans n'importe quel programme que vous utilisiez pour la lecture/écriture de fichiers texte. + +Pour git, c'est facile. Vérifiez juste le log git. + +Pour les versions égales ou en dessous 20150518, ou d'instantanés générés à partir du répertoire git en dessous de 127 commits après 20150518, et vous pouvez trouver un fichier nommé *commitid* à l'intérieur des archives. +Si vous utilisez des images de ROM pré-construites venant du projet libreboot, vous pouvez presser C dans GRUB pour accéder au terminal, et ensuite exécutez cette commande: + + lscoreboot + +Vous pouvez trouver une date ici, détaillant quand l'image de la ROM a été construite. +Pour les images pré-construites distribuées par le projet libreboot, c'est une vague approximation de la version que vous avez, parce que les numéros de versions sont datés, et les archives de version sont construites le même jour que la version; vous pouvez corréler cela avec les informations de version dans [release.md](release.md). + +Pour la 20160818, notez que le fichier lbversion manquait du CBFS sur les images GRUB. +Vous pouvez quand même deviner quelle version de libreboot que vous avez en comparant les sommes de contrôle des décharges d'image (images dumps) (avec le descripteur rempli de 00s, et la même est faite aux ROMS de l'archive de la version si vous êtes sur un ordinateur portable GM45). + +Il peut y avoir aussi un fichier ChangeLog dans votre archive de version, comme ça vous pouvez regarder dedans pour deviner quelle version vous avez. + +Vous pouvez aussi vérifier la documentation venant avec vos archives, et dans *docs/release.html* il y aura les informations à propos de la version de libreboot que vous utilisez. + +Généralement parlant, il est conseillé d'utiliser la dernière version de libreboot. + +Copyright © 2014, 2015, 2016 Leah Rowe \ + +Permission est donnée de copier, distribuer et/ou modifier ce document sous les termes de la Licence de documentation libre GNU version 1.3 ou quelconque autre versions publiées plus tard par la Free Software Foundation sans Sections Invariantes, Textes de Page de Garde, et Textes de Dernière de Couverture. + +Une copie de cette license peut être trouvé dans [fdl-1.3.md](fdl-1.3.md). diff --git a/i18n/fr_FR/docs/install/$ b/i18n/fr_FR/docs/install/$ new file mode 100644 index 00000000..cd98e1f1 --- /dev/null +++ b/i18n/fr_FR/docs/install/$ @@ -0,0 +1,384 @@ +--- +Titre: Instructions d'installation +... + +Cette section concerne l'installation de Libreboot sur les cibles supportées. + +NOTE: si vous éxecutiez `flashrom -p internal` pour le flashage basé logiciellement, et vous avez une erreur concernant l'accés à `/dev/mem`, vous devrez redémarrer avec le paramètre de kernel `iomem=relaxed` avant d'éxecuter flashrom, ou utiliser un kernel qui a `CONFIG_STRICT_DEVMEM ` non activé. + +Quels systèmes sont compatibles avec Libreboot ? +-------------------------------------------- + +- [Information à propos de la compatibilité matérielle Libreboot](../hardware) + + +Informations générales +------------------- + +- [Information à propos des images ROM libreboot](#rom) + +Flashage via des méthodes logicielles, sur système: +----------------------------------------- + +- [Comment mettre à jour ou installer libreboot sur tout les systèmes](#flashrom) + +- [How to update or install libreboot on all systems](#flashrom) +- [ASUS KFSN4-DRE](#flashrom) +- [ThinkPad X60/T60 (if running Lenovo BIOS)](#flashrom_lenovobios) +- [Apple MacBook2,1](#flashrom_macbook21) +- [ASUS Chromebook C201](c201.md) + +Mettre en place les programmeurs, pour le flashage externe SPI +----------------------------------------------------------------- + +- [BeagleBone Black Setup](bbb_setup.md) +- [Raspberry Pi Setup](rpi_setup.md) + +Flashage via les méthodes matérielles, sur le système: +----------------------------------------- + +- [Gigabyte GA-G41-ES2L](ga-g41m-es2l.md) +- [Intel D510MO](d510mo.md) +- [Intel D945GCLF](d945gclf.md) +- [ASUS KGPE-D16](kgpe-d16.md) +- [ASUS KCMA-D8](kcma-d8.md) +- [ASUS Chromebook C201](c201.md) +- [ThinkPad X60](x60_unbrick.md) +- [ThinkPad X60 Tablet](x60tablet_unbrick.md) +- [ThinkPad T60](t60_unbrick.md) +- [ThinkPad X200/X200S/X200T](x200_external.md) +- [ThinkPad R400](r400_external.md) +- [ThinkPad T400](t400_external.md) +- [ThinkPad T500](t500_external.md) +- [ThinkPad W500](t500_external.md) + +Information à propos des images ROM libreboot {#rom} +====================================== + +Libreboot distribue des images ROM pré-compilée, construites à partir du code source de libreboot. Ces images sont fournies pour le confort de l'utilisateur, comme ça ils n'ont pas à construire quoi que ce soit depuis la source de leur propre chef. + +Ces images ROM dans chaque archive utilise le suivant à la fin de leur nom de fichier, si elles sont construites avec la charge utile GRUB: `*_*keymap*_*mode*.rom` + +Modes disponibles: vesafb ou txtmode. Les images ROM vesafb sont recommandés pour un usage régulier, mais quand vous flashez pour la première fois utilisez la version txtmode, car elle vient avec Memtext86+, qui demande le text-mode au lieu du framebuffer d'habitude utilisé par l'initialisation des graphiques natifs de coreboot. +La machine devrait être testée avec Memtest86+ après chaque réassemblage ou changement du bios constructeur (d'origine) à cause de différences dans le code de raminit. + +`keymap` peut être une des quelques mappage de touches que le clavier supporte (il y en a quelques un), qui affecte la configuration de la disposition du clavier qui est utilisé dans GRUB. Ca n'a pas d'importance quel image ROM vous utilisez ici, tant que le mappage des touches dans GNU+Linux est concerné. + + +Les mappages de touches sont nommés en accordance avec chaque disposition de clavier supportées dans GRUB. Pour apprendre comment ces mappages de touches sont créés, regardez [../grub/\#grub\_keyboard](../grub/#grub_keyboard) + + +QEMU +---- + +Libreboot arrive avec des images ROM construites pour QEMU par défaut: + +Des exemples de comment utiliser les images ROM de libreboot dans QEMU: + + $ qemu-system-i386 -M q35 -m 512 -bios qemu_q35_ich9_keymap_mode.rom + $ qemu-system-i386 -M pc -m 512 -bios qemu_i440fx_piix4_keymap_mode.rom + +Vous pouvez optionnellement spécifié l'argument `-serial stdio`, comme ça QEMU émulera un terminal en série sur l'entrée/sortie standard (très certainement votre émulateur de terminal ou TTY). + +D'autres arguments sont disponibles pour QEMU. Le manuel contiendra plus d'informations. + +Comment mettre à jour ou installer libreboot (si vous êtes déjà en train d'éxecuter libreboot ou coreboot) {#flashrom} +===================================================================================== + +Sur toutes les cibles actuelles, mettre à jour libreboot peut être accomplit sans désassemblage, +et de ce fait, sans avoir à re-flasher extérieurement en utilisant n'important quel matériel spécialisé. +En d'autres mots, vous pouvez tout faire de façon logicielle, directement depuis le système d'exploitation qui +est en cours d'éxecution sur votre système Libreboot. + +*Si vous êtes en train d'utiliser `libreboot_src` ou git, alors rendez-vous bien sûr +que vous avez compilé les sources en premier (regardez [../git/\#build](../git/#build)).* + +Regardez à la [liste des images ROM](#rom) pour voir quelle image est compatible avec votre appareil. + + +Êtes-vous en train d'exécuter le micrologiciel d'origine propriétaire ? +------------------------------------------------------------- + +Si vous êtes en train d'éxecuter le micrologiciel propriétaire (ni libreboot ou coreboot), alors les instructions de flashage pour votre système vont être différentes. + +Les utilisateurs du X60/T60 éxecutant le micrologiciel propriétaire devrait se référer à [\#flashrom\_lenovobios](#flashrom_lenovobios). Les utilisateurs de MacBook2,1 éxecutant l'EFI d'Apple devrait se référer à [\#flashrom\_macbook21](#flashrom_macbook21) + +Les utilisateurs de X200, se référeront à [x200\_external.md](x200_external.md), ceux de R400 à [r400\_external.md](r400_external.md), ceux de T400 à [t400\_external.md](t400_external.md), et ceux de T500 et W500 à [t500\_external.md](t500_external.md) + + +ASUS KFSN4-DRE? +--------------- + +Le flashage interne devrait marcher comme il faut, même si vous êtes en train +de démarrer le micrologiciel propriétaire. + +Libreboot manque en ce moment de documentation pour re-flasher +extérieurement une puce flash LPC. Cependant, ces cartes mères ont la puce de flash +à l'intérieur d'un socket PLCC, et il est possible d'échanger à chaud +les puces. Si vous voulez sauvegarder votre image connu pour marcher, échangez +simplement à chaud la puce pour un qui est de même capacité, après avoir déchargé +une copie du micrologiciel courant (flashrom -p internal -r yourchosenname.rom), et +flashez ensuite cette puce avec l'image connue pour marcher. Vérifiez si le système +démarre encore, et si il démarre alors il est sécurisé de flashé la nouvelle image +(parce que maintenant vous avez une sauvegarde de la vieille image). + +Garder au moins une puce LPC PLCC en stock avec le micrologiciel fonctionnel dessus +est fortement recommandé, en cas de bousillage. + +*N'ÉCHANGEZ PAS à chaud la puce avec vos mains nues. Utilisez un extracteur de puce PLCC. +Elles peuvent être trouvées en ligne. +Voyez * + +Vérifez la saisie HCL: [../hardware/kfsn4-dre.md](../hardware/kfsn4-dre.md) + +ASUS KGPE-D16? +-------------- + +Si vous avez un BIOS propriétaire, vous avez besoin de flasher libreboot +extérieurement. Voir [kgpe-d16.md](kgpe-d16.md) + +Si vous déjà coreboot ou libreboot installé, sans protection contre l'écriture sur +la puce flash, alors vous pouvez le faire logiciellement (sinon, voir le lien ci-dessus). + +*N'ÉCHANGEZ PAS à chaud la puce avec vos mains nues. Utilisez un extracteur de puce PDIP-8. +Elles peuvent être trouvées en ligne. +Voyez * + +Vérifier l'entrée HCL: [../hardware/kgpe-d16.md](../hardware/kgpe-d16.md) + +ASUS KCMA-D8? +------------- + +Si vous un BIOS propriétaire, nous avons besoin de flasher +libreboot extérieurement. Voir [kmca-d8.md](kmca-d8.md). + +Si vous avez déjà coreboot ou libreboot installé, sans protection +contre l'écriture sur la puce flash, alors vous pouvez le faire +logiciellement (sinon, voir le lien ci-dessus). + +*N'ÉCHANGEZ PAS à chaud la puce avec vos mains nues. Utilisez un extracteur de puce PDIP-8. +Elles peuvent être trouvées en ligne. +Voyez * + +Vérifier l'entrée HCL: [../hardware/kgpe-d16.md](../hardware/kgpe-d16.md) + + +Intel D945GCLF? +--------------- + +Si vous éxecutez le BIOS d'usine Intel original, alors vous aurez +besoin de le flasher extérieurement. Pour des instructions sur comment + faire celà, référez-vous [d945gclf.md](d945gclf.md). + +Sinon, lisez les instructions générales en dessous pour utiliser +le script *flash*. + + +Êtes-vous en train d'éxecuter libreboot (ou coreboot)? +-------------------------------------------------- + +Les utilisateurs X60/T60 devrait être OK avec ce guide. +Si vous avez protégé en écriture la puce flash, référez-vous +silvouplait à [x60\_unbrick.md](x60_unbrick.md), +[x60tablet\_unbrick.md](x60tablet_unbrick.md) ou +[t60\_unbrick.md](t60_unbrick.md). *Cela ne s'applique pas probablement + à vous. La majorité de gens ne protège pas en écriture la puce flash, donc + vous ne l'avez probablement pas fait* + +Similairement, c'est possible de protéger en écriture la puce flash dans +coreboot ou libreboot sur les ordinateurs portables GM45 (X200/R400/T400/T500/W500). +Si vous faites ça, alors vous aurez besoin d'utiliser les liens au-dessus pour +le flashage, traitant votre ordinateur portable comme si il avait le micrologiciel +propriétaire (parce que la puce SPI protégé en écriture aura besoin d'un reflashage, +externe, comme c'est le cas quand on éxecute le micrologiciel propriétaire). + +Si vous n'avez pas protégé en écriture la puce flash,ou elle est +arrivé chez vous sans aucune protection en écriture (*libreboot ne protège +pas en écriture la puce flash par défaut, donc ça s'applique à vous*), continuez à lire! + + +Adresse MAC sur GM45 (X200/R400/T400/T500/W500) +----------------------------------------- + +*Utilisateurs du X200/R400/T400/T500/W500, prenez note:* L'adresse MAC pour le jeu de puces +ethernet embarqué est situé à l'intérieur de la puce flash. Les images ROM de Libreboot pour +ces ordinateurs portables contiennent une adresse MAC générique par défaut, mais ce n'est +pas que vous voulez. *Assurez vous bien de change l'adresse MAC à l'intérieur de l'image ROM +avant de la flasher. Les instructions dans [../hardware/gm45\_remove\_me.html\#ich9gen](../hardware/gm45_remove_me.html#ich9gen) +montrent comment faire celà. + +C'est important que vous changiez l'adresse MAC par défaut, avant flashage. +Elle sera imprimée sur un sticker en bas de l'ordinateur portable, ou il sera +imprimé sur un sticker à côté ou sous la RAM. +Alternativement, et assumant que votre micrologiciel en cours d'exécution à la +bonne adresse MAC en lui, vous pouvez la récupérer depuis votre système d'exploitation. + + +Apple iMac 5,2? +--------------- + +Le flashage interne marche, même quand on flashing depuis l'EFI d'Apple vers Libreboot. +Continuez à lire les instructions ci-dessous. + +*NOTE*: Si vous flashez une plus vieille version de libreboot, la carte mère de l'iMac5,2 est compatible avec le MacBook2,1. +Flashez simplement une image ROM MacBook2,1, et ça devrait marcher. + + +Taille de la puce flash +--------------- + +Utilisez ceci pour trouver: + + # flashrom -p internal + + +Tout bon ? +--------- + +Excellent! On bouge... + +Téléchargez l'archive *libreboot\_util.tar.xz*, et extrayez là. À +l'intérieur vous trouverez un répertoire appelé *flashrom*. Il contient +des fichiers éxecutables compilés statiquement de l'utilitaire *flashrom*, que +vous utiliserez pour re-flasher votre système libreboot. + +Utilisez simplement *cd* sur votre terminal, pour vous mettre sur le répertoire +*libreboot\_util*. À l'intérieur, il y a un script appelé *flash*, qui détectera quelle +architecture de processeur vous avez (e.g. i686, x86\_64) et utilisera l'éxecutable +approprié. Il est aussi possible pour vous de construire ces éxecutables à partir +des archives de code source de libreboot. + +Comment mettre à jour le contenu de la puce flash: + + `$ sudo ./flash update `[`yourrom.rom`](#rom) + +Occasionellement, coreboot change le nom d'une carte mère. Si flashrom se plaint à +propos d'une carte mère qui ne correspond pas, mais vous êtes sur que vous choisissez +l'image ROM correcte, alors éxecutez cette commande alternative: + + `$ sudo ./flash forceupdate `[`yourrom.rom](#rom) + +Vous devriez voir `Vérification du flash... VÉRIFIÉ.` écris à la fin de la sortie +de flashrom. *Éteignez* après que vous voyez ceci, et ensuite démarrez de nouveau après quelques secondes. + +ThinkPad X60/T60: Guide d'installation initiale (si vous êtes en train d'éxecutez le micrologiciel propriétaire) {#flashroms_lenovobios} +================================================================================== + +*Ceci est pour le ThinkPad X60 et T60 pendant que vous êtes en train +d'éxecuter le BIOS de Lenovo. Si vous êtes déjà en train d'éxecuter +coreboot ou libreboot, alors rendez-vous sur [\#flashrom](#flashrom)!* + +*Si vous pouvez, rendez-vous sûr que la batterie RTC n'est pas déchargée. Une batterie RTC déchargé peut amener à un bousillage dû car la valeur du registre BUC n'est pas maintenue..* + +*Si vous êtes en train de flasher un Lenovo ThinkPad T60, assurez-vous de lire +[../hardware/\#supported\_t60\_list](../hardware/#supported_t60_list) + +*Si vous êtes en train d'utilisez libreboot\_src ou git, alors +rendez-vous sûr que vous avez compilé les sources en premier +(voir [../git/\#build](../git/#build))* + +*Attention: ce guide n'instruirera pas l'utiliser sur comment sauvegarder +le micrologiciel original du BIOS Lenovo. Ces sauvegardes sont liés à chaque système, et +ne marcheront sur aucun autre. Pour ceci, référez-vous silvouplaît à .* + +*Si vous êtes en train d'utiliser libreboot 20150518, notez qu'il y +a une erreur dans le script de flashage. faites celà: * + + rm -f patch + wget -O flash https://notabug.org/libreboot/libreboot/raw/9d850543ad90b72e0e333c98075530b31e5d23f1/flash + chmod +x flash + +La première moitié de la procédure est comme le suivant: + +`$ sudo ./flash i945lenovo_firstflash `[`yourrom.rom`](#rom) + +Vous devrez voir dans la sortie le suivant: + + Updated BUC.TS=1 - 64kb address ranges at 0xFFFE0000 and 0xFFFF0000 are + swapped + (A mis à jour BUC.TS=1 - La rangée d'adresses 64kb à 0xFFFE0000 et 0xFFFF0000 sont échangées.) + +Vous devrez voir aussi celà dans la sortie: + + Your flash chip is in an unknown state + ... + FAILED + ... + DO NOT REBOOT OR POWEROFF + + (Votre puce de flash est dans un état inconnu + ... + A ÉCHOUÉ + ... + NE PAS REDÉMARRER OU ÉTEINDRE) + +Voir ceci veut dire que l'opération était d'un succés *retentissant* ! +*NE PANIQUEZ PAS* + +Voir ce lien pour plus de détails: +. + +Si le dessus est ce que vous voyez, alors *ÉTEIGNEZ* (mais n'enlevez pas le jus, espécialement la batterie RTC). Attendez +quelques secondes et ensuite démarrez; libreboot est éxecuté, mais il y a une deuxième procédure nécessaire (voir +ci-dessous). + +Quand vous avez démarré de nouveau, vous devez aussi faire ceci: + +`$ sudo ./flash i945lenovo_secondflash `[`yourrom.rom`](#rom) + +Si le flashage a échoué à ce stage, essayez le suivant: + +`$ sudo ./flashrom/i686/flashrom -p internal:laptop=force_I_want_a_brick -w `[`yourrom.rom`](#rom) + +Vous devriez voir dans la sortie le suivant: + + Updated BUC.TS=0 - 128kb address range 0xFFFE0000-0xFFFFFFFF is + untranslated + (A mis à jour BUC.TS=0 - La rangé d'adresses 128kb 0xFFFE000-0xFFFFFFFF + est non traduite) + +Vous devriez aussi voir le suivant dans la sortie: + + Vérification du flash... VÉRIFIÉ. + + +MacBook 2,1: Guide d'installation initial (si vous êtes en train d'éxecuter le micrologiciel propriétaire) {#flashrom_macbook21} +============================================================================ + +*If you have a MacBook1,1, refer to +[../hardware/\#information-about-the-macbook11](../hardware/#information-about-the-macbook11) for flashing instructions.* + +*This is for the MacBook2,1 while running Apple EFI firmware. If you +already have coreboot or libreboot running, then go to +[\#flashrom](#flashrom) instead!* + +Be sure to read the information in +[../hardware/\#information-about-the-macbook21](../hardware/#information-about-the-macbook21). + +*Warning: this guide will not instruct the user how to backup the +original Apple EFI firmware. For that, please refer to +.* + +*If you are using libreboot\_src or git, then make sure that you built +the sources first (see [../git/\#build](../git/#build)).* + +Look at the [list of ROM images](#rom) to see which image is compatible +with your device. + +Use this flashing script, to install libreboot: + +`$ sudo ./flash i945apple_firstflash `[`yourrom.rom`](#rom) + +You should also see within the output the following: + + Verifying flash... VERIFIED. + +Shut down. + +Copyright © 2014, 2015, 2016 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/.index.md.swo b/i18n/fr_FR/docs/install/.index.md.swo new file mode 100644 index 00000000..58122958 Binary files /dev/null and b/i18n/fr_FR/docs/install/.index.md.swo differ diff --git a/i18n/fr_FR/docs/install/.index.md.swp b/i18n/fr_FR/docs/install/.index.md.swp new file mode 100644 index 00000000..d8569309 Binary files /dev/null and b/i18n/fr_FR/docs/install/.index.md.swp differ diff --git a/i18n/fr_FR/docs/install/bbb_setup.md b/i18n/fr_FR/docs/install/bbb_setup.md new file mode 100644 index 00000000..73b11d19 --- /dev/null +++ b/i18n/fr_FR/docs/install/bbb_setup.md @@ -0,0 +1,329 @@ +--- +title: Comment programmer une puce flash SPI avec le BeagleBone Black ou Teensy 3.1 +... + +Ce document existe en tant que guide pour lire ou écrire dans une puce +flash SPI avec le BeagleBone Black, utilisant le logiciel [flashrom] + +This document exists as a guide for reading from or writing to an SPI +flash chip with the BeagleBone Black, using the +[flashrom](http://flashrom.org/Flashrom) software. A BeagleBone Black, +rev. C was used when creating this guide, but earlier revisions may also +work. + +***NOTE: Use of BeagleBone black is for example purposes only, +don't buy it unless you want _it_ specifically.*** *There are many ARM +Single Board Computers (SBC) that are capable of in system programming +(external flashing) and they perform similarly terrible at that task. +Common use of devicetrees on those devices allows for configuring them +in similar way, but not identical, so a bit of own research is required. +Lastly SBC is an example of self-contained device that is capable of flashing, +but it's possible to use smaller device like stm32 bluepill +with another computer to achieve similar result.* + +*Note: This guide was written for Debian Stretch 9.5, which is the latest +operating system for the BeagleBone Black as of June 2019. It is possible that +these instructions may be outdated if newer operating systems versions +have been released since then.* + +There was no justification for a further section for the Teensy. Simply +refer to [this page on +flashrom.org](https://www.flashrom.org/Teensy_3.1_SPI_%2B_LPC/FWH_Flasher#ISP_Usage) +for information about how to set it up, and correlate that with the pins +on the SPI flash chip as per other guides in the libreboot documentation +for each board. At the time of writing, the teensy is tested for +flashing on the ThinkPad X200, but it should work for other targets. +here is a photo of the setup for the teensy: + + +Onto the Beaglebone black... + +Hardware requirements +===================== + +Shopping list (pictures of this hardware is shown later): + +- A [Flashrom](http://flashrom.org)-compatible external SPI + programmer: *BeagleBone Black*, sometimes referred to as 'BBB', + (rev. C) is highly recommended. You can buy one from + [Adafruit](https://www.adafruit.com) (USA), + [ElectroKit](http://electrokit.com) (Sweden) or any of the + distributors listed on [BeagleBoard's website](http://beagleboard.org/black) (look below + 'Purchase'). We recommend this product because we know that it + works well for our purposes and doesn't require any non-free + software. + +- Electrical/insulative tape: cover the entire bottom surface of the + BBB (the part that rests on a surface). This is important, when + placing the BBB on top of a board so that nothing shorts. Most + hardware/electronics stores have this. Optionally, you can use the + bottom half of a [hammond plastic + enclosure](http://www.hammondmfg.com/1593HAM.htm#BeagleBoneBlack). +- Clip for connecting to the flash chip: if you have a SOIC-16 flash + chip (16 pins), you will need the *Pomona 5252* or equivalent. For + SOIC-8 flash chips (8 pins), you will need the *Pomona 5250* or + equivalent. Do check which chip you have, before ordering a clip. + Also, you might as well buy two clips or more since they break + easily. [Farnell element 14](http://farnell.com/) sells these and + ships to many countries. Some people find these clips difficult to + get hold of, especially in South America. If you know of any good + suppliers, please contact the libreboot project with the relevant + information. *If you can't get hold of a pomona clip, some other + clips might work, e.g. 3M, but they are not always reliable. You can + also directly solder the wires to the chip, if that suits you; the + clip is just for convenience, really.* +- *External 3.3V DC power supply*, for powering the flash chip: an + ATX power supply / PSU (common on Intel/AMD desktop computers) will + work for this. A lab PSU (DC) will also work (adjusted to 3.3V). + - Getting a multimeter might be worthwhile, to verify that it's + supplying 3.3V. +- *External 5V DC power supply* (barrel connector), for powering the + BBB: the latter can have power supplied via USB, but a dedicated + power supply is recommended. These should be easy to find in most + places that sell electronics. OPTIONAL. Only needed if not + powering with the USB cable, or if you want to use [EHCI + debug](../misc/bbb_ehci.md). +- *Pin header / jumper cables* (2.54mm / 0.1" headers): you should + get male--male, male--female and female--female cables in 10cm + size. Just get a load of them. Other possible names for these + cables/wires/leads are as follows: + - flying leads + - breadboard cables (since they are often used on breadboards). + - You might also be able to make these cables yourself. + + [Adafruit](https://www.adafruit.com) sell them, as do many others. + *Some people find them difficult to buy. Please contact the + libreboot project if you know of any good sellers.* You might also + be able to make these cables yourself. For PSU connections, using + long cables, e.g. 20cm, is fine, and you can extend them longer than + that if needed. +- *Mini USB A-B cable* (the BeagleBone probably already comes with + one.) - *OPTIONAL - only needed for [EHCI + debug](../misc/bbb_ehci.md) or for serial/ssh access without + ethernet cable (g\_multi kernel module)* +- *FTDI TTL cable or debug board*: used for accessing the serial + console on the BBB. [This + page](http://elinux.org/Beagleboard:BeagleBone_Black_Serial) + contains a list. *OPTIONAL\---only needed for serial console on + the BBB, if not using SSH via ethernet cable.* + +Setting up the 3.3V DC PSU +========================== + +ATX PSU pinouts can be read on [this Wikipedia +page](https://en.wikipedia.org/wiki/Power_supply_unit_%28computer%29#Wiring_diagrams). + +You can use pin 1 or 2 (orange wire) on a 20-pin or 24-pin ATX PSU for +3.3V, and any of the ground/earth sources (black cables) for ground. +Short PS\_ON\# / Power on (green wire; pin 16 on 24-pin ATX PSU, or pin +14 on a 20-pin ATX PSU) to a ground (black; there is one right next to +it) using a wire/paperclip/jumper, then power on the PSU by grounding +PS\_ON\# (this is also how an ATX motherboard turns on a PSU). + +*DO NOT use pin 4, 6, do NOT use pin 19 or 20 (on a +20-pin ATX PSU), and DO NOT use pin 21, 22 or 23 (on a 24-pin +ATX PSU). Those wires (the red ones) are 5V, and they WILL kill +your flash chip. NEVER supply more than 3.3V to your flash +chip (that is, if it's a 3.3V flash chip; 5V and 1.8V SPI flash chips +do exist, but they are rare. Always check what voltage your chip takes. +Most of them take 3.3V).* + +You only need one 3.3V supply and one ground for the flash chip, after +grounding PS\_ON\#. + +The male end of a 0.1" or 2.54mm header cable is not thick enough to +remain permanently connected to the ATX PSU on its own. When connecting +header cables to the connector on the ATX PSU, use a female end attached +to a thicker piece of wire (you could use a paper clip), or wedge the +male end of the jumper cable into the sides of the hole in the +connector, instead of going through the centre. + +Here is an example set up:\ +![](images/x200/psu33.jpg "Copyright © 2015 Patrick "P. J." McDermott see license notice at the end of this document") + +Accessing the operating system on the BBB +========================================= + +Follow the [Getting Started](https://beagleboard.org/getting-started) +instructions to install the latest version of Debian onto the BBB. +It is recommended to download the eMMC IoT Flasher edition, which will +write its image to the on-board eMMC. + +The operating system on the BBB can be accessed over SSH, with username +'debian' and password 'temppwd'. Follow the instructions on the Getting +Started page for complete details. + +You will also be using the OS on your BBB for programming an SPI flash +chip. + +Alternatives to SSH (in case SSH fails) +--------------------------------------- + +You can also use a serial FTDI debug board with GNU Screen, to access +the serial console. + # screen /dev/ttyUSB0 115200 + +Here are some example photos:\ +![](images/x200/ftdi.jpg) ![](images/x200/ftdi_port.jpg)\ + +You can also connect the USB cable from the BBB to another computer and +a new network interface will appear, with its own IP address. This is +directly accessible from SSH, or screen: + + # screen /dev/ttyACM0 115200 + +You can also access the uboot console, using the serial method instead +of SSH. + +Setting up spidev on the BBB +============================ + +Log in to the BBB using either SSH or a serial console as +described in [\#bbb\_access](#bbb_access). + +*Note: The following commands are run as root. To run them from a normal user +account, add yourself to the `gpio` group to configure the pins and the `spi` +group to access spidev.* + +Run the following commands to enable spidev: + + # config-pin P9.17 spi_cs + # config-pin P9.18 spi + # config-pin P9.21 spi + # config-pin P9.22 spi_sclk + +Verify that the spidev devices now exist: + + # ls /dev/spidev* + +Output: + + /dev/spidev1.0 /dev/spidev1.1 /dev/spidev2.0 /dev/spidev2.1 + +Now the BBB is ready to be used for flashing. The following systemd service +file can optionally be enabled to make this persistent across reboots. + +``` +[Unit] +Description=Enable SPI function on pins + +[Service] +Type=oneshot +ExecStart=config-pin P9.17 spi_cs +ExecStart=config-pin P9.18 spi +ExecStart=config-pin P9.21 spi +ExecStart=config-pin P9.22 spi_sclk +RemainAfterExit=yes + +[Install] +WantedBy=multi-user.target +``` + +Get flashrom from the libreboot\_util release archive, or build it from +libreboot\_src/git if you need to. An ARM binary (statically compiled) +for flashrom exists in libreboot\_util releases. Put the flashrom binary +on your BBB. + +You may also need ich9gen, if you will be flashing an ICH9-M laptop +(such as the X200). Get it from libreboot\_util, or build it from +libreboot\_src, and put the ARM binary for it on your BBB. + +Finally, get the ROM image that you would like to flash and put that on +your BBB. + +Now test flashrom: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 + +Output: + + Calibrating delay loop... OK. + No EEPROM/flash device found. + Note: flashrom can never write if the flash chip isn't found automatically. + +This means that it's working (the clip isn't connected to any flash +chip, so the error is fine). + +Connecting the Pomona 5250/5252 +=============================== + +Use this image for reference when connecting the pomona to the BBB: + (D0 = MISO or connects +to MISO). + +The following shows how to connect clip to the BBB (on the P9 header), +for SOIC-16 (clip: Pomona 5252): + + NC - - 21 + 1 - - 17 + NC - - NC + NC - - NC + NC - - NC + NC - - NC + 18 - - 3.3V (PSU) + 22 - - NC - this is pin 1 on the flash chip + This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. + + You may also need to connect pins 1 and 9 (tie to 3.3V supply). These are HOLD# and WP#. + On some systems they are held high, if the flash chip is attached to the board. + If you're flashing a chip that isn't connected to a board, you'll almost certainly + have to connect them. + + SOIC16 pinout (more info available online, or in the datasheet for your flash chip): + HOLD 1-16 SCK + VDD 2-15 MOSI + N/C 3-14 N/C + N/C 4-13 N/C + N/C 5-12 N/C + N/C 6-11 N/C + SS 7-10 GND + MISO 8-9 WP + +The following shows how to connect clip to the BBB (on the P9 header), +for SOIC-8 (clip: Pomona 5250): + + 18 - - 1 + 22 - - NC + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip + This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. + + You may also need to connect pins 3 and 7 (tie to 3.3V supply). These are HOLD# and WP#. + On some systems they are held high, if the flash chip is attached to the board. + If you're flashing a chip that isn't connected to a board, you'll almost certainly + have to connect them. + + SOIC8 pinout (more info available online, or in the datasheet for your flash chip): + SS 1-8 VDD + MISO 2-7 HOLD + WP 3-6 SCK + GND 4-5 MOSI + +`NC = no connection` + +*DO NOT connect 3.3V (PSU) yet. ONLY connect this once the pomona is +connected to the flash chip.* + +*You also need to connect the BLACK wire (ground/earth) from the 3.3V +PSU to pin 2 on the BBB (P9 header). It is safe to install this now +(that is, before you connect the pomona to the flash chip); in fact, you +should.* + +if you need to extend the 3.3v psu leads, just use the same colour M-F +leads, *but* keep all other leads short and equal length (30cm or less). +Keep in mind that length isn't inversely proportional to signal quality, +so trying out different lengths will yield different results. +Same goes for spispeed. + +You should now have something that looks like this:\ +![](images/x200/5252_bbb0.jpg) ![](images/x200/5252_bbb1.jpg) + +Copyright © 2014, 2015 Leah Rowe \ +Copyright © 2015 Patrick "P. J." McDermott \ +Copyright © 2015 Albin Söderqvist\ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/c201.md b/i18n/fr_FR/docs/install/c201.md new file mode 100644 index 00000000..94828cd8 --- /dev/null +++ b/i18n/fr_FR/docs/install/c201.md @@ -0,0 +1,220 @@ +--- +title: ASUS Chromebook C201 installation guide +x-toc-enable: true +... + +These instructions are for installing Libreboot to the ASUS Chromebook +C201 (more known under a name [*veyron speedy*](../misc/codenames.md)). +Since the device ships with Coreboot, the installation +instructions are the same before and after flashing Libreboot for the +first time. + +*If you are using libreboot\_src or git, then make sure that you built +the sources first (see [../git/\#build](../git/#build)).* + +Look at the [list of ROM images](#rom) to see which image is compatible +with your device. + +Libreboot can be installed internally from the device, with sufficient +privileges. The installation process requires using *Google's modified +version of flashrom*, that has support for reflashing the Chromebook's +SPI flash. Otherwise, flashing externally will work with the upstream +flashrom version. + +*Google's modified version of flashrom* is free software and its +source code is made available by Google: +[flashrom](https://chromium.googlesource.com/chromiumos/third_party/flashrom/).\ +It is not distributed along with Libreboot yet. However, it is +preinstalled on the device, with ChromeOS. + +Installing Libreboot internally requires sufficient privileges on the system +installed on the device. When the device has ChromeOS installed (as it does +initially), it is necessary to gain root privileges in ChromeOS, to be able to +access a root shell. + +Gaining root privileges on ChromeOS +-------------------------------- + +In order to gain root privileges on ChromeOS, developer mode has to be +enabled from the recovery mode screen and debugging features have to be +enabled in ChromeOS. + +Instructions to access the [recovery mode +screen](../depthcharge/#recovery_mode_screen) and [enabling developer +mode](../depthcharge/#enabling_developer_mode) are available on the page +dedicated to [depthcharge](../depthcharge/). + +Once developer mode is enabled, the device will boot to the [developer +mode screen](../depthcharge/#developer_mode_screen). ChromeOS can be +booted by waiting for 30 seconds (the delay is shortened in Libreboot) +or by pressing *Ctrl + D* + +After the system has booted, root access can be enabled by clicking on +the *Enable debugging features* link. A confirmation dialog will ask +whether to proceed.\ +After confirming by clicking *Proceed*, the device will reboot and ask +for the root password to set. Finally, the operation has to be confirmed +by clicking *Enable*. + +After setting the root password, it becomes possible to log-in as root. +A tty prompt can be obtained by pressing *Ctrl + Alt + Next*. The +*Next* key is the one on the top left of the keyboard. + +Preparing the device for the installation +Before installing Libreboot on the device, both its software and +hardware has to be prepared to allow the installation procedure and to +ensure that security features don't get in the way. + +Configuring verified boot parameters +------------------------------------ + +It is recommended to have access to the [developer mode +screen](../depthcharge/#developer_mode_screen) and to [configure the +following verified boot +parameters](../depthcharge/#configuring_verified_boot_parameters): + +- Kernels signature verification: *disabled* +- External media boot: *enabled* + +Those changes can be reverted later, when the device is known to be in a +working state. + +Removing the write protect screw +-------------------------------- + +Since part of the SPI flash is write-protected by a screw, it is +necessary to remove the screw to remove the write protection and allow +writing Libreboot to the *read-only* part of the flash. + +To access the screw, the device has to be opened. There are 8 screws to +remove from the bottom of the device, as shown on the picture below. Two +are hidden under the top pads. After removing the screws, the keyboard +plastic part can be carefully detached from the rest. *Beware: there +are cables attached to it!* It is advised to flip the keyboard plastic +part over, as shown on the picture below. The write protect screw is +located next to the SPI flash chip, circled in red in the picture below. +It has to be removed. + +[![Screws](images/c201/screws.jpg)](images/c201/screws.jpg) [![WP +screw](images/c201/wp-screw.jpg)](images/c201/wp-screw.jpg) + +The write protect screw can be put back in place later, when the device +is known to be in a working state. + +Installing Libreboot to the SPI flash +===================================== + +The SPI flash (that holds Libreboot) is divided into various partitions +that are used to implement parts of the CrOS security system. Libreboot +is installed in the *read-only* coreboot partition, that becomes +writable after removing the write-protect screw. + +Installing Libreboot internally, from the device +------------------------------------------------ + +Before installing Libreboot to the SPI flash internally, the device has +to be reassembled. + +All the files from the `veyron_speedy` release (or build) have to be +transferred to the device. + +The following operations have to be executed with root privileges on the +device (e.g. using the `root` account). In addition, the +`cros-flash-replace` script has to be made executable: + + # chmod a+x cros-flash-replace + +The SPI flash has to be read first: + + # flashrom -p host -r flash.img + +*Note: it might be a good idea to copy the produced flash.img file at +this point and store it outside of the device for backup purposes.* + +Then, the `cros-flash-replace` script has to be executed as such: + + # sudo bash ./cros-flash-replace flash.img coreboot ro-frid + +If any error is shown, it is definitely a bad idea to go further than +this point. + +The resulting flash image can then be flashed back: + + # flashrom -p host -w flash.img + +You should also see within the output the following: + + Verifying flash... VERIFIED. + +Shut down. The device will now boot to Libreboot. + +Installing Libreboot externally, with a SPI flash programmer +------------------------------------------------------------ + +Before installing Libreboot to the SPI flash internally, the device has +to be opened. + +The SPI flash is located next to the write protect screw. Its layout is +indicated in the picture below. Note that it is not necessary to connect +`WP#` since after removing the screw it is pulled up weakly to 3v3. Before +writing to the chip externally, the battery has to be unplugged. +Battery connector is located under the heat spreader, that has to be +unscrewed from the rest of the case. It is located on +the right and has colorful cables, as shown on the picture below. + +[![SPI flash +layout](images/c201/spi-flash-layout.jpg)](images/c201/spi-flash-layout.jpg) +[![Battery +connector](images/c201/battery-connector.jpg)](images/c201/battery-connector.jpg) + +All the files from the `veyron_speedy` release (or build) have to be +transferred to the host. + +The following operations have to be executed with root privileges on the +host (e.g. using the `root` account). In addition, the +`cros-flash-replace` script has to be made executable: + + # chmod a+x cros-flash-replace + +The SPI flash has to be read first (using the right spi programmer): + + # flashrom -p *programmer* -r flash.img + +*Note: it might be a good idea to copy the produced flash.img file at +this point and store it outside of the device for backup purposes.* + +Then, the `cros-flash-replace` script has to be executed as such: + + # ./cros-flash-replace flash.img coreboot ro-frid + +If any error is shown, it is definitely a bad idea to go further than +this point. + +The resulting flash image can then be flashed back (using the right spi +programmer): + + # flashrom -p *programmer* -w flash.img + +You should also see within the output the following: + + Verifying flash... VERIFIED. + +The device will now boot to Libreboot. + +Installing Debian +--------------------- +Debian is recommended for this device (which is on that list. + +See . + +Also look at the HCL entry for operating systems (Debian, Devuan, Parabola): + + +Copyright © 2015 Paul Kocialkowski \ +Copyright © 2017 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/d510mo.md b/i18n/fr_FR/docs/install/d510mo.md new file mode 100644 index 00000000..315962b8 --- /dev/null +++ b/i18n/fr_FR/docs/install/d510mo.md @@ -0,0 +1,30 @@ +--- +title: D510MO flashing tutorial +... + +This guide is for those who want libreboot on their Intel D510MO +motherboard while they still have the original BIOS present. + +Flash chip size {#flashchips} +=============== + +Use this to find out: + + # flashrom -p internal + +Flashing instructions {#clip} +===================== + +Refer to [bbb\_setup.md](bbb_setup.md) for how to set up the BBB for +flashing. + +This is an image of the flash chip, for reference:\ +![](../images/d510mo/d510mo.jpg) + +Copyright © 2016 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/d945gclf.md b/i18n/fr_FR/docs/install/d945gclf.md new file mode 100644 index 00000000..ddb52a64 --- /dev/null +++ b/i18n/fr_FR/docs/install/d945gclf.md @@ -0,0 +1,26 @@ +--- +title: Intel D945GCLF flashing tutorial +... + +This guide is for those who want libreboot on their Intel D945GCLF +motherboard while they still have the original BIOS present. + +For information about this board, go to +[../hardware/d945gclf.md](../hardware/d945gclf.md) + +Flashing instructions {#clip} +===================== + +Refer to [bbb\_setup.md](bbb_setup.md) for how to set up the BBB for +external flashing. + +Here is an image of the flash chip:\ +![](../images/d945gclf/d945gclf_spi.jpg) + +Copyright © 2016 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/ga-g41m-es2l.md b/i18n/fr_FR/docs/install/ga-g41m-es2l.md new file mode 100644 index 00000000..6020565e --- /dev/null +++ b/i18n/fr_FR/docs/install/ga-g41m-es2l.md @@ -0,0 +1,55 @@ +--- +title: GA-G41M-ES2L flashing tutorial +... + +This guide is for those who want libreboot on their Intel GA-G41M-ES2L +motherboard while they still have the original BIOS present. + +Flash chip size {#flashchips} +=============== + +Use this to find out: + + # flashrom -p internal + +Flashing instructions {#clip} +===================== + +Refer to [bbb\_setup.md](bbb_setup.md) for how to set up the BBB for +external flashing. *You can only externally reprogram one of the chips +at a time, and you need to disable the chip that you're not flashing, +by connecting 3v3 to /CS of that chip, so you will actually need second test +clip or IC pin mini grabber.* + +Here is an image of the flash chip:\ +![](../images/ga-g41m-es2l/ga-g41m-es2l.jpg) + +Internal flashing is possible. Boot with the proprietary BIOS and +GNU+Linux. There are 2 flash chips (one is backup). + +Flash the first chip: + + ./flashrom -p internal:dualbiosindex=0 -w libreboot.rom + +Flash the second chip: + + ./flashrom -p internal:dualbiosindex=1 -w libreboot.rom + +NOTE: you can still boot the system with just the main flash chip +connected, after desoldering the backup chip. This has been tested while +libreboot was already installed onto the main chip. + +NOTE: You need the latest flashrom. Just get it on flashrom.org from +their SVN or Git repos. + +NOTE: due to a bug in the hardware, the MAC address is hardcoded in +coreboot-libre. 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differ diff --git a/i18n/fr_FR/docs/install/index.md b/i18n/fr_FR/docs/install/index.md new file mode 100644 index 00000000..017b130f --- /dev/null +++ b/i18n/fr_FR/docs/install/index.md @@ -0,0 +1,375 @@ +--- +Titre: Instructions d'installation +... + +Cette section concerne l'installation de Libreboot sur les cibles supportées. + +NOTE: si vous éxecutiez `flashrom -p internal` pour le flashage basé logiciellement, et vous avez une erreur concernant l'accés à `/dev/mem`, vous devrez redémarrer avec le paramètre de kernel `iomem=relaxed` avant d'éxecuter flashrom, ou utiliser un kernel qui a `CONFIG_STRICT_DEVMEM ` non activé. + +Quels systèmes sont compatibles avec Libreboot ? +-------------------------------------------- + +- [Information à propos de la compatibilité matérielle Libreboot](../hardware) + + +Informations générales +------------------- + +- [Information à propos des images ROM libreboot](#rom) + +Flashage via des méthodes logicielles, sur système: +----------------------------------------- + +- [Comment mettre à jour ou installer libreboot sur tout les systèmes](#flashrom) + +- [How to update or install libreboot on all systems](#flashrom) +- [ASUS KFSN4-DRE](#flashrom) +- [ThinkPad X60/T60 (if running Lenovo BIOS)](#flashrom_lenovobios) +- [Apple MacBook2,1](#flashrom_macbook21) +- [ASUS Chromebook C201](c201.md) + +Mettre en place les programmeurs, pour le flashage externe SPI +----------------------------------------------------------------- + +- [BeagleBone Black Setup](bbb_setup.md) +- [Raspberry Pi Setup](rpi_setup.md) + +Flashage via les méthodes matérielles, sur le système: +----------------------------------------- + +- [Gigabyte GA-G41-ES2L](ga-g41m-es2l.md) +- [Intel D510MO](d510mo.md) +- [Intel D945GCLF](d945gclf.md) +- [ASUS KGPE-D16](kgpe-d16.md) +- [ASUS KCMA-D8](kcma-d8.md) +- [ASUS Chromebook C201](c201.md) +- [ThinkPad X60](x60_unbrick.md) +- [ThinkPad X60 Tablet](x60tablet_unbrick.md) +- [ThinkPad T60](t60_unbrick.md) +- [ThinkPad X200/X200S/X200T](x200_external.md) +- [ThinkPad R400](r400_external.md) +- [ThinkPad T400](t400_external.md) +- [ThinkPad T500](t500_external.md) +- [ThinkPad W500](t500_external.md) + +Information à propos des images ROM libreboot {#rom} +====================================== + +Libreboot distribue des images ROM pré-compilée, construites à partir du code source de libreboot. Ces images sont fournies pour le confort de l'utilisateur, comme ça ils n'ont pas à construire quoi que ce soit depuis la source de leur propre chef. + +Ces images ROM dans chaque archive utilise le suivant à la fin de leur nom de fichier, si elles sont construites avec la charge utile GRUB: `*_*keymap*_*mode*.rom` + +Modes disponibles: vesafb ou txtmode. Les images ROM vesafb sont recommandés pour un usage régulier, mais quand vous flashez pour la première fois utilisez la version txtmode, car elle vient avec Memtext86+, qui demande le text-mode au lieu du framebuffer d'habitude utilisé par l'initialisation des graphiques natifs de coreboot. +La machine devrait être testée avec Memtest86+ après chaque réassemblage ou changement du bios constructeur (d'origine) à cause de différences dans le code de raminit. + +`keymap` peut être une des quelques mappage de touches que le clavier supporte (il y en a quelques un), qui affecte la configuration de la disposition du clavier qui est utilisé dans GRUB. Ca n'a pas d'importance quel image ROM vous utilisez ici, tant que le mappage des touches dans GNU+Linux est concerné. + + +Les mappages de touches sont nommés en accordance avec chaque disposition de clavier supportées dans GRUB. Pour apprendre comment ces mappages de touches sont créés, regardez [../grub/\#grub\_keyboard](../grub/#grub_keyboard) + + +QEMU +---- + +Libreboot arrive avec des images ROM construites pour QEMU par défaut: + +Des exemples de comment utiliser les images ROM de libreboot dans QEMU: + + $ qemu-system-i386 -M q35 -m 512 -bios qemu_q35_ich9_keymap_mode.rom + $ qemu-system-i386 -M pc -m 512 -bios qemu_i440fx_piix4_keymap_mode.rom + +Vous pouvez optionnellement spécifié l'argument `-serial stdio`, comme ça QEMU émulera un terminal en série sur l'entrée/sortie standard (très certainement votre émulateur de terminal ou TTY). + +D'autres arguments sont disponibles pour QEMU. Le manuel contiendra plus d'informations. + +Comment mettre à jour ou installer libreboot (si vous êtes déjà en train d'éxecuter libreboot ou coreboot) {#flashrom} +===================================================================================== + +Sur toutes les cibles actuelles, mettre à jour libreboot peut être accomplit sans désassemblage, +et de ce fait, sans avoir à re-flasher extérieurement en utilisant n'important quel matériel spécialisé. +En d'autres mots, vous pouvez tout faire de façon logicielle, directement depuis le système d'exploitation qui +est en cours d'éxecution sur votre système Libreboot. + +*Si vous êtes en train d'utiliser `libreboot_src` ou git, alors rendez-vous bien sûr +que vous avez compilé les sources en premier (regardez [../git/\#build](../git/#build)).* + +Regardez à la [liste des images ROM](#rom) pour voir quelle image est compatible avec votre appareil. + + +Êtes-vous en train d'exécuter le micrologiciel d'origine propriétaire ? +------------------------------------------------------------- + +Si vous êtes en train d'éxecuter le micrologiciel propriétaire (ni libreboot ou coreboot), alors les instructions de flashage pour votre système vont être différentes. + +Les utilisateurs du X60/T60 éxecutant le micrologiciel propriétaire devrait se référer à [\#flashrom\_lenovobios](#flashrom_lenovobios). Les utilisateurs de MacBook2,1 éxecutant l'EFI d'Apple devrait se référer à [\#flashrom\_macbook21](#flashrom_macbook21) + +Les utilisateurs de X200, se référeront à [x200\_external.md](x200_external.md), ceux de R400 à [r400\_external.md](r400_external.md), ceux de T400 à [t400\_external.md](t400_external.md), et ceux de T500 et W500 à [t500\_external.md](t500_external.md) + + +ASUS KFSN4-DRE? +--------------- + +Le flashage interne devrait marcher comme il faut, même si vous êtes en train +de démarrer le micrologiciel propriétaire. + +Libreboot manque en ce moment de documentation pour re-flasher +extérieurement une puce flash LPC. Cependant, ces cartes mères ont la puce de flash +à l'intérieur d'un socket PLCC, et il est possible d'échanger à chaud +les puces. Si vous voulez sauvegarder votre image connu pour marcher, échangez +simplement à chaud la puce pour un qui est de même capacité, après avoir déchargé +une copie du micrologiciel courant (flashrom -p internal -r yourchosenname.rom), et +flashez ensuite cette puce avec l'image connue pour marcher. Vérifiez si le système +démarre encore, et si il démarre alors il est sécurisé de flashé la nouvelle image +(parce que maintenant vous avez une sauvegarde de la vieille image). + +Garder au moins une puce LPC PLCC en stock avec le micrologiciel fonctionnel dessus +est fortement recommandé, en cas de bousillage. + +*N'ÉCHANGEZ PAS à chaud la puce avec vos mains nues. Utilisez un extracteur de puce PLCC. +Elles peuvent être trouvées en ligne. +Voyez * + +Vérifez la saisie HCL: [../hardware/kfsn4-dre.md](../hardware/kfsn4-dre.md) + +ASUS KGPE-D16? +-------------- + +Si vous avez un BIOS propriétaire, vous avez besoin de flasher libreboot +extérieurement. Voir [kgpe-d16.md](kgpe-d16.md) + +Si vous déjà coreboot ou libreboot installé, sans protection contre l'écriture sur +la puce flash, alors vous pouvez le faire logiciellement (sinon, voir le lien ci-dessus). + +*N'ÉCHANGEZ PAS à chaud la puce avec vos mains nues. Utilisez un extracteur de puce PDIP-8. +Elles peuvent être trouvées en ligne. +Voyez * + +Vérifier l'entrée HCL: [../hardware/kgpe-d16.md](../hardware/kgpe-d16.md) + +ASUS KCMA-D8? +------------- + +Si vous un BIOS propriétaire, nous avons besoin de flasher +libreboot extérieurement. Voir [kmca-d8.md](kmca-d8.md). + +Si vous avez déjà coreboot ou libreboot installé, sans protection +contre l'écriture sur la puce flash, alors vous pouvez le faire +logiciellement (sinon, voir le lien ci-dessus). + +*N'ÉCHANGEZ PAS à chaud la puce avec vos mains nues. Utilisez un extracteur de puce PDIP-8. +Elles peuvent être trouvées en ligne. +Voyez * + +Vérifier l'entrée HCL: [../hardware/kgpe-d16.md](../hardware/kgpe-d16.md) + + +Intel D945GCLF? +--------------- + +Si vous éxecutez le BIOS d'usine Intel original, alors vous aurez +besoin de le flasher extérieurement. Pour des instructions sur comment + faire celà, référez-vous [d945gclf.md](d945gclf.md). + +Sinon, lisez les instructions générales en dessous pour utiliser +le script *flash*. + + +Êtes-vous en train d'éxecuter libreboot (ou coreboot)? +-------------------------------------------------- + +Les utilisateurs X60/T60 devrait être OK avec ce guide. +Si vous avez protégé en écriture la puce flash, référez-vous +silvouplait à [x60\_unbrick.md](x60_unbrick.md), +[x60tablet\_unbrick.md](x60tablet_unbrick.md) ou +[t60\_unbrick.md](t60_unbrick.md). *Cela ne s'applique pas probablement + à vous. La majorité de gens ne protège pas en écriture la puce flash, donc + vous ne l'avez probablement pas fait* + +Similairement, c'est possible de protéger en écriture la puce flash dans +coreboot ou libreboot sur les ordinateurs portables GM45 (X200/R400/T400/T500/W500). +Si vous faites ça, alors vous aurez besoin d'utiliser les liens au-dessus pour +le flashage, traitant votre ordinateur portable comme si il avait le micrologiciel +propriétaire (parce que la puce SPI protégé en écriture aura besoin d'un reflashage, +externe, comme c'est le cas quand on éxecute le micrologiciel propriétaire). + +Si vous n'avez pas protégé en écriture la puce flash,ou elle est +arrivé chez vous sans aucune protection en écriture (*libreboot ne protège +pas en écriture la puce flash par défaut, donc ça s'applique à vous*), continuez à lire! + + +Adresse MAC sur GM45 (X200/R400/T400/T500/W500) +----------------------------------------- + +*Utilisateurs du X200/R400/T400/T500/W500, prenez note:* L'adresse MAC pour le jeu de puces +ethernet embarqué est situé à l'intérieur de la puce flash. Les images ROM de Libreboot pour +ces ordinateurs portables contiennent une adresse MAC générique par défaut, mais ce n'est +pas que vous voulez. *Assurez vous bien de change l'adresse MAC à l'intérieur de l'image ROM +avant de la flasher. Les instructions dans [../hardware/gm45\_remove\_me.html\#ich9gen](../hardware/gm45_remove_me.html#ich9gen) +montrent comment faire celà. + +C'est important que vous changiez l'adresse MAC par défaut, avant flashage. +Elle sera imprimée sur un sticker en bas de l'ordinateur portable, ou il sera +imprimé sur un sticker à côté ou sous la RAM. +Alternativement, et assumant que votre micrologiciel en cours d'exécution à la +bonne adresse MAC en lui, vous pouvez la récupérer depuis votre système d'exploitation. + + +Apple iMac 5,2? +--------------- + +Le flashage interne marche, même quand on flashing depuis l'EFI d'Apple vers Libreboot. +Continuez à lire les instructions ci-dessous. + +*NOTE*: Si vous flashez une plus vieille version de libreboot, la carte mère de l'iMac5,2 est compatible avec le MacBook2,1. +Flashez simplement une image ROM MacBook2,1, et ça devrait marcher. + + +Taille de la puce flash +--------------- + +Utilisez ceci pour trouver: + + # flashrom -p internal + + +Tout bon ? +--------- + +Excellent! On bouge... + +Téléchargez l'archive *libreboot\_util.tar.xz*, et extrayez là. À +l'intérieur vous trouverez un répertoire appelé *flashrom*. Il contient +des fichiers éxecutables compilés statiquement de l'utilitaire *flashrom*, que +vous utiliserez pour re-flasher votre système libreboot. + +Utilisez simplement *cd* sur votre terminal, pour vous mettre sur le répertoire +*libreboot\_util*. À l'intérieur, il y a un script appelé *flash*, qui détectera quelle +architecture de processeur vous avez (e.g. i686, x86\_64) et utilisera l'éxecutable +approprié. Il est aussi possible pour vous de construire ces éxecutables à partir +des archives de code source de libreboot. + +Comment mettre à jour le contenu de la puce flash: + + `$ sudo ./flash update `[`yourrom.rom`](#rom) + +Occasionellement, coreboot change le nom d'une carte mère. Si flashrom se plaint à +propos d'une carte mère qui ne correspond pas, mais vous êtes sur que vous choisissez +l'image ROM correcte, alors éxecutez cette commande alternative: + + `$ sudo ./flash forceupdate `[`yourrom.rom](#rom) + +Vous devriez voir `Vérification du flash... VÉRIFIÉ.` écris à la fin de la sortie +de flashrom. *Éteignez* après que vous voyez ceci, et ensuite démarrez de nouveau après quelques secondes. + +ThinkPad X60/T60: Guide d'installation initiale (si vous êtes en train d'éxecutez le micrologiciel propriétaire) {#flashroms_lenovobios} +================================================================================== + +*Ceci est pour le ThinkPad X60 et T60 pendant que vous êtes en train +d'éxecuter le BIOS de Lenovo. Si vous êtes déjà en train d'éxecuter +coreboot ou libreboot, alors rendez-vous sur [\#flashrom](#flashrom)!* + +*Si vous pouvez, rendez-vous sûr que la batterie RTC n'est pas déchargée. Une batterie RTC déchargé peut amener à un bousillage dû car la valeur du registre BUC n'est pas maintenue..* + +*Si vous êtes en train de flasher un Lenovo ThinkPad T60, assurez-vous de lire +[../hardware/\#supported\_t60\_list](../hardware/#supported_t60_list) + +*Si vous êtes en train d'utilisez libreboot\_src ou git, alors +rendez-vous sûr que vous avez compilé les sources en premier +(voir [../git/\#build](../git/#build))* + +*Attention: ce guide n'instruirera pas l'utiliser sur comment sauvegarder +le micrologiciel original du BIOS Lenovo. Ces sauvegardes sont liés à chaque système, et +ne marcheront sur aucun autre. Pour ceci, référez-vous silvouplaît à .* + +*Si vous êtes en train d'utiliser libreboot 20150518, notez qu'il y +a une erreur dans le script de flashage. faites celà: * + + rm -f patch + wget -O flash https://notabug.org/libreboot/libreboot/raw/9d850543ad90b72e0e333c98075530b31e5d23f1/flash + chmod +x flash + +La première moitié de la procédure est comme le suivant: + +`$ sudo ./flash i945lenovo_firstflash `[`yourrom.rom`](#rom) + +Vous devrez voir dans la sortie le suivant: + + Updated BUC.TS=1 - 64kb address ranges at 0xFFFE0000 and 0xFFFF0000 are + swapped + (A mis à jour BUC.TS=1 - La rangée d'adresses 64kb à 0xFFFE0000 et 0xFFFF0000 sont échangées.) + +Vous devrez voir aussi celà dans la sortie: + + Your flash chip is in an unknown state + ... + FAILED + ... + DO NOT REBOOT OR POWEROFF + + (Votre puce de flash est dans un état inconnu + ... + A ÉCHOUÉ + ... + NE PAS REDÉMARRER OU ÉTEINDRE) + +Voir ceci veut dire que l'opération était d'un succés *retentissant* ! +*NE PANIQUEZ PAS* + +Voir ce lien pour plus de détails: +. + +Si le dessus est ce que vous voyez, alors *ÉTEIGNEZ* (mais n'enlevez pas le jus, espécialement la batterie RTC). Attendez +quelques secondes et ensuite démarrez; libreboot est éxecuté, mais il y a une deuxième procédure nécessaire (voir +ci-dessous). + +Quand vous avez démarré de nouveau, vous devez aussi faire ceci: + +`$ sudo ./flash i945lenovo_secondflash `[`yourrom.rom`](#rom) + +Si le flashage a échoué à ce stage, essayez le suivant: + +`$ sudo ./flashrom/i686/flashrom -p internal:laptop=force_I_want_a_brick -w `[`yourrom.rom`](#rom) + +Vous devriez voir dans la sortie le suivant: + + Updated BUC.TS=0 - 128kb address range 0xFFFE0000-0xFFFFFFFF is + untranslated + (A mis à jour BUC.TS=0 - La rangé d'adresses 128kb 0xFFFE000-0xFFFFFFFF + est non traduite) + +Vous devriez aussi voir le suivant dans la sortie: + + Vérification du flash... VÉRIFIÉ. + + +MacBook 2,1: Guide d'installation initial (si vous êtes en train d'éxecuter le micrologiciel propriétaire) {#flashrom_macbook21} +============================================================================ + +*Si vous avez un MacBook1,1, référez-vous à [../hardware/\#information-about-the-macbook11](../hardware/#information-about-the-macbook11) pour les instructions de flashage.* + +*Ceci est pour le MacBook2,1 pendant que vous éxecutez le micrologiciel EFI d'Apple. Si vous êtes déja en train d'éxecuter coreboot ou libreboot, alors allez à la section [\#flashrom](#flashrom)* + +Rendez-vous sûr de lire les informations dans [../hardware/\#information-about-the-macbook21](../hardware/#information-about-the-macbook21) + +*Attention: ce guide n'instruira pas l'utilisateur sur comment +sauvegarder le micrologiciel original EFI d'Apple. Pour ça, +référez-vous à .* + +*Si vous êtes en train d'utiliser libreboot\_src ou git, alors rendez-vous sûr que vous avez compilé les sources en premier (voir [../git/\#build](../git/\#build))* + +Jetez un oeil à la [liste des images ROM](#rom) pour voir quelle image est compatible avec votre appareil. + +Utilisez ce script de flashage pour installer libreboot: + +`$ sudo ./flash i945apple_firstflash `[`yourrom.rom`](#rom) + +Vous devrez voir notamment le suivant en sortie: + + Vérification du flash.... VÉRIFIÉ. + +Extinction. + +Copyright © 2014, 2015, 2016 Leah Rowe \ + +La permission est accordé pour copier, distribuer et/ou modifier ce document sous les termes de la GNU Free Documentation Licence version 1.3 ou n'importe quelles autre version plus récentes publié par la Free Software Foundation avec aucune Sections Invariantes, Texte de Couverture, et Texte de quatrième de couverture. +Une copie de cette licence est trouvé dans [fdl-1.3.md](fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/kcma-d8.md b/i18n/fr_FR/docs/install/kcma-d8.md new file mode 100644 index 00000000..8f9ecfc1 --- /dev/null +++ b/i18n/fr_FR/docs/install/kcma-d8.md @@ -0,0 +1,38 @@ +--- +title: KCMA-D8 external flashing instructions +x-toc-enable: true +... + +Initial flashing instructions for kcma-d8. + +This guide is for those who want libreboot on their ASUS kcma-d8 +motherboard, while they still have the proprietary ASUS BIOS present. +This guide can also be followed (adapted) if you brick you board, to +know how to recover. + +*Memory initialization is still problematic, for some modules. We +recommend avoiding Kingston modules.* + +For more general information about this board, refer to +[../hardware/kcma-d8.md](../hardware/kcma-d8.md). + +TODO: show photos here, and other info. + +External programmer {#programmer} +=================== + +Refer to [bbb\_setup.md](bbb_setup.md) for a guide on how to set up +an external SPI programmer. + +The flash chip is in a PDIP 8 socket (SPI flash chip) on the +motherboard, which you take out and then re-flash with libreboot, using +the programmer. *DO NOT* remove the chip with your hands. Use a chip +extractor tool. + +Copyright © 2016 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/kgpe-d16.md b/i18n/fr_FR/docs/install/kgpe-d16.md new file mode 100644 index 00000000..9810179f --- /dev/null +++ b/i18n/fr_FR/docs/install/kgpe-d16.md @@ -0,0 +1,38 @@ +--- +title: KGPE-D16 external flashing instructions +x-toc-enable: true +... + +Initial flashing instructions for KGPE-D16. + +This guide is for those who want libreboot on their ASUS KGPE-D16 +motherboard, while they still have the proprietary ASUS BIOS present. +This guide can also be followed (adapted) if you brick you board, to +know how to recover. + +*Memory initialization is still problematic, for some modules. We +recommend avoiding Kingston modules.* + +For more general information about this board, refer to +[../hardware/kgpe-d16.md](../hardware/kgpe-d16.md). + +TODO: show photos here, and other info. + +External programmer +=================== + +Refer to [bbb\_setup.md](bbb_setup.md) for a guide on how to set up +an external SPI programmer. + +The flash chip is in a PDIP 8 socket (SPI flash chip) on the +motherboard, which you take out and then re-flash with libreboot, using +the programmer. *DO NOT* remove the chip with your hands. Use a chip +extractor tool. + +Copyright © 2015 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/r400_external.md b/i18n/fr_FR/docs/install/r400_external.md new file mode 100644 index 00000000..19f673a6 --- /dev/null +++ b/i18n/fr_FR/docs/install/r400_external.md @@ -0,0 +1,367 @@ +--- +title: Flashing the R400 with a BeagleBone Black +... + +Initial flashing instructions for R400. + +This guide is for those who want libreboot on their ThinkPad R400 while +they still have the original Lenovo BIOS present. This guide can also be +followed (adapted) if you brick your R400, to know how to recover. + +Before following this section, please make sure to setup your libreboot +ROM properly first. Although ROM images are provided pre-built in +libreboot, there are some modifications that you need to make to the one +you chose before flashing. (instructions referenced later in this guide) + +Libreboot T400 {#t400} +============== + +You may also be interested in the smaller, more portable [Libreboot +T400](t400_external.md). + +Serial port {#serial_port} +----------- + +EHCI debug might not be needed. It has been reported that the docking +station for this laptop has a serial port, so it might be possible to +use that instead. + +A note about CPUs +================= + +[ThinkWiki](http://www.thinkwiki.org/wiki/Category:R400) has a list of +CPUs for this system. The Core 2 Duo P8400 and P8600 are believed to +work in libreboot. The Core 2 Duo T9600 was confirmed to work, so the +T9400 probably also works. *The Core 2 Duo T5870/5670 and Celeron M +575/585 are untested!* + +Quad-core CPUs +-------------- + +Incompatible. Do not use. + +A note about GPUs +================= + +Some models have an Intel GPU, while others have both an ATI and an +Intel GPU; this is referred to as "Dual Graphics" (previously +"switchable graphics"). In the *BIOS setup* program for lenovobios, +you can specify that the system will use one or the other (but not +both). + +Libreboot is known to work on systems with only the Intel GPU, using +native graphics initialization. On systems with switchable graphics, the +Intel GPU is used and the ATI GPU is disabled, so native graphics +initialization works all the same. + +CPU paste required +================== + +See [\#paste](#paste). + +Flash chip size {#flashchips} +=============== + +Use this to find out: + + # flashrom -p internal + +MAC address {#macaddress} +=========== + +Refer to [mac\_address.md](../hardware/mac_address.md). + +Initial BBB configuration +========================= + +Refer to [bbb\_setup.md](bbb_setup.md) for how to setup the BBB for +flashing. + +The following shows how to connect clip to the BBB (on the P9 header), +for SOIC-16 (clip: Pomona 5252): + + POMONA 5252 (correlate with the BBB guide) + === ethernet jack and VGA port ==== + NC - - 21 + 1 - - 17 + NC - - NC + NC - - NC + NC - - NC + NC - - NC + 18 - - 3.3V (PSU) + 22 - - NC - this is pin 1 on the flash chip + === SATA port === + This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. + +The following shows how to connect clip to the BBB (on the P9 header), +for SOIC-8 (clip: Pomona 5250): + + POMONA 5250 (correlate with the BBB guide) + === RAM slots ==== + 18 - - 1 + 22 - - NC + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip + === slot where the AC jack is connected === + This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. + +Disassembly +----------- + +Remove all screws:\ +![](images/r400/0000.jpg)\ +Remove the HDD and optical drive:\ +![](images/r400/0001.jpg)\ +Remove the hinge screws:\ +![](images/r400/0002.jpg) ![](images/r400/0003.jpg) + +Remove the palm rest and keyboard:\ +![](images/r400/0004.jpg) ![](images/r400/0005.jpg) + +Remove these screws, and then remove the bezel:\ +![](images/r400/0006.jpg) ![](images/r400/0007.jpg) + +Remove the speaker screws, but don't remove the speakers yet (just set +them loose):\ +![](images/r400/0008.jpg) ![](images/r400/0009.jpg) +![](images/r400/0010.jpg) + +Remove these screws, and then remove the metal plate:\ +![](images/r400/0011.jpg) ![](images/r400/0012.jpg) +![](images/r400/0013.jpg) + +Remove the antennas from the wifi card, and then start unrouting them:\ +![](images/r400/0014.jpg) ![](images/r400/0015.jpg) +![](images/r400/0016.jpg) ![](images/r400/0017.jpg) +![](images/r400/0018.jpg) ![](images/r400/0019.jpg) + +Disconnect the LCD cable from the motherboard:\ +![](images/r400/0020.jpg) ![](images/r400/0021.jpg) +![](images/r400/0022.jpg) ![](images/r400/0023.jpg) + +Remove the hinge screws, and then remove the LCD panel:\ +![](images/r400/0024.jpg) ![](images/r400/0025.jpg) +![](images/r400/0026.jpg) ![](images/r400/0027.jpg) + +Remove this:\ +![](images/r400/0028.jpg) ![](images/r400/0029.jpg) + +Remove this long cable (there are 3 connections):\ +![](images/r400/0030.jpg) ![](images/r400/0031.jpg) +![](images/r400/0032.jpg) ![](images/r400/0033.jpg) + +Disconnect the speaker cable, and remove the speakers:\ +![](images/r400/0034.jpg) + +Remove the heatsink screws, remove the fan and then remove the +heatsink/fan:\ +![](images/r400/0035.jpg) ![](images/r400/0036.jpg) +![](images/r400/0037.jpg) ![](images/r400/0038.jpg) + +Remove the NVRAM battery:\ +![](images/r400/0039.jpg) ![](images/r400/0040.jpg) + +Remove this screw:\ +![](images/r400/0041.jpg) ![](images/r400/0042.jpg) + +Disconnect the AC jack:\ +![](images/r400/0043.jpg) ![](images/r400/0044.jpg) + +Remove this screw and then remove what is under it:\ +![](images/r400/0045.jpg) + +Remove this:\ +![](images/r400/0046.jpg) + +Lift the motherboard (which is still inside the cage) from the side on +the right, removing it completely:\ +![](images/r400/0047.jpg) ![](images/r400/0048.jpg) + +Remove all screws, marking each hole so that you know where to re-insert +them. You should place the screws in a layout corresponding to the order +that they were in before removal: ![](images/r400/0049.jpg) +![](images/r400/0050.jpg) + +Remove the motherboard from the cage, and the SPI flash chip will be +next to the memory slots:\ +![](images/r400/0051.jpg) ![](images/r400/0052.jpg) + +Connect your programmer, then connect GND and 3.3V\ +![](images/t400/0065.jpg) ![](images/t400/0066.jpg) +![](images/t400/0067.jpg) ![](images/t400/0069.jpg) +![](images/t400/0070.jpg) ![](images/t400/0071.jpg) + +A dedicated 3.3V PSU was used to create this guide, but at ATX PSU is +also fine:\ +![](images/t400/0072.jpg) + +Of course, make sure to turn on your PSU:\ +![](images/x200/disassembly/0013.jpg) + +Now, you should be ready to install libreboot. + +Flashrom binaries for ARM (tested on a BBB) are distributed in +libreboot\_util. Alternatively, libreboot also distributes flashrom +source code which can be built. + +Log in as root on your BBB, using the instructions in +[bbb\_setup.html\#bbb\_access](bbb_setup.html#bbb_access). + +Test that flashrom works: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512\ + +In this case, the output was: + + flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) + flashrom is free software, get the source code at http://www.flashrom.org + Calibrating delay loop... OK. + Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. + Found Macronix flash chip "MX25L6406E/MX25L6436E" (8192 kB, SPI) on linux_spi. + Found Macronix flash chip "MX25L6445E/MX25L6473E" (8192 kB, SPI) on linux_spi. + Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)", "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E" + Please specify which chip definition to use with the -c option. + +How to backup factory.rom (change the -c option as neeed, for your flash +chip): + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory.rom + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory1.rom + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory2.rom + +Note: the `-c` option is not required in libreboot's patched +flashrom, because the redundant flash chip definitions in *flashchips.c* +have been removed. + +Now compare the 3 images: + + # sha512sum factory*.rom + +If the hashes match, then just copy one of them (the factory.rom) to a +safe place (on a drive connected to another system, not the BBB). This +is useful for reverse engineering work, if there is a desirable +behaviour in the original firmware that could be replicated in coreboot +and libreboot. + +Follow the instructions at +[../hardware/gm45\_remove\_me.html\#ich9gen](../hardware/gm45_remove_me.html#ich9gen) +to change the MAC address inside the libreboot ROM image, before +flashing it. Although there is a default MAC address inside the ROM +image, this is not what you want. *Make sure to always change the MAC +address to one that is correct for your system.* + +Now flash it: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w + +path/to/libreboot/rom/image.rom -V + +![](images/x200/disassembly/0015.jpg) + +You might see errors, but if it says `Verifying flash... VERIFIED` at +the end, then it's flashed and should boot. If you see errors, try +again (and again, and again); the message `Chip content is identical to +the requested image` is also an indication of a successful +installation. + +Example output from running the command (see above): + + flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) + flashrom is free software, get the source code at http://www.flashrom.org + Calibrating delay loop... OK. + Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. + Reading old flash chip contents... done. + Erasing and writing flash chip... FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xd716 + ERASE FAILED! + Reading current flash chip contents... done. Looking for another erase function. + Erase/write done. + Verifying flash... VERIFIED. + +Thermal paste (IMPORTANT) +========================= + +Because part of this procedure involved removing the heatsink, you will +need to apply new paste. Arctic MX-4 is ok. You will also need isopropyl +alcohol and an anti-static cloth to clean with. + +When re-installing the heatsink, you must first clean off all old paste +with the alcohol/cloth. Then apply new paste. Arctic MX-4 is also much +better than the default paste used on these systems. + +![](images/t400/paste.jpg) + +NOTE: the photo above is for illustration purposes only, and does not +show how to properly apply the thermal paste. Other guides online detail +the proper application procedure. + +Wifi +==== + +The R400 typically comes with an Intel wifi chipset, which does not work +without proprietary software. For a list of wifi chipsets that work +without proprietary software, see +[../hardware/\#recommended\_wifi](../hardware/#recommended_wifi). + +Some R400 laptops might come with an Atheros chipset, but this is +802.11g only. + +It is recommended that you install a new wifi chipset. This can only be +done after installing libreboot, because the original firmware has a +whitelist of approved chips, and it will refuse to boot if you use an +'unauthorized' wifi card. + +The following photos show an Atheros AR5B95 being installed, to replace +the Intel chip that this R400 came with:\ +![](images/t400/0012.jpg) ![](images/t400/ar5b95.jpg) + +WWAN +==== + +If you have a WWAN/3G card and/or sim card reader, remove them +permanently. The WWAN-3G card has proprietary firmware inside; the +technology is identical to what is used in mobile phones, so it can also +track your movements. + +Not to be confused with wifi (wifi is fine). + +Memory +====== + +You need DDR3 SODIMM PC3-8500 RAM installed, in matching pairs +(speed/size). Non-matching pairs won't work. You can also install a +single module (meaning, one of the slots will be empty) in slot 0. + +Make sure that the RAM you buy is the 2Rx8 density. + +[This page](http://www.forum.thinkpads.com/viewtopic.php?p=760721) might +be useful for RAM compatibility info (note: coreboot raminit is +different, so this page might be BS) + +The following photo shows 8GiB (2x4GiB) of RAM installed:\ +![](images/t400/memory.jpg) + +Boot it! +-------- + +You should see something like this: + +![](images/t400/boot0.jpg) ![](images/t400/boot1.jpg) + +Now [install GNU+Linux](../gnulinux/). + +Copyright © 2014, 2015 Leah Rowe \ +Copyright © 2018 Nico Rikken \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/rpi_setup.md b/i18n/fr_FR/docs/install/rpi_setup.md new file mode 100644 index 00000000..213931f4 --- /dev/null +++ b/i18n/fr_FR/docs/install/rpi_setup.md @@ -0,0 +1,401 @@ +--- +title: Comment programmer une puce flash SPI avec la Raspberry Pi +... + +Ce document existe comme un guide pour lire de ou écrire dans une puce flash +SPI avec la Raspberry Pi, utilisant le logiciel [flashrom](http://flashrom.org/Flashrom) +La plupart des révisions de la RPi devrait marcher. + +Le projet Libreboot recommande d'utiliser [GNU+Linux sans blob]() + +This document exists as a guide for reading from or writing to an SPI flash +chip with the Raspberry Pi, using the [flashrom](http://flashrom.org/Flashrom) +software. Most revisions of the RPi should work. + +Le projet Libreboot recommande l'utilisation de [GNU+Linux sans blobs](https://blog.rosenzweig.io/blobless-linux-on-the-pi.html) +sur la Raspberry Pi, pour éviter d'avoir à éxecuter des logiciels non-libres. C'est devenu +seulement possible en Février 2017 et les instructions ci-dessous ne sont +pas encore mises à jour avec les étapes nécessaires, donc silvouplaît ne suivez pas les +étapes ci-dessous à moins que vous consentez à éxecuter des logiciels non-libre sur votre +Raspberry Pi. + +Cela concerne seulement les puces flash SOIC-8 pour l'instant. Le guide pour les +SOIC-16 viendra plus tard (pour l'instant, ça devrait être facile pour vous de déduire ce +qu'il y a faire pour les SOIC-16). + + +Raspberry Pi (ThinkPad X60/T60 et Macbook 2,1) +------------------------------------------------ + +La Raspberry Pi (un ordinateur GNU+Linux versatile pour \$25) peut être utilisé comme +un outil de flashage de BIOS, grâce à ses broches GPIO et son support de SPI. + +Note: La Raspberry Pi Model A n'est pas supportée, puisqu'elle n'a pas de broches GPIO. +### Désassembler les ThinkPad + +Suivez le [manuel de maintenance matérielle X60](http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf) +ou le [manuel de maintenance matérielle T60](http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42t7844_04.pdf) pour +désassembler l'ordinateur portable, jusqu'à ce que vous pouvez accéder la puce BIOS. + +Pour des photos, suivez le [Guide Libreboot de Récupération du T60](t60_unbrick.md). + + Sur le X60, la puce BIOS est sur le bas de la carte mère, sous une + couche de ruban adhésif noir protecteur. + + Sur le T60, la puce BIOS est juste en dessous du repose main, mais + bloqué par une plaque en magnésium (que vous aurez à enlever). + + +### Pomona Clip Pinout + +Diagram of the 26 GPIO Pins of the Raspberry Pi Model B (for the Model +B+ with 40 pins, start counting from the right and leave 14 pins): + +![](images/rpi/0012.png) ![](images/rpi/0013.png) + + 8-pin for X60: + + ~~~~ LCD (Front) ~~~~ + 8765 + ---- + | | + ---- + 1234 + ~~~ Palmrest (back) ~~ + + Pin \# SPI Pin Name BP (Seeed) BP (Spkfun) [Beagleboard Black](http://beagleboard.org/Support/bone101#headers) [Raspberry Pi](images/rpi/0000.jpg) + -------- -------------- ------------ ------------- --------------------------------------------------------------------- ------------------------------------- + 1 CS White Red Pin 17 24 + 2 MISO Black Brown Pin 21 21 + 3 *not used* *not used* *not used* *not used* *not used* + 4 GND Brown Black Pin 1 25 + 5 MOSI Gray Orange Pin 18 19 + 6 CLK Purple Yellow Pin 22 23 + 7 *not used* *not used* *not used* *not used* *not used* + 8 3.3V *red* White [3.3V PSU RED](bbb_setup.md) 17 + +Make sure the pinouts are correct; otherwise, Flashrom will fail to +detect a chip, or it will "detect" a `0x0` chip. Finally, make sure +that the Pomona clip makes contact with the metal wires of the chip. It +can be a challenge, but keep trying. + +### How to supply power to the flashchip + +There are two ways to supply power to the chip: plugging in an AC +adapter (without turning the laptop on), and using the 8th 3.3v pin. + +I have found that the SST chips work best with the 8th pin, while the +Macronix chips require an AC Adapter to power up. + +*Never connect both the 8th pin and the AC adapter at the same time.* + +Your results may vary. + +Reading the Flashchip +---------------------- + +First, visually inspect (with a magnifying glass) the type of flashchip +on the motherboard. + +Next, download and compile the latest Flashrom source code on the +Raspberry Pi. + + sudo apt-get install build-essential pciutils usbutils libpci-dev libusb-dev libftdi1 libftdi-dev zlib1g-dev subversion libusb-1.0-0-dev + svn co svn://flashrom.org/flashrom/trunk flashrom + cd flashrom + make + sudo modprobe spi_bcm2708 + sudo modprobe spidev + +If your chip is an SST, run this command: + + sudo ./flashrom -p linux_spi:dev=/dev/spidev0.0 -r test.rom + +If your chip is a Macronix, run this command: + + sudo ./flashrom -c "MX25L1605" -p linux_spi:dev=/dev/spidev0.0 -r test.rom + +Next, check the md5sum of the dump: + + md5sum test.rom + +Run the `flashrom` command again to make a second dump. Then, check the +md5sum of the second dump: + + md5sum test.rom + +If the md5sums match after three tries, `flashrom` has managed to read +the flashchip precisely (but not always accurately). You may try and +flash Libreboot now. + +Flashing Libreboot +------------------- + +Note: replace `/path/to/libreboot.rom` with the location of your chosen ROM, +such as `../bin/x60/libreboot_usqwerty.rom`): + +If your chip is an SST, run this command: + + sudo ./flashrom -p linux_spi:dev=/dev/spidev0.0 -w /path/to/libreboot.rom + +If your chip is a Macronix, run this command: + + sudo ./flashrom -c "MX25L1605" -p linux_spi:dev=/dev/spidev0.0 -w /path/to/libreboot.rom + +Once that command outputs the following, the flash has completed +successfully. If not, just flash again. + + Reading old flash chip contents... done. + Erasing and writing flash chip... Erase/write done. + Verifying flash... VERIFIED. + +### Sources + +- [Scruss - Simple ADC with the Raspberry + Pi](http://scruss.com/blog/2013/02/02/simple-adc-with-the-raspberry-pi/) +- [Flashing coreboot on a T60 with a Raspberry Pi - + the\_unconventional's + blog](https://web.archive.org/web/20150709043222/http://blogs.fsfe.org:80/the_unconventional/2015/05/08/coreboot-t60-raspberry-pi/) +- *Pomona SOIC Clip flashing* + - [Arch Linux Wiki - Installing Arch Linux on + Chromebook](https://wiki.archlinux.org/index.php/Chromebook) + - [Google Drive - Raspberry Pi SOIC Clip + connection](https://drive.google.com/folderview?id=0B9f62MH0umbmRTA2Xzd5WHhjWEU&usp=sharing) + - [rPI with Flashrom and SOIC Clip + Powerpoint](http://satxhackers.org/wp/hack-content/uploads/2013/04/rPI_flashrom.pdf) + +### Raspberry Pi Pinout Diagrams + + MCP 3008 Pin Pi GPIO Pin \# Pi Pin Name + ----- ---------- ---------------- -------------------- + 16 `VDD` 1 `3.3 V` + 15 `VREF` 1 `3.3 V` + 14 `AGND` 6 `GND` + 13 `CLK` 23 `GPIO11 SPI0_SCLK` + 12 `DOUT` 21 `GPIO09 SPI0_MISO` + 11 `DIN` 19 `GPIO10 SPI0_MOSI` + 10 `CS` 24 `GPIO08 CE0` + 9 `DGND` 6 `GND` + +- Source: [Perl & Raspberry Pi - Raspberry Pi GPIO + Pinout](http://raspberrypi.znix.com/hipidocs/topic_gpiopins.htm) + +Raspberry Pi (ThinkPad X200) +----------------------------- + +### Requirements: + +- An x86, x86\_64, or arm7l (for changing the libreboot.rom image mac + address) +- Raspberry Pi and peripherals +- Relevant SOIC clip +- 6 female - female jumpers +- Internet connection +- Screw drivers + +Follow the [ThinkPad X200: Initial installation +guide](x200_external.md) to +disassemble the laptop, and access the BIOS rom chip. + +Note: `x86#` refers to commands to be run on the x86 computer, and `pi#` refers +to commands to be run on the pi. A good practice is to make a work directory to +keep your libreboot stuff inside. + + x86# mkdir ~/work + +If you're running Raspian, you can do **sudo raspi-config**, enable SPI +under Advanced and then spidev will be enabled. Simple, eh? + +[Download Libreboot from their releases +page](../../download/). For your safety, verify the +GPG signature as well. + + x86# gpg --keyserver prefered.keyserver.org --recv-keys 0x656F212E + + x86# for signature in $(ls *.sig); do gpg --verify $signature; done + +Install dependencies: + + pi# sudo apt-get update && sudo apt-get install libftdi1 libftdi-dev libusb-dev libpci-dev subversion libusb-1.0-0-dev pciutils, zlib, libusb, build-essential + +Download and build flashrom. + + pi# svn co svn://flashrom.org/flashrom/trunk ~/flashrom + + pi# cd ~/flashrom + + pi# make + + pi# sudo make install + +On your x86 box change the libreboot.rom mac address + + x86# cd ~/work/libreboot_bin/ + +Change the mac address on the libreboot images to match yours. + + x86# ./ich9macchange XX:XX:XX:XX:XX:XX + +Move the libreboot.rom image over to your pi + + x86# scp ~/work/libreboot_bin/ pi@your.pi.address:~/flashrom/libreboot.rom + +Shutdown your pi, write down your rom chip model, and wire up the clip + + pi# sudo shutdown now -hP + +Chip model name + +![](images/rpi/0001.jpg) + +Pinout. You may want to download the image so you can zoom in on the +text. + +![](images/rpi/0002.jpg) + + Pin \# SPI Pin Name Raspberry Pi Pin \# + -------- -------------- --------------------- + 1 *not used* *not used* + 2 3.3V 1 + 3 *not used* *not used* + 4 *not used* *not used* + 5 *not used* *not used* + 6 *not used* *not used* + 7 CS\# 24 + 8 S0/SIO1 21 + 9 *not used* *not used* + 10 GND 25 + 11 *not used* *not used* + 12 *not used* *not used* + 13 *not used* *not used* + 14 *not used* *not used* + 15 S1/SIO0 19 + 16 SCLK 23 + +Note: The raspberry pi 3.3V rail should be sufficient to power the chip during +flashing, so no external power supply should be required; however, at the time +of writing that has only been tested and confirmed for one chip, the +MX25L6405D. + +Macronix Spec sheet so you can adjust your pinout for 8 pin 4Mb chips as +necessary + +![](images/rpi/0014.gif) + +At this point connect your SOIC clip to the rom chip before powering on +your PI. + +Power on your Pi, and run the following. Ensure you swap out +"your\_chip\_name" with the proper name/model of your chip. Check that +it can be read successfully. If you cannot read the chip and receive an +error similar to "no EEPROM Detected" then +you may want to make sure that MISO/MOSI are not swapped around, check +with multimeter whether voltage is right and that ground is connected +between "programmer" and target. + + pi# cd ~/flashrom + + pi# ./flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 --chip -r romread1.rom + + pi# ./flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 --chip -r romread2.rom + + pi# ./flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 --chip -r romread3.rom + + pi# sha512sum romread*.rom + +If they are identical sha512 hashes then you can generally assume that +it's safe to flash your rom. + + pi# ./flashrom -p linux_spi:dev=/dev/spidev0.0,spispeed=512 --chip -w libreboot.rom + +It may fail a couple times, but keep at it and when you get the message +`Verifying flash... Verified` or +`Warning: Chip content is identical to the requested image` then you're +done. + +Shut down your pi, put your box back together, and install a libre OS +for great good! + +Raspberry Pi (C720 Chromebook) +------------------------------- + +The Raspberry Pi (a multipurpose \$25 GNU+Linux computer) can be used as +a BIOS flashing tool, thanks to its GPIO pins and SPI support. + +### [](#what-you-need){#user-content-what-you-need .anchor}What you need + +- \$25 - Raspberry Pi Model B (Rev.2 or higher) +- \$10-20 - SOIC-8 Pomona Clip + - Usually comes bundled with nice, color-colored *female to + female* wires + +### [](#raspberry-pi-pinouts){#user-content-raspberry-pi-pinouts .anchor}Raspberry Pi Pinouts + +GPIO Pinouts: + +![](images/rpi/0009.png) ![](images/rpi/0010.png) + +> \*Diagram made by ["Pacman" from Win-Raid +> Forums\*](http://www.win-raid.com/t58f16-Guide-Recover-from-failed-BIOS-flash-using-Raspberry-PI.md) + +SOIC Pinouts: + +![](docs/rpi/0011.png) + +### [](#plugging-in-the-soic-clip){#user-content-plugging-in-the-soic-clip .anchor}Plugging in the SOIC Clip + +We have to connect the Raspberry Pi to the SOIC Clip as shown in the +below diagram (using the f-f wires usually included with the Pomona +clip). + +![SOIC Pinouts for C720 Chromebook](images/rpi/0003.png) + +(C720 Only?) The diagram depicts a "bridged" connection. You will need +to fashion one with some copper wire: + +![Bridged wires](images/rpi/0004.jpg) + +Plug in the wires to the clip as shown below: + +![Pomona Clip connections](images/rpi/0005.jpg) + +Plug in the other end of the wires to the Raspberry Pi as shown below: + +![Raspberry Pi connections](images/rpi/0006.jpg) + +(C720 only?) Plug in the "bridged" wires as shown below: + +![Bridged wires connected](images/rpi/0007.jpg) + +Finally, put the Pomona SOIC clip on the chip: + +![Pomona Clip Connected](images/rpi/0008.jpg) + +### Flashrom + +[Once it's all set up, flashrom works out of the +box.](http://www.flashrom.org/RaspberryPi) + +### Sources + +- *Pomona SOIC Clip flashing* + - [Arch Linux Wiki - Installing Arch Linux on + Chromebook](https://wiki.archlinux.org/index.php/Chromebook) + - [Google Drive - Raspberry Pi SOIC Clip + connection](https://drive.google.com/folderview?id=0B9f62MH0umbmRTA2Xzd5WHhjWEU&usp=sharing) + - [rPI with Flashrom and SOIC Clip + Powerpoint](http://satxhackers.org/wp/hack-content/uploads/2013/04/rPI_flashrom.pdf) + - [Tnhh - Unbricking Chromebook with + Beaglebone](http://www.tnhh.net/2014/08/25/unbricking-chromebook-with-beaglebone.md) +- *Use a DIY DIP System to flash an desoldered BIOS chip* + - [Viktak - How to recover laptop after failed BIOS + flash](http://diy.viktak.com/2014/07/how-to-recover-laptop-after-failed-bios.md) + - [Win-Raid - Recover from Failed BIOS Flashing using Raspberry + Pi](http://www.win-raid.com/t58f16-Guide-Recover-from-failed-BIOS-flash-using-Raspberry-PI.md) + +Copyright © 2014, 2015 Lawrence Wu \ +Copyright © 2015 snuffeluffegus <>\ +Copyright © 2015 Kevin Keijzer <>\ +Copyright © 2016 Leah Rowe \ + +This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) diff --git a/i18n/fr_FR/docs/install/t400_external.md b/i18n/fr_FR/docs/install/t400_external.md new file mode 100644 index 00000000..362b2243 --- /dev/null +++ b/i18n/fr_FR/docs/install/t400_external.md @@ -0,0 +1,359 @@ +--- +title: Flashing the T400 with a BeagleBone Black +... + +Initial flashing instructions for T400. + +This guide is for those who want libreboot on their ThinkPad T400 while +they still have the original Lenovo BIOS present. This guide can also be +followed (adapted) if you brick your T400, to know how to recover. + +An +["HMM"](https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/43y6629_05.pdf#page=386) +(Hardware Maintenance Manual) detailing the process of \[dis\]assembly +is available for this model. Be careful when reassembling the laptop as +the screws on page 114 (with title "1130 Keyboard bezel") are swapped +and if you follow the HMM you will punch a hole through the bezel in the +upper right corner. + +Serial port {#serial_port} +----------- + +EHCI debug might not be needed. It has been reported that the docking +station for this laptop has a serial port, so it might be possible to +use that instead. + +A note about CPUs +================= + +[ThinkWiki](http://www.thinkwiki.org/wiki/Category:T400) has a list of +CPUs for this system. The Core 2 Duo P8400, P8600 and P8700 are believed +to work in libreboot. + +T9600, T9500, T9550 and T9900 are all compatible, as reported by users. + +Quad-core CPUs +-------------- + +Very likely to be compatible, but requires hardware modification. +Based on info from German forum post about installing Core Quad CPU on T500 found in coreboot mailing list. Currently work in progress and no guide available. + +- [Coreboot mailing list post](https://mail.coreboot.org/pipermail/coreboot/2016-November/082463.html) +- [German forum post about install Core Quad on T500](https://thinkpad-forum.de/threads/199129) + + +A note about GPUs +================= + +Some models have an Intel GPU, while others have both an ATI and an +Intel GPU; this is referred to as "switchable graphics". In the *BIOS +setup* program for lenovobios, you can specify that the system will use +one or the other (but not both). + +Libreboot is known to work on systems with only the Intel GPU, using +native graphics initialization. On systems with switchable graphics, the +Intel GPU is used and the ATI GPU is disabled, so native graphics +initialization works all the same. + +CPU paste required +================== + +See [\#paste](#paste). + +Flash chip size {#flashchips} +=============== + +Use this to find out: + + # flashrom -p internal + +MAC address {#macaddress} +=========== + +Refer to [mac\_address.md](../hardware/mac_address.md). + +Initial BBB configuration +========================= + +Refer to [bbb\_setup.md](bbb_setup.md) for how to configure the BBB +for flashing. + +The following shows how to connect clip to the BBB (on the P9 header), +for SOIC-16 (clip: Pomona 5252): + + POMONA 5252 (correlate with the BBB guide) + === ethernet jack and VGA port ==== + NC - - 21 + 1 - - 17 + NC - - NC + NC - - NC + NC - - NC + NC - - NC + 18 - - 3.3V (PSU) + 22 - - NC - this is pin 1 on the flash chip + === SATA port === + This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. + +The following shows how to connect clip to the BBB (on the P9 header), +for SOIC-8 (clip: Pomona 5250): + + POMONA 5250 (correlate with the BBB guide) + === RAM slots ==== + 18 - - 1 + 22 - - NC + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip + === slot where the AC jack is connected === + + This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. + +The procedure +------------- + +Remove *all* screws, placing them in the order that you removed them:\ +![](images/t400/0001.jpg) ![](images/t400/0002.jpg) + +Remove those three screws then remove the rear bezel:\ +![](images/t400/0003.jpg) ![](images/t400/0004.jpg) +![](images/t400/0005.jpg) ![](images/t400/0006.jpg) + +Remove the speakers:\ +![](images/t400/0007.jpg) ![](images/t400/0008.jpg) +![](images/t400/0009.jpg) ![](images/t400/0010.jpg) +![](images/t400/0011.jpg) + +Remove the wifi:\ +![](images/t400/0012.jpg) ![](images/t400/0013.jpg) + +Remove this cable:\ +![](images/t400/0014.jpg) ![](images/t400/0015.jpg) +![](images/t400/0016.jpg) ![](images/t400/0017.jpg) +![](images/t400/0018.jpg) + +Unroute those antenna wires:\ +![](images/t400/0019.jpg) ![](images/t400/0020.jpg) +![](images/t400/0021.jpg) ![](images/t400/0022.jpg) +![](images/t400/0023.jpg) + +Remove the LCD assembly:\ +![](images/t400/0024.jpg) ![](images/t400/0025.jpg) +![](images/t400/0026.jpg) ![](images/t400/0027.jpg) +![](images/t400/0028.jpg) ![](images/t400/0029.jpg) +![](images/t400/0030.jpg) ![](images/t400/0031.jpg) + +Disconnect the NVRAM battery:\ +![](images/t400/0033.jpg) + +Disconnect the fan:\ +![](images/t400/0034.jpg) + +Unscrew these:\ +![](images/t400/0035.jpg) ![](images/t400/0036.jpg) +![](images/t400/0037.jpg) ![](images/t400/0038.jpg) + +Unscrew the heatsink, then lift it off:\ +![](images/t400/0039.jpg) ![](images/t400/0040.jpg) + +Disconnect the power jack:\ +![](images/t400/0041.jpg) ![](images/t400/0042.jpg) + +Loosen this:\ +![](images/t400/0043.jpg) + +Remove this:\ +![](images/t400/0044.jpg) ![](images/t400/0045.jpg) +![](images/t400/0046.jpg) ![](images/t400/0047.jpg) +![](images/t400/0048.jpg) + +Unscrew these:\ +![](images/t400/0049.jpg) ![](images/t400/0050.jpg) + +Remove this:\ +![](images/t400/0051.jpg) ![](images/t400/0052.jpg) + +Unscrew this:\ +![](images/t400/0053.jpg) + +Remove the motherboard (the cage is still attached) from the right hand +side, then lift it out:\ +![](images/t400/0054.jpg) ![](images/t400/0055.jpg) +![](images/t400/0056.jpg) + +Remove these screws, placing the screws in the same layout and marking +each screw hole (so that you know what ones to put the screws back into +later): ![](images/t400/0057.jpg) ![](images/t400/0058.jpg) +![](images/t400/0059.jpg) ![](images/t400/0060.jpg) +![](images/t400/0061.jpg) ![](images/t400/0062.jpg) + +Separate the motherboard:\ +![](images/t400/0063.jpg) ![](images/t400/0064.jpg) + +Connect your programmer, then connect GND and 3.3V\ +![](images/t400/0065.jpg) ![](images/t400/0066.jpg) +![](images/t400/0067.jpg) ![](images/t400/0069.jpg) +![](images/t400/0070.jpg) ![](images/t400/0071.jpg) + +A dedicated 3.3V PSU was used to create this guide, but at ATX PSU is +also fine:\ +![](images/t400/0072.jpg) + +Of course, make sure to turn on your PSU:\ +![](images/x200/disassembly/0013.jpg) + +Now, you should be ready to install libreboot. + +Flashrom binaries for ARM (tested on a BBB) are distributed in +libreboot\_util. Alternatively, libreboot also distributes flashrom +source code which can be built. + +Log in as root on your BBB, using the instructions in +[bbb\_setup.html\#bbb\_access](bbb_setup.html#bbb_access). + +Test that flashrom works: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 + +In this case, the output was: + + flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) + flashrom is free software, get the source code at http://www.flashrom.org + Calibrating delay loop... OK. + Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. + Found Macronix flash chip "MX25L6406E/MX25L6436E" (8192 kB, SPI) on linux_spi. + Found Macronix flash chip "MX25L6445E/MX25L6473E" (8192 kB, SPI) on linux_spi. + Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)", "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E" + Please specify which chip definition to use with the -c option. + +How to backup factory.rom (change the -c option as needed, for your flash +chip): + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory.rom + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory1.rom + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory2.rom + +Note: the `-c` option is not required in libreboot's patched flashrom, because +the redundant flash chip definitions in `flashchips.c` have been removed. + +Now compare the 3 images: + + # sha512sum factory*.rom + +If the hashes match, then just copy one of them (the factory.rom) to a +safe place (on a drive connected to another system, not the BBB). This +is useful for reverse engineering work, if there is a desirable +behaviour in the original firmware that could be replicated in coreboot +and libreboot. + +Follow the instructions at +[../hardware/gm45\_remove\_me.html\#ich9gen](../hardware/gm45_remove_me.html#ich9gen) +to change the MAC address inside the libreboot ROM image, before +flashing it. Although there is a default MAC address inside the ROM +image, this is not what you want. *Make sure to always change the MAC +address to one that is correct for your system.* + +Now flash it: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w path/to/libreboot/rom/image.rom -V + +![](images/x200/disassembly/0015.jpg) + +You might see errors, but if it says `Verifying flash... VERIFIED` at +the end, then it's flashed and should boot. If you see errors, try +again (and again, and again); the message `Chip content is identical to +the requested image` is also an indication of a successful +installation. + +Example output from running the command (see above): + + flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) + flashrom is free software, get the source code at http://www.flashrom.org + Calibrating delay loop... OK. + Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. + Reading old flash chip contents... done. + Erasing and writing flash chip... FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xd716 + ERASE FAILED! + Reading current flash chip contents... done. Looking for another erase function. + Erase/write done. + Verifying flash... VERIFIED. + +Thermal paste (IMPORTANT) +========================= + +Because part of this procedure involved removing the heatsink, you will +need to apply new paste. Arctic MX-4 is ok. You will also need isopropyl +alcohol and an anti-static cloth to clean with. + +When re-installing the heatsink, you must first clean off all old paste +with the alcohol/cloth. Then apply new paste. Arctic MX-4 is also much +better than the default paste used on these systems. + +![](images/t400/paste.jpg) + +NOTE: the photo above is for illustration purposes only, and does not +show how to properly apply the thermal paste. Other guides online detail +the proper application procedure. + +Wifi +==== + +The T400 typically comes with an Intel wifi chipset, which does not work +without proprietary software. For a list of wifi chipsets that work +without proprietary software, see +[../hardware/\#recommended\_wifi](../hardware/#recommended_wifi). + +Some T400 laptops might come with an Atheros chipset, but this is +802.11g only. + +It is recommended that you install a new wifi chipset. This can only be +done after installing libreboot, because the original firmware has a +whitelist of approved chips, and it will refuse to boot if you use an +'unauthorized' wifi card. + +The following photos show an Atheros AR5B95 being installed, to replace +the Intel chip that this T400 came with:\ +![](images/t400/0012.jpg) ![](images/t400/ar5b95.jpg) + +WWAN +==== + +If you have a WWAN/3G card and/or sim card reader, remove them +permanently. The WWAN-3G card has proprietary firmware inside; the +technology is identical to what is used in mobile phones, so it can also +track your movements. + +Not to be confused with wifi (wifi is fine). + +Memory +====== + +You need DDR3 SODIMM PC3-8500 RAM installed, in matching pairs +(speed/size). Non-matching pairs won't work. You can also install a +single module (meaning, one of the slots will be empty) in slot 0. + +Make sure that the RAM you buy is the 2Rx8 density. + +[This page](http://www.forum.thinkpads.com/viewtopic.php?p=760721) might +be useful for RAM compatibility info (note: coreboot raminit is +different, so this page might be BS) + +The following photo shows 8GiB (2x4GiB) of RAM installed:\ +![](images/t400/memory.jpg) + +Boot it! +-------- + +You should see something like this: + +![](images/t400/boot0.jpg) ![](images/t400/boot1.jpg) + +Now [install GNU+Linux](../gnulinux/). + +Copyright © 2015 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/t500_external.md b/i18n/fr_FR/docs/install/t500_external.md new file mode 100644 index 00000000..fc66387c --- /dev/null +++ b/i18n/fr_FR/docs/install/t500_external.md @@ -0,0 +1,386 @@ +--- +title: Flashing the T500 with a BeagleBone Black +... + +Initial flashing instructions for T500. + +This guide is for those who want libreboot on their ThinkPad T500 while +they still have the original Lenovo BIOS present. This guide can also be +followed (adapted) if you brick your T500, to know how to recover. + +W500 is also mostly compatible with this guide. + +Libreboot T400 {#t400} +============== + +You may also be interested in the smaller, more portable [Libreboot +T400](t400_external.md). + +Serial port {#serial_port} +----------- + +EHCI debug might not be needed. It has been reported that the docking +station for this laptop has a serial port, so it might be possible to +use that instead. + +A note about CPUs +================= + +[ThinkWiki](http://www.thinkwiki.org/wiki/Category:T500) has a list of +CPUs for this system. The Core 2 Duo P8400, P8600 and P8700 are believed +to work in libreboot. The T9600 was also tested on the T400 and +confirmed working. + +T9550 and T9900 was tested by a user, and is compatible as reported in the IRC channel. +T9500 and T9400 may also work, but YMMV. + +Quad-core CPUs +-------------- +Very likely to be compatible, but requires hardware modification. +Based on info from German forum post about installing Core Quad CPU on T500 found in coreboot mailing list. Currently work in progress and no guide available. + +Q9100 is compatible and confirmed working (after hw mod), as reported by users in the IRC +channel + +- [Coreboot mailing list post](https://mail.coreboot.org/pipermail/coreboot/2016-November/082463.html) +- [German forum post about install Core Quad on T500](https://thinkpad-forum.de/threads/199129) + +A note about GPUs +================= + +Some models have an Intel GPU, while others have both an ATI and an +Intel GPU; this is referred to as "switchable graphics". In the *BIOS +setup* program for lenovobios, you can specify that the system will use +one or the other (but not both). + +Libreboot is known to work on systems with only the Intel GPU, using +native graphics initialization. On systems with switchable graphics, the +Intel GPU is used and the ATI GPU is disabled, so native graphics +initialization works all the same. + +CPU paste required +================== + +See [\#paste](#paste). + +Flash chip size {#flashchips} +=============== + +Use this to find out: + + # flashrom -p internal + +MAC address {#macaddress} +=========== + +Refer to [mac\_address.md](../hardware/mac_address.md). + +Initial BBB configuration +========================= + +Refer to [bbb\_setup.md](bbb_setup.md) for how to configure the BBB +for flashing. + +The following shows how to connect clip to the BBB (on the P9 header), +for SOIC-16 (clip: Pomona 5252): + + POMONA 5252 (correlate with the BBB guide) + === ethernet jack and VGA port ==== + NC - - 21 + 1 - - 17 + NC - - NC + NC - - NC + NC - - NC + NC - - NC + 18 - - 3.3V (PSU) + 22 - - NC - this is pin 1 on the flash chip + === SATA port === + This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. + +The following shows how to connect clip to the BBB (on the P9 header), +for SOIC-8 (clip: Pomona 5250): + + POMONA 5250 (correlate with the BBB guide) + === RAM slots ==== + 18 - - 1 + 22 - - NC + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip + === slot where the AC jack is connected === + + This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. + +The procedure +------------- + +Remove all screws:\ +![](images/t500/0000.jpg)\ +It is also advisable to, throughout the disassembly, place any screws +and/or components that you removed in the same layout or arrangement. +The follow photos demonstrate this:\ +![](images/t500/0001.jpg) ![](images/t500/0002.jpg) + +Remove the HDD/SSD and optical drive:\ +![](images/t500/0003.jpg) ![](images/t500/0004.jpg) + +Remove the palm rest:\ +![](images/t500/0005.jpg) ![](images/t500/0006.jpg) + +Remove the keyboard and rear bezel:\ +![](images/t500/0007.jpg) ![](images/t500/0008.jpg) +![](images/t500/0009.jpg) ![](images/t500/0010.jpg) +![](images/t500/0011.jpg) ![](images/t500/0012.jpg) + +If you have a WWAN/3G card and/or sim card reader, remove them +permanently. The WWAN-3G card has proprietary firmware inside; the +technology is identical to what is used in mobile phones, so it can also +track your movements:\ +![](images/t500/0013.jpg) ![](images/t500/0017.jpg) +![](images/t500/0018.jpg) + +Remove this frame, and then remove the wifi chip:\ +![](images/t500/0014.jpg) ![](images/t500/0015.jpg) +![](images/t500/0016.jpg) + +Remove the speakers:\ +![](images/t500/0019.jpg) ![](images/t500/0020.jpg) +![](images/t500/0021.jpg) ![](images/t500/0022.jpg) +![](images/t500/0023.jpg) ![](images/t500/0024.jpg) +![](images/t500/0025.jpg) + +Remove the NVRAM battery (already removed in this photo):\ +![](images/t500/0026.jpg) + +When you re-assemble, you will be replacing the wifi chip with another. +These two screws don't hold anything together, but they are included in +your system because the screw holes for half-height cards are a +different size, so use these if you will be installing a half-height +card:\ +![](images/t500/0027.jpg) + +Unroute the antenna wires:\ +![](images/t500/0028.jpg) ![](images/t500/0029.jpg) +![](images/t500/0030.jpg) ![](images/t500/0031.jpg) + +Disconnect the LCD cable from the motherboard:\ +![](images/t500/0032.jpg) ![](images/t500/0033.jpg) + +Remove the LCD assembly hinge screws, and then remove the LCD assembly:\ +![](images/t500/0034.jpg) ![](images/t500/0035.jpg) +![](images/t500/0036.jpg) + +Remove the fan and heatsink:\ +![](images/t500/0037.jpg) ![](images/t500/0038.jpg) +![](images/t500/0039.jpg) + +Remove this screw:\ +![](images/t500/0040.jpg) + +Remove these cables, keeping note of how and in what arrangement they +are connected:\ +![](images/t500/0041.jpg) ![](images/t500/0042.jpg) +![](images/t500/0043.jpg) ![](images/t500/0044.jpg) +![](images/t500/0045.jpg) ![](images/t500/0046.jpg) +![](images/t500/0047.jpg) ![](images/t500/0048.jpg) +![](images/t500/0049.jpg) + +Disconnect the power jack:\ +![](images/t500/0050.jpg) ![](images/t500/0051.jpg) + +Remove the motherboard and cage from the base (the marked hole is where +those cables were routed through):\ +![](images/t500/0052.jpg) ![](images/t500/0053.jpg) + +Remove all screws, arranging them in the same layout when placing the +screws on a surface and marking each screw hole (this is to reduce the +possibility of putting them back in the wrong holes):\ +![](images/t500/0054.jpg) ![](images/t500/0055.jpg) + +Also remove this:\ +![](images/t500/0056.jpg) ![](images/t500/0057.jpg) + +Separate the motherboard from the cage:\ +![](images/t500/0058.jpg) ![](images/t500/0059.jpg) + +The flash chip is next to the memory slots. On this system, it was a +SOIC-8 (4MiB or 32Mb) flash chip:\ +![](images/t500/0060.jpg) + +Connect your programmer, then connect GND and 3.3V\ +![](images/t500/0061.jpg)\ +![](images/t400/0067.jpg) ![](images/t400/0069.jpg) +![](images/t400/0070.jpg) ![](images/t400/0071.jpg) + +A dedicated 3.3V PSU was used to create this guide, but at ATX PSU is +also fine:\ +![](images/t400/0072.jpg) + +Of course, make sure to turn on your PSU:\ +![](images/x200/disassembly/0013.jpg) + +Now, you should be ready to install libreboot. + +Flashrom binaries for ARM (tested on a BBB) are distributed in +libreboot\_util. Alternatively, libreboot also distributes flashrom +source code which can be built. + +Log in as root on your BBB, using the instructions in +[bbb\_setup.html\#bbb\_access](bbb_setup.html#bbb_access). + +Test that flashrom works: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 + +In this case, the output was: + + flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) + flashrom is free software, get the source code at http://www.flashrom.org + Calibrating delay loop... OK. + Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. + Found Macronix flash chip "MX25L6406E/MX25L6436E" (8192 kB, SPI) on linux_spi. + Found Macronix flash chip "MX25L6445E/MX25L6473E" (8192 kB, SPI) on linux_spi. + Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)", "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E" + Please specify which chip definition to use with the -c option. + +How to backup factory.rom (change the -c option as neeed, for your flash +chip): + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory.rom + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory1.rom + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory2.rom + +Note: the `-c` option is not required in libreboot's patched +flashrom, because the redundant flash chip definitions in *flashchips.c* +have been removed.\ +Now compare the 3 images: + + # sha512sum factory\*.rom + +If the hashes match, then just copy one of them (the factory.rom) to a +safe place (on a drive connected to another system, not the BBB). This +is useful for reverse engineering work, if there is a desirable +behaviour in the original firmware that could be replicated in coreboot +and libreboot. + +Follow the instructions at +[../hardware/gm45\_remove\_me.html\#ich9gen](../hardware/gm45_remove_me.html#ich9gen) +to change the MAC address inside the libreboot ROM image, before +flashing it. Although there is a default MAC address inside the ROM +image, this is not what you want. *Make sure to always change the MAC +address to one that is correct for your system.* + +Now flash it: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w + +path/to/libreboot/rom/image.rom -V + +![](images/x200/disassembly/0015.jpg) + +You might see errors, but if it says `Verifying flash... VERIFIED` at +the end, then it's flashed and should boot. If you see errors, try +again (and again, and again); the message `Chip content is identical to +the requested image` is also an indication of a successful +installation. + +Example output from running the command (see above): + + flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) + flashrom is free software, get the source code at http://www.flashrom.org + Calibrating delay loop... OK. + Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. + Reading old flash chip contents... done. + Erasing and writing flash chip... FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xd716 + ERASE FAILED! + Reading current flash chip contents... done. Looking for another erase function. + Erase/write done. + Verifying flash... VERIFIED. + +Thermal paste (IMPORTANT) +========================= + +Because part of this procedure involved removing the heatsink, you will +need to apply new paste. Arctic MX-4 is ok. You will also need isopropyl +alcohol and an anti-static cloth to clean with. + +When re-installing the heatsink, you must first clean off all old paste +with the alcohol/cloth. Then apply new paste. Arctic MX-4 is also much +better than the default paste used on these systems. + +![](images/t400/paste.jpg) + +NOTE: the photo above is for illustration purposes only, and does not +show how to properly apply the thermal paste. Other guides online detail +the proper application procedure. + +Wifi +==== + +The T500 typically comes with an Intel wifi chipset, which does not work +without proprietary software. For a list of wifi chipsets that work +without proprietary software, see +[../hardware/\#recommended\_wifi](../hardware/#recommended_wifi). + +Some T500 laptops might come with an Atheros chipset, but this is +802.11g only. + +It is recommended that you install a new wifi chipset. This can only be +done after installing libreboot, because the original firmware has a +whitelist of approved chips, and it will refuse to boot if you use an +'unauthorized' wifi card. + +The following photos show an Atheros AR5B95 being installed, to replace +the Intel chip that this T500 came with:\ +![](images/t400/0012.jpg) ![](images/t400/ar5b95.jpg) + +WWAN +==== + +If you have a WWAN/3G card and/or sim card reader, remove them +permanently. The WWAN-3G card has DMA, and proprietary firmware inside; +the technology is identical to what is used in mobile phones, so it can +also track your movements. + +Not to be confused with wifi (wifi is fine). + +Memory +====== + +DDR3 SO-DIMM sticks will work at PC3-8500 clock and voltage, so make sure that +timings of sticks are matched while they operate at its frequency. +Non-matching pairs won't work. You can also install a +single module (meaning, one of the slots will be empty) in slot 0. + +Make sure that the RAM you buy has 2Rx8 arrangement when buying 4GiB modules. + +[This page](http://www.forum.thinkpads.com/viewtopic.php?p=760721) might +be useful for RAM compatibility info (note: coreboot raminit is +different, so this page might be BS) + +The following photo shows 8GiB (2x4GiB) of RAM installed:\ +![](images/t400/memory.jpg) + +Boot it! +-------- + +You should see something like this: + +![](images/t500/0062.jpg) + +Now [install GNU+Linux](../gnulinux/). + +Copyright © 2015 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/t60_unbrick.md b/i18n/fr_FR/docs/install/t60_unbrick.md new file mode 100644 index 00000000..c61c3a5e --- /dev/null +++ b/i18n/fr_FR/docs/install/t60_unbrick.md @@ -0,0 +1,211 @@ +--- +title: ThinkPad T60 Recovery guide +x-toc-enable: true +... + +This section documents how to recover from a bad flash that prevents +your ThinkPad T60 from booting. + +Brick type 1: bucts not reset. {#bucts_brick} +============================== + +You still have Lenovo BIOS, or you had libreboot running and you flashed +another ROM; and you had bucts 1 set and the ROM wasn't dd'd.\* or if +Lenovo BIOS was present and libreboot wasn't flashed.\ + +In this case, unbricking is easy: reset BUC.TS to 0 by removing that +yellow cmos coin (it's a battery) and putting it back after a minute or +two:\ +![](../images/t60_dev/0006.JPG)\ + +\*Those dd commands should be applied to all newly compiled T60 ROM +images (the ROM images in libreboot binary archives already have this +applied!):\ +dd if=coreboot.rom of=top64k.bin bs=1 skip=\$\[\$(stat -c %s +coreboot.rom) - 0x10000\] count=64k\ +dd if=coreboot.rom bs=1 skip=\$\[\$(stat -c %s coreboot.rom) - 0x20000\] +count=64k | hexdump\ +dd if=top64k.bin of=coreboot.rom bs=1 seek=\$\[\$(stat -c %s +coreboot.rom) - 0x20000\] count=64k conv=notrunc\ +(doing this makes the ROM suitable for use when flashing a system that +still has Lenovo BIOS running, using those instructions: +. (it says x60, +but instructions for t60 are identical) + +bad rom (or user error), system won't boot {#recovery} +=========================================== + +In this scenario, you compiled a ROM that had an incorrect +configuration, or there is an actual bug preventing your system from +booting. Or, maybe, you set BUC.TS to 0 and shut down after first flash +while Lenovo BIOS was running. In any case, your system is bricked and +will not boot at all. + +"Unbricking" means flashing a known-good (working) ROM. The problem: +you can't boot the system, making this difficult. In this situation, +external hardware (see hardware requirements above) is needed which can +flash the SPI chip (where libreboot resides). + +Remove those screws and remove the HDD:\ +![](../images/t60_dev/0001.JPG) ![](../images/t60_dev/0002.JPG) + +Lift off the palm rest:\ +![](../images/t60_dev/0003.JPG) + +Lift up the keyboard, pull it back a bit, flip it over like that and +then disconnect it from the board:\ +![](../images/t60_dev/0004.JPG) ![](../images/t60_dev/0005.JPG) +![](../images/t60_dev/0006.JPG) + +Gently wedge both sides loose:\ +![](../images/t60_dev/0007.JPG) ![](../images/t60_dev/0008.JPG) + +Remove that cable from the position:\ +![](../images/t60_dev/0009.JPG) ![](../images/t60_dev/0010.JPG) + +Now remove that bezel. Remove wifi, nvram battery and speaker connector +(also remove 56k modem, on the left of wifi):\ +![](../images/t60_dev/0011.JPG) + +Remove those screws:\ +![](../images/t60_dev/0012.JPG) + +Disconnect the power jack:\ +![](../images/t60_dev/0013.JPG) + +Remove nvram battery:\ +![](../images/t60_dev/0014.JPG) + +Disconnect cable (for 56k modem) and disconnect the other cable:\ +![](../images/t60_dev/0015.JPG) ![](../images/t60_dev/0016.JPG) + +Disconnect speaker cable:\ +![](../images/t60_dev/0017.JPG) + +Disconnect the other end of the 56k modem cable:\ +![](../images/t60_dev/0018.JPG) + +Make sure you removed it:\ +![](../images/t60_dev/0019.JPG) + +Unscrew those:\ +![](../images/t60_dev/0020.JPG) + +Make sure you removed those:\ +![](../images/t60_dev/0021.JPG) + +Disconnect LCD cable from board:\ +![](../images/t60_dev/0022.JPG) + +Remove those screws then remove the LCD assembly:\ +![](../images/t60_dev/0023.JPG) ![](../images/t60_dev/0024.JPG) +![](../images/t60_dev/0025.JPG) + +Once again, make sure you removed those:\ +![](../images/t60_dev/0026.JPG) + +Remove the shielding containing the motherboard, then flip it over. +Remove these screws, placing them on a steady surface in the same layout +as they were in before you removed them. Also, you should mark each +screw hole after removing the screw (a permanent marker pen will do), +this is so that you have a point of reference when re-assembling the +system: + +![](../images/t60_dev/0027.JPG) ![](../images/t60_dev/0028.JPG) +![](../images/t60_dev/0029.JPG) ![](../images/t60_dev/0031.JPG) +![](../images/t60_dev/0032.JPG) ![](../images/t60_dev/0033.JPG) + +Now wire up the BBB and the Pomona with your PSU.\ +Refer to [bbb\_setup.md](bbb_setup.md) for how to setup the BBB for +flashing. + +*Note, the guide mentions a 3.3v DC PSU but you don't need this on the +T60: if you don't have or don't want to use an external PSU, then make +sure not to connect the 3.3v leads mentioned in the guide; instead, +connect the AC adapter (the one that normally charges your battery) so +that the board has power (but don't boot it up)* + +![](../images/t60_dev/0030.JPG) + +Correlate the following with the BBB guide linked above: + + POMONA 5250: + === DVD drive ==== + 18 - - 1 + 22 - - NC ---- RAM is on this end + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip + === audio jacks === + This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. + +Connect the pomona from the BBB to the flash chip. No pics +unfortunately. (use the text diagram above). + +Flashrom binaries for ARM (tested on a BBB) are distributed in +libreboot\_util. Alternatively, libreboot also distributes flashrom +source code which can be built. + +SSH'd into the BBB: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w + +yourrom.rom + +It should be `Verifying flash... VERIFIED` at the end. If flashrom +complains about multiple flash chip definitions detected, then choose +one of them following the instructions in the output. + +Put those screws back:\ +![](../images/t60_dev/0047.JPG) + +Put it back into lower chassis:\ +![](../images/t60_dev/0048.JPG) + +Attach LCD and insert screws (also, attach the lcd cable to the board):\ +![](../images/t60_dev/0049.JPG) + +Insert those screws:\ +![](../images/t60_dev/0050.JPG) + +On the CPU (and there is another chip south-east to it, sorry forgot to +take pic) clean off the old thermal paste (with the alcohol) and apply +new (Artic Silver 5 is good, others are good too) you should also clean +the heatsink the same way\ +![](../images/t60_dev/0051.JPG) + +Attach the heatsink and install the screws (also, make sure to install +the AC jack as highlighted):\ +![](../images/t60_dev/0052.JPG) + +Reinstall that upper bezel:\ +![](../images/t60_dev/0053.JPG) + +Do that:\ +![](../images/t60_dev/0054.JPG) ![](../images/t60_dev/0055.JPG) + +Re-attach modem, wifi, (wwan?), and all necessary cables. Sorry, forgot +to take pics. Look at previous removal steps to see where they go back +to. + +Attach keyboard and install nvram battery:\ +![](../images/t60_dev/0056.JPG) ![](../images/t60_dev/0057.JPG) + +Place keyboard and (sorry, forgot to take pics) reinstall the palmrest +and insert screws on the underside:\ +![](../images/t60_dev/0058.JPG) + +It lives!\ +![](../images/t60_dev/0071.JPG) ![](../images/t60_dev/0072.JPG) +![](../images/t60_dev/0073.JPG) + +Always stress test ('stress -c 2' and xsensors. below 90C is ok) when +replacing cpu paste/heatsink:\ +![](../images/t60_dev/0074.JPG) + +Copyright © 2014, 2015 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/x200_external.md b/i18n/fr_FR/docs/install/x200_external.md new file mode 100644 index 00000000..0b574a68 --- /dev/null +++ b/i18n/fr_FR/docs/install/x200_external.md @@ -0,0 +1,305 @@ +--- +title: Flashing the X200 with a BeagleBone Black +x-toc-enable: true +... + +This guide is for those who want libreboot on their ThinkPad X200 while +they still have the original Lenovo BIOS present. This guide can also be +followed (adapted) if you brick your X200, to know how to recover. + +X200 laptops with libreboot pre-installed +========================================= + +If you don't want to install libreboot yourself, companies exist that +sell these laptops with libreboot pre-installed, along with a free +GNU+Linux distribution. + +Flash chip size +=============== + +Run this command on x200 to find out flash chip model and its size: + + # flashrom -p internal + +The X200S and X200 Tablet will use a WSON-8 flash chip, on the bottom of the +motherboard (this requires removal of the motherboard). Not all X200S/X200T are +supported; see the [hardware](../hardware/x200.html#x200s) page. + +MAC address +=========== + +Refer to [mac\_address.md](../hardware/mac_address.md). + +Initial BBB configuration +========================= + +Refer to [bbb\_setup.md](bbb_setup.md) for how to set up the BBB for +flashing. + +The following table shows how to connect the test clip to the BBB (on the P9 +header), for SOIC-8/SOIC-16: + +|BeagleBoneBlack|Pin on P9|SPI |25xx SOIC8 pin|SOIC16|Ball |DTS | +|---------------|---------|----|--------------|------|--------|---------| +|I2C1_SCL |17 |/CS |1 |7 |A16 |spi0_cs0 | +|I2C1_SDA |18 |MOSI|5 |15 |B16 |spi0_d1 | +|UART2_RXD |22 |CLK |6 |16 |A17 |spi0_sclk| +|UART2_TXD |21 |MISO|2 |8 |B17 |spi0_d0 | +|GND |1 or 2 |GND |4 |10 |GND |GND | +|VDD_3V3D |3 or 4 |Vcc |8 |2 |VDD_3V3D|VDD_3V3D | + +*Pictures of flash chip location are located further down on this page* + +If onboard 3.3V supply happens to be insuficient, use a separate +module/power supply and set its current limit to 400mA. +Do not forget that in this case ground has to be continuous across between +motherboard, BBB and PSU (all three)! + +On the X200S and X200 Tablet the flash chip is underneath the board, in a WSON +package. The pinout is very much the same as a SOIC-8, but such package makes +it impossible to use testclip. In order to enable external flashing of device, +chip has to be changed to SOIC-8 one. Such procedure requires hot air station +and soldering station (with "knife" K-Tip to easily solder SOIC-8). + +Check the list of SOIC-8 flash chips at [List of supported flash +chips](https://www.flashrom.org/Supported_hardware#Supported_flash_chips)\ 25XX +series SPI NOR Flash in 8/16MiB sizes will work fine with libreboot. + +The procedure +------------- + +This section is for the X200. This does not apply to the X200S or X200 +Tablet (for those systems, you have to remove the motherboard +completely, since the flash chip is on the other side of the board). + +Remove these screws:\ +![](images/x200/disassembly/0003.jpg) + +Gently push the keyboard towards the screen, then lift it off, and optionally +disconnect it from the board:\ +![](images/x200/disassembly/0004.jpg) +![](images/x200/disassembly/0005.jpg) + +Disconnect the cable of the fingerpring reader, and then pull up the palm rest, +lifting up the left and right side of it:\ +![](images/x200/disassembly/0006.1.jpg) +![](images/x200/disassembly/0006.jpg) + +This shows the location of the flash chip, for both SOIC-8 and SOIC-16:\ +![](images/x200/x200_soic16.jpg) +![](images/x200/x200_soic8.jpg) + +Lift back the tape that covers a part of the flash chip, and then +connect the clip:\ +![](images/x200/disassembly/0008.jpg) + +On pin 2 of the BBB, where you have the ground (GND), connect the ground +to your PSU:\ +![](images/x200/disassembly/0009.jpg) +![](images/x200/disassembly/0010.jpg) + +Connect the 3.3V DC supply from your PSU to the flash chip (via the clip):\ +![](images/x200/disassembly/0011.jpg) +![](images/x200/disassembly/0012.jpg) + +Now, you should be ready to install libreboot. + +Flashrom binaries for ARM (tested on a BBB) are distributed in +libreboot\_util. Alternatively, libreboot also distributes flashrom +source code which can be built. + +Log in as root on your BBB, using the instructions in +[bbb\_setup.html\#bbb\_access](bbb_setup.html#bbb_access). + +Probe for chips with flashrom: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 + +In this case, the output was: + + flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) + flashrom is free software, get the source code at http://www.flashrom.org + Calibrating delay loop... OK. + Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. + Found Macronix flash chip "MX25L6406E/MX25L6436E" (8192 kB, SPI) on linux_spi. + Found Macronix flash chip "MX25L6445E/MX25L6473E" (8192 kB, SPI) on linux_spi. + Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)", "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E" + Please specify which chip definition to use with the -c option. + +Here is how to backup factory.rom: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory.rom + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory1.rom + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory2.rom + +Note: the `-c` option is not required in libreboot's patched +flashrom, because the redundant flash chip definitions in *flashchips.c* +have been removed. + +Now compare the 3 images: + + # sha512sum factory*.rom + +If the hashes match and if hex editor (like `dhex`) shows that +they have valid contents (eg. it's not filled entirely with `0x00`/`0xFF`), +then just copy one of them (the factory.rom) to a +safe place (on a drive connected to another system, not the BBB). This +is useful for reverse engineering work, if there is a desirable +behaviour in the original firmware that could be replicated in coreboot +and libreboot. + +Follow the instructions at +[../hardware/gm45\_remove\_me.html\#ich9gen](../hardware/gm45_remove_me.html#ich9gen) +to change the MAC address inside the libreboot ROM image, before +flashing it. Although there is a default MAC address inside the ROM +image, this is not what you want. Make sure to always change the MAC +address to one that is correct for your system. + +Now flash it: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w path/to/libreboot/rom/image.rom + +![](images/x200/disassembly/0015.jpg) + +You might see errors, but if it says `Verifying flash... VERIFIED` at +the end, then it's flashed and should boot. If you see errors, try +again (and again, and again); the message `Chip content is identical to +the requested image` is also an indication of a successful +installation. + +Example output from running the command (see above): + + flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) + flashrom is free software, get the source code at http://www.flashrom.org + Calibrating delay loop... OK. + Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. + Reading old flash chip contents... done. + Erasing and writing flash chip... FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xd716 + ERASE FAILED! + Reading current flash chip contents... done. Looking for another erase function. + Erase/write done. + Verifying flash... VERIFIED. + +Wifi +==== + +The X200 typically comes with an Intel wifi chipset, which does not work +without proprietary software. For a list of wifi chipsets that work +without proprietary software, see +[../hardware/\#recommended\_wifi](../hardware/#recommended_wifi). + +Some X200 laptops come with an Atheros chipset, but this is 802.11g +only. + +It is recommended that you install a new wifi chipset. This can only be +done after installing libreboot, because the original firmware has a +whitelist of approved chips, and it will refuse to boot if you use an +'unauthorized' wifi card. + +The following photos show an Atheros AR5B95 being installed, to replace +the Intel chip that this X200 came with: + +![](images/x200/disassembly/0016.jpg) +![](images/x200/disassembly/0017.jpg) + +WWAN +==== + +If you have a WWAN/3G card and/or sim card reader, remove them +permanently. The WWAN-3G card has proprietary firmware inside; the +technology is identical to what is used in mobile phones, so it can also +track your movements. + +Not to be confused with wifi (wifi is fine). + +Intel Turbo Memory +================== + +Some X200 devices were sold with Intel Turbo Memory installed in the top-most +mini PCI-e slot. + +If you have one installed, you should probably remove it as it mostly likely +brings no benefits, while having many issues: +- It has been [shown to be + ineffective](http://www.anandtech.com/show/2252) at disk caching or battery + saving in most use cases. Having it installed might lead to more + battery consumption. +- Using it will most likely lead to data loss because with its + [driver](https://github.com/yarrick/turbomem), + "data cannot be written/read back reliably". The driver development + has also stopped. +- It might also be a security risk as it may have access to the system + RAM through the PCIe bus. + +Memory +====== + +You need DDR3 SODIMM PC3-8500 RAM installed, in matching pairs +(speed/size) as some non-matching pairs are known not to work. +You can also install a single module (meaning, one of the +slots will be empty) in slot 0. + +Make sure that the RAM you buy is the 2Rx8 density. + +In this photo, 8GiB of RAM (2x4GiB) is installed: + +![](images/x200/disassembly/0018.jpg) + +Boot it! +-------- + +You should see something like this: + +![](images/x200/disassembly/0019.jpg) + +Now [install GNU+Linux](../gnulinux/). + +X200S and X200 Tablet users: GPIO33 trick will not work. +-------------------------------------------------------- + +sgsit found out about a pin called GPIO33, which can be grounded to +disable the flashing protections by the descriptor and stop the ME from +starting (which itself interferes with flashing attempts). The theory +was proven correct; however, it is still useless in practise. + +Look just above the 7 in TP37 (that's GPIO33): + +![](../hardware/images/x200/gpio33_location.jpg) + +By default we would see this in lenovobios, when trying flashrom -p +internal -w rom.rom: + + FREG0: Warning: Flash Descriptor region (0x00000000-0x00000fff) is read-only. + FREG2: Warning: Management Engine region (0x00001000-0x005f5fff) is locked. + +With GPIO33 grounded during boot, this disabled the flash protections as +set by descriptor, and stopped the ME from starting. The output changed +to: + + The Flash Descriptor Override Strap-Pin is set. Restrictions implied by + the Master Section of the flash descriptor are NOT in effect. Please note + that Protected Range (PR) restrictions still apply. + +The part in bold is what got us. This was still observed: + + PR0: Warning: 0x007e0000-0x01ffffff is read-only. + PR4: Warning: 0x005f8000-0x005fffff is locked. + +It is actually possible to disable these protections. Lenovobios does, +when updating the BIOS (proprietary one). One possible way to go about +this would be to debug the BIOS update utility from Lenovo, to find out +how it's disabling these protections. Some more research is available +here: + + +On a related note, libreboot has a utility that could help with +investigating this: +[../hardware/gm45\_remove\_me.html\#demefactory](../hardware/gm45_remove_me.md#demefactory) + +Copyright © 2014, 2015 Leah Rowe + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/x60_unbrick.md b/i18n/fr_FR/docs/install/x60_unbrick.md new file mode 100644 index 00000000..d7cb17a8 --- /dev/null +++ b/i18n/fr_FR/docs/install/x60_unbrick.md @@ -0,0 +1,218 @@ +--- +title: ThinkPad X60 Recovery guide +x-toc-enable: true +... + +This section documents how to recover from a bad flash that prevents +your ThinkPad X60 from booting. + +Brick type 1: bucts not reset. {#bucts_brick} +============================== + +You still have Lenovo BIOS, or you had libreboot running and you flashed +another ROM; and you had bucts 1 set and the ROM wasn't dd'd.\* or if +Lenovo BIOS was present and libreboot wasn't flashed.\ + +In this case, unbricking is easy: reset BUC.TS to 0 by removing that +yellow cmos coin (it's a battery) and putting it back after a minute or +two:\ +![](../images/x60_unbrick/0004.jpg)\ + +\*Those dd commands should be applied to all newly compiled X60 ROM +images (the ROM images in libreboot binary archives already have this +applied!): + + dd if=coreboot.rom of=top64k.bin bs=1 skip=\$\[\$(stat -c %s coreboot.rom) - 0x10000\] count=64k + dd if=coreboot.rom bs=1 skip=\$\[\$(stat -c %s coreboot.rom) - 0x20000\] count=64k | hexdump + dd if=top64k.bin of=coreboot.rom bs=1 seek=\$\[\$(stat -c %s coreboot.rom) - 0x20000\] count=64k conv=notrunc + +(doing this makes the ROM suitable for use when flashing a system that +still has Lenovo BIOS running, using those instructions: +. + +bad rom (or user error), system won't boot {#recovery} +=========================================== + +In this scenario, you compiled a ROM that had an incorrect +configuration, or there is an actual bug preventing your system from +booting. Or, maybe, you set BUC.TS to 0 and shut down after first flash +while Lenovo BIOS was running. In any case, your system is bricked and +will not boot at all. + +"Unbricking" means flashing a known-good (working) ROM. The problem: +you can't boot the system, making this difficult. In this situation, +external hardware (see hardware requirements above) is needed which can +flash the SPI chip (where libreboot resides). + +Remove those screws:\ +![](../images/x60_unbrick/0000.jpg) + +Push the keyboard forward (carefully):\ +![](../images/x60_unbrick/0001.jpg) + +Lift the keyboard up and disconnect it from the board:\ +![](../images/x60_unbrick/0002.jpg) + +Grab the right-hand side of the chassis and force it off (gently) and +pry up the rest of the chassis:\ +![](../images/x60_unbrick/0003.jpg) + +You should now have this:\ +![](../images/x60_unbrick/0004.jpg) + +Disconnect the wifi antenna cables, the modem cable and the speaker:\ +![](../images/x60_unbrick/0005.jpg) + +Unroute the cables along their path, carefully lifting the tape that +holds them in place. Then, disconnect the modem cable (other end) and +power connection and unroute all the cables so that they dangle by the +monitor hinge on the right-hand side:\ +![](../images/x60_unbrick/0006.jpg) + +Disconnect the monitor from the motherboard, and unroute the grey +antenna cable, carefully lifting the tape that holds it into place:\ +![](../images/x60_unbrick/0008.jpg) + +Carefully lift the remaining tape and unroute the left antenna cable so +that it is loose:\ +![](../images/x60_unbrick/0009.jpg) + +Remove the screw that is highlighted (do NOT remove the other one; it +holds part of the heatsink (other side) into place):\ +![](../images/x60_unbrick/0011.jpg) + +Remove those screws:\ +![](../images/x60_unbrick/0012.jpg) + +Carefully remove the plate, like so:\ +![](../images/x60_unbrick/0013.jpg) + +Remove the SATA connector:\ +![](../images/x60_unbrick/0014.jpg) + +Now remove the motherboard (gently) and cast the lcd/chassis aside:\ +![](../images/x60_unbrick/0015.jpg) + +Lift back that tape and hold it with something. Highlighted is the SPI +flash chip:\ +![](../images/x60_unbrick/0016.jpg) + +Now wire up the BBB and the Pomona with your PSU.\ +Refer to [bbb\_setup.md](bbb_setup.md) for how to setup the BBB for +flashing.\ +*Note, the guide mentions a 3.3v DC PSU but you don't need this on the +X60: if you don't have or don't want to use an external PSU, then make +sure not to connect the 3.3v leads mentioned in the guide; instead, +connect the AC adapter (the one that normally charges your battery) so +that the board has power (but don't boot it up)* +![](../images/x60_unbrick/0017.jpg)\ +Correlate the following with the BBB guide linked above: + + POMONA 5250: + === golden finger and wifi switch ==== + 18 - - 1 + 22 - - NC ---------- audio jacks are on this end + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip + === CPU fan === + This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. + +Connecting the BBB and pomona (in this image, an external 3.3v DC PSU +was used):\ +![](images/x60/th_bbb_flashing.jpg) + +Flashrom binaries for ARM (tested on a BBB) are distributed in +libreboot\_util. Alternatively, libreboot also distributes flashrom +source code which can be built. + +SSH'd into the BBB: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w + +yourrom.rom + +It should be `Verifying flash... VERIFIED` at the end. If flashrom +complains about multiple flash chip definitions detected, then choose +one of them following the instructions in the output. + +Remove the programmer and put it away somewhere. Put back the tape and +press firmly over it:\ +![](../images/x60_unbrick/0026.jpg) + +Your empty chassis:\ +![](../images/x60_unbrick/0027.jpg) + +Put the motherboard back in:\ +![](../images/x60_unbrick/0028.jpg) + +Reconnect SATA:\ +![](../images/x60_unbrick/0029.jpg) + +Put the plate back and re-insert those screws:\ +![](../images/x60_unbrick/0030.jpg) + +Re-route that antenna cable around the fan and apply the tape:\ +![](../images/x60_unbrick/0031.jpg) + +Route the cable here and then (not shown, due to error on my part) +reconnect the monitor cable to the motherboard and re-insert the +screws:\ +![](../images/x60_unbrick/0032.jpg) + +Re-insert that screw:\ +![](../images/x60_unbrick/0033.jpg) + +Route the black antenna cable like so:\ +![](../images/x60_unbrick/0034.jpg) + +Tuck it in neatly like so:\ +![](../images/x60_unbrick/0035.jpg) + +Route the modem cable like so:\ +![](../images/x60_unbrick/0036.jpg) + +Connect modem cable to board and tuck it in neatly like so:\ +![](../images/x60_unbrick/0037.jpg) + +Route the power connection and connect it to the board like so:\ +![](../images/x60_unbrick/0038.jpg) + +Route the antenna and modem cables neatly like so:\ +![](../images/x60_unbrick/0039.jpg) + +Connect the wifi antenna cables. At the start of the tutorial, this +system had an Intel wifi chip. Here you see I've replaced it with an +Atheros AR5B95 (supports 802.11n and can be used without blobs):\ +![](../images/x60_unbrick/0040.jpg) + +Connect the modem cable:\ +![](../images/x60_unbrick/0041.jpg) + +Connect the speaker:\ +![](../images/x60_unbrick/0042.jpg) + +You should now have this:\ +![](../images/x60_unbrick/0043.jpg) + +Re-connect the upper chassis:\ +![](../images/x60_unbrick/0044.jpg) + +Re-connect the keyboard:\ +![](../images/x60_unbrick/0045.jpg) + +Re-insert the screws that you removed earlier:\ +![](../images/x60_unbrick/0046.jpg) + +Power on!\ +![](../images/x60_unbrick/0047.jpg) + +Operating system:\ +![](../images/x60_unbrick/0049.jpg) + +Copyright © 2014, 2015 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/install/x60flashscript.patch b/i18n/fr_FR/docs/install/x60flashscript.patch new file mode 100644 index 00000000..7f4c8307 --- /dev/null +++ b/i18n/fr_FR/docs/install/x60flashscript.patch @@ -0,0 +1,27 @@ +From 34270811fce1ecf0bcf3b1363b0dc3dbf284ab09 Mon Sep 17 00:00:00 2001 +From: Leah Rowe +Date: Wed, 10 Jun 2015 22:53:28 +0000 +Subject: flash script: fix a really really really dumb mistake + +--- +diff --git a/flash b/flash +index c96b915..04fd274 100755 +--- a/flash ++++ b/flash +@@ -95,12 +95,12 @@ if [ "$mode" = "i945lenovo_firstflash" ] || [ "$mode" = "i945lenovo_secondflash" + # git or libreboot_src + bucts="./bucts/bucts" + flashrom_lenovobios_sst="./flashrom/flashrom_lenovobios_sst" +- flashrom_lenovobios_macronix="./flashrom/flashrom_lenovobios_sst" ++ flashrom_lenovobios_macronix="./flashrom/flashrom_lenovobios_macronix" + else + # libreboot_util + bucts="./bucts/$arch/bucts" + flashrom_lenovobios_sst="./flashrom/$arch/flashrom_lenovobios_sst" +- flashrom_lenovobios_macronix="./flashrom/$arch/flashrom_lenovobios_sst" ++ flashrom_lenovobios_macronix="./flashrom/$arch/flashrom_lenovobios_macronix" + fi + + # anti-bricking precaution +-- +cgit v0.9.0.2 diff --git a/i18n/fr_FR/docs/install/x60tablet_unbrick.md b/i18n/fr_FR/docs/install/x60tablet_unbrick.md new file mode 100644 index 00000000..fe4352bc --- /dev/null +++ b/i18n/fr_FR/docs/install/x60tablet_unbrick.md @@ -0,0 +1,125 @@ +--- +title: ThinkPad X60 Tablet Recovery guide +x-toc-enable: true +... + +This section documents how to recover from a bad flash that prevents +your ThinkPad X60 Tablet from booting. + +Brick type 1: bucts not reset. {#bucts_brick} +============================== + +You still have Lenovo BIOS, or you had libreboot running and you flashed +another ROM; and you had bucts 1 set and the ROM wasn't dd'd.\* or if +Lenovo BIOS was present and libreboot wasn't flashed.\ + +In this case, unbricking is easy: reset BUC.TS to 0 by removing that +yellow cmos coin (it's a battery) and putting it back after a minute or +two:\ +![](../images/x60t_unbrick/0008.JPG)\ + +\*Those dd commands should be applied to all newly compiled X60 ROM +images (the ROM images in libreboot binary archives already have this +applied!): + + dd if=coreboot.rom of=top64k.bin bs=1 skip=\$\[\$(stat -c %s coreboot.rom) - 0x10000\] count=64k + dd if=coreboot.rom bs=1 skip=\$\[\$(stat -c %s coreboot.rom) - 0x20000\] count=64k | hexdump + dd if=top64k.bin of=coreboot.rom bs=1 seek=\$\[\$(stat -c %s coreboot.rom) - 0x20000\] count=64k conv=notrunc + +(doing this makes the ROM suitable for use when flashing a system that +still has Lenovo BIOS running, using those instructions: +. + +bad rom (or user error), system won't boot {#recovery} +=========================================== + +In this scenario, you compiled a ROM that had an incorrect +configuration, or there is an actual bug preventing your system from +booting. Or, maybe, you set BUC.TS to 0 and shut down after first flash +while Lenovo BIOS was running. In any case, your system is bricked and +will not boot at all. + +"Unbricking" means flashing a known-good (working) ROM. The problem: +you can't boot the system, making this difficult. In this situation, +external hardware (see hardware requirements above) is needed which can +flash the SPI chip (where libreboot resides). + +![](../images/x60t_unbrick/0000.JPG) + +Remove those screws:\ +![](../images/x60t_unbrick/0001.JPG) + +Remove the HDD:\ +![](../images/x60t_unbrick/0002.JPG) + +Push keyboard forward to loosen it:\ +![](../images/x60t_unbrick/0003.JPG) + +Lift:\ +![](../images/x60t_unbrick/0004.JPG) + +Remove those:\ +![](../images/x60t_unbrick/0005.JPG) + +![](../images/x60t_unbrick/0006.JPG) + +Also remove that (marked) and unroute the antenna cables:\ +![](../images/x60t_unbrick/0007.JPG) + +For some X60T laptops, you have to unroute those too:\ +![](../images/x60t_unbrick/0010.JPG) + +Remove the LCD extend board screws. Also remove those screws (see blue +marks) and remove/unroute the cables and remove the metal plate:\ +![](../images/x60t_unbrick/0008.JPG) + +Remove that screw and then remove the board:\ +![](../images/x60t_unbrick/0009.JPG) + +Now wire up the BBB and the Pomona with your PSU.\ +Refer to [bbb\_setup.md](bbb_setup.md) for how to setup the BBB for +flashing.\ +*Note, the guide mentions a 3.3v DC PSU but you don't need this on the +X60 Tablet: if you don't have or don't want to use an external PSU, +then make sure not to connect the 3.3v leads mentioned in the guide; +instead, connect the AC adapter (the one that normally charges your +battery) so that the board has power (but don't boot it up)* +![](../images/x60t_unbrick/0011.JPG)\ +Correlate the following with the BBB guide linked above: + + POMONA 5250: + === golden finger and wifi switch ==== + 18 - - 1 + 22 - - NC ---------- audio jacks are on this end + NC - - 21 + 3.3V (PSU) - - 17 - this is pin 1 on the flash chip + === CPU fan === + This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. + +Connecting the BBB and pomona (in this image, an external 3.3v DC PSU +was used):\ +![](images/x60/th_bbb_flashing.jpg) + +Flashrom binaries for ARM (tested on a BBB) are distributed in +libreboot\_util. Alternatively, libreboot also distributes flashrom +source code which can be built. + +SSH'd into the BBB: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w + +yourrom.rom + +It should be `Verifying flash... VERIFIED` at the end. If flashrom +complains about multiple flash chip definitions detected, then choose +one of them following the instructions in the output. + +Reverse the steps to re-assemble your system. + +Copyright © 2014, 2015 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/misc/bbb_ehci.md b/i18n/fr_FR/docs/misc/bbb_ehci.md new file mode 100644 index 00000000..50801a33 --- /dev/null +++ b/i18n/fr_FR/docs/misc/bbb_ehci.md @@ -0,0 +1,360 @@ +--- +title: EHCI debugging on the BeagleBone Black +... + +EHCI debugging +============== + +1. [Find USB port on the target that supports EHCI + debug](#FindUSBportonthetargetthatsupportsEHCIdebug) + +2. [Initial setup of BBB to act as EHCI debug + dongle](#InitialsetupofBBBtoactasEHCIdebugdongle) +3. [Patch BBB's `g_dbgp` module (optional, but highly + recommended)](#PatchBBBsgdbgpmoduleoptionalbuthighlyrecommended) +4. [Configure libreboot with EHCI + debug](#ConfigurelibrebootwithEHCIdebug) + 1. [Selecting `HCD Index` and + `USB Debug port`](#SelectingHCDIndexandUSBDebugport) +5. [How to get the debug logs](#Howtogetthedebuglogs) +6. [Eneble EHCI Debug on the target's kernel (optional, + recommended)](#EnebleEHCIDebugonthetargetskerneloptionalrecommended) +7. [References](#References) + +*NOTE: this documentation may be outdated, and discusses configuring +EHCI debug on the default Debian system that the BBB sometimes comes +with. If you want an easier time, just use [BBB +ScrewDriver](https://www.coreboot.org/BBB_screwdriver) which comes +pre-configured.* + +If your computer does not boot after installing libreboot, it is very +useful to get debug logs from it, from the payload (grub) and/or the +kernel (if gets to there). All of them stream debug logs on the +available serial (RS-232) by default. However, most of todays laptops +lack RS-232 port. The other option is to stream the logs to USB EHCI +debug port. + +This section explains step-by-step how to setup BBB as a “USB EHCI debug +dongle” and configure libreboot and the linux kernel to stream logs to +it (TODO: grub). + +I will refer to three computers: + +- *host* - this is the computer you use, have tools, compiler, + Internet, etc +- *BBB* - Beaglebone Black (rev. B or higher, i use rev. C) +- *target* - the computer you are trying to install liberboot + +### Find USB port on the target that supports EHCI debug {#FindUSBportonthetargetthatsupportsEHCIdebug} + +Not all USB controllers support EHCI debug (see: [EHCI Debug +Port](http://www.coreboot.org/EHCI_Debug_Port#Hardware_capability) ). +Even more, if a USB controller supports EHCI debug, it is available only +*on a single port* that might or might not be exposed externally. + +- You need running OS (GNU+Linux) on your target for this step (If + you've flashed libreboot and it does not boot, you have to flush + back the stock bios) +- You need USB memory stick (the data on it will not be touched). +- The EHCI debugging can not be done through external hub, BBB must be + connected directly to the debug port of the controller (so, no hubs) + + + +- Download^[1](#___fn1)^ + [this](http://www.coreboot.org/pipermail/coreboot/attachments/20080909/ae11c291/attachment.sh) + shell script. + +1. Plug the usb stick in the first available usb port +2. Run the script, you will get output similar to following: +3. The buses the support debug are Bus 3 (0000:00:1a.0) on Port 1 and + Bus 4 (0000:00:1d.0) on port 2. Your usb stick is plugged on Bus 1, + Port 3 +4. Repeat the steps, plugging the USB stick in the next available port +5. Go through all available ports and remember(write down) those for + which bus/port of the usb stick matches one of the bus/port that + support debug (bold). + +Remember (write down) for each port (external plug) you found that +supports debug: *PCI device id, the bus id, the port number, and the +physical location of the usb plug.* + +If you do not find a match, you can not get debug over EHCI. Sorry. + +^1^ The guys from coreboot were talking about including the script in +coreboot distribution (check the status). + +### Initial setup of BBB to act as EHCI debug dongle {#InitialsetupofBBBtoactasEHCIdebugdongle} + +BBB must be powered with a barrel power connector since the mini-B USB +plug will be used for the EHCI debug stream. So you will need: + +- power supply (5V, 2A(10W) is sufficient). +- an extra usb cable: A to mini-B + +(On BBB) The linux kernel includes module (g\_dbgp that enables one of +the usb ports on a computer to behave as EHCI debug dongle. Make sure +you have this module available on your BBB (Debian 7.8 that comes with +BBB should have it), if not, you should compile it yourself (see next +section): + + ls /lib/modules/3.8.13-bone70/kernel/drivers/usb/gadget/g_dbgp.ko + +Unload all other g\_\* modules: + + # lsmod + # rmmod g_multi + ... + +Then load g\_dbgp : + + # modprobe g_dbgp + # lsmod # should show that g_dbgp is loaded, and no other g_* + +Plug the mini-B side of the USB cable in your BBB and the A side in your +target. Then one of the usb devices on your target (with lsusb ) should +be: + + Bus 001 Device 024: ID 0525:c0de Netchip Technology, Inc. + +If you see the device on the target, you are good to continue to the +next step. + +### Patch BBB's g\_dbgp module (optional, but highly recommended) {#PatchBBBsgdbgpmoduleoptionalbuthighlyrecommended} + +For the reasons why you need this, see: [EHCI Gadget +Debug](http://www.coreboot.org/EHCI_Gadget_Debug).\ +Make sure that you have cross compiling environment for +arm-linux-gnueabihf setup on your *host*. + +- On BBB: uname -r - this will give you version number like + 3.8.13-bone70 (I will refer to this as: \$mav.\$miv-\$lv: where + mav=3.8, miv=13, lv=bone70 +- Get the BBB kernel ready on your host for cross-compiling: + + + + $ cd $work_dir + $ git clone https://github.com/beagleboard/kernel.git + $ cd kernel + $ git checkout $mav (see above) + $ ./patch.sh + $ wget http://arago-project.org/git/projects/?p=am33x-cm3.git\;a=blob_plain\;f=bin/am335x-pm-firmware.bin\;hb=HEAD -O kernel/firmware/am335x-pm-firmware.bin + $ cp configs/beaglebone kernel/arch/arm/configs/beaglebone_defconfig + +- Download the patch from + [coreboot.org](http://www.coreboot.org/images/8/88/Ehci-debug-gadget-patches.tar.gz) +- tar -xf Ehci-debug-gadget-patches.tar.gz (will create dir: + usbdebug-gadget) +- Note that there are two patches (patch\_1 and patch\_2) for each of + the two different version of the kernel (3.8 and 3.10). I will use + 3.8. (If using kernel 3.12 patch\_1 is not needed) +- cd kernel (note that this is one more level: you should be in + \$work\_dir/kernel/kernel) +- Apply the patches: + + + + git apply ../usbdebug-gadget/v3.8-debug-gadget/0001-usb-dbgp-gadget-Fix-re-connecting-after-USB-disconne.patch + git apply ../usbdebug-gadget/v3.8-debug-gadget/0002-usb-serial-gadget-no-TTY-hangup-on-USB-disconnect-WI.patch + ; + make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- beaglebone_defconfig -j4@ + +- You should also apply the linux-libre *deblob* script to turn it + into linux-libre (deletes all the blobs from the linux kernel). + [fsfla website](http://www.fsfla.org/ikiwiki/selibre/linux-libre/) - + see + [scripts](http://www.fsfla.org/svn/fsfla/software/linux-libre/scripts/). +- Get your current BBB kernel config (from: /boot/config-) + and copy it to your host as \$work\_dir/kernel/kernel/.config +- Set proper version number: + - On your host, edit \$work\_dir/kernel/kernel/.config (the one + you've just copied from BBB), find the line + CONFIG\_LOCALVERSION="" and change + it to CONFIG\_LOCALVERSION="-\$lv", so it will look something + like: CONFIG\_LOCALVERSION="-bone70" +- Also, make sure that: CONFIG\_USB\_G\_DBGP=m (If not, make + menuconfig, and set @Device Drivers-> USB Support -> USB + Gadget Support -> EHCI Debug Device Gadget=m +- Build the module: + + + + $ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- -j4 (is it possoble to build only the gadget modules) + $ mkdir ../tmp && make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- INSTALL_MOD_PATH=../tmp modules_install + +- on BBB, backup /lib/modules/3.8.13-bone70/kernel/drivers/usb/gadget + (i.e. mv /lib/modules/3.8.13-bone70/kernel/drivers/usb/gadget + \$HOME) +- copy the freshly compiled usb/gadget dir to + /lib/modules/3.8.13-bone70/kernel/drivers/usb +- restart BBB +- Remove all g\_\* modules (rmmod g\_<>) +- modprobpe g\_dbgp + +### Configure libreboot with EHCI debug {#ConfigurelibrebootwithEHCIdebug} + +Libreboot(coreboot) should be configured with debug turned on and to +push debug messages to the EHCI debug port.\ +If you've downloaded the binary distribution, you can check if it is +properly configured in the following way: + +- Go to the libreboot dist root directory cd \$libreboot\_bin +- Locate the rom image for your target (I will call it: \$img\_path) +- Running the following command will extract the config in a file + ./my\_config: + + + + ./cbfstool/i686/cbfstool $img_path extract -n config -f ./my_config + +- Make sure that the following params in the config are set as + following: + + + + CONFIG_USBDEBUG=y (Generic Drivers -> USB 2.0 EHCI debug dongle support) + CONFIG_USBDEBUG_IN_ROMSTAGE=y (Generic Drivers -> Enable early (pre-RAM) usbdebug) + CONFIG_USBDEBUG_HCD_INDEX= (Generic Drivers -> Index for EHCI controller to use with usbdebug) + CONFIG_USBDEBUG_DEFAULT_PORT= (Generic Drivers -> Default USB port to use as Debug Port) + +The following three are behind radio button in the menu. Only the first +one^[2](#___fn2)^ should be = y + + USBDEBUG_DONGLE_STD=y (Generic Drivers -> Type of dongle (Net20DC or compatible) -> Net20DC or compatible) + CONFIG_USBDEBUG_DONGLE_BEAGLEBONE=n (Generic Drivers -> Type of dongle (Net20DC or compatible) -> BeagleBone) + CONFIG_USBDEBUG_DONGLE_BEAGLEBONE_BLACK=n (Generic Drivers -> Type of dongle (Net20DC or compatible) -> BeagleBone Black) + +^2^ The g\_dbgp module on BeagleBone Black (Rev. C) reports it self as +Net20DC, the other options are for older BB(B) - ver1. This is +documented +[on John Lewis's blog](https://johnlewis.ie/coreboot-ehci-debug-gadget-demonstration/) +(also tested/verified). + +Then:\ + + CONFIG_CONSOLE_USB=y (Console -> USB dongle console output) + +Also Debugging \---> Output verbose XYZ ) (*FIXME* somebody verify +these): + + CONFIG_DEBUG_CBFS=y (Output verbose CBFS debug messages ) + CONFIG_HAVE_DEBUG_RAM_SETUP=y (??? What/where is this) + CONFIG_DEBUG_RAM_SETUP=y (Output verbose RAM init debug messages) + CONFIG_DEBUG_SMI=y (Output verbose SMI debug messages) + CONFIG_DEBUG_ACPI=y (Output verbose ACPI debug messages ) + CONFIG_DEBUG_USBDEBUG=y (Output verbose USB 2.0 EHCI debug dongle messages) + +If some of the above mentioned configuration options are not as +specified, you have to configure and compile libreboot yourself. Please +refer to the doc(*FIXME: link* about compiling libreboot. + +#### Selecting HCD Index and USB Debug port {#SelectingHCDIndexandUSBDebugport} + +This applies (and works) only if the USB controller that supports debug +(found in the first section) is from Intel.\ +If the PCI ID of the port you found in the first section is 0000:00:1a.0 +or 0000:00:1d.0 , you are ok. Otherwise you have to try without +guarantee that will work. + +If the externally exposed port is on a bus with PCI ID == 0000:00:1a.0 +then for CONFIG\_USBDEBUG\_HCD\_INDEX choose 2, otherwise choose 0 . + +For CONFIG\_USBDEBUG\_DEFAULT\_PORT choose the port from the first +section that correspond to the PCI ID + +Notes:\ +The above is based on the implementation of +coreboot/src/southbridge/intel/common/usb\_debug.c : +pci\_ehci\_dbg\_dev() .\ +This is enough as it applies for the supported GM45/G45 Thinkpads. +coreboot support some other contollers too, but they are irellevent for +libreboot (for now). + +- On T500 (with switchable GPU) the debug ports for both intel + controllers is exposed. +- On x200t the debug ports for both intel controllers is exposed. + +### How to get the debug logs {#Howtogetthedebuglogs} + +- Plug the USB cable in the target's debug port (the one you found in + step 1) and BBB's mini-B USB +- Make sure no other then g\_dbgp of the g\_\* modules is loaded on + your BBB +- On the BBB: + + + + stty -icrnl -inlcr -F /dev/ttyGS0 + cat /dev/ttyGS0 + +- Power on the target with libreboot +- You should see debug logs comming on your BBB console + +Note that this is not permanent on BBB, if you reboot it, you have to +rmmod g\_\* and modprobe g\_dbgp + +### Eneble EHCI Debug on the target's kernel (optional, recommended) {#EnebleEHCIDebugonthetargetskerneloptionalrecommended} + +You have to know how to compile kernel for your target. + +1. Check if early debugging is already enabled: grep + CONFIG\_EARLY\_PRINTK\_DBGP /boot/config- +2. If enabled, you do not have to compile the kernel (skip this step). + Otherwise, prepare kernel source for your distribution and select + (Kernel hacking -> Early printk via EHCI debug port). Compile and + install the new kernel. +3. Edit your grub configuration and add following to the kenel + parameters^[20](#___fn20)[21](#___fn21)^: earlyprintk=dbgp,keep. + Also, try: earlyprintk=dbgp,keep where N is the debug port + id if the first does not work. + +### References {#References} + +^10^ [EHCI Debug Port](http://www.coreboot.org/EHCI_Debug_Port) + +^11^ [coreboot EHCI debug gadget +demonstration](https://johnlewis.ie/coreboot-ehci-debug-gadget-demonstration/) + +^12^ [EHCI Gadget Debug](http://www.coreboot.org/EHCI_Gadget_Debug) + +^13^ +[Ehci-debug-gadget-patches.tar.gz](http://www.coreboot.org/images/8/88/Ehci-debug-gadget-patches.tar.gz) + +^14^ [Compiling the BeagleBone Black +Kernel](http://wiki.beyondlogic.org/index.php/BeagleBoneBlack_Building_Kernel) + +^15^ +http://dumb-looks-free.blogspot.ca/2014/06/beaglebone-black-bbb-compile-kernel.html + +^16^ +http://dumb-looks-free.blogspot.fr/2014/06/beaglebone-black-bbb-kernal-headers.html + +^17^ [Building BBB Kernel](http://elinux.org/Building_BBB_Kernel) + +^18^ +http://komposter.com.ua/documents/USB-2.0-Debug-Port%28John-Keys%29.pdf + +^19^ [Exploring USB at the Hardware/Software +Interface](http://cs.usfca.edu/~cruse/cs698s10/) + +^20^ https://www.kernel.org/doc/Documentation/x86/earlyprintk.txt + +^21^ https://wiki.ubuntu.com/Kernel/Debugging/USBearlyprintk + +*TODO*: + +1. grub does not send messages to EHCI debug. Investigate. +2. The section “Configure libreboot with EHCI debug” can be + skipped/simplified if a common configuration works for all relevant + targets is selected as defualt +3. Patch and compule g\_dbgp on BBB instead cross-compile +4. Find a simple way to send debug messages from targets userland + +Copyright © 2015 Alex David \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/misc/codenames.md b/i18n/fr_FR/docs/misc/codenames.md new file mode 100644 index 00000000..482d3c64 --- /dev/null +++ b/i18n/fr_FR/docs/misc/codenames.md @@ -0,0 +1,116 @@ +--- +title: Product Codenames +... + +Introduction +============ + +This document lists product codenames for some hardware. +Please note that just because a certain device is listed here does NOT mean +that it is supported in Libreboot. For supported devices refer to the +installation documentation. + +### A note on GPUs + +Some laptops come with and without a discrete GPU (dGPU). Whether the +motherboard includes one or not can be determined by (in descending order +of reliability): + +- often thorough disassembly and searching for the actual chip +- looking at white PCB markings near RAM slots / under keyboard + and comparing with some known codenames (if not available FRU ID sticker) + listed below. +- sometimes by looking at heatsink grills: on + discrete GPU laptops these will look orange and on intergrated ones + they will appear silver. + +List of models and codenames +============================ + +### Codenames + +- Asus Chromebook C201PA: speedy\_rk3288, veyron-speedy + +- ThinkPad X60: KS Note +- ThinkPad X60s (slim): KS Note-2 / KS-2 +- ThinkPad X60 Tablet: Dali (Same PCB as KS Note-2, different EC firmware) + +- ThinkPad X200: Mocha-1 +- ThinkPad X200s (slim): Pecan-1 +- ThinkPad X200 Tablet: Caramel-1 + +- ThinkPad R400/T400: Malibu-3 + - with discrete GPU (dGPU), at board revision 0: "MLB3D-0 + - with only integrated GPU (iGPU), at board revision 0: "MLB3I-0" + +- ThinkPad T500/W500: Coronado-5 + - with dGPU (radeon): "COR5D-0" (last number is the board revision) + - with only iGPU: "COR5I-0" + +- ThinkPad T400s (slim): Shinai-MV +- ThinkPad R500: Waikiki-3 + +- T6x (whole family): Davinci. They don't have codename label in +silkscreen so you need to use FRU label of the board, which is placed +under RAM sticks. +- T60: + - with dGPU (radeon): Magi-0 (last number is the board revision) + - with iGPU: Lisa-0 + +- R60(e): RP-1, RP-2 - Rockwell / Picasso + +- With ThinkPads on Intel platforms newer than Montevina (Except T410), + the codenames become more consistent. All boards have the following + appended based on the type of graphics they have: + - with dGPU: SWG (SWitchable Graphics) + - with only iGPU: UMA (Unified Memory Access) + +*Note that Intel platforms newer than Montevina are not supported by libreboot +yet!. Currently only Calistoga and Montevina platforms are supported. + +- These are the known model codenames: + - ThinkPad T410: NOZOMI-1 # EXT/INT + - ThinkPad T410s: SHINAI-2 # SWG/UMA + - ThinkPad T420: NOZOMI-3 # SWG/UMA + - ThinkPad T420s: SHINAI-3 # SWG/UMA + - ThinkPad T430: NOZOMI-4 # SWG/UMA + - ThinkPad T430s: SHINAI-4 # SWG/UMA + - ThinkPad T520: KENDO-1 + - ThinkPad W520: KENDO-1 WS + - ThinkPad T520: KENDO-3 + - ThinkPad W520: KENDO-3 WS + - ThinkPad T530: KENDO-4 + - ThinkPad W530: KENDO-4 WS + + +### Miscellaneous +- [Calistoga](https://ark.intel.com/products/codename/5950/Calistoga): +945GM/945PM chipset family name +- Napa: calistoga based platform +- [Cantiga](https://ark.intel.com/products/codename/26552/Cantiga): +GM45/GS45/PM45 chipset family name. + This is the chipset used in T400,X200 and similar. +- Montevina: cantiga based platform. +- PMH: the Power Management Hub is a gate array for managing the power + up/down sequence. It is additionally tasked with extending EC's I/O. + Its later version was called "Thinker-1", and eventually it was merged + with PMIC (Rinkan) as ThinkEngine (Do not confuse it with EC chip which is also + has ThinkEngine logo on ThinkPad boards) +- Kozak, Tsurumai, Rinkan: These are successive versions of power management + ICs for Notebook PCs. Tsurumai chip marking is "TB62501F" and datasheet + of it fully describes its operation. + +See also +======== +- Many more Intel codenames can be found at + [Wikipedia](https://en.wikipedia.org/wiki/List_of_Intel_codenames). +- For ThinkPads see [Documentation/thinkpad/codenames.csv @ Coreboot] +(https://review.coreboot.org/cgit/coreboot.git/tree/Documentation/thinkpad/codenames.csv) + +Copyright © 2018 Fedja Beader + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/misc/index.md b/i18n/fr_FR/docs/misc/index.md new file mode 100644 index 00000000..1f4561c6 --- /dev/null +++ b/i18n/fr_FR/docs/misc/index.md @@ -0,0 +1,307 @@ +--- +title: Miscellaneous +x-toc-enable: true +... + +High Pitched Whining Noise on Idle in Debian or Devuan +====================================================================== + +Start powertop automatically at boot time. + +Included with libreboot is a script called 'powertop.debian'. Run this +as root and it will setup powertop to run with --auto-tune at boot +time. Load the file in your text editor to see how it does that. + + $ sudo ./resources/scripts/misc/powertop.debian + +Might want to run with --calibrate first + +If powertop doesn't work, another way (reduces battery life slightly) +is to add *processor.max\_cstate=2* to the *linux* line in grub.cfg, +using [this guide](../gnulinux/grub_cbfs.md). + +High Pitched Whining Noise on Idle in Parabola +============================================================== + +The following removes most of the noise. It reduces what is a high +frequency whine (that not everyone can hear) to a slight buzz (which +most people can't hear or doesn't bother most people). + +This is not perfect! The full solution is still not discovered but this +is a step towards that. Also, in some instances you will need to run +'sudo powertop --auto-tune' again. This needs to be implemented +properly in coreboot itself! + +On the X60 with coreboot or libreboot, there is a high pitched sound +when idle. So far we have use processor.max\_cstate=2 or idle=halt in +GRUB. These consume power. Stop using them! + +Be root + + $ su - + +Installed powertop: + + # pacman -S powertop + +and added the following to /etc/systemd/system/powertop.service : + + [Unit] + Description=Powertop tunings + + [Service] + Type=oneshot + RemainAfterExit=no + ExecStart=/usr/bin/powertop --auto-tune + # "powertop --auto-tune" still needs a terminal for some reason. Possibly a bug? + Environment="TERM=xterm" + + [Install] + WantedBy=multi-user.target + +Finally, as root do that: + + # systemctl enable powertop + # systemctl start powertop + +The next time you boot the system, the buzz will be gone. + +Might want to run with --calibrate first + +If powertop doesn't work, another way (reduces battery life slightly) +is to add *processor.max\_cstate=2* to the *linux* line in grub.cfg, +using [this guide](../gnulinux/grub_cbfs.md). + +X60/T60: Serial port - how to use (for dock owners) + +[Note: using a grsec enabled kernel will disable the powertop function. ](https://en.wikibooks.org/wiki/Grsecurity/Appendix/Grsecurity_and_PaX_Configuration_Options) +=================================================== + +For the Thinkpad X60 you can use the "UltraBase X6" dock (for the +X60 Tablet it is called X6 Tablet UltraBase). For the ThinkPad T60, you +can use the "Advanced Mini Dock". + +If you are using one of the ROM images with 'serial' in the name, then +you have serial port enabled in libreboot and you have memtest86+ +included inside the ROM. Connect your null modem cable to the serial +port on the dock and connect the other end to a 2nd system using your +USB Serial adapter. + +On the 2nd system, you can try this (using GNU Screen): + + $ sudo screen /dev/ttyUSB0 115200 + +How to quit GNU Screen: Ctrl+A then release and press K, and then press +Y. + +There are also others like Minicom but I like GNU Screen + +By doing this before booting the X60/T60, you will see console output +from libreboot. You will also see GRUB displaying on the serial output, +and you will be able to see MemTest86+ on the serial output aswell. You +can also configure your distro so that a terminal (TTY) is accessible +from the serial console. + +The following guide is for Ubuntu, but it should work in Debian and +Devuan, to enable a serial console using GeTTY:\ + (we DO NOT +recommend Ubuntu, because it contains non-free software in the default +repos. Use Debian or Devuan) + +Note: part of the tutorial above requires changing your grub.cfg. Just +change the `linux` line to add instructions for enabling getty. See +[../gnulinux/grub\_cbfs.md](../gnulinux/grub_cbfs.md). + +Finetune backlight control on intel gpu's +========================================= + +Sometimes the backlight control value (BLC\_PWM\_CTL) set by libreboot +is not ideal. The result is either flicker, which could cause nausea or +epilepsy or an uneven backlight and/or coil whine coming from the +display. To fix this a different value for the gpu reg BLC\_PWM\_CTL +needs to be set. See p94 of + +for more information on this reg. The tool for setting registry values +on intel gpu's is included in intel-gpu-tools. Install intel-gpu-tools: + + sudo apt-get install intel-gpu-tools + +You can set values: + + sudo intel_reg write 0x00061254 your_value_in_C_hex_format + +NOTE: on older versions of this utility, use `intel_reg_write` instead. + +The value set has the following structure: bits \[31:16\] is PWM +divider. PWM / PWM\_divider = frequency bits \[15:0\] is the duty cycle +and determines the portion of the backlight modulation frequency. A +value of 0 will mean that the display is off. A value equal to the +backlight modulation frequency means full on. The value should not be +larger than the backlight modulation frequency. + +On displays with a CCFL backlight start from: 0x60016001 To verify if +all modes work as desired use: `xbacklight -set 10` and gradually +increase until 100. Displays with an LED backlight need a lower +backlight modulation. Do the same thing but start from 0x01290129 . Try +setting different values until you have found a value which presents no +issue. + +It is important to know that there are four failure modes: + +1. flickering very fast, which could cause epilepsy (frequency is too + low. decrease divider) +2. randomly flickering in random intervals - driver IC cannot keep up + with toggling the mosfet (frequency too fast, increase divider) +3. frequency is in audible range and causes coils to whine (frequency + is too high. increase divider) +4. backlight is uneven. (CCFL specific, frequency is too high. increase + divider) + +To check for flickering try moving your laptop while looking at it. + +A higher frequency equals higher power consumption. You want to find the +highest good working value. + +Next this value should be set at boot: either add + + intel_reg write 0x00061254 <your_ideal_value> + +NOTE: on older versions of this utility, use `intel_reg_write` instead. + +before exit 0 in /etc/rc.local or create a systemd service file +/etc/systemd/system/backlight.service: + [Unit] + Description=Set BLC_PWM_CTL to a good value + [Service] + Type=oneshot + RemainAfterExit=no + ExecStart=/usr/bin/intel_reg write 0x00061254 <your_value> + [Install] + WantedBy=multi-user.target + + +Now start and enable it: + + sudo systemctl start backlight && sudo systemctl enable backlight + +Special note on i945: + +i945 behaves differently. Bit 16 needs to be 1 and the duty cycle is not +updated when backlight is changed. There are no available datasheets on +this target so why it behaves in such a way is not known. So to find a +working value BLC\_PWM\_CTL set bit 16 to 1 and make sure PWM divider == +duty cycle. see on bit 16. The +cause of this issue is that i945, in contrast with to GM45, is set to +work in BLM Legacy Mode. This makes backlight more complicated since the +duty cycle is derived from 3 instead of 2 registers using the following +formula: if(BPC\[7:0\] <> xFF) then BPCR\[15:0\] \* BPC\[7:0\] +Else BPCR\[15:0\] BPC is LBB - PCI Backlight Control Register, described +on on page 315. BPCR +is BLC\_PWM\_CTL described in + +on page 94. More research needs to be done on this target so proceed +with care. + +Power Management Beeps on Thinkpads +=================================== + +When disconnecting or connecting the charger, a beep occurs. When the +battery goes to a critically low charge level, a beep occurs. Nvramtool +is included in libreboot, and can be used to enable or disable this +behaviour. + +You need to write changes in a libreboot rom image, and flash it, in order +to apply them. You can either use a pre-compiled rom image, or create an image +from the current one in your computer. See here + for +more information on how to do that. + +Once you have a libreboot rom image, say 'libreboot.rom', you can write +changes on the image with the following commands. + +Disable or enable beeps when removing/adding the charger: + + $ sudo ./nvramtool -C libreboot.rom -w power_management_beeps=Enable + $ sudo ./nvramtool -C libreboot.rom -w power_management_beeps=Disable + +Disable or enable beeps when battery is low: + + $ sudo ./nvramtool -C libreboot.rom -w low_battery_beep=Enable + $ sudo ./nvramtool -C libreboot.rom -w low_battery_beep=Disable + +You can check that the parameters are set in the image with : + + $ sudo ./nvramtool -C libreboot.rom -a + +Finally, you need to flash the rom with this new image. See here + +for a detailed explanation. + +Get EDID: Find out the name (model) of your LCD panel +===================================================== + +Get the panel name: + + sudo get-edid | strings + +Or look in `/sys/class/drm/card0-LVDS-1/edid` + +Alternatively you can use i2cdump. In Debian and Devuan, this is in the +package i2c-tools. + + $ sudo modprobe i2c-dev + $ sudo i2cdump -y 5 0x50 (you might have to change the value for + +-y) + + $ sudo rmmod i2c-dev + +You'll see the panel name in the output (from the EDID dump). + +If neither of these options work (or they are unavailable), physically +removing the LCD panel is an option. Usually, there will be information +printed on the back. + +e1000e driver trouble shooting (Intel NICs) +=========================================== + +Example error, ¿may happen on weird and complex routing schemes(citation +needed for cause): + + e1000e 0000:00:19.0 enp0s25: Detected Hardware Unit Hang + +Possible workaround, tested by Nazara: Disable C-STATES. + +*NOTE: this also disables power management, because disabling C-States +means that your CPU will now be running at full capacity (and therefore +using more power) non-stop, which will drain battery life if this is a +laptop. If power usage is a concern, then you should not use this. +(we're also not sure whether this workaround is appropriate)* + +To disable c-states, do this in GNU+Linux: + + for i in /sys/devices/system/cpu/cpu/cpuidle/state/disable; + do + echo 1 > $i; + done + +You can reproduce this issue more easily by sending lots of traffic +across subnets on the same interface (NIC). + +More information, including logs, can be found on [this +page](https://notabug.org/libreboot/libreboot/issues/23). + +USB keyboard wakeup on GM45 laptops +=================================== + +Look at resources/scripts/helpers/misc/libreboot\_usb\_bugfix + +Put this script in /etc/init.d/ on debian-based systems. + +Copyright © 2014, 2015, 2016 Leah Rowe \ + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/i18n/fr_FR/docs/release.md b/i18n/fr_FR/docs/release.md new file mode 100644 index 00000000..8a50ceb3 --- /dev/null +++ b/i18n/fr_FR/docs/release.md @@ -0,0 +1,1101 @@ +--- +title: Listes de changements par version stable. +x-toc-enable: true +... + +Les versions mises à jour de libreboot peuvent être trouvée sur [libreboot.org](/). +Les annoncements de publication de nouvelles versions de Libreboot peuvent être trouvée dans la [section des actualités](../news/) sur le site web. + +Libreboot 20160907 {#release20160907} +================== + +Date de publication : 7 Septembre 2016 + +Pour les cartes mères existantes, il n'y pas de nouveaux changements spécifiques. + +Cette version ajoute une nouvelle carte mère à libreboot: + +- Carte mère de bureau Intel D945GCLF (merci à Arthur Heymans) + +Autres correction de bogue : + +- Nombreuses améliorations de la documentation +- Réajout de "unset superusers" au grub.cfg, qui était nécessaire pour quelques utilisateurs en fonction de la distribution qu'ils utilisaient. + + +Libreboot 20160902 {#release20160922} +================== + +Date de publication: 2 Septembre 2016. + +Cela corrige des problèmes dans la version précédente 20160818. +Regardez le journal des changements pour des détails. + + +Libreboot 20160818 {#release20160818} +================== + +Date de publication: 18 Août 2016. + +Les instructions d'installation peuvent être trouvée dans `docs/install`. +Les instructions de constructions (pour le code source) peuvent être trouvé dans `docs/git/\#build`. + + +Machines supportées dans cette version: +----------------------------------- + +- **ASUS Chromebook C201** + - Regardez les notes dans ***docs/hardware/c201.html*** +- **Gigabyte GA-G41M-ES2L desktop motherboard** + - Regardez les notes dans ***docs/hardware/ga-g41m-es2l.html*** +- **Intel D510MO desktop motherboard** + - Regardez les notes dans ***docs/hardware/d510mo.html*** +- **Intel D945GCLF desktop motherboard** + - Regardez les notes dans ***docs/hardware/d945gclf.html*** +- **Apple iMac 5,2** + - Regardez les notes dans ***docs/hardware/imac52.html*** +- **ASUS KFSN4-DRE server board** + - PCB revision 1.05G is the best version (can use 6-core CPUs) + - Regardez les notes dans ***docs/hardware/kfsn4-dre.html*** +- **ASUS KGPE-D16 server board** + - Regardez les notes dans ***docs/hardware/kgpe-d16.html*** +- **ASUS KCMA-D8 desktop/workstation board** + - Regardez les notes dans ***docs/hardware/kcma-d8.html*** +- **ThinkPad X60/X60s** + - Vous pouvez aussi enlever la carte mère d'un X61/X61s et la remplacer avec une carte mère X60/X60s. Une carte d'une X60 Tablet rentrera aussi dans l'intérieur d'un X60/X60s. + +- **ThinkPad X60 Tablet** (résolution 1024x768 et 1400x1050) avec support pour scanneur + + + - ***docs/hardware/\#supported\_x6Ot\_list*** pour la lste d'écrans LCD supportés. + - C'est inconnu s'il se peut qu'une X61 Tablet ait sa carte mère remplacée par une carté mère d'une X60 Tablet. + + +- **ThinkPad T60** (Intel GPU) (il y a des problèmes; regardez en dessous): + + - Regardez les notes ci-dessous pour les exceptions et + ***docs/hardware/\#supported\_t60\_list*** pour une liste connue d'écrans LCD fonctionnels. + + - C'est inconnu s'il se peut qu'un T61 ait sa carte mère remplacée par une carté mère d'un T60. + - Regardez **docs/future/\#t60\_cpu\_microcode***. + - Le T60p (et ordinateurs portables avec carte graphiques ATI) ne sera surêment jamais supporté : ***docs/hardware/\#t60\_ati\_intel***. + + +- **ThinkPad X200** + - **ME/AMT**: libreboot enlève ceci, permanemment. + ***docs/hardware/gm45\_remove\_me.html*** + +- **ThinkPad R400** + - Regardez **docs/hardware/r400.html** + - **ME/AMT**: libreboot enlève ceci, permanemment. + ***docs/hardware/gm45\_remove\_me.html*** + +- **ThinkPad T400** + - Regardez ***docs/hardware/t400.html*** + - **ME/AMT**: libreboot enlève ceci, permanemment. + ***docs/hardware/gm45\_remove\_me.html*** + +- **ThinkPad T500**: + - Regardez ***docs/hardware/t500.html*** + - **ME/AMT**: libreboot enlève ceci, permanemment. + ***docs/hardware/gm45\_remove\_me.html*** + +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - Regardez ***docs/hardware/\#macbook11***. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - Regardez ***docs/hardware/\#macbook21***. + + +Changements pour cette version, relatif à r20150518 (les changements les plus récents en dernier, les changements récents en premier) +--------------------------------------------------------------------------------------------- + +Libreboot 20160818 + +- NOUVELLES CARTES MÈRES AJOUTÉES: + - ASUS Chromebook C201 (ordi portable ARM) (grâce à Paul Kocialkowski) + - Gigabyte GA-G41M-ES2L carte mère (bureau) (grâce à Damien Zammit) + - Intel D510MO carte mère (bureau) (grâce à Damien Zammit) + - ASUS KCMA-D8 carte mère (bureau) (grâce à Timothy Pearson) + - ASUS KFSN4-DRE carte mère (serveur) (grâce à Timothy Pearson) + - ASUS KGPE-D16 carte mère (serveur) (grâce à Timothy Pearson) + + +Pour les cartes précedemment supportées, de nombreuses corrections venant d'amont ont été fusionnées. + +Autre changements (par rapport à la version libreboot 20150518): +(ceci est un résumé. Pour une liste plus détaillée des changements, veuillez vous référer au git log). + +256Mo VRAM alloué sur la GM45 (X200, T400, T500, R400) au lieu de 32Mo. +C'est une amélioration par rapport au BIOS Lenovo et Libreboot 20150518, permettant le décodage vidéo à 1080p d'être plus fluide. (merci Arthur Heymans). Pour clarifier, la performance vidéo GM45 dans libreboot 20160818 est meilleure que le BIOS originel et la précédente version. + +64Mo VRAM sur i945 (X60, T60, MacBook2,1) maintenant supporté dans coreboot-libre, et utilisé par défaut (dans les précédentes versions, il y avait 8Mo alloué). Merci à Arthur Heymans. + +Une meilleure durée de vie de la batterie sur la GM45 (X200, T400, T500, R400) dû au niveau plus haut de cstates maitenant supportés.(merci Arthur Heymans). États de puissances C4 maintenant supportés. + +Le mode texte de la GM45 (X200, T400, T500, R400) marche maitenant, permettant d'utiliser MemText86+ comfortablement. (grâce à Nick High de coreboot) + +Les affichages LVDS à double canaux sur la GM45 (T400, T500) sont maintenant automatiquement détecté coreboot-libre. (merci Vladimir Serbinenko de coreboot) + +Résolution partielle dans coreboot-libre par rapport à l'affichage du GRUB sur la GM45, résolution plus haute pour les écrans LCD pour les affichages LVDS à double canaux (T400, T500). (merci Arthur Heymans) + +Améliorations massive de la configuration du GRUB, rendant plus facile le démarrage automatique +de nombreux systèmes d'exploitations chiffré, et généralement un menu plus utile pour démarrer (les remerciements grâce à Klemens Nanni du projet autoboot). +Libreboot utilise maintenant automatiquement le grub.cfg fourni par la distribution +GNU+Linux installée, si présente, passant sur cette configuration. Celà est fait à travers de multiples partitions où libreboot cherche activement pour un fichier de configuration +(notamment sur les volumes chiffrés et LVM). Celà devrait rendre Libreboot plus facile +à utiliser pour les utilisateurs non techniques, sans avoir à modifier la +configuration GRUB utilisée dans libreboot. + +Les archives des utilitaires sont maitenant en mode source seulement . Vous aurez besoin de compiler les paquets +dedans (scripts de builds sont compris, et un script pour installer les dépendances du build). (les archives de fichiers binaires sont de nouveau prévues dans une nouvelle version où le nouveau système de build sera fusionné). + +SeaGRUB est maintenant le payload par défaut des cartes x86. (SeaBIOS configuré pour immédiatement charger un payload GRUB depuis CBFS sans fournir une interface dans SeaBIOS. De cette façon, GRUB est encore utilisé mais maintenant les services du BIOS sont disponibles, vous obtenez donc le meilleur des deux mondes). Les remerciements reviennent à Timothy Pearson +de coreboot pour cette idée. + +crossgcc est maintenant téléchargé et construit en tant que module séparé de coreboot-libre, +avec une révision universelle utilisée pour build toutes les cartes. + +Les cartes mères spécifiques ont leur propre patchs et modification de coreboot, indépendantes des autres autres. Celà rend la maintenance plus facile. + +Mise à jour de tous les utilitaires et modules (coreboot, GRUB, etc) vers des versions plus récentes, +avec de nombreuses correction de bogues et améliorations en amont. + +Le problème de l'octect "siècle" de l'Horloge Temps Réél (RTC/HTR) est mainteant corrigé sur la GM45 dans coreboot-libre, donc la date devrait maitenant s'afficher +correctement lors de l'utilisation du dernier kernel linux, au lieu de voir 1970-01-01 au démarrage (grâce à Alexander Couzens de coreboot) + +Le système de build utilise maintenant plusieurs coeurs d'un CPU, accélérant le build pour certaine personnes. +La spécification manuelle du nombre de coeurs a utiliser est possible pour ceux qui utilise le système de build dans un environnement chrooté (les remerciements vont à +Timothy Pearson de coreboot). + +Dans le système de build (répo git), https:// est maitenant utilisée lors du clonage de coreboot. +http:// est utilisé en tant qu'alternative pour GRUB si git:// échoue + +Nouveau chargeur d'amorçage, depthcharge (libre et maintenu par Google) +prêt à l'utilisation sur l'ASUS Chromebook C201. (les remerciements vont à Paul Kocialkowski) + + +Nombreuses corrections à l'utilitaire ich9gen (p.e maintenant la densité du composant flash est correctement mise dans la description, les descriptions gbe-less sont maintenant supportées.) + + +Version 20150518 {#release20150518} +================ + +Date de publication : 18 May 2015. + +Instructions d'installation peuvent être trouvé à ***docs/install/*** +Instructions de constructions (pour le code source) peuvent être trouvée dans ***docs/git/\#build***. + + +Machines supportés dans cette version: +----------------------------------- + +- **ThinkPad X60/X60s** + - Vous pouvez aussi enlever la carte mère d'un X61/X61s et la remplacer avec une carte mère d'un X60/X60s. Une carte mère d'une X60 Tablet rentrera aussi à l'intérieur d'une X60/X60s +- **ThinkPad X60 Tablet** (1024x768 et 1400x1050) avec support pour scanneur + - Regardez ***docs/hardware/\#supported\_x60t\_list*** pour une liste des écrans LCD supportés + - C'est inconnu s'il se peut qu'un X61 Tablet peut avoir sa carte mère remplacée par une carte mère d'une X60 Tablet. +- **ThinkPad T60** (Carte graphique Intel) (il y a des problèmes; regardez ci-dessous): + - Regardez les notes ci-dessous pour des exceptions, et ***docs/hardware/\#supported\_t60\_list*** pour les écrans LCDs connus pour marcher. + - C'est inconnu s'il se peut qu'un T61 peut avoir sa carte mère remplacée par une carte mère d'un T60. + - Regardez ***docs/future/\#t60\_ati\_intel*** +- **ThinkPad X200** + - X200S et X200 Tablet sont aussi supportés, conditionnellement; regardez + ***docs/hardware/x200.html\#x200s*** + - **ME/AMT**: libreboot enlève ceci, définitevement. + ***docs/hardware/gm45\_remove\_me.html*** +- **ThinkPad R400** + - Regardez ***docs/hardware/r400.html*** + - **ME/AMT**: libreboot enlève ceci, définitevement. + ***docs/hardware/gm45\_remove\_me.html*** +- **ThinkPad T400** + - Regardez ***docs/hardware/t400.html*** + - **ME/AMT**: libreboot enlève ceci, définitevement. + ***docs/hardware/gm45\_remove\_me.html*** +- **ThinkPad T500** + - Regardez ***docs/hardware/t500.html*** + - **ME/AMT**: libreboot enlève ceci, définitevement. + ***docs/hardware/gm45\_remove\_me.html*** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - Regardez ***docs/hardware/\#macbook11***. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, + MB063LL/A, MB062LL/A) + - Regardez ***docs/hardware/\#macbook21***. + +Changements pour cette version, relatif à r20150518 (les changements les plus récents en dernier, les changements récents en premier) +--------------------------------------------------------------------------------------------- + +- Ajoute une donnée de liste blanche dans board\_enable.c dans la flashrom, pour le ThinkPad R400, T400 et T500 +- Flashrom mis à jour (à la révision SVN 1889) + - Patch de la liste blanche pour le X200 enlevé (fusionné depuis l'amont) + - Liste blanche X200 modifiée pour inclure le X200S et le X200 Tablet +- libreboot\_util: n'inclut pas les fichiers d'agencement du cmos (ne sont plus nécessaires) +- **coreboot_libre: Patchs rétroactifs pour le support du scanneur pour les X200 Tablet** +- build/release/archives: créé un fichier manifeste de somme SHA512 des archives de version. +- build/release/archives: séparation de crossgcc dans une nouvelle archive +- désactivé la génération d'images ROM txtmode pour maintenant ( elles seront de retour de nouveau encore dans une prochaine version) +- coreboot-libre: supprimer le code inutilisé (réduit la taille de l'archive src) +- Guides de flashage: rendus plus amicaux pour les personnes daltonienne. +- docs/gnulinux/encrypted\_\*.html: suppression de la mention de la longueur du mot de passe - c'était arbitraire et sans intérêt. +- docs/maintain/: Finir le guide +- scripts/download/coreboot: utilise les diffs incluses dans libreboot, pas quelques bon bouts du gerrit extérieur - review.coreboot.org (gerrit) étant hors service ne tue plus libreboot (des mirroirs de sauvegardes du répertoire maître existent). +- docs/install/bbb\_setup.html: ajout d'infos à propos de wp/hold et pinouts +- docs/: améliore la description de libreboot +- docs/hardware/gm45\_remove\_me.html: notes à propos de l'utilitaire demefactory. +- docs/install/bbb\_setup.html: débug EHCI : recommander linux-libre. +- docs/install/bbb\_setup.html: Guide de mise en place des fichiers journaux de débug de l'EHCI. +- docs/hardware/t500.html: ajout du rapport de compatibilité des écrans (ÀFAIRE: corriger les écrans incompatibles) +- Met à jour coreboot(encore) + fusionne les patchs de carte graphiques hybride GM45 - celà signifie que la mise en place d'un T400/T500 avec GPU hybride ATI+Intel marchera (ATI désactivé, Intel activé définitivement). L'option power\_on\_after\_fail de la nvram ajoutée à toutes les cartes mères GM45, par défaut sur Non, comme ça la brancher sur secteur ne démarre pas le système contre la volonté de l'utilisateur. Net20DC est maintenant le boîtier de déboguage par défaut sur toutes les cartes mères (compatibles avec BBB). +- demefactory (nouvel utilitaire): créée la factory.rom sans la ME +- ich9deblob: re-façonnage des fonctions de descriptor.c +- docs/hardware/t500.html: ajout des journaux matériels +- docs/gnulinux/encrypted\_\*.html: pas de mot de passe pour la saisie par défaut +- docs/git/: Ajout de plus détails à propos de BUC.TS +- grub.cfg: Scanne aussi pour grub2/grub.cfg, pas juste grub/grub.cfg +- docs/maintain/ (nouvelle section. Travail en cours !): Faire la maintenance de libreboot +- docs/gnulinux/grub\_boot\_installer.html: Correction d'une instruction hasardeuse +- docs/tasks.html: meilleure catégorisation entre intel/amd/arm +- docs/install/bbb\_setup.html: notes à propos de la stabilité de l'utilitaire de flashage SPI. +- docs/install/bbb\_setup.html: plus de noms pour les cables de 0.1 pouce. +- docs/install/\*\_external.html: ajout d'un avis de non responsabilité à propos de la pâte thermique. +- docs/install/bbb\_setup.html: Correction des liens cassés +- docs/install/bbb\_setup.html: notes préliminaires à propos du déboguage EHCI. +- docs/hardware/gm45\_remove\_me.html: lien vers les sites webs parlant de la ME. +- docs/install/{t400,t500,r400}\_external.html: notes à propos de la compatibilité des processeurs (CPU). +- Supprime le script ich9macchange. Il est inutile et embrouille les gens. +- docs/hardware/gm45\_remove\_me.html: prioritisation du chemin d'éxecutable d'ich9gen. +- docs/hardware/gm45\_remove\_me.html: prioritisation du changement d'adresse MAC. +- docs/hardware/gm45\_remove\_me.html: notes moins embrouillantes à propos d'ich9gen +- build/dependencies/parabola: Ajout de dépendances pour l'architecture x86_64. +- scripts/dependencies/paraboladependencies: dépendances de constructions (pour 32-bit Parabola). +- **Nouvelle carte mère**: ThinkPad T500 +- Ajout des diffs pour les différences de descripteurs/gbe entre le T500 et X200 +- coreboot-libre: fournit une meilleure catégorisation des blobs. +- docs/hardware/gm45\_remove\_me.html: ajout de notes à propos de la protection d'écriture flash. +- **Nouvelle carte mère**: ThinkPad T400 +- GRUB: ajout d'un support partial de vesamenu.c32 (corrige la fin du menu ISOLINUX) +- Mise à jour du GRUB (à la révision fa07d919d1ff868b18d8a42276d094b63a58e299). +- Mise à jour de coreboot (à la révsion 83b05eb0a85d7b7ac0837cece67afabbdb46ea65) + - Le microcode du CPU Intel (la majorité de) n'est plus supprimé désormais, parce que c'était supprimé en amont (bougé dans un répertoire tierce partie). + - Le patch du cstate pour Macbook2,1 n'est plus choisi sur le volet (fusionné de l'amont). + - Le patch pour désactiver l'utilisation de l'horodatage dans coreboot n'est plus inclus (fusionné de l'amont) +- coreboot-libre: ne pas lister le micrologiciel kbd vortex86ex en tant que microcode +- coreboot-libre: ajout de la license GPLv3 aux scripts findblobs. +- coreboot-libreboot: ne supprime pas raminit\_tables (nahelem/sandybridge) (ils ne sont pas des blobs) +- coreboot-libre: ne supprime pas les fichiers .spd.hex (ils ne sont pas des blobs). +- build/release/archives: ne met pas rmodtool dans libreboot\_util +- docs/install/x200\_external.html: recommande l'installation de GNU+Linux à la fin. +- docs/install/x200\_external.html: ajoute plus de photos, améliore les instructions +- build/clean/grub: utilise distclean au lieu de clean +- grub-assemble: Ajoute les modules *bsd* et *part\_bsd* +- build/roms/withgrub: n'éxecute seulement ich9gen si les images de gm45/gs45 existe +- docs/git/: ajout de notes à propos de la compilation pour certaines cartes mères spécifiques. +- build/roms/withgrub: permet la compilation pour une portée customisée de cartes mères. +- grub-assemble: désactive la sortie verbeuse. +- Ajoute de la documentation sur comment déverouiller le système de fichiers chiffré avec clé dans initramfs dans Parabola Linux +- docs/gnulinux/grub\_cbfs.html: amélioration de la structure (plus facile à utiliser) +- grub.cfg: Désactive le beep au démarrage. +- docs/install/bbb\_setup.html: rend le guide plus facile à utiliser +- docs/gnulinux/grub\_cbfs: supprime les instructions redondantes +- docs/install/x200\_external.html: met des punaises dans les images. +- docs/install/bbb\_setup.html: remplace la photo du bloc d'alimentation 3.3V avec un bloc d'alimentation ATX +- docs/hardware/x200.html: ajout de décharges du X200 4Mo avec BIOS Lenovo v3.22 +- docs/hardware/x200.html: ajout de décharges du X200 4Mo avec BIOS Lenovo v3.18 +- grub.cfg: ajout d'une entrée de menu syslinux\_configfile pour ahci0 +- grub.cfg: ajout de plus de chemins pour syslinux\_configfile +- docs/future.html: T60: ajout d'une décharge EDID du LG-Philips LP150E05-AK21 +- docs/install/bbb\_setup.html: clarifie encore plus quel clip est nécessaire +- scripts bash: rend la sortie du script plus amicale pour l'utilisateur en général. +- scripts bash: active seulement la sortie verbeuse si DEBUG= est utilisé. +- build: Supporte de nombreuses options extras - maintenant possible de compiler de multiples images pour les cartes mères +de votre choix (configs), mais sans construire l'entière collection. +- A supprimé la clé de signement de l'archive - au lieu de cela l'empreinte et l'ID sont donnés, comme ça l'utilisateur peut le télécharger depuis un serveur de clé. +- scripts/helpers/build/release: déplace les documentations pour séparer l'archive - réduit la taille des autres archives considérablement. +- déplace le fichier DEBLOB dans resources/utilities/coreboot-libre/deblob +- scripts/helpers/build/release: supprime DEBLOB de libreboot\_src/ - pas nécessaire dans libreboot\_src (archive de version) parce qu'il contient une révision de coreboot qui a déjà été déblobbé. +- flash (script): Utilise *build* au lieu de *DEBLOB* pour savoir si on est dans src +- docs/install/r400\_external.html: Montre les images, ne pas mettre de liens. +- docs/install/x200\_external.html: Montre les images, ne pas mettre de liens. +- docs/install/bbb\_setup.html: Montre les images, au lieu de mettre des liens +- Documentation: optimise toutes les images (réduit la taille des fichiers) +- Enlève les liens de téléchargements sur la page de publication de version ( et de la page d'archive) - les archives de versions sont hébergés différement à la suite de cette version,ce qui signifie que les vieilles méthodes ne sont plus viables. +- A déplacé ich9macchange dans resources/scripts/misc/ich9macchange +- ich9macchange: on assume qu'il est éxecuté depuis \_util (agit seulement sur une seule image ROM, définie par un chemin fournit par l'utilisateur). +- Déplace grub-background dans resources/scripts/misc/grub-background +- grub-background: on assume qu'il est éxecuté depuis libreboot\_util +- grub-background: change seulement une image ROM, spécifié par chemin +- build (archives de version): ajoute le fichier commitid dans release/ +- build-release: déplace les archives de versions dans release/ +- Fusionne tout les scripts de compilation/construction dans un seul script générique, avec les helpers (scripts de fonctions) dans resources/scripts/helpers/build/ +- Remplace *getall* avec *download*, qui prend en entrée un argument spécifiant quel programme l'utilisateur veut télécharger +- A déplacé les scripts de téléchargements dans resources/scripts/helpers/download +- build-release: enlève les entrées powertop +- Documentation: améliorations générales des instructions de flashage. +- Fusionne tous les scripts de flashage dans un seul script.- Mis à jour GRUB +- bucts: le rendre compilable sans git +- A déplacé dejavu-fonts-tff-2.34/AUTHORS dans resources/grub/font/ +- A supprimé GRUB Invaders de libreboot +- A supprimé SeaBIOS de libreboot +- build-release: optimise l'utilisation de tar (taille des fichiers réduites) +- grub.cfg: ajoute un autre chemin pour la configuration SYSLINUX (/syslinux/syslinux.cfg) +- build-release: enlève le répertoire bin/ de libreboot\_util +- cleandeps: enlève le répertoire bin/ +- buildrom-withgrub: créer le répertoire bin si il n'existe pas +- coreboot-libre: n'utilise pas git pour l'horodatage de version +- i945-pwm: ajout d'une commande de nettoyage (clean) dans le Makefile +- i945-pwn: ajout de -lz à la Makefile. +- docs/install/x200\_external: Mentionne le mode non-descripteur de la GPIO33 +- docs/hardware/: enlève les liens redondants +- ich9macchange: ajout de R400 +- build-release: sépare les images de ROM dans des archives individuelle +- build-release: renomme libreboot\_bin en libreboot\_util +- **Nouvelle carte mère**: le support du ThinkPad R400 a été ajouté à libreboot. +- bbb\_setup.html: dis à l'utilisateur d'utiliser la flashrom propre à libreboot. + + +Version 20150124, 20150126 et 20150208 {#release20150124} +======================================= + +Date de publication: 24 Janvier 2015. + +Machines supportées dans cette version: +----------------------------------- + +- **Lenovo ThinkPad X60/X60s** + - Vous pouvez aussi enlever la carte mère d'un X61/X61s et le remplacer avec la carte mère d'un X60/X60s. + La carte mère d'un X60 Tablet rentrera aussi à l'intérieur d'un X60/X60s. +- **Lenovo ThinkPad X60 Tablet** (résolution 1024x768 et 1400x1050) avec support pour scanneur + - Voir **hardware/\#supported\_x60t\_list** pour une liste d'écrans LCD supportés + - C'est inconnu si une X61 Tablet peut avoir sa carte mère remplacé par celle d'une X60 Tablet. +- **Lenovo ThinkPad T60** (carte graphique Intel) (il y a des problèmes install/x200\_external.html; regardez ci-dessous): + - Regardez les notes ci-dessous pour des exceptions, et **hardware/\#supported\_t60\_list** pour une liste d'écrans LCD connus pour marcher. + - Il est inconnu si un T61 peut avoir sa carte mère remplaçée avec celle d'un T60. + - Voir **future/\#t60\_cpu\_microcode**. + - Le T60p (et ordinateurs T60 avec carte graphique ATI) ne seront sûrement jamais supportés: **hardware/\#t60\_ati\_intel** +- **Lenovo ThinkPad X200** + - X200S et X200 sont aussi supportés, conditionnellement; voir + **hardware/x200.html\#x200s** + - **ME/AMT**: libreboot enlève ceci, définitivement. + **hardware/gm45\_remove\_me.html** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - Voir **hardware/\#macbook11**. +- **Apple Macbook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, MB063LL/A, MB062LL/A) + - Voir **hardware/\#macbook21**. + +Modifications pour r20150208 (relatif à 20150126) +----------------------------------------------- + +C'est une version de maintenance (de polissage) basé sur r20150126. Les utilisateurs qui ont installé la r20150126 n'ont pas vraiment besoin de mettre à jour à cette version. + +- buildrom-withgrub : utilise le fond d'écran gnulove.jpg sur les ordinateurs portables avec un ratio écran 16:10 (MacBook2,1 et X200) +- build-release: inclut le script grub-background dans libreboot\_bin +- grub-background (nouveau): laisse l'utilisateur choisit le fond d'écran du GRUB. +- grub-assemble: ajout d'un lien à l'utilitaire original. +- buildrom-withgrub: Met background.jpg dans CBFS, non dans le disque mémoire GRUB. +- grub-assemble: fusionne les scripts en un seul script gen.sh +- Documentation: implémente un thème, améliore drastiquement la lisibilité +- docs/hardware/: met à jour une liste des écrans LCD compatibles avec le T60. +- docs/: plus de clarification sur le but établi de libreboot. +- build-release: inclut le fichier commitid dans les archives de version. +- docs/: plus souligner la nécessité de GNU+Linux +- lenovobios\_firstflash: corrige les erreurs BASH +- lenovobios\_secondflash: corrige les erreurs BASH +- docs/install/x200\_external.html: dit à l'utilisateur de changer son adresse MAC. +- docs/git/: ajoute à la liste des hôtes compatibles avec l'architecture x86_64. +- docs/install/: enlève les vieilles informations (obsolètes). +- docs/git/: indiquer que les dépendances de compilation sont pour src (et non nécessaire pour libreboot\_bin) +- build: +- X60, X60S et X60 Tablet partagent maintenant les même images de ROM. +- Ajoute le support de QEMU (q35/ich9) à libreboot +- Ajout le support de QEMU (i440x/piix4) à libreboot +- docs/: réécrit la description de ce qu'est libreboot. +- docs/release.html: ajoute des notes sur comment utiliser GPG. +- build-release: supprime le fichier commitid des archives de versions +- build-release: créé un fichier nommé commitid après build-release + + +Modifications pour r20150126 (relatif à r20150124) +----------------------------------------------- +C'est une version de correction de bogue basé sur r20150124. Elle contient quelques petits changements: +- grub.cfg: code en dur la liste des partitions à chercher (accélère le démarrage considérablement. L'expression régulière du GRUB n'est pas très bien optimisée) +- Docs (x200.html hcl): enlève les informations incorrectes + - Documentation (bbb\_setup.md): Corrige les erreurs d'orthographes +- build-release: supprime les fichiers ich9fdgbe\_{4m,8m}.bin du dossier ich9gen + - Ils ont été inclus accidentellement dans la version r20150124. + Ils sont générés depuis ich9gen donc c'est ok, mais ils n'ont pas besoin d'être dans l'archive. +- Documentation (grub\_cbfs.md): boucle dans libreboot\_grub.cfg (ajoute des notes à propos de cela si l'utilisateur l'a copié depuis grub.cfg dans CBFS). + + +Changements pour cette version (les derniers changements en premier, les plus récents en dernier) +---------------------------------------------------------------------- + +- grub.cfg: a ajouté (ahci1) à la liste des appareils pour l'analyseur syntaxique (CD/DVD) d'ISOLINUX (ceci est nécessaire pour le dock du X200). +- grub.cfg: l'analyse syntaxique d'ISOLINUX est maintenant faite sur toutes les partitions USB. +- grub.cfg: change automatiquement sur /boot/grub/libreboot\_grub.cfg sur une partition, si le fichier existe. +- libreboot\_bin: a ajouté les éxecutables statiques sur architecture ARM pour flashrom, cbfstool, ich9gen et ich9deblob (testé sur beaglebone black). +- Flashrom: a enlevé les définitions redondantes de la puce de flashage (flashchip) (pour les propriétaires d'X200). +- Flashrom: a ajouté une liste blanche pour le ThinkPad X200. +- X200: a corrigé un rétroéclairage inégal (à bas niveaux) +- ich9macchange (nouveau script, utilise ich9gen): pour changer l'adresse MAC par défaut pour les images ROM du X200. +- ich9gen: a ajouté la capacité de changer l'adresse MAC par défaut (et met à jour la somme de contrôle) +- ich9deblob: a ajouté un nouvel utilitaire ich9gen: cela peut générer une image descriptor+gbe sans la présence d'un dump factory.rom. +- A modifié ich9deblob afin d'utiliser une structure pour Gbe, documentant le tout. +- A mis à jour massivement l'utilitaire ich9deblob: a complétement tout retravaillé. +- A activé les cstates 1 et 2 sur macbook21. Cela réduit la chaleur au repos / consommation électrique. +- buildrom-withgrub: a désactivé la création de \*txtmode\*.rom pour le X200 (seulement le tampon d'affichage graphique marche) +- A mis à jour SeaBIOS (encore) +- docs/install/\#flashrom\_x200: améliore les instructions +- A mis à jour flashrom (encore) - a mis à jour les patchs +- A mis à jour GRUB (encore) +- A mis à jour coreboot (encore) +- build-release: pas tout les fichiers étaient copié dans libreboot\_src. corrige cela. +- build-release: inclus cbmem (compilé statiquement) dans libreboot\_bin +- Documentation (X200): a ajouté les instructions pour le flashage basée logiciellement. +- Documentation: a enlevé toutes les références du connecteur pirate (a été remplacé avec des tutoriels de flashages BBB). +- **Nouvelle carte mère:** a ajouté le support du ThinkPad X200S et X200 dans libreboot +- build: trouve automatiquement les noms de cartes mères (configs) afin de compilé pour celles-ci +- **Nouvelle carte mère:** a ajouté le support du ThinkPad X200 dans libreboot +- configuration de coreboot-libre (toutes cartes mères): active la sortie du journal de clé USB (pour BeagleBone Black) +- cleandeps: en fait, nettoyer les grubinvaders +- .gitignore: ajoute le répertoire powertop +- cleandeps: nettoie l'utilitaire i945-pwn +- scripts (tous): corrige les fautes de frappes +- Documentation: nettoyage général. +- builddeps-flashrom: réduit les commandes de compilations dans une seule boucle pour/for. +- scripts (tous): remplace les rm -Rf non nécessaires avec rm -f +- docs/release.html: ajoute lenovo g505s à la liste des candidats +- .gitignore: ajoute libreboot\_bin.tar.xz et libreboot\_src.tar.xz +- libreboot\_bin.tar.xz: inclut les utilitaires en tant que binaires liés statiquement + - Cela veut dire que l'utilisateur n'a plus à installer les dépendances de compilation ou à compiler depuis la source. +- deps-parabola (enlevé) enlève le script des dépendances de Parabola. Rajoutera plus tard (proprement testé) +- grub.cfg: ajoute plus de chemins à vérifier à l'analyseur syntaxique isolinux (plus d'images ISOs devrait marcher maintenant) +- Met à jour SeaBIOS +- x60flashfrom5 (nouveau), pour les utilisateurs de X60 mettant à jour depuis la 5ième/récente version. +- Met à jour flashrom +- Met à jour GRUB +- A mis à jour coreboot-libre + - i945: a établi permanemment tft\_brightness à 0xff (corrige un bogue sur l'X60 où monter la luminosité au max ferait retourner en basse luminosité). +- getcb: révocations des contrôles de rétroéclairage aux origines pour le X60/T60. + - Les patchs de luminosité ACPI ont été abandonnés et rendus obsolètes. +- grub.cfg: charge seulement initrd.img si cela existe. Ajoute rw à la ligne linux (pour ProteanOS). +- build: Génère seulement les configurations GRUB une seule fois (réutilise sur toutes les images) +- Compile seulement 2 charges utiles (payload) GRUB éxecutables, réutilise sur toutes les cartes mères. +- resources/utilities/grub-assemble/gen.txtmode.sh: Utilise GNU BASH\ + resources/utilities/grub-assemnle/gen.vesafb.sh: Utilise GNU BASH +- scripts (traitement des erreurs): remplace exit avec exit 1 (rend le déboguage plus facile) +- Bouge la majorité des fichiers dans CBFS dans le disque mémoire GRUB, sauf grub.cfg et grubtest.cfg +- docs/release.html Ajoute le processeur DM&P vortex86ex à la liste des candidats. +- docs/release.html Ajoute le ThinkPad X201 à la liste des candidats. +- Nouveaux liens ajouté à docs/security/x60\_security et docs/security/t60\_security +- lenovobios\_secondflash: avertit si BUCTS n'est pas présent (ce n'est pas un drame. Pouvez juste enlever la batterie/pièce nvram). +- lenovobios\_firstflash: échoue si BUCTS échoue. (précaution d'anti-bousillage) +- A enlevé des avertissements déplaisants des scripts de flashage, a amélioré la documentation en contrepartie. +- scripts (tous): ajoute une vérification d'erreur propre (échoue rapidement, échoue tôt. Ne continue plus c'il y a des erreurs) +- buildrom-withgrub: renomme les images en boardname\_layout\_romtype.rom +- buildrom-withgrub: ne bouge pas cbfstool, exécute directement +- resources/utilities/grub-assemble: ajoute la disposition de clavier française Dvorak (BEPO). +- Documentation: ajoute docs/hardware/x60\_keyboard.html (montre comment remplacer le clavier sur X60/X60T) +- Documentation: nettoyage majeur (meilleure structure, plus facile pour trouver des choses) +- docs/release.html: enlève l'Acer CB5 de la liste des futurs candidats. + - Trop de problèmes. Les Chromebooks sont limités (RAM/stockage/wifi soudé) et ont trop de problèmes ergonomiques pour le projet libreboot. +- docs/gnulinux/grub\_cbfs.html nettoyage majeur. Améliorations ergonomiques. +- flash (script flashrom): enlève boardmismatch=force + - C'était mis là avant pour les utilisateurs mettant à jour de libreboot r5 à libreboot r6, mais permet aussi à l'utilisateur de flasher la mauvaise image. Par example, l'utilisateur pouvait flasher l'image d'un T60 sur un X60, et donc bousiller le système. Il est presque certain que la majorité des pergens ont mis à jour maintenant, donc nous enlevons cette option potentiellement dangereuse. +- Documentation: met à jour la liste de compatibilité pour les écrans LCD X60T. +- docs/release.html: ajoute une note à propos de la carte mère du X60 Tablet dans les X60/X60s. +- docs/howtos/grub\_boot\_installer.html: petites corrections +- docs/howtos/grub\_boot\_installer.html: lisibilité améliorée, a corrigé les erreurs html. +- Documentation (en lien avec le macbook21): nettoyage général. + + +Version 20141015 {#release20141015} +================ + +Machines supportées dans cette version: +----------------------------------- + +- **Lenovo ThinkPad X60/X60s** + - Vous pouvez aussi enlever la carte mère d'un X61/X61s et le remplacer avec la carte mère d'un X60/X60s. La carte mère d'une X60 Tablet pourra aussi rentrer à l'intérieur d'un X60/X60s. +- **Lenovo ThinkPad X60 Tablet** (résolutions 1024x768 et 1400x1050) avec support pour scanneur. + - Regardez **hardware/\#supported\_x60t\_list** pour une liste d'écran LCDs supportés. + - C'est inconnu s'il se peut qu'une X61 Tablet ait sa carte mère remplacée par une carté mère d'une X60 Tablet. +- **Lenovo ThinkPad T60** (carte graphique Intel) (il y a des problèmes, regardez ci-dessous): + - Regardez les notes pour les exceptions, et **hardware/\#supported\_t60\_list** pour des écrans LCD connus pour marcher. + - C'est inconnu s'il se peut qu'une T61 ait sa carte mère remplacée par une carté mère d'une T60. + - Voir **future/\#t60\_cpu\_microcode**. + - Le T60p (et variante du T60 avec carte graphique ATI) ne sera sûrement jamais supporté: + **hardware/\#t60\_ati\_intel** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - Voir **hardware/\#macbook11**. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA7600LL/A, MB063LL/A, MB062LL/A) + - Voir **hardware/\#macbook21**. + + + + +Changements pour cette version (les derniers changements en premier, les plus récents en dernier) +---------------------------------------------------------------------- + +- A mis à jour coreboot (git commit 8ffc085e1affaabbe3dca8ac6a89346b71dfc02e), la dernière version au temps de l'écriture. +- A mis à jour SeaBIOS (git commit 67d1fbef0f630e1e823f137d1bae7fa5790bcf4e), la dernière version au temps de l'écriture. +- A mis à jour Flashrom (révision svn 1850), la dernière version au temps de l'écriture. +- A mis à jour GRUB (git commit 9a67e1ac8e92cd0b7521c75a734fcaf2e58523ad), la dernière version au temps de l'écriture. +- A nettoyé la documentation, enlève les fichiers non nécessaires. +- ec/lenovo/h8 (x60/x60s/x60t/t60): active le wifi/bluetooth/wwan/pavé tactile/dispositif de pointage par défaut. +- Documentation: a mis à jour la liste des écrans LCD du T60 (Samsung LTN150XG 15" XGA listé comme ne marchant pas). +- builddeps-coreboot: ne compile pas libpayload (non nécessaire. Cela a été laissé par erreur, lors de l'essai de la charge utile TINT). +- Remplace la majorité des fichiers de diff (patchs) avec des branches gerrit (choisies sur le volet). +- Documentation: x60\_security.html et t60\_security.html: a ajouté des liens pour informer à propos du contrôleur Ethernet (Intel 82573). +- Documentation: x60\_security.html et t60\_security.html: a ajouté des notes à propos de DMA (accés direct à la mémoire) et du dock. +- Documentation: configuring\_parabola.html: étapes basiques de post-installation pour Parabola GNU+Linux (utile, puisque le développement de libreboot est en train d'être bougé sur Parabola GNU+Linux au temps de l'écriture). +- builddeps-coreboot: utiliser 'make crossgcc-i386' au lieu de 'make crossgcc'. Libreboot cible seulement l'architecture x86 au temps de l'écriture. +- Les images ROM n'incluent plus SeaBIOS. Au lieu de ça, l'utilisateur l'ajoute après. A mis à jour la documentation et les scripts. +- docs/images/encrypted\_parabola.html: Notes à propos de linux-libre-grsec +- Documentation: encrypted\_parabola.html: ajoute un tutoriel pour une installation chiffrée de Parabola GNU+Linux. +- Documentation: a ajouté plus d'information à propos des jeu de puces (chipsets) wifi. + + +6ième version (pre-version, bêta pour la 7ième) {#release20140911} +=================================== + +- Publié le 11 Juillet 2014 (pré-version) première bêta +- Revu (pré-version, seconde bêta) le 16 Juillet 2014 +- Revu (pré-version, troisième bêta) 20 Juillet 2014 +- Revu (pré-version, quatrième bêta) 29 Juillet 2014 +- Revu (pré-version, cinquième bêta) 11 Août 2014 (corrigé le jour-même) +- Revu (pré-version, sixième bêta) 3 Septembre 2014 +- Revu (pré-version, septième bêta) 11 Septembre 2014: + + +Machines encore supportées (comparé à la dernière version): +-------------------------------------------------------- + +- **Lenovo ThinkPad X60/X60s** + - Vous pouvez aussi enlever la carte mère d'un X61/X61s et la remplacer avec celle d'un X60/X60s. + + +Nouveaux systèmes supportés dans cette version: +-------------------------------------- + +- **Lenovo ThinkPad X60 Tablet** (résolution 1024x768 et 1400x1050) avec support pour le scanneur + - Voir **hardware/\#supported\_x60t\_list** pour la liste d'écrans LCD supportés. + - C'est inconnu s'il se peut qu'une X61 Tablet ait sa carte mère remplacée par celle d'une X60 Tablet. +- **Lenovo ThinkPad T60** (carte graphique Intel) (il y a des problèmes; regardez ci-dessous) + - Voir les notes ci-dessous pour des exceptions, et **hardware/\#supported\_t60\_list** pour des écrans LCD connus pour marcher. + - C'est inconnu s'il se peut qu'un T61 ait sa carte mère remplacée par celle d'un T60. + - Le T60p (et variantes du T60 avec carte graphique ATI) ne sera sûrement jamais supporté: + **hardware/\#t60\_ati\_intel** +- **Apple MacBook1,1** (MA255LL/A, MA254LL/A, MA472LL/A) + - Voir **hardware/\#macbook11**. +- **Apple MacBook2,1** (MA699LL/A, MA701LL/A, MB061LL/A, MA700LL/A, MB063LL/A, MB062LL/A) + - Voir **hardware/\#macbook21** + +Machines n'étant plus supportés (comparé à la version précédente): +------------------------------------------------------------ + +- **Tous les systèmes précédents sont encore supportés** + +Modifications pour r20140911 (7ième bêta) (11 Septembre 2014) +-------------------------------------------------------- + +- Les changements ci-dessous ont été fait dans un répertoire git, contrairement aux précédentes versions. Les descriptions ci-dessous sont copiés depuis 'git log'. +- Met à jour .gitignore pour les nouvelles dépendances. +- Utilise un submodule pour i945-pwm. +- Ne nettoie pas les paquetages qui échouent ou qui n'ont pas besoin de nettoyage. +- Ne nettoie pas i945-pwn, ce n'est pas nécessaire. +- Correction de régression: Ré-ajoute CD-ROM (ata0) dans le GRUB +- Documentation: ajoute des notes à propos de la pénalité de performance lors de l'utilisation d'ecryptfs. +- Documentation: a corrigé des erreurs de grammaire et d'orthographe. +- Documentation: macbook21: ajoute un nouveau système comme testé +- Documentation: macbook21: ajoute des infos à propos de l'amélioration de la sensitivité du pavé tactile. +- Documentation: X60 Tablet: ajoute plus d'informations à propos de la saisie des doigts. +- Documentation: release.html: ajoute des informations à propos des commit récemment fusionnés dans coreboot. + + +Modifications pour r20140903 (6ième bêta) (3 Septembre 2014) +------------------------------------------------------- + +- A ajouté des scripts builddeb\* modifiés pour Parabola GNU+Linux-libre: + builpac, builpac-flashrom, buildpac-bucts (courtoisie de Noah Vesely) +- Documentation: a mis à jour toutes les sections concernés pour mentionner l'utilisation des scripts dans buildpac\* pour les utilisateurs de Parabola. +- Documentation: a ajouté des informations montrant comment activer ou désactiver le bluetooth sur le X60. +- MacBook1,1 testé! Regardez **hardware/\#macbook11** +- Documentation: a corrigé une faute d'ortographe dans \#get\_edid\_panelname (a changé get-edit en get-edid) +- Documentation: a ajouté images/x60\_lcd\_change/ (seulement des images pour maintenant) +- A ajouté gcry\_serpent et gcry\_whirlpool à la liste de module GRUB +dans le script 'build' (pour les utilisateurs de luks) +- **Libreboot est maintenant basé sur une nouvelle version de coreboot du 23 août, 2014:\ + A fusionné les commits (concerne les cartes mères qui étaient déjà supportées dans libreboot):** + - + - (déjà fusionné) + - (déjà fusionné) + - (déjà fusionné) + - (déjà fusionné) + - ** (déjà fusionné)** + - (déjà fusionné) + - (déjà fusionné) + - (déjà fusionné) + (patch mode texte, pourrait peut-être activé memtest. macbook21) + - (FUSIONNÉ) (enlève le délai inutile dans le clavier ps/2 du macbook21. déjà fusionné) +- Ceux qui ont été aussi fusionné dans coreboot (concerne les cartes mères que libreboot supporte déjà): + - (fusionné) + - (fusionné) + - (fusionné) + - (fusionné) + - (fusionné) + - (fusionné) + +- Documentation: a enlevé la section à propos de tft\_brightness sur l'X60 (le nouveau code le rend obsolète) +- A enlevé tous les patchs de resources/libreboot/patch/ et a ajouté un nouveau patch: 0000\_t60\_textmode.git.diff +- A mis à jour le script getcb et DEBLOB. +- A mis à jour les fichiers de configuration sous resources/libreboot/config pour s'accommoder à la nouvelle version de coreboot. +- A enlevé grub\_serial\*.cfg et libreboot\_serial\*.rom, tous les fichiers de configurations/rom sont maintenant unifiés (contenant la même configuration comme les fichiers de ROM serial d'avant) +- A enlevé grub\_serial\*.cfg et libreboot\_serial\*.rom, tous les fichiers de configuration/rom sont maintenant unifiées (contient la même configuration comme les fichiers de rom en série d'avant) + - Documentation: a mis à jour \#rom pour refléter le dessus. +- A mis à jour GRUB à la nouvelle version du 14 Août, 2014. +- A unifié toutes les configuration grub pour tous les systèmes dans un seul grub.cfg sous resources/grub/config +- A mis à jour flashrom à la nouvelle version du 20 Août 2014. +- A ajouté getseabios et builddeps-seabios (builddeps et getall ont été aussi mis à jour). + - A ajouté des instructions à 'buildrom-withgrub' pour inclure bios.bin.elf et vgaroms/vgabios.bin de SeaBIOS à l'intérieur de la ROM. +- A ajouté seabios (et sgavgabios) dans grub en tant qu'option de charge utile dans le menu. +- A désactivé la sortie série dans Memtest86+ (n'est plus nécessaire) pour accélérer les tests. + - MemTest86+ marche proprement maintenant, il peut s'afficher sur l'écran de l'ordinateur portable (plus besoin de port série). +- A ajouté getgrubinvaders, et les scripts builddeps-grubinvaders. A ajouté ceux-ci à getall et builddeps. + - A ajouté [GRUB Invaders](https://www.coreboot.org/GRUB_invaders) dans les choix de menu dans resources/grub/config/grub.cfg +- A ajouté des régles à builddeps-coreboot pour construire libpayload avec TinyCurses (a ajouté les instructions approprié dans le script cleandeps) +- A décommenté des lignes dans resources/grub/config/grub.cfg pour faire charger les polices d'écritures/fonds d'écrans (n'est plus utile, maintenant que grub est en mode texte). +- A décommenté des lignes dans buildrom-withgrub qui incluaient les polices d'écritures/fonds d'écrans (n'est plus utile, maintenant que grub est en mode texte). +- A ajouté resources/utilities/i945-pwm/ (de git://git.mtjm.eu/i945-pwd), pour déboguer la luminosité acpi sur les systèmes i945. + - A ajouté des instructions pour celà dans builddeps, builddeps-i945pwm, builddeb et cleandeps +- script de 'build': a enlevé les parties qui ont généré les manifestes sha512sum (non nécessaire, depuis que les tarballs de versions sont signés avec GPG). +- script de 'build': a enlevé les parties qui ont généré le répertoire libreboot\_meta (n'est plus nécessaire, depuis que \_meta sera hébergé dans git) + - A mis à jour \#build\_meta (et autres parties de la documentation) pour s'adapter à ce changement. +- Documentation: a simplifié (a refaçonné) les notes dans \#rom +- script de 'build': a enlevé les parties qui ont généré libreboot\_bin et les a ajoutés dans un nouveau script: 'build-release' + - Documentation: \#build mis à jour pour réfléter le dessus. +- A ajouté tous les modules gcry\_\* dans grub (luks/cryptomount): + gcry\_arcfour gcry\_camellia gcry\_crc gcry\_dsa gcry\_md4 + gcry\_rfc2268 gcry\_rmd160 gcry\_seed gcry\_sha1 gcry\_sha512 + gcry\_twofish gcry\_blowfish gcry\_cast5 gcry\_des gcry\_idea + gcry\_md5 gcry\_rijndael gcry\_rsa gcry\_serpent gcry\_sha256 + gcry\_tiger gcry\_whirlpool~~ +- A ajouté la liste de modules GNUtoo (incluent tous les modules gcry\_\* d'au-dessus), cryptomount devrait marcher maintenant. +- A enlevé builddeb-bucts et builddeb-flashrom, a fusionné avec builddeb (a mis à jour en accordance). +- A enlevé builddeb-bucts et builddeb-flashrom, a fusionné avec buildpac (a mis à jour en accordance). +- A renommé buildpac en deps-parabola (a mis à jour en accordance). +- Documentation: a enlevé toutes les parties à propos des dépendances de build, les a remplacées avec des liens vers \#build\_dependencies, +- Documentation: a mis l'emphase plus fortement dans la documentation sur le fait du besoin de recompiler bucts et/ou flashrom avant de la flasher une image ROM. +- build-release: flashrom, nvramtool, cbfstool et bucts ne sont plus fournis pré-compilé dans les archives d'éxecutables, et sont maintenant sous la forme source seulement. (pour maximiser la compatibilité avec les distributions). +- script de 'build': a remplacé les instructions d'assemblage de grub.elf, c'est maintenant pris en charge par un utilitaire ajouté sous resources/utilities/grub-assemble. +- A bougé resources/grub/keymap dans resources/utilities/grub-assemble/keymap, et a mis à jour cet utilitaire. +- Documentation: a enlevé les liens inutiles d'images de dispositions de claviers et de dispositions non modifiés. +- A enlevé toutes les polices d'écritures non utilisées du répertoire dejavu-fonts-ttf-2.34/ +- script de 'buildrom-withgrub': a mis à jour pour créer 2 sets de ROMs pour chaque système: un avec le mode texte, un avec la mémoire d'affichage de coreboot. +- Documentation: a mis à jour \#rom en accordance avec le dessus. +- A supprimé les fichiers inutilisés README et COPYING du répertoire principal. +- A enlevé quelques instructions d'rm -Rf .git\* des scripts get\* et les a bougés dans le script build-release. +- A partagé la grub.cfg par défaut en 6 partiess: + extra/{common.cfg,txtmode.cfg,vesafb.cfg} et + menuentries/{common.cfg,txtmode.cfg,vesafb.cfg} + - le script buildrom-withgrub utilise ceux-ci pour générer le grub.cfg pour chaque type de configuration. +- grub\_memdisk.cfg (utilisé à l'intérieur de grub.elf) charge maitenant seulement grub.cfg depuis cbfs. Celà n'active plus la sortie série ou met en place des préfixes (menuentries/common.cfg le fait à la place). +- resources/grub/config/extra/common.cfg a ajouté: + - instructions insmod pour charger ces modules: nativedisk, ehci, ohci, uhci, usb, usbserial\_pl2303, usbserial\_ftdi, usbserial\_usbdebug + - a mis à jour prefix=(memdisk)/boot/grub + - Pour les graphiques natifs (recommandé par le wiki coreboot):\gfxpayload=keep\terminal\_output \--append gfxterm + - Joue un beep au démarrage:\ play 480 440 1 +- Documentation: a mis à jour gnulinux/grub\_cbfs pour le rendre plus sécurisé (et facile) à suivre. + + +Corrections dans r20140811 (5ième beta) (11 Août 2014) +------------------------------------------------------ +- A corrigé un erreur où la liste des révisions pour la 5ième bêta était listée comme étant du 11 Mars 2014, alors qu'en fait du 11 Août 2014 +- A corrigé un grub.cfg incorrect qui a été actuellement plaçé dans resources/grub/config/x60/grub\_usqwerty.cfg qui a cassé l'option par défaut du menu GRUB du X60. + + + +Corrections to r20140811 (5ième beta) (11 Août 2014) +----------------------------------------------------- +- build: a ajouté 'luks', 'lvm', 'cmosdump' et 'cmostest' à la liste des modules pour grub.elf +- Documentation: a ajouté des images montrat le débousillage du T60 (encore besoin d'écrire un tutoriel) +- compilation: a inclut les fichiers cmos.layout (coreboot/src/mainboard/manufacturer/model/cmos.layout) dans libreboot\_bin +- Documentation: a ajouté **install/x60tablet\_unbrick.html** +- Documentation: a ajouté **install/t60\_unbrick.html** +- Documentation: a ajouté **install/t60\_lcd\_15.html** +- Documentation: a ajouté **install/t60\_security.html** +- Documentation: a ajouté **install/t60\_heatsink.html** +- Documentation: a renommé RELEASE.html en release.html +- Documentation: a enlevé la référence à pcmcia dans x60\_security.html (c'est cardbus) +- Documentation: a ajouté des informations préliminaires à propos de la marque au hasard (pour la détection d'intrusion physique) dans x60\_security.html et t60\_security.html +- Documentation: a ajouté des informations préliminaires à propos de la marque au hasard (pour la détection d'intrusion physique) dans x60\_security.html et t60\_security.html +- Documentation: a ajouté des informations préliminaires à propos de prévenir/mitiger les attaques de démarrage à froid dans x60\_security.html et t60\_security.html +- Documentation: a ajouté des informations dans \#macbook21 avertissant à propos de problèmes avec macbook21 +- Documentation: X60/T60: a ajouté des informations à propos de la vérification des ROMs personnalisés en utilisant dd, pour savoir si oui ou non la région de 64Ko est dupliqué en dessous de top ou non. Conseille la prudence à propos de cela dans le tutoriel qui traite avec le flashage sur le BIOS Lenovo, citant les commandes dd nécessaires si il est confirmé que la ROM n'a pas encore été appliquée avec dd. (dans le cas que l'utilisateur a compilé leur propre ROMs depuis libreboot, en utilisant pas les scripts de build, ou si ils ont oublié d'utiliser dd, etc). +- A partagé resources/libreboot/patch/gitdiff dans des fichiers de patch séparés (le script getcb a été mis à jour pour s'accomoder à ce changement). +- A ré-ajouté les fichiers .git à bucts +- A corrigé l'oubli où le fichier macbook21\_firstflash n'était pas inclut dans les archives d'éxecutables +- Les archives de versions sont maintenant compressées utilisant .tar.xz pour une meilleure compression. + + +Modifications pour r20140729 (4ième beta) (29 Juillet 2014) +--------------------------------------------------- + +- Documentation: a été amélioré (plus d'explications, informations contextuelles) dans docs/security/x60\_security.html (courtoisie de Denis Carikli) +- Le MacBook2,1 a été testé (et confirmé) +- macbook21: a ajouté le script 'macbook21\_firstflash' pour le flashage de libreboot pendant que le micrologiciel EFI d'Apple est en marche. +- Documentation: macbook21: a ajouté des instructions pour le flashage basé logiciel de libreboot pendant que le micrologiciel EFI d'Apple est en marche. +- A réduit la taille du fichier libreboot\_src.tar.gz: + - A enlevé .git et .gitignore du répertoire grub (libreboot\_src); pas nécessaire. Les enlever réduit la taille de l'archive (par beaucoup). Le développement de GRUB devrait se faire en amont. + - A enlévé .git et .gitignore du répertoire bucts (libreboot\_src); pas nécessaire. Les enlever réduit la taille de l'archive. Le développement de bucts devrait se faire en amont. + - A enlevé .svn du répertoire flashrom (libreboot\_src); pas nécessaire. L'enlever réduit la taille de l'archive. Le développement de flashrom devrait se faire en amont. +- A ajouté des ROMs avec une dispostion Qwerty (Italienne) dans GRUB (libreboot\*itqwerty.rom) +- A ajouté le script ressources/utilities/i945gpu/intel-regs.py pour des problèmes de débogguage en lien avec la compatibilité d'écrans LCD sur l'X60 Tablet et le T60. (courtoisie de [Michał Masłowski](http://mtjm.eu)) + + +Modifications pour r20140720 (3ième beta) (20 Juillet 2014) +--------------------------------------------------- + +- A corrigé la faute d'ortographe qui a existé dans la seconde bêta où la date de publication de cette dernière était listée comme étant en 2016, alors qu'en fait c'était 2014. +- Documentation: a ajouté des détails (préliminaires) à propos de (rares) processeurs bogués sur le ThinkPad T60 qui ont été trouvé comme en échec (instabilité, panique de kernels, etc) sans les mises à jour du microcode. +- Documentation: a ajouté docs/hardware/x60\_heatsink.html pour montrer comment changer le dissipateur thermique sur le ThinkPad X60 +- A ajouté des images ROMs pour la disposition clavier Azerty (Français) dans GRUB (courtoisie d'Olivier Mondoloni). +- A réarrangé quelques scripts: + - ~~Re-factorisé ces scripts (les a rendus plus facile à lire/maintenir): + build-x60, build-x60t, build-t60, build-macbook21~~ + - ~~A réduit le nombre de configurations grub à 2 (ou 1, pour le macbook21), les scripts de compilation génère maintenant les autres configurations au temps de la compilation.~~ + - A supprimé build-x60, build-x60t, build-t60, build-macbook21 et l'a remplacé avec un script (générique) buildrom-withgrub intelligent + - A mis à jour la compilation pour utiliser le script buildrom-withgrub pour la compilation des images ROM. + - coreboot.rom et coreboot\_serial.rom ont été renommé en coreboot\_usqwerty.rom et coreboot\_serial\_usqwerty.rom + - coreboot\_dvorak et coreboot\_serial\_dvorak.rom ont été renommé en coreboot\_usdvorak.rom et coreboot\_serial\_usdvrak.rom + - A renommé coreboot\*rom en libreboot\*rom + - A rendu les scripts flash, lenovobios\_firtflash et lenovobios\_secondflash s'arrêter et échouer si le fichier spécifié n'existe pas. + - A mis à jour toutes les parties pertinentes de la documentation pour réfléchir le dessus. + - A remplaçé le background.png avec background.jpg. A ajouté gnulove.jpg. (resources/grub/background) +- A mis à jour buildrom-withgrub pour utiliser background.jpg au lieu de background.png +- A mis à jour buildrom-withgrub pour utiliser gnulove.jpg aussi +- A mis à jour les fichiers ressources/grub/config/macbook21/grub\*cfg pour utiliser le fond d'écran gnulove.jpg. +- A mis à jours les fichiers resources/grub/config/{x60,t60,x60t}/grub\*cfg pour utiliser le fond d'écran background.jpg +- Documentation: a mis à jour docs/\#grub\_custom\_keyboard pour être généralement plus utile. +- nvramtool: + - A mis à jour le script builddeps-coreboot pour le compiler + - A mis à jour le script de compilation pour l'inclure dans libreboot\_bin +- Documentation: a ajouté docs/security/x60\_security.html ( durcissement de la sécurité pour le X60) + +Modifications pour r20140716 (Seconde beta) (16 Juillet 2014) +-------------------------------------------------- + +- A supprimé tous les fichiers liés à git dans le répertoire coreboot. C'était nécessaire parce qu'avec ceux-ci il est possible d'exécuter 'git diff' qui montre les changements fait sous la forme d'un patch (sous format diff); cela inclut les blobs qui ont été supprimé pendant le déblobbage. + + +Modifications pour r20140711 (1ère beta) (11 Juillet 2014) +--------------------------------------------------- + +- Publication initiale (nouvelle base coreboot, datée du 1 Juin 2014. Voir le script 'getcb' pour référence) +- coreboot DÉBLOBBÉ +- A enlevé la partie de memtest86+ 'make' où ça essayait de se connecter à un serveur scp pendant la compilation ( a décommenté la ligne 24 dans la Makefile) +- Le X60 utilise maintenant un seul .config (pour coreboot) +- Le X60 utilise maintenant un seul grub.cfg (pour le disque mémoire grub) +- Le X60 utilise maitenant un seul grub.elf (en tant que charge utile) +- A ajouté un nouveau code graphique pour X60 (remplace le vieux code 'replay') de Vladimir Serbinenko: 5320/9 de review.coreboot.org +- Le T60 est maintenant supporté, avec des graphiques natifs (5345/4 de review.coreboot.org, pris sur le volet au dessus du checkout 5320/9) +- A ajouté le support pour le macbook2,1 ( fait par Mono Moosbart et Vladimir Serbinenko) depuis review.coreboot.org (voir le script 'getcb' pour savoir comment cela a été fait) + - Documentation: a ajouté des informations amenant sur la bonne page et parlant à propos des modèles qui sont supportés + - A ajouté le fichier resources/libreboot/config/macbook21config + - macbook21: a ajouté le script 'build-macbook21' et a fait un lien vers lui dans 'build' (les ROMs incluent sous bin/macbook21/) + - macbook21: a enlevé les instructions dd du script build-macbook21 (le macbook21 n'a pas besoin de bucts lors du flashage du libreboot pendant que le micrologiciel EFI d'Apple est en marche ). + - Documentation: a ajouté les ROMs macbook21 à la liste des ROMs dans docs/\#rom + - Documentation: a écrit la documentation faisant lien vers la page de Mono Moosbart à propos du macbook21 et Parabola (et inclut une copie) +- Documentation: a ajouté une copie du guide d'installation de Parabola de Mono (pour le macbook21 avec le micrologiciel EFI d'Apple) a mis un lien vers dans la page principale. +- Documentation: a ajouté une copie de la page coreboot de Mono (pour macbook21) et a mis un lien vers dans la page principale. +- T60: copie les options CD des fichiers grub.cfg pour les images \*serial\*.rom du T60 dans les configurations grub pour les images non-serial. (les ordinateurs portables ont un disque CD/DVD sur l'ordinateur portable principal) +- macbook21: enlève les options dans build-macbook21 pour \*serial\.rom (il n'y pas de dock ou port série disponible pour macbook21) +- A ajouté des patchs pour les contrôles du rétroéclairage sur le X60 et T60 avec l'aide de Denis Cariskli (voir ./resources/libreboot/patch/gitdiff et ./getcb et docs/i945\_backlight.md) + - Documentation: a ajouté docs/i945\_backlight.md montrant comment les contrôles du rétroclairage ont été concus pour marcher sur le X60/T60. +- Documentation: a ajouté des informations à propos de la récupération du nom de l'écran LCD basé sur les données EDID. + - Documentation: a ajouté un lien vers cela depuis la liste des ordinateurs portables T60 supportés et des écrans supportés pour les ordinateurs portables T60 (comme ça l'utilisateur peut vérifier quel écran LCD ils ont). +- X60/T60: A fusionné les patchs pour la correction de la 3D (de Paul Menzel) lors de l'utilisation du kernel 3.12 ou plus haut (voir ./resources/libreboot/patch/git diff et ./getcb) + - basé sur 5927/11 et 5932/5 de review.coreboot.org +- A amélioré le support de thinkpad\_acpi (de coreboot) : les xsensors montrent plus d'informations. + - pris de 4650/29 dans review.coreboot.org (fusionné dans le 'master' de coreboot le 1er Juin 2014) +- A fusionné les changements pour le numériseur (X60 Tablet et IR (X60 et T60) basé sur 5243/17, 5242/17 et 5239/19 de review.coreboot.org + - (voir ./resources/libreboot/patch/gitdiff et ./getcb) +- Documentation: a ajouté des informations à propos de la compilation de flashrom utilisant le script 'builddeps-flashrom'. +- A re-créé resources/libreboot/config/x60config +- A re-créé resources/libreboot/config/t60config +- A ajouté 'x60tconfig' dans resources/libreboot/config (parce que la X60 Tablet a des informations différentes à propos de serial/model/version dans 'dmidecode') + - A ajouté le script 'build-x60t' + - A mis à jour le script 'build' pour utiliser 'build-x60t' + - Documentation: a ajouté à la section \#config la section \#config\_x60t (la configuration de libreboot et l'information de dmidecode) + - Documentation: a ajouté les ROMs x60t à la liste des ROMs. +- A arrangé le script 'builddeps' (plus facile à lire) +- A arrangé le script 'cleandeps' (plus facile à lire) +- A annoté le script 'buildall' +- A ajouté le script 'getcb' pour récupérer la modification depuis coreboot utilisée depuis git, et la patcher. +- A ajouté le script 'getgrub' pour récupérer la modification de GRUB utilisée depuis git, et la patcher. +- A ajouté le script 'getmt86' pour récupérer la version de memtest86+ utilisée, et la patcher. +- A ajouté le script 'getbucts' pour récupérer la version de bucts utilisée. +- A ajouté le script 'getflashrom' pour récupérer la version de flashrom utilisé, et la patcher. +- A ajouté le script 'getall' qui exécute tout les autres scripts 'get'. +- Ajoute des instructions dans le script 'build' pour préparer libreboot meta.tar.gz + - Nouvelle archive: libreboot\_meta.tar.gz - archive minimale, utilisant les scripts 'get' pour télécharger toutes les dépendances (coreboot, memtest, grub et ainsi de suite). +- Documentation: a ajouté des informations à propos d'où le script 'build' prépare l'archive libreboot\_meta.tar.gz. +- Documentation: a ajouté des informations à propos de la façon d'utiliser les scripts 'get' dans libreboot\_meta.tar.gz (pour générer libreboot\_src.tar.gz) + - Documentation: mention que la meta ne créé pas le répertoire libreboot\_src/, mais que libreboot\_meta lui-même devient le même. + - Documentation: conseille de renommer libreboot\_meta en libreboot\_src après avoir exécuté 'getall'. +- A annoté le script 'builddeb', pour dire qu'est ce que chaque lots de dépendances sont pour. +- A divisé les sections bucts/flashrom builddeb en des scripts séparés +- A annoté le script 'builddep', pour dire ce que chaque set de dépendances sont faites pour. +- A séparé les sections builddeb bucts/flashrom en des scripts séparés: builddeb-flashrom, builddeb-bucts. +- Documentation: A mis à jour des parties pertinentes en relation avec les information ci-dessus. +- A ajouté des instructions au script 'buil pour inclure builddeb-bucts et builddeb-flashrom dans libreboot\_bin +- A mis à jour la révision de flashrom (r1822 2014-06-16) depuis SVN (http://flashrom.org/Download). + - A mis à les instructions dans docs/ pour les nouvelles commandes necéssaires (Puce Macronix sur le X60/T60) + - Pour X60/T60 (flahrom): a patchéles exécutables + flashchips.c\_lenovobios\_macronix et + flashchips.c\_lenovobios\_sst pour SST/macronix + (inlus dans resources/flashrom/patch) + - A mis à jour builddeps pour construire flashrom__lenovobios\_sst et flashrom\_lenovobio\_macronix, pour les utilisateurs du X60/T60 avec le BIOS Lenovo + - A bougé les instructions de compilations flashrom de 'builddeps' et les a mis dans 'builddeps-flashrim', a executé celà depuis 'builddeps'. + - A ajouté builddeps-flashrom dans libreboot\_bin.tar.gz +- flashrom: a ajouté le flashchips.c patché dans resources/flashrom/patch (utilise automatiquement la puce macronix correcte sur libreboot, sans utilisé le paramètre -c) + - A enlevé les entrées 'MX25L1605' et 'MX25L1605A/MX25L1606E' dans flashchips.c pour la verion patchée de flashchips.c + - A ajouté des instructions pour 'builddeps-flashrom' pour automatiquement utiliser ce flashchips.c modifié dans la compilation par défaut. +- A ajouté builddeb pour libreboot\_bin.tar.gz +- A bougé les instructions de la compilation de 'bucts' depuis builddeps dans builddep-bucts. + - builddeps exécute maintenant 'builddeps-bucts' au lieu de celà. + - A ajouté 'builddeps-bucts' dans libreboot\_bin.tar.gz + - Documentation: a ajouté des informations à propos de l'utilisation de 'builddep-bucts' pour construire l'utilitaire BUC.TS +- A ajouté les scripts 'lenovobios\_firstflash' et 'lenovobios\_secondflash' + - A ajouté des instructions dans le script 'build' pour inclure ces fichiers dans libreboot\_bin + - Documentation: ajout d'un tutoriel pour flashé pendant que le BIOS Lenovo est en marche (sur le X60/T60). + + - Added instructions to 'build' script for including those files + in libreboot\_bin + - Documentation: Add tutorial for flashing while Lenovo BIOS is + running (on X60/T60) +- A ajouté le script 'flash' (assurez-vous d'exécuter en premier builddeps-flashrom) qui (pendant que libreboot est déjà exécutéé) peut utiliser flahrom pour flasher une ROM + - ex: "sudo ./flash bin/x60/coreboot\_serial\_ukdvorak.rom" est équivalent à "sudo ./flashrom/flashrom -p internal -w bin/x60/coreboot\_uk\_dvorak.rom" + - A mis à jour le script 'build' pour inclure le script 'flash' dans libreboot\_bin.tar.gz +- Documentation: a remplacé le tutoriel par défaut flashrom pour recommander le script 'flash' à la place. +- Ré-ajout du code source de cbstool dans libreboot\_bin.tar.gz, en tant que cbfstool\_standalone + - A patché cette version pour marché (capable d'être compilé et utilisée) sans avoir besoin de la totalité du code source de coreboot. + - A créé une version patché des fichiers sources concernés et les a ajoutés dans resources/cbfstool/patch + - regardez coreboot/util/cbfstoll/rmodule.c et ensuite la version patchée dans resources/cbfstool/patch/rmodule.c + - regardez coreboot/src/include/rmodule-defs.h et la régle dans 'build' pour inclure ceci dans ../libreboot\_bin/cbfstool\_standalone + - A ajouté des instructions dans le script 'build' pour appliquer ce patch sur la source cbfstool\_standalone dans libreboot\_bin + - A ajouté des instructions dans le script 'build' pour ensuite re-compiler cbfstool\_standalone dans libreboot\_bin après avoir appliqué le patch. + - A ajouté un script 'builddeps-cbfstool' (dans src, mais seulement utilisé dans bin et mis dans bin par 'build') qui compile cbfstool\_standalone dans libreboot\_bin (make), déplace les éxecutables cbfstool et rmodtool dans libreboot\_bin/ et ensuite fait 'make clean' dans libreboot\_bin/cbfstool\_standalone + - A mis à jour le script 'build' pour mettre 'builddep-cbfstool' dans libreboot\_bin + - A mis à jour le script 'build' dans cbfstool (standalone) pour s'accomoder au dessus. + - Documentation: a ajouté des notes à propos de cbfstool (standalone) dans libreboot\_bin +- Documentation: a rendu docs/gnulinux/grub\_cbfs.html légèrement plus facile à suivre. +- A annoté les scripts 'build\*' avec des commandes 'echo', pour aider l'utilisateur à comprendre qu'est ce qui en train de se passer pendant le processus de compilation. +- Documentation: a ajouté des informations à propos de comment les données de 'dmidecode' ont été mise dans les configs de coreboot + - Documentation: En fait, documente comment les fichiers 'config' dans resources/libreboot/config/ ont été créé. +- Documentation: A ajouté des informations à propos de quels ordinateurs portables ThinkPad T60 sont supportés, et ceux qui ne le sont pas. +- Documentation: a ajouté des informations à propos des onduleurs LCD (pour une mise à niveau de l'écran LCD sur un T60 14.1' XGA ou 15.1' XGA) + - c'est FRU P/N 41W1478 (sur le T60 14.1") donc ça a été ajouté dans les documentations. + - c'est P/N 42T0078 FRU 42T0079 ou P/N 41W1338 (sur T60 15.1") donc ça a été dans la documentations. +- Documentation: a ajouté des informations à propos des noms des écrans LCD pour le T60 dans les parties concernés de la documentation. +- Documentation: a ajouté des informations (avec des images) à propos des différences entre le T60 avec une carte graphique Intel et le T60 avec carte graphique ATI. +- Documentation: a ajouté des images de dispositions de claviers (US/UK Qwerty/Dvorak) à la liste des ROM, pour laisser l'utilisateur comparer avec son propre clavier. +- A déplacé les instructions de compilation de coreboot de 'builddeps' dans 'builddeps-coreboot' et met un lien dans 'builddeps' + - Attache à 'builddeps-coreboot' dans le stage final de 'getcb' 'builddeps-grub', relié depuis 'builddeps' + - Attache à 'builddeps-grub' dans le stage final de 'getgrub' +- Déplace les instructions de compilation de MemTest86+ de 'builddeps' dans 'builddeps-memtest86', relié depuis 'builddeps' + - Attache à 'builddeps-memtest86' dans le stage final de 'getmt86' +- a rendu le script 'build' mettre le répertoire resources/ dans libreboot\_bin, pour faire marcher builddeps-flashrom dans libreboot\_bin +- A enlevé les instructions pour compiler le code source dans le script 'get' (elles n'ont pas vraiment quelque chose à faire là-bas) +- A ajouté libfuse-dev et liblzma-dev à la liste des dépendances de GRUB dans le script 'builddeb'. +- A converti le fichier 'RELEASE' en 'docs/RELEASE.html' +- A ajouté ces dépendaces au script builddeb (pour la partie GRUB): gawk libdevmapper-dev libtool libfreetype6-dev +- A ajouté des instructions à la fin du script de compilation pour créer sha512sum.txt avec un fichier de manifeste plus des sommes de controle. +- A supprimé les fichiers RELEASE et BACKPORT (ne sont plus nécessaires) +- Documentation: a ajouté des informations à propos du dock +X60/T60 (ultrabase x6 et minidock avancé) dans les sections concernées. + - Ajouté dans docs/\#serial + +Version 20140622 (5ième version) {#release20140622} +============================== + +- 7 Mars 2014 +- a revu la version du 22 Juin 2014 + +Officiellement supportés +-------------------- + +- ThinkPad X60 +- ThinkPad X60s + +Révision (22 Juin 2014 - extra) +--------------------------------- + +- Documentation: a ajouté le tutoriel de débousillage du X60- Documentation: a ajouté des infos à propos de l'activation ou la désactivation du wifi +- Documentation: a ajouté des infos à propos de l'activation ou la désactivation du dispositif de pointage. + + +Révision (22 Juin 2014 - extra) +--------------------------------- + +- Documentation: A amélioré les instructions pour utiliser flashrom +- Documentation: A amélioré les instructions pour utiliser cbfstool (pour changer le menu GRUB par défaut) +- Documentation: Nombreuses petites corrections. + +Notes de révisions (22 Juin 2014) +------------------------------- + +- A mis à jour GRUB (git 4b8b9135f1676924a8458da528d264bbc7bbb301, 20 Avril 2014) +- A fait de "DeJavu Sans Mono" la police d'écriture par défaut dans GRUB (corrige la corruption des bordures). +- A ré-ajouté un fond d'écran dans GRUB (GNU en train de méditer) +- A ajouté 6 images de plus: + - coreboot\_ukqwerty.rom (disposition de clavier UK Qwerty dans GRUB) + - coreboot\_serial\_ukqwerty.rom (disposition de clavier + UK Qwerty dans GRUB) + - coreboot\_dvorak.rom (disposition de clavier US Dvorak dans GRUB) + - coreboot\_ukdvorak.rom (disposition de clavier US Dvorak dans GRUB) + - coreboot\_serial\_dvorak.rom (disposition de clavier US Dvorak dans GRUB) + - (coreboot.rom et coreboot\_serial.rom ont une disposition de clavier US Qwerty dans GRUB, comme d'habitude) +- A amélioré la documentation: + - a supprimé FLASH\_INSTRUCTION et README.powertop et les a fusionné avec README. + - a enlevé les informations obsolètes du README et l'a nettoyé. + - a supprimé le README (remplacé avec docs/) +- a nettoyé les entrées du menu dans GRUB +- a nettoyé le répertoire racine de X60\_source/, a trié plus de fichiers dans des sous-répertoires +- a amélioré le commentaire à l'intérieur du script 'build' (devrait rendre sa modification plus facile) +- A renommé X60\_binary.tar.gz et X60\_source.tar.gz en libreboot\_bin.tar.gz et libreboot\_src.tar.gz, respectivement +- A remplacé "GNU GRUB version" avec "FREE AS IN FREEDOM" sur l'écran de démarrage GNU GRUB. +- A ajouté les fichiers sha512.txt dans libreboot\_src et libreboot\_bin. (à l'intérieur des archives) +- A ajouté les fichiers libreboot\_bin.tar.gz.sha512.txt et libreboot\_src.tar.gz.sha512.txt (en dehors des archives) + + +Notes de révisions (11 Juin 2014): +-------------------------------- + +- a enlevé l'option de démarrage 'CD' de coreboot.rom (non nécessaire) +- a enlevé les options 'processor.max\_cstate=2' et 'idle=halt' (voir le fichier README.powertop) + +Notes de révisions (5 Juin 2014): +------------------------------- + +- a ajouté le support du rétroéclairage (Fn+Home et Fn+End) sur le X60 +- a corrigé la 3D cassé/instable quand vous utilisez le kernel 3.12 ou plus haut +- (voir le fichier 'BACKPORT') + +Notes de révision (9 Mars 2015): +-------------------------------- + +- a recrée la configuration de coreboot depuis rien +- GRUB charge encore plus vite maintenant (moins de deux secondes). +- Le temps de démarrage a été réduit de 5 secondes de plus. +- A ajouté les modules crypto et cryptodisk dans GRUB +- cbfstool est maintenant inclut dans les archives de binaire. + +Notes de développement +----------------- + +- L'archive de binarie a maintenant 2 images: + - Avec la sortie en série activée et memtest86+ inclut (niveau de déboguage 8 dans coreboot) + - Avec la sortie en série désactive et memtest86+ exclut (temps de démarrage réduits) (déboguage désactivé) +- A réduit l'impact sur la vie de la batterie: + - 'processor.max\_cstate=2' au lieu de 'idle=halt' pour démarrer le kernel par défaut. +- coreboot.rom (vitesses de démarrage plus rapides, déboguage désactivé): + - A désactivé la sortie en série de coreboot (Console-> dans "make menuconfig") + - A mis le niveau de déboguage de coreboot à 0 au lieu de 8 (Console-> dans "make menuconfig") + - A changé le délai d'inactivé à 1 seconde au lieu de 2 (dans grub.cfg) + - A enlevé le fond d'écran dans GRUB. + - A enlevé la charge utile memtest86+ (car celà dépend de la sortie série) +- coreboot\_serial.rom (vitesses de démarrage plus lentes, déboguage activé): + - Temps de démarrage encore réduit, mais seulement par \~2 secondes + - a la charge utile memtest86+ incluse dans la ROM + - a le port série activé. Comment celà est achevé (depuis X60\_source): mettez le niveau de déboguage à 8, et activez la sortie série +- (dans Console-> dans coreboot "make menuconfig") +- (et compile avec grub\_serial.cfg et grub\_memdisk\_serial.cfg) + + +Version 20140221 (4ième version) {#release20140221} +============================== + +- 21 Février 2014 + +Officiellement supportés +-------------------- + +- ThinkPad X60 +- ThinkPad X60s + +Notes de développement +----------------- + +- A enlevé SeaBIOS (redondant) +- Nouvelle version GRUB (2.02\~beta2)a + - Corrige quelques problèmes USB + - Inclut l'analyseur syntaxique ISOLINUX/SYSLINUX +- Nouveau grub.cfg +- A enlevé les options inutiles: + - options pour démarrer sda 2/3/4 + - option de démarrage seabios +- A ajouté de nouvelles entrées de menu: + - Analyse syntaxique ISOLINUX (USB) + - Analyse syntaxique de la configuration ISOLINUX (CD) + - A ajouté le module 'cat' pour l'utiliser sur la ligne de commande GRUB. +- "set pager=1" est configuré dans grub.cfg, pour une fonctionnalité comme less + +Les options "Parse" lisent ./isolinux/isolinux.cfg sur un CD ou une USB, et le convertit automatiquement en une config grub et change sur le menu de démarrage de cette distribution. Celà rend le démarrage des ISOs \*beaucoup\* plus facile qu'avant. + +r20131214 (3ième version) {#release20131214} +======================= + +- 14 Décembre 2013 + +Supportés: +---------- + +- ThinkPad X60 +- ThinkPad X60s + +Notes de développement +----------------- + +- A ajouté la charge utile SeaBIOS à GRUB2 (pour démarrer les clés USBs) +- nouveau grub.cfg + +r20131213 (deuxième version) {#releae20131213} +======================= + +- 13 Décembre 2013 + +Supportés: +---------- + +- ThinkPad X60 +- ThinkPad X60s + +Notes de développement +----------------- + +- a ajouté le fond d'écran dans GRUB2 +- a ajouté la charge utile memtest86+ +- améliorations de la documentation +- nouveau grub.cfg + +r20131212 (première version) {#release20131212} +======================= + +- 12 Décembre 2013 + +Supportés: +---------- + +- ThinkPad X60 +- ThinkPad X60s + +Notes de développement +----------------- + +- version initiale +- code source déblobbé + +Copyright © 2014, 2015, 2016 Leah Rowe \ + +La permission est accordé pour copier, distribuer et/ou modifier ce document sous les termes de la GNU Free Documentation Licence version 1.3 ou n'importe quelles autre version plus récentes publié par la Free Software Foundation avec aucune Sections Invariantes, Texte de Couverture, et Texte de quatrième de couverture. +Une copie de cette licence est trouvé dans [fdl-1.3.md](fdl-1.3.md) diff --git a/i18n/fr_FR/download b/i18n/fr_FR/download new file mode 100755 index 00000000..f9f9c4a3 --- /dev/null +++ b/i18n/fr_FR/download @@ -0,0 +1,100 @@ +#!/usr/bin/env bash + +# download script: Download the programs used in libreboot, that +# aren't distributed in the git repository. +# +# Copyright (C) 2014, 2015 Leah Rowe +# Copyright (C) 2015 Klemens Nanni +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +[ "x${DEBUG+set}" = 'xset' ] && set -v +set -u -e + +download="resources/scripts/helpers/download" + +# echo "${programs##*/}" ; echo "${programs%/*}" +programs="$(for program in ${download}/*; do printf "%s\n" "${program##*/}"; done)" + +noconfirm="0" + +help () { + printf "%s\n\n" "./download program(s) # programs are space separated, if specifing multiple programs" + printf "possible values for 'programs':\nall:\n%s\n\n" "${programs}" + printf "Example (download everything): ./download all\n" + printf "Example (download flashrom): ./download flashrom\n" + printf "Example (download coreboot): ./download coreboot\n" + printf "Example (download coreboot and flashrom): ./download coreboot flashrom\n" + printf "Example (lists all available downloadable components): ./download list\n" +} + +if [ $# -lt 1 ]; then + printf "ERROR: download script: no argument given.\n" + help + exit 1 +fi + +if [ "${1}" = "--noconfirm" ] || [ "${1}" = "-y" ]; then + noconfirm="1" + shift 1 +fi + +case "${1}" in + all) + ;; + list) + printf "possible values for 'programs':\nall\n%s\n\n" "${programs}" + exit + ;; + help) + help + exit + ;; + *) + for program in "${@}"; do + printf "%s" "${programs}\n" | grep -wq "${program}" || (printf "ERROR: Invalid program '%s'. See ./download help.\n" "${program}"; exit 1) + done + programs="${*}" + ;; +esac + +for program in ${programs}; do + + if [ "${noconfirm}" = "0" ]; then + printf "Use \"./download --noconfirm\" or \"./download -y\" if you want to be rid of these confirmation dialogues.\n\n" + if [ -d "${program}/" ]; then + if [ "${program}" = "seabios" ]; then + # temporary hack. download grub also downloads seabios, + # which breaks automated build when running ./download all + # Later on, we'll delete the seabios download script + # and grub download script and replace both with + # a download seagrub script + + rm -Rf "${program:?}" && printf "Old %s directory deleted.\n\n" "${program}" + else + printf "A %s/ directory already exists, delete it? [yN]: " "${program}" + read -r answer + if [ "${answer}" = "y" ]; then + rm -Rf "${program:?}" && printf "Old %s directory deleted.\n\n" "${program}" + else + printf "%s directory not deleted, and therefore not replaced.\n" "${program}" + continue + fi + fi + fi + fi + + "${download}/${program}" +done diff --git a/i18n/fr_FR/flash b/i18n/fr_FR/flash new file mode 100755 index 00000000..7d4b0e2e --- /dev/null +++ b/i18n/fr_FR/flash @@ -0,0 +1,134 @@ +#!/usr/bin/env bash + +# flash script: uses flashrom to flash a libreboot ROM image +# +# Copyright (C) 2014, 2015 Leah Rowe +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +# So that I one day find it again +# http://pubs.opengroup.org/onlinepubs/9699919799/utilities/V3_chap02.html#tag_18_06_02 + +## Don't add here. errors are expected. +[ "x${DEBUG+set}" = 'xset' ] && set -v +# set -u -e + +if [ ${EUID} -ne 0 ]; then + printf "This script must be run as root\n" + exit 1 +fi + +arch="unknown" +if [ "$(uname -i)" = "i686" ] || [ "$(uname -m)" = "i686" ]; then + arch="i686" +elif [ "$(uname -i)" = "x86_64" ] || [ "$(uname -m)" = "x86_64" ]; then + arch="x86_64" +else + printf "This script must be run on an i686 or x86_64 host. x86_64 is recommended.\n" + exit 1 +fi + +usage="usage: ./flash mode path/to/yourrom.rom" +availablemodes="update, forceupdate, i945lenovo_firstflash, i945lenovo_secondflash, i945apple_firstflash" + +mode="unknown" +rompath="unknown" + +# User specified no or too few/many parameters +if [ $# -lt 2 ]; then + printf "%s\n" "${usage}" + printf "You need to specify exactly one mode, and one file\n" + printf "%s\n" "${availablemodes}" + exit 1 +fi + +mode="${1}" +rompath="${2}" + +# User specified an invalid mode of operation +if [ "${mode}" != "update" ] && [ "${mode}" != "forceupdate" ] && [ "${mode}" != "i945lenovo_firstflash" ] && [ "${mode}" != "i945lenovo_secondflash" ] && [ "${mode}" != "i945apple_firstflash" ]; then + printf "%s\n" "${usage}" + printf "Invalid mode. Modes available: %s\n" "${availablemodes}" + exit 1 +else + printf "Mode selected: %s\n" "${mode}" +fi + +# The specified file does not exist +if [ ! -f "${rompath}" ]; then + printf "File not found!\n" + exit 1 +fi + +flashrom="unknown" +if [ -f "build" ]; then + # git or libreboot_src + flashrom="./flashrom/flashrom" +else + # libreboot_util + flashrom="./flashrom/${arch}/flashrom" +fi +if [ ! -f "${flashrom}" ]; then + printf "flashrom binary not present\n" + exit 1 +fi + +# i945 lenovobios +bucts="unknown" +flashrom_lenovobios_sst="unknown" +flashrom_lenovobios_macronix="unknown" +if [ "${mode}" = "i945lenovo_firstflash" ] || [ "${mode}" = "i945lenovo_secondflash" ]; then + if [ -f "build" ]; then + # git or libreboot_src + bucts="./bucts/bucts" + flashrom_lenovobios_sst="./flashrom/flashrom_lenovobios_sst" + flashrom_lenovobios_macronix="./flashrom/flashrom_lenovobios_macronix" + else + # libreboot_util + bucts="./bucts/${arch}/bucts" + flashrom_lenovobios_sst="./flashrom/${arch}/flashrom_lenovobios_sst" + flashrom_lenovobios_macronix="./flashrom/${arch}/flashrom_lenovobios_macronix" + fi + + # anti-bricking precaution + if [ ! -f "${bucts}" ]; then + printf "bucts binary not present. ABORTING so as to protect against bricking the system.\n" + exit 1 + fi + + # fail if flashrom is not present + if [ ! -f "${flashrom_lenovobios_sst}" ] || [ ! -f "${flashrom_lenovobios_macronix}" ]; then + printf "Flashrom binaries not present.\n" + exit 1 + fi +fi + +if [ "${mode}" = "update" ]; then + ${flashrom} -p internal -w "${rompath}" +elif [ "${mode}" = "forceupdate" ]; then + ${flashrom} -p internal:boardmismatch=force,laptop=force_I_want_a_brick -w "${rompath}" +elif [ "${mode}" = "i945apple_firstflash" ]; then + ${flashrom} -p internal:laptop=force_I_want_a_brick -w "${rompath}" +elif [ "${mode}" = "i945lenovo_firstflash" ]; then + ${bucts} 1 # needed to prevent bricks. + # One will fail (this is harmless), and the other will succeed. + ${flashrom_lenovobios_sst} -p internal -w "${rompath}" + ${flashrom_lenovobios_macronix} -p internal -w "${rompath}" +elif [ "${mode}" = "i945lenovo_secondflash" ]; then + ${flashrom} -p internal:laptop=force_I_want_a_brick -w "${rompath}" + ${bucts} 0 +fi + + diff --git a/i18n/fr_FR/libreboot b/i18n/fr_FR/libreboot new file mode 100755 index 00000000..b3c97f5d --- /dev/null +++ b/i18n/fr_FR/libreboot @@ -0,0 +1,271 @@ +#!/usr/bin/env bash + +# Copyright (C) 2016 Paul Kocialkowski +# Copyright (C) 2017 Andrew Robbins +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +GLOBIGNORE=".:.." # This enables the shell option 'dotglob' as well. +shopt -s nullglob extglob + +libreboot_usage() { + local action + local target + + printf '%s\n' "$executable [action] [target] [arguments]" + + printf '\n%s\n' 'Generic project actions:' + + for action in "${PROJECT_ACTIONS_GENERIC[@]}"; do + printf '%s\n' " $action" + done + + printf '\n%s\n' 'Virtual project actions:' + printf '%s\n' ' sources' + printf '%s\n' ' produce' + printf '%s\n' ' test' + + printf '\n%s\n' 'Project targets:' + + for target in "$root/$PROJECTS"/*; do + if project_check "$target"; then + printf '%s\n' " ${target##*/}" + fi + done + + printf '\n%s\n' 'Generic tool actions:' + + for action in "${TOOL_ACTIONS_GENERIC[@]}"; do + printf '%s\n' " $action" + done + + printf '\n%s\n' 'Tool targets:' + + for target in "$root/$TOOLS"/*; do + if tool_check "$target"; then + printf '%s\n' " ${target##*/}" + fi + done + + printf '\n%s\n' 'Environment variables:' + printf '%s\n' ' PROJECTS_FORCE - Projects to always perform actions for' + printf '%s\n' ' TOOLS_FORCE - Tools to always perform actions for' + printf '%s\n' ' RELEASE_KEY - GPG key to use for release' + printf '%s\n' ' VBOOT_KEYS_PATH - Path to the vboot keys' + printf '%s\n' ' LIBFAKETIME_PATH - Path to libfaketime' + printf '%s\n' ' TASKS - Number of simultaneous tasks to run' + printf '%s\n' ' VERSION - Version string to use' + + printf '\n%s\n' 'Configuration files:' + printf '%s\n' " $BUILD_SYSTEM.conf - Environment variables configuration" +} + +libreboot_project() { + action="$1" + shift + project="$1" + shift + + case "$action" in + 'sources') + if project_action_arguments 'extract' "$project" "$@"; then + return + else + printf 1>&2 '\n%s\n\n' 'Attempting to download instead...' + project_action_arguments 'download' "$project" "$@" + fi + ;; + 'produce') + for action in 'build' 'install' 'release'; do + project_action_arguments "$action" "$project" "$@" + done + ;; + 'test') + for action in "${PROJECT_ACTIONS[@]}"; do + project_action_arguments "$action" "$project" "$@" + done + ;; + *) + if ! project_function_check "$project" "$action"; then + libreboot_usage + exit 1 + elif [[ $action == usage ]]; then + project_action_usage "$project" "$@" + else + project_action_arguments "$action" "$project" "$@" + fi + ;; + esac +} + +libreboot_tool() { + action="$1" + shift + tool="$1" + shift + + if ! tool_function_check "$tool" "$action"; then + libreboot_usage + exit 1 + elif [[ "$action" == 'usage' ]]; then + tool_action "$action" "$tool" "$@" + else + tool_action_arguments_recursive "$action" "$tool" "$@" + fi +} + +libreboot_setup() { + root="$(readlink -f "$(dirname "$0")")" + executable="$(basename "$0")" + + libreboot_setup_include + libreboot_setup_tool_actions + libreboot_setup_project_actions + + requirements tar sed gpg sha256sum git mmd mcopy grep mkfs.fat + + libreboot_setup_variables +} + +libreboot_setup_include() { + local libs_path="$root/libs" + local conf_path + + source "$libs_path/project" + source "$libs_path/tool" + source "$libs_path/common" + source "$libs_path/git" + + conf_path="$root/$BUILD_SYSTEM.conf" + + if [[ -f "$conf_path" ]]; then + source "$conf_path" + fi +} + +libreboot_setup_tool_actions() { + local ignore="${TOOL_ACTIONS_GENERIC_IGNORE_CHECK[*]}" + + local -a tool_actions + + for ((i=0, nogeneric=${#TOOL_ACTIONS_GENERIC[@]}; i /dev/null || echo 'git')" + elif [[ -f "$version_path" ]]; then + VERSION="$(< "$version_path")" + else + VERSION="$BUILD_SYSTEM" + fi + fi + + if [[ -d "$vboot_tools_path/devkeys/" ]]; then + VBOOT_KEYS_PATH="${VBOOT_KEYS_PATH:-$vboot_tools_path/devkeys/}" + fi + + libreboot_setup_reproducible_builds_variables +} + +libreboot_setup_reproducible_builds_variables() { + local epoch_path="$root/$DOTEPOCH" + local rnd_seed_path="$root/$DOTRNDSEED" + + # Used by GCC, e.g., -frandom-seed="$RANDOM_SEED" + if [[ -z "$RANDOM_SEED" ]]; then + if [[ -f "$rnd_seed_path" ]]; then + RANDOM_SEED="$(< "$rnd_seed_path")" + else + RANDOM_SEED="$RANDOM" # True randomness is unnecessary + fi + + export RANDOM_SEED + fi + + # Also used by GCC, but as an environment variable + if [[ -z "$SOURCE_DATE_EPOCH" ]]; then + if git_check "$root"; then + SOURCE_DATE_EPOCH="$(git log -1 --format=%ct)" + elif [[ -f "$epoch_path" ]]; then + SOURCE_DATE_EPOCH="$(< "$epoch_path")" + else + SOURCE_DATE_EPOCH="$(date +%s)" + fi + + export SOURCE_DATE_EPOCH + fi + + # Relevant only when libfaketime path is given in $BUILD_SYSTEM.conf + if [[ -n "$LIBFAKETIME_PATH" ]]; then + BUILD_DATE_FMT="%Y-%m-%d %H:%M:%S" + BUILD_DATE="$(date -u -d "@$SOURCE_DATE_EPOCH" "+$BUILD_DATE_FMT" 2>/dev/null || date -u -r "$SOURCE_DATE_EPOCH" "+$BUILD_DATE_FMT" 2>/dev/null || date -u "+$BUILD_DATE_FMT")" + FAKETIME="@$BUILD_DATE" + LC_ALL='C.UTF-8' + LD_PRELOAD="$LIBFAKETIME_PATH" + TZ='UTC' + + export BUILD_DATE_FMT BUILD_DATE FAKETIME LC_ALL LD_PRELOAD TZ + fi +} + +libreboot() { + action="$1" + shift + target="$1" + shift + + set -e + + libreboot_setup "$@" + + if project_check "$target"; then + libreboot_project "$action" "$target" "$@" + elif tool_check "$target"; then + libreboot_tool "$action" "$target" "$@" + else + libreboot_usage + exit 1 + fi +} + +libreboot "$@" diff --git a/i18n/fr_FR/libs/common b/i18n/fr_FR/libs/common new file mode 100755 index 00000000..b1091e4f --- /dev/null +++ b/i18n/fr_FR/libs/common @@ -0,0 +1,441 @@ +#!/usr/bin/env bash + +# Copyright (C) 2016 Paul Kocialkowski +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +BUILD_SYSTEM="libreboot" + +PROJECTS="projects" +SOURCES="sources" +BUILD="build" +INSTALL="install" +RELEASE="release" +SYSTEMS="systems" +IMAGES="images" +TOOLS="tools" + +CONFIGS="configs" +PATCHES="patches" +TARGETS="targets" +REVISION="revision" +VARIANTS="variants" +BLOBS="blobs" +BLOBS_IGNORE="blobs-ignore" +BLOBS_DISCOVER="blobs-discover" +DEPENDENCIES="dependencies" + +DOTEPOCH=".epoch" +DOTRNDSEED=".rndseed" +DOTVERSION=".version" +DOTREVISION=".revision" +DOTTARFILES=".tarfiles" +ARCHIVE="tar.xz" +CHECKSUM="sha256sum" +DSIG="asc" + +CONFIG_SHELL="${CONFIG_SHELL:-$(which bash)}" +EDITOR="${EDITOR:-$(which vi || true)}" +TASKS="${TASKS:-1}" + +function_check() { + local function=$1 + + declare -f -F "$function" > /dev/null +} + +variable_check() { + local variable=$1 + + test ! -z "${!variable}" +} + +arguments_list() { + local argument + + for argument in "$@" + do + printf '%s\n' "$argument" + done +} + +download_wrapper() { + local download_dir="$1" + shift + local uris=($@) + + local wget_options=( + '--config=/dev/null' + '--secure-protocol=PFS' + "--directory-prefix=$download_dir" + '--continue' + '--' + ) + + local curl_options=( + '-q' + '--continue-at -' + '--remote-name' + '--retry 20' + '--ssl' + '--tlsv1.2' + '--' + ) + + if hash wget > /dev/null 2>&1; then + + wget "${wget_options[@]}" "${uris[@]}" + + elif hash curl > /dev/null 2>&1; then + ( + cd "$download_dir" + + curl "${curl_options[@]}" "${uris[@]}" + ) + else + printf '\n%s\n\n' 'Error: Neither wget nor curl were found' 1>&2 + + return 1 + fi +} + +diff_patch() { + local sources_path=$1 + local patch_path=$2 + + patch -fd "$sources_path" -r - < "$patch_path" +} + +diff_patch_check() { + local sources_path=$1 + local patch_path=$2 + + patch -sfd "$sources_path" --dry-run < "$patch_path" > /dev/null 2>&1 +} + +path_wildcard_expand() { + local path=$@ + + # Evaluation fails with unescaped whitespaces. + path=$(printf '%s\n' "$path" | sed "s/ /\\\ /g") + + eval "arguments_list "$path"" +} + +file_checksum_create() { + local path=$1 + + local checksum_path="$path.$CHECKSUM" + local name=$(basename "$path") + local directory_path=$(dirname "$path") + + ( + cd "$directory_path" + sha256sum "$name" > "$checksum_path" + ) +} + +file_checksum_check() { + local path=$1 + + local checksum_path="$path.$CHECKSUM" + local name=$(basename "$path") + local directory_path=$(dirname "$path") + + if ! [[ -f "$checksum_path" ]] + then + printf 1>&2 '%s\n' 'Could not verify file checksum!' + return 1 + fi + + ( + cd "$directory_path" + sha256sum -c "$checksum_path" + ) +} + +file_signature_create() { + local path=$1 + + local signature_path="$path.$DSIG" + + if [[ -z "$RELEASE_KEY" ]] + then + return 0 + fi + + gpg --default-key "$RELEASE_KEY" --armor --output "$signature_path" --detach-sign --yes "$path" +} + +file_signature_check() { + local path=$1 + + local signature_path="$path.$DSIG" + + if ! [[ -f "$signature_path" ]] + then + printf 1>&2 '%s\n' 'Could not verify file signature!' + return 1 + fi + + gpg --armor --verify "$signature_path" "$path" +} + +file_verification_create() { + local path=$1 + + file_checksum_create "$path" + file_signature_create "$path" +} + +file_verification_check() { + local path=$1 + + file_checksum_check "$path" + file_signature_check "$path" +} + +file_exists_check() { + local path=$1 + + test -f "$path" +} + +directory_filled_check() { + local path=$1 + + if [[ -z "$(ls -A "$path" 2> /dev/null)" ]] + then + return 1 + else + return 0 + fi +} + +archive_files_create() { + local source_path="$1" + + local directory="$(basename "$source_path")" + local tarfiles_path="$source_path/$DOTTARFILES" + local revision_path="$source_path/$DOTREVISION" + local version_path="$source_path/$DOTVERSION" + local epoch_path="$source_path/$DOTEPOCH" + local rnd_seed_path="$source_path/$DOTRNDSEED" + + # Files in "$tarfiles_path" are NUL terminated. + # `tr '\0' '\n'` for human-readable output. + if git_check "$source_path"; then + git_files "$source_path" > "$tarfiles_path" + printf '%s\0' "$DOTTARFILES" >> "$tarfiles_path" + else + find "$source_path" -print0 | env LC_ALL='C.UTF-8' sort -z | sed -z "1d;s,^$source_path/\\?,,;/^$DOTTARFILES\$/d" > "$tarfiles_path" + fi + + for dotfile in "$revision_path" \ + "$version_path" \ + "$epoch_path" \ + "$rnd_seed_path" + do + if [[ -f "$dotfile" ]]; then + printf '%s\0' ".${dotfile##*.}" >> "$tarfiles_path" + fi + done +} + +archive_files_date() { + local source_path="$1" + + local epoch_path="$source_path/$DOTEPOCH" + + if [[ -n "$SOURCE_DATE_EPOCH" ]]; then + find "$source_path" -execdir touch --no-dereference --date="@$SOURCE_DATE_EPOCH" {} + + fi +} + +archive_create() { + local archive_path="$1" + local source_path="$2" + local directory="$3" + + local tarfiles_path="$source_path/$DOTTARFILES" + local directory_path="$(dirname "$archive_path")" + + mkdir -p "$directory_path" + + if [[ -z "$directory" ]]; then + directory="$(basename "$source_path")" + fi + + archive_files_create "$source_path" + archive_files_date "$source_path" + + local tar_options=( + --create + --xz + --file="$archive_path" + --files-from="$tarfiles_path" + --transform="s,^,$directory/,S" + --no-recursion + --warning=no-filename-with-nuls + --null + --owner=0 + --group=0 + --numeric-owner + ) + + ( + cd "$source_path" + tar "${tar_options[@]}" + ) +} + +archive_extract() { + local archive_path="$1" + local destination_path="$2" + + if [[ -z "$destination_path" ]]; then + destination_path="$(dirname "$archive_path")" + fi + + tar -xf "$archive_path" -ps -C "$destination_path" +} + +rootfs_files_create() { + local source_path="$1" + + local directory="$(basename "$source_path")" + local tarfiles_path="$source_path/$DOTTARFILES" + + # Files in "$tarfiles_path" are NUL terminated. + # `tr '\0' '\n'` for human-readable output. + execute_root find "$source_path" -print0 | env LC_ALL='C.UTF-8' sort -z | sed -z "1d;s,^$source_path/\\?,,;/^$DOTTARFILES\$/d" > "$tarfiles_path" +} + +rootfs_files_date() { + local source_path="$1" + + local epoch_path="$source_path/$DOTEPOCH" + + if [[ -n "$SOURCE_DATE_EPOCH" ]]; then + execute_root find "$source_path" -execdir touch --no-dereference --date="@$SOURCE_DATE_EPOCH" {} + + fi +} + +rootfs_create() { + local rootfs_path="$1" + local source_path="$2" + local directory="$3" + + local tarfiles_path="$source_path/$DOTTARFILES" + local directory_path="$(dirname "$rootfs_path")" + + mkdir -p "$directory_path" + + if [[ -z "$directory" ]]; then + directory="$(basename "$source_path")" + fi + + rootfs_files_create "$source_path" + rootfs_files_date "$source_path" + + local tar_options=( + --create + --xz + --file="$rootfs_path" + --files-from="$tarfiles_path" + --no-recursion + --warning=no-filename-with-nuls + --null + --owner=0 + --group=0 + --numeric-owner + ) + + ( + cd "$source_path" + execute_root tar "${tar_options[@]}" + ) + + execute_root chmod 644 "$rootfs_path" + execute_root chown "$USER:$USER" "$rootfs_path" +} + +requirements() { + local requirement + local requirement_path + + for requirement in "$@" + do + requirement_path=$(which "$requirement" || true) + + if [[ -z "$requirement_path" ]] + then + printf 1>&2 '%s\n' "Missing requirement: $requirement" + exit 1 + fi + done +} + +requirements_root() { + local requirement + local requirement_path + + for requirement in "$@" + do + # We need to keep stdout output to show the command. + requirement_path=$(execute_root which "$requirement" || true) + + if [[ -z "$requirement_path" ]] + then + printf 1>&2 '%s\n' "Missing requirement: $requirement" + exit 1 + fi + done +} + +arguments_concat() { + local delimiter=$1 + shift + + local concat + + for argument in "$@" + do + if [[ -n "$concat" ]] + then + concat="$concat""$delimiter""$argument" + else + concat="$argument" + fi + done + + printf '%s\n' "$concat" +} + +execute_root() { + local sudo=$(which sudo 2> /dev/null || true) + local arguments + + printf 1>&2 '%s' 'Running command as root: ' + printf 1>&2 '%b\n' "$*" + + if [[ -n "$sudo" ]] + then + sudo "$@" + else + # Quote arguments for eval through su. + arguments=$(printf '%q ' "$@") + su -c "$arguments" + fi +} diff --git a/i18n/fr_FR/libs/git b/i18n/fr_FR/libs/git new file mode 100755 index 00000000..2cde3dd3 --- /dev/null +++ b/i18n/fr_FR/libs/git @@ -0,0 +1,614 @@ +#!/usr/bin/env bash + +# Copyright (C) 2016 Paul Kocialkowski +# Copyright (C) 2019 Andrew Robbins +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +BRANCH_PREFIX="libreboot-" +DOTGIT=".git" +HEAD="HEAD" +ORIGIN_HEAD="origin/HEAD" +WILDDOTPATCH="*.patch" +GIT_NAME="Libreboot" +GIT_EMAIL="libreboot@libreboot.org" + +git_check() { + local repository_path=$1 + + directory_filled_check "$repository_path/$DOTGIT" +} + +git_clone() { + local repository_path=$1 + local url=$2 + + git clone "$url" "$repository_path" +} + +git_submodule_update() { + local repository_path=$1 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git submodule update --init + ) +} + +git_merge() { + local repository_path=$1 + local revision=$2 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git merge "$revision" + ) +} + +git_branch_create() { + local repository_path=$1 + local branch=$2 + local revision=$3 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git checkout -B "$branch" + + if [[ -n "$revision" ]] + then + git reset --hard "$revision" + fi + ) +} + +git_branch_delete() { + local repository_path=$1 + local branch=$2 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git branch -D "$branch" + ) +} + +git_branch_checkout() { + local repository_path=$1 + local branch=$2 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git checkout "$branch" > /dev/null + ) +} + +git_branch_check() { + local repository_path=$1 + local branch=$2 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git rev-parse --verify "$branch" >/dev/null 2>&1 + ) +} + +git_fetch() { + local repository_path=$1 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git fetch origin + ) +} + +git_fetch_check() { + local repository_path=$1 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git fetch --dry-run origin >/dev/null 2>&1 + ) +} + +git_clean() { + local repository_path=$1 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git clean -df + ) +} + +git_remove() { + local repository_path=$1 + local path=$2 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git rm -rf "$path" + ) +} + +git_diff_staged_check() { + local repository_path=$1 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git diff --staged --quiet + ) +} + +git_diff_check() { + local repository_path=$1 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git diff --quiet + ) +} + +git_commit() { + local repository_path=$1 + local message=$2 + + ( + export GIT_COMMITTER_NAME=$GIT_NAME + export GIT_COMMITTER_EMAIL=$GIT_EMAIL + + cd "$repository_path" 2>/dev/null || exit 1 + + git commit --author="$GIT_NAME <$GIT_EMAIL>" -m "$message" + ) +} + +git_am() { + local repository_path=$1 + local branch=$2 + local patch=$3 + + ( + export GIT_COMMITTER_NAME=$GIT_NAME + export GIT_COMMITTER_EMAIL=$GIT_EMAIL + + cd "$repository_path" 2>/dev/null || exit 1 + + git checkout "$branch" >/dev/null 2>&1 + + if ! git am "$patch"; then + git am --abort + + exit 1 + fi + ) +} + +git_apply() { + local repository_path=$1 + local branch=$2 + local patch=$3 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git checkout "$branch" >/dev/null 2>&1 + git apply --index "$patch" + ) +} + +git_apply_check() { + local repository_path=$1 + local branch=$2 + local patch=$3 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git checkout "$branch" >/dev/null 2>&1 + git apply --check "$patch" + ) +} + +git_patch() { + local repository_path=$1 + local branch=$2 + local patch=$3 + + git_apply_check "$repository_path" "$branch" "$patch" || return 1 + + case $patch in + *.patch) + git_am "$repository_path" "$branch" "$patch" + ;; + *.diff) + git_apply "$repository_path" "$branch" "$patch" + git_commit "$repository_path" "Applied ${patch##*/}" + ;; + *) + ;; + esac +} + +git_revision() { + local repository_path=$1 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git rev-parse "$HEAD" + ) +} + +git_describe() { + local repository_path=$1 + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git describe --tags + ) +} + +git_files() { + local repository_path="$1" + + ( + cd "$repository_path" 2>/dev/null || exit 1 + + git ls-files -z | sort -z + ) +} + +git_project_repository_path() { + local repository=$1 + + printf '%s\n' "$root/$SOURCES/$repository" +} + +git_project_check() { + local repository=$1 + + local repository_path=$(git_project_repository_path "$repository") + + git_check "$repository_path" +} + +git_project_patch_recursive() { + local project=$1 + local repository=$2 + local branch=$3 + local path=$4 + + local repository_path=$(git_project_repository_path "$repository") + local project_path=$(project_path "$project") + local patches_path=$project_path/$PATCHES/$path + + if ! [[ -d $project_path/$PATCHES ]]; then + return 0 + fi + + for patch in "$patches_path"/[!.]*.@(patch|diff); do + git_patch "$repository_path" "$branch" "$patch" || return 1 + done + + if [[ -n $path && $path != . ]]; then + git_project_patch_recursive "$project" "$repository" "$branch" "$(dirname "$path")" + fi +} + +git_project_clone() { + local repository=$1 + shift + local urls=$@ + + local repository_path=$(git_project_repository_path "$repository") + local directory_path=$(dirname "$repository_path") + local url + + mkdir -p "$directory_path" + + ( + set +e + + for url in $urls + do + if git_clone "$repository_path" "$url" + then + return 0 + fi + done + + return 1 + ) +} + +git_project_prepare() { + local project=$1 + shift + local repository=$1 + shift + + git_project_prepare_revision "$project" "$repository" "$@" + git_project_prepare_blobs "$project" "$repository" "$@" + git_project_prepare_patch "$project" "$repository" "$@" +} + +git_project_prepare_blobs() { + local project=$1 + shift + local repository=$1 + shift + + local repository_path=$(git_project_repository_path "$repository") + local blob + + while read -r blob + do + git_remove "$repository_path" "$blob" + done < <(project_blobs "$project" "$@") + + if ! git_diff_staged_check "$repository_path" + then + git_commit "$repository_path" "Removed blobs" + fi +} + +git_project_prepare_patch() { + local project=$1 + shift + local repository=$1 + shift + + local branch=$project + local argument + local path + + for argument in "$@" + do + if [[ -z "$path" ]] + then + path="$argument" + else + path="$path/$argument" + fi + + branch="$branch-$argument" + done + + if [[ -n $branch ]] + then + local prepare_branch=$BRANCH_PREFIX$branch + local prepare_path=$path + + git_project_patch_recursive "$project" "$repository" "$prepare_branch" "$prepare_path" + fi +} + +git_project_prepare_revision() { + local project=$1 + shift + local repository=$1 + shift + + local repository_path=$(git_project_repository_path "$repository") + local project_path=$(project_path "$project") + local configs_path="$project_path/$CONFIGS" + local branch=$project + local prepare_revision + local argument + local path + + for argument in "" "$@" + do + if [[ -n $argument ]] + then + if [[ -z $path ]] + then + path="$argument" + else + path="$path/$argument" + fi + + branch="$branch-$argument" + fi + + local revision_path="$configs_path/$path/$REVISION" + + if [[ -f $revision_path ]]; then + prepare_revision=$(< "$revision_path") + fi + done + + if [[ -n $branch ]] + then + local prepare_branch=$BRANCH_PREFIX$branch + + git_branch_create "$repository_path" "$prepare_branch" "$prepare_revision" + fi +} + +git_project_prepare_check() { + local project=$1 + shift + local repository=$1 + shift + + local repository_path=$(git_project_repository_path "$repository") + local branch=$project + local argument + + for argument in "$@" + do + branch="$branch-$argument" + done + + if [[ -n $branch ]] + then + local prepare_branch=$BRANCH_PREFIX$branch + + git_branch_check "$repository_path" "$prepare_branch" + fi +} + +git_project_prepare_clean() { + local project=$1 + shift + local repository=$1 + shift + + local repository_path=$(git_project_repository_path "$repository") + local branch=$project + local argument + + for argument in "$@" + do + branch="$branch-$argument" + done + + if [[ -n $branch ]] + then + local prepare_branch=$BRANCH_PREFIX$branch + + if git_branch_check "$repository_path" "$prepare_branch" + then + git_branch_delete "$repository_path" "$prepare_branch" + fi + fi +} + +git_project_checkout() { + local project=$1 + shift + local repository=$1 + shift + + local repository_path=$(git_project_repository_path "$repository") + local branch=$project + local argument + + for argument in "$@" + do + branch="$branch-$argument" + done + + if [[ -n $branch ]] + then + local checkout_branch=$BRANCH_PREFIX$branch + + if git_branch_check "$repository_path" "$checkout_branch" + then + git_branch_checkout "$repository_path" "$checkout_branch" + git_submodule_update "$repository_path" + fi + fi +} + +git_project_update() { + local project=$1 + shift + local repository=$1 + shift + + local repository_path=$(git_project_repository_path "$repository") + + git_fetch "$repository_path" + git_branch_checkout "$repository_path" "$ORIGIN_HEAD" + + git_project_prepare_clean "$project" "$repository" "$@" + git_project_prepare "$project" "$repository" "$@" +} + +git_project_update_check() { + local project=$1 + shift + local repository=$1 + shift + + git_project_prepare_check "$project" "$repository" "$@" + + git_fetch_check "$repository_path" +} + +git_project_release() { + local project=$1 + shift + local repository=$1 + shift + + local repository_path=$(git_project_repository_path "$repository") + local branch=$project + local argument + + for argument in "$@" + do + branch="$branch-$argument" + done + + if [[ -n $branch ]] + then + local release_branch=$BRANCH_PREFIX$branch + + if git_branch_check "$repository_path" "$release_branch" + then + local archive_path="$root/$RELEASE/$SOURCES/$project/$release_branch.$ARCHIVE" + local sources_path="$root/$SOURCES/$repository" + + printf '%s\n' "Releasing sources archive for $project (with ${arguments:-no argument}) from "$repository" git" + + git_branch_checkout "$repository_path" "$release_branch" + git_submodule_update "$repository_path" + git_clean "$repository_path" + archive_create "$archive_path" "$sources_path" "$release_branch" + file_verification_create "$archive_path" + fi + fi +} + +git_project_release_check() { + local project=$1 + shift + local repository=$1 + shift + + local repository_path=$(git_project_repository_path "$repository") + local branch=$project + local argument + + for argument in "$@" + do + branch="$branch-$argument" + done + + if [[ -n $branch ]] + then + local release_branch=$BRANCH_PREFIX$branch + + if git_branch_check "$repository_path" "$release_branch" + then + local archive_path="$root/$RELEASE/$SOURCES/$project/$release_branch.$ARCHIVE" + + file_exists_check "$archive_path" + fi + fi +} diff --git a/i18n/fr_FR/libs/project b/i18n/fr_FR/libs/project new file mode 100755 index 00000000..d884556d --- /dev/null +++ b/i18n/fr_FR/libs/project @@ -0,0 +1,1712 @@ +#!/usr/bin/env bash + +# Copyright (C) 2016 Paul Kocialkowski +# Copyright (C) 2018,2019 Andrew Robbins +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +PROJECT_ACTIONS_GENERIC=(usage dependencies download extract update build install release clean) +PROJECT_ACTIONS_GENERIC_IGNORE_CHECK=(usage clean) +PROJECT_ACTIONS_HELPERS=(arguments dependencies) + +INSTALL_REGEX='\([^:]*\):\(.*\)' + +project_include() { + local project=$1 + + local project_path=$(project_path "$project") + + unset -f "${PROJECT_ACTIONS[@]}" + + source "$project_path/$project" + + project_helper_include "$project" +} + +project_helper_include() { + local project=$1 + + local project_path=$(project_path "$project") + local include="$project_path/$project-helper" + + if [[ -f "$include" ]] + then + source "$include" + fi +} + +project_check() { + local project="${1##*/}" + + local project_path="$(project_path "$project")" + + if ! [[ -f "$project_path/$project" ]]; then + return 1 + fi +} + +project_dependencies() { + local project=$1 + shift + + if [[ -n "${PROJECTS_FORCE[*]}" ]]; then + local expanded + local project_force + + for project_force in "${PROJECTS_FORCE[@]}"; do + project_arguments_expand_recursive $project_force | while IFS='' read -r expanded; do + project_dependencies_sort $expanded + done + done + fi + + project_dependencies_sort "$project" "$@" | head -n -1 +} + +project_dependencies_collect() { + local project=$1 + shift + + local argument + local path + + for argument in "" "$@"; do + if [[ -z $argument ]]; then + path=$CONFIGS + else + path=$path/$argument + fi + + project_file_contents "$project" "$path" "$DEPENDENCIES" + done + + project_dependencies_collect_recursive "$project" "$@" +} + +project_dependencies_collect_recursive() { + local project=$1 + shift + + local argument + local path + + for argument in "" "$@"; do + if [[ -z $argument ]]; then + path=$CONFIGS + else + path=$path/$argument + fi + done + + project_action_helper arguments "$project" "$@" | while IFS='' read -r argument; do + project_file_contents "$project" "$path/$argument" "$DEPENDENCIES" + project_dependencies_collect_recursive "$project" "$@" "$argument" + done +} + +project_dependencies_encode_recursive() { + local project=$1 + shift + + local project_arguments=$(arguments_concat ' ' "$project" "$@") + local project_arguments_encoded=$(base64 -w0 <<< "$project_arguments") + + local dependency + + project_dependencies_collect "$project" "$@" | while IFS='' read -r dependency; do + local dependency_arguments=$(arguments_concat ' ' $dependency) + local dependency_arguments_encoded=$(base64 -w0 <<< "$dependency_arguments") + + printf '%s\n' "$project_arguments_encoded $dependency_arguments_encoded" + + project_dependencies_encode_recursive $dependency + done +} + +project_dependencies_sort() { + local project=$1 + shift + + ( + set -o pipefail + + project_dependencies_encode_recursive "$project" "$@" | tsort | base64 -d -w0 | tac + ) +} + +project_dependencies_check() { + local project=$1 + shift + + local dependency + local -i missing=0 + + project_dependencies "$project" "$@" | while read -r dependency; do + project_check $dependency || let ++missing + done + + return $missing +} + +project_dependencies_sources_check() { + local project=$1 + shift + + local dependency + local -i missing=0 + + project_dependencies "$project" "$@" | while read -r dependency; do + project_sources_directory_filled_check $dependency || let ++missing + done + + return $missing +} + +project_dependencies_action_arguments() { + local action=$1 + local project=$2 + shift 2 + + local -a dependency + + project_dependencies "$project" "$@" | while read -ra dependency; do + if project_function_check "${dependency[0]}" "$action"; then + project_action_arguments "$action" "${dependency[@]}" + fi + done +} + +project_function_check() { + local project=$1 + local function=$2 + + ( + project_include "$project" + + if ! function_check "$function"; then + exit 1 + fi + ) +} + +project_action() { + local action="$1" + shift + local project="$1" + shift + local arguments="$*" + + if project_action_check "$action" "$project" "$@"; then + return 0 + fi + + ( + set +e + + printf '%s\n' "Project $project $action (with ${arguments:-no argument})" + + ( + set -e + + "$action" "$@" + ) + + local -i exit_status=$? + + if ((exit_status)); then + printf 1>&2 '%s\n' "Project $project $action (with ${arguments:-no argument}) failed" + else + printf '%s\n' "Project $project $action (with ${arguments:-no argument}) completed" + fi + + exit $exit_status + ) + +} + +project_action_check() { + local action="$1" + shift + local project="$1" + shift + + ( + set +e + + if ! function_check "${action}_check"; then + return 1 + fi + + for project_force in $PROJECTS_FORCE; do + if [[ "$project_force" == "$project" ]]; then + return 1 + fi + done + + ( + set -e + "${action}_check" "$@" + ) + ) +} + +project_action_helper() { + local helper="$1" + shift + local project="$1" + shift + + ( + project_include "$project" + + if ! function_check "$helper"; then + exit 0 + fi + + "$helper" "$@" + ) +} + +project_action_arguments() { + local action="$1" + shift + local project="$1" + shift + + ( + project_include "$project" + + project_action_arguments_verify_recursive "$action" "$project" "$@" + project_action_arguments_recursive "$action" "$project" "$@" + ) +} + +project_action_arguments_verify_recursive() { + local action="$1" + shift + local project="$1" + shift + + local action_helper_arguments + + # Store final argument. + local argument="${*:$#}" + + local test + + if [[ "$#" -gt 1 ]]; then + # Set previous arguments. + set "${@:1:$#-1}" + elif [[ "$#" -eq 1 ]]; then + shift + else + return 0 + fi + + action_helper_arguments="$(project_action_helper 'arguments' "$project" "$@")" + + if [[ -n "$action_helper_arguments" ]]; then + test="$(printf '%s\n' "$action_helper_arguments" | grep -e "^$argument\$" || true)" + + if [[ -z "$test" ]]; then + printf 1>&2 '%s\n' "Invalid argument $argument for project $project action $action" + return 1 + fi + fi + + project_action_arguments_verify_recursive "$action" "$project" "$@" +} + +project_action_arguments_recursive() { + local action="$1" + shift + local project="$1" + shift + + local action_helper_arguments + local argument + + action_helper_arguments="$(project_action_helper 'arguments' "$project" "$@" || true)" + + if [[ -z "$action_helper_arguments" ]]; then + project_action "$action" "$project" "$@" + else + # This is to allow space characters in arguments. + local ifs_save="$IFS" + local IFS=$'\n' + + for argument in $(printf '%s\n' "$action_helper_arguments") + do + IFS="$ifs_save" + + # Only a single argument at a time is returned by the helper. + project_action_arguments_recursive "$action" "$project" "$@" "$argument" + done + fi +} + +project_action_projects() { + local action="$1" + shift + local project="$1" + shift + + local project_path="$(project_path "$project")" + local project_projects_path="$project_path/$CONFIGS/$PROJECTS" + local project_projects_action_path="$project_path/$CONFIGS/$PROJECTS-$action" + local arguments + local path + + if [[ -f "$project_projects_action_path" ]]; then + path="$project_projects_action_path" + else + path="$project_projects_path" + fi + + # Multiple arguments can be read from the file. + while read -r arguments; do + eval "project_action_arguments $action $arguments" + done < "$path" +} + +project_action_usage() { + local project=$1 + shift + + ( + project_include "$project" + + project_action usage "$project" "$@" + ) +} + +project_path() { + local project=$1 + + local project_path="$root/$PROJECTS/$project" + + printf '%s\n' "$project_path" +} + +project_sources_path() { + local project=$1 + shift + local repository=$1 + shift + + local sources_path + local argument + local path + + # Check downloaded and extracted sources first, using "$project." + path="$root/$SOURCES/$project" + + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + path="$path-$argument" + fi + + if ! directory_filled_check "$path" + then + continue + fi + + sources_path=$path + done + + if [[ -n "$sources_path" ]] + then + printf '%s\n' "$sources_path" + return + fi + + # Check downloaded sources then, using "$repository." + path="$root/$SOURCES/$repository" + + if directory_filled_check "$path" + then + printf '%s\n' "$path" + return + fi + + # Check project sources finally, using "$project." + path="$root/$PROJECTS/$project/$SOURCES" + + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + path="$path/$argument" + fi + + if ! directory_filled_check "$path" + then + continue + fi + + sources_path=$path + done + + if [[ -n "$sources_path" ]] + then + printf '%s\n' "$sources_path" + return + fi +} + +project_sources_directory_filled_check() { + local project=$1 + shift + + local sources_path=$(project_sources_path "$project" "$@") + + test ! -z "$sources_path" +} + +project_sources_directory_filled_error() { + local project=$1 + shift + local arguments="$*" + + local sources_path=$(project_sources_path "$project" "$@") + + if [[ -n "$sources_path" ]] + then + printf 1>&2 '%s\n' "Sources directory for project $project (with ${arguments:-no argument}) already exists" + return 1 + else + return 0 + fi +} + +project_sources_directory_missing_empty_error() { + local project=$1 + shift + local arguments="$*" + + local sources_path=$(project_sources_path "$project" "$@") + + if [[ -z "$sources_path" ]] + then + printf 1>&2 '%s\n' "Sources directory for project $project (with ${arguments:-no argument}) missing or empty" + return 1 + else + return 0 + fi +} + +project_sources_archive() { + local project=$1 + shift + + local sources_archive + local argument + local path="$root/$SOURCES/$project" + + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + path="$path-$argument" + fi + + local archive="$path.$ARCHIVE" + + if ! [[ -f "$archive" ]] + then + continue + fi + + sources_archive=$archive + done + + if [[ -n "$sources_archive" ]] + then + printf '%s\n' "$sources_archive" + fi +} + +project_sources_archive_extract() { + local project=$1 + shift + local arguments="$*" + + local archive=$(project_sources_archive "$project" "$@") + local destination=$(dirname "$archive") + + printf '%s\n' "Extracting source archive for $project (with ${arguments:-no argument})" + + file_verification_check "$archive" + archive_extract "$archive" "$destination" +} + +project_sources_archive_update() { + local project=$1 + shift + local arguments="$*" + + local repository=$project + local sources_path=$(project_sources_path "$project" "$repository" "$@") + local archive=$(project_sources_archive "$project" "$@") + local destination=$(dirname "$archive") + + if [[ -d "$sources_path" ]] + then + rm -rf "$sources_path" + fi + + printf '%s\n' "Extracting source archive for $project (with ${arguments:-no argument})" + + file_verification_check "$archive" + archive_extract "$archive" "$destination" +} + +project_sources_archive_missing_error() { + local project=$1 + shift + local arguments="$*" + + local archive=$(project_sources_archive "$project" "$@") + if [[ -z "$archive" ]] || ! [[ -f "$archive" ]] + then + printf 1>&2 '%s\n' "Missing sources archive for $project (with ${arguments:-no argument})" + return 1 + else + return 0 + fi +} + +project_sources_archive_missing_check() { + local project=$1 + shift + + local archive=$(project_sources_archive "$project" "$@") + if [[ -z "$archive" ]] || ! [[ -f "$archive" ]] + then + return 0 + else + return 1 + fi +} + +project_sources_prepare() { + local project="$1" + shift + + project_sources_prepare_blobs "$project" "$@" + project_sources_prepare_patch "$project" "$@" +} + +project_sources_prepare_blobs() { + local project=$1 + shift + + local sources_path=$(project_sources_path "$project" "$project" "$@") + + ( + cd "$sources_path" || exit 1 + + project_blobs "$project" "$@" | while IFS='' read -r blob; do + rm -f -- "$blob" + done + ) +} + +project_sources_prepare_patch() { + local project="$1" + shift + + local argument + local path + + for argument in "$@"; do + if [[ -z $path ]]; then + path=$argument + else + path=$path/$argument + fi + done + + if [[ -n $project ]]; then + project_sources_patch_recursive "$project" "$path" + fi +} + +project_sources_prepare_check() { + local project=$1 + shift + + local sources_path=$(project_sources_path "$project" "$project" "$@") + + directory_filled_check "$sources_path" +} + +project_sources_patch_recursive() { + local project=$1 + local path=$2 + + local project_path=$(project_path "$project") + local sources_path=$(project_sources_path "$project" "$project" "$@") + local patches_path=$project_path/$PATCHES/$path + + if ! [[ -d $project_path/$PATCHES ]]; then + return 0 + fi + + for patch in "$patches_path"/[!.]*.@(patch|diff); do + project_sources_patch "$sources_path" "$patch" || return 1 + done + + if [[ -n $path && $path != . ]]; then + project_sources_patch_recursive "$project" "$(dirname "$path")" + fi +} + +project_blobs() { + local project=$1 + shift + + local blobs_path=$(project_blobs_path "$project" "$@") + local blobs_ignore_path=$(project_blobs_ignore_path "$project" "$@") + + if [[ -n $blobs_path ]]; then + if [[ -n $blobs_ignore_path ]]; then + comm -23 <(sort "$blobs_path") <(sort "$blobs_ignore_path") + else + cat "$blobs_path" + fi + fi +} + +project_sources_patch() { + local sources_path=$1 + local patch_path=$2 + + if diff_patch_check "$sources_path" "$patch_path"; then + diff_patch "$sources_path" "$patch_path" + else + return 1 + fi +} + +project_blobs_path() { + local project=$1 + shift + + local project_path=$(project_path "$project") + local configs_path="$project_path/$CONFIGS" + local argument + local path + + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + if [[ -z "$path" ]] + then + path="$argument" + else + path="$path/$argument" + fi + fi + + local blobs_path="$configs_path/$path/$BLOBS" + + if [[ -f "$blobs_path" ]] + then + printf '%s\n' "$blobs_path" + return + fi + done +} + +project_blobs_ignore_path() { + local project=$1 + shift + + local project_path=$(project_path "$project") + local configs_path="$project_path/$CONFIGS" + local argument + local path + + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + if [[ -z "$path" ]] + then + path="$argument" + else + path="$path/$argument" + fi + fi + + blobs_ignore_path="$configs_path/$path/$BLOBS_IGNORE" + + if [[ -f "$blobs_ignore_path" ]] + then + printf '%s\n' "$blobs_ignore_path" + return + fi + done +} + +project_arguments_targets() { + local project=$1 + shift + + local project_path=$(project_path "$project") + local targets_path="$project_path/$CONFIGS" + local argument + + for argument in "$@" + do + targets_path="$targets_path/$argument" + done + + targets_path="$targets_path/$TARGETS" + + if [[ -f "$targets_path" ]] + then + cat "$targets_path" + fi +} + +project_arguments_expand_recursive() { + local project=$1 + shift + + local -a arguments + readarray -t arguments < <(project_action_helper arguments "$project" "$@") + + if [[ -z "${arguments[*]}" ]]; then + echo "$project" "$@" + + return 0 + fi + + local argument + + for argument in "${arguments[@]}"; do + project_arguments_expand_recursive "$project" "$@" "$argument" + done +} + +project_usage_actions() { + local project="$1" + shift + + printf '\n%s\n' 'Generic actions:' + + ( + for action in "${PROJECT_ACTIONS_GENERIC[@]}"; do + if function_check "$action"; then + printf '%s\n' " $action" + fi + done + ) + + if [[ "$#" -gt 0 ]]; then + printf '\n%s\n' 'Specific actions:' + + ( + for action in "$@"; do + printf '%s\n' " $action" + done + ) + fi +} + +project_usage_arguments() { + local project="$1" + shift + + printf '\n%s\n' 'Arguments:' + + project_usage_arguments_recursive "$project" ' ' "$@" +} + +project_usage_arguments_recursive() { + local project="$1" + shift + local spacing="$1" + shift + + local action_helper_arguments + local argument + + action_helper_arguments="$(project_action_helper 'arguments' "$project" "$@")" + + if [[ -n "$action_helper_arguments" ]]; then + for argument in $action_helper_arguments; do + printf '%s\n' "$spacing$argument" + project_usage_arguments_recursive "$project" " $spacing" "$@" "$argument" + done + fi +} + +project_download_git() { + local project=$1 + shift + local repository=$1 + shift + local urls=$1 + shift + + requirements "git" + + if ! git_project_check "$repository" + then + project_sources_directory_filled_error "$project" "$repository" "$@" + + git_project_clone "$repository" "$urls" + fi + + git_project_prepare "$project" "$repository" "$@" +} + +project_download_check_git() { + local project=$1 + shift + local repository=$1 + shift + + requirements "git" + + git_project_check "$repository" + git_project_prepare_check "$project" "$repository" "$@" +} + +project_download_archive() { + local project="$1" + shift + local archive_uri="$1" + shift + local archive_dsig_uri="$1" + + local archive="${archive_uri##*/}" + local compress_fmt="${archive##*.tar}" + + local directory_prefix="$root/$SOURCES" + local archive_path="$root/$SOURCES/$archive" + local sources_path="$root/$SOURCES/$project" + + if [[ "${compress_fmt#*.}" != "${ARCHIVE#*.}" ]]; then + ARCHIVE="tar$compress_fmt" + fi + + # TODO: Split this code block into separate functions + # Archive verification will be included at that point in time + if ! project_sources_directory_filled_check "$project"; then + download_wrapper "$directory_prefix" "$archive_uri" "$archive_dsig_uri" + archive_extract "$archive_path" "$directory_prefix" + + mv "${archive_path%.tar*}" "$sources_path" + fi + + project_sources_prepare "$project" +} + +project_download_check_archive() { + local project="$1" + local sources_path="$2" + + # TODO: Write the following function + #project_sources_archive_extract_check "$project" "$sources_path" +} + +project_extract() { + local project=$1 + shift + + local repository=$project + + if ! project_sources_directory_filled_check "$project" "$repository" "$@" + then + project_sources_archive_missing_error "$project" "$@" || return 1 + project_sources_archive_extract "$project" "$@" + fi +} + +project_extract_check() { + local project=$1 + shift + + local repository=$project + + project_sources_directory_filled_check "$project" "$repository" "$@" +} + +project_update_git() { + local project=$1 + shift + local repository=$1 + shift + + requirements "git" + + project_sources_directory_missing_empty_error "$project" "$repository" "$@" + + if git_project_check "$repository" + then + git_project_update "$project" "$repository" "$@" + else + if ! project_sources_archive_missing_check "$project" "$@" + then + project_sources_archive_update "$project" "$@" + fi + fi +} + +project_update_check_git() { + local project=$1 + shift + local repository=$1 + shift + + requirements "git" + + if git_project_check "$repository" + then + # Git repository should always be updated (even if upstream didn't progress). + # For instance, this is useful for testing new versions of patches without changing revision. + return 1 + else + project_sources_archive_missing_check "$project" "$@" + fi +} + +project_build_check() { + local project=$1 + shift + + local project_path=$(project_path "$project") + local build_path=$(project_build_path "$project" "$@") + local source_file_path + local argument + local rule + local path + + if ! [[ -d $build_path ]] + then + return 1 + fi + + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + if [[ -z "$path" ]] + then + path="$argument" + else + path="$path/$argument" + fi + fi + + configs_install_path="$project_path/$CONFIGS/$path/$INSTALL" + + if ! [[ -f "$configs_install_path" ]] + then + continue + fi + + while read -r rule + do + source=$(printf '%s\n' "$rule" | sed "s/$INSTALL_REGEX/\\1/g") + source_path="$build_path/$source" + + # Source may contain a wildcard. + path_wildcard_expand "$source_path" | while read -r source_file_path + do + if ! [[ -f "$source_file_path" ]] && ! [[ -d "$source_file_path" ]] + then + return 1 + fi + done + done < "$configs_install_path" + done +} + +project_build_path() { + local project=$1 + shift + + local build_path="$root/$BUILD/$project" + local argument + + for argument in "$@" + do + build_path="$build_path-$argument" + done + + printf '%s\n' "$build_path" +} + +project_build_directory_missing_empty_error() { + local project=$1 + shift + local arguments="$*" + + local build_path=$(project_build_path "$project" "$@") + + if ! directory_filled_check "$build_path" + then + printf 1>&2 '%s\n' "Build directory for project $project (with ${arguments:-no argument}) missing or empty" + return 1 + else + return 0 + fi +} + +project_install() { + local project=$1 + shift + + local project_path=$(project_path "$project") + local build_path=$(project_build_path "$project" "$@") + local install_path=$(project_install_path "$project" "$@") + local source_file_path + local argument + local rule + local path + + # Install built files first. + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + if [[ -z "$path" ]] + then + path="$argument" + else + path="$path/$argument" + fi + fi + + configs_install_path="$project_path/$CONFIGS/$path/$INSTALL" + + if ! [[ -f "$configs_install_path" ]] + then + continue + fi + + project_build_directory_missing_empty_error "$project" "$@" + + while read -r rule + do + source=$(printf '%s\n' "$rule" | sed "s/$INSTALL_REGEX/\\1/g") + source_path="$build_path/$source" + + destination=$(printf '%s\n' "$rule" | sed "s/$INSTALL_REGEX/\\2/g") + destination_path="$install_path/$destination" + destination_directory_path=$(dirname "$destination_path") + + mkdir -p "$destination_directory_path" + + # Source may contain a wildcard. + path_wildcard_expand "$source_path" | while read -r source_file_path + do + cp -rT "$source_file_path" "$destination_path" + done + done < "$configs_install_path" + done + + path="" + + # Install install files then. + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + if [[ -z "$path" ]] + then + path="$argument" + else + path="$path/$argument" + fi + fi + + install_install_path="$project_path/$INSTALL/$path/$INSTALL" + + if ! [[ -f "$install_install_path" ]] + then + continue + fi + + while read -r rule + do + source=$(printf '%s\n' "$rule" | sed "s/$INSTALL_REGEX/\\1/g") + source_path="$project_path/$INSTALL/$path/$source" + + destination=$(printf '%s\n' "$rule" | sed "s/$INSTALL_REGEX/\\2/g") + destination_path="$install_path/$destination" + destination_directory_path=$(dirname "$destination_path") + + mkdir -p "$destination_directory_path" + + # Source may contain a wildcard. + path_wildcard_expand "$source_path" | while read -r source_file_path + do + cp -rT "$source_file_path" "$destination_path" + done + done < "$install_install_path" + done +} + +project_install_check() { + local project=$1 + shift + + local project_path=$(project_path "$project") + local build_path=$(project_build_path "$project" "$@") + local install_path=$(project_install_path "$project" "$@") + local argument + local rule + local path + + if ! [[ -d $install_path ]] + then + return 1 + fi + + # Install built files first. + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + if [[ -z "$path" ]] + then + path="$argument" + else + path="$path/$argument" + fi + fi + + configs_install_path="$project_path/$CONFIGS/$path/$INSTALL" + + if ! [[ -f "$configs_install_path" ]] + then + continue + fi + + project_build_directory_missing_empty_error "$project" "$@" + + while read -r rule + do + destination=$(printf '%s\n' "$rule" | sed "s/$INSTALL_REGEX/\\2/g") + destination_path="$install_path/$destination" + + if ! [[ -f "$destination_path" ]] && ! [[ -d "$destination_path" ]] + then + return 1 + fi + done < "$configs_install_path" + done + + path="" + + # Install install files then. + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + if [[ -z "$path" ]] + then + path="$argument" + else + path="$path/$argument" + fi + fi + + install_install_path="$project_path/$INSTALL/$path/$INSTALL" + + if ! [[ -f "$install_install_path" ]] + then + continue + fi + + while read -r rule + do + destination=$(printf '%s\n' "$rule" | sed "s/$INSTALL_REGEX/\\2/g") + destination_path="$install_path/$destination" + + if ! [[ -f "$destination_path" ]] && ! [[ -d "$destination_path" ]] + then + return 1 + fi + done < "$install_install_path" + done +} + +project_install_path() { + local project=$1 + shift + + local install_path="$root/$INSTALL/$project" + local argument + + for argument in "$@" + do + install_path="$install_path-$argument" + done + + printf '%s\n' "$install_path" +} + +project_install_directory_missing_empty_error() { + local project=$1 + shift + local arguments="$*" + + local install_path=$(project_install_path "$project" "$@") + + if ! directory_filled_check "$install_path" + then + printf 1>&2 '%s\n' "Install directory for project $project (with ${arguments:-no argument}) missing or empty" + return 1 + else + return 0 + fi +} + +project_release_path() { + local project=$1 + shift + local prefix=$1 + + local release_path="$root/$RELEASE/$prefix" + + # Special care for tools and systems, that depend on the host arch. + if [[ "$prefix" = "$SYSTEMS" ]] || [[ "$prefix" = "$TOOLS" ]] + then + local machine=$(uname -m) + + release_path="$release_path/$machine/$project" + else + release_path="$release_path/$project" + fi + + printf '%s\n' "$release_path" +} + +project_release_archive_path() { + local project=$1 + shift + local prefix=$1 + shift + + local release_path=$(project_release_path "$project" "$prefix") + local argument + local path="$project" + + for argument in "$@" + do + path="$path-$argument" + done + + local archive_path="$release_path/$path.$ARCHIVE" + + printf '%s\n' "$archive_path" +} + +project_release_rootfs_path() { + local project=$1 + shift + local prefix=$1 + shift + + local release_path=$(project_release_path "$project" "$prefix") + local argument + local path="$project" + + for argument in "$@" + do + path="$path-$argument" + done + + local rootfs_path="$release_path/$path.$ARCHIVE" + + printf '%s\n' "$rootfs_path" +} + +project_release_sources_archive_path() { + local project=$1 + shift + + local repository="$project" + local sources_path="$(project_sources_path "$project" "$repository" "$@")" + local archive_path="$root/$RELEASE/$SOURCES/$project/${sources_path##*/}.$ARCHIVE" + + printf '%s\n' "$archive_path" +} + +project_release_sources_archive_create() { + local project=$1 + shift + local arguments="$*" + + local repository=$project + local archive_path=$(project_release_sources_archive_path "$project" "$@") + local sources_path=$(project_sources_path "$project" "$repository" "$@") + + printf '%s\n' "Releasing sources archive for $project (with ${arguments:-no argument})" + + archive_create "$archive_path" "$sources_path" + file_verification_create "$archive_path" +} + +project_release_sources_archive_exists_check() { + local project=$1 + shift + + local archive_path=$(project_release_sources_archive_path "$project" "$@") + if [[ -z "$archive_path" ]] || ! [[ -f "$archive_path" ]] + then + return 1 + else + return 0 + fi +} + +project_release_sources_git() { + local project=$1 + shift + local repository=$1 + shift + + requirements "git" + + project_sources_directory_missing_empty_error "$project" "$repository" "$@" + + if git_project_check "$repository" + then + if ! git_project_release_check "$project" "$repository" "$@" + then + git_project_release "$project" "$repository" "$@" + fi + else + if ! project_release_sources_archive_exists_check "$project" "$@" + then + project_release_sources_archive_create "$project" "$@" + fi + fi +} + +project_release_check_sources_git() { + local project=$1 + shift + local repository=$1 + shift + + requirements "git" + + if git_project_check "$repository" + then + git_project_release_check "$project" "$repository" "$@" + else + project_release_sources_archive_exists_check "$project" "$@" + fi +} + +project_release_install() { + local project=$1 + shift + local prefix=$1 + shift + + local install_path=$(project_install_path "$project" "$@") + local release_path=$(project_release_path "$project" "$prefix") + local directory_path + local path + + project_install_directory_missing_empty_error "$project" "$@" + + local files=$(find "$install_path" -type f || true) + local file + + printf '%s\n' "$files" | while read -r file + do + path="$release_path/$file" + directory_path=$(dirname "$path") + + mkdir -p "$directory_path" + + cp "$install_path/$file" "$path" + file_verification_create "$path" + done +} + +project_release_install_check() { + local project=$1 + shift + local prefix=$1 + shift + + local install_path=$(project_install_path "$project" "$@") + local release_path=$(project_release_path "$project" "$prefix") + local path + + project_install_directory_missing_empty_error "$project" "$@" + + local files=$(find "$install_path" -type f || true) + local file + + printf '%s\n' "$files" | while read -r file + do + path="$release_path/$file" + + file_exists_check "$path" + done +} + +project_release_install_archive() { + local project=$1 + shift + local prefix=$1 + shift + + project_install_directory_missing_empty_error "$project" "$@" + + project_release_install_archive_create "$project" "$prefix" "$@" +} + +project_release_install_archive_check() { + local project=$1 + shift + + project_release_install_archive_exists_check "$project" "$@" +} + +project_release_install_archive_create() { + local project=$1 + shift + local prefix=$1 + shift + local arguments="$*" + + local install_path=$(project_install_path "$project" "$@") + local archive_path=$(project_release_archive_path "$project" "$prefix" "$@") + + printf '%s\n' "Releasing $prefix archive for $project (with ${arguments:-no argument})" + + archive_create "$archive_path" "$install_path" + file_verification_create "$archive_path" +} + +project_release_install_archive_exists_check() { + local project=$1 + shift + local prefix=$1 + shift + + local archive_path=$(project_release_archive_path "$project" "$prefix" "$@") + + file_exists_check "$archive_path" +} + +project_release_install_rootfs() { + local project=$1 + shift + local prefix=$1 + shift + + project_install_directory_missing_empty_error "$project" "$@" + + if ! project_release_install_rootfs_exists_check "$project" "$prefix" "$@" + then + project_release_install_rootfs_create "$project" "$prefix" "$@" + fi +} + +project_release_install_rootfs_check() { + local project=$1 + shift + + project_release_install_rootfs_exists_check "$project" "$@" +} + +project_release_install_rootfs_create() { + local project=$1 + shift + local prefix=$1 + shift + local arguments="$*" + + local install_path=$(project_install_path "$project" "$@") + local rootfs_path=$(project_release_rootfs_path "$project" "$prefix" "$@") + + printf '%s\n' "Releasing $prefix rootfs for $project (with ${arguments:-no argument})" + + rootfs_create "$rootfs_path" "$install_path" + file_verification_create "$rootfs_path" +} + +project_release_install_rootfs_exists_check() { + local project=$1 + shift + local prefix=$1 + shift + + local rootfs_path=$(project_release_rootfs_path "$project" "$prefix" "$@") + + file_exists_check "$rootfs_path" +} + +project_clean() { + local project=$1 + shift + + project_clean_build "$project" "$@" + project_clean_install "$project" "$@" + project_clean_release "$project" "$@" +} + +project_clean_build() { + local project=$1 + shift + + local build_path=$(project_build_path "$project" "$@") + + rm -rf "$build_path" +} + +project_clean_install() { + local project=$1 + shift + + local install_path=$(project_install_path "$project" "$@") + + rm -rf "$install_path" +} + +project_clean_release() { + local project=$1 + shift + + local prefix + + for prefix in "$SOURCES" "$SYSTEMS" "$IMAGES" "$TOOLS" "$DOCS" + do + local release_path=$(project_release_path "$project" "$prefix") + + rm -rf "$release_path" + done +} + +project_clean_rootfs() { + local project=$1 + shift + + project_clean_build "$project" "$@" + project_clean_rootfs_install "$project" "$@" + project_clean_release "$project" "$@" + +} + +project_clean_rootfs_install() { + local project=$1 + shift + + local install_path=$(project_install_path "$project" "$@") + + execute_root rm -rf "$install_path" + +} + +project_file_path() { + local project=$1 + shift + local directory=$1 + shift + local file=$1 + shift + + local project_path=$(project_path "$project") + local path="$project_path/$directory" + local argument + local file_path + + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + path="$path/$argument" + fi + + if ! [[ -f "$path/$file" ]] + then + continue + fi + + file_path="$path/$file" + + break + done + + if [[ -z "$file_path" ]] + then + return 1 + fi + + printf '%s\n' "$file_path" +} + +project_file_test() { + local file_path=$(project_file_path "$@") + + test -f "$file_path" +} + +project_file_contents() { + local file_path=$(project_file_path "$@") + + if [[ -f "$file_path" ]] + then + cat "$file_path" + fi +} + +project_file_contents_herit() { + local project=$1 + shift + local directory=$1 + shift + local file=$1 + shift + + local project_path=$(project_path "$project") + local path="$project_path/$directory" + local argument + local file_path + + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + path="$path/$argument" + fi + + file_path="$path/$file" + + if ! [[ -f "$file_path" ]] + then + continue + fi + + cat "$file_path" + done +} diff --git a/i18n/fr_FR/libs/tool b/i18n/fr_FR/libs/tool new file mode 100755 index 00000000..f4e8a783 --- /dev/null +++ b/i18n/fr_FR/libs/tool @@ -0,0 +1,387 @@ +#!/usr/bin/env bash + +# Copyright (C) 2016 Paul Kocialkowski +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +TOOL_ACTIONS_GENERIC=(usage update execute) +TOOL_ACTIONS_GENERIC_IGNORE_CHECK=(usage update) +TOOL_ACTIONS_HELPERS=(arguments) + +tool_include() { + local tool=$1 + + local tool_path=$(tool_path "$tool") + + unset -f "${TOOL_ACTIONS[@]}" + + source "$tool_path/$tool" + + tool_helper_include "$tool" +} + +tool_helper_include() { + local tool=$1 + + local tool_path=$(tool_path "$tool") + local include="$tool_path/$tool-helper" + + if [[ -f "$include" ]] + then + source "$include" + fi +} + +tool_check() { + local tool="${1##*/}" + + local tool_path="$(tool_path "$tool")" + + if ! [[ -f "$tool_path/$tool" ]]; then + return 1 + fi +} + +tool_function_check() { + local tool=$1 + local function=$2 + + tool_include "$tool" + + if ! function_check "$function" + then + return 1 + fi + + return 0 +} + +tool_action() { + local action=$1 + shift + local tool=$1 + shift + local arguments=$@ + + ( + set +e + + if ! tool_check "$tool" + then + printf 1>&2 '%s\n' "Tool $tool check failed" + return 1 + fi + + tool_action_check "$action" "$tool" "$@" + + if [[ $? -eq 0 ]] + then + return 0 + fi + + tool_include "$tool" + + if ! function_check "$action" + then + return 0 + fi + + printf '%s\n\n' "Tool $tool $action (with ${arguments:-no argument})" + + ( + set -e + + "$action" "$@" + ) + + if [[ $? -ne 0 ]] + then + printf 1>&2 '\n%s\n' "Tool $tool $action (with ${arguments:-no argument}) failed" + + return 1 + else + printf '\n%s\n' "Tool $tool $action (with ${arguments:-no argument}) completed" + fi + ) +} + +tool_action_check() { + local action=$1 + shift + local tool=$1 + shift + + ( + set +e + + if ! tool_check "$tool" + then + printf 1>&2 '%s\n' "Tool $tool check failed" + return 1 + fi + + tool_include "$tool" + + if ! function_check "$action""_check" + then + return 1 + fi + + for tool_force in $TOOLS_FORCE + do + if [[ "$tool_force" = "$tool" ]] + then + return 1 + fi + done + + ( + set -e + "$action""_check" "$@" + ) + ) +} + +tool_action_helper() { + local helper=$1 + shift + local tool=$1 + shift + + ( + set +e + + if ! tool_check "$tool" + then + printf 1>&2 '%s\n' "Tool $tool check failed" + return 1 + fi + + tool_include "$tool" + + if ! function_check "$helper" + then + return 0 + fi + + ( + set -e + "$helper" "$@" + ) + ) +} + +tool_action_arguments_recursive() { + local action=$1 + shift + local tool=$1 + shift + + local action_helper_arguments=$(tool_action_helper "arguments" "$tool" "$@") + local argument + + if [[ $? -ne 0 ]] || [[ -z "$action_helper_arguments" ]] + then + tool_action "$action" "$tool" "$@" + else + printf '%s\n' "$action_helper_arguments" | while read argument + do + tool_action_arguments_recursive "$action" "$tool" "$@" "$argument" + done + fi +} + +tool_arguments_targets() { + local tool="$1" + shift + + local tool_path="$(tool_path "$tool")" + local targets_path="$tool_path/$CONFIGS" + local argument + + for argument in "$@"; do + targets_path="$targets_path/$argument" + done + + targets_path="$targets_path/$TARGETS" + + if [[ -f "$targets_path" ]]; then + cat "$targets_path" + fi +} + +tool_path() { + local tool=$1 + + local tool_path="$root/$TOOLS/$tool" + + printf '%s\n' "$tool_path" +} + +tool_sources_path() { + local tool=$1 + shift + + local path="$root/$TOOLS/$tool/$SOURCES" + local argument + + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + path="$path/$argument" + fi + + if directory_filled_check "$path" + then + printf '%s\n' "$path" + return + fi + done +} + +tool_usage_actions() { + local tool=$1 + shift + + printf '\n%s\n' 'Generic actions:' + + for action in "${TOOL_ACTIONS_GENERIC[@]}" + do + if function_check "$action" + then + printf '%s\n' " $action" + fi + done + + if [[ $# -gt 0 ]] + then + printf '\n%s\n' 'Specific actions:' + + for action in "$@" + do + printf '%s\n' " $action" + done + fi +} + +tool_usage_arguments() { + local tool=$1 + shift + + printf '\n%s\n' 'Arguments:' + + tool_usage_arguments_recursive "$tool" " " "$@" +} + +tool_usage_arguments_recursive() { + local tool=$1 + shift + local spacing=$1 + shift + + local action_helper_arguments=$(tool_action_helper "arguments" "$tool" "$@") + local argument + + if [[ -n "$action_helper_arguments" ]] + then + printf '%s\n' "$action_helper_arguments" | while read argument + do + printf '%s\n' "$spacing$argument" + tool_usage_arguments_recursive "$tool" " $spacing" "$@" "$argument" + done + fi +} + +tool_file_path() { + local tool=$1 + shift + local directory=$1 + shift + local file=$1 + shift + + local tool_path=$(tool_path "$tool") + local path="$tool_path/$directory" + local argument + local file_path + + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + path="$path/$argument" + fi + + if ! [[ -f "$path/$file" ]] + then + continue + fi + + file_path="$path/$file" + done + + if [[ -z "$file_path" ]] + then + return 1 + fi + + printf '%s\n' "$file_path" +} + +tool_file_test() { + local file_path=$(tool_file_path "$@") + + test -f "$file_path" +} + +tool_file_contents() { + local file_path=$(tool_file_path "$@") + + if [[ -f "$file_path" ]] + then + cat "$file_path" + fi +} + +tool_file_contents_herit() { + local tool=$1 + shift + local directory=$1 + shift + local file=$1 + shift + + local tool_path=$(tool_path "$tool") + local path="$tool_path/$directory" + local argument + local file_path + + for argument in "" "$@" + do + if [[ -n "$argument" ]] + then + path="$path/$argument" + fi + + file_path="$path/$file" + + if ! [[ -f "$file_path" ]] + then + continue + fi + + cat "$file_path" + done +} diff --git a/i18n/fr_FR/oldbuild b/i18n/fr_FR/oldbuild new file mode 100755 index 00000000..c0902012 --- /dev/null +++ b/i18n/fr_FR/oldbuild @@ -0,0 +1,101 @@ +#!/bin/sh + +# generic build script, for building components (all of them) +# +# Copyright (C) 2014, 2015 Leah Rowe +# Copyright (C) 2015 Patrick "P. J." McDermott +# Copyright (C) 2015, 2016 Klemens Nanni +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . +# + +[ "x${DEBUG+set}" = 'xset' ] && set -v +set -u -e + +build=./resources/scripts/helpers/build + +listmodes() { + for mode in "${build}"/*; do + printf '%s\n' "${mode##*/}" + done +} + +# Takes exactly one mode as parameter +listoptions() { + for option in "${build}"/"${1}"/*; do + printf '%s\n' "${option##*/}" + done +} + +help() { + cat <<- EOF + USAGE: ./oldbuild