From f8cf9dd9488fc3f4ac1993459d05ef99a4e5ba0f Mon Sep 17 00:00:00 2001 From: Andrew Robbins Date: Sat, 12 Jan 2019 19:30:37 -0500 Subject: Create 1MiB coreboot config/target for D945GCLF Previously it was thought that only boards with 512KiB flash chips were produced but JohnMH (in #libreboot) ran across one with an SST25LF080A 1MiB flash. D945GCLF Coreboot ROMs can be built with, e.g.: './libreboot build coreboot d945gclf textmode 1mb' --- projects/coreboot/configs/d945gclf/textmode/1mb/config | 5 +++++ projects/coreboot/configs/d945gclf/textmode/targets | 1 + 2 files changed, 6 insertions(+) create mode 100644 projects/coreboot/configs/d945gclf/textmode/1mb/config (limited to 'projects/coreboot') diff --git a/projects/coreboot/configs/d945gclf/textmode/1mb/config b/projects/coreboot/configs/d945gclf/textmode/1mb/config new file mode 100644 index 00000000..020bc913 --- /dev/null +++ b/projects/coreboot/configs/d945gclf/textmode/1mb/config @@ -0,0 +1,5 @@ +CONFIG_CBFS_SIZE=0x100000 +CONFIG_COREBOOT_ROMSIZE_KB_512=n +CONFIG_COREBOOT_ROMSIZE_KB_1024=y +CONFIG_COREBOOT_ROMSIZE_KB=1024 +CONFIG_ROM_SIZE=0x100000 diff --git a/projects/coreboot/configs/d945gclf/textmode/targets b/projects/coreboot/configs/d945gclf/textmode/targets index c01fccf5..8f8c3862 100644 --- a/projects/coreboot/configs/d945gclf/textmode/targets +++ b/projects/coreboot/configs/d945gclf/textmode/targets @@ -1,2 +1,3 @@ 16mb +1mb 512kb -- cgit v1.2.3-70-g09d2