KGPE-D16: update patch set (also update coreboot and vboot)

Also contains other fixes from coreboot, like:
* 551cff0 Derive lvds_dual_channel from EDID timings.
^ makes single/dual channel LVDS selection on GM45 automatic
* 26fc544 lenovo/t60: Enable native intel gfx init.
^ was being maintained in libreboot, now upstreamed so not needed

Framebuffer mode was disabled for the KGPE-D16, because only
text-mode works at the moment.

1 files changed, 149 insertions, 0 deletions

diff --git a/resources/libreboot/patch/kgpe-d16/0028-src-console-Add-x86-printk-spinlock-support.patch b/resources/libreboot/patch/kgpe-d16/0028-src-console-Add-x86-printk-spinlock-support.patch
new file mode 100644
index 00000000..2baeb9c9
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0028-src-console-Add-x86-printk-spinlock-support.patch
@@ -0,0 +1,149 @@
+From 5748ef1b46c9625a81b63c9141dfe2bf55dccc20 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Sat, 5 Sep 2015 19:23:49 -0500
+Subject: [PATCH 028/139] src/console: Add x86 printk spinlock support
+
+Change-Id: Ib189ab842ede603b8d5080012ceb92e6964d4fe0
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/Kconfig                              |  4 ++++
+ src/arch/x86/include/arch/smp/spinlock.h |  1 +
+ src/console/printk.c                     |  6 +++---
+ src/cpu/amd/car/disable_cache_as_ram.c   | 10 ++++++++++
+ src/cpu/amd/car/post_cache_as_ram.c      | 20 ++++++++++++++------
+ 5 files changed, 32 insertions(+), 9 deletions(-)
+
+diff --git a/src/Kconfig b/src/Kconfig
+index 2822bfe..4e46364 100644
+--- a/src/Kconfig
++++ b/src/Kconfig
+@@ -447,6 +447,10 @@ config HAVE_HARD_RESET
+ 	  This variable specifies whether a given board has a hard_reset
+ 	  function, no matter if it's provided by board code or chipset code.
+ 
++config HAVE_ROMSTAGE_CONSOLE_SPINLOCK
++	bool
++	default n
++
+ config HAVE_MONOTONIC_TIMER
+ 	def_bool n
+ 	help
+diff --git a/src/arch/x86/include/arch/smp/spinlock.h b/src/arch/x86/include/arch/smp/spinlock.h
+index a5904c7..5000779 100644
+--- a/src/arch/x86/include/arch/smp/spinlock.h
++++ b/src/arch/x86/include/arch/smp/spinlock.h
+@@ -13,6 +13,7 @@ typedef struct {
+ 
+ #ifdef __PRE_RAM__
+ spinlock_t* romstage_console_lock(void);
++void initialize_romstage_console_lock(void);
+ #endif
+ 
+ #define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 }
+diff --git a/src/console/printk.c b/src/console/printk.c
+index 2aae980..5a23db0 100644
+--- a/src/console/printk.c
++++ b/src/console/printk.c
+@@ -14,7 +14,7 @@
+ #include <stddef.h>
+ #include <trace.h>
+ 
+-#if defined(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
++#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
+ #ifndef __PRE_RAM__
+ DECLARE_SPIN_LOCK(console_lock)
+ #endif
+@@ -47,7 +47,7 @@ int do_printk(int msg_level, const char *fmt, ...)
+ 
+ 	DISABLE_TRACE;
+ #ifdef __PRE_RAM__
+-#ifdef CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK
++#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
+ 	spin_lock(romstage_console_lock());
+ #endif
+ #else
+@@ -61,7 +61,7 @@ int do_printk(int msg_level, const char *fmt, ...)
+ 	console_tx_flush();
+ 
+ #ifdef __PRE_RAM__
+-#ifdef CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK
++#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
+ 	spin_unlock(romstage_console_lock());
+ #endif
+ #else
+diff --git a/src/cpu/amd/car/disable_cache_as_ram.c b/src/cpu/amd/car/disable_cache_as_ram.c
+index 3b464b8..5eccf79 100644
+--- a/src/cpu/amd/car/disable_cache_as_ram.c
++++ b/src/cpu/amd/car/disable_cache_as_ram.c
+@@ -24,6 +24,16 @@
+ 
+ #include <cpu/x86/cache.h>
+ 
++static inline __attribute__((always_inline)) uint32_t amd_fam1x_cpu_family(void)
++{
++	uint32_t family;
++
++	family = cpuid_eax(0x80000001);
++	family = ((family & 0xf00000) >> 16) | ((family & 0xf00) >> 8);
++
++	return family;
++}
++
+ static inline __attribute__((always_inline)) void disable_cache_as_ram(void)
+ {
+ 	msr_t msr;
+diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
+index e265de1..257b41a 100644
+--- a/src/cpu/amd/car/post_cache_as_ram.c
++++ b/src/cpu/amd/car/post_cache_as_ram.c
+@@ -84,6 +84,10 @@ static void prepare_ramstage_region(void *resume_backup_memory)
+ 		memset_((void*)0, 0, CONFIG_RAMTOP - backup_top);
+ 	}
+ 
++#if IS_ENABLED(CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK)
++	initialize_romstage_console_lock();
++#endif
++
+ 	print_car_debug("Done\n");
+ }
+ 
+@@ -92,18 +96,19 @@ static void prepare_ramstage_region(void *resume_backup_memory)
+ static void vErrata343(void)
+ {
+ #ifdef BU_CFG2_MSR
+-    msr_t msr;
+-    unsigned int uiMask = 0xFFFFFFF7;
++	msr_t msr;
++	unsigned int uiMask = 0xFFFFFFF7;
+ 
+-    msr = rdmsr(BU_CFG2_MSR);
+-    msr.hi &= uiMask; // set bit 35 to 0
+-    wrmsr(BU_CFG2_MSR, msr);
++	msr = rdmsr(BU_CFG2_MSR);
++	msr.hi &= uiMask;	// IcDisSpecTlbWr (bit 35) = 0
++	wrmsr(BU_CFG2_MSR, msr);
+ #endif
+ }
+ 
+ void post_cache_as_ram(void)
+ {
+ 	void *resume_backup_memory = NULL;
++	uint32_t family = amd_fam1x_cpu_family();
+ 
+ 	struct romstage_handoff *handoff;
+ 	handoff = romstage_handoff_find_or_add();
+@@ -120,7 +125,10 @@ void post_cache_as_ram(void)
+ 	prepare_romstage_ramstack(resume_backup_memory);
+ 
+ 	/* from here don't store more data in CAR */
+-	vErrata343();
++	if (family < 0x6f) {
++		/* Family 10h or earlier */
++		vErrata343();
++	}
+ 
+ 	size_t car_size = car_data_size();
+ 	void *migrated_car = (void *)(CONFIG_RAMTOP - car_size);
+-- 
+1.9.1
+