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authorFrancis Rowe <info@gluglug.org.uk>2015-10-19 00:12:53 +0100
committerFrancis Rowe <info@gluglug.org.uk>2015-10-19 02:32:36 +0100
commit0622df6194dbb1b2120743c0fd1cc5e72c380128 (patch)
tree4c858b8c5667fe001a9907ae0578b4ec28a8f513 /resources/libreboot/patch/kgpe-d16/0065-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch
parent5999dba5f71f1c05040a551d2420ab8c7f3a9da4 (diff)
downloadlibrebootfr-0622df6194dbb1b2120743c0fd1cc5e72c380128.tar.gz
librebootfr-0622df6194dbb1b2120743c0fd1cc5e72c380128.zip
KGPE-D16: update patch set (also update coreboot and vboot)
Also contains other fixes from coreboot, like: * 551cff0 Derive lvds_dual_channel from EDID timings. ^ makes single/dual channel LVDS selection on GM45 automatic * 26fc544 lenovo/t60: Enable native intel gfx init. ^ was being maintained in libreboot, now upstreamed so not needed Framebuffer mode was disabled for the KGPE-D16, because only text-mode works at the moment.
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0065-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch')
-rw-r--r--resources/libreboot/patch/kgpe-d16/0065-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch96
1 files changed, 96 insertions, 0 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0065-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch b/resources/libreboot/patch/kgpe-d16/0065-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch
new file mode 100644
index 00000000..f63be477
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0065-src-southbridge-amd-sb700-Reset-SATA-controller-in-A.patch
@@ -0,0 +1,96 @@
+From 15a27b612b1da36173017dd671763ce455f319ad Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Sun, 21 Jun 2015 16:27:03 -0500
+Subject: [PATCH 065/139] src/southbridge/amd/sb700: Reset SATA controller in
+ AHCI mode during startup
+
+In AHCI mode SeaBIOS randomly fails to detect disks (AHCI timeouts),
+with the probability of a failure increasing with the number of disks
+connected to the controller. Resetting the SATA controller appears to
+show the true state of the underlying hardware, allowing the drive
+detection code to attempt link renegotiation as needed.
+
+Change-Id: Ib1f7c5f830a0cdba41cb6f5b05d759adee5ce369
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/southbridge/amd/sb700/sata.c | 47 ++++++++++++++++++++++++++++++----------
+ 1 file changed, 35 insertions(+), 12 deletions(-)
+
+diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c
+index 24f78dd..d51baa1 100644
+--- a/src/southbridge/amd/sb700/sata.c
++++ b/src/southbridge/amd/sb700/sata.c
+@@ -135,6 +135,8 @@ static void sata_init(struct device *dev)
+ /* get rev_id */
+ rev_id = pci_read_config8(sm_dev, 0x08) - 0x28;
+
++ printk(BIOS_SPEW, "rev_id=%x\n", rev_id);
++
+ if (sata_ahci_mode) {
+ /* Enable link latency enhancement on A14 and above */
+ if (rev_id >= 0x14) {
+@@ -245,6 +247,27 @@ static void sata_init(struct device *dev)
+ write32(sata_bar5 + 0xfc, dword);
+ }
+
++ if (sata_ahci_mode) {
++ /* FIXME
++ * SeaBIOS does not know how to spin
++ * up the drives and therefore hangs
++ * in AHCI init if this is enabled...
++ */
++ /* Enable staggered spin-up */
++ dword = read32(sata_bar5 + 0x00);
++#if 0
++ dword |= 0x1 << 27;
++#else
++ dword &= ~(0x1 << 27);
++#endif
++ write32(sata_bar5 + 0x00, dword);
++
++ /* Reset the HBA to avoid stuck drives in SeaBIOS */
++ dword = read32(sata_bar5 + 0x04);
++ dword |= 0x1;
++ write32(sata_bar5 + 0x04, dword);
++ }
++
+ /* Write protect Sub-Class Code */
+ byte = pci_read_config8(dev, 0x40);
+ byte &= ~(1 << 0);
+@@ -371,21 +394,21 @@ static void sata_init(struct device *dev)
+ }
+
+ /* Below is CIM InitSataLateFar */
+- /* Enable interrupts from the HBA */
+- byte = read8(sata_bar5 + 0x4);
+- byte |= 1 << 1;
+- write8((sata_bar5 + 0x4), byte);
+-
+ if (!sata_ahci_mode) {
+- /* Clear error status */
+- write32((sata_bar5 + 0x130), 0xFFFFFFFF);
+- write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
+- write32((sata_bar5 + 0x230), 0xFFFFFFFF);
+- write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
+- write32((sata_bar5 + 0x330), 0xFFFFFFFF);
+- write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
++ /* Enable interrupts from the HBA */
++ byte = read8(sata_bar5 + 0x4);
++ byte |= 1 << 1;
++ write8((sata_bar5 + 0x4), byte);
+ }
+
++ /* Clear error status */
++ write32((sata_bar5 + 0x130), 0xFFFFFFFF);
++ write32((sata_bar5 + 0x1b0), 0xFFFFFFFF);
++ write32((sata_bar5 + 0x230), 0xFFFFFFFF);
++ write32((sata_bar5 + 0x2b0), 0xFFFFFFFF);
++ write32((sata_bar5 + 0x330), 0xFFFFFFFF);
++ write32((sata_bar5 + 0x3b0), 0xFFFFFFFF);
++
+ /* Clear SATA status,Firstly we get the AcpiGpe0BlkAddr */
+ /* ????? why CIM does not set the AcpiGpe0BlkAddr , but use it??? */
+
+--
+1.9.1
+