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| author | Francis Rowe <info@gluglug.org.uk> | 2015-10-19 00:12:53 +0100 |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2015-10-19 02:32:36 +0100 |
| commit | 0622df6194dbb1b2120743c0fd1cc5e72c380128 (patch) | |
| tree | 4c858b8c5667fe001a9907ae0578b4ec28a8f513 /resources/libreboot/patch/kgpe-d16/0074-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch | |
| parent | 5999dba5f71f1c05040a551d2420ab8c7f3a9da4 (diff) | |
| download | librebootfr-0622df6194dbb1b2120743c0fd1cc5e72c380128.tar.gz librebootfr-0622df6194dbb1b2120743c0fd1cc5e72c380128.zip | |
KGPE-D16: update patch set (also update coreboot and vboot)
Also contains other fixes from coreboot, like:
* 551cff0 Derive lvds_dual_channel from EDID timings.
^ makes single/dual channel LVDS selection on GM45 automatic
* 26fc544 lenovo/t60: Enable native intel gfx init.
^ was being maintained in libreboot, now upstreamed so not needed
Framebuffer mode was disabled for the KGPE-D16, because only
text-mode works at the moment.
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0074-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0074-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0074-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch b/resources/libreboot/patch/kgpe-d16/0074-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch new file mode 100644 index 00000000..57034429 --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0074-northbridge-amd-amdmct-mct_ddr3-Work-around-strange-.patch @@ -0,0 +1,42 @@ +From 91caf442aef8c846b9d860bf3e8d2954a2a5e21b Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Thu, 25 Jun 2015 18:37:45 -0500 +Subject: [PATCH 074/139] northbridge/amd/amdmct/mct_ddr3: Work around strange + phy training issue + +Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +index bb076cb..bd37ba7 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +@@ -207,6 +207,22 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT + + pDCTData->WLCriticalGrossDelayPrevPass = cgd; + ++ if (pDCTstat->Speed != pDCTstat->TargetFreq) { ++ /* FIXME ++ * Using the Pass 1 training values causes major phy training problems on ++ * all Family 15h processors I tested (Pass 1 values are randomly too high, ++ * and Pass 2 cannot lock). ++ * Figure out why this is and fix it, then remove the bypass code below... ++ */ ++ if (pass == FirstPass) { ++ for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { ++ pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane]; ++ pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane]; ++ } ++ return 0; ++ } ++ } ++ + /* Compensate for occasional noise/instability causing sporadic training failure */ + for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { + uint8_t faulty_value_detected = 0; +-- +1.9.1 + |