Update coreboot to new version (use latest stable kgpe-d16 tree)

1 files changed, 64 insertions, 0 deletions

diff --git a/resources/libreboot/patch/kgpe-d16/0095-cpu-amd-family_10h-family_15h-Fix-incorrect-revision.patch b/resources/libreboot/patch/kgpe-d16/0095-cpu-amd-family_10h-family_15h-Fix-incorrect-revision.patch
new file mode 100644
index 00000000..90c51327
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0095-cpu-amd-family_10h-family_15h-Fix-incorrect-revision.patch
@@ -0,0 +1,64 @@
+From ba93fcaf7408e3e00c01056f9257c94b82302382 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Sun, 2 Aug 2015 21:31:48 -0500
+Subject: [PATCH 095/143] cpu/amd/family_10h-family_15h: Fix incorrect
+ revision detection
+
+Change-Id: I7a881a94d62ed455415f9dfc887fd698ac919429
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/cpu/amd/family_10h-family_15h/fidvid.c |   10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c
+index d99c37f..7453ad4 100644
+--- a/src/cpu/amd/family_10h-family_15h/fidvid.c
++++ b/src/cpu/amd/family_10h-family_15h/fidvid.c
+@@ -375,7 +375,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
+ 	pci_write_config32(dev, 0xd8, dtemp);
+ }
+ 
+-static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) {
++static u32 nb_clk_did(int node, uint64_t cpuRev, uint8_t procPkg) {
+         u8 link0isGen3 = 0;
+         u8 offset;
+         if (AMD_CpuFindCapability(node, 0, &offset)) {
+@@ -446,7 +446,7 @@ static u32 power_up_down(int node, u8 procPkg) {
+         return dword;
+ }
+ 
+-static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
++static void config_clk_power_ctrl_reg0(int node, uint64_t cpuRev, uint8_t procPkg) {
+        	device_t dev = NODE_PCI(node, 3);
+ 
+ 	/* Program fields in Clock Power/Control register0 (F3xD4) */
+@@ -471,7 +471,7 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
+ 
+ }
+ 
+-static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
++static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t procPkg) {
+ 	/* check PVI/SVI */
+ 	u32 dword = pci_read_config32(dev, 0xa0);
+ 
+@@ -504,7 +504,7 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
+ 	pci_write_config32(dev, 0xa0, dword);
+ }
+ 
+-static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
++static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) {
+ 	/* Note the following settings are additional from the ported
+ 	 * function setFidVidRegs()
+ 	 */
+@@ -526,7 +526,7 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
+ 	pci_write_config32(dev, 0xdc, dword);
+ }
+ 
+-static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) {
++static void config_acpi_pwr_state_ctrl_regs(device_t dev, uint64_t cpuRev, uint8_t procPkg) {
+ 	if (is_fam15h()) {
+ 		/* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */
+ 		pci_write_config32(dev, 0x80, 0xe20be281);
+-- 
+1.7.9.5
+