New board: ASUS KGPE-D16

coreboot build errors:

In file included from src/northbridge/amd/amdfam10/misc_control.c:35:0:
src/include/option.h:13:27: error: static declaration of 'get_option' follows non-static declaration
 static inline enum cb_err get_option(void *dest, const char *name)
                           ^
In file included from src/northbridge/amd/amdfam10/misc_control.c:34:0:
src/include/pc80/mc146818rtc.h:176:13: note: previous declaration of 'get_option' was here
 enum cb_err get_option(void *dest, const char *name);

Ping tpearson about this.

Also ping him about the fact that there isn't actually an option to
enable or disable native graphics initialization, but that the option
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is in fact available and set to Y in the
Kconfig file. I think this is probably since there isn't even an option
ROM available for the machine, so it's pointless to offer the setting.

1 files changed, 62 insertions, 0 deletions

diff --git a/resources/libreboot/patch/kgpe-d16/0095-cpu-amd-model_10xxx-Fix-incorrect-revision-detection.patch b/resources/libreboot/patch/kgpe-d16/0095-cpu-amd-model_10xxx-Fix-incorrect-revision-detection.patch
new file mode 100644
index 00000000..842202e9
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0095-cpu-amd-model_10xxx-Fix-incorrect-revision-detection.patch
@@ -0,0 +1,62 @@
+From 6212e218fbd616d7ddeb74fffd883741ba40a6d6 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+Date: Sun, 2 Aug 2015 21:31:48 -0500
+Subject: [PATCH 095/146] cpu/amd/model_10xxx: Fix incorrect revision
+ detection
+
+---
+ src/cpu/amd/model_10xxx/fidvid.c |   10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c
+index fe1cfb4..1d55275 100644
+--- a/src/cpu/amd/model_10xxx/fidvid.c
++++ b/src/cpu/amd/model_10xxx/fidvid.c
+@@ -375,7 +375,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
+ 	pci_write_config32(dev, 0xd8, dtemp);
+ }
+ 
+-static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) {
++static u32 nb_clk_did(int node, uint64_t cpuRev, uint8_t procPkg) {
+         u8 link0isGen3 = 0;
+         u8 offset;
+         if (AMD_CpuFindCapability(node, 0, &offset)) {
+@@ -446,7 +446,7 @@ static u32 power_up_down(int node, u8 procPkg) {
+         return dword;
+ }
+ 
+-static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
++static void config_clk_power_ctrl_reg0(int node, uint64_t cpuRev, uint8_t procPkg) {
+        	device_t dev = NODE_PCI(node, 3);
+ 
+ 	/* Program fields in Clock Power/Control register0 (F3xD4) */
+@@ -471,7 +471,7 @@ static void config_clk_power_ctrl_reg0(int node, u32 cpuRev, u8 procPkg) {
+ 
+ }
+ 
+-static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
++static void config_power_ctrl_misc_reg(device_t dev, uint64_t cpuRev, uint8_t procPkg) {
+ 	/* check PVI/SVI */
+ 	u32 dword = pci_read_config32(dev, 0xa0);
+ 
+@@ -504,7 +504,7 @@ static void config_power_ctrl_misc_reg(device_t dev,u32 cpuRev, u8 procPkg) {
+ 	pci_write_config32(dev, 0xa0, dword);
+ }
+ 
+-static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
++static void config_nb_syn_ptr_adj(device_t dev, uint64_t cpuRev) {
+ 	/* Note the following settings are additional from the ported
+ 	 * function setFidVidRegs()
+ 	 */
+@@ -526,7 +526,7 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) {
+ 	pci_write_config32(dev, 0xdc, dword);
+ }
+ 
+-static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) {
++static void config_acpi_pwr_state_ctrl_regs(device_t dev, uint64_t cpuRev, uint8_t procPkg) {
+ 	if (is_fam15h()) {
+ 		/* Family 15h BKDG Rev. 3.14 D18F3x80 recommended settings */
+ 		pci_write_config32(dev, 0x80, 0xe20be281);
+-- 
+1.7.9.5
+