New board: ASUS KGPE-D16

coreboot build errors:

In file included from src/northbridge/amd/amdfam10/misc_control.c:35:0:
src/include/option.h:13:27: error: static declaration of 'get_option' follows non-static declaration
 static inline enum cb_err get_option(void *dest, const char *name)
                           ^
In file included from src/northbridge/amd/amdfam10/misc_control.c:34:0:
src/include/pc80/mc146818rtc.h:176:13: note: previous declaration of 'get_option' was here
 enum cb_err get_option(void *dest, const char *name);

Ping tpearson about this.

Also ping him about the fact that there isn't actually an option to
enable or disable native graphics initialization, but that the option
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is in fact available and set to Y in the
Kconfig file. I think this is probably since there isn't even an option
ROM available for the machine, so it's pointless to offer the setting.

1 files changed, 63 insertions, 0 deletions

diff --git a/resources/libreboot/patch/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch b/resources/libreboot/patch/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch
new file mode 100644
index 00000000..f0af7290
--- /dev/null
+++ b/resources/libreboot/patch/kgpe-d16/0127-northbridge-amd-amdmct-mct_ddr3-Fix-odd-rank-data-co.patch
@@ -0,0 +1,63 @@
+From a89e50c7cef4090f00f530da8161d7d63d111e82 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
+Date: Thu, 27 Aug 2015 13:19:34 -0500
+Subject: [PATCH 127/146] northbridge/amd/amdmct/mct_ddr3: Fix odd rank data
+ corruption due to incorrect DQS training
+
+---
+ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c |   25 ++++++++++++++++--------
+ 1 file changed, 17 insertions(+), 8 deletions(-)
+
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+index eedff67..98d2f11 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+@@ -1324,9 +1324,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
+ 		Receiver = receiver_start;
+ 
+ 	/* There are four receiver pairs, loosely associated with chipselects.
+-	 * This is essentially looping over each DIMM.
++	 * This is essentially looping over each rank within each DIMM.
+ 	 */
+-	for (; Receiver < receiver_end; Receiver += 2) {
++	for (; Receiver < receiver_end; Receiver++) {
+ 		dimm = (Receiver >> 1);
+ 		if ((Receiver & 0x1) == 0) {
+ 			/* Even rank of DIMM */
+@@ -1340,18 +1340,27 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
+ 			continue;
+ 		}
+ 
++#if DQS_TRAIN_DEBUG > 0
++		printk(BIOS_DEBUG, "TrainDQSRdWrPos: Training DQS read/write position for receiver %d (DIMM %d)\n", Receiver, dimm);
++#endif
++
+ 		/* Initialize variables */
+ 		for (lane = lane_start; lane < lane_end; lane++) {
+ 			passing_dqs_delay_found[lane] = 0;
+ 		}
+-		memset(dqs_results_array, 0, sizeof(dqs_results_array));
++		if ((Receiver & 0x1) == 0) {
++			/* Even rank of DIMM */
++			memset(dqs_results_array, 0, sizeof(dqs_results_array));
++
++			/* Read initial read / write DQS delays */
++			read_dqs_write_timing_control_registers(initial_write_dqs_delay, dev, dct, dimm, index_reg);
++			read_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg);
+ 
+-		/* Read initial read / write DQS delays */
+-		read_dqs_write_timing_control_registers(initial_write_dqs_delay, dev, dct, dimm, index_reg);
+-		read_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg);
++			/* Read current settings of other (previously trained) lanes */
++			read_dqs_write_data_timing_registers(initial_write_data_timing, dev, dct, dimm, index_reg);
++		}
+ 
+-		/* Read current settings of other (previously trained) lanes */
+-		read_dqs_write_data_timing_registers(initial_write_data_timing, dev, dct, dimm, index_reg);
++		/* Initialize iterators */
+ 		memcpy(current_write_data_delay, initial_write_data_timing, sizeof(current_write_data_delay));
+ 
+ 		for (lane = lane_start; lane < lane_end; lane++) {
+-- 
+1.7.9.5
+