diff options
65 files changed, 416 insertions, 155 deletions
diff --git a/docs/gnulinux/grub_cbfs.md b/docs/gnulinux/grub_cbfs.md index 2e68cb0b..fc46180c 100644 --- a/docs/gnulinux/grub_cbfs.md +++ b/docs/gnulinux/grub_cbfs.md @@ -262,7 +262,7 @@ Then, add the new one to the ROM: $ ./cbfstool libreboot.rom add -n grubtest.cfg -f grubtest.cfg -t raw -#### Change MAC address in ROM +#### Change MAC address in ROM {#changeMAC} The last step before flashing the new ROM, is to change the MAC address inside it. Every libreboot ROM image contains a generic MAC address; you want to make sure that your ROM image contains yours, so as to not create any problems on your network diff --git a/docs/hardware/kcma-d8.md b/docs/hardware/kcma-d8.md index f6c6fad7..fb7e6eed 100644 --- a/docs/hardware/kcma-d8.md +++ b/docs/hardware/kcma-d8.md @@ -32,9 +32,9 @@ See <https://raptorengineeringinc.com/coreboot/kcma-d8-status.php>. Form factor {#formfactor} =========== -These boards use the SSI EEB 3.61 form factor; make sure that your case -supports this. This form factor is similar to E-ATX in that the size is -identical, but the position of the screws are different. +This board is ATX form factor. While the [ATX standard, version 2.2](https://web.archive.org/web/20120725150314/http://www.formfactors.org/developer/specs/atx2_2.pdf) +specifies board dimensions 305mm x 244mm, this board measures 305mm x 253mm; +ensure your case supports this extra ~centimeter in width. IPMI iKVM module add-on {#ipmi} ======================= diff --git a/docs/hardware/mac_address.md b/docs/hardware/mac_address.md new file mode 100644 index 00000000..0a0d3621 --- /dev/null +++ b/docs/hardware/mac_address.md @@ -0,0 +1,107 @@ +--- +title: Changing the MAC address +... + +Introduction (GM45+e1000) +========================= + +This section is applicable to all Libreboot-supported laptops with the +mobile 4 series chipset (as shown in `$ lspci`) +that use the e1000 ethernet controller (e.g. T400, X200). +The R500 is an exception to this as it does not use the built-in e1000. + +On all these laptops, the +[MAC address](https://en.wikipedia.org/wiki/MAC_address) +for the built-in gigabit ethernet controller is stored inside the flash chip, +along with Libreboot and other configuration data. Therefore, installing +Libreboot will overwrite it. + +Thus, for these laptops, prebuilt Libreboot already contains a generic +MAC address in the configuration section. This address is `00:f5:f0:40:71:fe` +in builds before 2018-01-16 and `00:4c:69:62:72:65` (see the ascii character +set) afterwards. +Unless you change it, your computer will boot and use it. This can lead +to network problems if you have more than one Libreboot computer on +the same layer2 network (e.g. on the same network switch). The switch +(postman) will simply not know who to deliver to as the MAC (house) addresses +will be the same. + +To prevent these address clashes, you can either modify prebuilt Libreboot +to use an address of your own choosing or you can change the address in your +operating system's boot scripts. + +In either case, it is a good idea to write down the address that your +computer originally had. + +Obtaining the existing MAC address +================================== + +The existing MAC address may be obtained by the following methods: + +1. Run `ip link` or `ifconfig` in a terminal/console/shell; + find your ethernet device (e.g., **enpXXX** or **ethXXX**), + and look for a set of 12 colon-delimited + [hexadecimal digits](https://en.wikipedia.org/wiki/Hexadecimal). + For example: `00:f3:f0:45:91:fe`. + + * `$ ip link` + + `... link/ether ??:??:??:??:??:?? brd ...` + + * Alternatively: + + `$ ifconfig` + + `... ether ??:??:??:??:??:?? txqueuelen ...` + + +2. Otherwise you can read the white label that is often found on the + motherboard under the memory sticks: +  + +3. The MAC address is usually listed on the laptop chassis as well. This one + will be incorrect if the motherboard was changed and the stickers were not + updated. + +Changing the MAC address in the operating system +================================================ + +There are three portable ways of doing so: + +1. Using the new iproute2 package: + + `# ip link set <interface> down` + + `# ip link set dev <interface> address 00:4c:69:62:72:65` + + `# ip link set <interface> up` + + +2. Using the old `ifconfig` command: + + `# ifconfig <interface> hw ether 00:4c:69:62:72:65` + + +3. Using the macchanger package. + +You can use use of these three methods in your operating system's +init scripts or you can use your operating system's own networking +configuration. Refer to your operating system's documentation for +how to do this. + +Changing the MAC address in Libreboot +===================================== + +See [here](../gnulinux/grub_cbfs.md#changeMAC). + + + +Copyright © 2017 Fedja Beader <fedja@protonmail.ch> + +Copyright © 2014, 2015 Leah Rowe <info@minifree.org> + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/r400_external.md b/docs/install/r400_external.md index 4036c761..8f9dd1ff 100644 --- a/docs/install/r400_external.md +++ b/docs/install/r400_external.md @@ -69,15 +69,7 @@ Use this to find out: MAC address {#macaddress} =========== -On the R400, the MAC address for the onboard gigabit ethernet chipset is -stored inside the flash chip, along with other configuration data. - -Keep a note of the MAC address before disassembly; this is very -important, because you will need to insert this into the libreboot ROM -image before flashing it. It will be written in one of these locations: - -  - +Refer to [mac\_address.md](../hardware/mac_address.md). Initial BBB configuration ========================= diff --git a/docs/install/t400_external.md b/docs/install/t400_external.md index 672ea46e..d377d4c0 100644 --- a/docs/install/t400_external.md +++ b/docs/install/t400_external.md @@ -70,15 +70,7 @@ Use this to find out: MAC address {#macaddress} =========== -On the T400, the MAC address for the onboard gigabit ethernet chipset is -stored inside the flash chip, along with other configuration data. - -Keep a note of the MAC address before disassembly; this is very -important, because you will need to insert this into the libreboot ROM -image before flashing it. It will be written in one of these locations: - -  - +Refer to [mac\_address.md](../hardware/mac_address.md). Initial BBB configuration ========================= diff --git a/docs/install/t500_external.md b/docs/install/t500_external.md index 9e114bca..2a29d8ed 100644 --- a/docs/install/t500_external.md +++ b/docs/install/t500_external.md @@ -73,15 +73,7 @@ Use this to find out: MAC address {#macaddress} =========== -On the T500, the MAC address for the onboard gigabit ethernet chipset is -stored inside the flash chip, along with other configuration data. - -Keep a note of the MAC address before disassembly; this is very -important, because you will need to insert this into the libreboot ROM -image before flashing it. It will be written in one of these locations: - -  - +Refer to [mac\_address.md](../hardware/mac_address.md). Initial BBB configuration ========================= diff --git a/docs/install/x200_external.md b/docs/install/x200_external.md index 83a5c23f..c7330ce9 100644 --- a/docs/install/x200_external.md +++ b/docs/install/x200_external.md @@ -28,16 +28,7 @@ supported; see the [hardware](../hardware/x200.html#x200s) page. MAC address =========== -On the X200/X200S/X200T, the MAC address for the onboard gigabit -ethernet chipset is stored inside the flash chip, along with other -configuration data. - -Keep a note of the MAC address before disassembly; this is very -important, because you will need to insert this into the libreboot ROM -image before flashing it. It will be written in one of these locations: - - - +Refer to [mac\_address.md](../hardware/mac_address.md). Initial BBB configuration ========================= diff --git a/projects/coreboot/configs/nyan/big/corebootfb/16mb/config b/projects/coreboot/configs/nyan/big/corebootfb/16mb/config new file mode 100644 index 00000000..d3e3b7aa --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/16mb/config @@ -0,0 +1,5 @@ +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=n +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 diff --git a/projects/coreboot/configs/nyan/big/corebootfb/16mb/depthcharge/config b/projects/coreboot/configs/nyan/big/corebootfb/16mb/depthcharge/config new file mode 100644 index 00000000..4fb44ffa --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/16mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-nyan-big/depthcharge.elf" diff --git a/projects/coreboot/configs/nyan/big/corebootfb/16mb/targets b/projects/coreboot/configs/nyan/big/corebootfb/16mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/16mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/nyan/big/corebootfb/4mb/config b/projects/coreboot/configs/nyan/big/corebootfb/4mb/config new file mode 100644 index 00000000..f8445518 --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/4mb/config @@ -0,0 +1,4 @@ +CONFIG_CBFS_SIZE=0x400000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 diff --git a/projects/coreboot/configs/nyan/big/corebootfb/4mb/depthcharge/config b/projects/coreboot/configs/nyan/big/corebootfb/4mb/depthcharge/config new file mode 100644 index 00000000..4fb44ffa --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/4mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-nyan-big/depthcharge.elf" diff --git a/projects/coreboot/configs/nyan/big/corebootfb/4mb/targets b/projects/coreboot/configs/nyan/big/corebootfb/4mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/4mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/nyan/big/corebootfb/targets b/projects/coreboot/configs/nyan/big/corebootfb/targets new file mode 100644 index 00000000..0169dcf0 --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/targets @@ -0,0 +1,2 @@ +16mb +4mb diff --git a/projects/coreboot/configs/nyan/big/targets b/projects/coreboot/configs/nyan/big/targets new file mode 100644 index 00000000..ffc50041 --- /dev/null +++ b/projects/coreboot/configs/nyan/big/targets @@ -0,0 +1 @@ +corebootfb diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/config b/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/config new file mode 100644 index 00000000..d3e3b7aa --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/config @@ -0,0 +1,5 @@ +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=n +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/depthcharge/config b/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/depthcharge/config new file mode 100644 index 00000000..1a6c06bc --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-nyan-blaze/depthcharge.elf" diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/targets b/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/config b/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/config new file mode 100644 index 00000000..f8445518 --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/config @@ -0,0 +1,4 @@ +CONFIG_CBFS_SIZE=0x400000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/depthcharge/config b/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/depthcharge/config new file mode 100644 index 00000000..1a6c06bc --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-nyan-blaze/depthcharge.elf" diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/targets b/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/targets b/projects/coreboot/configs/nyan/blaze/corebootfb/targets new file mode 100644 index 00000000..0169dcf0 --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/targets @@ -0,0 +1,2 @@ +16mb +4mb diff --git a/projects/coreboot/configs/nyan/blaze/targets b/projects/coreboot/configs/nyan/blaze/targets new file mode 100644 index 00000000..ffc50041 --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/targets @@ -0,0 +1 @@ +corebootfb diff --git a/projects/coreboot/configs/veyron/jerry/config b/projects/coreboot/configs/veyron/jerry/config index 9393e7de..30c978cf 100644 --- a/projects/coreboot/configs/veyron/jerry/config +++ b/projects/coreboot/configs/veyron/jerry/config @@ -110,7 +110,7 @@ CONFIG_MAINBOARD_PART_NUMBER="Veyron_Jerry" CONFIG_MAINBOARD_VENDOR="Google" CONFIG_MAX_CPUS=1 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 -CONFIG_CBFS_SIZE=0x100000 +CONFIG_CBFS_SIZE=0x400000 CONFIG_UART_FOR_CONSOLE=0 CONFIG_DIMM_SPD_SIZE=256 CONFIG_DEVICETREE="devicetree.cb" diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/config b/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/config new file mode 100644 index 00000000..d3e3b7aa --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/config @@ -0,0 +1,5 @@ +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=n +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/depthcharge/config b/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/depthcharge/config new file mode 100644 index 00000000..afde4a80 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-jerry/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/targets b/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/config b/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/config new file mode 100644 index 00000000..f8445518 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/config @@ -0,0 +1,4 @@ +CONFIG_CBFS_SIZE=0x400000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/depthcharge/config b/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/depthcharge/config new file mode 100644 index 00000000..afde4a80 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-jerry/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/targets b/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/targets b/projects/coreboot/configs/veyron/jerry/corebootfb/targets new file mode 100644 index 00000000..0169dcf0 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/targets @@ -0,0 +1,2 @@ +16mb +4mb diff --git a/projects/coreboot/configs/veyron/jerry/targets b/projects/coreboot/configs/veyron/jerry/targets new file mode 100644 index 00000000..ffc50041 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/targets @@ -0,0 +1 @@ +corebootfb diff --git a/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/config b/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/config new file mode 100644 index 00000000..f8445518 --- /dev/null +++ b/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/config @@ -0,0 +1,4 @@ +CONFIG_CBFS_SIZE=0x400000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 diff --git a/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/depthcharge/config b/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/depthcharge/config new file mode 100644 index 00000000..e27c1a5b --- /dev/null +++ b/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-mickey/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/targets b/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/mickey/corebootfb/targets b/projects/coreboot/configs/veyron/mickey/corebootfb/targets new file mode 100644 index 00000000..50d4bf27 --- /dev/null +++ b/projects/coreboot/configs/veyron/mickey/corebootfb/targets @@ -0,0 +1 @@ +4mb diff --git a/projects/coreboot/configs/veyron/mickey/targets b/projects/coreboot/configs/veyron/mickey/targets new file mode 100644 index 00000000..ffc50041 --- /dev/null +++ b/projects/coreboot/configs/veyron/mickey/targets @@ -0,0 +1 @@ +corebootfb diff --git a/projects/coreboot/configs/veyron/minnie/config b/projects/coreboot/configs/veyron/minnie/config index 45672bc9..d9d9206e 100644 --- a/projects/coreboot/configs/veyron/minnie/config +++ b/projects/coreboot/configs/veyron/minnie/config @@ -110,7 +110,7 @@ CONFIG_MAINBOARD_PART_NUMBER="Veyron_Minnie" CONFIG_MAINBOARD_VENDOR="Google" CONFIG_MAX_CPUS=1 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 -CONFIG_CBFS_SIZE=0x100000 +CONFIG_CBFS_SIZE=0x400000 CONFIG_UART_FOR_CONSOLE=0 CONFIG_DIMM_SPD_SIZE=256 CONFIG_DEVICETREE="devicetree.cb" diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/config b/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/config new file mode 100644 index 00000000..d3e3b7aa --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/config @@ -0,0 +1,5 @@ +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=n +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/depthcharge/config b/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/depthcharge/config new file mode 100644 index 00000000..aee1ccef --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-minnie/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/targets b/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/config b/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/config new file mode 100644 index 00000000..f8445518 --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/config @@ -0,0 +1,4 @@ +CONFIG_CBFS_SIZE=0x400000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/depthcharge/config b/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/depthcharge/config new file mode 100644 index 00000000..aee1ccef --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-minnie/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/targets b/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/targets b/projects/coreboot/configs/veyron/minnie/corebootfb/targets new file mode 100644 index 00000000..0169dcf0 --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/targets @@ -0,0 +1,2 @@ +16mb +4mb diff --git a/projects/coreboot/configs/veyron/minnie/targets b/projects/coreboot/configs/veyron/minnie/targets new file mode 100644 index 00000000..ffc50041 --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/targets @@ -0,0 +1 @@ +corebootfb diff --git a/projects/coreboot/configs/veyron/speedy/config b/projects/coreboot/configs/veyron/speedy/config index b4a74b9a..27ddca6b 100644 --- a/projects/coreboot/configs/veyron/speedy/config +++ b/projects/coreboot/configs/veyron/speedy/config @@ -110,7 +110,7 @@ CONFIG_MAINBOARD_PART_NUMBER="Veyron_Speedy" CONFIG_MAINBOARD_VENDOR="Google" CONFIG_MAX_CPUS=1 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 -CONFIG_CBFS_SIZE=0x100000 +CONFIG_CBFS_SIZE=0x400000 CONFIG_UART_FOR_CONSOLE=0 CONFIG_DIMM_SPD_SIZE=256 CONFIG_DEVICETREE="devicetree.cb" diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/config b/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/config new file mode 100644 index 00000000..d3e3b7aa --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/config @@ -0,0 +1,5 @@ +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=n +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/depthcharge/config b/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/depthcharge/config new file mode 100644 index 00000000..8b705934 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-speedy/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/targets b/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/config b/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/config new file mode 100644 index 00000000..f8445518 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/config @@ -0,0 +1,4 @@ +CONFIG_CBFS_SIZE=0x400000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/depthcharge/config b/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/depthcharge/config new file mode 100644 index 00000000..8b705934 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-speedy/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/targets b/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/targets b/projects/coreboot/configs/veyron/speedy/corebootfb/targets new file mode 100644 index 00000000..0169dcf0 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/targets @@ -0,0 +1,2 @@ +16mb +4mb diff --git a/projects/coreboot/configs/veyron/speedy/targets b/projects/coreboot/configs/veyron/speedy/targets new file mode 100644 index 00000000..ffc50041 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/targets @@ -0,0 +1 @@ +corebootfb diff --git a/projects/cros-ec/configs/nyan/revision b/projects/cros-ec/configs/nyan/revision index 6ce6b84b..c5b2d348 100644 --- a/projects/cros-ec/configs/nyan/revision +++ b/projects/cros-ec/configs/nyan/revision @@ -1 +1 @@ -origin/release-R65-10323.B +origin/firmware-nyan-5771.B diff --git a/projects/cros-ec/configs/veyron/revision b/projects/cros-ec/configs/veyron/revision index 6ce6b84b..6c728396 100644 --- a/projects/cros-ec/configs/veyron/revision +++ b/projects/cros-ec/configs/veyron/revision @@ -1 +1 @@ -origin/release-R65-10323.B +origin/firmware-veyron-6588.B diff --git a/projects/cros-ec/patches/veyron/0005-Don-t-include-missing-and-unnecessary-math-header.patch b/projects/cros-ec/patches/veyron/0005-Don-t-include-missing-and-unnecessary-math-header.patch deleted file mode 100644 index 0a099213..00000000 --- a/projects/cros-ec/patches/veyron/0005-Don-t-include-missing-and-unnecessary-math-header.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 913b2f1265bd7f3ebe6cf4cba92c20c5a423a6c3 Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski <contact@paulk.fr> -Date: Tue, 2 Aug 2016 12:05:55 +0200 -Subject: [PATCH 5/6] Don't include missing and unnecessary math header - -This removes the inclusion of an unnecessary math header that is neither -found nor necessary for non-cortex-m ECs. - -Change-Id: I56a04178dadedb76f841504fa645e2d43900d25f -Signed-off-by: Paul Kocialkowski <contact@paulk.fr> ---- - common/math_util.c | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/common/math_util.c b/common/math_util.c -index 120d13d..34a267d 100644 ---- a/common/math_util.c -+++ b/common/math_util.c -@@ -6,7 +6,6 @@ - /* Common math functions. */ - - #include "common.h" --#include "math.h" - #include "math_util.h" - #include "util.h" - --- -2.9.0 - diff --git a/projects/cros-ec/patches/veyron/0006-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch b/projects/cros-ec/patches/veyron/0005-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch index f0175825..b70e471e 100644 --- a/projects/cros-ec/patches/veyron/0006-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch +++ b/projects/cros-ec/patches/veyron/0005-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch @@ -1,8 +1,7 @@ -From 9dd7ae82d3f3fa9dae31a442365e233a0b44cce3 Mon Sep 17 00:00:00 2001 +From 27501308493bf2adadfc3b133fd1d6f4b4feec12 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski <contact@paulk.fr> Date: Sat, 23 Jul 2016 14:17:32 +0200 -Subject: [PATCH 6/6] cortex-m0: Use assembly exception handlers for task - switching +Subject: [PATCH] cortex-m0: Use assembly exception handlers for task switching The way Cortex processors handle exceptions allows writing exception routines directly in C, as return from exception is handled by providing @@ -38,15 +37,12 @@ TEST=Build and run speedy EC with a recent GCC version Change-Id: Ib068bc12ce2204aee3e0f563efcb94f15aa87013 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> --- - core/cortex-m0/switch.S | 81 ++++++++++++++++++++++++++++++++++--------------- - core/cortex-m0/task.c | 27 +---------------- - 2 files changed, 58 insertions(+), 50 deletions(-) diff --git a/core/cortex-m0/switch.S b/core/cortex-m0/switch.S index 95ea29e..d4b47cd 100644 --- a/core/cortex-m0/switch.S +++ b/core/cortex-m0/switch.S -@@ -7,12 +7,52 @@ +@@ -7,55 +7,14 @@ #include "config.h" @@ -58,29 +54,56 @@ index 95ea29e..d4b47cd 100644 .code 16 /** -+ * Start the task scheduling. r0 is a pointer to task_stack_ready, which is -+ * set to 1 after the task stack is set up. -+ */ -+.global __task_start -+.thumb_func -+__task_start: -+ ldr r2,=scratchpad @ area used as dummy thread stack for the first switch -+ movs r3, #2 @ use : priv. mode / thread stack / no floating point -+ adds r2, #17*4 @ put the pointer at the top of the stack -+ movs r1, #0 @ __Schedule parameter : re-schedule nothing -+ msr psp, r2 @ setup a thread stack up to the first context switch -+ movs r2, #1 -+ isb @ ensure the write is done -+ msr control, r3 -+ movs r3, r0 -+ movs r0, #0 @ __Schedule parameter : de-schedule nothing -+ isb @ ensure the write is done -+ str r2, [r3] @ Task scheduling is now active -+ bl __schedule @ execute the task with the highest priority -+ /* we should never return here */ -+ movs r0, #1 @ set to EC_ERROR_UNKNOWN -+ bx lr -+ +- * Task context switching +- * +- * Change the task scheduled after returning from the exception. +- * +- * Save the registers of the current task below the exception context on +- * its task, then restore the live registers of the next task and set the +- * process stack pointer to the new stack. +- * +- * r0: pointer to the task to switch from +- * r1: pointer to the task to switch to +- * +- * must be called from interrupt context +- * +- * the structure of the saved context on the stack is : +- * r8, r9, r10, r11, r4, r5, r6, r7, r0, r1, r2, r3, r12, lr, pc, psr +- * additional registers <|> exception frame +- */ +-.global __switchto +-.thumb_func +-__switchto: +- mrs r2, psp @ get the task stack where the context has been saved +- mov r3, sp +- mov sp, r2 +- push {r4-r7} @ save additional r4-r7 in the task stack +- mov r4, r8 +- mov r5, r9 +- mov r6, r10 +- mov r7, r11 +- push {r4-r7} @ save additional r8-r11 in the task stack +- mov r2, sp @ prepare to save former task stack pointer +- mov sp, r3 @ restore system stack pointer +- str r2, [r0] @ save the task stack pointer in its context +- ldr r2, [r1] @ get the new scheduled task stack pointer +- ldmia r2!, {r4-r7} @ restore r8-r11 for the next task context +- mov r8, r4 +- mov r9, r5 +- mov r10, r6 +- mov r11, r7 +- ldmia r2!, {r4-r7} @ restore r4-r7 for the next task context +- msr psp, r2 @ set the process stack pointer to exception context +- bx lr @ return from exception +- +-/** + * Start the task scheduling. r0 is a pointer to task_stack_ready, which is + * set to 1 after the task stack is set up. + */ +@@ -79,3 +38,77 @@ + movs r0, #1 @ set to EC_ERROR_UNKNOWN + bx lr + +/** + * SVC exception handler + */ @@ -96,53 +119,53 @@ index 95ea29e..d4b47cd 100644 + /* continue to __switchto to switch to the new task */ + +/** - * Task context switching - * - * Change the task scheduled after returning from the exception. -@@ -30,8 +70,6 @@ - * r8, r9, r10, r11, r4, r5, r6, r7, r0, r1, r2, r3, r12, lr, pc, psr - * additional registers <|> exception frame - */ --.global __switchto --.thumb_func - __switchto: - mrs r2, psp @ get the task stack where the context has been saved - mov r3, sp -@@ -53,29 +91,24 @@ __switchto: - mov r11, r7 - ldmia r2!, {r4-r7} @ restore r4-r7 for the next task context - msr psp, r2 @ set the process stack pointer to exception context -- bx lr @ return from exception ++ * Task context switching ++ * ++ * Change the task scheduled after returning from the exception. ++ * ++ * Save the registers of the current task below the exception context on ++ * its task, then restore the live registers of the next task and set the ++ * process stack pointer to the new stack. ++ * ++ * r0: pointer to the task to switch from ++ * r1: pointer to the task to switch to ++ * ++ * must be called from interrupt context ++ * ++ * the structure of the saved context on the stack is : ++ * r8, r9, r10, r11, r4, r5, r6, r7, r0, r1, r2, r3, r12, lr, pc, psr ++ * additional registers <|> exception frame ++ */ ++__switchto: ++ mrs r2, psp @ get the task stack where the context has been saved ++ mov r3, sp ++ mov sp, r2 ++ push {r4-r7} @ save additional r4-r7 in the task stack ++ mov r4, r8 ++ mov r5, r9 ++ mov r6, r10 ++ mov r7, r11 ++ push {r4-r7} @ save additional r8-r11 in the task stack ++ mov r2, sp @ prepare to save former task stack pointer ++ mov sp, r3 @ restore system stack pointer ++ str r2, [r0] @ save the task stack pointer in its context ++ ldr r2, [r1] @ get the new scheduled task stack pointer ++ ldmia r2!, {r4-r7} @ restore r8-r11 for the next task context ++ mov r8, r4 ++ mov r9, r5 ++ mov r10, r6 ++ mov r11, r7 ++ ldmia r2!, {r4-r7} @ restore r4-r7 for the next task context ++ msr psp, r2 @ set the process stack pointer to exception context + +svc_handler_return: + pop {pc} @ return from exception or return to caller - - /** -- * Start the task scheduling. r0 is a pointer to task_stack_ready, which is -- * set to 1 after the task stack is set up. ++ ++/** + * PendSVC exception handler - */ --.global __task_start ++ */ +.global pendsv_handler - .thumb_func --__task_start: -- ldr r2,=scratchpad @ area used as dummy thread stack for the first switch -- movs r3, #2 @ use : priv. mode / thread stack / no floating point -- adds r2, #17*4 @ put the pointer at the top of the stack -- movs r1, #0 @ __Schedule parameter : re-schedule nothing -- msr psp, r2 @ setup a thread stack up to the first context switch -- movs r2, #1 -- isb @ ensure the write is done -- msr control, r3 -- movs r3, r0 -- movs r0, #0 @ __Schedule parameter : de-schedule nothing -- isb @ ensure the write is done -- str r2, [r3] @ Task scheduling is now active -- bl __schedule @ execute the task with the highest priority -- /* we should never return here */ -- movs r0, #1 @ set to EC_ERROR_UNKNOWN -- bx lr -- ++.thumb_func +pendsv_handler: + push {lr} @ save link register + ldr r0, =#CPU_SCB_ICSR @ load CPU_SCB_ICSR's address @@ -156,10 +179,10 @@ index 95ea29e..d4b47cd 100644 + cpsie i @ leave priority 0 + pop {pc} @ return from exception diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c -index e51621b..f96ccf8 100644 +index 5d219a5..0261261 100644 --- a/core/cortex-m0/task.c +++ b/core/cortex-m0/task.c -@@ -57,7 +57,6 @@ static uint32_t task_switches; /* Number of times active task changed */ +@@ -59,7 +59,6 @@ static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ #endif @@ -167,7 +190,7 @@ index e51621b..f96ccf8 100644 extern int __task_start(int *task_stack_ready); #ifndef CONFIG_LOW_POWER_IDLE -@@ -120,7 +119,7 @@ uint8_t task_stacks[0 +@@ -124,7 +123,7 @@ /* Reserve space to discard context on first context switch. */ uint32_t scratchpad[17]; @@ -176,7 +199,7 @@ index e51621b..f96ccf8 100644 /* * Bitmap of all tasks ready to be run. -@@ -242,18 +241,6 @@ task_ *__svc_handler(int desched, task_id_t resched) +@@ -254,18 +253,6 @@ return current; } @@ -195,7 +218,7 @@ index e51621b..f96ccf8 100644 void __schedule(int desched, int resched) { register int p0 asm("r0") = desched; -@@ -262,18 +249,6 @@ void __schedule(int desched, int resched) +@@ -274,18 +261,6 @@ asm("svc 0" : : "r"(p0), "r"(p1)); } @@ -214,6 +237,3 @@ index e51621b..f96ccf8 100644 #ifdef CONFIG_TASK_PROFILING void task_start_irq_handler(void *excep_return) { --- -2.9.0 - diff --git a/projects/depthcharge/configs/nyan/targets b/projects/depthcharge/configs/nyan/targets new file mode 100644 index 00000000..419aafc5 --- /dev/null +++ b/projects/depthcharge/configs/nyan/targets @@ -0,0 +1,2 @@ +big +blaze diff --git a/projects/depthcharge/configs/veyron/targets b/projects/depthcharge/configs/veyron/targets index 1722192f..e4c9ca9e 100644 --- a/projects/depthcharge/configs/veyron/targets +++ b/projects/depthcharge/configs/veyron/targets @@ -1,2 +1,4 @@ +jerry +mickey minnie speedy diff --git a/www/download.md b/www/download.md index fc58adca..221ff2fa 100644 --- a/www/download.md +++ b/www/download.md @@ -59,6 +59,8 @@ university, USA) <https://mirror-hk.koddos.net/libreboot/> (koddos.net, Hong Kong) +<https://mirror.cyberbits.eu/libreboot/> (cyberbits.eu, France) + RSYNC mirrors {#rsync} ------------- @@ -102,6 +104,8 @@ if using HTTPS. <http://mirror.helium.in-berlin.de/libreboot/> (in-berlin.de, Germany) +<http://mirror.cyberbits.eu/libreboot/> (cyberbits.eu, France) + FTP mirrors {#ftp} ----------- @@ -149,6 +149,87 @@ cryptomount command from `for` loop in libreboot's It could be fixed in upstream grub by contributing patch that would add quiet flag to it. +How to save kernel panic logs on thinkpad laptops? +-------------------------------------------------- + +The easiest method of doing so is by using the kernel's netconsole +and reproducing the panic. Netconsole requires two machines, the one that is +panicky (source) and the one that will receive crash logs (target). The +source has to be connected with an ethernet cable and the target has to be +reachable at the time of the panic. To set this system up, execute the +following commands as root on the source (`source#`) and normal user on +the target (`target$`): + +1. Start a listener server on the target machine (netcat works well): + + `target$ nc -u -l -p 6666` + +2. Mount configfs (only once per boot, you can check if it is already mounted + with `mount | grep /sys/kernel/config`. This will return no output + if it is not). + + `source# modprobe configfs` + + `source# mkdir -p /sys/kernel/config` + + `source# mount none -t configfs /sys/kernel/config` + +3. find source's ethernet interface name, it should be of the form `enp*` or + `eth*`, see `ip address` or `ifconfig` output. + + `source# iface="enp0s29f8u1"` change this + + Fill the target machine's IPv4 address here: + + `source# tgtip="192.168.1.2"` change this + + +3. Create netconsole logging target on the source machine: + + `source# modprobe netconsole` + + `source# cd /sys/kernel/config/netconsole` + + `source# mkdir target1; cd target1` + + `source# srcip=$(ip -4 addr show dev "$iface" | grep -Eo '[0-9]+\.[0-9]+\.[0-9]+\.[0-9]+')` + + `source# echo "$srcip" > local_ip` + + `source# echo "$tgtip" > remote_ip` + + `source# echo "$iface" > dev_name` + + `source# arping -I "$iface" "$tgtip" -f | grep -o '..:..:..:..:..:..' > remote_mac` + + `source# echo 1 > enabled` + +4. Change console loglevel to debugging: + + `source# dmesg -n debug` + +5. Test if the logging works by e.g. inserting or removing an USB + device on the source. There should be a few lines appearing in the + terminal, in which you started netcat (nc), on the target host. + +6. Try to reproduce the kernel panic. + +Machine check exceptions on some Montevina (Penryn CPU) laptops +--------------------------------------------------------------- + +Some GM45 laptops have been freezing or experiencing a kernel panic +(blinking caps lock LED and totaly unresponsive machine, sometimes followed +by an automatic reboot within 30 seconds). +We do not know what the problem(s) is(are), but a CPU microcode +update in some cases prevents this from happening again. +See the following bug reports for more info: + +- [T400 Machine check: Processor context corrupt](https://notabug.org/libreboot/libreboot/issues/493) +- [X200 Machine check: Processor context corrupt](https://notabug.org/libreboot/libreboot/issues/289) + +- [Unrelated, RAM incompatibility and suspend-to-ram issues on X200](https://libreboot.org/docs/hardware/x200.html#ram_s3_microcode) + + Hardware compatibility ====================== @@ -1070,3 +1151,5 @@ Where can I learn more about electronics which is free software under MIT license. Use of youtube-dl with mpv would be recommended for youtube links + +Lastly the most important message to everybody gaining this wonderful new hobby - [Secret to Learning Electronics](https://www.youtube.com/watch?v=xhQ7d3BK3KQ) diff --git a/www/news/MANIFEST b/www/news/MANIFEST index 0e7cc034..e3b990e8 100644 --- a/www/news/MANIFEST +++ b/www/news/MANIFEST @@ -1,3 +1,4 @@ +news/freenode2018-workshop.md news/leah-fundraiser.md news/libreplanet2018-workshop.md news/release-testing-20171221.md diff --git a/www/news/freenode2018-workshop.md b/www/news/freenode2018-workshop.md new file mode 100644 index 00000000..9135e895 --- /dev/null +++ b/www/news/freenode2018-workshop.md @@ -0,0 +1,16 @@ +% Libreboot workshop at Freenode #live 2018 Conference in Bristol, UK +% Leah Rowe +% 2 November 2018 + +Freenode #live is the annual conference held by +[Freenode](https://freenode.net/) in Bristol, UK. This year I, Leah Rowe, will +be there doing a talk about Libreboot at 10AM (UTC +0) on November 3rd. In +addition, I have decided (hence this announcement) at the last minute that I'm +taking my SPI flashing equipment with me. More details about this conference +are on the Freenode #live website: <https://freenode.live/> + +If anyone attending this conference wants their system flashed with Libreboot, +bring it to the conference. I'll be volunteering at the FSF booth there all +day on both Saturday and Sunday. + +I will also be representing the FSF as a volunteer on both days. |