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152 files changed, 3438 insertions, 8947 deletions
diff --git a/docs/bsd/freebsd.md b/docs/bsd/freebsd.md index a21e309b..0148cf2f 100644 --- a/docs/bsd/freebsd.md +++ b/docs/bsd/freebsd.md @@ -1,5 +1,6 @@ --- title: How to install FreeBSD on a libreboot system +x-toc-enable: true ... This section relates to preparing, booting and installing FreeBSD on @@ -19,13 +20,6 @@ if it does not). Instructions are provided here, to boot and install FreeBSD but we're not sure whether it is currently fully compatible with libreboot. -- [Prepare the USB drive (in FreeBSD)](#prepare) -- [Installing FreeBSD without full disk encryption](#noencryption) -- [Installing FreeBSD with full disk encryption](#encryption) -- [Booting](#booting) -- [Configuring Grub](#configuring_grub) -- [Troubleshooting](#troubleshooting) - **This section is only for the GRUB payload. For depthcharge (used on CrOS devices in libreboot), instructions have yet to be written in the libreboot documentation.** @@ -85,6 +79,7 @@ the bootable FreeBSD USB drive: Connect the USB drive. Check dmesg: $ dmesg + Check lsblk to confirm which drive it is: $ lsblk @@ -143,7 +138,7 @@ because it doesn't exist. In most cases, you should use the vesafb ROM images. Example filename: libreboot\_ukdvorak\_vesafb.rom. -won't boot\...something about file not found +won't boot...something about file not found --------------------------------------------- Your device names (i.e. usb0, usb1, sd0, sd1, wd0, ahci0, hd0, etc) and @@ -151,4 +146,9 @@ numbers may differ. Use TAB completion. Copyright © 2016 Leah Rowe <info@minifree.org>\ Copyright © 2016 Scott Bonds <scott@ggr.com>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/bsd/index.md b/docs/bsd/index.md index c313128d..6fc5d7e6 100644 --- a/docs/bsd/index.md +++ b/docs/bsd/index.md @@ -15,4 +15,9 @@ instructions have yet to be written.** - [How to install FreeBSD on a libreboot system](freebsd.md) Copyright © 2016 Scott Bonds <scott@ggr.com>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/bsd/netbsd.md b/docs/bsd/netbsd.md index 2e52b376..226b3b96 100644 --- a/docs/bsd/netbsd.md +++ b/docs/bsd/netbsd.md @@ -1,5 +1,6 @@ --- title: How to install NetBSD on a libreboot system +x-toc-enable: true ... This section relates to preparing, booting and installing NetBSD on your @@ -14,13 +15,6 @@ Thanks go to ioxcide in [this Reddit post](https://www.reddit.com/r/BSD/comments/53jt70/libreboot_and_bsds/) for the initial instructions. -- [Prepare the USB drive (in NetBSD)](#prepare) -- [Installing NetBSD without full disk encryption](#noencryption) -- [Installing NetBSD with full disk encryption](#encryption) -- [Booting](#booting) -- [Configuring Grub](#configuring_grub) -- [Troubleshooting](#troubleshooting) - **This section is only for the GRUB payload. For depthcharge (used on CrOS devices in libreboot), instructions have yet to be written in the libreboot documentation.** @@ -81,6 +75,7 @@ the bootable NetBSD USB drive: Connect the USB drive. Check dmesg: $ dmesg + Check lsblk to confirm which drive it is: $ lsblk @@ -135,14 +130,13 @@ command to boot NetBSD every time, you can create a GRUB configuration that's aware of your NetBSD installation and that will automatically be used by libreboot. -On your NetBSD root partition, create the **/grub** directory and add -the file **libreboot\_grub.cfg** to it. Inside the -**libreboot\_grub.cfg** add these lines: +On your NetBSD root partition, create the `/grub` directory and add +the file `libreboot_grub.cfg` to it. Inside the +`libreboot_grub.cfg` add these lines: -**default=0 timeout=3 menuentry "NetBSD" {\ -    knetbsd -r wd0a (ahci0,netbsd1)/netbsd\ -}\ -** + default=0 timeout=3 menuentry "NetBSD" { +    knetbsd -r wd0a (ahci0,netbsd1)/netbsd + } The next time you boot, you'll see the old Grub menu for a few seconds, then you'll see the a new menu with only NetBSD on the list. After 3 @@ -160,7 +154,7 @@ because it doesn't exist. In most cases, you should use the vesafb ROM images. Example filename: libreboot\_ukdvorak\_vesafb.rom. -won't boot\...something about file not found +won't boot...something about file not found --------------------------------------------- Your device names (i.e. usb0, usb1, sd0, sd1, wd0, ahci0, hd0, etc) and @@ -168,4 +162,9 @@ numbers may differ. Use TAB completion. Copyright © 2016 Leah Rowe <info@minifree.org>\ Copyright © 2016 Scott Bonds <scott@ggr.com>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/bsd/openbsd.md b/docs/bsd/openbsd.md index c86eb39e..8c33e5df 100644 --- a/docs/bsd/openbsd.md +++ b/docs/bsd/openbsd.md @@ -1,5 +1,6 @@ --- title: How to install LibertyBSD or OpenBSD on a libreboot system +x-toc-enable: true ... NOTE: This guide was written for OpenBSD by the person who contributed @@ -13,13 +14,6 @@ This section relates to preparing, booting and installing OpenBSD on your libreboot system, using nothing more than a USB flash drive (and *dd*). They've only been tested on a Lenovo ThinkPad x200. -- [Prepare the USB drive (in OpenBSD)](#prepare) -- [Installing OpenBSD without full disk encryption](#noencryption) -- [Installing OpenBSD with full disk encryption](#encryption) -- [Booting](#booting) -- [Configuring Grub](#configuring_grub) -- [Troubleshooting](#troubleshooting) - **This section is only for the GRUB payload. For depthcharge (used on CrOS devices in libreboot), instructions have yet to be written in the libreboot documentation.** @@ -80,6 +74,7 @@ the bootable OpenBSD USB drive: Connect the USB drive. Check dmesg: $ dmesg + Check lsblk to confirm which drive it is: $ lsblk @@ -156,14 +151,12 @@ command to boot OpenBSD every time, you can create a GRUB configuration that's aware of your OpenBSD installation and that will automatically be used by libreboot. -On your OpenBSD root partition, create the **/grub** directory and add -the file **libreboot\_grub.cfg** to it. Inside the -**libreboot\_grub.cfg** add these lines: +On your OpenBSD root partition, create the `/grub` directory and add the file +`libreboot_grub.cfg` to it. Inside the `libreboot_grub.cfg` add these lines: -**default=0 timeout=3 menuentry "OpenBSD" {\ -    kopenbsd -r sd0a (ahci0,openbsd1)/bsd\ -}\ -** + default=0 timeout=3 menuentry "OpenBSD" { +    kopenbsd -r sd0a (ahci0,openbsd1)/bsd + } The next time you boot, you'll see the old Grub menu for a few seconds, then you'll see the a new menu with only OpenBSD on the list. After 3 @@ -181,7 +174,7 @@ because it doesn't exist. In most cases, you should use the vesafb ROM images. Example filename: libreboot\_ukdvorak\_vesafb.rom. -won't boot\...something about file not found +Won't boot...something about file not found --------------------------------------------- Your device names (i.e. usb0, usb1, sd0, sd1, wd0, ahci0, hd0, etc) and @@ -189,4 +182,9 @@ numbers may differ. Use TAB completion. Copyright © 2016 Scott Bonds <scott@ggr.com>\ Copyright © 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/depthcharge/index.md b/docs/depthcharge/index.md index cd9a3943..1c0c8d13 100644 --- a/docs/depthcharge/index.md +++ b/docs/depthcharge/index.md @@ -1,24 +1,11 @@ --- title: Depthcharge payload +x-toc-enable: true ... This section relates to the depthcharge payload used in libreboot. -- [CrOS security model](#cros_security_model) -- [Developer mode screen](#developer_mode_screen) - - Holding the developer mode screen - - Booting normally - - Booting from different mediums - - Showing device information - - Warnings - -- [Recovery mode screen](#recovery_mode_screen) - - [Recovering from a bad state](#recovering_bad_state) - - [Enabling developer mode](#enabling_developer_mode) -- [Configuring verified boot - parameters](#configuring_verified_boot_parameters) - -CrOS security model {#cros_security_model} +CrOS security model =================== CrOS (Chromium OS/Chrome OS) devices such as Chromebooks implement a @@ -32,27 +19,24 @@ kernels without verifying their signature and booting from external media or legacy payload unless explicitly allowed: see [configuring verified boot parameters](#configuring_verified_boot_parameters). -Developer mode screen {#developer_mode_screen} +Developer mode screen ===================== -The developer mode screen can be accessed in depthcharge when developer -mode is enabled.\ -Developer mode can be enabled from the [recovery mode -screen](#recovery_mode_screen). +The developer mode screen can be accessed in depthcharge when developer mode is +enabled. Developer mode can be enabled from the recovery mode screen. It allows booting normally, booting from internal storage, booting from -external media (when enabled), booting from legacy payload (when -enabled), showing information about the device and disabling developer -mode. +external media (when enabled), booting from legacy payload (when enabled), +showing information about the device and disabling developer mode. -Holding the developer mode screen {#holding_developer_mode_screen} +Holding the developer mode screen --------------------------------- As instructed on the developer mode screen, the screen can be held by pressing **Ctrl + H** in the first 3 seconds after the screen is shown. After that delay, depthcharge will resume booting normally. -Booting normally {#booting_normally} +Booting normally ---------------- As instructed on the developer mode screen, a regular boot will happen @@ -60,7 +44,7 @@ after **3 seconds** (if developer mode screen is not held).\ The default boot medium (internal storage, external media, legacy payload) is shown on screen. -Booting from different mediums {#booting_different_mediums} +Booting from different mediums ------------------------------ Depthcharge allows booting from different mediums, when they are allowed @@ -74,13 +58,12 @@ can be triggered by pressing various key combinations: - External media: **Ctrl + U** (when enabled) - Legacy payload: **Ctrl + L** (when enabled) -Showing device information {#showing_device_information} +Showing device information -------------------------- -As instructed on the developer mode screen, showing device information -can be triggered by pressing **Ctrl + I** or **Tab**.\ -Various information is shown, including vboot non-volatile data, TPM -status, GBB flags and key hashes.\ +As instructed on the developer mode screen, showing device information can be +triggered by pressing **Ctrl + I** or **Tab**. Various information is shown, +including vboot non-volatile data, TPM status, GBB flags and key hashes. Warnings -------- @@ -91,7 +74,7 @@ The developer mode screen will show warnings when: - Booting from external media is enabled - Booting legacy payloads is enabled -Recovery mode screen {#recovery_mode_screen} +Recovery mode screen ==================== The recovery mode screen can be accessed in depthcharge, by pressing @@ -101,7 +84,7 @@ It allows recovering the device from a bad state by booting from a trusted recovery media. When accessed with the device in a good state, it also allows enabling developer mode. -Recovering from a bad state {#recovering_bad_state} +Recovering from a bad state --------------------------- When the device fails to verify the signature of a piece of the boot @@ -127,15 +110,14 @@ replaced. When the recovery private key is available (e.g. when using self-generated keys), it can be used to sign a kernel for recovery purposes. -Enabling developer mode {#enabling_developer_mode} +Enabling developer mode ----------------------- As instructed on the recovery mode screen, developer mode can be enabled -by pressing **Ctrl + D**.\ -Instructions to confirm enabling developer mode are then shown on -screen. +by pressing **Ctrl + D**. Instructions to confirm enabling developer mode are +then shown on screen. -Configuring verified boot parameters {#configuring_verified_boot_parameters} +Configuring verified boot parameters ==================================== Depthcharge's behavior relies on the verified boot (vboot) reference @@ -161,37 +143,32 @@ security of the device. The following parameters can be configured: -- Kernels signature verification: - - Enabled with: +Kernels signature verification: - \# **crossystem dev\_boot\_signed\_only=1** - - Disabled with: + # crossystem dev_boot_signed_only=1 # enable + # crossystem dev_boot_signed_only=0 # disable - \# **crossystem dev\_boot\_signed\_only=0** -- External media boot: - - Enabled with: +External media boot: - \# **crossystem dev\_boot\_usb=1** - - Disabled with: + # crossystem dev_boot_usb=1 # enable + # crossystem dev_boot_usb=0 # disable - \# **crossystem dev\_boot\_usb=0** -- Legacy payload boot: - - Enabled with: +Legacy payload boot: - \# **crossystem dev\_boot\_legacy=1** - - Disabled with: + # crossystem dev_boot_legacy=1 # enable + # crossystem dev_boot_legacy=0 # disable - \# **crossystem dev\_boot\_legacy=0** -- Default boot medium: - - Internal storage: +Default boot medium: - \# **crossystem dev\_default\_boot=disk** - - External media: + # crossystem dev_default_boot=disk # internal storage + # crossystem dev_default_boot=usb # external media + # crossystem dev_default_boot=legacy # legacy payload - \# **crossystem dev\_default\_boot=usb** - - Legacy payload: - - \# **crossystem dev\_default\_boot=legacy** Copyright © 2015 Paul Kocialkowski <contact@paulk.fr>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/fdl-1.3.md b/docs/fdl-1.3.md new file mode 100644 index 00000000..0f883f0c --- /dev/null +++ b/docs/fdl-1.3.md @@ -0,0 +1,449 @@ +--- +title: GNU Free Documentation License +... + +Version 1.3, 3 November 2008 + +Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, +Inc. <http://fsf.org/> + +Everyone is permitted to copy and distribute verbatim copies of this +license document, but changing it is not allowed. + +#### 0. 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Depthcharge is currently not documented, since it is in the new build @@ -9,15 +10,7 @@ included in the BUILD\_HOWTO file in libreboot.git or \_src. This section relates to building libreboot from source, and working with the git repository. -- [Install build dependencies](#build_dependencies) -- [Get the full source code from metadata (git clone)](#build_meta) -- [How to build "bucts" (for LenovoBIOS - X60/X60S/X60T/T60)](#build_bucts) - -- [How to build "flashrom"](#build_flashrom) -- [How to build the ROM images](#build) - -Install build dependencies {#build_dependencies} +Install build dependencies ========================== Before doing anything, you need the dependencies first. This is true if @@ -28,17 +21,22 @@ statically compiled executables for the utilities are included.** For Debian Stretch (may also work on Debian Jessie), you can run the following command: + $ sudo ./oldbuild dependencies debian + (this will also work in Devuan) For Parabola, you can run the following command: + $ sudo ./oldbuild dependencies parabola\ + or: + # ./oldbuild dependencies parabola For other GNU+Linux distributions, you can adapt the existing scripts. -Get the full source code from metadata (git clone) {#build_meta} +Get the full source code from metadata (git clone) ================================================== If you downloaded libreboot from git, then there are some steps to @@ -57,6 +55,7 @@ requirement is: $ git config --global user.name "Your Name" $ git config --global user.email your@emailaddress.com + This is what will also appear in git logs if you ever commit your own changes to a given repository. For more information, see <http://git-scm.com/doc>. @@ -79,7 +78,7 @@ them. Read the script in a text editor to learn more. To build the ROM images, see [\#build](#build). -How to build "bucts" (for LenovoBIOS X60/X60S/X60T/T60) {#build_bucts} +How to build "bucts" (for LenovoBIOS X60/X60S/X60T/T60) ========================================================= **This is for Lenovo BIOS users on the ThinkPad X60/X60S, X60 Tablet and @@ -136,7 +135,7 @@ To statically compile it, do this: The "builddeps" script in libreboot\_src also makes use of builddeps-bucts. -How to build "flashrom" {#build_flashrom} +How to build "flashrom" ========================= Flashrom is the utility for flashing/dumping ROM images. This is what @@ -177,7 +176,7 @@ executables: The "builddeps" script in libreboot\_src also makes use of builddeps-flashrom. -How to build the ROM images {#build} +How to build the ROM images =========================== You don't need to do much, as there are scripts already written for you @@ -211,12 +210,14 @@ modulename*. To see the possible values for *modulename*, use: After that, build the ROM images (for all boards): $ ./oldbuild roms withgrub + Alternatively, you can build for a specific board or set of boards. For example: $ ./oldbuild roms withgrub x60 $ ./oldbuild roms withgrub x200\_8mb $ ./oldbuild roms withgrub x60 x200\_8mb + The list of board options can be found by looking at the directory names in **resources/libreboot/config/grub/**. @@ -314,6 +315,7 @@ The command that you used for generating the release archives will also run the following command: $ ./oldbuild release tobuild + The archive **tobuild.tar.xz** will have been created under **release/oldbuildsystem/**, containing bucts, flashrom and all other required resources for building them. @@ -326,4 +328,9 @@ The ROM images will be stored in separate archives for each system, under **release/oldbuildsystem/rom/**. Copyright © 2014, 2015, 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/gnulinux/configuring_parabola.md b/docs/gnulinux/configuring_parabola.md index f760c64b..2aef3624 100644 --- a/docs/gnulinux/configuring_parabola.md +++ b/docs/gnulinux/configuring_parabola.md @@ -1,5 +1,6 @@ --- title: Configuring Parabola (post-install) +x-toc-enable: true ... Post-installation configuration steps for Parabola GNU+Linux-libre. @@ -7,38 +8,6 @@ Parabola is extremely flexible; this is just an example. This example uses LXDE because it's lightweight, but we recommend the *MATE* desktop (which is actually about as lightweight as LXDE). -Table of Contents -================= - -- [Configuring pacman](#pacman_configure) - - [Updating Parabola](#pacman_update) - - [Maintaining Parabola during system updates](#pacman_maintain) - - [Clearing package cache after updating](#pacman_cacheclean) - - [Pacman command equivalents (compared to other package - managers)](#pacman_commandequiv) - - [your-freedom](#yourfreedom) - -- [Add a user account](#useradd) -- [System D](#systemd) -- [Interesting repositories](#interesting_repos) -- [Setup a network connection in Parabola](#network) - - [Setting hostname](#network_hostname) - - [Network status](#network_status) - - [Network interface names](#network_devicenames) - - [Network setup](#network_setup) -- [System maintenance](#system_maintain) - important! -- [Configuring the desktop](#desktop) - - [Install Xorg](#desktop_xorg) - - [Xorg keyboard layout](#desktop_kblayout) - - [Install LXDE](#desktop_lxde) - - [LXDE - clock](#lxde_clock) - - [LXDE - font](#lxde_font) - - [LXDE - screenlock](#lxde_screenlock) - - [LXDE - automounting](#lxde_automount) - - [LXDE - disable suspend](#lxde_suspend) - - [LXDE - battery monitor](#lxde_battery) - - [LXDE - network manager](#lxde_network) - While not strictly related to the libreboot project, this guide is intended to be useful for those interested in installing Parabola on their libreboot system. @@ -86,9 +55,13 @@ careful about this when reading anything on the Arch wiki. Some of these steps require internet access. I'll go into networking later but for now, I just connected my system to a switch and did: + # systemctl start dhcpcd.service + You can stop it later by running: + # systemctl stop dhcpcd.service\ + For most people this should be enough, but if you don't have DHCP on your network then you should setup your network connection first:\ [Setup network connection in Parabola](#network) @@ -114,6 +87,7 @@ In the end, I didn't change my configuration for pacman. When you are updating, resync with the latest package names/versions: # pacman -Syy + (according to the wiki, -Syy is better than Sy because it refreshes the package list even if it appears to be up to date, which can be useful when switching to another mirror).\ @@ -190,6 +164,7 @@ The wiki also mentions this method for removing everything from the cache, including currently installed packages that are cached: # pacman -Scc + This is inadvisable, since it means re-downloading the package again if you wanted to quickly re-install it. This should only be used when disk space is at a premium. @@ -227,6 +202,7 @@ Read the entire document linked to above, and then continue. Add your user: # useradd -m -G wheel -s /bin/bash *yourusername* + Set a password: # passwd *yourusername* @@ -254,6 +230,7 @@ supplier) to use systemd. The manpage should also help: # man systemd + The section on 'unit types' is especially useful. According to the wiki, systemd 'journal' keeps logs of a size up to @@ -287,9 +264,11 @@ Finally, the wiki mentions 'temporary' files and the utility for managing them. # man systemd-tmpfiles + The command for 'clean' is: # systemd-tmpfiles --clean + According to the manpage, this *"cleans all files and directories with an age parameter"*. According to the Arch wiki, this reads information in /etc/tmpfiles.d/ and /usr/lib/tmpfiles.d/ to know what actions to @@ -301,6 +280,7 @@ However, /usr/lib/tmpfiles.d/ contained some files. The first one was etc.conf, containing information and a reference to this manpage: # man tmpfiles.d + Read that manpage, and then continue studying all the files. The systemd developers tell me that it isn't usually necessary to touch @@ -343,6 +323,7 @@ when installing Parabola. You can also do it with systemd (do so now, if you like): # hostnamectl set-hostname *yourhostname* + This writes the specified hostname to /etc/hostname. More information can be found in these manpages: @@ -430,6 +411,7 @@ non-free firmware inside, but it's transparent to you but the smart data comes from it. Therefore, don't rely on it too much): # pacman -S smartmontools + Read <https://wiki.archlinux.org/index.php/S.M.A.R.T.> to learn how to use it. @@ -449,6 +431,7 @@ Based on <https://wiki.archlinux.org/index.php/Xorg>. Firstly, install it! # pacman -S xorg-server + I also recommend installing this (contains lots of useful tools, including *xrandr*): @@ -458,9 +441,11 @@ Install the driver. For me this was *xf86-video-intel* on the ThinkPad X60. T60 and macbook11/21 should be the same. # pacman -S xf86-video-intel + For other systems you can try: # pacman -Ss xf86-video- | less + Combined with looking at your *lspci* output, you can determine which driver is needed. By default, Xorg will revert to xf86-video-vesa which is a generic driver and doesn't provide true hardware acceleration. @@ -566,6 +551,7 @@ I also like to install these: Enable LXDM (the default display manager, providing a graphical login): # systemctl enable lxdm.service + It will start when you boot up the system. To start it now, do: # systemctl start lxdm.service @@ -576,17 +562,20 @@ start lxde without lxdm. Read <https://wiki.archlinux.org/index.php/Xinitrc>. Open LXterminal: + $ cp /etc/skel/.xinitrc \~ + Open .xinitrc and add the following plus a line break at the bottom of the file.\ *\# Probably not needed. The same locale info that we set before\ \# Based on advice from the LXDE wiki export LC\_ALL=en\_GB.UTF-8\ export LANGUAGE=en\_GB.UTF-8\ export LANG=en\_GB.UTF-8\ -\ + \# Start lxde desktop\ exec startlxde\ * Now make sure that it is executable: + $ chmod +x .xinitrc ### LXDE - clock {#lxde_clock} @@ -643,6 +632,7 @@ Install Network Manager: You will also want the graphical applet: # pacman -S network-manager-applet + Arch wiki says that an autostart rule will be written at */etc/xdg/autostart/nm-applet.desktop* @@ -657,6 +647,7 @@ LXDE uses openbox, so I refer to:\ It tells me for the applet I need: # pacman -S xfce4-notifyd gnome-icon-theme + Also, for storing authentication details (wifi) I need: # pacman -S gnome-keyring @@ -665,6 +656,7 @@ I wanted to quickly enable networkmanager: # systemctl stop dhcpcd # systemctl start NetworkManager + Enable NetworkManager at boot time: # systemctl enable NetworkManager @@ -676,4 +668,9 @@ add a new applet). I also later changed the icons to use the gnome icon theme, in *lxappearance*. Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/gnulinux/encrypted_debian.md b/docs/gnulinux/encrypted_debian.md index 6041f1d0..2a1e2e79 100644 --- a/docs/gnulinux/encrypted_debian.md +++ b/docs/gnulinux/encrypted_debian.md @@ -22,17 +22,20 @@ tampering by someone with physical access to the system. This guide is written for Debian net installer. You can download the ISO from the homepage on [debian.org](https://www.debian.org/). Use this on -the GRUB terminal to boot it from USB (for 64-bit Intel or AMD):\ -**set root='usb0'\ -linux /install.amd/vmlinuz\ -initrd /install.amd/initrd.gz\ -boot\ -** If you are on a 32-bit system (e.g. X60):\ -**set root='usb0'\ -linux /install.386/vmlinuz\ -initrd /install.386/initrd.gz\ -boot** - +the GRUB terminal to boot it from USB (for 64-bit Intel or AMD): + + set root='usb0' + linux /install.amd/vmlinuz + initrd /install.amd/initrd.gz + boot + +If you are on a 32-bit system (e.g. X60): + + set root='usb0' + linux /install.386/vmlinuz + initrd /install.386/initrd.gz + boot + [This guide](grub_boot_installer.md) shows how to create a boot USB drive with the Debian ISO image. @@ -165,13 +168,11 @@ Booting your system =================== At this point, you will have finished the installation. At your GRUB -payload, press C to get to the command line. +payload, press C to get to the command line, and enter: -Do that:\ grub> cryptomount -a - grub> set root='lvm/matrix-rootvol'\ -grub> **linux /vmlinuz root=/dev/mapper/matrix-rootvol -cryptdevice=/dev/mapper/matrix-rootvol:root**\ + grub> set root='lvm/matrix-rootvol' + grub> linux /vmlinuz root=/dev/mapper/matrix-rootvolcryptdevice=/dev/mapper/matrix-rootvol:root grub> initrd /initrd.img grub> boot @@ -182,6 +183,7 @@ If you didn't encrypt your home directory, then you can safely ignore this section. Immediately after logging in, do that: + $ sudo ecryptfs-unwrap-passphrase This will be needed in the future if you ever need to recover your home @@ -199,12 +201,11 @@ Modify your grub.cfg (in the firmware) [using this tutorial](grub_cbfs.md); just change the default menu entry 'Load Operating System' to say this inside: -**cryptomount -a**\ -**set root='lvm/matrix-rootvol'**\ -**linux /vmlinuz root=/dev/mapper/matrix-rootvol -cryptdevice=/dev/mapper/matrix-rootvol:root**\ -**initrd /initrd.img** - + cryptomount -a + set root='lvm/matrix-rootvol' + linux /vmlinuz root=/dev/mapper/matrix-rootvolcryptdevice=/dev/mapper/matrix-rootvol:root + initrd /initrd.img + Without specifying a device, the *-a* parameter tries to unlock all detected LUKS volumes. You can also specify -u UUID or -a (device). @@ -301,4 +302,9 @@ problems. Removing that worked around the issue. Does not write ultra high speed+ CD-RW media Copyright © 2014, 2015, 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/gnulinux/encrypted_parabola.md b/docs/gnulinux/encrypted_parabola.md index b88da31c..deb0ba4e 100644 --- a/docs/gnulinux/encrypted_parabola.md +++ b/docs/gnulinux/encrypted_parabola.md @@ -65,12 +65,14 @@ article](https://wiki.archlinux.org/index.php/Solid_State_Drives). Edit whole article and keep all points in mind, adapting them for this guide. Securely wipe the drive: + # dd if=/dev/urandom of=/dev/sda; sync NOTE: If you have an SSD, only do this the first time. If it was already LUKS-encrypted before, use the info below to wipe the LUKS header. Also, check online for your SSD what the recommended erase block size is. For example if it was 2MiB: + # dd if=/dev/urandom of=/dev/sda bs=2M; sync If your drive was already LUKS encrypted (maybe you are re-installing @@ -82,6 +84,7 @@ guide is recommending putting zero there. I'm going to use urandom. Do this: # head -c 3145728 /dev/urandom > /dev/sda; sync + (Wiping the LUKS header is important, since it has hashed passphrases and so on. It's 'secure', but 'potentially' a risk). @@ -93,6 +96,7 @@ list the available keymaps and use yours: # localectl list-keymaps # loadkeys LAYOUT + For me, LAYOUT would have been dvorak-uk. Establish an internet connection @@ -142,13 +146,14 @@ I am then directed to Parabola forces you to RTFM. Do that. -It tells me to run: +To populate the list below, it tells me to run: + + # cryptsetup benchmark - # cryptsetup benchmark (for making sure the list below is -populated)\ Then: # cat /proc/crypto + This gives me crypto options that I can use. It also provides a representation of the best way to set up LUKS (in this case, security is a priority; speed, a distant second). To gain a better understanding, I @@ -162,10 +167,14 @@ on Reading through, it seems like Serpent (encryption) and Whirlpool (hash) is the best option. -I am initializing LUKS with the following:\ -\# **cryptsetup -v --cipher serpent-xts-plain64 --key-size 512 --hash +I am initializing LUKS with the following: + + # cryptsetup -v --cipher serpent-xts-plain64 --key-size 512 --hash + whirlpool --iter-time 500 --use-random --verify-passphrase luksFormat -/dev/sda1** Choose a **secure** passphrase here. Ideally lots of +/dev/sda1 + + Choose a **secure** passphrase here. Ideally lots of lowercase/uppercase numbers, letters, symbols etc all in a random pattern. The password length should be as long as you are able to handle without writing it down or storing it anywhere. @@ -178,14 +187,14 @@ Create LVM Now I refer to <https://wiki.archlinux.org/index.php/LVM>. -Open the LUKS partition: +Open the LUKS partition at /dev/mapper/lvm: # cryptsetup luksOpen /dev/sda1 lvm -(it will be available at /dev/mapper/lvm) Create LVM partition: # pvcreate /dev/mapper/lvm + Show that you just created it: # pvdisplay @@ -194,22 +203,24 @@ Now I create the volume group, inside of which the logical volumes will be created: # vgcreate matrix /dev/mapper/lvm + (volume group name is 'matrix' - choose your own name, if you like) Show that you created it: # vgdisplay -Now create the logical volumes: +Now create the logical volumes (2G swap parittion named swapvol): + + # lvcreate -L 2G matrix -n swapvol - # lvcreate -L 2G matrix -n swapvol (2G swap partition, named -swapvol)\ -Again, choose your own name if you like. Also, make sure to choose a -swap size of your own needs. It basically depends on how much RAM you -have installed. I refer to +Again, choose your own name if you like. Also, make sure to choose a swap size +of your own needs. It basically depends on how much RAM you have installed. I +refer to <http://www.linux.com/news/software/applications/8208-all-about-linux-swap-space>. +This creates a single large partition in the rest of the space, named root: + + # lvcreate -l +100%FREE matrix -n root - # lvcreate -l +100%FREE matrix -n root (single large partition in -the rest of the space, named root)\ You can also be flexible here, for example you can specify a /boot, a /, a /home, a /var, a /usr, etc. For example, if you will be running a web/mail server then you want /var in its own partition (so that if it @@ -227,6 +238,7 @@ Create / and swap partitions, and mount For the swapvol LV I use: # mkswap /dev/mapper/matrix-swapvol + Activate swap: # swapon /dev/matrix/swapvol @@ -263,49 +275,70 @@ server)) and then did: # pacman -Syy # pacman -Syu - # pacman -Sy pacman (and then I did the other 2 steps above, -again)\ + # pacman -Sy pacman + In my case I did the steps in the next paragraph, and followed the steps in this paragraph again. -<troubleshooting>\ -   The following is based on 'Verification of package signatures' in -the Parabola install guide.\ -   Check there first to see if steps differ by now.\ -   Now you have to update the default Parabola keyring. This is used for -signing and verifying packages:\ -   \# **pacman -Sy parabola-keyring**\ -   It says that if you get GPG errors, then it's probably an expired -key and, therefore, you should do:\ -   \# **pacman-key --populate parabola**\ -   \# **pacman-key --refresh-keys**\ -   \# **pacman -Sy parabola-keyring**\ -   To be honest, you should do the above anyway. Parabola has a lot of -maintainers, and a lot of keys. Really!\ -   If you get an error mentioning dirmngr, do:\ -   \# **dirmngr </dev/null**\ -   Also, it says that if the clock is set incorrectly then you have to -manually set the correct time\ -   (if keys are listed as expired because of it):\ -   \# **date MMDDhhmm\[\[CC\]YY\]\[.ss\]**\ -   I also had to install:\ -   \# **pacman -S archlinux-keyring**\ -   \# **pacman-key --populate archlinux**\ -   In my case I saw some conflicting files reported in pacman, stopping -me from using it.\ -   I deleted the files that it mentioned and then it worked. -Specifically, I had this error:\ -   *licenses: /usr/share/licenses/common/MPS exists in filesystem*\ -   I rm -Rf'd the file and then pacman worked. I'm told that the -following would have also made it work:\ -   \# **pacman -Sf licenses**\ -</troubleshooting>\ +Troubleshooting +--------------- + +The following is based on 'Verification of package signatures' in +the Parabola install guide. + +Check there first to see if steps differ by now. + +Now you have to update the default Parabola keyring. This is used for +signing and verifying packages: + +   # pacman -Sy parabola-keyring + +It says that if you get GPG errors, then it's probably an expired +key and, therefore, you should do: + +   # pacman-key --populate parabola +   # pacman-key --refresh-keys +   # pacman -Sy parabola-keyring + +To be honest, you should do the above anyway. Parabola has a lot of +maintainers, and a lot of keys. Really! + +If you get an error mentioning dirmngr, do: + +   # dirmngr < /dev/null + +Also, it says that if the clock is set incorrectly then you have to manually +set the correct time + +   # date MMDDhhmm\[\[CC\]YY\]\[.ss\] + +I also had to install: + +   # pacman -S archlinux-keyring +   # pacman-key --populate archlinux + +In my case I saw some conflicting files reported in pacman, stopping +me from using it. +I deleted the files that it mentioned and then it worked. +Specifically, I had this error: + +   licenses: /usr/share/licenses/common/MPS exists in filesystem + +I rm -Rf'd the file and then pacman worked. I'm told that the +following would have also made it work: + + # pacman -Sf licenses + +More packages +-------------- I also like to install other packages (base-devel, compilers and so on) and wpa\_supplicant/dialog/iw/wpa\_actiond are needed for wireless after -the install:\ -\# **pacstrap /mnt base base-devel wpa\_supplicant dialog iw -wpa\_actiond** +the install: + + # pacstrap /mnt base base-devel wpa_supplicant dialog iw + +wpa\_actiond Configure the system -------------------- @@ -315,9 +348,11 @@ Generate an fstab - UUIDs are used because they have certain advantages prefer labels instead, replace the -U option with -L): # genfstab -U -p /mnt >> /mnt/etc/fstab + Check the created file: # cat /mnt/etc/fstab + (If there are any errors, edit the file. Do **NOT** run the genfstab command again!) @@ -346,16 +381,18 @@ Parabola does not have wget. This is sinister. Install it: Locale: # vi /etc/locale.gen + Uncomment your needed localisations. For example en\_GB.UTF-8 (UTF-8 is highly recommended over other options). # locale-gen - # echo LANG=en\_GB.UTF-8 > /etc/locale.conf - # export LANG=en\_GB.UTF-8 + # echo LANG=en_GB.UTF-8 > /etc/locale.conf + # export LANG=en_GB.UTF-8 Console font and keymap: # vi /etc/vconsole.conf + In my case: KEYMAP=dvorak-uk @@ -364,6 +401,7 @@ In my case: Time zone: # ln -s /usr/share/zoneinfo/Europe/London /etc/localtime + (Replace Zone and Subzone to your liking. See /usr/share/zoneinfo) Hardware clock: @@ -374,6 +412,7 @@ Hostname: Write your hostname to /etc/hostname. For example, if your hostname is parabola: # echo parabola > /etc/hostname + Add the same hostname to /etc/hosts: # vi /etc/hosts @@ -392,6 +431,7 @@ Mkinitcpio: Configure /etc/mkinitcpio.conf as needed (see information about each hook.) Specifically, for this use case: # vi /etc/mkinitcpio.conf + Then modify the file like so: - MODULES="i915" @@ -418,9 +458,11 @@ with (this is different from Arch, specifying linux-libre instead of linux): # mkinitcpio -p linux-libre + Also do it for linux-libre-lts: # mkinitcpio -p linux-libre-lts + Also do it for linux-libre-grsec: # mkinitcpio -p linux-libre-grsec @@ -430,9 +472,11 @@ default for its password hashing. I referred to <https://wiki.archlinux.org/index.php/SHA_password_hashes>. # vi /etc/pam.d/passwd + Add rounds=65536 at the end of the uncommented 'password' line. # passwd root + Make sure to set a secure password! Also, it must never be the same as your LUKS password. @@ -457,7 +501,8 @@ file=/var/log/faillog*\ To unlock a user manually (if a password attempt is failed 3 times), do: - # pam\_tally --user *theusername* --reset What the above + # pam_tally --user *theusername* --reset What the above + configuration does is lock the user out for 10 minutes, if they make 3 failed login attempts. @@ -487,6 +532,7 @@ Lock the encrypted partition (close it): # cryptsetup luksClose lvm # shutdown -h now + Remove the installation media, then boot up again. Booting from GRUB @@ -538,13 +584,18 @@ current firmware - where *libreboot.rom* is an example: make sure to adapt: # flashrom -p internal -r libreboot.rom + If flashrom complains about multiple flash chips detected, add a *-c* option at the end, with the name of your chosen chip is quotes.\ You can check if everything is in there (*grub.cfg* and *grubtest.cfg* would be really nice): + $ ./cbfstool libreboot.rom print + Extract grubtest.cfg: + $ ./cbfstool libreboot.rom extract -n grubtest.cfg -f grubtest.cfg\ + And modify: $ vi grubtest.cfg @@ -578,20 +629,25 @@ Save your changes in grubtest.cfg, then delete the unmodified config from the ROM image: $ ./cbfstool libreboot.rom remove -n grubtest.cfg -and insert the modified grubtest.cfg:\ -\$ **./cbfstool libreboot.rom add -n grubtest.cfg -f grubtest.cfg -t -raw**\ + +and insert the modified grubtest.cfg: + + # ./cbfstool libreboot.rom add -n grubtest.cfg -f grubtest.cfg -t + +raw Now refer to [../install/#flashrom](../install/#flashrom). Cd (up) to the libreboot\_util directory and update the flash chip contents: # ./flash update libreboot.rom + Ocassionally, coreboot changes the name of a given board. If flashrom complains about a board mismatch, but you are sure that you chose the correct ROM image, then run this alternative command: # ./flash forceupdate libreboot.rom -You should see "Verifying flash\... VERIFIED." written at the end of + +You should see "Verifying flash... VERIFIED." written at the end of the flashrom output. With this new configuration, Parabola can boot automatically and you @@ -616,13 +672,17 @@ the main config still links (in the menu) to grubtest.cfg, so that you don't have to manually switch to it, in case you ever want to follow this guide again in the future (modifying the already modified config). Inside libreboot\_util/cbfstool/{armv7l i686 x86\_64}, we can do this -with the following command:\ -\$ **sed -e 's:(cbfsdisk)/grub.cfg:(cbfsdisk)/grubtest.cfg:g' -e +with the following command: + + # sed -e 's:(cbfsdisk)/grub.cfg:(cbfsdisk)/grubtest.cfg:g' -e + 's:Switch to grub.cfg:Switch to grubtest.cfg:g' < grubtest.cfg > -grub.cfg**\ +grub.cfg + Delete the grub.cfg that remained inside the ROM: $ ./cbfstool libreboot.rom remove -n grub.cfg + Add the modified version that you just made: $ ./cbfstool libreboot.rom add -n grub.cfg -f grub.cfg -t raw @@ -632,7 +692,8 @@ Now you have a modified ROM. Once more, refer to directory and update the flash chip contents: # ./flash update libreboot.rom -And wait for the "Verifying flash\... VERIFIED." Once you have done + +And wait for the "Verifying flash... VERIFIED." Once you have done that, shut down and then boot up with your new configuration. When done, delete GRUB (remember, we only needed it for the @@ -656,26 +717,32 @@ will be asked to enter your passphrase a second time. A workaround is to put a keyfile inside initramfs, with instructions for the kernel to use it when booting. This is safe, because /boot/ is encrypted (otherwise, putting a keyfile inside initramfs would be a bad idea).\ -Boot up and login as root or your user. Then generate the key file:\ -\# **dd bs=512 count=4 if=/dev/urandom of=/etc/mykeyfile -iflag=fullblock**\ +Boot up and login as root or your user. Then generate the key file: + + # dd bs=512 count=4 if=/dev/urandom of=/etc/mykeyfile + +iflag=fullblock + Insert it into the luks volume: # cryptsetup luksAddKey /dev/sdX /etc/mykeyfile + and enter your LUKS passphrase when prompted. Add the keyfile to the initramfs by adding it to FILES in /etc/mkinitcpio.conf. For example: # FILES="/etc/mykeyfile" + Create the initramfs image from scratch: # mkinitcpio -p linux-libre # mkinitcpio -p linux-libre-lts # mkinitcpio -p linux-libre-grsec + Add the following to your grub.cfg - you are now able to do that, see above! -, or add it in the kernel command line for GRUB: # cryptkey=rootfs:/etc/mykeyfile -\ + You can also place this inside the grub.cfg that exists in CBFS: [grub\_cbfs.md](grub_cbfs.md). @@ -774,4 +841,9 @@ problems. Removing that worked around the issue. Copyright © 2014, 2015, 2016 Leah Rowe <info@minifree.org>\ Copyright © 2015 Jeroen Quint <jezza@diplomail.ch>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/gnulinux/grub_boot_installer.md b/docs/gnulinux/grub_boot_installer.md index e89bc99e..6137b5b7 100644 --- a/docs/gnulinux/grub_boot_installer.md +++ b/docs/gnulinux/grub_boot_installer.md @@ -1,18 +1,12 @@ --- title: How to install GNU+Linux on a libreboot system +x-toc-enable: true ... This section relates to preparing, booting and installing a GNU+Linux distribution on your libreboot system, using nothing more than a USB flash drive (and *dd*). -- [Prepare the USB drive (in GNU+Linux)](#prepare) -- [Installing GNU+Linux with full disk encryption](#encryption) -- [Debian or Devuan net install?](#debian_netinstall) -- [Booting ISOLINUX images (automatic method)](#parse_isolinux) -- [Booting ISOLINUX images (manual method)](#manual_isolinux) -- [Troubleshooting](#troubleshooting) - **This section is only for the GRUB payload. For depthcharge (used on CrOS devices in libreboot), instructions have yet to be written in the libreboot documentation.** @@ -72,6 +66,7 @@ how to create the bootable GNU+Linux USB drive: Connect the USB drive. Check dmesg: $ dmesg | tail + Check to confirm which drive it is, for example, if you think its sd3: $ disklabel sd3 @@ -92,10 +87,8 @@ Continue reading, for information about how to do that. Installing GNU+Linux with full disk encryption ---------------------------------------------- -- [Installing Debian or Devuan GNU+Linux with full disk encryption - (including /boot)](encrypted_debian.md) -- [Installing Parabola GNU+Linux with full disk encryption (including - /boot)](encrypted_parabola.md) +- [Debian or Devuan GNU+Linux with full disk encryption](encrypted_debian.md) +- [Parabola GNU+Linux with full disk encryption](encrypted_parabola.md) Debian or Devuan net install? ----------------------------- @@ -103,16 +96,21 @@ Debian or Devuan net install? Download the Debian or Devuan net installer. You can download the ISO from the homepage on [debian.org](https://www.debian.org/), or [the Devuan homepage](https://www.devuan.org/) for Devuan. Use this on the -GRUB terminal to boot it from USB (for 64-bit Intel or AMD):\ -**set root='usb0'\ -linux /install.amd/vmlinuz\ -initrd /install.amd/initrd.gz\ -boot\ -** If you are on a 32-bit system (e.g. X60):\ -**set root='usb0'\ -linux /install.386/vmlinuz\ -initrd /install.386/initrd.gz\ -boot**\ +GRUB terminal to boot it from USB (for 64-bit Intel or AMD): + + + set root='usb0' + linux /install.amd/vmlinuz + initrd /install.amd/initrd.gz + boot + +If you are on a 32-bit system (e.g. X60): + + set root='usb0' + linux /install.386/vmlinuz + initrd /install.386/initrd.gz + boot + We recommend using the *MATE* desktop. Booting ISOLINUX images (automatic method) @@ -131,14 +129,21 @@ distribution. You must adapt them appropriately, for whatever GNU+Linux distribution it is that you are trying to install.* If the ISOLINUX parser or *Search for GRUB configuration* options won't -work, then press C in GRUB to access the command line.\ +work, then press C in GRUB to access the command line. + grub> ls -Get the device from above output, eg (usb0). Example:\ - grub> cat (usb0)/isolinux/isolinux.cfg\ + +Get the device from above output, eg (usb0). Example: + + grub> cat (usb0)/isolinux/isolinux.cfg + Either this will show the ISOLINUX menuentries for that ISO, or link to -other .cfg files, for example /isolinux/foo.cfg.\ -If it did that, then you do:\ +other .cfg files, for example /isolinux/foo.cfg. + +If it did that, then you do: + grub> cat (usb0)/isolinux/foo.cfg + And so on, until you find the correct menuentries for ISOLINUX. **The file */isolinux/foo.cfg* is a fictional example. Do not actually use this example, unless you actually have that file, if it is @@ -154,15 +159,17 @@ options in txt.cfg. This is important if you want 64-bit booting on your system. Devuan versions based on Debian 8.x may also have the same issue. -Now look at the ISOLINUX menuentry. It'll look like:\ -**kernel /path/to/kernel\ -append PARAMETERS initrd=/path/to/initrd MAYBE\_MORE\_PARAMETERS\ -** GRUB works the same way, but in it's own way. Example GRUB -commands:\ - grub> set root='usb0'\ +Now look at the ISOLINUX menuentry. It'll look like: + + kernel /path/to/kernel append PARAMETERS initrd=/path/to/initrd ... + +GRUB works similarly. Example GRUB commands: + + grub> set root='usb0' grub> linux /path/to/kernel PARAMETERS MAYBE\_MORE\_PARAMETERS grub> initrd /path/to/initrd grub> boot + Note: *usb0* may be incorrect. Check the output of the *ls* command in GRUB, to see a list of USB devices/partitions. Of course this will vary from distro to distro. If you did all of that correctly, then it should @@ -193,8 +200,9 @@ When using the ROM images that use coreboot's "text mode" instead of the coreboot framebuffer, booting the Debian or Devuan net installer results in graphical corruption because it is trying to switch to a framebuffer which doesn't exist. Use that kernel parameter on the -'linux' line when booting it:\ -**vga=normal fb=false** +'linux' line when booting it: + + vga=normal fb=false This forces debian-installer to start in text-mode, instead of trying to switch to a framebuffer. @@ -210,4 +218,9 @@ debian-installer (text mode) net install method. Copyright © 2014, 2015, 2016 Leah Rowe <info@minifree.org>\ Copyright © 2016 Scott Bonds <scott@ggr.com>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/gnulinux/grub_cbfs.md b/docs/gnulinux/grub_cbfs.md index 92d56095..01e4d3de 100644 --- a/docs/gnulinux/grub_cbfs.md +++ b/docs/gnulinux/grub_cbfs.md @@ -1,5 +1,6 @@ --- title: How to replace the default GRUB configuration file +x-toc-enable: true ... Libreboot on x86 uses the GRUB @@ -27,20 +28,6 @@ Here is an excellent writeup about CBFS (coreboot filesystem): **This guide is \*only\* for the GRUB payload. If you use the depthcharge payload, ignore this section entirely.** -Table of Contents -================= - -- [Introduction](#introduction) -- [1st option: don't re-flash](#option1_dont_reflash) -- [2nd option: re-flash](#option2_reflash) - - [Acquire the necessary utilities](#tools) - - [Acquiring the correct ROM image](#rom) - - [Extract grubtest from the ROM image](#extract_testconfig) - - [Re-insert the modified grubtest.cfg into the ROM - image](#reinsert_modified_testconfig) - - [Testing](#testing) - - [Final steps](#final_steps) - Introduction ------------ @@ -58,7 +45,7 @@ If you aren't up to that then don't worry; it is possible to use a custom GRUB menu without flashing a new image, by loading a GRUB configuration from a partition on the main storage instead. -1st option: don't re-flash {#option1_dont_reflash} +1st option: don't re-flash --------------------------- By default, GRUB in libreboot is configured to scan all partitions on @@ -94,22 +81,23 @@ of this page is irrelevant to you); **in libreboot\_grub.cfg on disk, if you are adapting it based on grub.cfg from CBFS then remove the check for libreboot\_grub.cfg otherwise it will loop.**. -2nd option: re-flash {#option2_reflash} +2nd option: re-flash -------------------- You can modify what is stored inside the flash chip quite easily. Read on to find out how. -Acquire the necessary utilities {#tools} +Acquire the necessary utilities ------------------------------- Use ***cbfstool*** and ***flashrom***. There are available in the *libreboot\_util* release archive, or they can be compiled (see [../git/\#build\_flashrom](../git/#build_flashrom)). Flashrom is also available from the repositories: + # pacman -S flashrom -Acquiring the correct ROM image {#rom} +Acquiring the correct ROM image ------------------------------- You can either work directly with one of the ROM images already included @@ -119,19 +107,22 @@ image file is named *libreboot.rom*, so please make sure to adapt. ROM images are included pre-compiled in libreboot. You can also dump your current firmware, using flashrom: + $ sudo flashrom -p internal -r libreboot.rom # flashrom -p internal -r libreboot.rom + If you are told to specify the chip, add the option **-c {your chip}** to the command, for example: # flashrom -c MX25L6405 -p internal -r libreboot.rom -Extract grubtest.cfg from the ROM image {#extract_testconfig} +Extract grubtest.cfg from the ROM image --------------------------------------- You can check the contents of the ROM image, inside CBFS: - $ cd \.../libreboot\_util/cbfstool** $ ./cbfstool libreboot.rom + $ cd .../libreboot\_util/cbfstool** $ ./cbfstool libreboot.rom + print** The files *grub.cfg* and *grubtest.cfg* should be present. grub.cfg is @@ -145,7 +136,7 @@ Extract grubtest.cfg from the ROM image: Modify the grubtest.cfg accordingly. -Re-insert the modified grubtest.cfg into the ROM image {#reinsert_modified_testconfig} +Re-insert the modified grubtest.cfg into the ROM image ------------------------------------------------------ Once your grubtest.cfg is modified and saved, delete the unmodified @@ -164,11 +155,14 @@ Testing [../install/\#flashrom](../install/#flashrom) for information on how to flash it. $ cd /libreboot\_util** \# **./flash update libreboot.rom\ + Ocassionally, coreboot changes the name of a given board. If flashrom complains about a board mismatch, but you are sure that you chose the correct ROM image, then run this alternative command: + # ./flash forceupdate libreboot.rom -You should see **"Verifying flash\... VERIFIED."** written at the end + +You should see **"Verifying flash... VERIFIED."** written at the end of the flashrom output. Once you have done that, shut down and then boot up with your new test configuration.** @@ -180,7 +174,7 @@ sceptical in any way, then re-do the steps above until you get it right! Do \*not\* proceed past this point unless you are 100% sure that your new configuration is safe (or desirable) to use.** -Final steps {#final_steps} +Final steps ----------- When you are satisfied booting from grubtest.cfg, you can create a copy @@ -190,10 +184,12 @@ difference: the menuentry 'Switch to grub.cfg' will be changed to grubtest.cfg. This is so that the main config still links (in the menu) to grubtest.cfg, so that you don't have to manually switch to it, in case you ever want to follow this guide again in the future (modifying -the already modified config). From /libreboot\_util/cbfstool, do:\ -\$ **sed -e 's:(cbfsdisk)/grub.cfg:(cbfsdisk)/grubtest.cfg:g' -e +the already modified config). From /libreboot\_util/cbfstool, do: + + # sed -e 's:(cbfsdisk)/grub.cfg:(cbfsdisk)/grubtest.cfg:g' -e + 's:Switch to grub.cfg:Switch to grubtest.cfg:g' < grubtest.cfg > -grub.cfg**\ +grub.cfg Delete the grub.cfg that remained inside the ROM: @@ -210,4 +206,9 @@ boot up with your new configuration.** Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ Copyright © 2015 Jeroen Quint <jezza@diplomail.ch>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/gnulinux/grub_hardening.md b/docs/gnulinux/grub_hardening.md index 1dd02844..c4843890 100644 --- a/docs/gnulinux/grub_hardening.md +++ b/docs/gnulinux/grub_hardening.md @@ -31,14 +31,10 @@ image: Helpful links: -- [GRUB manual - \#security](https://www.gnu.org/software/grub/manual/html_node/Security.html#Security) -- [GRUB info - pages](http://git.savannah.gnu.org/cgit/grub.git/tree/docs/grub.texi) -- [SATA connected storage considered dangerous until proven - otherwise.](../../faq.md#firmware-hddssd) -- [Coreboot GRUB security - howto](https://www.coreboot.org/GRUB2#Security) +- [GRUB manual](https://www.gnu.org/software/grub/manual/html_node/Security.html#Security) +- [GRUB info pages](http://git.savannah.gnu.org/cgit/grub.git/tree/docs/grub.texi) +- [SATA connected storage considered dangerous.](../../faq.md#firmware-hddssd) +- [Coreboot GRUB security howto](https://www.coreboot.org/GRUB2#Security) GRUB Password ============= @@ -138,7 +134,7 @@ First generate a GPG keypair to use for signing. Option RSA (sign only) is ok. **Warning:** GRUB does not read ASCII armored keys. When attempting to -trust \... a key filename it will print error: bad signature +trust ... a key filename it will print error: bad signature mkdir --mode 0700 keys gpg --homedir keys --gen-key @@ -158,6 +154,7 @@ Now that we have a key, we can sign some files with it. We have to sign: Suppose that we have a pair of **my.kernel** and **my.initramfs** and an on-disk **libreboot\_grub.cfg**. We sign them by issuing the following commands: + gpg --homedir keys --detach-sign my.initramfs gpg --homedir keys --detach-sign my.kernel gpg --homedir keys --detach-sign libreboot_grub.cfg @@ -176,7 +173,12 @@ What remains now is to include the modifications into the image (rom): cbfstool my.rom add -n grubtest.cfg -f my.grubtest.cfg -t raw cbfstool my.rom add -n grubtest.cfg.sig -f my.grubtest.cfg.sig -t raw -\... and flashing it. +... and flashing it. Copyright © 2017 Fedja Beader <fedja@protonmail.ch>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/gnulinux/index.md b/docs/gnulinux/index.md index 10a953eb..4903d1c6 100644 --- a/docs/gnulinux/index.md +++ b/docs/gnulinux/index.md @@ -23,4 +23,9 @@ instructions have yet to be written.** security](grub_hardening.md) Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/grub/index.md b/docs/grub/index.md index 1b5acacb..12c86359 100644 --- a/docs/grub/index.md +++ b/docs/grub/index.md @@ -1,28 +1,23 @@ --- title: GRUB payload +x-toc-enable: true ... This section relates to the GRUB payload used in libreboot. -- [Changing the background image in GRUB](#grub_background) -- [Setting font in GRUB](#grub_font) -- [GRUB keyboard layouts](#grub_keyboard) - - [Custom keyboard layout in GRUB](#grub_custom_keyboard) - - [UK Dvorak keyboard layout in GRUB](#grub_ukdvorak_keyboard) - -Changing the background image in GRUB {#grub_background} +Changing the background image in GRUB ===================================== Use cbfstool from libreboot\_util, or libreboot\_src/coreboot/util/cbfstool/ if you want to build from source. -./cbfstool yourrom.rom remove background.png -n background.png\ -./cbfstool yourrom.rom add -f background.png -n background.png -t raw + $ ./cbfstool yourrom.rom remove background.png -n background.png + $ ./cbfstool yourrom.rom add -f background.png -n background.png -t raw When you've done this, re-flash your ROM and you should have a new background at boot time. -Setting font in GRUB (for reference) {#grub_font} +Setting font in GRUB (for reference) ==================================== You don't need to do this unless you would like to change the default @@ -43,27 +38,29 @@ This is a free font that is also contained in GNU+Linux distributions like Debian, Devuan or Parabola. $ cd libreboot\_src/grub + compile grub (the build scripts info on how to do this)\ come back out into libreboot\_src/resources/grub: $ cd ../libreboot\_src/resources/grub/font I took Dejavu Sans Mono from dejavu (included in this version of -libreboot) and did:\ -**\$ ../../../grub/grub-mkfont -o dejavusansmono.pf2 -dejavu-fonts-ttf-2.34/ttf/DejaVuSansMono.ttf** +libreboot) and did: + + $ ../../../grub/grub-mkfont -o dejavusansmono.pf2 dejavu-fonts-ttf-2.34/ttf/DejaVuSansMono.ttf I then added the instructions to 'gen.sh' script in grub-assemble to include resources/grub/dejavusansmono.pf2 in all of the ROM images, at the root of the GRUB memdisk.\ I then added that instructions to the grub.cfg files (to load the -font):\ -**loadfont (memdisk)/dejavusansmono.pf2** +font): + + loadfont (memdisk)/dejavusansmono.pf2 -GRUB keyboard layouts (for reference) {#grub_keyboard} +GRUB keyboard layouts (for reference) ===================================== -Custom keyboard layout in GRUB (for reference) {#grub_custom_keyboard} +Custom keyboard layout in GRUB (for reference) ---------------------------------------------- Keymaps are stored in resources/utilities/grub-assemble/keymap/. @@ -71,9 +68,10 @@ Keymaps are stored in resources/utilities/grub-assemble/keymap/. Example (French Azerty): $ ckbcomp fr > frazerty -\ -Go in grub directory:\ -**cat frazerty | ./grub/grub-mklayout -o frazerty.gkb** + +Go in grub directory: + + $ cat frazerty | ./grub/grub-mklayout -o frazerty.gkb You must make sure that the files are named keymap and keymap.gkb (where 'keymap' can be whatever you want). @@ -87,7 +85,7 @@ The build scripts will automatically see this, and automatically build ROM images with your custom layout (given the name) and include them under bin. Example: **libreboot\_frazerty.rom**. -UK Dvorak keyboard layout in GRUB (for reference) {#grub_ukdvorak_keyboard} +UK Dvorak keyboard layout in GRUB (for reference) ------------------------------------------------- ukdvorak had to be created manually, based on usdvorak. diff them (under @@ -97,4 +95,9 @@ file was created $ cat ukdvorak | ./grub/grub-mklayout -o ukdvorak.gkb Copyright © 2014 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/c201.md b/docs/hardware/c201.md index 4e568d4a..8dba1f85 100644 --- a/docs/hardware/c201.md +++ b/docs/hardware/c201.md @@ -1,5 +1,6 @@ --- title: ASUS Chromebook C201 +x-toc-enable: true ... This is a Chromebook, using the Rockchip RK3288 SoC. It uses an ARM CPU, @@ -16,18 +17,7 @@ confirmed to work.** Flashing instructions can be found at [../install/\#flashrom](../install/#flashrom) -- [Google's intent with CrOS devices](#googlesintent) -- [Considerations about ChromeOS and free operating systems](#os) -- [Caution: Video acceleration requires a non-free blob, software - rendering can be used instead.](#videoblobs) -- [Caution: WiFi requires a non-free blob, a USB dongle can be used - instead.](#wifiblobs) -- [EC firmware is free software!](#ec) -- [No microcode!](#microcode) -- [Depthcharge payload](#depthcharge) -- [Flash chip write protection: the screw](#thescrew) - -Google's intent with CrOS devices {#googlesintent} +Google's intent with CrOS devices ================================== CrOS (Chromium OS/Chrome OS) devices, such as Chromebooks, were not @@ -56,7 +46,7 @@ are supported in libreboot. Those laptops are supported, in spite of Apple and Lenovo, companies which are actually *hostile* to the free software movement. -Considerations about ChromeOS and free operating systems {#os} +Considerations about ChromeOS and free operating systems ======================================================== This laptop comes preinstalled (from the factory) with Google ChromeOS. @@ -73,7 +63,7 @@ install Debian. TODO: instructions for Devuan -Caution: Video acceleration requires a non-free blob, software rendering can be used instead. {#videoblobs} +Caution: Video acceleration requires a non-free blob, software rendering can be used instead. ============================================================================================= The Tamil driver source code for the onboard Mali T GPU is not released. @@ -92,7 +82,7 @@ The Tamil developer wrote this blog post, which sheds light on the story: [http://libv.livejournal.com/27461.html,http://libv.livejournal.com/27461.html](http://libv.livejournal.com/27461.html). -Caution: WiFi requires a non-free blob, a USB dongle can be used instead. {#wifiblobs} +Caution: WiFi requires a non-free blob, a USB dongle can be used instead. ========================================================================= These laptops have non-removeable (soldered on) WiFi chips, which @@ -117,7 +107,7 @@ These wifi dongles use the AR9271 (atheros) chipset, supported by the free *ath9k\_htc* driver in the Linux kernel. They work in *linux-libre* too. -EC firmware is free software! {#ec} +EC firmware is free software! ============================= It's free software. Google provides the source. Build scripts will be @@ -132,7 +122,7 @@ when using one of these laptops. The libreboot FAQ briefly describes what an *EC* is: [../../faq.md#firmware-ec](../../faq.md#firmware-ec) -No microcode! {#microcode} +No microcode! ============= Unlike x86 (e.g. Intel/AMD) CPUs, ARM CPUs do not use microcode, not @@ -146,14 +136,14 @@ present), which are proprietary software. On ARM CPUs, the instruction set is implemented in circuitry, without microcode. -Depthcharge payload {#depthcharge} +Depthcharge payload =================== These systems do not use the GRUB payload. Instead, they use a payload called depthcharge, which is common on CrOS devices. This is free software, maintained by Google. -Flash chip write protection: the screw {#thescrew} +Flash chip write protection: the screw ====================================== It's next to the flash chip. Unscrew it, and the flash chip is @@ -177,4 +167,9 @@ all current libreboot systems, but CrOS devices make it easy. The screw is such a stupidly simple idea, which all designs should implement. Copyright © 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/d510mo.md b/docs/hardware/d510mo.md index 11dece1e..b2e85b0a 100644 --- a/docs/hardware/d510mo.md +++ b/docs/hardware/d510mo.md @@ -14,4 +14,9 @@ Flashing instructions can be found at [../install/d510mo.md](../install/d510mo.md) Copyright © 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/d945gclf.md b/docs/hardware/d945gclf.md index a05c0f15..c3f4754a 100644 --- a/docs/hardware/d945gclf.md +++ b/docs/hardware/d945gclf.md @@ -75,36 +75,9 @@ fan connector back, and you are done. Copyright © 2016 Arthur Heymans <arthur@aheymans.xyz>\ Copyright © 2016 Vitaly Castaño Solana <vita\_cell@hotmail.com>\ -Permission is granted to copy, distribute and/or modify this document -under the terms of the Creative Commons Attribution-ShareAlike 4.0 -International license or any later version published by Creative -Commons; A copy of the license can be found at -[../cc-by-sa-4.0.txt](../cc-by-sa-4.0.txt) - -Updated versions of the license (when available) can be found at -<https://creativecommons.org/licenses/by-sa/4.0/legalcode> - -UNLESS OTHERWISE SEPARATELY UNDERTAKEN BY THE LICENSOR, TO THE EXTENT -POSSIBLE, THE LICENSOR OFFERS THE LICENSED MATERIAL AS-IS AND -AS-AVAILABLE, AND MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND -CONCERNING THE LICENSED MATERIAL, WHETHER EXPRESS, IMPLIED, STATUTORY, -OR OTHER. THIS INCLUDES, WITHOUT LIMITATION, WARRANTIES OF TITLE, -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NON-INFRINGEMENT, -ABSENCE OF LATENT OR OTHER DEFECTS, ACCURACY, OR THE PRESENCE OR ABSENCE -OF ERRORS, WHETHER OR NOT KNOWN OR DISCOVERABLE. WHERE DISCLAIMERS OF -WARRANTIES ARE NOT ALLOWED IN FULL OR IN PART, THIS DISCLAIMER MAY NOT -APPLY TO YOU. - -TO THE EXTENT POSSIBLE, IN NO EVENT WILL THE LICENSOR BE LIABLE TO YOU -ON ANY LEGAL THEORY (INCLUDING, WITHOUT LIMITATION, NEGLIGENCE) OR -OTHERWISE FOR ANY DIRECT, SPECIAL, INDIRECT, INCIDENTAL, CONSEQUENTIAL, -PUNITIVE, EXEMPLARY, OR OTHER LOSSES, COSTS, EXPENSES, OR DAMAGES -ARISING OUT OF THIS PUBLIC LICENSE OR USE OF THE LICENSED MATERIAL, EVEN -IF THE LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH LOSSES, -COSTS, EXPENSES, OR DAMAGES. WHERE A LIMITATION OF LIABILITY IS NOT -ALLOWED IN FULL OR IN PART, THIS LIMITATION MAY NOT APPLY TO YOU. - -The disclaimer of warranties and limitation of liability provided above -shall be interpreted in a manner that, to the extent possible, most -closely approximates an absolute disclaimer and waiver of all liability. +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/ga-g41m-es2l.md b/docs/hardware/ga-g41m-es2l.md index bfa73e91..fbcf2132 100644 --- a/docs/hardware/ga-g41m-es2l.md +++ b/docs/hardware/ga-g41m-es2l.md @@ -18,4 +18,9 @@ Flashing instructions can be found at [../install/\#flashrom](../install/#flashrom) Copyright © 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/gm45_remove_me.md b/docs/hardware/gm45_remove_me.md index e0aad8f5..5d9bc312 100644 --- a/docs/hardware/gm45_remove_me.md +++ b/docs/hardware/gm45_remove_me.md @@ -37,11 +37,13 @@ factory.bin dump. ich9gen executables can be found under ./ich9deblob/ statically compiled in libreboot\_util. If you are using src or git, build ich9gen from source with: + $ ./oldbuild module ich9deblob The executable will appear under resources/utilities/ich9deblob/ Run: + $ ./ich9gen Running ich9gen this way (without any arguments) generates a default @@ -70,6 +72,7 @@ generate a descriptor+gbe image with your own MAC address inside (with the Gbe checksum updated to match). Run: $ ./ich9gen --macaddress XX:XX:XX:XX:XX:XX + (replace the XX chars with the hexadecimal chars in the MAC address that you want) @@ -85,15 +88,23 @@ Two new files will be created: Assuming that your libreboot image is named **libreboot.rom**, copy the file to where **libreboot.rom** is located and then insert the descriptor+gbe file into the ROM image.\ -For 16MiB flash chips:\ -\$ **dd if=ich9fdgbe\_16m.bin of=libreboot.rom bs=1 count=12k -conv=notrunc**\ -For 8MiB flash chips:\ -\$ **dd if=ich9fdgbe\_8m.bin of=libreboot.rom bs=1 count=12k -conv=notrunc**\ -For 4MiB flash chips:\ -\$ **dd if=ich9fdgbe\_4m.bin of=libreboot.rom bs=1 count=12k -conv=notrunc**\ +For 16MiB flash chips: + + # dd if=ich9fdgbe_16m.bin of=libreboot.rom bs=1 count=12k + +conv=notrunc + +For 8MiB flash chips: + + # dd if=ich9fdgbe_8m.bin of=libreboot.rom bs=1 count=12k + +conv=notrunc + +For 4MiB flash chips: + + # dd if=ich9fdgbe_4m.bin of=libreboot.rom bs=1 count=12k + +conv=notrunc Your libreboot.rom image is now ready to be flashed on the system. Refer back to [../install/\#flashrom](../install/#flashrom) for how to flash @@ -164,6 +175,7 @@ you ran **./oldbuild module all** or **./oldbuild module ich9deblob** from the main directory (./), otherwise you can build it like so: $ ./oldbuild module ich9deblob + An executable file named **ich9deblob** will now appear under resources/utilities/ich9deblob/ @@ -192,9 +204,11 @@ Intel. Only the Intel NICs need a GbE region in the flash chip. Assuming that your libreboot image is named **libreboot.rom**, copy the **deblobbed\_descriptor.bin** file to where **libreboot.rom** is located -and then run:\ -\$ **dd if=deblobbed\_descriptor.bin of=libreboot.rom bs=1 count=12k -conv=notrunc** +and then run: + + # dd if=deblobbed_descriptor.bin of=libreboot.rom bs=1 count=12k + +conv=notrunc Alternatively, if you got a the **deblobbed\_4kdescriptor.bin** file (no GbE defined), do this: \$ **dd if=deblobbed\_4kdescriptor.bin @@ -235,9 +249,11 @@ Simply run (with factory.rom in the same directory): It will generate a 4KiB descriptor file (only the descriptor, no GbE). Insert that into a factory.rom image (NOTE: do this on a copy of it. -Keep the original factory.rom stored safely somewhere):\ -\$ **dd if=demefactory\_4kdescriptor.bin of=factory\_nome.rom bs=1 -count=4k conv=notrunc** +Keep the original factory.rom stored safely somewhere): + + # dd if=demefactory_4kdescriptor.bin of=factory_nome.rom bs=1 + +count=4k conv=notrunc TODO: test this.\ TODO: lenovobios (GM45 thinkpads) still write-protects parts of the @@ -423,7 +439,7 @@ actually be others on the X200. 0xBABA"* In honour of the song *Baba O'Reilly* by *The Who* apparently. We're -not making this stuff up\... +not making this stuff up... 0x3ABA, 0x34BA, 0x40BA and more have been observed in the main Gbe regions on the X200 factory.rom dumps. The checksums of the backup @@ -517,4 +533,9 @@ This is a 32K region from the factory image. It could be data It has only a 448 byte fragment different from 0x00 or 0xFF. Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/imac52.md b/docs/hardware/imac52.md index a868b128..99db1977 100644 --- a/docs/hardware/imac52.md +++ b/docs/hardware/imac52.md @@ -5,4 +5,9 @@ title: Apple iMac 5,2 Information to be written soon, but this board is merged in libreboot. Copyright © 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/index.md b/docs/hardware/index.md index d1f0ef54..fb9e0ed2 100644 --- a/docs/hardware/index.md +++ b/docs/hardware/index.md @@ -1,29 +1,18 @@ --- title: Hardware compatibility list +x-toc-enable: true ... This sections relates to known hardware compatibility in libreboot. For installatation instructions, refer to [../install/](../install/). -- [List of supported hardware](#supported_list) - - [Desktops (x86, AMD and Intel)](#supported_desktops_x86amdintel) - - [Servers/workstations](#supported_workstations_x86amd) - - [Laptops (ARM)](#supported_laptops_arm) - - [Laptops (Intel, x86)](#supported_laptops_x86intel) - -- NOTES: - - [Updating the EC firmware on i945 and GM45 - (recommended)](#ecupdate) - - [How to find what EC version you have (i945/GM45)](#ecversion) -- [Recommended wifi chipsets](#recommended_wifi) - -List of supported hardware {#supported_list} +List of supported hardware -------------------------- Libreboot supports the following systems in this release: -### Desktops (AMD, Intel, x86) {#supported_desktops_x86amdintel} +### Desktops (AMD, Intel, x86) - [Gigabyte GA-G41M-ES2L motherboard](ga-g41m-es2l.md) - [Intel D510MO motherboard](d510mo.md) @@ -31,27 +20,27 @@ Libreboot supports the following systems in this release: - [Intel D945GCLF](d945gclf.md) - [Apple iMac 5,2](imac52.md) -### Servers/workstations (AMD, x86) {#supported_workstations_x86amd} +### Servers/workstations (AMD, x86) - [ASUS KFSN4-DRE motherboard](kfsn4-dre.md) - [ASUS KGPE-D16 motherboard](kgpe-d16.md) -### Laptops (ARM) {#supported_laptops_arm} +### Laptops (ARM) - [ASUS Chromebook C201](c201.md) -### Laptops (Intel, x86) {#supported_laptops_x86intel} +### Laptops (Intel, x86) -- [Lenovo ThinkPad X60/X60s](#supported_x60_list) -- [Lenovo ThinkPad X60 Tablet](#supported_x60t_list) -- [Lenovo ThinkPad T60](#supported_t60_list) (there are exceptions. - see link) +- [Lenovo ThinkPad X60/X60s](#list-of-supported-x60s) +- [Lenovo ThinkPad X60 Tablet](#list-of-supported-x60-tablets) +- [Lenovo ThinkPad T60](#supported-t60-list) (some exceptions) - [Lenovo ThinkPad X200](x200.md) - [Lenovo ThinkPad R400](r400.md) - [Lenovo ThinkPad T400](t400.md) - [Lenovo ThinkPad T500](t500.md) -- [Apple MacBook1,1](#macbook11) -- [Apple MacBook2,1](#macbook21) +- [Lenovo ThinkPad W500](t500.md) +- [Apple MacBook1,1](#information-about-the-macbook11) +- [Apple MacBook2,1](#information-about-the-macbook21) 'Supported' means that the build scripts know how to build ROM images for these systems, and that the systems have been tested (confirmed @@ -61,7 +50,7 @@ working). There may be exceptions; in other words, this is a list of It is also possible to build ROM images (from source) for other systems (and virtual systems, e.g. QEMU). -EC update on i945 (X60, T60) and GM45 (X200, T400, T500, R400) {#ecupdate} +EC update on i945 (X60, T60) and GM45 (X200, T400, T500, R400, W500) ============================================================== It is recommended that you update to the latest EC firmware version. The @@ -80,19 +69,21 @@ only replaces the BIOS firmware, not EC. Updated EC firmware has several advantages e.g. bettery battery handling. -How to find what EC version you have (i945/GM45) {#ecversion} +How to find what EC version you have (i945/GM45) ================================================ -In GNU+Linux, you can try this:\ -**grep 'at EC' /proc/asound/cards** +In GNU+Linux, you can try this: + + $ grep 'at EC' /proc/asound/cards -Sample output:\ -**ThinkPad Console Audio Control at EC reg 0x30, fw 7WHT19WW-3.6** +Sample output: + + ThinkPad Console Audio Control at EC reg 0x30, fw 7WHT19WW-3.6 7WHT19WW is the version in different notation, use search engine to find out regular version - in this case it's a 1.06 for x200 tablet -Recommended wifi chipsets {#recommended_wifi} +Recommended wifi chipsets ------------------------- The following are known to work well: @@ -110,7 +101,7 @@ project if these work with linux-libre kernel (TODO: test): - \[0200\]: Qualcomm Atheros AR242x / AR542x Wireless Network Adapter (PCI-Express) \[168c:001c\] -List of supported ThinkPad X60s {#supported_x60_list} +List of supported ThinkPad X60s ------------------------------- Native gpu initialization ('native graphics') which replaces the @@ -138,7 +129,7 @@ is very easily replaced; just remove the card and install another one **after** libreboot is installed. See [\#recommended\_wifi](#recommended_wifi) for replacements. -List of supported ThinkPad X60 Tablets {#supported_x60t_list} +List of supported ThinkPad X60 Tablets -------------------------------------- Native gpu initialization ('native graphics') which replaces the @@ -222,7 +213,7 @@ could get finger input working. They used linuxwacom at git tag InputDevice "WTouch" "SendCoreEvents" EndSection -Supported T60 list {#supported_t60_list} +Supported T60 list ------------------ Native gpu initialization ('native graphics') which replaces the @@ -299,7 +290,7 @@ is very easily replaced; just remove the card and install another one **after** libreboot is installed. See [\#recommended\_wifi](#recommended_wifi) for replacements. -ThinkPad T60 (ATI GPU) and ThinkPad T60 (Intel GPU) differences. {#t60_ati_intel} +ThinkPad T60 (ATI GPU) and ThinkPad T60 (Intel GPU) differences. ---------------------------------------------------------------- If your T60 is a 14.1" or 15.1" model with an ATI GPU, it won't work @@ -320,7 +311,7 @@ cannot be used with libreboot under any circumstances. The following T60 motherboard (see area highlighted in white) shows an empty space where the ATI GPU would be (this particular motherboard has an Intel GPU):\ -\ +  The reason that the ATI GPU on T60 is unsupported is due to the VBIOS @@ -341,7 +332,7 @@ usable as a laptop because there would be no visual display at all. That being said, such a configuration is acceptable for use in a 'headless' server setup (with serial and/or ssh console as the display). -Information about the macbook1,1 {#macbook11} +Information about the macbook1,1 -------------------------------- There is an Apple laptop called the macbook1,1 from 2006 which uses the @@ -381,7 +372,7 @@ firmware is running. You will need to disassemble the system and flash externally. Reading from flash seems to work. For external flashing, refer to [../install/bbb\_setup.md](../install/bbb_setup.md). -Information about the macbook2,1 {#macbook21} +Information about the macbook2,1 -------------------------------- There is an Apple laptop called the macbook2,1 from late 2006 or early @@ -398,22 +389,13 @@ for whatever reason, since they include a lot of useful information. Backups created using wget: $ wget -m -p -E -k -K -np http://macbook.donderklumpen.de/ -**\$ wget -m -p -E -k -K -np -http://macbook.donderklumpen.de/coreboot/**\ -Use **-e robots=off** if using this trick for other sites and the site -restricts using robots.txt + $ wget -m -p -E -k -K -np http://macbook.donderklumpen.de/coreboot/ -**Links to wget backups (and the backups themselves) of Mono's pages -(see above) removed temporarily. Mono has given me permission to -distribute them, but I need to ask this person to tell me what license -these works fall under first. Otherwise, the above URLs should be fine. -NOTE TO SELF: REMOVE THIS WHEN DONE** +Use `-e robots=off` if using this trick for other sites and the site restricts +using robots.txt ### Installing GNU+Linux distributions (on Apple EFI firmware) -- [Parabola GNU+Linux installation on a macbook2,1 with Apple EFI - firmware](#) (this is a copy of Mono's page, see above) - How to boot an ISO: burn it to a CD (like you would normally) and hold down the Alt/Control key while booting. The bootloader will detect the GNU+Linux CD as 'Windows' (because Apple doesn't think GNU+Linux @@ -424,11 +406,6 @@ likes to think that Apple and Microsoft are all that exist.) Now to install libreboot, follow [../install/\#flashrom\_macbook21](../install/#flashrom_macbook21). -### Information about coreboot - -- [Coreboot on the macbook2,1](#) (this is a copy of Mono's page, see - above) - ### coreboot wiki page - <https://www.coreboot.org/Board:apple/macbook21> @@ -539,4 +516,9 @@ available at *resources/utilities/macbook21-three-finger-tap* in the libreboot git repository. Copyright © 2014, 2015, 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/kcma-d8.md b/docs/hardware/kcma-d8.md index 042bdf85..9d5067b1 100644 --- a/docs/hardware/kcma-d8.md +++ b/docs/hardware/kcma-d8.md @@ -96,4 +96,9 @@ Hardware specifications {#specifications} Check the ASUS website. Copyright © 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/kfsn4-dre.md b/docs/hardware/kfsn4-dre.md index f180f3f0..4efc4648 100644 --- a/docs/hardware/kfsn4-dre.md +++ b/docs/hardware/kfsn4-dre.md @@ -69,4 +69,9 @@ Other information [specifications](ftp://ftp.sgi.com/public/Technical%20Support/Pdf%20files/Asus/kfsn4-dre.pdf) Copyright © 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/kgpe-d16.md b/docs/hardware/kgpe-d16.md index a99be325..19d68416 100644 --- a/docs/hardware/kgpe-d16.md +++ b/docs/hardware/kgpe-d16.md @@ -210,4 +210,9 @@ The information here is adapted, from the ASUS website. processor Copyright © 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/r400.md b/docs/hardware/r400.md index c180e0f7..66854b5c 100644 --- a/docs/hardware/r400.md +++ b/docs/hardware/r400.md @@ -62,4 +62,9 @@ TODO: put hardware register logs here like on the [X200](x200.md) and [T400](t400.md) page. Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/t400.md b/docs/hardware/t400.md index 33104297..bec2d895 100644 --- a/docs/hardware/t400.md +++ b/docs/hardware/t400.md @@ -74,4 +74,9 @@ outputs from the T400: the one that libreboot git revision c164960 uses. Copyright © 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/t500.md b/docs/hardware/t500.md index 77c72dd2..862484dd 100644 --- a/docs/hardware/t500.md +++ b/docs/hardware/t500.md @@ -7,6 +7,8 @@ about [CPU compatibility](../install/t500_external.html#cpu_compatibility) for potential incompatibilities. +W500 is also compatible, and mostly the same design as T500. + There are two possible flash chip sizes for the T500: 4MiB (32Mbit) or 8MiB (64Mbit). This can be identified by the type of flash chip below the palmrest: 4MiB is SOIC-8, 8MiB is SOIC-16. @@ -70,6 +72,7 @@ The patches above are based on the output from ich9deblob on a factory.rom image dumped from the T500 with a SOIC-8 4MiB flash chip. The patch re-creates the X200 descriptor/gbe source, so the commands were something like: + $ diff -u t500gbe x200gbe $ diff -u t500descriptor x200descriptor @@ -93,4 +96,9 @@ outputs from the T500: - [../future/dumps/t500log/](../future/dumps/t500log/) Copyright © 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/hardware/x200.md b/docs/hardware/x200.md index 355ae1d5..8afbe504 100644 --- a/docs/hardware/x200.md +++ b/docs/hardware/x200.md @@ -33,6 +33,8 @@ will update both the BIOS and EC version. See: - [../install/#flashrom](../install/#flashrom) - <http://www.thinkwiki.org/wiki/BIOS_update_without_optical_disk> +- [X200, X200s, X200si BIOS Update](http://pcsupport.lenovo.com/au/en/products/laptops-and-netbooks/thinkpad-x-series-laptops/thinkpad-x200/downloads/ds015007) +- [X200t BIOS Update](http://pcsupport.lenovo.com/au/en/products/laptops-and-netbooks/thinkpad-x-series-tablet-laptops/thinkpad-x200-tablet/downloads/ds018814) NOTE: this can only be done when you are using Lenovo BIOS. How to update the EC firmware while running libreboot is unknown. Libreboot @@ -226,9 +228,11 @@ be useful for RAM compatibility info (note: coreboot raminit is different, so this page might be BS) pehjota started collecting some steppings for different CPUs on several -X200 laptops. You can get the CPUID by running:\ -\$ **dmesg | sed -n 's/\^.\* microcode: CPU0 -sig=0x\\(\[\^,\]\*\\),.\*\$/\\1/p'** +X200 laptops. You can get the CPUID by running: + + # dmesg | sed -n 's/\^.\* microcode: CPU0 + +sig=0x\\(\[\^,\]\*\\),.\*\$/\\1/p' What pehjota wrote: The laptops that have issues resuming from suspend, as well as a laptop that (as I mentioned earlier in \#libreboot) won't @@ -263,4 +267,9 @@ Unsorted notes {#unsorted} Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ Copyright © 2015 Patrick "P. J." McDermott <pj@pehjota.net>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/index.md b/docs/index.md index 7f8647b0..70d3e5f7 100644 --- a/docs/index.md +++ b/docs/index.md @@ -179,4 +179,9 @@ Generally speaking, it is advisable to use the latest version of libreboot. Copyright © 2014, 2015, 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [fdl-1.3.md](fdl-1.3.md) diff --git a/docs/install/bbb_setup.md b/docs/install/bbb_setup.md index af9026b3..b80203b4 100644 --- a/docs/install/bbb_setup.md +++ b/docs/install/bbb_setup.md @@ -28,7 +28,7 @@ flashing on the ThinkPad X200, but it should work for other targets. here is a photo of the setup for the teensy: <http://h5ai.swiftgeek.net/IMG_20160601_120855.jpg> -Onto the Beaglebone black\... +Onto the Beaglebone black... Hardware requirements ===================== @@ -150,12 +150,14 @@ Alternatives to SSH (in case SSH fails) You can also use a serial FTDI debug board with GNU Screen, to access the serial console. # screen /dev/ttyUSB0 115200 + Here are some example photos:\  \ You can also connect the USB cable from the BBB to another computer and a new network interface will appear, with its own IP address. This is directly accessible from SSH, or screen: + # screen /dev/ttyACM0 115200 You can also access the uboot console, using the serial method instead @@ -202,14 +204,16 @@ before continuing. Check that the firmware exists: # ls /lib/firmware/BB-SPI0-01-00A0.\* + Output: /lib/firmware/BB-SPI0-01-00A0.dtbo Then: - # echo BB-SPI0-01 > /sys/devices/bone\_capemgr.\*/slots - # cat /sys/devices/bone\_capemgr.\*/slots + # echo BB-SPI0-01 > /sys/devices/bone_capemgr.\*/slots + # cat /sys/devices/bone_capemgr.\*/slots + Output: 0: 54:PF--- @@ -223,6 +227,7 @@ Output: Verify that the spidev device now exists: # ls -al /dev/spid\* + Output: crw-rw---T 1 root spi 153, 0 Nov 19 21:07 /dev/spidev1.0 @@ -246,7 +251,8 @@ your BBB. Now test flashrom: - # ./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 + Output: Calibrating delay loop... OK. @@ -327,25 +333,12 @@ leads, **but** keep all other leads short (10cm or less) You should now have something that looks like this:\   -Notes about stability {#stability} -===================== - -<http://flashrom.org/ISP> is what we typically do in libreboot, though -not always. That page has some notes about using resistors to affect -stability. Currently, we use spispeed=512 (512kHz) but it is possible to -use higher speeds while maintaining stability. - -tty0\_ in \#libreboot was able to get better flashing speeds with the -following configuration: - -- "coax" with 0.1 mm core and aluminum foley (from my kitchen), add - 100 Ohm resistors (serial) -- put heatshrink above the foley, for: CS, CLK, D0, D1 -- Twisted pair used as core (in case more capacitors are needed) -- See this image: <http://i.imgur.com/qHGxKpj.jpg> -- He was able to flash at 50MHz (lower speeds are also fine). - Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ Copyright © 2015 Patrick "P. J." McDermott <pj@pehjota.net>\ Copyright © 2015 Albin Söderqvist\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/c201.md b/docs/install/c201.md index 648adde5..bcacd75b 100644 --- a/docs/install/c201.md +++ b/docs/install/c201.md @@ -1,5 +1,6 @@ --- title: ASUS Chromebook C201 installation guide +x-toc-enable: true ... These instructions are for installing Libreboot to the ASUS Chromebook @@ -25,26 +26,14 @@ source code is made available by Google: It is not distributed along with Libreboot yet. However, it is preinstalled on the device, with ChromeOS. -Installing Libreboot internally requires sufficient privileges on the -system installed on the device.\ -When the device has ChromeOS installed (as it does initially), it is -necessary to gain root privileges in ChromeOS, to be able to access a -root shell. - -- [Gaining root privileges on ChromeOS](#root_chromeos) -- [Preparing the device for the installation](#preparing_device) - - [Configuring verified boot - parameters](#configuring_verified_boot_parameters) - - [Removing the write protect - screw](#removing_write_protect_screw) -- [Installing Libreboot to the SPI flash]() - - [Installing Libreboot internally, from the - device](#installing_libreboot_internally) - - [Installing Libreboot externally, with a SPI flash - programmer](#installing_libreboot_externally) -- [Debian GNU+Linux is recommended for this device](#debian) +Installing Libreboot internally requires sufficient privileges on the system +installed on the device. When the device has ChromeOS installed (as it does +initially), it is necessary to gain root privileges in ChromeOS, to be able to +access a root shell. Gaining root privileges on ChromeOS +-------------------------------- + In order to gain root privileges on ChromeOS, developer mode has to be enabled from the recovery mode screen and debugging features have to be enabled in ChromeOS. @@ -75,7 +64,7 @@ Before installing Libreboot on the device, both its software and hardware has to be prepared to allow the installation procedure and to ensure that security features don't get in the way. -Configuring verified boot parameters {#configuring_verified_boot_parameters} +Configuring verified boot parameters ------------------------------------ It is recommended to have access to the [developer mode @@ -89,7 +78,7 @@ parameters](../depthcharge/#configuring_verified_boot_parameters): Those changes can be reverted later, when the device is known to be in a working state. -Removing the write protect screw {#removing_write_protect_screw} +Removing the write protect screw -------------------------------- Since part of the SPI flash is write-protected by a screw, it is @@ -111,7 +100,7 @@ screw](images/c201/wp-screw.jpg)](images/c201/wp-screw.jpg) The write protect screw can be put back in place later, when the device is known to be in a working state. -Installing Libreboot to the SPI flash {#installing_libreboot_spi_flash} +Installing Libreboot to the SPI flash ===================================== The SPI flash (that holds Libreboot) is divided into various partitions @@ -119,7 +108,7 @@ that are used to implement parts of the CrOS security system. Libreboot is installed in the *read-only* coreboot partition, that becomes writable after removing the write-protect screw. -Installing Libreboot internally, from the device {#installing_libreboot_internally} +Installing Libreboot internally, from the device ------------------------------------------------ Before installing Libreboot to the SPI flash internally, the device has @@ -131,16 +120,20 @@ transferred to the device. The following operations have to be executed with root privileges on the device (e.g. using the *root* account). In addition, the **cros-flash-replace** script has to be made executable: + # chmod a+x cros-flash-replace The SPI flash has to be read first: + # flashrom -p host -r flash.img\ + **Note: it might be a good idea to copy the produced flash.img file at this point and store it outside of the device for backup purposes.** Then, the **cros-flash-replace** script has to be executed as such: # ./cros-flash-replace flash.img coreboot ro-frid + If any error is shown, it is definitely a bad idea to go further than this point. @@ -149,11 +142,11 @@ The resulting flash image can then be flashed back: # flashrom -p host -w flash.img You should also see within the output the following:\ -**"Verifying flash\... VERIFIED."** +**"Verifying flash... VERIFIED."** Shut down. The device will now boot to Libreboot. -Installing Libreboot externally, with a SPI flash programmer {#installing_libreboot_externally} +Installing Libreboot externally, with a SPI flash programmer ------------------------------------------------------------ Before installing Libreboot to the SPI flash internally, the device has @@ -184,12 +177,14 @@ host (e.g. using the *root* account). In addition, the The SPI flash has to be read first (using the right spi programmer): # flashrom -p *programmer* -r flash.img + **Note: it might be a good idea to copy the produced flash.img file at this point and store it outside of the device for backup purposes.** Then, the **cros-flash-replace** script has to be executed as such: # ./cros-flash-replace flash.img coreboot ro-frid + If any error is shown, it is definitely a bad idea to go further than this point. @@ -199,7 +194,7 @@ programmer): # flashrom -p *programmer* -w flash.img You should also see within the output the following:\ -**"Verifying flash\... VERIFIED."** +**"Verifying flash... VERIFIED."** The device will now boot to Libreboot. @@ -210,4 +205,9 @@ Debian is recommended for this device (which is on that list. See <https://wiki.debian.org/InstallingDebianOn/Asus/C201>. Copyright © 2015 Paul Kocialkowski <contact@paulk.fr>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/d510mo.md b/docs/install/d510mo.md index a695ce48..4a03c29c 100644 --- a/docs/install/d510mo.md +++ b/docs/install/d510mo.md @@ -9,6 +9,7 @@ Flash chip size {#flashchips} =============== Use this to find out: + # flashrom -p internal -V Flashing instructions {#clip} @@ -21,4 +22,9 @@ This is an image of the flash chip, for reference:\  Copyright © 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/d945gclf.md b/docs/install/d945gclf.md index 351fc3e0..ddb52a64 100644 --- a/docs/install/d945gclf.md +++ b/docs/install/d945gclf.md @@ -18,4 +18,9 @@ Here is an image of the flash chip:\  Copyright © 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/ga-g41m-es2l.md b/docs/install/ga-g41m-es2l.md index a4f197ef..cf119bbc 100644 --- a/docs/install/ga-g41m-es2l.md +++ b/docs/install/ga-g41m-es2l.md @@ -9,6 +9,7 @@ Flash chip size {#flashchips} =============== Use this to find out: + # flashrom -p internal -V Flashing instructions {#clip} @@ -45,4 +46,9 @@ coreboot-libre. Therefore, you must set your own MAC address in your operating system. Copyright © 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/images/x200/disassembly/0006.1.jpg b/docs/install/images/x200/disassembly/0006.1.jpg Binary files differnew file mode 100644 index 00000000..1888012b --- /dev/null +++ b/docs/install/images/x200/disassembly/0006.1.jpg diff --git a/docs/install/index.md b/docs/install/index.md index 6b33a33c..5d9ba5c3 100644 --- a/docs/install/index.md +++ b/docs/install/index.md @@ -4,10 +4,10 @@ title: Installation instructions This section relates to installing Libreboot on supported targets. -**NOTE: if running flashrom -p internal for software based flashing, and -you get an error related to /dev/mem access, you should reboot with -iomem=relaxed kernel parameter before running flashrom, or use a kernel -that has CONFIG\_STRICT\_DEVMEM not enabled.** +**NOTE: if running flashrom -p internal for software based flashing, and you +get an error related to `/dev/mem` access, you should reboot with +`iomem=relaxed` kernel parameter before running flashrom, or use a kernel that +has `CONFIG_STRICT_DEVMEM` not enabled.** Which systems are Libreboot compatible with? -------------------------------------------- @@ -28,14 +28,11 @@ Flashing via software methods, on system: - [Apple MacBook2,1](#flashrom_macbook21) - [ASUS Chromebook C201](c201.md) -Setting up programmers, for external flashing via hardware method +Setting up programmers, for external SPI flashing ----------------------------------------------------------------- -- [How to program an SPI flash chip with the BeagleBone - Black](bbb_setup.md) - -- [How to program an SPI flash chip with the Raspberry - Pi](rpi_setup.md) +- [BeagleBone Black Setup](bbb_setup.md) +- [Raspberry Pi Setup](rpi_setup.md) Flashing via hardware methods, on system: ----------------------------------------- @@ -53,6 +50,7 @@ Flashing via hardware methods, on system: - [ThinkPad R400](r400_external.md) - [ThinkPad T400](t400_external.md) - [ThinkPad T500](t500_external.md) +- [ThinkPad W500](t500_external.md) Information about libreboot ROM images {#rom} ====================================== @@ -62,15 +60,14 @@ source code. These images are provided for user convenience, so that they don't have to build anything from source on their own. The ROM images in each archive use the following at the end of the file -name, if they are built with the GRUB payload: -**\_*keymap*\_*mode*.rom** +name, if they are built with the GRUB payload: `*_*keymap*_*mode*.rom` -Available *modes*: **vesafb** or **txtmode**. The *vesafb* ROM images -are recommended, in most cases; *txtmode* ROM images come with +Available `modes`: `vesafb` or `txtmode`. The `vesafb` ROM images +are recommended, in most cases; `txtmode` ROM images come with MemTest86+, which requires text-mode instead of the usual framebuffer used by coreboot native graphics initialization. -*keymap* can be one of several keymaps that keyboard supports (there are +`keymap` can be one of several keymaps that keyboard supports (there are quite a few), which affects the keyboard layout configuration that is used in GRUB. It doesn't matter which ROM image you choose here, as far as the keymap in GNU+Linux is concerned. @@ -86,12 +83,10 @@ Libreboot comes with ROM images built for QEMU, by default: Examples of how to use libreboot ROM images in QEMU: -- \$ **qemu-system-i386 -M q35 -m 512 -bios - qemu\_q35\_ich9\_keymap\_mode.rom** -- \$ **qemu-system-i386 -M pc -m 512 -bios - qemu\_i440fx\_piix4\_keymap\_mode.rom** + $ qemu-system-i386 -M q35 -m 512 -bios qemu_q35_ich9_keymap_mode.rom + $ qemu-system-i386 -M pc -m 512 -bios qemu_i440fx_piix4_keymap_mode.rom -You can optionally specify the **-serial stdio** argument, so that QEMU +You can optionally specify the `-serial stdio` argument, so that QEMU will emulate a serial terminal on the standard input/output (most likely your terminal emulator or TTY). @@ -107,8 +102,8 @@ any dedicated hardware. In other words, you can do everything entirely in software, directly from the OS that is running on your libreboot system. -**If you are using libreboot\_src or git, then make sure that you built -the sources first (see [../git/\#build](../git/#build)).** +**If you are using `libreboot_src` or git, then make sure that you built the +sources first (see [../git/\#build](../git/#build)).** Look at the [list of ROM images](#rom) to see which image is compatible with your device. @@ -126,7 +121,7 @@ Apple EFI should refer to [\#flashrom\_macbook21](#flashrom_macbook21) X200 users, refer to [x200\_external.md](x200_external.md), R400 users refer to [r400\_external.md](r400_external.md), T400 users -refer to [t400\_external.md](t400_external.md), T500 users refer to +refer to [t400\_external.md](t400_external.md), T500 and W500 users refer to [t500\_external.md](t500_external.md) ASUS KFSN4-DRE? @@ -207,7 +202,7 @@ you. Most people do not write-protect the flash chip, so you probably didn't either.* Similarly, it is possible to write-protect the flash chip in coreboot or -libreboot on GM45 laptops (X200/R400/T400/T500). If you did this, then +libreboot on GM45 laptops (X200/R400/T400/T500/W500). If you did this, then you will need to use the links above for flashing, treating your laptop as though it currently has the proprietary firmware (because write-protected SPI flash requires external re-flashing, as is also the @@ -217,10 +212,10 @@ If you did not write-protect the flash chip, or it came to you without any write-protection (***libreboot does not write-protect the flash chip by default, so this probably applies to you***), read on! -MAC address on GM45 (X200/R400/T400/T500) +MAC address on GM45 (X200/R400/T400/T500/W500) ----------------------------------------- -**Users of the X200/R400/T400/T500 take note:** The MAC address for the +**Users of the X200/R400/T400/T500/W500 take note:** The MAC address for the onboard ethernet chipset is located inside the flash chip. Libreboot ROM images for these laptops contain a generic MAC address by default, but this is not what you want. *Make sure to change the MAC address inside @@ -248,12 +243,13 @@ Flash chip size --------------- Use this to find out: + # flashrom -p internal -V All good? --------- -Excellent! Moving on\... +Excellent! Moving on... Download the *libreboot\_util.tar.xz* archive, and extract it. Inside, you will find a directory called *flashrom*. This contains statically @@ -267,6 +263,7 @@ appropriate executable. It is also possible for you to build these executables from the libreboot source code archives. How to update the flash chip contents: + $ sudo ./flash update [yourrom.rom](#rom) Ocassionally, coreboot changes the name of a given board. If flashrom @@ -275,7 +272,7 @@ correct ROM image, then run this alternative command: $ sudo ./flash forceupdate [yourrom.rom](#rom) -You should see **"Verifying flash\... VERIFIED."** written at the end +You should see **"Verifying flash... VERIFIED."** written at the end of the flashrom output. **Shut down** after you see this, and then boot up again after a few seconds. @@ -327,16 +324,18 @@ When you have booted up again, you must also do this: $ sudo ./flash i945lenovo\_secondflash [yourrom.rom](#rom) -If flashing fails at this stage, try the following:\ -\$ **sudo ./flashrom/i686/flashrom -p -internal:laptop=force\_I\_want\_a\_brick -w [yourrom.rom](#rom)** +If flashing fails at this stage, try the following: + + # sudo ./flashrom/i686/flashrom -p + +internal:laptop=force\_I\_want\_a\_brick -w [yourrom.rom](#rom) You should see within the output the following:\ **"Updated BUC.TS=0 - 128kb address range 0xFFFE0000-0xFFFFFFFF is untranslated"** You should also see within the output the following:\ -**"Verifying flash\... VERIFIED."** +**"Verifying flash... VERIFIED."** MacBook2,1: Initial installation guide (if running the proprietary firmware) {#flashrom_macbook21} ============================================================================ @@ -366,9 +365,14 @@ Use this flashing script, to install libreboot: $ sudo ./flash i945apple\_firstflash [yourrom.rom](#rom) You should also see within the output the following:\ -**"Verifying flash\... VERIFIED."** +**"Verifying flash... VERIFIED."** Shut down. Copyright © 2014, 2015, 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/kcma-d8.md b/docs/install/kcma-d8.md index 1dced30b..c4f83eea 100644 --- a/docs/install/kcma-d8.md +++ b/docs/install/kcma-d8.md @@ -1,5 +1,6 @@ --- title: KCMA-D8 external flashing instructions +x-toc-enable: true ... Initial flashing instructions for kcma-d8. @@ -17,11 +18,6 @@ For more general information about this board, refer to TODO: show photos here, and other info. -- [kcma-d8 boards (and full systems) with libreboot - preinstalled](#preinstall) - -- [External programmer](#programmer) - External programmer {#programmer} =================== @@ -34,4 +30,9 @@ the programmer. **DO NOT** remove the chip with your hands. Use a chip extractor tool. Copyright © 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/kgpe-d16.md b/docs/install/kgpe-d16.md index 8e041834..8e0ad8fd 100644 --- a/docs/install/kgpe-d16.md +++ b/docs/install/kgpe-d16.md @@ -1,5 +1,6 @@ --- title: KGPE-D16 external flashing instructions +x-toc-enable: true ... Initial flashing instructions for KGPE-D16. @@ -17,12 +18,7 @@ For more general information about this board, refer to TODO: show photos here, and other info. -- [KGPE-D16 boards (and full systems) with libreboot - preinstalled](#preinstall) - -- [External programmer](#programmer) - -External programmer {#programmer} +External programmer =================== Refer to [bbb\_setup.md](bbb_setup.md) for a guide on how to set up @@ -34,4 +30,9 @@ the programmer. **DO NOT** remove the chip with your hands. Use a chip extractor tool. Copyright © 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/r400_external.md b/docs/install/r400_external.md index c0c50d80..80e1a676 100644 --- a/docs/install/r400_external.md +++ b/docs/install/r400_external.md @@ -62,6 +62,7 @@ Flash chip size {#flashchips} =============== Use this to find out: + # flashrom -p internal -V MAC address {#macaddress} @@ -214,7 +215,9 @@ Log in as root on your BBB, using the instructions in [bbb\_setup.html\#bbb\_access](bbb_setup.html#bbb_access). Test that flashrom works: - # ./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512\ + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512\ + In this case, the output was: flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) @@ -227,19 +230,27 @@ In this case, the output was: Please specify which chip definition to use with the -c <chipname> option. How to backup factory.rom (change the -c option as neeed, for your flash -chip):\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r -factory.rom**\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r -factory1.rom**\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r -factory2.rom**\ +chip): + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory.rom + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory1.rom + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory2.rom + Note: the **-c** option is not required in libreboot's patched flashrom, because the redundant flash chip definitions in *flashchips.c* have been removed.\ Now compare the 3 images: # sha512sum factory\*.rom + If the hashes match, then just copy one of them (the factory.rom) to a safe place (on a drive connected to another system, not the BBB). This is useful for reverse engineering work, if there is a desirable @@ -253,13 +264,15 @@ flashing it. Although there is a default MAC address inside the ROM image, this is not what you want. **Make sure to always change the MAC address to one that is correct for your system.** -Now flash it:\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -w -path/to/libreboot/rom/image.rom -V** +Now flash it: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w + +path/to/libreboot/rom/image.rom -V  -You might see errors, but if it says **Verifying flash\... VERIFIED** at +You might see errors, but if it says **Verifying flash... VERIFIED** at the end, then it's flashed and should boot. If you see errors, try again (and again, and again); the message **Chip content is identical to the requested image** is also an indication of a successful @@ -351,4 +364,9 @@ You should see something like this: Now [install GNU+Linux](../gnulinux/). Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/rpi_setup.md b/docs/install/rpi_setup.md index 3230cb63..23b99aae 100644 --- a/docs/install/rpi_setup.md +++ b/docs/install/rpi_setup.md @@ -2,25 +2,22 @@ title: How to program an SPI flash chip with the Raspberry Pi ... -This document exists as a guide for reading from or writing to an SPI -flash chip with the Raspberry Pi, using the -[flashrom](http://flashrom.org/Flashrom) software. Most revisions of the -RPi should work. +This document exists as a guide for reading from or writing to an SPI flash +chip with the Raspberry Pi, using the [flashrom](http://flashrom.org/Flashrom) +software. Most revisions of the RPi should work. The Libreboot project recommends using -[blobless GNU/Linux](https://blog.rosenzweig.io/blobless-linux-on-the-pi.html) -on the Raspberry Pi, to avoid having to run non-free software. This -only became possible in February 2017 and the instructions below are -not yet updated with the necessary steps, so please do not follow the -steps below unless you are willing to run non-free software on your -Raspberry Pi. +[blobless GNU+Linux](https://blog.rosenzweig.io/blobless-linux-on-the-pi.html) +on the Raspberry Pi, to avoid having to run non-free software. This only became +possible in February 2017 and the instructions below are not yet updated with +the necessary steps, so please do not follow the steps below unless you are +willing to run non-free software on your Raspberry Pi. -This only covers SOIC-8 flash chips, for now. SOIC-16 guide coming later -(for now, it should be easy enough for you to figure this out for -SOIC-16). +This only covers SOIC-8 flash chips, for now. SOIC-16 guide coming later (for +now, it should be easy enough for you to figure this out for SOIC-16). -[](#raspberry-pi-thinkpad-x60t60-and-macbook-21){#user-content-raspberry-pi-thinkpad-x60t60-and-macbook-21 .anchor}Raspberry Pi (ThinkPad X60/T60 and Macbook 2,1) ------------------------------------------------------------------------------------------------------------------------------------------------------------------- +Raspberry Pi (ThinkPad X60/T60 and Macbook 2,1) +------------------------------------------------ The Raspberry Pi (a multipurpose \$25 GNU+Linux computer) can be used as a BIOS flashing tool, thanks to its GPIO pins and SPI support. @@ -28,7 +25,7 @@ a BIOS flashing tool, thanks to its GPIO pins and SPI support. > **Note:** The Raspberry Pi Model A is not supported, since it has no > GPIO pins. -### [](#disassembling-the-thinkpad){#user-content-disassembling-the-thinkpad .anchor}Disassembling the ThinkPad +### Disassembling the ThinkPad Follow the [X60 Hardware Maintenance Manual](http://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles_pdf/42x3550_04.pdf) @@ -45,7 +42,7 @@ Guide](t60_unbrick.md). - On the T60, the BIOS chip is just under the palmrest, but blocked by a magnesium frame (which you will have to remove). -### [](#pomona-clip-pinout){#user-content-pomona-clip-pinout .anchor}Pomona Clip Pinout +### Pomona Clip Pinout Diagram of the 26 GPIO Pins of the Raspberry Pi Model B (for the Model B+ with 40 pins, start counting from the right and leave 14 pins): @@ -78,7 +75,7 @@ detect a chip, or it will "detect" a `0x0` chip. Finally, make sure that the Pomona clip makes contact with the metal wires of the chip. It can be a challenge, but keep trying. -### [](#how-to-supply-power-to-the-flashchip){#user-content-how-to-supply-power-to-the-flashchip .anchor}How to supply power to the flashchip +### How to supply power to the flashchip There are two ways to supply power to the chip: plugging in an AC adapter (without turning the laptop on), and using the 8th 3.3v pin. @@ -90,8 +87,8 @@ Macronix chips require an AC Adapter to power up. Your results may vary. -[](#reading-the-flashchip){#user-content-reading-the-flashchip .anchor}Reading the Flashchip --------------------------------------------------------------------------------------------- +Reading the Flashchip +---------------------- First, visually inspect (with a magnifying glass) the type of flashchip on the motherboard. @@ -99,7 +96,7 @@ on the motherboard. Next, download and compile the latest Flashrom source code on the Raspberry Pi. - sudo apt-get install build-essential pciutils usbutils libpci-dev libusb-dev libftdi1 libftdi-dev zlib1g-dev subversion + sudo apt-get install build-essential pciutils usbutils libpci-dev libusb-dev libftdi1 libftdi-dev zlib1g-dev subversion libusb-1.0-0-dev svn co svn://flashrom.org/flashrom/trunk flashrom cd flashrom make @@ -127,8 +124,8 @@ If the md5sums match after three tries, `flashrom` has managed to read the flashchip precisely (but not always accurately). You may try and flash Libreboot now. -[](#flashing-libreboot){#user-content-flashing-libreboot .anchor}Flashing Libreboot ------------------------------------------------------------------------------------ +Flashing Libreboot +------------------- > **Note:** replace `/path/to/libreboot.rom` with the location of your > chosen ROM, such as `../bin/x60/libreboot_usqwerty.rom`): @@ -148,7 +145,7 @@ successfully. If not, just flash again. Erasing and writing flash chip... Erase/write done. Verifying flash... VERIFIED. -### [](#sources){#user-content-sources .anchor}Sources +### Sources - [Scruss - Simple ADC with the Raspberry Pi](http://scruss.com/blog/2013/02/02/simple-adc-with-the-raspberry-pi/) @@ -163,7 +160,7 @@ successfully. If not, just flash again. - [rPI with Flashrom and SOIC Clip Powerpoint](http://satxhackers.org/wp/hack-content/uploads/2013/04/rPI_flashrom.pdf) -### [](#raspberry-pi-pinout-diagrams){#user-content-raspberry-pi-pinout-diagrams .anchor}Raspberry Pi Pinout Diagrams +### Raspberry Pi Pinout Diagrams MCP 3008 Pin Pi GPIO Pin \# Pi Pin Name ----- ---------- ---------------- -------------------- @@ -179,10 +176,10 @@ successfully. If not, just flash again. - Source: [Perl & Raspberry Pi - Raspberry Pi GPIO Pinout](http://raspberrypi.znix.com/hipidocs/topic_gpiopins.htm) -[](#raspberry-pi-thinkpad-x200){#user-content-raspberry-pi-thinkpad-x200 .anchor}Raspberry Pi (ThinkPad X200) -------------------------------------------------------------------------------------------------------------- +Raspberry Pi (ThinkPad X200) +----------------------------- -### [](#requirements){#user-content-requirements .anchor}Requirements: +### Requirements: - An x86, x86\_64, or arm7l (for changing the libreboot.rom image mac address) @@ -229,7 +226,7 @@ Install Noobs to your fat32 formatted SD card x86# cp -R ~/work/noobs/* /path/to/mounted/SDcard/ -### [](#set-up-noobs-on-raspberry-pi){#user-content-set-up-noobs-on-raspberry-pi .anchor}Set up NOOBS on Raspberry Pi +### Set up NOOBS on Raspberry Pi Plug in the NOOBs SDCard to your Raspberry Pi, and enable the following under 'Advanced Options': @@ -246,7 +243,7 @@ On first boot On second boot - pi# sudo apt-get update && sudo apt-get install libftdi1 libftdi-dev libusb-dev libpci-dev subversion + pi# sudo apt-get update && sudo apt-get install libftdi1 libftdi-dev libusb-dev libpci-dev subversion libusb-1.0-0-dev Other dependencies that should already be installed with the noobs base install include: @@ -353,8 +350,8 @@ done. Shut down your pi, put your box back together, and install a libre OS for great good! -[](#raspberry-pi-c720-chromebook){#user-content-raspberry-pi-c720-chromebook .anchor}Raspberry Pi (C720 Chromebook) -------------------------------------------------------------------------------------------------------------------- +Raspberry Pi (C720 Chromebook) +------------------------------- The Raspberry Pi (a multipurpose \$25 GNU+Linux computer) can be used as a BIOS flashing tool, thanks to its GPIO pins and SPI support. @@ -408,12 +405,12 @@ Finally, put the Pomona SOIC clip on the chip:  -### [](#flashrom){#user-content-flashrom .anchor}Flashrom +### Flashrom [Once it's all set up, flashrom works out of the box.](http://www.flashrom.org/RaspberryPi) -### [](#sources-1){#user-content-sources-1 .anchor}Sources +### Sources - **Pomona SOIC Clip flashing** - [Arch Linux Wiki - Installing Arch Linux on @@ -434,4 +431,5 @@ Copyright © 2014, 2015 Lawrence Wu <sagnessagiel@gmail.com>\ Copyright © 2015 snuffeluffegus <>\ Copyright © 2015 Kevin Keijzer <>\ Copyright © 2016 Leah Rowe <info@minifree.org>\ + This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) diff --git a/docs/install/t400_external.md b/docs/install/t400_external.md index d81376e0..bbb7240f 100644 --- a/docs/install/t400_external.md +++ b/docs/install/t400_external.md @@ -28,8 +28,9 @@ A note about CPUs [ThinkWiki](http://www.thinkwiki.org/wiki/Category:T400) has a list of CPUs for this system. The Core 2 Duo P8400, P8600 and P8700 are believed -to work in libreboot. The T9600 was confirmed to work, so the -T9500/T9550 probably also work. +to work in libreboot. + +T9600, T9500 and T9550 are all compatible, as reported by users. Quad-core CPUs -------------- @@ -58,6 +59,7 @@ Flash chip size {#flashchips} =============== Use this to find out: + # flashrom -p internal -V MAC address {#macaddress} @@ -211,7 +213,9 @@ Log in as root on your BBB, using the instructions in [bbb\_setup.html\#bbb\_access](bbb_setup.html#bbb_access). Test that flashrom works: - # ./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 + In this case, the output was: flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) @@ -224,19 +228,27 @@ In this case, the output was: Please specify which chip definition to use with the -c <chipname> option. How to backup factory.rom (change the -c option as neeed, for your flash -chip):\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r -factory.rom**\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r -factory1.rom**\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r -factory2.rom**\ +chip): + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory.rom + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory1.rom + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory2.rom + Note: the **-c** option is not required in libreboot's patched flashrom, because the redundant flash chip definitions in *flashchips.c* have been removed.\ Now compare the 3 images: # sha512sum factory\*.rom + If the hashes match, then just copy one of them (the factory.rom) to a safe place (on a drive connected to another system, not the BBB). This is useful for reverse engineering work, if there is a desirable @@ -250,13 +262,15 @@ flashing it. Although there is a default MAC address inside the ROM image, this is not what you want. **Make sure to always change the MAC address to one that is correct for your system.** -Now flash it:\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -w -path/to/libreboot/rom/image.rom -V** +Now flash it: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w + +path/to/libreboot/rom/image.rom -V  -You might see errors, but if it says **Verifying flash\... VERIFIED** at +You might see errors, but if it says **Verifying flash... VERIFIED** at the end, then it's flashed and should boot. If you see errors, try again (and again, and again); the message **Chip content is identical to the requested image** is also an indication of a successful @@ -348,4 +362,9 @@ You should see something like this: Now [install GNU+Linux](../gnulinux/). Copyright © 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/t500_external.md b/docs/install/t500_external.md index 731ec8e0..749ef455 100644 --- a/docs/install/t500_external.md +++ b/docs/install/t500_external.md @@ -8,6 +8,8 @@ This guide is for those who want libreboot on their ThinkPad T500 while they still have the original Lenovo BIOS present. This guide can also be followed (adapted) if you brick your T500, to know how to recover. +W500 is also mostly compatible with this guide. + Libreboot T400 {#t400} ============== @@ -27,8 +29,10 @@ A note about CPUs [ThinkWiki](http://www.thinkwiki.org/wiki/Category:T500) has a list of CPUs for this system. The Core 2 Duo P8400, P8600 and P8700 are believed to work in libreboot. The T9600 was also tested on the T400 and -confirmed working, so the T9400/T9500/T9550 probably also work, but they -are untested. +confirmed working. + +T9550 was tested by a user, and is compatible as reported in the IRC channel. +T9500 and T9400 may also work, but YMMV. Quad-core CPUs -------------- @@ -57,6 +61,7 @@ Flash chip size {#flashchips} =============== Use this to find out: + # flashrom -p internal -V MAC address {#macaddress} @@ -225,7 +230,9 @@ Log in as root on your BBB, using the instructions in [bbb\_setup.html\#bbb\_access](bbb_setup.html#bbb_access). Test that flashrom works: - # ./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 + In this case, the output was: flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) @@ -238,19 +245,27 @@ In this case, the output was: Please specify which chip definition to use with the -c <chipname> option. How to backup factory.rom (change the -c option as neeed, for your flash -chip):\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r -factory.rom**\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r -factory1.rom**\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r -factory2.rom**\ +chip): + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory.rom + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory1.rom + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + +factory2.rom + Note: the **-c** option is not required in libreboot's patched flashrom, because the redundant flash chip definitions in *flashchips.c* have been removed.\ Now compare the 3 images: # sha512sum factory\*.rom + If the hashes match, then just copy one of them (the factory.rom) to a safe place (on a drive connected to another system, not the BBB). This is useful for reverse engineering work, if there is a desirable @@ -264,13 +279,15 @@ flashing it. Although there is a default MAC address inside the ROM image, this is not what you want. **Make sure to always change the MAC address to one that is correct for your system.** -Now flash it:\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -w -path/to/libreboot/rom/image.rom -V** +Now flash it: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w + +path/to/libreboot/rom/image.rom -V  -You might see errors, but if it says **Verifying flash\... VERIFIED** at +You might see errors, but if it says **Verifying flash... VERIFIED** at the end, then it's flashed and should boot. If you see errors, try again (and again, and again); the message **Chip content is identical to the requested image** is also an indication of a successful @@ -362,4 +379,9 @@ You should see something like this: Now [install GNU+Linux](../gnulinux/). Copyright © 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/t60_unbrick.md b/docs/install/t60_unbrick.md index 8df863e7..bc8d83e3 100644 --- a/docs/install/t60_unbrick.md +++ b/docs/install/t60_unbrick.md @@ -1,30 +1,23 @@ --- title: ThinkPad T60 Recovery guide +x-toc-enable: true ... This section documents how to recover from a bad flash that prevents your ThinkPad T60 from booting. -Table of Contents ------------------ - -- Types of brick: - - [Brick type 1: bucts not reset](#bucts_brick) - - [Brick type 2: bad rom (or user error), system won't - boot](#recovery) - Brick type 1: bucts not reset. {#bucts_brick} ============================== You still have Lenovo BIOS, or you had libreboot running and you flashed another ROM; and you had bucts 1 set and the ROM wasn't dd'd.\* or if Lenovo BIOS was present and libreboot wasn't flashed.\ -\ + In this case, unbricking is easy: reset BUC.TS to 0 by removing that yellow cmos coin (it's a battery) and putting it back after a minute or two:\ \ -\ + \*Those dd commands should be applied to all newly compiled T60 ROM images (the ROM images in libreboot binary archives already have this applied!):\ @@ -148,11 +141,13 @@ Flashrom binaries for ARM (tested on a BBB) are distributed in libreboot\_util. Alternatively, libreboot also distributes flashrom source code which can be built. -SSH'd into the BBB:\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -w -yourrom.rom** +SSH'd into the BBB: -It should be **Verifying flash\... VERIFIED** at the end. If flashrom + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w + +yourrom.rom + +It should be **Verifying flash... VERIFIED** at the end. If flashrom complains about multiple flash chip definitions detected, then choose one of them following the instructions in the output. @@ -204,4 +199,9 @@ replacing cpu paste/heatsink:\  Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/x200_external.md b/docs/install/x200_external.md index adcc473b..6414fe7c 100644 --- a/docs/install/x200_external.md +++ b/docs/install/x200_external.md @@ -1,42 +1,31 @@ --- -title: Flashing the X200 with a BeagleBone Black +title: Flashing the X200 with a BeagleBone Black +x-toc-enable: true ... -Initial flashing instructions for X200. - This guide is for those who want libreboot on their ThinkPad X200 while they still have the original Lenovo BIOS present. This guide can also be followed (adapted) if you brick your X200, to know how to recover. -- [X200 laptops with libreboot pre-installed](#preinstall) -- [Flash chips](#flashchips) -- [MAC address](#macaddress) -- [Initial BBB configuration and installation procedure](#clip) -- [Boot it!](#boot) -- [Wifi](#wifi) -- [wwan](#wwan) -- [Memory](#memory) -- [X200S and X200 Tablet users: GPIO33 trick will not work.](#gpio33) - -X200 laptops with libreboot pre-installed {#preinstall} +X200 laptops with libreboot pre-installed ========================================= If you don't want to install libreboot yourself, companies exist that sell these laptops with libreboot pre-installed, along with a free GNU+Linux distribution. -Flash chip size {#flashchips} +Flash chip size =============== Use this to find out: + # flashrom -p internal -V -The X200S and X200 Tablet will use a WSON-8 flash chip, on the bottom of -the motherboard (this requires removal of the motherboard). **Not all -X200S/X200T are supported; see -[../hardware/x200.html\#x200s](../hardware/x200.html#x200s).** +The X200S and X200 Tablet will use a WSON-8 flash chip, on the bottom of the +motherboard (this requires removal of the motherboard). Not all X200S/X200T are +supported; see [here](../hardware/x200.html#x200s). -MAC address {#macaddress} +MAC address =========== On the X200/X200S/X200T, the MAC address for the onboard gigabit @@ -50,7 +39,7 @@ image before flashing it. It will be written in one of these locations:   -Initial BBB configuration {#clip} +Initial BBB configuration ========================= Refer to [bbb\_setup.md](bbb_setup.md) for how to set up the BBB for @@ -73,8 +62,6 @@ header), for SOIC-16 (clip: Pomona 5252): This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack. Here is a photo of the SOIC-16 flash chip. Pins are labelled: - - The following shows how to connect the clip to the BBB (on the P9 header), for SOIC-8 (clip: Pomona 5250): @@ -91,18 +78,15 @@ header), for SOIC-8 (clip: Pomona 5250): Look at the pads in that photo, on the left and right. Those are for SOIC-16. Would it be possible to remove the SOIC-8 and solder a SOIC-16 chip on those pins? -**On the X200S and X200 Tablet the flash chip is underneath the board, -in a WSON package. The pinout is very much the same as a SOIC-8, except -you need to solder (there are no clips available).\ -The following image shows how this is done:**\ -\ -In this image, a pin header was soldered onto the WSON. Another solution -might be to de-solder the WSON-8 chip and put a SOIC-8 there instead. -Check the list of SOIC-8 flash chips at -[../hardware/gm45\_remove\_me.html\#flashchips](../hardware/gm45_remove_me.md#flashchips) -but do note that these are only 4MiB (32Mb) chips. The only X200 SPI -chips with 8MiB capacity are SOIC-16. For 8MiB capacity in this case, -the X201 SOIC-8 flash chip (Macronix 25L6445E) might work. +On the X200S and X200 Tablet the flash chip is underneath the board, in a WSON +package. The pinout is very much the same as a SOIC-8, but such package makes +it impossible to use testclip. In order to enable external flashing of device, +chip has to be changed to SOIC-8 one. Such procedure requires hot air station +and soldering station (with "knife" K-Tip to easily solder SOIC-8). + +Check the list of SOIC-8 flash chips at [List of supported flash +chips](https://www.flashrom.org/Supported_hardware#Supported_flash_chips)\ 25XX +series SPI NOR Flash in 8/16MiB sizes will work fine with libreboot. The procedure ------------- @@ -114,13 +98,14 @@ completely, since the flash chip is on the other side of the board). Remove these screws:\  -Push the keyboard forward, gently, then lift it off and disconnect it -from the board:\ +Gently push the keyboard towards the screen, then lift it off, and optionally +disconnect it from the board:\   -Pull the palm rest off, lifting from the left and right side at the back -of the palm rest:\ +Disconnect the cable of the fingerpring reader, and then pull up the palm rest, +lifting up the left and right side of it:\ +  Lift back the tape that covers a part of the flash chip, and then @@ -133,19 +118,10 @@ to your PSU:\   -Connect the 3.3V supply from your PSU to the flash chip (via the clip):\ +Connect the 3.3V DC supply from your PSU to the flash chip (via the clip):\   -Of course, make sure that your PSU is also plugged in and turn on:\ - - -This tutorial tells you to use an ATX PSU, for the 3.3V DC supply. The -PSU used when taking these photos is actually not an ATX PSU, but a PSU -that is designed specifically for providing 3.3V DC (an ATX PSU will -also work):\ - - Now, you should be ready to install libreboot. Flashrom binaries for ARM (tested on a BBB) are distributed in @@ -156,7 +132,9 @@ Log in as root on your BBB, using the instructions in [bbb\_setup.html\#bbb\_access](bbb_setup.html#bbb_access). Test that flashrom works: - # ./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 + In this case, the output was: flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) @@ -168,20 +146,20 @@ In this case, the output was: Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)", "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E" Please specify which chip definition to use with the -c <chipname> option. -How to backup factory.rom (change the -c option as neeed, for your flash -chip):\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r -factory.rom**\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r -factory1.rom**\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -r -factory2.rom**\ -Note: the **-c** option is not required in libreboot's patched +Here is how to backup factory.rom: + + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory.rom + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory1.rom + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory2.rom + +Note: the `-c` option is not required in libreboot's patched flashrom, because the redundant flash chip definitions in *flashchips.c* -have been removed.\ +have been removed. + Now compare the 3 images: - # sha512sum factory\*.rom + # sha512sum factory*.rom + If the hashes match, then just copy one of them (the factory.rom) to a safe place (on a drive connected to another system, not the BBB). This is useful for reverse engineering work, if there is a desirable @@ -192,19 +170,19 @@ Follow the instructions at [../hardware/gm45\_remove\_me.html\#ich9gen](../hardware/gm45_remove_me.html#ich9gen) to change the MAC address inside the libreboot ROM image, before flashing it. Although there is a default MAC address inside the ROM -image, this is not what you want. **Make sure to always change the MAC -address to one that is correct for your system.** +image, this is not what you want. Make sure to always change the MAC +address to one that is correct for your system. + +Now flash it: -Now flash it:\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -w -path/to/libreboot/rom/image.rom -V** + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w path/to/libreboot/rom/image.rom -V  -You might see errors, but if it says **Verifying flash\... VERIFIED** at +You might see errors, but if it says `Verifying flash... VERIFIED` at the end, then it's flashed and should boot. If you see errors, try -again (and again, and again); the message **Chip content is identical to -the requested image** is also an indication of a successful +again (and again, and again); the message `Chip content is identical to +the requested image` is also an indication of a successful installation. Example output from running the command (see above): @@ -237,7 +215,8 @@ whitelist of approved chips, and it will refuse to boot if you use an 'unauthorized' wifi card. The following photos show an Atheros AR5B95 being installed, to replace -the Intel chip that this X200 came with:\ +the Intel chip that this X200 came with: +   @@ -251,6 +230,17 @@ track your movements. Not to be confused with wifi (wifi is fine). +Intel Turbo Memory +================== + +Some X200 devices were sold with Intel Turbo Memory installed in the top-most +mini PCI-e slot. This has been [shown to be +ineffective](http://www.anandtech.com/show/2252) at disk caching or battery +saving in most use cases. While there are [Linux +drivers](https://github.com/yarrick/turbomem) available, it is blacklisted in +at least GNU+Trisquel, and possibly other free operating systems. It should +probably be removed. + Memory ====== @@ -263,10 +253,11 @@ work in some cases. Make sure that the RAM you buy is the 2Rx8 density. -In this photo, 8GiB of RAM (2x4GiB) is installed:\ +In this photo, 8GiB of RAM (2x4GiB) is installed: +  -Boot it! {#boot} +Boot it! -------- You should see something like this: @@ -275,7 +266,7 @@ You should see something like this: Now [install GNU+Linux](../gnulinux/). -X200S and X200 Tablet users: GPIO33 trick will not work. {#gpio33} +X200S and X200 Tablet users: GPIO33 trick will not work. -------------------------------------------------------- sgsit found out about a pin called GPIO33, which can be grounded to @@ -283,7 +274,8 @@ disable the flashing protections by the descriptor and stop the ME from starting (which itself interferes with flashing attempts). The theory was proven correct; however, it is still useless in practise. -Look just above the 7 in TP37 (that's GPIO33):\ +Look just above the 7 in TP37 (that's GPIO33): +  By default we would see this in lenovobios, when trying flashrom -p @@ -316,5 +308,10 @@ On a related note, libreboot has a utility that could help with investigating this: [../hardware/gm45\_remove\_me.html\#demefactory](../hardware/gm45_remove_me.md#demefactory) -Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) +Copyright © 2014, 2015 Leah Rowe <info@minifree.org> + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/x60_unbrick.md b/docs/install/x60_unbrick.md index af040705..9c558631 100644 --- a/docs/install/x60_unbrick.md +++ b/docs/install/x60_unbrick.md @@ -1,30 +1,23 @@ --- title: ThinkPad X60 Recovery guide +x-toc-enable: true ... This section documents how to recover from a bad flash that prevents your ThinkPad X60 from booting. -Table of Contents -================= - -- Types of brick: - - [Brick type 1: bucts not reset](#bucts_brick) - - [Brick type 2: bad rom (or user error), system won't - boot](#recovery) - Brick type 1: bucts not reset. {#bucts_brick} ============================== You still have Lenovo BIOS, or you had libreboot running and you flashed another ROM; and you had bucts 1 set and the ROM wasn't dd'd.\* or if Lenovo BIOS was present and libreboot wasn't flashed.\ -\ + In this case, unbricking is easy: reset BUC.TS to 0 by removing that yellow cmos coin (it's a battery) and putting it back after a minute or two:\ \ -\ + \*Those dd commands should be applied to all newly compiled X60 ROM images (the ROM images in libreboot binary archives already have this applied!):\ @@ -133,11 +126,13 @@ Flashrom binaries for ARM (tested on a BBB) are distributed in libreboot\_util. Alternatively, libreboot also distributes flashrom source code which can be built. -SSH'd into the BBB:\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -w -yourrom.rom** +SSH'd into the BBB: -It should be **Verifying flash\... VERIFIED** at the end. If flashrom + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w + +yourrom.rom + +It should be **Verifying flash... VERIFIED** at the end. If flashrom complains about multiple flash chip definitions detected, then choose one of them following the instructions in the output. @@ -216,4 +211,9 @@ Operating system:\  Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/install/x60tablet_unbrick.md b/docs/install/x60tablet_unbrick.md index 78adf270..3a04ad3f 100644 --- a/docs/install/x60tablet_unbrick.md +++ b/docs/install/x60tablet_unbrick.md @@ -1,30 +1,23 @@ --- title: ThinkPad X60 Tablet Recovery guide +x-toc-enable: true ... This section documents how to recover from a bad flash that prevents your ThinkPad X60 Tablet from booting. -Table of Contents ------------------ - -- Types of brick: - - [Brick type 1: bucts not reset](#bucts_brick) - - [Brick type 2: bad rom (or user error), system won't - boot](#recovery) - Brick type 1: bucts not reset. {#bucts_brick} ============================== You still have Lenovo BIOS, or you had libreboot running and you flashed another ROM; and you had bucts 1 set and the ROM wasn't dd'd.\* or if Lenovo BIOS was present and libreboot wasn't flashed.\ -\ + In this case, unbricking is easy: reset BUC.TS to 0 by removing that yellow cmos coin (it's a battery) and putting it back after a minute or two:\ \ -\ + \*Those dd commands should be applied to all newly compiled X60 ROM images (the ROM images in libreboot binary archives already have this applied!):\ @@ -112,15 +105,22 @@ Flashrom binaries for ARM (tested on a BBB) are distributed in libreboot\_util. Alternatively, libreboot also distributes flashrom source code which can be built. -SSH'd into the BBB:\ -\# **./flashrom -p linux\_spi:dev=/dev/spidev1.0,spispeed=512 -w -yourrom.rom** +SSH'd into the BBB: -It should be **Verifying flash\... VERIFIED** at the end. If flashrom + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w + +yourrom.rom + +It should be **Verifying flash... VERIFIED** at the end. If flashrom complains about multiple flash chip definitions detected, then choose one of them following the instructions in the output. Reverse the steps to re-assemble your system. Copyright © 2014, 2015 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/misc/bbb_ehci.md b/docs/misc/bbb_ehci.md index fbc9e9d4..6af3c2a4 100644 --- a/docs/misc/bbb_ehci.md +++ b/docs/misc/bbb_ehci.md @@ -352,4 +352,9 @@ Interface](http://cs.usfca.edu/~cruse/cs698s10/) 4. Find a simple way to send debug messages from targets userland Copyright © 2015 Alex David <opdecirkel@gmail.com>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/misc/index.md b/docs/misc/index.md index 32ca10bf..79b8d367 100644 --- a/docs/misc/index.md +++ b/docs/misc/index.md @@ -124,7 +124,7 @@ on intel gpu's is included in intel-gpu-tools. Install intel-gpu-tools: **sudo apt-get install intel-gpu-tools** You can set values: **sudo intel\_reg write 0x00061254 -<your\_value>** +your_value_in_C_hex_format** The value set has the following structure: bits \[31:16\] is PWM divider. PWM / PWM\_divider = frequency bits \[15:0\] is the duty cycle @@ -201,10 +201,12 @@ is included in libreboot, and can be used to enable or disable this behaviour. Disable or enable beeps when removing/adding the charger: + $ sudo ./nvramtool -w power\_management\_beeps=Enable $ sudo ./nvramtool -w power\_management\_beeps=Disable Disable or enable beeps when battery is low: + $ sudo ./nvramtool -w low\_battery\_beep=Enable $ sudo ./nvramtool -w low\_battery\_beep=Disable @@ -222,9 +224,11 @@ package i2c-tools. $ sudo modprobe i2c-dev $ sudo i2cdump -y 5 0x50 (you might have to change the value for + -y) $ sudo rmmod i2c-dev + You'll see the panel name in the output (from the EDID dump). If neither of these options work (or they are unavailable), physically @@ -264,4 +268,9 @@ Look at resources/scripts/helpers/misc/libreboot\_usb\_bugfix Put this script in /etc/init.d/ on debian-based systems. Copyright © 2014, 2015, 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](../cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/release.md b/docs/release.md index 7f5a1c61..56b2548f 100644 --- a/docs/release.md +++ b/docs/release.md @@ -425,8 +425,6 @@ Changes for this release, relative to r20150208 (earliest changes last, recent c - **New board:** ThinkPad R400 support added to libreboot. - bbb\_setup.html: tell user to use libreboot's own flashrom - - Release 20150124, 20150126 and 20150208 {#release20150124} ======================================= @@ -638,8 +636,6 @@ Changes for this release (latest changes first, earliest changes last) html errors - Documentation (macbook21 related): clean up - - Release 20141015 {#release20141015} ================ @@ -1482,6 +1478,10 @@ Development notes - initial release - source code deblobbed - Copyright © 2014, 2015, 2016 Leah Rowe <info@minifree.org>\ -This page is available under the [CC BY SA 4.0](cc-by-sa-4.0.txt) + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [fdl-1.3.md](fdl-1.3.md) diff --git a/models.txt b/models.txt deleted file mode 100644 index 4ebae766..00000000 --- a/models.txt +++ /dev/null @@ -1 +0,0 @@ -http://gagarine.paulk.fr/collins/~paulk/libreboot/cros/models/ diff --git a/projects/flashrom/patches/0004-Whitelist-ThinkPad-W500.patch b/projects/flashrom/patches/0004-Whitelist-ThinkPad-W500.patch new file mode 100644 index 00000000..bb1c2bc3 --- /dev/null +++ b/projects/flashrom/patches/0004-Whitelist-ThinkPad-W500.patch @@ -0,0 +1,24 @@ +From 8c970dcf19661bc3d128a10e3ca79c24b4479186 Mon Sep 17 00:00:00 2001 +From: Gauvain Roussel-Tarbouriech <govanify@protonmail.com> +Date: Sat, 29 Apr 2017 19:01:11 +0200 +Subject: [PATCH 1/1] Whitelist ThinkPad W500 + +--- + board_enable.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/board_enable.c b/board_enable.c +index fc99615..a418e4f 100644 +--- a/board_enable.c ++++ b/board_enable.c +@@ -2430,6 +2430,7 @@ const struct board_match board_matches[] = { + {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad R400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad R400", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T400", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T400", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad T500", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T500", 0, OK, p2_whitelist_laptop}, ++ {0x8086, 0x2917, 0x17AA, 0x20F5, 0x8086, 0x2930, 0x17AA, 0x20F9, "^ThinkPad W500", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad W500", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x1E22, 0x17AA, 0x21F6, 0x8086, 0x1E55, 0x17AA, 0x21F6, "^ThinkPad T530", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T530", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x27a0, 0x17aa, 0x2015, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60", 0, OK, p2_whitelist_laptop}, + {0x8086, 0x27a0, 0x17aa, 0x2017, 0x8086, 0x27b9, 0x17aa, 0x2009, "^ThinkPad T60", NULL, NULL, P2, "IBM/Lenovo", "ThinkPad T60(s)", 0, OK, p2_whitelist_laptop}, +-- +2.12.2 + diff --git a/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision b/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision index 4f7158f6..e785a260 100644 --- a/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision +++ b/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision @@ -1 +1 @@ -55a54f662e2e793306dc7003afbcb82b49db0a8c +7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b diff --git a/resources/libreboot/config/grub/ga-g41m-es2l/config b/resources/libreboot/config/grub/ga-g41m-es2l/config index ec4790da..a0c7fc0c 100644 --- a/resources/libreboot/config/grub/ga-g41m-es2l/config +++ b/resources/libreboot/config/grub/ga-g41m-es2l/config @@ -139,7 +139,6 @@ CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y # CONFIG_BOARD_GIGABYTE_MA785GMT is not set # CONFIG_BOARD_GIGABYTE_MA78GM is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set -CONFIG_DEVICETREE="devicetree.cb" # CONFIG_CONSOLE_POST is not set CONFIG_DRIVERS_UART_8250IO=y CONFIG_CPU_ADDR_BITS=36 diff --git a/resources/libreboot/config/grub/w500_16mb/architecture b/resources/libreboot/config/grub/w500_16mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/w500_16mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/w500_16mb/cbrevision b/resources/libreboot/config/grub/w500_16mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/w500_16mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/w500_16mb/config b/resources/libreboot/config/grub/w500_16mb/config new file mode 100644 index 00000000..1abc3d16 --- /dev/null +++ b/resources/libreboot/config/grub/w500_16mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W500" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0xFFD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +CONFIG_BOARD_LENOVO_T500=y +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/w500_16mb/vbootrevision b/resources/libreboot/config/grub/w500_16mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/w500_16mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/w500_4mb/architecture b/resources/libreboot/config/grub/w500_4mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/w500_4mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/w500_4mb/cbrevision b/resources/libreboot/config/grub/w500_4mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/w500_4mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/w500_4mb/config b/resources/libreboot/config/grub/w500_4mb/config new file mode 100644 index 00000000..e4ddb2a4 --- /dev/null +++ b/resources/libreboot/config/grub/w500_4mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W500" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x3FD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +CONFIG_BOARD_LENOVO_T500=y +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/w500_4mb/vbootrevision b/resources/libreboot/config/grub/w500_4mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/w500_4mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/w500_8mb/architecture b/resources/libreboot/config/grub/w500_8mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/w500_8mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/w500_8mb/cbrevision b/resources/libreboot/config/grub/w500_8mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/w500_8mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/w500_8mb/config b/resources/libreboot/config/grub/w500_8mb/config new file mode 100644 index 00000000..bd4c48fe --- /dev/null +++ b/resources/libreboot/config/grub/w500_8mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W500" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x7FD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +CONFIG_BOARD_LENOVO_T500=y +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/w500_8mb/vbootrevision b/resources/libreboot/config/grub/w500_8mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/w500_8mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch deleted file mode 100644 index 884b2829..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Fri, 2 Sep 2016 22:35:32 +0200 -Subject: [PATCH 1/2] i945/gma.c use latest linux code to calculate divisors. - -The code to compute n, m1, m2, p1 divisors is not correct in coreboot and -on some targets hits a working mode at lower refresh rate, which is why -display is working on some targets. -This patch also fixes reference frequency. - -This patch reuses linux code to correctly compute divisors. - -The result is that some previously not working displays (Lenovo T60 with -1024x786, 1400x1050, 2048x1536) - -TESTED on T60 with 1024x786. - -Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- - 1 file changed, 38 insertions(+), 44 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..3f0b5b4 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -26,6 +26,8 @@ - #include <string.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> -+#include <commonlib/helpers.h> -+ - - #include "i945.h" - #include "chip.h" -@@ -43,7 +45,7 @@ - #define PGETBL_CTL 0x2020 - #define PGETBL_ENABLED 0x00000001 - --#define BASE_FREQUENCY 120000 -+#define BASE_FREQUENCY 100000 - - #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - -@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - u8 edid_data[128]; - unsigned long temp; - int hpolarity, vpolarity; -- u32 candp1, candn; -- u32 best_delta = 0xffffffff; -+ u32 smallest_err = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; -+ u32 pixel_p2; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; -@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - -- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock -- : (2 * mode->pixel_clock); -- -- /* Find suitable divisors. */ -- for (candp1 = 1; candp1 <= 8; candp1++) { -- for (candn = 5; candn <= 10; candn++) { -- u32 cur_frequency; -- u32 m; /* 77 - 131. */ -- u32 denom; /* 35 - 560. */ -- u32 current_delta; -- -- denom = candn * candp1 * 7; -- /* Doesnt overflow for up to -- 5000000 kHz = 5 GHz. */ -- m = (target_frequency * denom -- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; -- -- if (m < 77 || m > 131) -- continue; -- -- cur_frequency = (BASE_FREQUENCY * m) / denom; -- if (target_frequency > cur_frequency) -- current_delta = target_frequency - cur_frequency; -- else -- current_delta = cur_frequency - target_frequency; -- -- if (best_delta > current_delta) { -- best_delta = current_delta; -- pixel_n = candn; -- pixel_p1 = candp1; -- pixel_m2 = ((m + 3) % 5) + 7; -- pixel_m1 = (m - pixel_m2) / 5; -+ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; -+ target_frequency = mode->pixel_clock; -+ -+ /* Find suitable divisors, m1, m2, p1, n. */ -+ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ -+ /* should be closest to target frequency as possible */ -+ u32 candn, candm1, candm2, candp1; -+ for (candm1 = 8; candm1 <= 18; candm1++) { -+ for (candm2 = 3; candm2 <= 7; candm2++) { -+ for (candn = 1; candn <= 6; candn++) { -+ for (candp1 = 1; candp1 <= 8; candp1++) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * pixel_p2; -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if ((m < 70) || (m > 120)) -+ continue; -+ if (this_err < smallest_err) { -+ smallest_err = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } - } - } - } - -- if (best_delta == 0xffffffff) { -+ if (smallest_err == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return -1; - } -@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n -- / (pixel_p1 * 7)); -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * pixel_p2)); - - #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(pmmio + FP0(1), -- ((pixel_n - 2) << 16) -- | ((pixel_m1 - 2) << 8) | pixel_m2); -+ (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS -@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (conf->gpu_lvds_use_spread_spectrum_clock - ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV - : 0) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | -@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + HTOTAL(1), - ((hactive + right_border + hblank - 1) << 16) --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0006-i945-gma.c-add-native-VGA-init.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0006-i945-gma.c-add-native-VGA-init.patch deleted file mode 100644 index 26eed5b4..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0006-i945-gma.c-add-native-VGA-init.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 7ed0951bcf59dfd8b1893232b674455ff8f03f83 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 5 Sep 2016 22:46:11 +0200 -Subject: [PATCH 2/2] i945/gma.c: add native VGA init - -This reuses the Intel Pineview native graphic initialization -to have output on the VGA connector of i945 devices. - -The behavior is the same as with the vendor VBIOS BLOB. -It uses the external VGA display if it is connected. - -Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 196 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 194 insertions(+), 2 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 3f0b5b4..ac19d5a 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase) - return 0; - } - --static int intel_gma_init(struct northbridge_intel_i945_config *conf, -+static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, - unsigned int pphysbase, unsigned int piobase, - void *pmmio, unsigned int pgfx) - { -@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - #endif - return 0; - } -+ -+static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, -+ unsigned int pphysbase, unsigned int piobase, -+ void *pmmio, unsigned int pgfx) -+{ -+ int i; -+ u32 hactive, vactive; -+ u16 reg16; -+ u32 uma_size; -+ -+ printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", -+ (u32)pmmio, piobase, pphysbase); -+ -+ gtt_setup(pmmio); -+ -+ /* Disable VGA. */ -+ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); -+ -+ /* Disable pipes. */ -+ write32(pmmio + PIPECONF(0), 0); -+ write32(pmmio + PIPECONF(1), 0); -+ -+ write32(pmmio + INSTPM, 0x800); -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(pmmio + VGA0, 0x200074); -+ write32(pmmio + VGA1, 0x200074); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); -+ write32(pmmio + DSPCLK_GATE_D, 0); -+ write32(pmmio + FW_BLC, 0x03060106); -+ write32(pmmio + FW_BLC2, 0x00000306); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + 0x7041c, 0x0); -+ -+ write32(pmmio + DPLL_MD(0), 0x3); -+ write32(pmmio + DPLL_MD(1), 0x3); -+ write32(pmmio + DSPCNTR(1), 0x1000000); -+ write32(pmmio + PIPESRC(1), 0x027f01df); -+ -+ vga_misc_write(0x67); -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ // Disable screen memory to prevent garbage from appearing. -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(pmmio + PF_WIN_POS(0), 0); -+ -+ write32(pmmio + PIPESRC(0), (639 << 16) | 399); -+ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(pmmio + PFIT_CONTROL, 0x0); -+ -+ mdelay(1); -+ -+ write32(pmmio + FDI_RX_CTL(0), 0x00002040); -+ mdelay(1); -+ write32(pmmio + FDI_RX_CTL(0), 0x80002050); -+ write32(pmmio + FDI_TX_CTL(0), 0x00044000); -+ mdelay(1); -+ write32(pmmio + FDI_TX_CTL(0), 0x80044000); -+ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(pmmio + VGACNTRL, 0x0); -+ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1); -+ write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); -+ write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); -+ write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); -+ -+ /* Set up GTT. */ -+ -+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); -+ uma_size = 0; -+ if (!(reg16 & 2)) { -+ uma_size = decode_igd_memory_size((reg16 >> 4) & 7); -+ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); -+ } -+ -+ for (i = 0; i < (uma_size - 256) / 4; i++) -+ { -+ outl((i << 2) | 1, piobase); -+ outl(pphysbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ /* Clear interrupts. */ -+ write32(pmmio + DEIIR, 0xffffffff); -+ write32(pmmio + SDEIIR, 0xffffffff); -+ write32(pmmio + IIR, 0xffffffff); -+ write32(pmmio + IMR, 0xffffffff); -+ write32(pmmio + EIR, 0xffffffff); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ return 0; -+ -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should have a correct header */ -+static int vga_connected(u8 *pmmio) { -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(pmmio + GMBUS0); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - #endif - - static void gma_func0_init(struct device *dev) -@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev) - ); - - int err; -- err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ if (vga_connected(mmiobase)) -+ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ iobase, mmiobase, graphics_base); -+ else -+ err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0007-i945-gma.c-generate-fake-VBT.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0007-i945-gma.c-generate-fake-VBT.patch deleted file mode 100644 index 6f0272fd..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0007-i945-gma.c-generate-fake-VBT.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 60cc2c4532f63a40486b7c4e891fb87fb6d4ab7f Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Wed, 7 Sep 2016 22:10:57 +0200 -Subject: [PATCH] i945/gma.c: generate fake VBT - -This generates a fake VBT for the Intel i945 graphic device. -i945 supports both the mobile chipset 945gm (calistoga) -and the desktop chipset 945gc (lakeport), -which is why a VBT with a different id string -needs to be created for each target. - -The VBT id string is obtained from the vbios blob in the following way: -"strings vbios.bin | grep VBT". - -Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..f0944b9 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -433,6 +433,15 @@ static void gma_func0_init(struct device *dev) - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); -+ /* Linux relies on VBT for panel info. */ -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT CALISTOGA "); -+ } -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT LAKEPORT-G "); -+ } - #endif - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch deleted file mode 100644 index 0b8e146a..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch +++ /dev/null @@ -1,53 +0,0 @@ -From bbd04909524d7b9fd2e2b4dbd804801bbde66e44 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Wed, 7 Sep 2016 21:16:21 +0200 -Subject: [PATCH] lenovo/t60: add hda_verb.c - -This creates a config for the Lenovo T60 sound card based -on values taken from vendor bios -(in /sys/class/sound/hwC0D0/init_pin_configs on linux 3.16). -The sound card configuration on the vendor bios is the same -as the one on the Lenovo x60. - -It improves the default behavior of the sound card: -- internal microphone is chosen by default -- when jack is inserted it is chosen instead of internal speaker - -Change-Id: I44e3eaac437fe4ad97ff2b0eb32d36b33222c09b -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/mainboard/lenovo/t60/hda_verb.c | 19 +++++++++++++++++-- - 1 file changed, 17 insertions(+), 2 deletions(-) - -diff --git a/src/mainboard/lenovo/t60/hda_verb.c b/src/mainboard/lenovo/t60/hda_verb.c -index 072a306..dee3e80 100644 ---- a/src/mainboard/lenovo/t60/hda_verb.c -+++ b/src/mainboard/lenovo/t60/hda_verb.c -@@ -1,7 +1,22 @@ - #include <device/azalia_device.h> - --const u32 cim_verb_data[0] = {}; -+const u32 cim_verb_data[] = { -+ 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ -+ 0x17aa2025, /* Subsystem ID */ -+ 0x0000000b, /* Number of 4 dword sets */ - --const u32 pc_beep_verbs[0] = {}; -+ AZALIA_SUBVENDOR(0x0, 0x17aa2025), - -+ AZALIA_PIN_CFG(0, 0x05, 0xc3014110), -+ AZALIA_PIN_CFG(0, 0x06, 0x4221401f), -+ AZALIA_PIN_CFG(0, 0x07, 0x591311f0), -+ AZALIA_PIN_CFG(0, 0x08, 0xc3a15020), -+ AZALIA_PIN_CFG(0, 0x09, 0x41813021), -+ AZALIA_PIN_CFG(0, 0x0a, 0x014470f0), -+ AZALIA_PIN_CFG(0, 0x16, 0x59f311f0), -+ AZALIA_PIN_CFG(0, 0x17, 0x59931122), -+ AZALIA_PIN_CFG(0, 0x18, 0x41a19023), -+ AZALIA_PIN_CFG(0, 0x19, 0x9933e12e) -+}; -+const u32 pc_beep_verbs[0] = {}; - AZALIA_ARRAY_SIZES; --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch deleted file mode 100644 index 86bd6cb0..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Fri, 2 Sep 2016 22:35:32 +0200 -Subject: [PATCH] i945/gma.c use latest linux code to calculate divisors. - -The code to compute n, m1, m2, p1 divisors is not correct in coreboot and -on some targets hits a working mode at lower refresh rate, which is why -display is working on some targets. -This patch also fixes reference frequency. - -This patch reuses linux code to correctly compute divisors. - -The result is that some previously not working displays (Lenovo T60 with -1024x786, 1400x1050, 2048x1536) - -TESTED on T60 with 1024x786. - -Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- - 1 file changed, 38 insertions(+), 44 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..3f0b5b4 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -26,6 +26,8 @@ - #include <string.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> -+#include <commonlib/helpers.h> -+ - - #include "i945.h" - #include "chip.h" -@@ -43,7 +45,7 @@ - #define PGETBL_CTL 0x2020 - #define PGETBL_ENABLED 0x00000001 - --#define BASE_FREQUENCY 120000 -+#define BASE_FREQUENCY 100000 - - #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - -@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - u8 edid_data[128]; - unsigned long temp; - int hpolarity, vpolarity; -- u32 candp1, candn; -- u32 best_delta = 0xffffffff; -+ u32 smallest_err = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; -+ u32 pixel_p2; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; -@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - -- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock -- : (2 * mode->pixel_clock); -- -- /* Find suitable divisors. */ -- for (candp1 = 1; candp1 <= 8; candp1++) { -- for (candn = 5; candn <= 10; candn++) { -- u32 cur_frequency; -- u32 m; /* 77 - 131. */ -- u32 denom; /* 35 - 560. */ -- u32 current_delta; -- -- denom = candn * candp1 * 7; -- /* Doesnt overflow for up to -- 5000000 kHz = 5 GHz. */ -- m = (target_frequency * denom -- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; -- -- if (m < 77 || m > 131) -- continue; -- -- cur_frequency = (BASE_FREQUENCY * m) / denom; -- if (target_frequency > cur_frequency) -- current_delta = target_frequency - cur_frequency; -- else -- current_delta = cur_frequency - target_frequency; -- -- if (best_delta > current_delta) { -- best_delta = current_delta; -- pixel_n = candn; -- pixel_p1 = candp1; -- pixel_m2 = ((m + 3) % 5) + 7; -- pixel_m1 = (m - pixel_m2) / 5; -+ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; -+ target_frequency = mode->pixel_clock; -+ -+ /* Find suitable divisors, m1, m2, p1, n. */ -+ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ -+ /* should be closest to target frequency as possible */ -+ u32 candn, candm1, candm2, candp1; -+ for (candm1 = 8; candm1 <= 18; candm1++) { -+ for (candm2 = 3; candm2 <= 7; candm2++) { -+ for (candn = 1; candn <= 6; candn++) { -+ for (candp1 = 1; candp1 <= 8; candp1++) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * pixel_p2; -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if ((m < 70) || (m > 120)) -+ continue; -+ if (this_err < smallest_err) { -+ smallest_err = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } - } - } - } - -- if (best_delta == 0xffffffff) { -+ if (smallest_err == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return -1; - } -@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n -- / (pixel_p1 * 7)); -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * pixel_p2)); - - #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(pmmio + FP0(1), -- ((pixel_n - 2) << 16) -- | ((pixel_m1 - 2) << 8) | pixel_m2); -+ (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS -@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (conf->gpu_lvds_use_spread_spectrum_clock - ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV - : 0) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | -@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + HTOTAL(1), - ((hactive + right_border + hblank - 1) << 16) --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch deleted file mode 100644 index 884b2829..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Fri, 2 Sep 2016 22:35:32 +0200 -Subject: [PATCH 1/2] i945/gma.c use latest linux code to calculate divisors. - -The code to compute n, m1, m2, p1 divisors is not correct in coreboot and -on some targets hits a working mode at lower refresh rate, which is why -display is working on some targets. -This patch also fixes reference frequency. - -This patch reuses linux code to correctly compute divisors. - -The result is that some previously not working displays (Lenovo T60 with -1024x786, 1400x1050, 2048x1536) - -TESTED on T60 with 1024x786. - -Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- - 1 file changed, 38 insertions(+), 44 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..3f0b5b4 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -26,6 +26,8 @@ - #include <string.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> -+#include <commonlib/helpers.h> -+ - - #include "i945.h" - #include "chip.h" -@@ -43,7 +45,7 @@ - #define PGETBL_CTL 0x2020 - #define PGETBL_ENABLED 0x00000001 - --#define BASE_FREQUENCY 120000 -+#define BASE_FREQUENCY 100000 - - #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - -@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - u8 edid_data[128]; - unsigned long temp; - int hpolarity, vpolarity; -- u32 candp1, candn; -- u32 best_delta = 0xffffffff; -+ u32 smallest_err = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; -+ u32 pixel_p2; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; -@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - -- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock -- : (2 * mode->pixel_clock); -- -- /* Find suitable divisors. */ -- for (candp1 = 1; candp1 <= 8; candp1++) { -- for (candn = 5; candn <= 10; candn++) { -- u32 cur_frequency; -- u32 m; /* 77 - 131. */ -- u32 denom; /* 35 - 560. */ -- u32 current_delta; -- -- denom = candn * candp1 * 7; -- /* Doesnt overflow for up to -- 5000000 kHz = 5 GHz. */ -- m = (target_frequency * denom -- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; -- -- if (m < 77 || m > 131) -- continue; -- -- cur_frequency = (BASE_FREQUENCY * m) / denom; -- if (target_frequency > cur_frequency) -- current_delta = target_frequency - cur_frequency; -- else -- current_delta = cur_frequency - target_frequency; -- -- if (best_delta > current_delta) { -- best_delta = current_delta; -- pixel_n = candn; -- pixel_p1 = candp1; -- pixel_m2 = ((m + 3) % 5) + 7; -- pixel_m1 = (m - pixel_m2) / 5; -+ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; -+ target_frequency = mode->pixel_clock; -+ -+ /* Find suitable divisors, m1, m2, p1, n. */ -+ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ -+ /* should be closest to target frequency as possible */ -+ u32 candn, candm1, candm2, candp1; -+ for (candm1 = 8; candm1 <= 18; candm1++) { -+ for (candm2 = 3; candm2 <= 7; candm2++) { -+ for (candn = 1; candn <= 6; candn++) { -+ for (candp1 = 1; candp1 <= 8; candp1++) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * pixel_p2; -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if ((m < 70) || (m > 120)) -+ continue; -+ if (this_err < smallest_err) { -+ smallest_err = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } - } - } - } - -- if (best_delta == 0xffffffff) { -+ if (smallest_err == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return -1; - } -@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n -- / (pixel_p1 * 7)); -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * pixel_p2)); - - #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(pmmio + FP0(1), -- ((pixel_n - 2) << 16) -- | ((pixel_m1 - 2) << 8) | pixel_m2); -+ (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS -@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (conf->gpu_lvds_use_spread_spectrum_clock - ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV - : 0) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | -@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + HTOTAL(1), - ((hactive + right_border + hblank - 1) << 16) --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0006-i945-gma.c-add-native-VGA-init.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0006-i945-gma.c-add-native-VGA-init.patch deleted file mode 100644 index 26eed5b4..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0006-i945-gma.c-add-native-VGA-init.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 7ed0951bcf59dfd8b1893232b674455ff8f03f83 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 5 Sep 2016 22:46:11 +0200 -Subject: [PATCH 2/2] i945/gma.c: add native VGA init - -This reuses the Intel Pineview native graphic initialization -to have output on the VGA connector of i945 devices. - -The behavior is the same as with the vendor VBIOS BLOB. -It uses the external VGA display if it is connected. - -Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 196 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 194 insertions(+), 2 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 3f0b5b4..ac19d5a 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase) - return 0; - } - --static int intel_gma_init(struct northbridge_intel_i945_config *conf, -+static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, - unsigned int pphysbase, unsigned int piobase, - void *pmmio, unsigned int pgfx) - { -@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - #endif - return 0; - } -+ -+static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, -+ unsigned int pphysbase, unsigned int piobase, -+ void *pmmio, unsigned int pgfx) -+{ -+ int i; -+ u32 hactive, vactive; -+ u16 reg16; -+ u32 uma_size; -+ -+ printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", -+ (u32)pmmio, piobase, pphysbase); -+ -+ gtt_setup(pmmio); -+ -+ /* Disable VGA. */ -+ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); -+ -+ /* Disable pipes. */ -+ write32(pmmio + PIPECONF(0), 0); -+ write32(pmmio + PIPECONF(1), 0); -+ -+ write32(pmmio + INSTPM, 0x800); -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(pmmio + VGA0, 0x200074); -+ write32(pmmio + VGA1, 0x200074); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); -+ write32(pmmio + DSPCLK_GATE_D, 0); -+ write32(pmmio + FW_BLC, 0x03060106); -+ write32(pmmio + FW_BLC2, 0x00000306); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + 0x7041c, 0x0); -+ -+ write32(pmmio + DPLL_MD(0), 0x3); -+ write32(pmmio + DPLL_MD(1), 0x3); -+ write32(pmmio + DSPCNTR(1), 0x1000000); -+ write32(pmmio + PIPESRC(1), 0x027f01df); -+ -+ vga_misc_write(0x67); -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ // Disable screen memory to prevent garbage from appearing. -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(pmmio + PF_WIN_POS(0), 0); -+ -+ write32(pmmio + PIPESRC(0), (639 << 16) | 399); -+ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(pmmio + PFIT_CONTROL, 0x0); -+ -+ mdelay(1); -+ -+ write32(pmmio + FDI_RX_CTL(0), 0x00002040); -+ mdelay(1); -+ write32(pmmio + FDI_RX_CTL(0), 0x80002050); -+ write32(pmmio + FDI_TX_CTL(0), 0x00044000); -+ mdelay(1); -+ write32(pmmio + FDI_TX_CTL(0), 0x80044000); -+ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(pmmio + VGACNTRL, 0x0); -+ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1); -+ write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); -+ write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); -+ write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); -+ -+ /* Set up GTT. */ -+ -+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); -+ uma_size = 0; -+ if (!(reg16 & 2)) { -+ uma_size = decode_igd_memory_size((reg16 >> 4) & 7); -+ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); -+ } -+ -+ for (i = 0; i < (uma_size - 256) / 4; i++) -+ { -+ outl((i << 2) | 1, piobase); -+ outl(pphysbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ /* Clear interrupts. */ -+ write32(pmmio + DEIIR, 0xffffffff); -+ write32(pmmio + SDEIIR, 0xffffffff); -+ write32(pmmio + IIR, 0xffffffff); -+ write32(pmmio + IMR, 0xffffffff); -+ write32(pmmio + EIR, 0xffffffff); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ return 0; -+ -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should have a correct header */ -+static int vga_connected(u8 *pmmio) { -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(pmmio + GMBUS0); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - #endif - - static void gma_func0_init(struct device *dev) -@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev) - ); - - int err; -- err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ if (vga_connected(mmiobase)) -+ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ iobase, mmiobase, graphics_base); -+ else -+ err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0007-i945-gma.c-generate-fake-VBT.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0007-i945-gma.c-generate-fake-VBT.patch deleted file mode 100644 index 6f0272fd..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0007-i945-gma.c-generate-fake-VBT.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 60cc2c4532f63a40486b7c4e891fb87fb6d4ab7f Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Wed, 7 Sep 2016 22:10:57 +0200 -Subject: [PATCH] i945/gma.c: generate fake VBT - -This generates a fake VBT for the Intel i945 graphic device. -i945 supports both the mobile chipset 945gm (calistoga) -and the desktop chipset 945gc (lakeport), -which is why a VBT with a different id string -needs to be created for each target. - -The VBT id string is obtained from the vbios blob in the following way: -"strings vbios.bin | grep VBT". - -Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..f0944b9 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -433,6 +433,15 @@ static void gma_func0_init(struct device *dev) - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); -+ /* Linux relies on VBT for panel info. */ -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT CALISTOGA "); -+ } -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT LAKEPORT-G "); -+ } - #endif - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch deleted file mode 100644 index 884b2829..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Fri, 2 Sep 2016 22:35:32 +0200 -Subject: [PATCH 1/2] i945/gma.c use latest linux code to calculate divisors. - -The code to compute n, m1, m2, p1 divisors is not correct in coreboot and -on some targets hits a working mode at lower refresh rate, which is why -display is working on some targets. -This patch also fixes reference frequency. - -This patch reuses linux code to correctly compute divisors. - -The result is that some previously not working displays (Lenovo T60 with -1024x786, 1400x1050, 2048x1536) - -TESTED on T60 with 1024x786. - -Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- - 1 file changed, 38 insertions(+), 44 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..3f0b5b4 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -26,6 +26,8 @@ - #include <string.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> -+#include <commonlib/helpers.h> -+ - - #include "i945.h" - #include "chip.h" -@@ -43,7 +45,7 @@ - #define PGETBL_CTL 0x2020 - #define PGETBL_ENABLED 0x00000001 - --#define BASE_FREQUENCY 120000 -+#define BASE_FREQUENCY 100000 - - #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - -@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - u8 edid_data[128]; - unsigned long temp; - int hpolarity, vpolarity; -- u32 candp1, candn; -- u32 best_delta = 0xffffffff; -+ u32 smallest_err = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; -+ u32 pixel_p2; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; -@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - -- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock -- : (2 * mode->pixel_clock); -- -- /* Find suitable divisors. */ -- for (candp1 = 1; candp1 <= 8; candp1++) { -- for (candn = 5; candn <= 10; candn++) { -- u32 cur_frequency; -- u32 m; /* 77 - 131. */ -- u32 denom; /* 35 - 560. */ -- u32 current_delta; -- -- denom = candn * candp1 * 7; -- /* Doesnt overflow for up to -- 5000000 kHz = 5 GHz. */ -- m = (target_frequency * denom -- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; -- -- if (m < 77 || m > 131) -- continue; -- -- cur_frequency = (BASE_FREQUENCY * m) / denom; -- if (target_frequency > cur_frequency) -- current_delta = target_frequency - cur_frequency; -- else -- current_delta = cur_frequency - target_frequency; -- -- if (best_delta > current_delta) { -- best_delta = current_delta; -- pixel_n = candn; -- pixel_p1 = candp1; -- pixel_m2 = ((m + 3) % 5) + 7; -- pixel_m1 = (m - pixel_m2) / 5; -+ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; -+ target_frequency = mode->pixel_clock; -+ -+ /* Find suitable divisors, m1, m2, p1, n. */ -+ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ -+ /* should be closest to target frequency as possible */ -+ u32 candn, candm1, candm2, candp1; -+ for (candm1 = 8; candm1 <= 18; candm1++) { -+ for (candm2 = 3; candm2 <= 7; candm2++) { -+ for (candn = 1; candn <= 6; candn++) { -+ for (candp1 = 1; candp1 <= 8; candp1++) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * pixel_p2; -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if ((m < 70) || (m > 120)) -+ continue; -+ if (this_err < smallest_err) { -+ smallest_err = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } - } - } - } - -- if (best_delta == 0xffffffff) { -+ if (smallest_err == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return -1; - } -@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n -- / (pixel_p1 * 7)); -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * pixel_p2)); - - #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(pmmio + FP0(1), -- ((pixel_n - 2) << 16) -- | ((pixel_m1 - 2) << 8) | pixel_m2); -+ (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS -@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (conf->gpu_lvds_use_spread_spectrum_clock - ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV - : 0) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | -@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + HTOTAL(1), - ((hactive + right_border + hblank - 1) << 16) --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch deleted file mode 100644 index 26eed5b4..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 7ed0951bcf59dfd8b1893232b674455ff8f03f83 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 5 Sep 2016 22:46:11 +0200 -Subject: [PATCH 2/2] i945/gma.c: add native VGA init - -This reuses the Intel Pineview native graphic initialization -to have output on the VGA connector of i945 devices. - -The behavior is the same as with the vendor VBIOS BLOB. -It uses the external VGA display if it is connected. - -Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 196 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 194 insertions(+), 2 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 3f0b5b4..ac19d5a 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase) - return 0; - } - --static int intel_gma_init(struct northbridge_intel_i945_config *conf, -+static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, - unsigned int pphysbase, unsigned int piobase, - void *pmmio, unsigned int pgfx) - { -@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - #endif - return 0; - } -+ -+static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, -+ unsigned int pphysbase, unsigned int piobase, -+ void *pmmio, unsigned int pgfx) -+{ -+ int i; -+ u32 hactive, vactive; -+ u16 reg16; -+ u32 uma_size; -+ -+ printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", -+ (u32)pmmio, piobase, pphysbase); -+ -+ gtt_setup(pmmio); -+ -+ /* Disable VGA. */ -+ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); -+ -+ /* Disable pipes. */ -+ write32(pmmio + PIPECONF(0), 0); -+ write32(pmmio + PIPECONF(1), 0); -+ -+ write32(pmmio + INSTPM, 0x800); -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(pmmio + VGA0, 0x200074); -+ write32(pmmio + VGA1, 0x200074); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); -+ write32(pmmio + DSPCLK_GATE_D, 0); -+ write32(pmmio + FW_BLC, 0x03060106); -+ write32(pmmio + FW_BLC2, 0x00000306); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + 0x7041c, 0x0); -+ -+ write32(pmmio + DPLL_MD(0), 0x3); -+ write32(pmmio + DPLL_MD(1), 0x3); -+ write32(pmmio + DSPCNTR(1), 0x1000000); -+ write32(pmmio + PIPESRC(1), 0x027f01df); -+ -+ vga_misc_write(0x67); -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ // Disable screen memory to prevent garbage from appearing. -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(pmmio + PF_WIN_POS(0), 0); -+ -+ write32(pmmio + PIPESRC(0), (639 << 16) | 399); -+ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(pmmio + PFIT_CONTROL, 0x0); -+ -+ mdelay(1); -+ -+ write32(pmmio + FDI_RX_CTL(0), 0x00002040); -+ mdelay(1); -+ write32(pmmio + FDI_RX_CTL(0), 0x80002050); -+ write32(pmmio + FDI_TX_CTL(0), 0x00044000); -+ mdelay(1); -+ write32(pmmio + FDI_TX_CTL(0), 0x80044000); -+ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(pmmio + VGACNTRL, 0x0); -+ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1); -+ write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); -+ write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); -+ write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); -+ -+ /* Set up GTT. */ -+ -+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); -+ uma_size = 0; -+ if (!(reg16 & 2)) { -+ uma_size = decode_igd_memory_size((reg16 >> 4) & 7); -+ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); -+ } -+ -+ for (i = 0; i < (uma_size - 256) / 4; i++) -+ { -+ outl((i << 2) | 1, piobase); -+ outl(pphysbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ /* Clear interrupts. */ -+ write32(pmmio + DEIIR, 0xffffffff); -+ write32(pmmio + SDEIIR, 0xffffffff); -+ write32(pmmio + IIR, 0xffffffff); -+ write32(pmmio + IMR, 0xffffffff); -+ write32(pmmio + EIR, 0xffffffff); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ return 0; -+ -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should have a correct header */ -+static int vga_connected(u8 *pmmio) { -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(pmmio + GMBUS0); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - #endif - - static void gma_func0_init(struct device *dev) -@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev) - ); - - int err; -- err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ if (vga_connected(mmiobase)) -+ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ iobase, mmiobase, graphics_base); -+ else -+ err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch deleted file mode 100644 index 6f0272fd..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 60cc2c4532f63a40486b7c4e891fb87fb6d4ab7f Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Wed, 7 Sep 2016 22:10:57 +0200 -Subject: [PATCH] i945/gma.c: generate fake VBT - -This generates a fake VBT for the Intel i945 graphic device. -i945 supports both the mobile chipset 945gm (calistoga) -and the desktop chipset 945gc (lakeport), -which is why a VBT with a different id string -needs to be created for each target. - -The VBT id string is obtained from the vbios blob in the following way: -"strings vbios.bin | grep VBT". - -Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..f0944b9 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -433,6 +433,15 @@ static void gma_func0_init(struct device *dev) - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); -+ /* Linux relies on VBT for panel info. */ -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT CALISTOGA "); -+ } -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT LAKEPORT-G "); -+ } - #endif - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch b/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch deleted file mode 100644 index 187dbc9a..00000000 --- a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch +++ /dev/null @@ -1,415 +0,0 @@ -From 9659556d9edbba6c3530ed1d0630add30419210f Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sun, 4 Sep 2016 16:01:11 +0200 -Subject: [PATCH 1/2] x4x/gma.c: Add VESA native resolution mode - -This patch implements native resolution, VESA mode, on the VGA output of -x4x. - -It relies on EDID to modeset, but has a fallback-mode (640 x 480 @ -60Hz) if this is no EDID could be found. This fallback mode only works in textmode -since in VESA mode some payloads (grub2) rely on VBE info, which is being -generated from an EDID. - -Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/x4x/gma.c | 282 ++++++++++++++++++++++++++++++++++------ - 1 file changed, 242 insertions(+), 40 deletions(-) - -diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c -index 2679026..118f98d 100644 ---- a/src/northbridge/intel/x4x/gma.c -+++ b/src/northbridge/intel/x4x/gma.c -@@ -26,24 +26,68 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" - #include "x4x.h" - #include <drivers/intel/gma/intel_bios.h> -+#include <drivers/intel/gma/edid.h> - #include <drivers/intel/gma/i915.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUENCY 96000 -+ -+static u8 edid_is_null(u8 *edid, u32 edid_size) -+{ -+ u32 i; -+ for (i = 0; i < edid_size; i++) { -+ if (*(edid + i) != 0) -+ return 0; -+ } -+ return 1; -+} - static void intel_gma_init(const struct northbridge_intel_x4x_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -+ - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u8 edid_not_found; -+ -+ /* Initialise mode variables for 640 x 480 @ 60Hz */ -+ u32 hactive = 640, vactive = 480; -+ u32 right_border = 0, bottom_border = 0; -+ int hpolarity = 0, vpolarity = 0; -+ u32 hsync = 96, vsync = 2; -+ u32 hblank = 160, vblank = 45; -+ u32 hfront_porch = 16, vfront_porch = 10; -+ u32 target_frequency = 25175; -+ -+ u32 err_most = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Set up GTT */ -+ for (i = 0; i < 0x1000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -73,107 +117,258 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ edid_not_found = edid_is_null(edid_data, sizeof(edid_data)); -+ if (!edid_not_found) { -+ printk(BIOS_DEBUG, "EDID is not null"); -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ } else -+ printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode"); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 16; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST( -+ BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < err_most) { -+ err_most = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (err_most == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * 10)); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ hactive * vactive * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } - } - - static void native_init(struct device *dev) - { -+ struct resource *lfb_res; -+ struct resource *pio_res; -+ u32 physbase; - struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); - struct northbridge_intel_x4x_config *conf = dev->chip_info; - -+ lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); -+ pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); -+ physbase = pci_read_config32(dev, 0x5c) & ~0xf; -+ - if (gtt_res && gtt_res->base) { - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0)); -+ intel_gma_init(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ -@@ -182,6 +377,7 @@ static void native_init(struct device *dev) - - static void gma_func0_init(struct device *dev) - { -+ u16 reg16; - u32 reg32; - - /* IGD needs to be Bus Master */ -@@ -189,6 +385,12 @@ static void gma_func0_init(struct device *dev) - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - -+ /* configure GMBUSFREQ */ -+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc); -+ reg16 &= ~0x1ff; -+ reg16 |= 0xbc; -+ pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc, reg16); -+ - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) - native_init(dev); - else --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch b/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch deleted file mode 100644 index d579df55..00000000 --- a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch +++ /dev/null @@ -1,30 +0,0 @@ -From f9a84edfc672424c9dcaa0a71ad0751c2355c3d0 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 5 Sep 2016 12:07:57 +0200 -Subject: [PATCH 2/2] gigabyte/ga-g41m-es2l: add VESA mode to Kconfig - -This patch adds MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG to the -gigabyte/ga-g41m-es2l Kconfig to allow selecting between textmode and -vesamode in menuconfig. - -Change-Id: I84b61118fa0419d49d2498b66029711cdce97576 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig -index 6452f4d..281d498 100644 ---- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig -+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig -@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS - select BOARD_ROMSIZE_KB_1024 - select INTEL_EDID - select MAINBOARD_HAS_NATIVE_VGA_INIT -+ select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list index 451d1b75..145d6c30 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list index 4ea9a7ad..0ed8edc9 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list @@ -1,4 +1,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch index 26632b7d..26632b7d 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch index ef42f3e8..ef42f3e8 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch index fb30c4c2..fb30c4c2 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/INFO b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/INFO new file mode 100644 index 00000000..0537bbc8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/INFO @@ -0,0 +1,4 @@ +# NOTE: remove this when updating coreboot. This has been merged upstream +printf "ThinkPad T500 (depends on T400 patch)\n" +git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/reused.list new file mode 100644 index 00000000..59e0a36a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch index 26632b7d..26632b7d 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch index ef42f3e8..ef42f3e8 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch index fb30c4c2..fb30c4c2 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/reused.list new file mode 100644 index 00000000..59e0a36a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch index 26632b7d..26632b7d 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch index ef42f3e8..ef42f3e8 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch index fb30c4c2..fb30c4c2 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/INFO b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/INFO new file mode 100644 index 00000000..0537bbc8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/INFO @@ -0,0 +1,4 @@ +# NOTE: remove this when updating coreboot. This has been merged upstream +printf "ThinkPad T500 (depends on T400 patch)\n" +git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/reused.list new file mode 100644 index 00000000..59e0a36a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list index 8a98e98c..71fc4dfc 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list @@ -2,4 +2,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list index 8a98e98c..71fc4dfc 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list @@ -2,4 +2,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch deleted file mode 100644 index d89e4884..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 0821d0290e7e17e375ffdb48a86b56504db4f77e Mon Sep 17 00:00:00 2001 -From: Damien Zammit <damien@zamaudio.com> -Date: Sat, 27 Aug 2016 00:35:48 +1000 -Subject: [PATCH] nb/intel/gm45: Fix IOMMU - -Previously the ME was being reported as present in ACPI -even when it's firmware was missing. Now we do a check via the pci device -(HECI) to verify if the ME is there or not. - -Note that this test could fail if ME is present but disabled in devicetree, -but in that case you won't see it in the lspci tree anyway so it shouldn't -be an issue. - -Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0 -Signed-off-by: Damien Zammit <damien@zamaudio.com> ---- - src/northbridge/intel/gm45/acpi.c | 3 ++- - src/northbridge/intel/gm45/iommu.c | 2 ++ - 2 files changed, 4 insertions(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c -index 8990c3b..b90afca 100644 ---- a/src/northbridge/intel/gm45/acpi.c -+++ b/src/northbridge/intel/gm45/acpi.c -@@ -72,7 +72,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) - - static unsigned long acpi_fill_dmar(unsigned long current) - { -- int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL); -+ int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL) && -+ (pci_read_config8(dev_find_slot(0, PCI_DEVFN(3, 0)), PCI_CLASS_REVISION) != 0xff); - int stepping = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_CLASS_REVISION); - - unsigned long tmp = current; -diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c -index 10548f4..0c3c18e 100644 ---- a/src/northbridge/intel/gm45/iommu.c -+++ b/src/northbridge/intel/gm45/iommu.c -@@ -40,6 +40,8 @@ void init_iommu() - } - if (me_active) { - MCHBAR32(0x10) = IOMMU_BASE3 | 1; /* ME @ 0:3.0-3 */ -+ } else { -+ MCHBAR32(0x10) = 0; /* disable IOMMU for ME */ - } - MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */ - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/scripts/helpers/build/roms/withgrub b/resources/scripts/helpers/build/roms/withgrub index d4b6529b..28f35736 100755 --- a/resources/scripts/helpers/build/roms/withgrub +++ b/resources/scripts/helpers/build/roms/withgrub @@ -95,7 +95,7 @@ done # Then put them in the ROM images. if [ -d "bin/grub/" ]; then cd "bin/grub/" - for board in "x200" "r400" "t400" "t500" + for board in "x200" "r400" "t400" "t500" "w500" do for romsize in "4m" "8m" "16m" do diff --git a/resources/scripts/helpers/build/roms/withgrub_helper b/resources/scripts/helpers/build/roms/withgrub_helper index c4e14b29..26d69f0b 100755 --- a/resources/scripts/helpers/build/roms/withgrub_helper +++ b/resources/scripts/helpers/build/roms/withgrub_helper @@ -88,7 +88,7 @@ fi for romtype in txtmode vesafb do - if [ "${boardtarget}" = "kgpe-d16" ] || [ "${boardtarget}" = "kcma-d8" ] || [ "${boardtarget}" = "d510mo" ]; then + if [ "${boardtarget}" = "kgpe-d16" ] || [ "${boardtarget}" = "ga-g41m-es2l" ] || [ "${boardtarget}" = "kcma-d8" ] || [ "${boardtarget}" = "d510mo" ]; then if [ "${romtype}" = "vesafb" ]; then printf "Only text-mode is reported to work on KGPE-D16, KCMA-D8, D510MO and ga-g41m-es2l\n" printf "TODO: get tpearson to fix it\n" @@ -150,7 +150,8 @@ do # Add the background image if [ "$romtype" = "vesafb" ] then - if [ "$1" = "macbook21" ] || [ "$1" = "x200_4mb" ] || [ "$1" = "x200_8mb" ] || [ "$1" = "x200_16mb" ] || [ "$1" = "r400_4mb" ] || [ "$1" = "r400_8mb" ] || [ "$1" = "r400_16mb" ] || [ "$1" = "t400_4mb" ] || [ "$1" = "t400_8mb" ] || [ "$1" = "t400_16mb" ] || [ "$1" = "t500_4mb" ] || [ "$1" = "t500_8mb" ] || [ "$1" = "t500_16mb" ] + if [ "$1" = "macbook21" ] || [ "$1" = "x200_4mb" ] || [ "$1" = "x200_8mb" ] || [ "$1" = "x200_16mb" ] || [ "$1" = "r400_4mb" ] || [ "$1" = "r400_8mb" ] || [ "$1" = "r400_16mb" ] || [ "$1" = "t400_4mb" ] || [ "$1" = "t400_8mb" ] || [ "$1" = "t400_16mb" ] || [ "$1" = "t500_4mb" ] || [ "$1" = "t500_8mb" ] || [ "$1" = "t500_16mb" ] || [ "$1" = "w500_4mb" ] || [ "$1" = "w500_8mb" ] || [ "$1" = "w500_16mb" ] + then ./util/cbfstool/cbfstool "${boardtarget}_${romtype}.rom" add -f ../../../resources/grub/background/background1280x800.png -n background.png -t raw else diff --git a/resources/scripts/helpers/download/flashrom b/resources/scripts/helpers/download/flashrom index e7a58949..a706e9ee 100755 --- a/resources/scripts/helpers/download/flashrom +++ b/resources/scripts/helpers/download/flashrom @@ -49,7 +49,7 @@ git reset --hard # Apply patches # ------------------------------------------------------------------------------ -printf "Enabling whitelist for X200S, X200 Tablet, T400, T500 and R400\n" +printf "Enabling whitelist for X200S, X200 Tablet, T400, T500, W500 and R400\n" git am "../resources/flashrom/patch/0001-New-laptops-whitelisted-ThinkPad-R400-and-ThinkPad-T.patch" printf "Enabling whitelist for Libiquity Taurinus X200\n" diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/blobs.list b/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/blobs.list deleted file mode 100644 index a8a9a964..00000000 --- a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/blobs.list +++ /dev/null @@ -1,52 +0,0 @@ -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c -src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000f.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c -src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c -src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c 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-src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h -src/vendorcode/amd/cimx/rd890/HotplugFirmware.h -src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc -src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h -src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h -src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h -src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h -src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs.list b/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs.list deleted file mode 100644 index 6f672156..00000000 --- a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs.list +++ /dev/null @@ -1,335 +0,0 @@ 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-src/cpu/intel/fsp_model_406dx/acpi.c -src/northbridge/intel/fsp_sandybridge/fsp/Kconfig -src/drivers/aspeed/common/ast_dram_tables.h -src/drivers/aspeed/common/ast_tables.h -src/mainboard/intel/cougar_canyon2/Kconfig -src/cpu/amd/family_10h-family_15h/processor_name.c -src/cpu/amd/family_10h-family_15h/init_cpus.c -src/cpu/intel/fsp_model_206ax/acpi.c diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs_notes b/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs_notes deleted file mode 100644 index 551da4a8..00000000 --- a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs_notes +++ /dev/null @@ -1,15 +0,0 @@ -.spd.hex files - serial presence detect. These are not blobs -see JEDEC standard or https://en.wikipedia.org/wiki/Serial_presence_detect -These are added to the nonblobs file - -src/northbridge/intel/nehalem/raminit_tables.c" -src/northbridge/intel/sandybridge/raminit_patterns.h -These are used by native raminit for the relevant platforms, and are not blobs - -"src/southbridge/nvidia/mcp55/early_setup_ss.h" \ -"src/southbridge/nvidia/ck804/early_setup_ss.h" \ -"src/southbridge/sis/sis966/early_setup_ss.h" -not blobs - -The text in this file is CC-BY-SA 4.0 or higher. All contributions to it must -be made under the same license. diff --git a/www/download.md b/www/download.md index 321d0679..325c29c5 100644 --- a/www/download.md +++ b/www/download.md @@ -36,28 +36,21 @@ HTTPS mirrors {#https} These mirrors are recommended, since they use TLS (https://) encryption. -<https://mirrors.peers.community/mirrors/libreboot/> (Peers Community -Project, USA) - <https://www.mirrorservice.org/sites/libreboot.org/release/> (University of Kent, UK) <https://mirror.math.princeton.edu/pub/libreboot/> (Princeton university, USA) -<https://mirrors.cicku.me/libreboot/> (CICKU FOSS Mirror Service, -Germany) +<https://mirrors.peers.community/mirrors/libreboot/> (Peers Community +Project, USA) <https://vimuser.org/libreboot/> (vimuser.org, Netherlands) -<https://ginette.swordarmor.fr/libreboot/> (swordarmor.fr, France) - <https://mirror.se.partyvan.eu/pub/libreboot/> (partyvan.eu, Sweden) <https://elgrande74.net/libreboot/> (elgrande74.net, France) -<https://nedson.net/libreboot> (nedson.net, USA) - HTTP mirrors {#http} ------------ @@ -78,6 +71,8 @@ Undisclosed location) <http://libreboot.mirror.si/> (mirror.si, Slovenia) +<http://ginette.swordarmor.fr/libreboot/> (swordarmor.fr, France) + FTP mirrors {#ftp} ----------- diff --git a/www/footer.md b/www/footer.md new file mode 100644 index 00000000..dfddfd75 --- /dev/null +++ b/www/footer.md @@ -0,0 +1,7 @@ + +[License](/docs/fdl-1.3.md) -- +[Template](/license.md) -- +[Authors](/contrib.md) -- +[Conduct Guidelines](/conduct.md) -- +[Management Guidelines](/management.md) -- +[Peers Community](https://peers.community/) -- @@ -33,6 +33,31 @@ GNU+Linux distributions package it in their repositories). GNU+Linux is generally recommended as the OS of choice, for Libreboot development. +General code review guidelines +------------------------------ + +Non-core members will push to their own repository, and issue a Pull Request. +Core maintainers of Libreboot can push to the repository, but not to the master +branch; they must push it to a non-master branch, and again issue a Pull +Request. + +An individual or group of people will then review the patch sent by the +contributor. With approval from a core maintainer, or otherwise someone with +merge rights on the repository, the patch will be merged into the official +*master* branch. + +Those with push/merge access on the official Libreboot repository must never +directly push their own patches to the master branch, and they must never +merge their own Pull Request. Regardless of the individual's standing and +frequency of contributions within the project, those who decide whether to +merge a patch will *always* differ from the original contributor. + +These guidelines are *enforced*, to avoid the appearance of a BDFL (Benevolent +Dictator for Life) in the Libreboot project, as one previously existed in the +project. Libreboot is a collectively and democratically governed project. +Maintainers who violate these guidelines may, at the discretion of other +maintainers, have their push/merge rights revoked. + How to download Libreboot from the Git repository ------------------------------------------------- diff --git a/www/global.css b/www/global.css index 0264e4ef..b325ef31 100644 --- a/www/global.css +++ b/www/global.css @@ -13,11 +13,8 @@ body { body { line-height: 1.6; font-family: Cantarell, sans-serif; - font-size: 1.1em; color: #222; -} - -header { - text-align: center; + font-size: 1.1em; + color: #222; } #logo { @@ -37,3 +34,11 @@ a:hover { .date { display: block; } + +h1, h2, h3, .h:hover a { + display: inline; +} + +.h a { + display: none; +} diff --git a/www/headercenter.css b/www/headercenter.css new file mode 100644 index 00000000..6b8c294c --- /dev/null +++ b/www/headercenter.css @@ -0,0 +1,3 @@ +header { + text-align: center; +} diff --git a/www/headerleft.css b/www/headerleft.css deleted file mode 100644 index 645ab4ea..00000000 --- a/www/headerleft.css +++ /dev/null @@ -1,3 +0,0 @@ -header { - text-align: left !important; -} diff --git a/www/index.md b/www/index.md index 63dc327b..f15b3082 100644 --- a/www/index.md +++ b/www/index.md @@ -8,19 +8,24 @@ mascot"){#logo}](faq.md#who-did-the-logo) [FAQ](faq.md) -- [Download](download.md) -- [Install](docs/install/) -- -[Documentation](docs/) -- +[Docs](docs/) -- [News](news/) -- -[Contact/IRC](https://webchat.freenode.net/?channels=libreboot) -- -[Report bugs](https://notabug.org/libreboot/libreboot/issues) -- -[Send patches](git.md) +[IRC](https://webchat.freenode.net/?channels=libreboot) -- +[Bugs](https://notabug.org/libreboot/libreboot/issues) -- +[Contribute](git.md) -- +[Management](management.md) -- +[Tasks](https://notabug.org/libreboot/libreboot/milestones) -Libreboot is a [free](https://www.gnu.org/philosophy/free-sw.html) and Open -Source BIOS or UEFI replacement, initialising the hardware and booting your -operating system. We are a member of the -[Peers Community](https://peers.community/) project, an organisation that -supports Free Software. +Libreboot is a [free](https://www.gnu.org/philosophy/free-sw.html) (as in +freedom) BIOS or UEFI replacement, initialising the hardware and booting your +operating system. -**[Libreboot no longer opposes FSF/GNU. Read our open peace letter to the community.](news/unity.md)** +**[Community feedback is needed on whether libreboot.org domain name +ownership should be transferred to the +Software Freedom Conservancy](news/sfc-domain-offer.md)** + +**[Libreboot has applied to re-join the GNU project, +under new democratic leadership](news/formalised-structure.md)** Why use Libreboot? ------------------ @@ -42,6 +47,3 @@ which we deblob. We upstream our custom patches to projects like coreboot, depthcharge, GRUB, and flashrom where possible. Together, we provide an automated build and installation system with nontechnical documentation, allowing Libreboot to be widely used. - -[Watch our FOSDEM 2017 presentation about Libreboot (speaker is Leah -Rowe)](https://video.fosdem.org/2017/K.1.105/libreboot.mp4) diff --git a/www/license.md b/www/license.md index eecf1c2f..d70a4733 100644 --- a/www/license.md +++ b/www/license.md @@ -1,17 +1,4 @@ -Website: - -Copyright 2015-2017 Leah Rowe <info@minifree.org> \ -Copyright 2017 Alyssa Rosenzweig <alyssa@rosenzweig.io> - -This document is released under the Creative Commons Attribution-ShareAlike 4.0 -International Public License and all future versions. A copy of the license -can be found at "cc-by-sa-4.txt". - -This document is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS -FOR A PARTICULAR PURPOSE. See cc-by-sa-4.txt for more information. - -Template: +Pandoc template used on the Libreboot website: Copyright (c) 2014--2017, John MacFarlane diff --git a/www/management.md b/www/management.md new file mode 100644 index 00000000..629d5cd7 --- /dev/null +++ b/www/management.md @@ -0,0 +1,115 @@ +--- +title: General management guidelines and leadership information +x-toc-enable: true +... + +This document sets out general guidelines for how the Libreboot project is +governed, managed and who constitutes the core leadership of the project. + +All project members must act according to the +[Guidelines for Good Conduct in the Libreboot community](conduct.md). + +Democratic governance of the Libreboot project +---------------------------------------------- + +Previously, the Libreboot leadership was a BDFL (Benevolent Dictator For Life) +arrangement, with the project's founder (Leah Rowe) having exclusive control +over the project, delegating tasks (by her own exclusive discretion) to others. +This style was very similar to the leadership structure of the Linux kernel +project via Linus Torvalds and, while initially effective, was found to be +ineffective and counter-productive in the long term. + +The old leadership structure has been **abandoned**, and Leah is no longer leader +of the Libreboot project. This decision was made democratically and +collectively, by the same overall standards set out in this document, with +Leah's direct approval and participation, in the best long-term interests of +the Libreboot project, where she agreed to stand down as project leader. + +In principle and in practise, Libreboot is now a collectively and democratically +governed project. Any individual member of the community, regardless of their +current standing or reputation, can propose changes to the project (this +includes code/documentation contributions, project management decisions and +so on). The proposal can be absolutely anything, within reason where it is +relevant to Libreboot and could be beneficial. + +All proposals are subject to review and approval by the community. In the case +of code patches, any member of the public can also voice their opinions on a +contribution; the patch will also be reviewed by one of the core maintainers +of the project. In the case of general project decisions, such as general +policies of the project and management roles (such as, removing a core member +who starts acting out of line with and/or in violation of project policies), +the decision will also be polled by the community, to assess public support for +such a decision. With public approval, and agreement among the core maintainers, +the decision would then be enacted, and it falls on them to implement the +mandate that was set, whatever that mandate might be. + +Actual places to poll members of the public, shall be decided on by the core +maintainers. Examples could include the IRC channel, the subreddit r/libreboot, +the mailing list (if one exists), and any other place deemed appropriate. + +Those who are part of the core maintainers and core management team, can be +appointed and removed at the behest of popular public demand, with approval +from the current +core maintainers and/or management team within the Libreboot project. + +Generally, the project should not have a single leader, but if such a role is +required in the future, it will be a rotating leadership, to be changed +after a certain period, subject to approval by the core maintainers and by +popular public demand. Exact infrastructure for how to cast such votes and +make such appointments will be decided at that time, when it becomes necessary +for the Libreboot project. + +Information about Libreboot's code review and code management guidelines +can be found +[on the Git section of the website](git.md#general-code-review-guidelines). + +Information about core team members, responsible for the Libreboot project +-------------------------------------------------------------------------- + +- Alyssa Rosenzweig handles Communications and Public Relations\*, acting + additionally as the official System Administrator for the Libreboot project + infrastructure. + IRC nick **alyssa** on Freenode. +- Paul Kocialkowski is one of the core developers. IRC nick **paulk-X** on + Freenode (**X** is variable, for this individual, and changes over time) +- Leah Rowe is one of the core developers. IRC nick **\_4of7** on Freenode +- Swift Geek is one of the core developers. IRC nick **swiftgeek** on Freenode + +All of the people above are moderators in the Libreboot IRC channel, and +form the basis of the project's collective inner leadership, responsible as +trustees for the project in ensuring the projects long-term success and for +general management of the project. + +All core members have push access to the Git repository for Libreboot. +Additionally, Alyssa and Leah have SSH access (including root) to the main +server for libreboot.org (this list will expand, if Alyssa and Leah both agree +and if it is appropriate, e.g. if more System Administrators join the +project). + +Any member of the public can join this list, if they make substantial +contributions and the core team members agree to it. Libreboot's leadership is +open to the public. + +Other team members (IRC operators) who also have influence: + +- IRC nick **specing** on the Libreboot IRC channel. +- IRC nick **pizzaiolo** on the Libreboot IRC channel. +- IRC nick **jxself** on the Libreboot IRC channel. + +Additionally, Libreboot has a separate set of operators on the subreddit +r/libreboot. Check Reddit for more information. Actions taken by moderators +there are also subject to these management guidelines. + +GNU project oversight (pending Libreboot's potential GNU membership) +-------------------------------------------------------------------- + +Libreboot has applied to become a member of the GNU project, per agreement by +the core maintainers, plus widespread public support. This is being +handled by Alyssa. It is not yet known whether GNU will accept Libreboot, and +we (the core maintainers) are awaiting their response. + +If Libreboot is accepted as a GNU member, then the GNU project will also form +as part of Libreboot's core leadership, overseeing the project. This will +include Richard Stallman. GNU's own leadership is separate from that of the +Libreboot project (and vice versa), at present, but they would merge on +Libreboot's side if a union does occur. diff --git a/www/news/formalised-structure.md b/www/news/formalised-structure.md new file mode 100644 index 00000000..a630ff23 --- /dev/null +++ b/www/news/formalised-structure.md @@ -0,0 +1,35 @@ +% Formalising Democracy +% Alyssa Rosenzweig +% 25 Apr 2017 + +One month ago, the [Open Letter to the Free Software Community](/news/unity.md) +was published, alluding to the new Libreboot leadership. Today, the ideals +expressed there have been formalised into an official project policy. In the +new [General Management Guidelines](/management.md), the ins-and-outs of our +democratic system is codified, including the formal team list. Hint, hint: the +structure isn't "I, Alyssa Rosenzweig, decide everything and Thou shall bow +down to me"! There are four core team members, and we welcome community +feedback for major decisions. + +There was an underlying tension in the letter: should Libreboot rejoin GNU? On +purely political and technical levels, the answer is a resounding "yes". We +share the mission of spreading free software. Our communities overlap. Most of +the Libreboot community uses GNU software, and much of GNU uses libreboot. +Technically, the tighter integration is useful. Politically, closer ties will +strengthen both of our projects. But this is neither completely a political or +technical question -- it is a human one. + +There is no easy answer to this. But the best course of action is to reach out +beyond the team to the community at large. A number of people ranging from +Libreboot users to GNU developers to casual bystanders chimed in, and the +answer was an overwhelming "yes, you should have done this a month ago!" + +With that in mind, we have reapplied for GNU. Leah conducted the initial +discussions, such as the Reddit thread, as she felt that she needed to correct +her own error. I have since been handling the application itself, which was +submitted recently. GNU has not yet made a decision on the matter. Ultimately, +it will be up to Richard Stallman himself whether the mutual benefits of +joining will outweigh any potential awkwardness. + +No matter the response, Libreboot remains committed to free software. Whether +or not we need a g'new name, this will never change. diff --git a/www/news/fsf-domain-offer.md b/www/news/fsf-domain-offer.md new file mode 100644 index 00000000..486e4cfc --- /dev/null +++ b/www/news/fsf-domain-offer.md @@ -0,0 +1,15 @@ +% Community feedback on whether to offer libreboot.org domain name to FSF +% Leah Rowe +% 26 Apr 2017 + +I, Leah Rowe, have stepped down as leader of the Libreboot project. This means +that I must also transfer ownership of the libreboot.org domain name to +another entity. I have chosen to propose the FSF as that entity. + +This is something that could be offered to GNU as part of Libreboot's +filed application to re-join GNU. + +Commenting will be taken on +<https://www.reddit.com/r/libreboot/comments/67rd46/proposal_transfer_librebootorg_ownership_to_fsf/> +as to whether this decision should be taken. Full reasoning is documented +there. diff --git a/www/news/proposal-rejoin-gnu.md b/www/news/proposal-rejoin-gnu.md new file mode 100644 index 00000000..795821e1 --- /dev/null +++ b/www/news/proposal-rejoin-gnu.md @@ -0,0 +1,9 @@ +% Community feedback needed on whether Libreboot should re-join the GNU project +% +% 22 Apr 2017 + +Community feedback is needed on whether Libreboot should re-join the GNU +project, having previously been a member. The discussion place for this topic +is on [this thread in the Libreboot subreddit at reddit.com/r/libreboot/](https://www.reddit.com/r/libreboot/comments/66tdds/proposal_for_libreboot_rejoin_gnu_community/). With sufficient community support, Libreboot will +apply to re-join to become a member of the GNU project. Full reasoning and +history behind this proposal is detailed in the thread. diff --git a/www/news/sfc-domain-offer.md b/www/news/sfc-domain-offer.md new file mode 100644 index 00000000..f53ce283 --- /dev/null +++ b/www/news/sfc-domain-offer.md @@ -0,0 +1,36 @@ +% Community feedback on whether to offer libreboot.org domain name to SFC +% Leah Rowe +% 27 Apr 2017 + +I, Leah Rowe, have stepped down as leader of the Libreboot project. This means +that I must also transfer ownership of the libreboot.org domain name to +another entity. I have chosen to propose the Software Freedom Conservancy (SFC) +as that entity. + +Commenting will be taken on +<https://www.reddit.com/r/libreboot/comments/67x3bs/proposal_transfer_librebootorg_domain_name/> +as to whether this decision should be taken. Full reasoning is documented +there. + +Software Freedom Conservancy is heavily affiliated with the FSF. Conservancy +provides legal services, e.g. GPL enforcement, for those who violate the GNU +General Public License. They generally offer legal services related to Free +Software. Its founder, Bradley Kuhn, is also a former Executive Director of +the FSF. (Karen Sandler, is SFC's current Executive Director). + +In addition to legal services, Conservancy also helps promote Free Software +and provides certain infrastructure for Free Software projects, and does +sometimes assist in development of projects. + +More information: +<https://en.wikipedia.org/wiki/Software_Freedom_Conservancy> + +Conservancy website: +<https://sfconservancy.org/> + +This is something that could be offered to GNU as part of Libreboot's +filed application to re-join GNU. + +Previously, it was proposed that the domain name be transferred to the FSF, but +this was vetoed by an opposing member of the core leadership, when I proposed +it. SFC was then recommended as an alternative, hence this new proposal. diff --git a/www/publish.sh b/www/publish.sh index 098df29c..e75ec332 100755 --- a/www/publish.sh +++ b/www/publish.sh @@ -35,13 +35,15 @@ if [ "${FILE}" != "./index" ]; then fi RETURN="<a href='$DEST'>Back to previous index</a>" - OPTS="--css /headerleft.css -T Libreboot" + OPTS="-T Libreboot" +else + OPTS="--css /headercenter.css" fi -echo "" >> temp.md -printf "[License](/license.md) --\n" >> temp.md -printf "[Information about the Libreboot authors](/contrib.md) --\n" >> temp.md -printf "[Please read our guidelines for good conduct](/conduct.md)\n" >> temp.md + +if [ "${FILE}" != "./docs/fdl-1.3" ] && [ "${FILE}" != "./conduct" ]; then + cat footer.md >> temp.md +fi # change out .md -> .html sed temp.md -i -e 's/\.md\(#[a-z\-]*\)*)/.html\1)/g' @@ -59,3 +61,6 @@ pandoc $TOC $SMART temp.md -s --css /global.css $OPTS \ # additionally, produce bare file for RSS pandoc $1 > $FILE.bare.html + +# generate section title anchors as [link] +sed $FILE.html -i -e 's_^<h\([123]\) id="\(.*\)">\(.*\)</h\1>_<div class="h"><h\1 id="\2">\3</h\1><a aria-hidden="true" href="#\2">[link]</a></div>_' |
