diff options
178 files changed, 1770 insertions, 451 deletions
diff --git a/docs/gnulinux/encrypted_debian.md b/docs/gnulinux/encrypted_debian.md index 83f0dd28..23b4503f 100644 --- a/docs/gnulinux/encrypted_debian.md +++ b/docs/gnulinux/encrypted_debian.md @@ -5,6 +5,16 @@ title: Installing Debian or Devuan GNU+Linux with full disk encryption (includin This guide is written for the Debian distribution, but it should also work for Devuan with the net installer. +Gigabyte GA-G41M-ES2L +===================== + +To boot the Trisquel net installer, make sure to specify fb=false on the linux +kernel parameters in GRUB. This will boot the installer in text mode instead +of using a framebuffer. + +Moving on... +============ + Libreboot on x86 uses the GRUB [payload](http://www.coreboot.org/Payloads#GRUB_2) by default, which means that the GRUB configuration file (where your GRUB menu comes from) diff --git a/docs/gnulinux/encrypted_parabola.md b/docs/gnulinux/encrypted_parabola.md index 99d5dee7..30b9261d 100644 --- a/docs/gnulinux/encrypted_parabola.md +++ b/docs/gnulinux/encrypted_parabola.md @@ -181,8 +181,10 @@ Check to make sure tha the partition was created: # pvdisplay Next, we create the volume group, inside of which the logical volumes will -be created. For this example, we will call this group **matrix**. You can call -yours whatever you would like; just make sure that you remember its name: +be created. In libreboot's case, we will call this group **matrix**. +If you want to have it work via *Load Operating System (incl. fully +encrypted disks) [o]* it needs to be called **matrix** (as it is harcoded +in libreboot's grub.cfg on the flash) # vgcreate matrix /dev/mapper/lvm diff --git a/docs/gnulinux/encrypted_trisquel.md b/docs/gnulinux/encrypted_trisquel.md index 8768c5c7..32ff87f6 100644 --- a/docs/gnulinux/encrypted_trisquel.md +++ b/docs/gnulinux/encrypted_trisquel.md @@ -5,6 +5,12 @@ x-toc enable: true This guide is written for the Trisquel 7.0 (Belenos) GNU+Linux distribution, but it should also work for Trisquel 6.0 (Toutatis). +## Gigabyte GA-G41M-ES2L + +To boot the Trisquel net installer, make sure to specify fb=false on the linux +kernel parameters in GRUB. This will boot the installer in text mode instead +of using a framebuffer. + ## Boot the Installation Media Boot your operating system, with the installation media. If you don't know how to do so, refer to [How to Prepare and Boot a USB Installer in Libreboot Systems](grub_boot_installer.md). diff --git a/docs/gnulinux/grub_boot_installer.md b/docs/gnulinux/grub_boot_installer.md index 7d4375e6..48ecaa37 100644 --- a/docs/gnulinux/grub_boot_installer.md +++ b/docs/gnulinux/grub_boot_installer.md @@ -69,13 +69,16 @@ Thirdly, boot the USB and enter these commands in the GRUB terminal grub> boot If you are on a 32-bit system (e.g. some Thinkpad X60's) then you will need to -use these commands instead: +use these commands (this is also true for 32-bit running on 64-bit machines): grub> set root='usb0' grub> linux /install.386/vmlinuz grub> initrd /install.386/initrd.gz grub> boot +NOTE FOR G41M USERS (32 bit, 64 bit): On the *linux* line, specify fb=false to +boot in text mode or the installer won't have a display on your monitor. + ## Booting ISOLINUX Images (Automatic Method) Boot it in GRUB using the `Parse ISOLINUX config (USB)` option. A new menu should appear in GRUB, showing the boot options for that distro; this is a GRUB menu, converted from the usual ISOLINUX menu provided by that distro. diff --git a/docs/gnulinux/grub_cbfs.md b/docs/gnulinux/grub_cbfs.md index 2e68cb0b..fc46180c 100644 --- a/docs/gnulinux/grub_cbfs.md +++ b/docs/gnulinux/grub_cbfs.md @@ -262,7 +262,7 @@ Then, add the new one to the ROM: $ ./cbfstool libreboot.rom add -n grubtest.cfg -f grubtest.cfg -t raw -#### Change MAC address in ROM +#### Change MAC address in ROM {#changeMAC} The last step before flashing the new ROM, is to change the MAC address inside it. Every libreboot ROM image contains a generic MAC address; you want to make sure that your ROM image contains yours, so as to not create any problems on your network diff --git a/docs/hardware/index.md b/docs/hardware/index.md index 12580cf8..d939fad6 100644 --- a/docs/hardware/index.md +++ b/docs/hardware/index.md @@ -139,10 +139,11 @@ BIOS](https://en.wikipedia.org/wiki/Video_BIOS)' or 'VBIOS'). To find what LCD panel you have, see: [../misc/\#get\_edid\_panelname](../misc/#get_edid_panelname). -There are 5 known LCD panels for the X60 Tablet: +There are 6 known LCD panels for the X60 Tablet: - *X60T XGA (1024x768):* - BOE-Hydis HV121X03-100 (works) + - Toshiba Matsushita LTD121KC9B (works) - Samsung LTN121XP01 (does not work. blank screen) - BOE-Hydis HT12X21-351 (does not work. blank screen) - *X60T SXGA+ (1400x1050):* diff --git a/docs/hardware/kcma-d8.md b/docs/hardware/kcma-d8.md index f6c6fad7..fb7e6eed 100644 --- a/docs/hardware/kcma-d8.md +++ b/docs/hardware/kcma-d8.md @@ -32,9 +32,9 @@ See <https://raptorengineeringinc.com/coreboot/kcma-d8-status.php>. Form factor {#formfactor} =========== -These boards use the SSI EEB 3.61 form factor; make sure that your case -supports this. This form factor is similar to E-ATX in that the size is -identical, but the position of the screws are different. +This board is ATX form factor. While the [ATX standard, version 2.2](https://web.archive.org/web/20120725150314/http://www.formfactors.org/developer/specs/atx2_2.pdf) +specifies board dimensions 305mm x 244mm, this board measures 305mm x 253mm; +ensure your case supports this extra ~centimeter in width. IPMI iKVM module add-on {#ipmi} ======================= diff --git a/docs/hardware/mac_address.md b/docs/hardware/mac_address.md new file mode 100644 index 00000000..0a0d3621 --- /dev/null +++ b/docs/hardware/mac_address.md @@ -0,0 +1,107 @@ +--- +title: Changing the MAC address +... + +Introduction (GM45+e1000) +========================= + +This section is applicable to all Libreboot-supported laptops with the +mobile 4 series chipset (as shown in `$ lspci`) +that use the e1000 ethernet controller (e.g. T400, X200). +The R500 is an exception to this as it does not use the built-in e1000. + +On all these laptops, the +[MAC address](https://en.wikipedia.org/wiki/MAC_address) +for the built-in gigabit ethernet controller is stored inside the flash chip, +along with Libreboot and other configuration data. Therefore, installing +Libreboot will overwrite it. + +Thus, for these laptops, prebuilt Libreboot already contains a generic +MAC address in the configuration section. This address is `00:f5:f0:40:71:fe` +in builds before 2018-01-16 and `00:4c:69:62:72:65` (see the ascii character +set) afterwards. +Unless you change it, your computer will boot and use it. This can lead +to network problems if you have more than one Libreboot computer on +the same layer2 network (e.g. on the same network switch). The switch +(postman) will simply not know who to deliver to as the MAC (house) addresses +will be the same. + +To prevent these address clashes, you can either modify prebuilt Libreboot +to use an address of your own choosing or you can change the address in your +operating system's boot scripts. + +In either case, it is a good idea to write down the address that your +computer originally had. + +Obtaining the existing MAC address +================================== + +The existing MAC address may be obtained by the following methods: + +1. Run `ip link` or `ifconfig` in a terminal/console/shell; + find your ethernet device (e.g., **enpXXX** or **ethXXX**), + and look for a set of 12 colon-delimited + [hexadecimal digits](https://en.wikipedia.org/wiki/Hexadecimal). + For example: `00:f3:f0:45:91:fe`. + + * `$ ip link` + + `... link/ether ??:??:??:??:??:?? brd ...` + + * Alternatively: + + `$ ifconfig` + + `... ether ??:??:??:??:??:?? txqueuelen ...` + + +2. Otherwise you can read the white label that is often found on the + motherboard under the memory sticks: +  + +3. The MAC address is usually listed on the laptop chassis as well. This one + will be incorrect if the motherboard was changed and the stickers were not + updated. + +Changing the MAC address in the operating system +================================================ + +There are three portable ways of doing so: + +1. Using the new iproute2 package: + + `# ip link set <interface> down` + + `# ip link set dev <interface> address 00:4c:69:62:72:65` + + `# ip link set <interface> up` + + +2. Using the old `ifconfig` command: + + `# ifconfig <interface> hw ether 00:4c:69:62:72:65` + + +3. Using the macchanger package. + +You can use use of these three methods in your operating system's +init scripts or you can use your operating system's own networking +configuration. Refer to your operating system's documentation for +how to do this. + +Changing the MAC address in Libreboot +===================================== + +See [here](../gnulinux/grub_cbfs.md#changeMAC). + + + +Copyright © 2017 Fedja Beader <fedja@protonmail.ch> + +Copyright © 2014, 2015 Leah Rowe <info@minifree.org> + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) diff --git a/docs/index.md b/docs/index.md index 64bad0fe..afbd5e23 100644 --- a/docs/index.md +++ b/docs/index.md @@ -32,6 +32,7 @@ Other information ================= - [Miscellaneous](misc/) +- [List of codenames](misc/codenames.md) About the libreboot project =========================== @@ -74,8 +75,8 @@ The libreboot project has three main goals: and support. Most people will simply give up before attempting to install coreboot. -Libreboot attempts to bridge this divide, making sure that everything from -building to installing coreboot is automated, as much as is feasibly possible. +Libreboot attempts to bridge this divide by providing a build system +automating much of the coreboot image creation and customization. Secondly, the project produces documentation aimed at non-technical users. Thirdly, the project attempts to provide excellent user support via mailing lists and IRC. @@ -86,9 +87,9 @@ the complicated steps that are otherwise required, are instead done for the user in advance. You can download ROM images for your libreboot system and install -them, without having to build anything from source. The build system -is also fully automated, so building from source is easy if you -wanted to do that (for whatever reason). +them without having to build anything from source. If, however, you are +interested in building your own image, the build system makes it relatively +easy to do so. Libreboot is a coreboot distribution, not a coreboot fork --------------------------------------------------------- diff --git a/docs/install/r400_external.md b/docs/install/r400_external.md index 4036c761..8f9dd1ff 100644 --- a/docs/install/r400_external.md +++ b/docs/install/r400_external.md @@ -69,15 +69,7 @@ Use this to find out: MAC address {#macaddress} =========== -On the R400, the MAC address for the onboard gigabit ethernet chipset is -stored inside the flash chip, along with other configuration data. - -Keep a note of the MAC address before disassembly; this is very -important, because you will need to insert this into the libreboot ROM -image before flashing it. It will be written in one of these locations: - -  - +Refer to [mac\_address.md](../hardware/mac_address.md). Initial BBB configuration ========================= diff --git a/docs/install/t400_external.md b/docs/install/t400_external.md index 672ea46e..68bfb4ac 100644 --- a/docs/install/t400_external.md +++ b/docs/install/t400_external.md @@ -70,15 +70,7 @@ Use this to find out: MAC address {#macaddress} =========== -On the T400, the MAC address for the onboard gigabit ethernet chipset is -stored inside the flash chip, along with other configuration data. - -Keep a note of the MAC address before disassembly; this is very -important, because you will need to insert this into the libreboot ROM -image before flashing it. It will be written in one of these locations: - -  - +Refer to [mac\_address.md](../hardware/mac_address.md). Initial BBB configuration ========================= @@ -232,20 +224,14 @@ In this case, the output was: Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)", "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E" Please specify which chip definition to use with the -c <chipname> option. -How to backup factory.rom (change the -c option as neeed, for your flash +How to backup factory.rom (change the -c option as needed, for your flash chip): - # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r - -factory.rom + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory.rom - # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory1.rom -factory1.rom - - # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r - -factory2.rom + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -r factory2.rom Note: the `-c` option is not required in libreboot's patched flashrom, because the redundant flash chip definitions in `flashchips.c` have been removed. @@ -269,9 +255,7 @@ address to one that is correct for your system.* Now flash it: - # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w - -path/to/libreboot/rom/image.rom -V + # ./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -w path/to/libreboot/rom/image.rom -V  diff --git a/docs/install/t500_external.md b/docs/install/t500_external.md index 9e114bca..2a29d8ed 100644 --- a/docs/install/t500_external.md +++ b/docs/install/t500_external.md @@ -73,15 +73,7 @@ Use this to find out: MAC address {#macaddress} =========== -On the T500, the MAC address for the onboard gigabit ethernet chipset is -stored inside the flash chip, along with other configuration data. - -Keep a note of the MAC address before disassembly; this is very -important, because you will need to insert this into the libreboot ROM -image before flashing it. It will be written in one of these locations: - -  - +Refer to [mac\_address.md](../hardware/mac_address.md). Initial BBB configuration ========================= diff --git a/docs/install/x200_external.md b/docs/install/x200_external.md index 83a5c23f..c7330ce9 100644 --- a/docs/install/x200_external.md +++ b/docs/install/x200_external.md @@ -28,16 +28,7 @@ supported; see the [hardware](../hardware/x200.html#x200s) page. MAC address =========== -On the X200/X200S/X200T, the MAC address for the onboard gigabit -ethernet chipset is stored inside the flash chip, along with other -configuration data. - -Keep a note of the MAC address before disassembly; this is very -important, because you will need to insert this into the libreboot ROM -image before flashing it. It will be written in one of these locations: - - - +Refer to [mac\_address.md](../hardware/mac_address.md). Initial BBB configuration ========================= diff --git a/docs/misc/codenames.md b/docs/misc/codenames.md new file mode 100644 index 00000000..adaae6be --- /dev/null +++ b/docs/misc/codenames.md @@ -0,0 +1,115 @@ +--- +title: Product Codenames +... + +Introduction +============ + +This document lists product codenames for some hardware. +Please note that just because a certain device is listed here does NOT mean +that it is supported in Libreboot. For supported devices refer to the +installation documentation. + +### A note on GPUs + +Some laptops come with and without a discrete GPU (dGPU). Whether the +motherboard includes one or not can be determined by (in descending order +of reliability): + +- often thorough disassembly and searching for the actual chip +- looking at white PCB markings near RAM slots / under keyboard + and comparing with some known codenames (if not available FRU ID sticker) + listed below. +- sometimes by looking at heatsink grills: on + discrete GPU laptops these will look orange and on intergrated ones + they will appear silver. + +List of models and codenames +============================ + +### Codenames + +- Asus Chromebook C201PA: speedy\_rk3288, veyron-speedy + +- ThinkPad X60: KS Note +- ThinkPad X60s (slim): KS Note-2 / KS-2 +- ThinkPad X60 Tablet: Dali (Same PCB as KS Note-2, different EC firmware) + +- ThinkPad X200: Mocha-1 +- ThinkPad X200s (slim): Pecan-1 +- ThinkPad X200 Tablet: Caramel-1 + +- ThinkPad R400/T400: Malibu-3 + - with discrete GPU (dGPU), at board revision 0: "MLB3D-0 + - with only integrated GPU (iGPU), at board revision 0: "MLB3I-0" + +- ThinkPad T500/W500: Coronado-5 + - with dGPU (radeon): "COR5D-0" (last number is the board revision) + - with only iGPU: "COR5I-0" + +- ThinkPad T400s (slim): Shinai-MV +- ThinkPad R500: Waikiki-3 + +- R6x/T6x (whole family): Davinci. They don't have codename label in +silkscreen so you need to use FRU label of the board, which is placed +under RAM sticks. +- R60/T60: + - with dGPU (radeon): Magi-0 (last number is the board revision) + - with iGPU: Lisa-0 + +- With ThinkPads on Intel platforms newer than Montevina (Except T410), + the codenames become more consistent. All boards have the following + appended based on the type of graphics they have: + - with dGPU: SWG (SWitchable Graphics) + - with only iGPU: UMA (Unified Memory Access) + +*Note that Intel platforms newer than Montevina are not supported by libreboot +yet!. Currently only Calistoga and Montevina (only when using DDR3) +are the supported platforms.* + +- These are the known model codenames: + - ThinkPad T410: NOZOMI-1 # EXT/INT + - ThinkPad T410s: SHINAI-2 # SWG/UMA + - ThinkPad T420: NOZOMI-3 # SWG/UMA + - ThinkPad T420s: SHINAI-3 # SWG/UMA + - ThinkPad T430: NOZOMI-4 # SWG/UMA + - ThinkPad T430s: SHINAI-4 # SWG/UMA + - ThinkPad T520: KENDO-1 + - ThinkPad W520: KENDO-1 WS + - ThinkPad T520: KENDO-3 + - ThinkPad W520: KENDO-3 WS + - ThinkPad T530: KENDO-4 + - ThinkPad W530: KENDO-4 WS + + +### Miscellaneous +- [Calistoga](https://ark.intel.com/products/codename/5950/Calistoga): +945GM/945PM chipset family name +- Napa: calistoga based platform +- [Cantiga](https://ark.intel.com/products/codename/26552/Cantiga): +GM45/GS45/PM45 chipset family name. + This is the chipset used in T400,X200 and similar. +- Montevina: cantiga based platform. +- PMH: the Power Management Hub is a gate array for managing the power + up/down sequence. It is additionally tasked with extending EC's I/O. + Its later version was called "Thinker-1", and eventually it was merged + with PMIC (Rinkan) as ThinkEngine (Do not confuse it with EC chip which is also + has ThinkEngine logo on ThinkPad boards) +- Kozak, Tsurumai, Rinkan: These are successive versions of power management + ICs for Notebook PCs. Tsurumai chip marking is "TB62501F" and datasheet + of it fully describes its operation. + +See also +======== +- Many more Intel codenames can be found at + [Wikipedia](https://en.wikipedia.org/wiki/List_of_Intel_codenames). +- For ThinkPads see [Documentation/thinkpad/codenames.csv @ Coreboot] +(https://review.coreboot.org/cgit/coreboot.git/tree/Documentation/thinkpad/codenames.csv) + +Copyright © 2018 Fedja Beader <fedja@protonmail.ch> + +Permission is granted to copy, distribute and/or modify this document +under the terms of the GNU Free Documentation License Version 1.3 or any later +version published by the Free Software Foundation +with no Invariant Sections, no Front Cover Texts, and no Back Cover Texts. +A copy of this license is found in [../fdl-1.3.md](../fdl-1.3.md) @@ -63,7 +63,7 @@ libreboot_usage() { printf 1>&2 '%s\n' ' TOOLS_FORCE - Tools to always perform actions for' printf 1>&2 '%s\n' ' RELEASE_KEY - GPG key to use for release' printf 1>&2 '%s\n' ' VBOOT_KEYS_PATH - Path to the vboot keys' - printf 1>&2 '%s\n' ' LIBFAKETIME_PATH - Path to the libfaketime shared library' + printf 1>&2 '%s\n' ' LIBFAKETIME_PATH - Path to libfaketime' printf 1>&2 '%s\n' ' TASKS - Number of simultaneous tasks to run' printf 1>&2 '%s\n' ' VERSION - Version string to use' @@ -133,7 +133,7 @@ libreboot_setup() { libreboot_setup_tool_actions libreboot_setup_project_actions - requirements 'tar' 'sed' 'gpg' 'sha256sum' 'git' + requirements tar sed gpg sha256sum git mmd mcopy grep mkfs.fat libreboot_setup_variables } @@ -220,6 +220,8 @@ libreboot_setup_reproducible_builds_variables() { else RANDOM_SEED="$RANDOM" # True randomness is unnecessary fi + + export RANDOM_SEED fi # Also used by GCC, but as an environment variable @@ -231,9 +233,11 @@ libreboot_setup_reproducible_builds_variables() { else SOURCE_DATE_EPOCH="$(date +%s)" fi + + export SOURCE_DATE_EPOCH fi - # Relevant only when libfaketime is preloaded + # Relevant only when libfaketime path is given in $BUILD_SYSTEM.conf if [[ -n "$LIBFAKETIME_PATH" ]]; then BUILD_DATE_FMT="%Y-%m-%d %H:%M:%S" BUILD_DATE="$(date -u -d "@$SOURCE_DATE_EPOCH" "+$BUILD_DATE_FMT" 2>/dev/null || date -u -r "$SOURCE_DATE_EPOCH" "+$BUILD_DATE_FMT" 2>/dev/null || date -u "+$BUILD_DATE_FMT")" @@ -241,6 +245,8 @@ libreboot_setup_reproducible_builds_variables() { LC_ALL='C.UTF-8' LD_PRELOAD="$LIBFAKETIME_PATH" TZ='UTC' + + export BUILD_DATE_FMT BUILD_DATE FAKETIME LC_ALL LD_PRELOAD TZ fi } diff --git a/projects/coreboot/configs/d510mo/config b/projects/coreboot/configs/d510mo/config index cf8d27f6..1e1c2630 100644 --- a/projects/coreboot/configs/d510mo/config +++ b/projects/coreboot/configs/d510mo/config @@ -594,7 +594,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y diff --git a/projects/coreboot/configs/d510mo/textmode/16mb/seabios/config b/projects/coreboot/configs/d510mo/textmode/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/d510mo/textmode/16mb/seabios/config +++ b/projects/coreboot/configs/d510mo/textmode/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/d510mo/textmode/1mb/seabios/config b/projects/coreboot/configs/d510mo/textmode/1mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/d510mo/textmode/1mb/seabios/config +++ b/projects/coreboot/configs/d510mo/textmode/1mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/d945gclf/config b/projects/coreboot/configs/d945gclf/config index 1f2d39b7..50e647c6 100644 --- a/projects/coreboot/configs/d945gclf/config +++ b/projects/coreboot/configs/d945gclf/config @@ -622,7 +622,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y diff --git a/projects/coreboot/configs/d945gclf/textmode/16mb/seabios/config b/projects/coreboot/configs/d945gclf/textmode/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/d945gclf/textmode/16mb/seabios/config +++ b/projects/coreboot/configs/d945gclf/textmode/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/d945gclf/textmode/512kb/seabios/config b/projects/coreboot/configs/d945gclf/textmode/512kb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/d945gclf/textmode/512kb/seabios/config +++ b/projects/coreboot/configs/d945gclf/textmode/512kb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/ga-g41m-es2l/config b/projects/coreboot/configs/ga-g41m-es2l/config index 237f6daa..755afcd5 100644 --- a/projects/coreboot/configs/ga-g41m-es2l/config +++ b/projects/coreboot/configs/ga-g41m-es2l/config @@ -581,7 +581,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y diff --git a/projects/coreboot/configs/ga-g41m-es2l/corebootfb/16mb/seabios/config b/projects/coreboot/configs/ga-g41m-es2l/corebootfb/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/ga-g41m-es2l/corebootfb/16mb/seabios/config +++ b/projects/coreboot/configs/ga-g41m-es2l/corebootfb/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/ga-g41m-es2l/corebootfb/1mb/seabios/config b/projects/coreboot/configs/ga-g41m-es2l/corebootfb/1mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/ga-g41m-es2l/corebootfb/1mb/seabios/config +++ b/projects/coreboot/configs/ga-g41m-es2l/corebootfb/1mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/ga-g41m-es2l/textmode/16mb/seabios/config b/projects/coreboot/configs/ga-g41m-es2l/textmode/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/ga-g41m-es2l/textmode/16mb/seabios/config +++ b/projects/coreboot/configs/ga-g41m-es2l/textmode/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/ga-g41m-es2l/textmode/1mb/seabios/config b/projects/coreboot/configs/ga-g41m-es2l/textmode/1mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/ga-g41m-es2l/textmode/1mb/seabios/config +++ b/projects/coreboot/configs/ga-g41m-es2l/textmode/1mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/imac52 b/projects/coreboot/configs/imac52 new file mode 120000 index 00000000..a5b8c293 --- /dev/null +++ b/projects/coreboot/configs/imac52 @@ -0,0 +1 @@ +macbook21
\ No newline at end of file diff --git a/projects/coreboot/configs/kcma-d8/config b/projects/coreboot/configs/kcma-d8/config index 8b78ab25..b46824cb 100644 --- a/projects/coreboot/configs/kcma-d8/config +++ b/projects/coreboot/configs/kcma-d8/config @@ -627,7 +627,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y diff --git a/projects/coreboot/configs/kcma-d8/textmode/16mb/seabios/config b/projects/coreboot/configs/kcma-d8/textmode/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/kcma-d8/textmode/16mb/seabios/config +++ b/projects/coreboot/configs/kcma-d8/textmode/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/kcma-d8/textmode/2mb/seabios/config b/projects/coreboot/configs/kcma-d8/textmode/2mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/kcma-d8/textmode/2mb/seabios/config +++ b/projects/coreboot/configs/kcma-d8/textmode/2mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/kfsn4-dre/config b/projects/coreboot/configs/kfsn4-dre/config index e4435801..3ade5731 100644 --- a/projects/coreboot/configs/kfsn4-dre/config +++ b/projects/coreboot/configs/kfsn4-dre/config @@ -646,7 +646,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y diff --git a/projects/coreboot/configs/kfsn4-dre/corebootfb/1mb/seabios/config b/projects/coreboot/configs/kfsn4-dre/corebootfb/1mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/kfsn4-dre/corebootfb/1mb/seabios/config +++ b/projects/coreboot/configs/kfsn4-dre/corebootfb/1mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/kfsn4-dre/corebootfb/2mb/seabios/config b/projects/coreboot/configs/kfsn4-dre/corebootfb/2mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/kfsn4-dre/corebootfb/2mb/seabios/config +++ b/projects/coreboot/configs/kfsn4-dre/corebootfb/2mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/kfsn4-dre/textmode/1mb/seabios/config b/projects/coreboot/configs/kfsn4-dre/textmode/1mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/kfsn4-dre/textmode/1mb/seabios/config +++ b/projects/coreboot/configs/kfsn4-dre/textmode/1mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/kfsn4-dre/textmode/2mb/seabios/config b/projects/coreboot/configs/kfsn4-dre/textmode/2mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/kfsn4-dre/textmode/2mb/seabios/config +++ b/projects/coreboot/configs/kfsn4-dre/textmode/2mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/kgpe-d16/config b/projects/coreboot/configs/kgpe-d16/config index 7a2eca9c..ff31b4a0 100644 --- a/projects/coreboot/configs/kgpe-d16/config +++ b/projects/coreboot/configs/kgpe-d16/config @@ -629,7 +629,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y diff --git a/projects/coreboot/configs/kgpe-d16/textmode/16mb/seabios/config b/projects/coreboot/configs/kgpe-d16/textmode/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/kgpe-d16/textmode/16mb/seabios/config +++ b/projects/coreboot/configs/kgpe-d16/textmode/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/kgpe-d16/textmode/2mb/seabios/config b/projects/coreboot/configs/kgpe-d16/textmode/2mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/kgpe-d16/textmode/2mb/seabios/config +++ b/projects/coreboot/configs/kgpe-d16/textmode/2mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/macbook21/config b/projects/coreboot/configs/macbook21/config index 2fcf83ea..9726814a 100644 --- a/projects/coreboot/configs/macbook21/config +++ b/projects/coreboot/configs/macbook21/config @@ -574,7 +574,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y diff --git a/projects/coreboot/configs/macbook21/corebootfb/16mb/seabios/config b/projects/coreboot/configs/macbook21/corebootfb/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/macbook21/corebootfb/16mb/seabios/config +++ b/projects/coreboot/configs/macbook21/corebootfb/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/macbook21/corebootfb/2mb/seabios/config b/projects/coreboot/configs/macbook21/corebootfb/2mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/macbook21/corebootfb/2mb/seabios/config +++ b/projects/coreboot/configs/macbook21/corebootfb/2mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/macbook21/textmode/16mb/seabios/config b/projects/coreboot/configs/macbook21/textmode/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/macbook21/textmode/16mb/seabios/config +++ b/projects/coreboot/configs/macbook21/textmode/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/macbook21/textmode/2mb/seabios/config b/projects/coreboot/configs/macbook21/textmode/2mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/macbook21/textmode/2mb/seabios/config +++ b/projects/coreboot/configs/macbook21/textmode/2mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/macbook21/variants/imac52 b/projects/coreboot/configs/macbook21/variants/imac52 new file mode 100644 index 00000000..91464e6e --- /dev/null +++ b/projects/coreboot/configs/macbook21/variants/imac52 @@ -0,0 +1,4 @@ +CONFIG_MAINBOARD_PART_NUMBER="iMac5,2" +CONFIG_BOARD_APPLE_MACBOOK21=n +CONFIG_BOARD_APPLE_IMAC52=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="iMac5,2" diff --git a/projects/coreboot/configs/macbook21/variants/macbook21 b/projects/coreboot/configs/macbook21/variants/macbook21 new file mode 100644 index 00000000..a83cd1f3 --- /dev/null +++ b/projects/coreboot/configs/macbook21/variants/macbook21 @@ -0,0 +1,3 @@ +CONFIG_MAINBOARD_PART_NUMBER="MacBook2,1" +CONFIG_BOARD_APPLE_MACBOOK21=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1" diff --git a/projects/coreboot/configs/nyan/big/corebootfb/16mb/config b/projects/coreboot/configs/nyan/big/corebootfb/16mb/config new file mode 100644 index 00000000..d3e3b7aa --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/16mb/config @@ -0,0 +1,5 @@ +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=n +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 diff --git a/projects/coreboot/configs/nyan/big/corebootfb/16mb/depthcharge/config b/projects/coreboot/configs/nyan/big/corebootfb/16mb/depthcharge/config new file mode 100644 index 00000000..4fb44ffa --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/16mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-nyan-big/depthcharge.elf" diff --git a/projects/coreboot/configs/nyan/big/corebootfb/16mb/targets b/projects/coreboot/configs/nyan/big/corebootfb/16mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/16mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/nyan/big/corebootfb/4mb/config b/projects/coreboot/configs/nyan/big/corebootfb/4mb/config new file mode 100644 index 00000000..f8445518 --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/4mb/config @@ -0,0 +1,4 @@ +CONFIG_CBFS_SIZE=0x400000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 diff --git a/projects/coreboot/configs/nyan/big/corebootfb/4mb/depthcharge/config b/projects/coreboot/configs/nyan/big/corebootfb/4mb/depthcharge/config new file mode 100644 index 00000000..4fb44ffa --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/4mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-nyan-big/depthcharge.elf" diff --git a/projects/coreboot/configs/nyan/big/corebootfb/4mb/targets b/projects/coreboot/configs/nyan/big/corebootfb/4mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/4mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/nyan/big/corebootfb/targets b/projects/coreboot/configs/nyan/big/corebootfb/targets new file mode 100644 index 00000000..0169dcf0 --- /dev/null +++ b/projects/coreboot/configs/nyan/big/corebootfb/targets @@ -0,0 +1,2 @@ +16mb +4mb diff --git a/projects/coreboot/configs/nyan/big/targets b/projects/coreboot/configs/nyan/big/targets new file mode 100644 index 00000000..ffc50041 --- /dev/null +++ b/projects/coreboot/configs/nyan/big/targets @@ -0,0 +1 @@ +corebootfb diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/config b/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/config new file mode 100644 index 00000000..d3e3b7aa --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/config @@ -0,0 +1,5 @@ +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=n +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/depthcharge/config b/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/depthcharge/config new file mode 100644 index 00000000..1a6c06bc --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-nyan-blaze/depthcharge.elf" diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/targets b/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/16mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/config b/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/config new file mode 100644 index 00000000..f8445518 --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/config @@ -0,0 +1,4 @@ +CONFIG_CBFS_SIZE=0x400000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/depthcharge/config b/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/depthcharge/config new file mode 100644 index 00000000..1a6c06bc --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-nyan-blaze/depthcharge.elf" diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/targets b/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/4mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/nyan/blaze/corebootfb/targets b/projects/coreboot/configs/nyan/blaze/corebootfb/targets new file mode 100644 index 00000000..0169dcf0 --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/corebootfb/targets @@ -0,0 +1,2 @@ +16mb +4mb diff --git a/projects/coreboot/configs/nyan/blaze/targets b/projects/coreboot/configs/nyan/blaze/targets new file mode 100644 index 00000000..ffc50041 --- /dev/null +++ b/projects/coreboot/configs/nyan/blaze/targets @@ -0,0 +1 @@ +corebootfb diff --git a/projects/coreboot/configs/qemu_i440fx_piix4/config b/projects/coreboot/configs/qemu_i440fx_piix4/config index a6110151..68d9efe7 100644 --- a/projects/coreboot/configs/qemu_i440fx_piix4/config +++ b/projects/coreboot/configs/qemu_i440fx_piix4/config @@ -530,7 +530,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y diff --git a/projects/coreboot/configs/qemu_q35_ich9/config b/projects/coreboot/configs/qemu_q35_ich9/config index 7c3a47cf..f7f05e75 100644 --- a/projects/coreboot/configs/qemu_q35_ich9/config +++ b/projects/coreboot/configs/qemu_q35_ich9/config @@ -530,7 +530,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y diff --git a/projects/coreboot/configs/revision b/projects/coreboot/configs/revision index 24940261..30357a1c 100644 --- a/projects/coreboot/configs/revision +++ b/projects/coreboot/configs/revision @@ -1 +1 @@ -a17796e6012041e2d8ebe16b0bde0b99809ee87c +8f560d9b9c20c7e72b031e60cf0e828d7d27ec8e diff --git a/projects/coreboot/configs/t400/config b/projects/coreboot/configs/t400/config index 045c9d37..f6f7b95b 100644 --- a/projects/coreboot/configs/t400/config +++ b/projects/coreboot/configs/t400/config @@ -584,7 +584,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y diff --git a/projects/coreboot/configs/t400/corebootfb/16mb/seabios/config b/projects/coreboot/configs/t400/corebootfb/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/t400/corebootfb/16mb/seabios/config +++ b/projects/coreboot/configs/t400/corebootfb/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/t400/corebootfb/4mb/seabios/config b/projects/coreboot/configs/t400/corebootfb/4mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/t400/corebootfb/4mb/seabios/config +++ b/projects/coreboot/configs/t400/corebootfb/4mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/t400/corebootfb/8mb/seabios/config b/projects/coreboot/configs/t400/corebootfb/8mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/t400/corebootfb/8mb/seabios/config +++ b/projects/coreboot/configs/t400/corebootfb/8mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/t400/textmode/16mb/seabios/config b/projects/coreboot/configs/t400/textmode/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/t400/textmode/16mb/seabios/config +++ b/projects/coreboot/configs/t400/textmode/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/t400/textmode/4mb/seabios/config b/projects/coreboot/configs/t400/textmode/4mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/t400/textmode/4mb/seabios/config +++ b/projects/coreboot/configs/t400/textmode/4mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/t400/textmode/8mb/seabios/config b/projects/coreboot/configs/t400/textmode/8mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/t400/textmode/8mb/seabios/config +++ b/projects/coreboot/configs/t400/textmode/8mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/t60/config b/projects/coreboot/configs/t60/config index 04512207..e4910cea 100644 --- a/projects/coreboot/configs/t60/config +++ b/projects/coreboot/configs/t60/config @@ -598,7 +598,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y diff --git a/projects/coreboot/configs/t60/corebootfb/16mb/seabios/config b/projects/coreboot/configs/t60/corebootfb/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/t60/corebootfb/16mb/seabios/config +++ b/projects/coreboot/configs/t60/corebootfb/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/t60/corebootfb/2mb/seabios/config b/projects/coreboot/configs/t60/corebootfb/2mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/t60/corebootfb/2mb/seabios/config +++ b/projects/coreboot/configs/t60/corebootfb/2mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/t60/textmode/16mb/seabios/config b/projects/coreboot/configs/t60/textmode/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/t60/textmode/16mb/seabios/config +++ b/projects/coreboot/configs/t60/textmode/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/t60/textmode/2mb/seabios/config b/projects/coreboot/configs/t60/textmode/2mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/t60/textmode/2mb/seabios/config +++ b/projects/coreboot/configs/t60/textmode/2mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/targets b/projects/coreboot/configs/targets index c6aa3b64..8bc162d5 100644 --- a/projects/coreboot/configs/targets +++ b/projects/coreboot/configs/targets @@ -1,6 +1,7 @@ d510mo d945gclf ga-g41m-es2l +imac52 kcma-d8 kfsn4-dre kgpe-d16 @@ -16,3 +17,4 @@ veyron w500 x200 x60 +z61t diff --git a/projects/coreboot/configs/veyron/jerry/config b/projects/coreboot/configs/veyron/jerry/config index 9393e7de..30c978cf 100644 --- a/projects/coreboot/configs/veyron/jerry/config +++ b/projects/coreboot/configs/veyron/jerry/config @@ -110,7 +110,7 @@ CONFIG_MAINBOARD_PART_NUMBER="Veyron_Jerry" CONFIG_MAINBOARD_VENDOR="Google" CONFIG_MAX_CPUS=1 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 -CONFIG_CBFS_SIZE=0x100000 +CONFIG_CBFS_SIZE=0x400000 CONFIG_UART_FOR_CONSOLE=0 CONFIG_DIMM_SPD_SIZE=256 CONFIG_DEVICETREE="devicetree.cb" diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/config b/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/config new file mode 100644 index 00000000..d3e3b7aa --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/config @@ -0,0 +1,5 @@ +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=n +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/depthcharge/config b/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/depthcharge/config new file mode 100644 index 00000000..afde4a80 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-jerry/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/targets b/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/16mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/config b/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/config new file mode 100644 index 00000000..f8445518 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/config @@ -0,0 +1,4 @@ +CONFIG_CBFS_SIZE=0x400000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/depthcharge/config b/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/depthcharge/config new file mode 100644 index 00000000..afde4a80 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-jerry/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/targets b/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/4mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/jerry/corebootfb/targets b/projects/coreboot/configs/veyron/jerry/corebootfb/targets new file mode 100644 index 00000000..0169dcf0 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/corebootfb/targets @@ -0,0 +1,2 @@ +16mb +4mb diff --git a/projects/coreboot/configs/veyron/jerry/targets b/projects/coreboot/configs/veyron/jerry/targets new file mode 100644 index 00000000..ffc50041 --- /dev/null +++ b/projects/coreboot/configs/veyron/jerry/targets @@ -0,0 +1 @@ +corebootfb diff --git a/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/config b/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/config new file mode 100644 index 00000000..f8445518 --- /dev/null +++ b/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/config @@ -0,0 +1,4 @@ +CONFIG_CBFS_SIZE=0x400000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 diff --git a/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/depthcharge/config b/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/depthcharge/config new file mode 100644 index 00000000..e27c1a5b --- /dev/null +++ b/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-mickey/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/targets b/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/mickey/corebootfb/4mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/mickey/corebootfb/targets b/projects/coreboot/configs/veyron/mickey/corebootfb/targets new file mode 100644 index 00000000..50d4bf27 --- /dev/null +++ b/projects/coreboot/configs/veyron/mickey/corebootfb/targets @@ -0,0 +1 @@ +4mb diff --git a/projects/coreboot/configs/veyron/mickey/targets b/projects/coreboot/configs/veyron/mickey/targets new file mode 100644 index 00000000..ffc50041 --- /dev/null +++ b/projects/coreboot/configs/veyron/mickey/targets @@ -0,0 +1 @@ +corebootfb diff --git a/projects/coreboot/configs/veyron/minnie/config b/projects/coreboot/configs/veyron/minnie/config index 45672bc9..d9d9206e 100644 --- a/projects/coreboot/configs/veyron/minnie/config +++ b/projects/coreboot/configs/veyron/minnie/config @@ -110,7 +110,7 @@ CONFIG_MAINBOARD_PART_NUMBER="Veyron_Minnie" CONFIG_MAINBOARD_VENDOR="Google" CONFIG_MAX_CPUS=1 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 -CONFIG_CBFS_SIZE=0x100000 +CONFIG_CBFS_SIZE=0x400000 CONFIG_UART_FOR_CONSOLE=0 CONFIG_DIMM_SPD_SIZE=256 CONFIG_DEVICETREE="devicetree.cb" diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/config b/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/config new file mode 100644 index 00000000..d3e3b7aa --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/config @@ -0,0 +1,5 @@ +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=n +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/depthcharge/config b/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/depthcharge/config new file mode 100644 index 00000000..aee1ccef --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-minnie/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/targets b/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/16mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/config b/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/config new file mode 100644 index 00000000..f8445518 --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/config @@ -0,0 +1,4 @@ +CONFIG_CBFS_SIZE=0x400000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/depthcharge/config b/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/depthcharge/config new file mode 100644 index 00000000..aee1ccef --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-minnie/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/targets b/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/4mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/minnie/corebootfb/targets b/projects/coreboot/configs/veyron/minnie/corebootfb/targets new file mode 100644 index 00000000..0169dcf0 --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/corebootfb/targets @@ -0,0 +1,2 @@ +16mb +4mb diff --git a/projects/coreboot/configs/veyron/minnie/targets b/projects/coreboot/configs/veyron/minnie/targets new file mode 100644 index 00000000..ffc50041 --- /dev/null +++ b/projects/coreboot/configs/veyron/minnie/targets @@ -0,0 +1 @@ +corebootfb diff --git a/projects/coreboot/configs/veyron/speedy/config b/projects/coreboot/configs/veyron/speedy/config index b4a74b9a..27ddca6b 100644 --- a/projects/coreboot/configs/veyron/speedy/config +++ b/projects/coreboot/configs/veyron/speedy/config @@ -110,7 +110,7 @@ CONFIG_MAINBOARD_PART_NUMBER="Veyron_Speedy" CONFIG_MAINBOARD_VENDOR="Google" CONFIG_MAX_CPUS=1 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 -CONFIG_CBFS_SIZE=0x100000 +CONFIG_CBFS_SIZE=0x400000 CONFIG_UART_FOR_CONSOLE=0 CONFIG_DIMM_SPD_SIZE=256 CONFIG_DEVICETREE="devicetree.cb" diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/config b/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/config new file mode 100644 index 00000000..d3e3b7aa --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/config @@ -0,0 +1,5 @@ +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=n +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/depthcharge/config b/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/depthcharge/config new file mode 100644 index 00000000..8b705934 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-speedy/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/targets b/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/16mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/config b/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/config new file mode 100644 index 00000000..f8445518 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/config @@ -0,0 +1,4 @@ +CONFIG_CBFS_SIZE=0x400000 +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/depthcharge/config b/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/depthcharge/config new file mode 100644 index 00000000..8b705934 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/depthcharge/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-speedy/depthcharge.elf" diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/targets b/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/4mb/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/configs/veyron/speedy/corebootfb/targets b/projects/coreboot/configs/veyron/speedy/corebootfb/targets new file mode 100644 index 00000000..0169dcf0 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/corebootfb/targets @@ -0,0 +1,2 @@ +16mb +4mb diff --git a/projects/coreboot/configs/veyron/speedy/targets b/projects/coreboot/configs/veyron/speedy/targets new file mode 100644 index 00000000..ffc50041 --- /dev/null +++ b/projects/coreboot/configs/veyron/speedy/targets @@ -0,0 +1 @@ +corebootfb diff --git a/projects/coreboot/configs/x200/config b/projects/coreboot/configs/x200/config index 8e2be019..01efbc79 100644 --- a/projects/coreboot/configs/x200/config +++ b/projects/coreboot/configs/x200/config @@ -582,7 +582,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y diff --git a/projects/coreboot/configs/x200/corebootfb/16mb/seabios/config b/projects/coreboot/configs/x200/corebootfb/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/x200/corebootfb/16mb/seabios/config +++ b/projects/coreboot/configs/x200/corebootfb/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/x200/corebootfb/4mb/seabios/config b/projects/coreboot/configs/x200/corebootfb/4mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/x200/corebootfb/4mb/seabios/config +++ b/projects/coreboot/configs/x200/corebootfb/4mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/x200/corebootfb/8mb/seabios/config b/projects/coreboot/configs/x200/corebootfb/8mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/x200/corebootfb/8mb/seabios/config +++ b/projects/coreboot/configs/x200/corebootfb/8mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/x200/textmode/16mb/seabios/config b/projects/coreboot/configs/x200/textmode/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/x200/textmode/16mb/seabios/config +++ b/projects/coreboot/configs/x200/textmode/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/x200/textmode/4mb/seabios/config b/projects/coreboot/configs/x200/textmode/4mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/x200/textmode/4mb/seabios/config +++ b/projects/coreboot/configs/x200/textmode/4mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/x200/textmode/8mb/seabios/config b/projects/coreboot/configs/x200/textmode/8mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/x200/textmode/8mb/seabios/config +++ b/projects/coreboot/configs/x200/textmode/8mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/x60/config b/projects/coreboot/configs/x60/config index 8257be82..510854f5 100644 --- a/projects/coreboot/configs/x60/config +++ b/projects/coreboot/configs/x60/config @@ -603,7 +603,7 @@ CONFIG_PAYLOAD_ELF=y # CONFIG_PAYLOAD_UBOOT is not set # CONFIG_PAYLOAD_LINUX is not set # CONFIG_PAYLOAD_TIANOCORE is not set -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" CONFIG_PAYLOAD_OPTIONS="" # CONFIG_PXE is not set CONFIG_COMPRESSED_PAYLOAD_LZMA=y diff --git a/projects/coreboot/configs/x60/corebootfb/16mb/seabios/config b/projects/coreboot/configs/x60/corebootfb/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/x60/corebootfb/16mb/seabios/config +++ b/projects/coreboot/configs/x60/corebootfb/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/x60/corebootfb/2mb/seabios/config b/projects/coreboot/configs/x60/corebootfb/2mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/x60/corebootfb/2mb/seabios/config +++ b/projects/coreboot/configs/x60/corebootfb/2mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/x60/textmode/16mb/seabios/config b/projects/coreboot/configs/x60/textmode/16mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/x60/textmode/16mb/seabios/config +++ b/projects/coreboot/configs/x60/textmode/16mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/x60/textmode/2mb/seabios/config b/projects/coreboot/configs/x60/textmode/2mb/seabios/config index b1e08f99..a3c13aff 100644 --- a/projects/coreboot/configs/x60/textmode/2mb/seabios/config +++ b/projects/coreboot/configs/x60/textmode/2mb/seabios/config @@ -1 +1 @@ -CONFIG_PAYLOAD_FILE="$(obj)/../seabios-bios/bios.bin.elf" +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/z61t/arch b/projects/coreboot/configs/z61t/arch new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/projects/coreboot/configs/z61t/arch @@ -0,0 +1 @@ +i386 diff --git a/projects/coreboot/configs/z61t/config b/projects/coreboot/configs/z61t/config new file mode 100644 index 00000000..69a55442 --- /dev/null +++ b/projects/coreboot/configs/z61t/config @@ -0,0 +1,674 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_LOWRISC is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WINNET is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/z61t" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad Z61t" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 +CONFIG_CBFS_SIZE=0x200000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_VGA_BIOS_ID="8086,27a2" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +CONFIG_DIMM_SPD_SIZE=256 +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xfefc0000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_ID_SECTION_OFFSET=0x80 +# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set +# CONFIG_BOARD_EMULATION_QEMU_POWER8 is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_Q35 is not set +# CONFIG_BOARD_EMULATION_QEMU_UCB_RISCV is not set +# CONFIG_BOARD_EMULATION_SPIKE_UCB_RISCV is not set +CONFIG_POST_DEVICE=y +# CONFIG_VBOOT is not set +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_TTYS0_LCS=3 +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_L520 is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_S230U is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_THINKPAD_T430 is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X131E is not set +# CONFIG_BOARD_LENOVO_X1_CARBON_GEN1 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_Z61T=y +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_NO_POST is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_RAMBASE=0x100000 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +# CONFIG_SOC_BROADCOM_CYGNUS is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_STACK_SIZE=0x1000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_INTEL_KABYLAKE is not set +# CONFIG_SOC_LOWRISC_LOWRISC is not set +# CONFIG_SOC_MARVELL_MVMAP2315 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_INTEL_COMMON=y +CONFIG_ENABLE_VMX=y +CONFIG_SET_VMX_LOCK_BIT=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +# CONFIG_NO_CAR_GLOBAL_MIGRATION is not set +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_NO_MMCONF_SUPPORT is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +# CONFIG_I945_LVDS is not set +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_TI_PCI1X2X=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y +# CONFIG_SUPERIO_NUVOTON_NCT6776_COM_A is not set + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_BEEP_ON_DEATH=y +CONFIG_H8_FLASH_LEDS_ON_DEATH=y +# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set +CONFIG_H8_DOCK_EARLY_INIT=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +CONFIG_AP_IN_SIPI_WAIT=y +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_CBMEM_TOP_BACKUP is not set +# CONFIG_LATE_CBMEM_INIT is not set +# CONFIG_EARLY_EBDA_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +# CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_NO_GFX_INIT is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set + +# +# Display +# +CONFIG_VGA_TEXT_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_INTEL_GMA_ADD_VBT_DATA_FILE is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_SMM is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVERS_AMD_PI is not set +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +CONFIG_DRIVERS_I2C_CK505=y +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +CONFIG_VGA=y +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +# CONFIG_MAINBOARD_HAS_TPM_CR50 is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_COMMON_FADT=y +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" +# CONFIG_SEABIOS_STABLE is not set +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y diff --git a/projects/coreboot/configs/z61t/targets b/projects/coreboot/configs/z61t/targets new file mode 100644 index 00000000..3ee846a9 --- /dev/null +++ b/projects/coreboot/configs/z61t/targets @@ -0,0 +1 @@ +textmode diff --git a/projects/coreboot/configs/z61t/textmode/16mb/config b/projects/coreboot/configs/z61t/textmode/16mb/config new file mode 100644 index 00000000..a4cf5cf7 --- /dev/null +++ b/projects/coreboot/configs/z61t/textmode/16mb/config @@ -0,0 +1,5 @@ +CONFIG_CBFS_SIZE=0x1000000 +CONFIG_COREBOOT_ROMSIZE_KB_2048=n +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 diff --git a/projects/coreboot/configs/z61t/textmode/16mb/grub/config b/projects/coreboot/configs/z61t/textmode/16mb/grub/config new file mode 100644 index 00000000..5170a90a --- /dev/null +++ b/projects/coreboot/configs/z61t/textmode/16mb/grub/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../grub-coreboot/grub2" diff --git a/projects/coreboot/configs/z61t/textmode/16mb/seabios/config b/projects/coreboot/configs/z61t/textmode/16mb/seabios/config new file mode 100644 index 00000000..a3c13aff --- /dev/null +++ b/projects/coreboot/configs/z61t/textmode/16mb/seabios/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/z61t/textmode/16mb/targets b/projects/coreboot/configs/z61t/textmode/16mb/targets new file mode 100644 index 00000000..f2cba0e5 --- /dev/null +++ b/projects/coreboot/configs/z61t/textmode/16mb/targets @@ -0,0 +1,2 @@ +grub +seabios diff --git a/projects/coreboot/configs/z61t/textmode/2mb/config b/projects/coreboot/configs/z61t/textmode/2mb/config new file mode 100644 index 00000000..adffe7ae --- /dev/null +++ b/projects/coreboot/configs/z61t/textmode/2mb/config @@ -0,0 +1,4 @@ +CONFIG_CBFS_SIZE=0x200000 +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 diff --git a/projects/coreboot/configs/z61t/textmode/2mb/grub/config b/projects/coreboot/configs/z61t/textmode/2mb/grub/config new file mode 100644 index 00000000..5170a90a --- /dev/null +++ b/projects/coreboot/configs/z61t/textmode/2mb/grub/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../grub-coreboot/grub2" diff --git a/projects/coreboot/configs/z61t/textmode/2mb/seabios/config b/projects/coreboot/configs/z61t/textmode/2mb/seabios/config new file mode 100644 index 00000000..a3c13aff --- /dev/null +++ b/projects/coreboot/configs/z61t/textmode/2mb/seabios/config @@ -0,0 +1 @@ +CONFIG_PAYLOAD_FILE="$(obj)/../seabios/bios.bin.elf" diff --git a/projects/coreboot/configs/z61t/textmode/2mb/targets b/projects/coreboot/configs/z61t/textmode/2mb/targets new file mode 100644 index 00000000..f2cba0e5 --- /dev/null +++ b/projects/coreboot/configs/z61t/textmode/2mb/targets @@ -0,0 +1,2 @@ +grub +seabios diff --git a/projects/coreboot/configs/z61t/textmode/targets b/projects/coreboot/configs/z61t/textmode/targets new file mode 100644 index 00000000..b22e49ab --- /dev/null +++ b/projects/coreboot/configs/z61t/textmode/targets @@ -0,0 +1,2 @@ +16mb +2mb diff --git a/projects/coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch b/projects/coreboot/patches/0001-Don-t-pull-in-3rdparty-git-submodules.patch index 24964bb4..ddba7bc3 100644 --- a/projects/coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch +++ b/projects/coreboot/patches/0001-Don-t-pull-in-3rdparty-git-submodules.patch @@ -1,10 +1,10 @@ -From b403ddd709578d11f1e6d32abfc94701f57cae16 Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski <contact@paulk.fr> -Date: Thu, 25 Jan 2018 17:31:55 -0500 -Subject: [PATCH] Avoid using git submodules for 3rdparty +From 8b436fdcc99f111e17cd98da6d60a4d6977241e6 Mon Sep 17 00:00:00 2001 +From: Andrew Robbins <contact@andrewrobbins.info> +Date: Fri, 7 Dec 2018 21:59:21 -0500 +Subject: [PATCH] Don't pull in 3rdparty git submodules -This gets rid of git submodules entirely, to avoid the nuisance caused -by automatically checking them out. +Libreboot's build system uses separate git repositories for the +third-party software. --- .gitmodules | 20 -------------------- 3rdparty/arm-trusted-firmware | 1 - @@ -52,51 +52,51 @@ index c3270e6..3a617c7 100644 - url = ../libgfxinit.git diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware deleted file mode 160000 -index b118723..0000000 +index 693e278..0000000 --- a/3rdparty/arm-trusted-firmware +++ /dev/null @@ -1 +0,0 @@ --Subproject commit b1187232fdf819586ba8c8ece4a27a7515cbdc6d +-Subproject commit 693e278e308441d716f7f5116c43aa150955da31 diff --git a/3rdparty/blobs b/3rdparty/blobs deleted file mode 160000 -index 8eb92ba..0000000 +index 372012e..0000000 --- a/3rdparty/blobs +++ /dev/null @@ -1 +0,0 @@ --Subproject commit 8eb92ba947e171df11b3c62f5f257ce69b9e2d55 +-Subproject commit 372012e8e1d0d01f3e77ff73b118665b41ff68b6 diff --git a/3rdparty/chromeec b/3rdparty/chromeec deleted file mode 160000 -index 9fb1038..0000000 +index 11bd4c0..0000000 --- a/3rdparty/chromeec +++ /dev/null @@ -1 +0,0 @@ --Subproject commit 9fb10386a720d270e37ce61da3ff3a6d5a69951e +-Subproject commit 11bd4c0f4d11357ab830982d7dec164813c886dd diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit deleted file mode 160000 -index 42fb2d0..0000000 +index 718c79b..0000000 --- a/3rdparty/libgfxinit +++ /dev/null @@ -1 +0,0 @@ --Subproject commit 42fb2d065d604eb08c723ac6b96aeebb4c84cbd3 +-Subproject commit 718c79bb0713b5b90c9cc44e03197dc777066e3d diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase deleted file mode 160000 -index 6685971..0000000 +index 637f2a4..0000000 --- a/3rdparty/libhwbase +++ /dev/null @@ -1 +0,0 @@ --Subproject commit 66859712e4817288591908d737dbf41ddea31c3a +-Subproject commit 637f2a4f21ead8ccc45d5256834eb27ce72088db diff --git a/3rdparty/vboot b/3rdparty/vboot deleted file mode 160000 -index f6780a3..0000000 +index 392211f..0000000 --- a/3rdparty/vboot +++ /dev/null @@ -1 +0,0 @@ --Subproject commit f6780a36ff19b36abcdb5ace903c4ae2272fb574 +-Subproject commit 392211f0358919d510179ad399d8f056180e652e diff --git a/Makefile.inc b/Makefile.inc -index 413f7ad..ed2d839 100644 +index 3840505..da567de 100644 --- a/Makefile.inc +++ b/Makefile.inc -@@ -191,18 +191,6 @@ ifeq ($(CONFIG_COVERAGE),y) +@@ -188,18 +188,6 @@ ifeq ($(CONFIG_COVERAGE),y) ramstage-c-ccopts += -fprofile-arcs -ftest-coverage endif @@ -116,5 +116,5 @@ index 413f7ad..ed2d839 100644 ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) -- -1.9.1 +2.7.4 diff --git a/projects/cros-ec/configs/nyan/revision b/projects/cros-ec/configs/nyan/revision index 6ce6b84b..c5b2d348 100644 --- a/projects/cros-ec/configs/nyan/revision +++ b/projects/cros-ec/configs/nyan/revision @@ -1 +1 @@ -origin/release-R65-10323.B +origin/firmware-nyan-5771.B diff --git a/projects/cros-ec/configs/veyron/revision b/projects/cros-ec/configs/veyron/revision index 6ce6b84b..6c728396 100644 --- a/projects/cros-ec/configs/veyron/revision +++ b/projects/cros-ec/configs/veyron/revision @@ -1 +1 @@ -origin/release-R65-10323.B +origin/firmware-veyron-6588.B diff --git a/projects/cros-ec/patches/veyron/0005-Don-t-include-missing-and-unnecessary-math-header.patch b/projects/cros-ec/patches/veyron/0005-Don-t-include-missing-and-unnecessary-math-header.patch deleted file mode 100644 index 0a099213..00000000 --- a/projects/cros-ec/patches/veyron/0005-Don-t-include-missing-and-unnecessary-math-header.patch +++ /dev/null @@ -1,29 +0,0 @@ -From 913b2f1265bd7f3ebe6cf4cba92c20c5a423a6c3 Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski <contact@paulk.fr> -Date: Tue, 2 Aug 2016 12:05:55 +0200 -Subject: [PATCH 5/6] Don't include missing and unnecessary math header - -This removes the inclusion of an unnecessary math header that is neither -found nor necessary for non-cortex-m ECs. - -Change-Id: I56a04178dadedb76f841504fa645e2d43900d25f -Signed-off-by: Paul Kocialkowski <contact@paulk.fr> ---- - common/math_util.c | 1 - - 1 file changed, 1 deletion(-) - -diff --git a/common/math_util.c b/common/math_util.c -index 120d13d..34a267d 100644 ---- a/common/math_util.c -+++ b/common/math_util.c -@@ -6,7 +6,6 @@ - /* Common math functions. */ - - #include "common.h" --#include "math.h" - #include "math_util.h" - #include "util.h" - --- -2.9.0 - diff --git a/projects/cros-ec/patches/veyron/0006-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch b/projects/cros-ec/patches/veyron/0005-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch index f0175825..b70e471e 100644 --- a/projects/cros-ec/patches/veyron/0006-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch +++ b/projects/cros-ec/patches/veyron/0005-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch @@ -1,8 +1,7 @@ -From 9dd7ae82d3f3fa9dae31a442365e233a0b44cce3 Mon Sep 17 00:00:00 2001 +From 27501308493bf2adadfc3b133fd1d6f4b4feec12 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski <contact@paulk.fr> Date: Sat, 23 Jul 2016 14:17:32 +0200 -Subject: [PATCH 6/6] cortex-m0: Use assembly exception handlers for task - switching +Subject: [PATCH] cortex-m0: Use assembly exception handlers for task switching The way Cortex processors handle exceptions allows writing exception routines directly in C, as return from exception is handled by providing @@ -38,15 +37,12 @@ TEST=Build and run speedy EC with a recent GCC version Change-Id: Ib068bc12ce2204aee3e0f563efcb94f15aa87013 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> --- - core/cortex-m0/switch.S | 81 ++++++++++++++++++++++++++++++++++--------------- - core/cortex-m0/task.c | 27 +---------------- - 2 files changed, 58 insertions(+), 50 deletions(-) diff --git a/core/cortex-m0/switch.S b/core/cortex-m0/switch.S index 95ea29e..d4b47cd 100644 --- a/core/cortex-m0/switch.S +++ b/core/cortex-m0/switch.S -@@ -7,12 +7,52 @@ +@@ -7,55 +7,14 @@ #include "config.h" @@ -58,29 +54,56 @@ index 95ea29e..d4b47cd 100644 .code 16 /** -+ * Start the task scheduling. r0 is a pointer to task_stack_ready, which is -+ * set to 1 after the task stack is set up. -+ */ -+.global __task_start -+.thumb_func -+__task_start: -+ ldr r2,=scratchpad @ area used as dummy thread stack for the first switch -+ movs r3, #2 @ use : priv. mode / thread stack / no floating point -+ adds r2, #17*4 @ put the pointer at the top of the stack -+ movs r1, #0 @ __Schedule parameter : re-schedule nothing -+ msr psp, r2 @ setup a thread stack up to the first context switch -+ movs r2, #1 -+ isb @ ensure the write is done -+ msr control, r3 -+ movs r3, r0 -+ movs r0, #0 @ __Schedule parameter : de-schedule nothing -+ isb @ ensure the write is done -+ str r2, [r3] @ Task scheduling is now active -+ bl __schedule @ execute the task with the highest priority -+ /* we should never return here */ -+ movs r0, #1 @ set to EC_ERROR_UNKNOWN -+ bx lr -+ +- * Task context switching +- * +- * Change the task scheduled after returning from the exception. +- * +- * Save the registers of the current task below the exception context on +- * its task, then restore the live registers of the next task and set the +- * process stack pointer to the new stack. +- * +- * r0: pointer to the task to switch from +- * r1: pointer to the task to switch to +- * +- * must be called from interrupt context +- * +- * the structure of the saved context on the stack is : +- * r8, r9, r10, r11, r4, r5, r6, r7, r0, r1, r2, r3, r12, lr, pc, psr +- * additional registers <|> exception frame +- */ +-.global __switchto +-.thumb_func +-__switchto: +- mrs r2, psp @ get the task stack where the context has been saved +- mov r3, sp +- mov sp, r2 +- push {r4-r7} @ save additional r4-r7 in the task stack +- mov r4, r8 +- mov r5, r9 +- mov r6, r10 +- mov r7, r11 +- push {r4-r7} @ save additional r8-r11 in the task stack +- mov r2, sp @ prepare to save former task stack pointer +- mov sp, r3 @ restore system stack pointer +- str r2, [r0] @ save the task stack pointer in its context +- ldr r2, [r1] @ get the new scheduled task stack pointer +- ldmia r2!, {r4-r7} @ restore r8-r11 for the next task context +- mov r8, r4 +- mov r9, r5 +- mov r10, r6 +- mov r11, r7 +- ldmia r2!, {r4-r7} @ restore r4-r7 for the next task context +- msr psp, r2 @ set the process stack pointer to exception context +- bx lr @ return from exception +- +-/** + * Start the task scheduling. r0 is a pointer to task_stack_ready, which is + * set to 1 after the task stack is set up. + */ +@@ -79,3 +38,77 @@ + movs r0, #1 @ set to EC_ERROR_UNKNOWN + bx lr + +/** + * SVC exception handler + */ @@ -96,53 +119,53 @@ index 95ea29e..d4b47cd 100644 + /* continue to __switchto to switch to the new task */ + +/** - * Task context switching - * - * Change the task scheduled after returning from the exception. -@@ -30,8 +70,6 @@ - * r8, r9, r10, r11, r4, r5, r6, r7, r0, r1, r2, r3, r12, lr, pc, psr - * additional registers <|> exception frame - */ --.global __switchto --.thumb_func - __switchto: - mrs r2, psp @ get the task stack where the context has been saved - mov r3, sp -@@ -53,29 +91,24 @@ __switchto: - mov r11, r7 - ldmia r2!, {r4-r7} @ restore r4-r7 for the next task context - msr psp, r2 @ set the process stack pointer to exception context -- bx lr @ return from exception ++ * Task context switching ++ * ++ * Change the task scheduled after returning from the exception. ++ * ++ * Save the registers of the current task below the exception context on ++ * its task, then restore the live registers of the next task and set the ++ * process stack pointer to the new stack. ++ * ++ * r0: pointer to the task to switch from ++ * r1: pointer to the task to switch to ++ * ++ * must be called from interrupt context ++ * ++ * the structure of the saved context on the stack is : ++ * r8, r9, r10, r11, r4, r5, r6, r7, r0, r1, r2, r3, r12, lr, pc, psr ++ * additional registers <|> exception frame ++ */ ++__switchto: ++ mrs r2, psp @ get the task stack where the context has been saved ++ mov r3, sp ++ mov sp, r2 ++ push {r4-r7} @ save additional r4-r7 in the task stack ++ mov r4, r8 ++ mov r5, r9 ++ mov r6, r10 ++ mov r7, r11 ++ push {r4-r7} @ save additional r8-r11 in the task stack ++ mov r2, sp @ prepare to save former task stack pointer ++ mov sp, r3 @ restore system stack pointer ++ str r2, [r0] @ save the task stack pointer in its context ++ ldr r2, [r1] @ get the new scheduled task stack pointer ++ ldmia r2!, {r4-r7} @ restore r8-r11 for the next task context ++ mov r8, r4 ++ mov r9, r5 ++ mov r10, r6 ++ mov r11, r7 ++ ldmia r2!, {r4-r7} @ restore r4-r7 for the next task context ++ msr psp, r2 @ set the process stack pointer to exception context + +svc_handler_return: + pop {pc} @ return from exception or return to caller - - /** -- * Start the task scheduling. r0 is a pointer to task_stack_ready, which is -- * set to 1 after the task stack is set up. ++ ++/** + * PendSVC exception handler - */ --.global __task_start ++ */ +.global pendsv_handler - .thumb_func --__task_start: -- ldr r2,=scratchpad @ area used as dummy thread stack for the first switch -- movs r3, #2 @ use : priv. mode / thread stack / no floating point -- adds r2, #17*4 @ put the pointer at the top of the stack -- movs r1, #0 @ __Schedule parameter : re-schedule nothing -- msr psp, r2 @ setup a thread stack up to the first context switch -- movs r2, #1 -- isb @ ensure the write is done -- msr control, r3 -- movs r3, r0 -- movs r0, #0 @ __Schedule parameter : de-schedule nothing -- isb @ ensure the write is done -- str r2, [r3] @ Task scheduling is now active -- bl __schedule @ execute the task with the highest priority -- /* we should never return here */ -- movs r0, #1 @ set to EC_ERROR_UNKNOWN -- bx lr -- ++.thumb_func +pendsv_handler: + push {lr} @ save link register + ldr r0, =#CPU_SCB_ICSR @ load CPU_SCB_ICSR's address @@ -156,10 +179,10 @@ index 95ea29e..d4b47cd 100644 + cpsie i @ leave priority 0 + pop {pc} @ return from exception diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c -index e51621b..f96ccf8 100644 +index 5d219a5..0261261 100644 --- a/core/cortex-m0/task.c +++ b/core/cortex-m0/task.c -@@ -57,7 +57,6 @@ static uint32_t task_switches; /* Number of times active task changed */ +@@ -59,7 +59,6 @@ static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ #endif @@ -167,7 +190,7 @@ index e51621b..f96ccf8 100644 extern int __task_start(int *task_stack_ready); #ifndef CONFIG_LOW_POWER_IDLE -@@ -120,7 +119,7 @@ uint8_t task_stacks[0 +@@ -124,7 +123,7 @@ /* Reserve space to discard context on first context switch. */ uint32_t scratchpad[17]; @@ -176,7 +199,7 @@ index e51621b..f96ccf8 100644 /* * Bitmap of all tasks ready to be run. -@@ -242,18 +241,6 @@ task_ *__svc_handler(int desched, task_id_t resched) +@@ -254,18 +253,6 @@ return current; } @@ -195,7 +218,7 @@ index e51621b..f96ccf8 100644 void __schedule(int desched, int resched) { register int p0 asm("r0") = desched; -@@ -262,18 +249,6 @@ void __schedule(int desched, int resched) +@@ -274,18 +261,6 @@ asm("svc 0" : : "r"(p0), "r"(p1)); } @@ -214,6 +237,3 @@ index e51621b..f96ccf8 100644 #ifdef CONFIG_TASK_PROFILING void task_start_irq_handler(void *excep_return) { --- -2.9.0 - diff --git a/projects/cros-ec/patches/veyron/0006-Remove-duplicate-consts-declaration-specifiers.patch b/projects/cros-ec/patches/veyron/0006-Remove-duplicate-consts-declaration-specifiers.patch new file mode 100644 index 00000000..f04e2f27 --- /dev/null +++ b/projects/cros-ec/patches/veyron/0006-Remove-duplicate-consts-declaration-specifiers.patch @@ -0,0 +1,63 @@ +From 48acbee142ed1712ecdd4e5338f2a2d46bfbb1f3 Mon Sep 17 00:00:00 2001 +From: Andrew Robbins <contact@andrewrobbins.info> +Date: Thu, 15 Nov 2018 18:43:07 -0500 +Subject: [PATCH] Remove duplicate consts declaration specifiers + +--- + util/comm-dev.c | 2 +- + util/ectool.c | 2 +- + util/lbcc.c | 6 +++--- + 3 files changed, 5 insertions(+), 5 deletions(-) + +diff --git a/util/comm-dev.c b/util/comm-dev.c +index cdbbbdf..0fb4027 100644 +--- a/util/comm-dev.c ++++ b/util/comm-dev.c +@@ -23,7 +23,7 @@ static int fd = -1; + #define ARRAY_SIZE(t) (sizeof(t) / sizeof(t[0])) + #endif + +-static const char const *meanings[] = { ++static const char *meanings[] = { + "SUCCESS", + "INVALID_COMMAND", + "ERROR", +diff --git a/util/ectool.c b/util/ectool.c +index 9ba8de9..74e6366 100644 +--- a/util/ectool.c ++++ b/util/ectool.c +@@ -5199,7 +5199,7 @@ static int cmd_tmp006cal_v1(int idx, int argc, char *argv[]) + int i, rv, cmdsize; + + /* Algorithm 1 parameter names */ +- static const char const *alg1_pname[] = { ++ static const char *alg1_pname[] = { + "s0", "a1", "a2", "b0", "b1", "b2", "c2", + "d0", "d1", "ds", "e0", "e1", + }; +diff --git a/util/lbcc.c b/util/lbcc.c +index b34b21e..eb8a7e1 100644 +--- a/util/lbcc.c ++++ b/util/lbcc.c +@@ -81,15 +81,15 @@ static const int num_operands[] = { + + #define OP(NAME, BYTES, MNEMONIC) MNEMONIC, + #include "lightbar_opcode_list.h" +-static const char const *opcode_sym[] = { ++static const char *opcode_sym[] = { + LIGHTBAR_OPCODE_TABLE + }; + #undef OP + +-static const char const *control_sym[] = { ++static const char *control_sym[] = { + "beg", "end", "phase", "<invalid>" + }; +-static const char const *color_sym[] = { ++static const char *color_sym[] = { + "r", "g", "b", "<invalid>" + }; + +-- +2.7.4 + diff --git a/projects/cros-ec/patches/veyron/0007-Remove-unused-SHA256_digestinfo-declaration.patch b/projects/cros-ec/patches/veyron/0007-Remove-unused-SHA256_digestinfo-declaration.patch new file mode 100644 index 00000000..4f811727 --- /dev/null +++ b/projects/cros-ec/patches/veyron/0007-Remove-unused-SHA256_digestinfo-declaration.patch @@ -0,0 +1,31 @@ +From c4b1a9b5547321126658be2b418edc5b86010e3a Mon Sep 17 00:00:00 2001 +From: Andrew Robbins <contact@andrewrobbins.info> +Date: Thu, 15 Nov 2018 18:54:57 -0500 +Subject: [PATCH] Remove unused SHA256_digestinfo declaration + +--- + common/sha256.c | 8 -------- + 1 file changed, 8 deletions(-) + +diff --git a/common/sha256.c b/common/sha256.c +index e8f9f18..7e74a7f 100644 +--- a/common/sha256.c ++++ b/common/sha256.c +@@ -104,14 +104,6 @@ static const uint32_t sha256_k[64] = { + 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, + 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2}; + +-#define SHA256_DIGESTINFO_LEN 19 +- +-static const uint8_t SHA256_digestinfo[] = { +- 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86, +- 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05, +- 0x00, 0x04, 0x20 +-}; +- + void SHA256_init(struct sha256_ctx *ctx) + { + int i; +-- +2.7.4 + diff --git a/projects/crossgcc/crossgcc b/projects/crossgcc/crossgcc index 46b9e3f3..1c3f33d8 100755 --- a/projects/crossgcc/crossgcc +++ b/projects/crossgcc/crossgcc @@ -157,7 +157,7 @@ build() { bootstrap_flag='-b' fi - make -C "$sources_path" "$bootstrap_flag" CPUS="$TASKS" DEST="$build_path" "crossgcc-$arch" + make -C "$sources_path" $bootstrap_flag CPUS="$TASKS" DEST="$build_path" "crossgcc-$arch" } build_check() { diff --git a/projects/crossgcc/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch b/projects/crossgcc/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch deleted file mode 120000 index 627443a5..00000000 --- a/projects/crossgcc/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch +++ /dev/null @@ -1 +0,0 @@ -../../coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch
\ No newline at end of file diff --git a/projects/crossgcc/patches/0001-Don-t-pull-in-3rdparty-git-submodules.patch b/projects/crossgcc/patches/0001-Don-t-pull-in-3rdparty-git-submodules.patch new file mode 120000 index 00000000..250b848b --- /dev/null +++ b/projects/crossgcc/patches/0001-Don-t-pull-in-3rdparty-git-submodules.patch @@ -0,0 +1 @@ +../../coreboot/patches/0001-Don-t-pull-in-3rdparty-git-submodules.patch
\ No newline at end of file diff --git a/projects/dejavu-fonts/configs/unicode/ucd-files b/projects/dejavu-fonts/configs/unicode/ucd-files new file mode 100644 index 00000000..9b46bb9a --- /dev/null +++ b/projects/dejavu-fonts/configs/unicode/ucd-files @@ -0,0 +1,2 @@ +Blocks.txt +UnicodeData.txt diff --git a/projects/dejavu-fonts/configs/unicode/ucd-version b/projects/dejavu-fonts/configs/unicode/ucd-version new file mode 100644 index 00000000..275283a1 --- /dev/null +++ b/projects/dejavu-fonts/configs/unicode/ucd-version @@ -0,0 +1 @@ +11.0.0 diff --git a/projects/dejavu-fonts/dejavu-fonts b/projects/dejavu-fonts/dejavu-fonts index 037aa3d9..d380235f 100755 --- a/projects/dejavu-fonts/dejavu-fonts +++ b/projects/dejavu-fonts/dejavu-fonts @@ -26,17 +26,24 @@ usage() { download() { local repository="$project" + local sources_path="$(project_sources_path "$project" "$repository" "$@")" + local ucd_version="$(dejavu_fonts_ucd_version "$UNICODE" "$@")" + local ucd_files_path="$(dejavu_fonts_ucd_files_path "$UNICODE" "$@")" - project_download_git "$project" \ - "$repository" \ - 'https://github.com/dejavu-fonts/dejavu-fonts.git' \ - "$@" + local -a download_list + local -a ucd_files - local sources_path="$(project_sources_path "$project" "$repository" "$@")" + mapfile -t ucd_files < "$ucd_files_path" + + for file in "${ucd_files[@]}"; do + download_list+=("https://www.unicode.org/Public/$ucd_version/ucd/$file") + done - download_wrapper "$sources_path/resources" \ - 'https://www.unicode.org/Public/UNIDATA/UnicodeData.txt' \ - 'https://www.unicode.org/Public/UNIDATA/Blocks.txt' + project_download_git "$project" "$repository" https://github.com/dejavu-fonts/dejavu-fonts.git "$@" + download_wrapper "$sources_path/resources" "${download_list[@]}" + + # Create a symlink to fontconfig's orthography files + ln -fs ../../fontconfig/fc-lang "$sources_path/resources/fc-lang" } download_check() { @@ -83,9 +90,6 @@ build() { mkdir -p "$build_path" - # Create a symlink to the orthography files provided by fontconfig - ln -s "$root/$SOURCES/fontconfig/fc-lang" "$sources_path/resources/fc-lang" - make -C "$sources_path" -j"$TASKS" cp "$sources_path/build"/[!.]*.ttf "$build_path" make -C "$sources_path" clean diff --git a/projects/dejavu-fonts/dejavu-fonts-helper b/projects/dejavu-fonts/dejavu-fonts-helper new file mode 100644 index 00000000..ff750588 --- /dev/null +++ b/projects/dejavu-fonts/dejavu-fonts-helper @@ -0,0 +1,28 @@ +#!/usr/bin/env bash + +# Copyright (C) 2018 Andrew Robbins <contact@andrewrobbins.info> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. + +UCD_FILES='ucd-files' +UCD_VERSION='ucd-version' +UNICODE='unicode' + +dejavu_fonts_ucd_version() { + project_file_contents "$project" "$CONFIGS" "$UCD_VERSION" "$@" +} + +dejavu_fonts_ucd_files_path() { + project_file_path "$project" "$CONFIGS" "$UCD_FILES" "$@" +} diff --git a/projects/dejavu-fonts/patches/0001-Ignore-fc-lang-UnicodeData.txt-and-Blocks.txt.patch b/projects/dejavu-fonts/patches/0001-Ignore-fc-lang-UnicodeData.txt-and-Blocks.txt.patch new file mode 100644 index 00000000..df92cfc0 --- /dev/null +++ b/projects/dejavu-fonts/patches/0001-Ignore-fc-lang-UnicodeData.txt-and-Blocks.txt.patch @@ -0,0 +1,28 @@ +From b5ece2b11361fdce57cab3e0504babc0b616c396 Mon Sep 17 00:00:00 2001 +From: Andrew Robbins <contact@andrewrobbins.info> +Date: Mon, 10 Dec 2018 23:18:26 -0500 +Subject: [PATCH] Ignore fc-lang, UnicodeData.txt, and Blocks.txt + +UnicodeData.txt and Blocks.txt should be preserved after a +`git clean -df` to avoid needless refetching of these resources. + +Additionally, the fc-lang symlink is kept in order to avoid +recreating it before each build. +--- + .gitignore | 3 +++ + 1 file changed, 3 insertions(+) + +diff --git a/.gitignore b/.gitignore +index dedd2b5..74203a0 100644 +--- a/.gitignore ++++ b/.gitignore +@@ -2,3 +2,6 @@ build/ + dist/ + tmp/ + /src/*.sfd~ ++resources/Blocks.txt ++resources/UnicodeData.txt ++resources/fc-lang +-- +2.7.4 + diff --git a/projects/dejavu-fonts/patches/0001-Preserve-unicode-source-files-thru-git-clean-df.patch b/projects/dejavu-fonts/patches/0001-Preserve-unicode-source-files-thru-git-clean-df.patch deleted file mode 100644 index 52798b1e..00000000 --- a/projects/dejavu-fonts/patches/0001-Preserve-unicode-source-files-thru-git-clean-df.patch +++ /dev/null @@ -1,24 +0,0 @@ -From 9ac03500773a1cc69b198ce1c43770a7fc66da98 Mon Sep 17 00:00:00 2001 -From: Andrew Robbins <contact@andrewrobbins.info> -Date: Tue, 5 Sep 2017 23:57:34 -0400 -Subject: [PATCH] Preserve unicode source files thru `git clean -df` - -UnicodeData.txt and Blocks.txt should be preserved after a -`git clean -df` to avoid needless refetching of these resources. ---- - .gitignore | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/.gitignore b/.gitignore -index dedd2b5..841e748 100644 ---- a/.gitignore -+++ b/.gitignore -@@ -2,3 +2,5 @@ build/ - dist/ - tmp/ - /src/*.sfd~ -+resources/Blocks.txt -+resources/UnicodeData.txt --- -1.9.1 - diff --git a/projects/dejavu-fonts/patches/0002-Require-a-recent-fontforge-for-reproducibility.patch b/projects/dejavu-fonts/patches/0002-Require-a-recent-fontforge-for-reproducibility.patch new file mode 100644 index 00000000..3caaadb8 --- /dev/null +++ b/projects/dejavu-fonts/patches/0002-Require-a-recent-fontforge-for-reproducibility.patch @@ -0,0 +1,51 @@ +From 9dd7a8b9376b4fb6b82422899e0ed7b8606c73ce Mon Sep 17 00:00:00 2001 +From: Andrew Robbins <contact@andrewrobbins.info> +Date: Thu, 27 Dec 2018 23:37:07 -0500 +Subject: [PATCH] Require a recent fontforge for reproducibility + +The required version is set to 20171220 which is the earliest +date from which fontforge built from source was able to produce +the non-LGC subset of DejaVu deterministically. "20171220" refers +to upstream revision 69e561773b91e37096a855f0353b1d6781a61250 + +Note there was not an actual dejavu-fonts release made on 2017-12-20; +the date is intended to be both a reference point, as previously +described, and a mechanism to prevent non-deterministic fonts being +produced by Libreboot's build system due to an unsupported version +of fontforge being used. +--- + scripts/generate.pe | 4 ++-- + scripts/generate.py | 2 +- + 2 files changed, 3 insertions(+), 3 deletions(-) + +diff --git a/scripts/generate.pe b/scripts/generate.pe +index 5d9d03d..144e8b1 100755 +--- a/scripts/generate.pe ++++ b/scripts/generate.pe +@@ -16,8 +16,8 @@ + def_gen_flags = 0x20 + 0x40 + 0x800 + exp_gen_flags = def_gen_flags + 8 + +-if ($version < "20080330") +- Error("Your version of FontForge is too old - 20080330 or newer is required"); ++if ($version < "20171220") ++ Error("Your version of FontForge is too old - 20171220 or newer is required"); + endif + # FoundryName is not used in TTF generation + SetPref("FoundryName", "DejaVu") +diff --git a/scripts/generate.py b/scripts/generate.py +index 467d52b..168a2be 100755 +--- a/scripts/generate.py ++++ b/scripts/generate.py +@@ -7,7 +7,7 @@ + # chmod +x generate.pe + # ./generate.pe *.sfd + import fontforge, sys; +-required_version = "20080330" ++required_version = "20171220" + + # font generation flags: + # omit-instructions => do not include TT instructions (for experimental typefaces) +-- +2.7.4 + diff --git a/projects/depthcharge/configs/nyan/targets b/projects/depthcharge/configs/nyan/targets new file mode 100644 index 00000000..419aafc5 --- /dev/null +++ b/projects/depthcharge/configs/nyan/targets @@ -0,0 +1,2 @@ +big +blaze diff --git a/projects/depthcharge/configs/veyron/targets b/projects/depthcharge/configs/veyron/targets index 1722192f..e4c9ca9e 100644 --- a/projects/depthcharge/configs/veyron/targets +++ b/projects/depthcharge/configs/veyron/targets @@ -1,2 +1,4 @@ +jerry +mickey minnie speedy diff --git a/projects/depthcharge/depthcharge b/projects/depthcharge/depthcharge index 966b9689..dee1f555 100755 --- a/projects/depthcharge/depthcharge +++ b/projects/depthcharge/depthcharge @@ -69,7 +69,7 @@ build() { local sources_path=$(project_sources_path "$project" "$repository" "$@") local build_path=$(project_build_path "$project" "$@") - local libpayload_build_path=$(project_build_path "libpayload" "$project" "$@") + local libpayload_build_path=$(depthcharge_libpayload_build_path "$project" "$@") local libpayload_build_install_path="$libpayload_build_path/install" local vboot_sources_path=$(project_sources_path "vboot" "vboot" "devices") diff --git a/projects/depthcharge/depthcharge-helper b/projects/depthcharge/depthcharge-helper index 440fe0fe..d389fb97 100755 --- a/projects/depthcharge/depthcharge-helper +++ b/projects/depthcharge/depthcharge-helper @@ -1,6 +1,7 @@ #!/usr/bin/env bash # Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> +# Copyright (C) 2018 Andrew Robbins <contact@andrewrobbins.info> # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -24,3 +25,22 @@ depthcharge_arch() { depthcharge_device() { arguments_concat "_" "$@" } + +depthcharge_libpayload_build_path() { + local project='libpayload' + local build_path="$root/$BUILD/$project" + + local argument + + for argument in "$@"; do + build_path="$build_path-$argument" + + if [[ -d $build_path ]]; then + break + else + continue + fi + done + + printf '%s\n' "$build_path" +} diff --git a/projects/grub/configs/bios/config b/projects/grub/configs/bios/config index 9e627e2f..f971795c 100644 --- a/projects/grub/configs/bios/config +++ b/projects/grub/configs/bios/config @@ -1,2 +1,4 @@ -set root=(cbfsdisk) +set root=(fd0) +set prefix=($root)/boot/grub + source (cbfsdisk)/fallback/grub.cfg diff --git a/projects/grub/configs/bios/modules-minimal b/projects/grub/configs/bios/modules-minimal index 706aa529..b9684529 100644 --- a/projects/grub/configs/bios/modules-minimal +++ b/projects/grub/configs/bios/modules-minimal @@ -5,10 +5,14 @@ cbmemc configfile ehci ext2 +fat halt loadenv +memdisk +minicmd part_bsd part_gpt pata reboot +test verify diff --git a/projects/grub/configs/bios/prefix b/projects/grub/configs/bios/prefix index 48604ad8..c3e91bb3 100644 --- a/projects/grub/configs/bios/prefix +++ b/projects/grub/configs/bios/prefix @@ -1 +1 @@ -(cbfsdisk)/fallback +(fd0)/boot/grub diff --git a/projects/grub/configs/bios/size b/projects/grub/configs/bios/size index a7625603..693832e1 100644 --- a/projects/grub/configs/bios/size +++ b/projects/grub/configs/bios/size @@ -1 +1 @@ -160 +2880 diff --git a/projects/grub/configs/coreboot/config b/projects/grub/configs/coreboot/config index e3792e94..f5d969f9 100644 --- a/projects/grub/configs/coreboot/config +++ b/projects/grub/configs/coreboot/config @@ -1,4 +1,4 @@ -set prefix=(cbfsdisk)/fallback - set root=(cbfsdisk) -source (cbfsdisk)/fallback/grub.cfg +set prefix=($root)/fallback + +source $prefix/grub.cfg diff --git a/projects/grub/configs/coreboot/modules-minimal b/projects/grub/configs/coreboot/modules-minimal index 0480a0d0..f67c1dcc 100644 --- a/projects/grub/configs/coreboot/modules-minimal +++ b/projects/grub/configs/coreboot/modules-minimal @@ -6,9 +6,11 @@ ehci ext2 halt loadenv +minicmd part_bsd part_gpt pata reboot +test usbms verify diff --git a/projects/grub/configs/uefi/config b/projects/grub/configs/uefi/config index e3792e94..f5d969f9 100644 --- a/projects/grub/configs/uefi/config +++ b/projects/grub/configs/uefi/config @@ -1,4 +1,4 @@ -set prefix=(cbfsdisk)/fallback - set root=(cbfsdisk) -source (cbfsdisk)/fallback/grub.cfg +set prefix=($root)/fallback + +source $prefix/grub.cfg diff --git a/projects/grub/configs/uefi/modules-minimal b/projects/grub/configs/uefi/modules-minimal index 0480a0d0..f67c1dcc 100644 --- a/projects/grub/configs/uefi/modules-minimal +++ b/projects/grub/configs/uefi/modules-minimal @@ -6,9 +6,11 @@ ehci ext2 halt loadenv +minicmd part_bsd part_gpt pata reboot +test usbms verify diff --git a/projects/grub/grub-helper b/projects/grub/grub-helper index 596f7d96..ce874070 100755 --- a/projects/grub/grub-helper +++ b/projects/grub/grub-helper @@ -1,6 +1,6 @@ #!/usr/bin/env bash -# Copyright (C) 2017 Andrew Robbins <contact@andrewrobbins.info> +# Copyright (C) 2017,2018 Andrew Robbins <contact@andrewrobbins.info> # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -62,6 +62,47 @@ grub_modmin_path() { project_file_path "$project" "$CONFIGS" "$MODMIN" "$@" } +grub_bo_search() { + local pattern="$1" + local comparand="$2" + + grep -Fbof <(grub_bo_dump "$pattern") <(grub_bo_dump "$comparand") | cut -d: -f1 +} + +grub_bo_dump() { + local file="$1" + + od -An -t x1 -w16 -v "$file" | paste -sd '' | tr -d ' ' +} + +grub_bo() { + local pattern="$1" + local comparand="$2" + + local nibble_offset="$(grub_bo_search "$pattern" "$comparand")" + + if [[ -n "$nibble_offset" ]]; then + printf '0x%X\n' $((nibble_offset / 2)) + else + return 1 + fi +} + +grub_blocklist_format() { + local blocklist="$1" + local byte + + while read -N 2 byte; do + printf '%s' "\\x$byte" + done <<< "$blocklist" +} + +grub_blocklist_generate() { + local -i byte_offset="$1" + + printf '%04x' $((byte_offset / 512)) | tac -rs .. +} + grub_copy_modules() { local grub_module_dir="$sources_path/grub-core" local keep_dir="$build_path/$(grub_format "$target" "$@")" @@ -72,14 +113,12 @@ grub_copy_modules() { } grub_build_font() { - # Font project-specific filenames and paths local font_file="$(grub_font_file "$FONTS" "$@")" local font_project="$(grub_font_project "$FONTS" "$@")" local font_build_dir="$root/$BUILD/$font_project" local grub_mkfont="$sources_path/grub-mkfont" - # GRUB font directory for outputting the built PF2 file mkdir -p "$build_path/$FONTS" "$grub_mkfont" --output="$build_path/$FONTS/${font_file%.*}.pf2" \ @@ -88,8 +127,6 @@ grub_build_font() { grub_build_utils() { ( - # If arch and/or platform files don't exist, - # the configure script will pick a reasonable default local arch="$(grub_arch "$target" "$@")" local platform="$(grub_platform "$target" "$@")" @@ -135,25 +172,31 @@ grub_build_bootable_image() { local grub_mkimage="$sources_path/grub-mkimage" local grub_module_dir="$sources_path/grub-core" - local grubimg="$build_path/grub.img" local grub_bootimg="$grub_module_dir/boot.img" - local grub_bootable_img="$build_path/grub2" + local grub_coreimg="$build_path/core.img" "$grub_mkimage" \ --config="$config_path" \ --directory="$grub_module_dir" \ - --output="$grubimg" \ + --output="$grub_coreimg" \ --format="$format" \ --prefix="$prefix" \ "${modmin[@]}" - cat "$grub_bootimg" "$grubimg" > "$grub_bootable_img" - rm -f "$grubimg" + cp -a "$grub_bootimg" "$build_path" } grub_build_floppy_image() { - local grubimg="$build_path/grub2" - local tempfile="$build_path/temp.file" + local floppyimg="$build_path/floppy.img" + local format="$(grub_format "$target" "$@")" + local grub_module_dir="$sources_path/grub-core" + local size="$(grub_size "$target" "$@")" + + local -a modules + + for module in "$grub_module_dir"/*.mod; do + modules+=($module) + done if ! grub_build_bootable_image "$@"; then printf '\n%s\n\n' "Error: Failed to build a GRUB image" 1>&2 @@ -161,33 +204,19 @@ grub_build_floppy_image() { return 1 fi - local size="$(grub_size "$target" "$@")" - - # Pre-allocate a floppy-sized image + # Pre-allocate a floppy-sized image with a FAT12 filesystem # SeaBIOS requires floppy images to have a "correct" size - if ! [[ -e "$tempfile" ]]; then - dd if=/dev/zero of="$tempfile" bs=1024 count="${size:-160}" + if ! [[ -e "$floppyimg" ]]; then + mkfs.fat -C -D 0x00 -F 12 -M 0xF9 -n SEAGRUB --invariant "$floppyimg" "$size" else - printf '\n%s\n\n' "Error: File $tempfile already exists!" 1>&2 + printf '\n%s\n\n' "Error: File $floppyimg already exists!" 1>&2 return 1 fi - local -i grubimg_size="$(stat -c %s "$grubimg")" - local -i floppy_size="$((${size:-160} * 1024))" - - # Graft the GRUB image onto the blank floppy image - if ((grubimg_size <= floppy_size)); then - dd if="$grubimg" of="$tempfile" bs=1 conv=notrunc - - rm -f "$grubimg" - mv "$tempfile" "$grubimg" - else - printf '\n%s' "Error: Image ${grubimg##*/} is too large; " 1>&2 - printf '%s\n\n' "it must be less than ${floppy_size}KiB in size" 1>&2 - - return 1 - fi + grub_floppy_image_mmd "$floppyimg" /boot /boot/grub "/boot/grub/$format" + grub_floppy_image_mcopy "$floppyimg" "/boot/grub/$format" "${modules[@]}" + grub_floppy_image_make_bootable "$floppyimg" } grub_build_standalone_image() { @@ -216,3 +245,80 @@ grub_build_standalone_image() { --output="$grubimg" \ /boot/grub/grub.cfg="$config_path" } + +grub_floppy_image_mmd() { + local img="$1" + local -a dirs=("${@:2}") + + if [[ -n "$img" ]]; then + mmd -i "$img" "${dirs[@]}" + else + return 1 + fi +} + +grub_floppy_image_mcopy() { + local img="$1" + local target="$2" + local -a files=("${@:3}") + + if [[ -z "$img" ]]; then + return 1 + elif [[ -z "${files[@]}" ]]; then + mcopy -i "$img" -pv "::$target" + else + mcopy -i "$img" -pQv "${files[@]}" "::$target" + fi +} + +grub_floppy_image_make_bootable() { + local floppyimg="$1" + local bootimg="$build_path/boot.img" + local coreimg="$build_path/core.img" + local oem_name='\x4C\x49\x42\x52\x45\x20\x20\x20' + + # write $floppyimg Bios Parameter Block to $bootimg first + dd if="$floppyimg" of="$bootimg" bs=1 skip=11 seek=11 count=51 conv=notrunc + dd if=<(printf "$oem_name") of="$bootimg" bs=1 seek=3 conv=notrunc + dd if=/dev/zero of="$floppyimg" count=1 conv=notrunc + dd if="$bootimg" of="$floppyimg" conv=notrunc + + grub_floppy_image_mcopy "$floppyimg" /boot/grub "$bootimg" + grub_floppy_image_mcopy "$floppyimg" /boot/grub "$coreimg" + + grub_floppy_image_update_blocklists "$coreimg" "$floppyimg" + rm -f "$bootimg" "$coreimg" +} + +grub_floppy_image_update_blocklists() { + local coreimg="$1" + local floppyimg="$2" + + local -i coreimg_offset="$(grub_bo "$coreimg" "$floppyimg")" + local -i coreimg_second_sector_offset=$((coreimg_offset + 0x200)) + + local -i boot_record_blocklist_offset=0x5C + local -i coreimg_blocklist_offset=$((coreimg_offset + 0x1F4)) + + # blocklists (little endian) describe the $coreimg_offset in sectors + local boot_record_blocklist="$(grub_blocklist_generate "$coreimg_offset")" + local coreimg_blocklist="$(grub_blocklist_generate "$coreimg_second_sector_offset")" + + if [[ $coreimg_offset -gt 0 ]]; then + dd if=<(printf "$(grub_blocklist_format "$boot_record_blocklist")") \ + of="$floppyimg" \ + bs=1 \ + seek="$boot_record_blocklist_offset" \ + conv=notrunc + + dd if=<(printf "$(grub_blocklist_format "$coreimg_blocklist")") \ + of="$floppyimg" \ + bs=1 \ + seek="$coreimg_blocklist_offset" \ + conv=notrunc + else + printf 1>&2 '%s\n' "Error: ${coreimg##*/} offset not found" + + return 1 + fi +} diff --git a/projects/libpayload/configs/depthcharge/veyron/targets b/projects/libpayload/configs/depthcharge/veyron/targets deleted file mode 100644 index 1722192f..00000000 --- a/projects/libpayload/configs/depthcharge/veyron/targets +++ /dev/null @@ -1,2 +0,0 @@ -minnie -speedy diff --git a/projects/seabios/configs/bios/config b/projects/seabios/configs/bios/config deleted file mode 100644 index cd13ec77..00000000 --- a/projects/seabios/configs/bios/config +++ /dev/null @@ -1,91 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# SeaBIOS Configuration -# - -# -# General Features -# -CONFIG_COREBOOT=y -# CONFIG_QEMU is not set -# CONFIG_CSM is not set -# CONFIG_QEMU_HARDWARE is not set -CONFIG_THREADS=y -CONFIG_RELOCATE_INIT=y -CONFIG_BOOTMENU=y -CONFIG_BOOTSPLASH=y -CONFIG_BOOTORDER=y -CONFIG_COREBOOT_FLASH=y -CONFIG_LZMA=y -CONFIG_CBFS_LOCATION=0 -CONFIG_MULTIBOOT=y -CONFIG_ENTRY_EXTRASTACK=y -CONFIG_MALLOC_UPPERMEMORY=y -CONFIG_ROM_SIZE=0 - -# -# Hardware support -# -CONFIG_ATA=y -# CONFIG_ATA_DMA is not set -# CONFIG_ATA_PIO32 is not set -CONFIG_AHCI=y -CONFIG_SDCARD=y -CONFIG_MEGASAS=y -CONFIG_FLOPPY=y -CONFIG_FLASH_FLOPPY=y -CONFIG_PS2PORT=y -CONFIG_USB=y -CONFIG_USB_UHCI=y -CONFIG_USB_OHCI=y -CONFIG_USB_EHCI=y -CONFIG_USB_XHCI=y -CONFIG_USB_MSC=y -CONFIG_USB_UAS=y -CONFIG_USB_HUB=y -CONFIG_USB_KEYBOARD=y -CONFIG_USB_MOUSE=y -CONFIG_SERIAL=y -CONFIG_LPT=y -CONFIG_RTC_TIMER=y -CONFIG_HARDWARE_IRQ=y -CONFIG_PMTIMER=y -CONFIG_TSC_TIMER=y - -# -# BIOS interfaces -# -CONFIG_DRIVES=y -CONFIG_CDROM_BOOT=y -CONFIG_CDROM_EMU=y -CONFIG_PCIBIOS=y -CONFIG_APMBIOS=y -CONFIG_PNPBIOS=y -CONFIG_OPTIONROMS=y -CONFIG_PMM=y -CONFIG_BOOT=y -CONFIG_KEYBOARD=y -CONFIG_KBD_CALL_INT15_4F=y -CONFIG_MOUSE=y -CONFIG_S3_RESUME=y -CONFIG_VGAHOOKS=y -# CONFIG_DISABLE_A20 is not set -CONFIG_TCGBIOS=y - -# -# VGA ROM -# -CONFIG_NO_VGABIOS=y -# CONFIG_VGA_GEODEGX2 is not set -# CONFIG_VGA_GEODELX is not set -# CONFIG_VGA_COREBOOT is not set -# CONFIG_BUILD_VGABIOS is not set -CONFIG_VGA_EXTRA_STACK_SIZE=512 - -# -# Debugging -# -CONFIG_DEBUG_LEVEL=1 -# CONFIG_DEBUG_SERIAL is not set -# CONFIG_DEBUG_SERIAL_MMIO is not set -CONFIG_DEBUG_COREBOOT=y diff --git a/projects/seabios/configs/vgabios/config b/projects/seabios/configs/config index a2725409..5b2d44b6 100644 --- a/projects/seabios/configs/vgabios/config +++ b/projects/seabios/configs/config @@ -34,6 +34,7 @@ CONFIG_SDCARD=y CONFIG_MEGASAS=y CONFIG_FLOPPY=y CONFIG_FLASH_FLOPPY=y +CONFIG_NVME=y CONFIG_PS2PORT=y CONFIG_USB=y CONFIG_USB_UHCI=y @@ -46,6 +47,7 @@ CONFIG_USB_HUB=y CONFIG_USB_KEYBOARD=y CONFIG_USB_MOUSE=y CONFIG_SERIAL=y +CONFIG_SERCON=y CONFIG_LPT=y CONFIG_RTC_TIMER=y CONFIG_HARDWARE_IRQ=y diff --git a/projects/seabios/configs/bios/install b/projects/seabios/configs/install index 9189ec8f..dd4c65c0 100644 --- a/projects/seabios/configs/bios/install +++ b/projects/seabios/configs/install @@ -1 +1,2 @@ bios.bin.elf:bios.bin.elf +vgabios.bin:vgabios.bin diff --git a/projects/seabios/configs/revision b/projects/seabios/configs/revision index 3274dbdb..2c6e65b5 100644 --- a/projects/seabios/configs/revision +++ b/projects/seabios/configs/revision @@ -1 +1 @@ -rel-1.11.0 +rel-1.12.0 diff --git a/projects/seabios/configs/targets b/projects/seabios/configs/targets deleted file mode 100644 index 98a59a61..00000000 --- a/projects/seabios/configs/targets +++ /dev/null @@ -1,2 +0,0 @@ -bios -vgabios diff --git a/projects/seabios/configs/vgabios/install b/projects/seabios/configs/vgabios/install deleted file mode 100644 index ddc1571e..00000000 --- a/projects/seabios/configs/vgabios/install +++ /dev/null @@ -1 +0,0 @@ -vgabios.bin:vgabios.bin diff --git a/projects/seabios/seabios b/projects/seabios/seabios index ce9593b0..8f523f61 100755 --- a/projects/seabios/seabios +++ b/projects/seabios/seabios @@ -27,7 +27,8 @@ usage() { download() { local repository="$project" - project_download_git "$project" "$repository" 'https://review.coreboot.org/seabios.git' "$@" + project_download_git "$project" "$repository" 'https://git.seabios.org/seabios.git' "$@" || \ + project_download_git "$project" "$repository" 'https://review.coreboot.org/cgit/seabios.git/' "$@" } download_check() { @@ -74,14 +75,7 @@ build() { mkdir -p "$build_path" cp "$seabios_config_path" "$sources_path/.config" - make -C "$sources_path" -j"$TASKS" - - if [[ "$target" == 'bios' ]]; then - cp "$sources_path/out/bios.bin.elf" "$build_path" - elif [[ "$target" == 'vgabios' ]]; then - cp "$sources_path/out/vgabios.bin" "$build_path" - fi - + make -C "$sources_path" OUT="$build_path/" -j"$TASKS" make -C "$sources_path" distclean rm -f "$sources_path/.config" diff --git a/resources/scripts/helpers/download/seabios b/resources/scripts/helpers/download/seabios index b773ec59..8e92618a 100755 --- a/resources/scripts/helpers/download/seabios +++ b/resources/scripts/helpers/download/seabios @@ -35,7 +35,8 @@ rm -rf "seabios/" # ------------------------------------------------------------------------------ # download it using git -git clone https://git.seabios.org/seabios.git seabios +git clone https://git.seabios.org/seabios.git seabios || \ +git clone https://review.coreboot.org/cgit/seabios.git/ seabios ( # modifications are required diff --git a/www/download.md b/www/download.md index fc58adca..221ff2fa 100644 --- a/www/download.md +++ b/www/download.md @@ -59,6 +59,8 @@ university, USA) <https://mirror-hk.koddos.net/libreboot/> (koddos.net, Hong Kong) +<https://mirror.cyberbits.eu/libreboot/> (cyberbits.eu, France) + RSYNC mirrors {#rsync} ------------- @@ -102,6 +104,8 @@ if using HTTPS. <http://mirror.helium.in-berlin.de/libreboot/> (in-berlin.de, Germany) +<http://mirror.cyberbits.eu/libreboot/> (cyberbits.eu, France) + FTP mirrors {#ftp} ----------- @@ -149,6 +149,87 @@ cryptomount command from `for` loop in libreboot's It could be fixed in upstream grub by contributing patch that would add quiet flag to it. +How to save kernel panic logs on thinkpad laptops? +-------------------------------------------------- + +The easiest method of doing so is by using the kernel's netconsole +and reproducing the panic. Netconsole requires two machines, the one that is +panicky (source) and the one that will receive crash logs (target). The +source has to be connected with an ethernet cable and the target has to be +reachable at the time of the panic. To set this system up, execute the +following commands as root on the source (`source#`) and normal user on +the target (`target$`): + +1. Start a listener server on the target machine (netcat works well): + + `target$ nc -u -l -p 6666` + +2. Mount configfs (only once per boot, you can check if it is already mounted + with `mount | grep /sys/kernel/config`. This will return no output + if it is not). + + `source# modprobe configfs` + + `source# mkdir -p /sys/kernel/config` + + `source# mount none -t configfs /sys/kernel/config` + +3. find source's ethernet interface name, it should be of the form `enp*` or + `eth*`, see `ip address` or `ifconfig` output. + + `source# iface="enp0s29f8u1"` change this + + Fill the target machine's IPv4 address here: + + `source# tgtip="192.168.1.2"` change this + + +3. Create netconsole logging target on the source machine: + + `source# modprobe netconsole` + + `source# cd /sys/kernel/config/netconsole` + + `source# mkdir target1; cd target1` + + `source# srcip=$(ip -4 addr show dev "$iface" | grep -Eo '[0-9]+\.[0-9]+\.[0-9]+\.[0-9]+')` + + `source# echo "$srcip" > local_ip` + + `source# echo "$tgtip" > remote_ip` + + `source# echo "$iface" > dev_name` + + `source# arping -I "$iface" "$tgtip" -f | grep -o '..:..:..:..:..:..' > remote_mac` + + `source# echo 1 > enabled` + +4. Change console loglevel to debugging: + + `source# dmesg -n debug` + +5. Test if the logging works by e.g. inserting or removing an USB + device on the source. There should be a few lines appearing in the + terminal, in which you started netcat (nc), on the target host. + +6. Try to reproduce the kernel panic. + +Machine check exceptions on some Montevina (Penryn CPU) laptops +--------------------------------------------------------------- + +Some GM45 laptops have been freezing or experiencing a kernel panic +(blinking caps lock LED and totaly unresponsive machine, sometimes followed +by an automatic reboot within 30 seconds). +We do not know what the problem(s) is(are), but a CPU microcode +update in some cases prevents this from happening again. +See the following bug reports for more info: + +- [T400 Machine check: Processor context corrupt](https://notabug.org/libreboot/libreboot/issues/493) +- [X200 Machine check: Processor context corrupt](https://notabug.org/libreboot/libreboot/issues/289) + +- [Unrelated, RAM incompatibility and suspend-to-ram issues on X200](https://libreboot.org/docs/hardware/x200.html#ram_s3_microcode) + + Hardware compatibility ====================== @@ -1070,3 +1151,5 @@ Where can I learn more about electronics which is free software under MIT license. Use of youtube-dl with mpv would be recommended for youtube links + +Lastly the most important message to everybody gaining this wonderful new hobby - [Secret to Learning Electronics](https://www.youtube.com/watch?v=xhQ7d3BK3KQ) diff --git a/www/index.md b/www/index.md index 9181a429..8d13c9ea 100644 --- a/www/index.md +++ b/www/index.md @@ -41,6 +41,6 @@ firmware. Libreboot provides many advanced features, like encrypted Libreboot's main upstream provider is [coreboot](https://www.coreboot.org/), which we deblob. We upstream our custom patches to projects like coreboot, -depthcharge, GRUB, and flashrom where possible. Together, we provide an -automated build and installation system with non-technical documentation, -allowing Libreboot to be widely used. +depthcharge, GRUB, and flashrom where possible. Together, our build system +and documentation is provided with the aim of making free boot firmware +accessible to all. diff --git a/www/news/MANIFEST b/www/news/MANIFEST index 0e7cc034..e3b990e8 100644 --- a/www/news/MANIFEST +++ b/www/news/MANIFEST @@ -1,3 +1,4 @@ +news/freenode2018-workshop.md news/leah-fundraiser.md news/libreplanet2018-workshop.md news/release-testing-20171221.md diff --git a/www/news/freenode2018-workshop.md b/www/news/freenode2018-workshop.md new file mode 100644 index 00000000..9135e895 --- /dev/null +++ b/www/news/freenode2018-workshop.md @@ -0,0 +1,16 @@ +% Libreboot workshop at Freenode #live 2018 Conference in Bristol, UK +% Leah Rowe +% 2 November 2018 + +Freenode #live is the annual conference held by +[Freenode](https://freenode.net/) in Bristol, UK. This year I, Leah Rowe, will +be there doing a talk about Libreboot at 10AM (UTC +0) on November 3rd. In +addition, I have decided (hence this announcement) at the last minute that I'm +taking my SPI flashing equipment with me. More details about this conference +are on the Freenode #live website: <https://freenode.live/> + +If anyone attending this conference wants their system flashed with Libreboot, +bring it to the conference. I'll be volunteering at the FSF booth there all +day on both Saturday and Sunday. + +I will also be representing the FSF as a volunteer on both days. diff --git a/www/publish.sh b/www/publish.sh index 9a8a6abc..d2924a48 100755 --- a/www/publish.sh +++ b/www/publish.sh @@ -56,12 +56,7 @@ if [[ $FILE != "./docs/fdl-1.3" && $FILE != "docs/fdl-1.3" && fi # change out .md -> .html -sed -i -e 's/\.md\(#[a-z\-]*\)*)/.html\1)/g' "$TMPFILE" -sed -i -e 's/\.md\(#[a-z\-]*\)*]/.html\1]/g' "$TMPFILE" - -# change out .md -> .html -sed -i -e 's/\.md\(#[a-z\-]*\)*)/.html\1)/g' "$TMPFILE" -sed -i -e 's/\.md\(#[a-z\-]*\)*]/.html\1]/g' "$TMPFILE" +sed -i -e 's/\.md\(#[a-zA-Z0-9_-]*\)\?\([])]*\)/.html\1\2/g' "$TMPFILE" # work around issue #2872 TOC=$(grep -q "^x-toc-enable: true$" "$TMPFILE" && printf '%s\n' "--toc --toc-depth=2") || TOC="" |