diff options
Diffstat (limited to 'projects/cros-ec/patches')
| -rw-r--r-- | projects/cros-ec/patches/veyron/0005-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch | 180 |
1 files changed, 100 insertions, 80 deletions
diff --git a/projects/cros-ec/patches/veyron/0005-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch b/projects/cros-ec/patches/veyron/0005-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch index f0175825..b70e471e 100644 --- a/projects/cros-ec/patches/veyron/0005-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch +++ b/projects/cros-ec/patches/veyron/0005-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch @@ -1,8 +1,7 @@ -From 9dd7ae82d3f3fa9dae31a442365e233a0b44cce3 Mon Sep 17 00:00:00 2001 +From 27501308493bf2adadfc3b133fd1d6f4b4feec12 Mon Sep 17 00:00:00 2001 From: Paul Kocialkowski <contact@paulk.fr> Date: Sat, 23 Jul 2016 14:17:32 +0200 -Subject: [PATCH 6/6] cortex-m0: Use assembly exception handlers for task - switching +Subject: [PATCH] cortex-m0: Use assembly exception handlers for task switching The way Cortex processors handle exceptions allows writing exception routines directly in C, as return from exception is handled by providing @@ -38,15 +37,12 @@ TEST=Build and run speedy EC with a recent GCC version Change-Id: Ib068bc12ce2204aee3e0f563efcb94f15aa87013 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> --- - core/cortex-m0/switch.S | 81 ++++++++++++++++++++++++++++++++++--------------- - core/cortex-m0/task.c | 27 +---------------- - 2 files changed, 58 insertions(+), 50 deletions(-) diff --git a/core/cortex-m0/switch.S b/core/cortex-m0/switch.S index 95ea29e..d4b47cd 100644 --- a/core/cortex-m0/switch.S +++ b/core/cortex-m0/switch.S -@@ -7,12 +7,52 @@ +@@ -7,55 +7,14 @@ #include "config.h" @@ -58,29 +54,56 @@ index 95ea29e..d4b47cd 100644 .code 16 /** -+ * Start the task scheduling. r0 is a pointer to task_stack_ready, which is -+ * set to 1 after the task stack is set up. -+ */ -+.global __task_start -+.thumb_func -+__task_start: -+ ldr r2,=scratchpad @ area used as dummy thread stack for the first switch -+ movs r3, #2 @ use : priv. mode / thread stack / no floating point -+ adds r2, #17*4 @ put the pointer at the top of the stack -+ movs r1, #0 @ __Schedule parameter : re-schedule nothing -+ msr psp, r2 @ setup a thread stack up to the first context switch -+ movs r2, #1 -+ isb @ ensure the write is done -+ msr control, r3 -+ movs r3, r0 -+ movs r0, #0 @ __Schedule parameter : de-schedule nothing -+ isb @ ensure the write is done -+ str r2, [r3] @ Task scheduling is now active -+ bl __schedule @ execute the task with the highest priority -+ /* we should never return here */ -+ movs r0, #1 @ set to EC_ERROR_UNKNOWN -+ bx lr -+ +- * Task context switching +- * +- * Change the task scheduled after returning from the exception. +- * +- * Save the registers of the current task below the exception context on +- * its task, then restore the live registers of the next task and set the +- * process stack pointer to the new stack. +- * +- * r0: pointer to the task to switch from +- * r1: pointer to the task to switch to +- * +- * must be called from interrupt context +- * +- * the structure of the saved context on the stack is : +- * r8, r9, r10, r11, r4, r5, r6, r7, r0, r1, r2, r3, r12, lr, pc, psr +- * additional registers <|> exception frame +- */ +-.global __switchto +-.thumb_func +-__switchto: +- mrs r2, psp @ get the task stack where the context has been saved +- mov r3, sp +- mov sp, r2 +- push {r4-r7} @ save additional r4-r7 in the task stack +- mov r4, r8 +- mov r5, r9 +- mov r6, r10 +- mov r7, r11 +- push {r4-r7} @ save additional r8-r11 in the task stack +- mov r2, sp @ prepare to save former task stack pointer +- mov sp, r3 @ restore system stack pointer +- str r2, [r0] @ save the task stack pointer in its context +- ldr r2, [r1] @ get the new scheduled task stack pointer +- ldmia r2!, {r4-r7} @ restore r8-r11 for the next task context +- mov r8, r4 +- mov r9, r5 +- mov r10, r6 +- mov r11, r7 +- ldmia r2!, {r4-r7} @ restore r4-r7 for the next task context +- msr psp, r2 @ set the process stack pointer to exception context +- bx lr @ return from exception +- +-/** + * Start the task scheduling. r0 is a pointer to task_stack_ready, which is + * set to 1 after the task stack is set up. + */ +@@ -79,3 +38,77 @@ + movs r0, #1 @ set to EC_ERROR_UNKNOWN + bx lr + +/** + * SVC exception handler + */ @@ -96,53 +119,53 @@ index 95ea29e..d4b47cd 100644 + /* continue to __switchto to switch to the new task */ + +/** - * Task context switching - * - * Change the task scheduled after returning from the exception. -@@ -30,8 +70,6 @@ - * r8, r9, r10, r11, r4, r5, r6, r7, r0, r1, r2, r3, r12, lr, pc, psr - * additional registers <|> exception frame - */ --.global __switchto --.thumb_func - __switchto: - mrs r2, psp @ get the task stack where the context has been saved - mov r3, sp -@@ -53,29 +91,24 @@ __switchto: - mov r11, r7 - ldmia r2!, {r4-r7} @ restore r4-r7 for the next task context - msr psp, r2 @ set the process stack pointer to exception context -- bx lr @ return from exception ++ * Task context switching ++ * ++ * Change the task scheduled after returning from the exception. ++ * ++ * Save the registers of the current task below the exception context on ++ * its task, then restore the live registers of the next task and set the ++ * process stack pointer to the new stack. ++ * ++ * r0: pointer to the task to switch from ++ * r1: pointer to the task to switch to ++ * ++ * must be called from interrupt context ++ * ++ * the structure of the saved context on the stack is : ++ * r8, r9, r10, r11, r4, r5, r6, r7, r0, r1, r2, r3, r12, lr, pc, psr ++ * additional registers <|> exception frame ++ */ ++__switchto: ++ mrs r2, psp @ get the task stack where the context has been saved ++ mov r3, sp ++ mov sp, r2 ++ push {r4-r7} @ save additional r4-r7 in the task stack ++ mov r4, r8 ++ mov r5, r9 ++ mov r6, r10 ++ mov r7, r11 ++ push {r4-r7} @ save additional r8-r11 in the task stack ++ mov r2, sp @ prepare to save former task stack pointer ++ mov sp, r3 @ restore system stack pointer ++ str r2, [r0] @ save the task stack pointer in its context ++ ldr r2, [r1] @ get the new scheduled task stack pointer ++ ldmia r2!, {r4-r7} @ restore r8-r11 for the next task context ++ mov r8, r4 ++ mov r9, r5 ++ mov r10, r6 ++ mov r11, r7 ++ ldmia r2!, {r4-r7} @ restore r4-r7 for the next task context ++ msr psp, r2 @ set the process stack pointer to exception context + +svc_handler_return: + pop {pc} @ return from exception or return to caller - - /** -- * Start the task scheduling. r0 is a pointer to task_stack_ready, which is -- * set to 1 after the task stack is set up. ++ ++/** + * PendSVC exception handler - */ --.global __task_start ++ */ +.global pendsv_handler - .thumb_func --__task_start: -- ldr r2,=scratchpad @ area used as dummy thread stack for the first switch -- movs r3, #2 @ use : priv. mode / thread stack / no floating point -- adds r2, #17*4 @ put the pointer at the top of the stack -- movs r1, #0 @ __Schedule parameter : re-schedule nothing -- msr psp, r2 @ setup a thread stack up to the first context switch -- movs r2, #1 -- isb @ ensure the write is done -- msr control, r3 -- movs r3, r0 -- movs r0, #0 @ __Schedule parameter : de-schedule nothing -- isb @ ensure the write is done -- str r2, [r3] @ Task scheduling is now active -- bl __schedule @ execute the task with the highest priority -- /* we should never return here */ -- movs r0, #1 @ set to EC_ERROR_UNKNOWN -- bx lr -- ++.thumb_func +pendsv_handler: + push {lr} @ save link register + ldr r0, =#CPU_SCB_ICSR @ load CPU_SCB_ICSR's address @@ -156,10 +179,10 @@ index 95ea29e..d4b47cd 100644 + cpsie i @ leave priority 0 + pop {pc} @ return from exception diff --git a/core/cortex-m0/task.c b/core/cortex-m0/task.c -index e51621b..f96ccf8 100644 +index 5d219a5..0261261 100644 --- a/core/cortex-m0/task.c +++ b/core/cortex-m0/task.c -@@ -57,7 +57,6 @@ static uint32_t task_switches; /* Number of times active task changed */ +@@ -59,7 +59,6 @@ static uint32_t irq_dist[CONFIG_IRQ_COUNT]; /* Distribution of IRQ calls */ #endif @@ -167,7 +190,7 @@ index e51621b..f96ccf8 100644 extern int __task_start(int *task_stack_ready); #ifndef CONFIG_LOW_POWER_IDLE -@@ -120,7 +119,7 @@ uint8_t task_stacks[0 +@@ -124,7 +123,7 @@ /* Reserve space to discard context on first context switch. */ uint32_t scratchpad[17]; @@ -176,7 +199,7 @@ index e51621b..f96ccf8 100644 /* * Bitmap of all tasks ready to be run. -@@ -242,18 +241,6 @@ task_ *__svc_handler(int desched, task_id_t resched) +@@ -254,18 +253,6 @@ return current; } @@ -195,7 +218,7 @@ index e51621b..f96ccf8 100644 void __schedule(int desched, int resched) { register int p0 asm("r0") = desched; -@@ -262,18 +249,6 @@ void __schedule(int desched, int resched) +@@ -274,18 +261,6 @@ asm("svc 0" : : "r"(p0), "r"(p1)); } @@ -214,6 +237,3 @@ index e51621b..f96ccf8 100644 #ifdef CONFIG_TASK_PROFILING void task_start_irq_handler(void *excep_return) { --- -2.9.0 - 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