diff options
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0009-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0009-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0009-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch b/resources/libreboot/patch/kgpe-d16/0009-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch new file mode 100644 index 00000000..877d6b05 --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0009-northbridge-amd-amdmct-mct_ddr3-Fix-curly-brace-styl.patch @@ -0,0 +1,95 @@ +From 008cfb1a5e464a79af252b34086b1eb28d8b3420 Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Tue, 8 Sep 2015 16:08:45 -0500 +Subject: [PATCH 009/139] northbridge/amd/amdmct/mct_ddr3: Fix curly brace + style violations + +Change-Id: Ic27d404a7ed76b58043037e8b66097db6d664501 +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 37 ++++++++------------------- + 1 file changed, 10 insertions(+), 27 deletions(-) + +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +index c76476b..9f42d54 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +@@ -818,28 +818,19 @@ void setWLByteDelay(sDCTStruct *pDCTData, u8 ByteLane, u8 dimm, u8 targetAddr) + + tempB = 0; + offsetAddr = (u8)(3 * dimm); +- if (ByteLane < 2) +- { ++ if (ByteLane < 2) { + tempB = (u8)(16 * ByteLane); + addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_01; +- } +- else if (ByteLane <4) +- { ++ } else if (ByteLane <4) { + tempB = (u8)(16 * ByteLane); + addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_01 + 1; +- } +- else if (ByteLane <6) +- { ++ } else if (ByteLane <6) { + tempB = (u8)(16 * ByteLane); + addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_45; +- } +- else if (ByteLane <8) +- { ++ } else if (ByteLane <8) { + tempB = (u8)(16 * ByteLane); + addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_45 + 1; +- } +- else +- { ++ } else { + tempB = 0; + addr = DRAM_CONT_ADD_DQS_TIMING_CTRL_BL_01 + 2; + } +@@ -883,19 +874,14 @@ void getWLByteDelay(sDCTStruct *pDCTData, u8 ByteLane, u8 dimm) + u32 addr, fine, gross; + tempB = 0; + index = (u8)(MAX_BYTE_LANES*dimm); +- if (ByteLane < 4) +- { ++ if (ByteLane < 4) { + tempB = (u8)(8 * ByteLane); + addr = DRAM_CONT_ADD_PHASE_REC_CTRL_LOW; +- } +- else if (ByteLane < 8) +- { ++ } else if (ByteLane < 8) { + tempB1 = (u8)(ByteLane - 4); + tempB = (u8)(8 * tempB1); + addr = DRAM_CONT_ADD_PHASE_REC_CTRL_HIGH; +- } +- else +- { ++ } else { + tempB = 0; + addr = DRAM_CONT_ADD_ECC_PHASE_REC_CTRL; + } +@@ -911,16 +897,13 @@ void getWLByteDelay(sDCTStruct *pDCTData, u8 ByteLane, u8 dimm) + /* Adjust seed gross delay overflow (greater than 3): + * - Adjust the trained gross delay to the original seed gross delay. + */ +- if(pDCTData->WLGrossDelay[index+ByteLane] >= 3) +- { ++ if (pDCTData->WLGrossDelay[index+ByteLane] >= 3) { + gross += pDCTData->WLGrossDelay[index+ByteLane]; + if(pDCTData->WLGrossDelay[index+ByteLane] & 1) + gross -= 1; + else + gross -= 2; +- } +- else if((pDCTData->WLGrossDelay[index+ByteLane] == 0) && (gross == 3)) +- { ++ } else if ((pDCTData->WLGrossDelay[index+ByteLane] == 0) && (gross == 3)) { + /* If seed gross delay is 0 but PRE result gross delay is 3, it is negative. + * We will then round the negative number to 0. + */ +-- +1.9.1 + |