diff options
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0048-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0048-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch | 103 |
1 files changed, 0 insertions, 103 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0048-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch b/resources/libreboot/patch/kgpe-d16/0048-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch deleted file mode 100644 index a3de30df..00000000 --- a/resources/libreboot/patch/kgpe-d16/0048-northbridge-amd-amdmct-Skip-DCT-config-write-to-Flas.patch +++ /dev/null @@ -1,103 +0,0 @@ -From e513231d8e07299c740ef0cb8750816d5ac69998 Mon Sep 17 00:00:00 2001 -From: Timothy Pearson <tpearson@raptorengineeringinc.com> -Date: Mon, 8 Jun 2015 19:54:56 -0500 -Subject: [PATCH 048/143] northbridge/amd/amdmct: Skip DCT config write to - Flash if unchanged - -Change-Id: I5fee5f5fdf30ab6e3c4f94ed3e54ea66c1204352 -Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> ---- - src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 3 +++ - src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 1 + - src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 21 +++++++++++++++++++-- - 3 files changed, 23 insertions(+), 2 deletions(-) - -diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -index 4044c36..3edce9e 100644 ---- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c -@@ -1361,6 +1361,7 @@ restartinit: - #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) - printk(BIOS_DEBUG, "mctAutoInitMCT_D: Restoring DCT configuration from NVRAM\n"); - restore_mct_information_from_nvram(0); -+ pMCTstat->GStatus |= 1 << GSB_ConfigRestored; - #endif - - printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); -@@ -2087,6 +2088,8 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, - - if (is_fam15h()) - exit_training_mode_fam15(pMCTstat, pDCTstatA); -+ -+ pMCTstat->GStatus |= 1 << GSB_ConfigRestored; - } - - /* FIXME - currently uses calculated value TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */ -diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h -index 539ecc3..adf89b2 100644 ---- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h -+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h -@@ -316,6 +316,7 @@ struct MCTStatStruc { - #define GSB_SpIntRemapHole 16 /* Special condition for Node Interleave and HW remapping*/ - #define GSB_EnDIMMSpareNW 17 /* Indicates that DIMM Spare can be used without a warm reset */ - /* NOTE: This is a local bit used by memory code */ -+#define GSB_ConfigRestored 18 /* Training configuration was restored from NVRAM */ - - /*=============================================================================== - Local DCT Status structure (a structure for each DCT) -diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c -index 83c7b02..1e5c1a0 100644 ---- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c -+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c -@@ -213,7 +213,7 @@ static uint32_t read_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t d - return pci_read_config32(dev, reg); - } - --static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data) -+static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* persistent_data, uint8_t * restored) - { - uint8_t node; - uint8_t dimm; -@@ -236,6 +236,13 @@ static void copy_cbmem_spd_data_to_save_variable(struct amd_s3_persistent_data* - for (node = 0; node < MAX_NODES_SUPPORTED; node++) - for (channel = 0; channel < 2; channel++) - persistent_data->node[node].memclk[channel] = mem_info->dct_stat[node].Speed; -+ -+ if (restored) { -+ if (mem_info->mct_stat.GStatus & (1 << GSB_ConfigRestored)) -+ *restored = 1; -+ else -+ *restored = 0; -+ } - } - - void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_data) -@@ -1034,6 +1041,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste - int8_t save_mct_information_to_nvram(void) - { - uint8_t nvram; -+ uint8_t restored = 0; - - if (acpi_is_wakeup_s3()) - return 0; -@@ -1055,7 +1063,16 @@ int8_t save_mct_information_to_nvram(void) - copy_mct_data_to_save_variable(persistent_data); - - /* Save RAM SPD data at the same time */ -- copy_cbmem_spd_data_to_save_variable(persistent_data); -+ copy_cbmem_spd_data_to_save_variable(persistent_data, &restored); -+ -+ if (restored) { -+ /* Allow training bypass if DIMM configuration is unchanged on next boot */ -+ nvram = 1; -+ set_option("allow_spd_nvram_cache_restore", &nvram); -+ -+ printk(BIOS_DEBUG, "Hardware configuration unchanged since last boot; skipping write\n"); -+ return 0; -+ } - - /* Obtain CBFS file offset */ - s3nv_offset = get_s3nv_file_offset(); --- -1.7.9.5 - |