diff options
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Set-SkewMemClk-when-.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Set-SkewMemClk-when-.patch | 112 |
1 files changed, 112 insertions, 0 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Set-SkewMemClk-when-.patch b/resources/libreboot/patch/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Set-SkewMemClk-when-.patch new file mode 100644 index 00000000..5f3df4ae --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0080-northbridge-amd-amdmct-mct_ddr3-Set-SkewMemClk-when-.patch @@ -0,0 +1,112 @@ +From 171fd97470dab51d069dc434e3e99ef64a8c77bd Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <kb9vqf@pearsoncomputing.net> +Date: Fri, 26 Jun 2015 17:49:25 -0500 +Subject: [PATCH 080/146] northbridge/amd/amdmct/mct_ddr3: Set SkewMemClk when + both DCTs are in use + +--- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 41 +++++++++++++++++++++------ + src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 +- + 2 files changed, 34 insertions(+), 9 deletions(-) + +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +index 68ff3f8..98a6952 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +@@ -2636,7 +2636,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC + + /* Reset DCT registers */ + ClearDCT_D(pMCTstat, pDCTstat, dct); +- pDCTstat->stopDCT = 1; /*preload flag with 'disable' */ ++ pDCTstat->stopDCT[dct] = 1; /* preload flag with 'disable' */ + + if (!is_fam15h()) { + /* Enable DDR3 support */ +@@ -2647,7 +2647,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC + + /* Read the SPD information into the data structures */ + if (mct_DIMMPresence(pMCTstat, pDCTstat, dct) < SC_StopError) { +- printk(BIOS_DEBUG, "\t\tDCTInit_D: mct_DIMMPresence Done\n"); ++ printk(BIOS_DEBUG, "\t\tDCTPreInit_D: mct_DIMMPresence Done\n"); + } + } + +@@ -2673,17 +2673,40 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst + printk(BIOS_DEBUG, "\t\tDCTInit_D: AutoConfig_D Done\n"); + if (PlatformSpec_D(pMCTstat, pDCTstat, dct) < SC_StopError) { + printk(BIOS_DEBUG, "\t\tDCTInit_D: PlatformSpec_D Done\n"); +- pDCTstat->stopDCT = 0; +- if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW))) { +- printk(BIOS_DEBUG, "\t\tDCTInit_D: StartupDCT_D\n"); +- StartupDCT_D(pMCTstat, pDCTstat, dct); /*yeaahhh! */ +- } ++ pDCTstat->stopDCT[dct] = 0; + } + } + } + } + +- if (pDCTstat->stopDCT) { ++ ++} ++ ++static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) ++{ ++ uint32_t dword; ++ ++ /* Finalize DRAM init on a single node */ ++ if (is_fam15h()) { ++ /* Set memory clock skew if needed */ ++ if (dct == 0) { ++ if (!pDCTstat->stopDCT[0] && !pDCTstat->stopDCT[1]) { ++ dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, 0x98, 0x0d0fe00a); ++ dword |= (0x1 << 4); /* SkewMemClk = 1 */ ++ Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, 0x98, 0x0d0fe00a, dword); ++ } ++ } ++ } ++ ++ if (!pDCTstat->stopDCT[dct]) { ++ if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW))) { ++ printk(BIOS_DEBUG, "\t\tDCTFinalInit_D: StartupDCT_D Start\n"); ++ StartupDCT_D(pMCTstat, pDCTstat, dct); ++ printk(BIOS_DEBUG, "\t\tDCTFinalInit_D: StartupDCT_D Done\n"); ++ } ++ } ++ ++ if (pDCTstat->stopDCT[dct]) { + dword = 1 << DisDramInterface; + Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x94, dword); + +@@ -4337,6 +4360,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, + + /* Config. DCT0 for Ganged or unganged mode */ + DCTInit_D(pMCTstat, pDCTstat, 0); ++ DCTFinalInit_D(pMCTstat, pDCTstat, 0); + if (pDCTstat->ErrCode == SC_FatalErr) { + /* Do nothing goto exitDCTInit; any fatal errors? */ + } else { +@@ -4346,6 +4370,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, + err_code = pDCTstat->ErrCode; /* save DCT0 errors */ + pDCTstat->ErrCode = 0; + DCTInit_D(pMCTstat, pDCTstat, 1); ++ DCTFinalInit_D(pMCTstat, pDCTstat, 1); + if (pDCTstat->ErrCode == 2) /* DCT1 is not Running */ + pDCTstat->ErrCode = err_code; /* Using DCT0 Error code to update pDCTstat.ErrCode */ + } else { +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +index 8c9da47..7bc392b 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +@@ -338,7 +338,7 @@ struct DCTStatStruc { /* A per Node structure*/ + u8 Node_ID; /* Node ID of current controller */ + uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ + uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */ +- uint8_t stopDCT; /* Set if the DCT will be stopped */ ++ uint8_t stopDCT[2]; /* Set if the DCT will be stopped */ + u8 ErrCode; /* Current error condition of Node + 0= no error + 1= Variance Error, DCT is running but not in an optimal configuration. +-- +1.7.9.5 + |