diff options
Diffstat (limited to 'resources/libreboot')
201 files changed, 26560 insertions, 0 deletions
diff --git a/resources/libreboot/config/grub/d510mo/architecture b/resources/libreboot/config/grub/d510mo/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/d510mo/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/d510mo/cbrevision b/resources/libreboot/config/grub/d510mo/cbrevision new file mode 100644 index 00000000..1ab8299e --- /dev/null +++ b/resources/libreboot/config/grub/d510mo/cbrevision @@ -0,0 +1 @@ +2a3434757ef425dbdfedf1fc69e1a033a6e7310d diff --git a/resources/libreboot/config/grub/d510mo/config b/resources/libreboot/config/grub/d510mo/config new file mode 100644 index 00000000..ebe6636b --- /dev/null +++ b/resources/libreboot/config/grub/d510mo/config @@ -0,0 +1,521 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +# CONFIG_COMPRESS_PRERAM_STAGES is not set +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_EARLY_CBMEM_INIT is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +CONFIG_FLASHMAP_OFFSET=0 +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_ACPI_SATA_GENERATOR is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +CONFIG_VENDOR_INTEL=y +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="intel/d510mo" +CONFIG_MAINBOARD_PART_NUMBER="D510MO" +CONFIG_MAINBOARD_VENDOR="Intel" +CONFIG_MAX_CPUS=4 +CONFIG_VGA_BIOS_ID="8086,a001" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +# CONFIG_UDELAY_IO is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_DCACHE_RAM_BASE=0xffafc000 +CONFIG_DCACHE_RAM_SIZE=0x4000 +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel" +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_RAMTOP=0x200000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x100000 +CONFIG_POST_DEVICE=y +# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set +# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set +# CONFIG_BOARD_INTEL_BAKERSPORT_FSP is not set +# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set +# CONFIG_BOARD_INTEL_BAYLEYBAY_FSP is not set +# CONFIG_BOARD_INTEL_COUGAR_CANYON2 is not set +CONFIG_BOARD_INTEL_D510MO=y +# CONFIG_BOARD_INTEL_D810E2CB is not set +# CONFIG_BOARD_INTEL_D945GCLF is not set +# CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set +# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set +# CONFIG_BOARD_INTEL_GALILEO is not set +# CONFIG_BOARD_INTEL_KUNIMITSU is not set +# CONFIG_BOARD_INTEL_LITTLEPLAINS is not set +# CONFIG_BOARD_INTEL_MINNOWMAX is not set +# CONFIG_BOARD_INTEL_MOHONPEAK is not set +# CONFIG_BOARD_INTEL_MTARVON is not set +# CONFIG_BOARD_INTEL_STARGO2 is not set +# CONFIG_BOARD_INTEL_STRAGO is not set +# CONFIG_BOARD_INTEL_TRUXTON is not set +# CONFIG_BOARD_INTEL_WTM2 is not set +CONFIG_CPU_ADDR_BITS=32 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_1024=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +CONFIG_COREBOOT_ROMSIZE_KB_1024=y +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=1024 +CONFIG_ROM_SIZE=0x100000 +CONFIG_FMDFILE="" +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/pineview/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_HEAP_SIZE=0x4000 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_106CX=y +CONFIG_CPU_INTEL_SOCKET_FCBGA559=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +CONFIG_SERIALIZED_SMM_INITIALIZATION=y +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y + +# +# Super I/O +# +CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE=y +CONFIG_SUPERIO_WINBOND_W83627THG=y + +# +# Embedded Controllers +# +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +CONFIG_AP_IN_SIPI_WAIT=y +CONFIG_SIPI_VECTOR_IN_ROM=y +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +# CONFIG_ROMCC is not set +CONFIG_LATE_CBMEM_INIT=y +CONFIG_PC80_SYSTEM=y +# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_COMPILE_IN_DSDT is not set +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_PXE_ROM is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_RTC=y +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +# CONFIG_HAVE_ACPI_RESUME is not set +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +# CONFIG_HAVE_OPTION_TABLE is not set +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_DEBUG_BOOT_STATE is not set diff --git a/resources/libreboot/config/grub/d510mo/vbootrevision b/resources/libreboot/config/grub/d510mo/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/d510mo/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/ga-g41m-es2l/architecture b/resources/libreboot/config/grub/ga-g41m-es2l/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/ga-g41m-es2l/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision b/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision new file mode 100644 index 00000000..4f7158f6 --- /dev/null +++ b/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision @@ -0,0 +1 @@ +55a54f662e2e793306dc7003afbcb82b49db0a8c diff --git a/resources/libreboot/config/grub/ga-g41m-es2l/config b/resources/libreboot/config/grub/ga-g41m-es2l/config new file mode 100644 index 00000000..ec4790da --- /dev/null +++ b/resources/libreboot/config/grub/ga-g41m-es2l/config @@ -0,0 +1,544 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +CONFIG_VENDOR_GIGABYTE=y +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="gigabyte/ga-g41m-es2l" +CONFIG_MAINBOARD_PART_NUMBER="GA-G41M-ES2L" +CONFIG_MAINBOARD_VENDOR="GIGABYTE" +CONFIG_MAX_CPUS=1 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x100000 +CONFIG_VGA_BIOS_ID="8086,2e32" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_DCACHE_RAM_BASE=0xfeffc000 +CONFIG_DCACHE_RAM_SIZE=0x4000 +CONFIG_MMCONF_BASE_ADDRESS=0xe0000000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="GIGABYTE" +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +# CONFIG_BOARD_GIGABYTE_GA_6BXC is not set +# CONFIG_BOARD_GIGABYTE_GA_6BXE is not set +# CONFIG_BOARD_GIGABYTE_GA_B75M_D3H is not set +# CONFIG_BOARD_GIGABYTE_GA_B75M_D3V is not set +CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y +# CONFIG_BOARD_GIGABYTE_GA_2761GXDK is not set +# CONFIG_BOARD_GIGABYTE_M57SLI is not set +# CONFIG_BOARD_GIGABYTE_MA785GM is not set +# CONFIG_BOARD_GIGABYTE_MA785GMT is not set +# CONFIG_BOARD_GIGABYTE_MA78GM is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_1024=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +CONFIG_COREBOOT_ROMSIZE_KB_1024=y +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=1024 +CONFIG_ROM_SIZE=0x100000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/x4x/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_MODEL_F3X=y +CONFIG_CPU_INTEL_MODEL_F4X=y +CONFIG_SSE2=y +CONFIG_CPU_INTEL_SOCKET_LGA775=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +# CONFIG_LAPIC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_X4X=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y + +# +# Super I/O +# +CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE=y +CONFIG_SUPERIO_ITE_IT8718F=y + +# +# Embedded Controllers +# +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +CONFIG_AP_IN_SIPI_WAIT=y +CONFIG_SIPI_VECTOR_IN_ROM=y +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set +# CONFIG_ON_DEVICE_ROM_LOAD is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_CLK_PM=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +CONFIG_REALTEK_8168_RESET=y +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +# CONFIG_INTEL_INT15 is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +# CONFIG_HAVE_ACPI_RESUME is not set +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +# CONFIG_HAVE_OPTION_TABLE is not set +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_COMMON_FADT=y +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="GA-G41M-ES2L" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/ga-g41m-es2l/vbootrevision b/resources/libreboot/config/grub/ga-g41m-es2l/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/ga-g41m-es2l/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/kcma-d8/architecture b/resources/libreboot/config/grub/kcma-d8/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/kcma-d8/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/kcma-d8/cbrevision b/resources/libreboot/config/grub/kcma-d8/cbrevision new file mode 100644 index 00000000..a4c248f2 --- /dev/null +++ b/resources/libreboot/config/grub/kcma-d8/cbrevision @@ -0,0 +1 @@ +eee0e229764e965996479d7eb07e6086176b8bf0 diff --git a/resources/libreboot/config/grub/kcma-d8/config b/resources/libreboot/config/grub/kcma-d8/config new file mode 100644 index 00000000..ec7c745b --- /dev/null +++ b/resources/libreboot/config/grub/kcma-d8/config @@ -0,0 +1,602 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +CONFIG_FLASHMAP_OFFSET=0 +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_ACPI_SATA_GENERATOR is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +CONFIG_VENDOR_ASUS=y +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="asus/kcma-d8" +CONFIG_MAINBOARD_PART_NUMBER="KCMA-D8" +CONFIG_IRQ_SLOT_COUNT=13 +CONFIG_MAINBOARD_VENDOR="ASUS" +CONFIG_APIC_ID_OFFSET=0 +CONFIG_HW_MEM_HOLE_SIZEK=0x100000 +CONFIG_MAX_CPUS=16 +CONFIG_MAX_PHYSICAL_CPUS=2 +# CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC is not set +CONFIG_HT_CHAIN_END_UNITID_BASE=0x20 +CONFIG_HT_CHAIN_UNITID_BASE=0x0 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_DCACHE_RAM_BASE=0xc2000 +CONFIG_DCACHE_RAM_SIZE=0x1e000 +CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" +# CONFIG_BOARD_ASUS_A8N_E is not set +# CONFIG_BOARD_ASUS_A8N_SLI is not set +# CONFIG_BOARD_ASUS_A8V_E_DELUXE is not set +# CONFIG_BOARD_ASUS_A8V_E_SE is not set +# CONFIG_BOARD_ASUS_DSBF is not set +# CONFIG_BOARD_ASUS_F2A85_M is not set +# CONFIG_BOARD_ASUS_F2A85_M_LE is not set +# CONFIG_BOARD_ASUS_K8V_X is not set +CONFIG_BOARD_ASUS_KCMA_D8=y +# CONFIG_BOARD_ASUS_KFSN4_DRE is not set +# CONFIG_BOARD_ASUS_KFSN4_DRE_K8 is not set +# CONFIG_BOARD_ASUS_KGPE_D16 is not set +# CONFIG_BOARD_ASUS_M2N_E is not set +# CONFIG_BOARD_ASUS_M2V_MX_SE is not set +# CONFIG_BOARD_ASUS_M2V is not set +# CONFIG_BOARD_ASUS_M4A78_EM is not set +# CONFIG_BOARD_ASUS_M4A785M is not set +# CONFIG_BOARD_ASUS_M4A785TM is not set +# CONFIG_BOARD_ASUS_M5A88_V is not set +# CONFIG_BOARD_ASUS_MEW_AM is not set +# CONFIG_BOARD_ASUS_MEW_VM is not set +# CONFIG_BOARD_ASUS_P2B_D is not set +# CONFIG_BOARD_ASUS_P2B_DS is not set +# CONFIG_BOARD_ASUS_P2B_F is not set +# CONFIG_BOARD_ASUS_P2B_LS is not set +# CONFIG_BOARD_ASUS_P2B is not set +# CONFIG_BOARD_ASUS_P3B_F is not set +# CONFIG_POST_IO is not set +CONFIG_AGP_APERTURE_SIZE=0x4000000 +CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/asus/kcma-d8/bootblock.c" +CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD=0x3f +CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL=y +CONFIG_MAX_REBOOT_CNT=10 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_RAMTOP=0x400000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x200000 +# CONFIG_POST_DEVICE is not set +CONFIG_BOOT_MEDIA_SPI_BUS=0 +CONFIG_CONSOLE_POST=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_CPU_ADDR_BITS=48 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_FMDFILE="" +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/amd/amdfam10/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/sb700/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_HEAP_SIZE=0xc0000 +CONFIG_CONSOLE_CBMEM=y +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_DCACHE_BSP_STACK_SLUSH=0x4000 +CONFIG_DCACHE_AP_STACK_SIZE=0x500 +CONFIG_CPU_SOCKET_TYPE=0x14 +# CONFIG_EXT_RT_TBL_SUPPORT is not set +CONFIG_CBB=0x0 +CONFIG_CDB=0x18 +CONFIG_XIP_ROM_SIZE=0x80000 +CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA=y +CONFIG_DIMM_SUPPORT=0x0005 +CONFIG_LIFT_BSP_APIC_ID=y +CONFIG_SET_FIDVID=y +CONFIG_SET_FIDVID_DEBUG=y +# CONFIG_SET_FIDVID_CORE0_ONLY is not set +CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST=y +CONFIG_CPU_AMD_MODEL_10XXX=y +CONFIG_USE_LARGE_DCACHE=y +CONFIG_NUM_IPI_STARTS=1 +CONFIG_SET_FIDVID_CORE_RANGE=0 +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_S3_DATA_POS=0x0 +CONFIG_S3_DATA_SIZE=32768 +# CONFIG_CPU_AMD_PI is not set +# CONFIG_EXT_CONF_SUPPORT is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +CONFIG_PARALLEL_CPU_INIT=y +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +# CONFIG_LAPIC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +CONFIG_TSC_SYNC_LFENCE=y +# CONFIG_TSC_SYNC_MFENCE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +CONFIG_X86_AMD_FIXED_MTRRS=y +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +CONFIG_MMCONF_BUS_NUMBER=256 +CONFIG_NORTHBRIDGE_AMD_AMDFAM10=y +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=y +# CONFIG_HT_CHAIN_DISTRIBUTE is not set +# CONFIG_DIMM_FBDIMM is not set +# CONFIG_DIMM_DDR2 is not set +CONFIG_DIMM_DDR3=y +CONFIG_DIMM_REGISTERED=y +CONFIG_DIMM_VOLTAGE_SET_SUPPORT=y +# CONFIG_SVI_HIGH_FREQ is not set + +# +# HyperTransport setup +# +# CONFIG_LIMIT_HT_DOWN_WIDTH_8 is not set +CONFIG_LIMIT_HT_DOWN_WIDTH_16=y +# CONFIG_LIMIT_HT_UP_WIDTH_8 is not set +CONFIG_LIMIT_HT_UP_WIDTH_16=y +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_HPET_MIN_TICKS=0x14 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_AMD_SB700=y +CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100=y +# CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT is not set +CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA=y +CONFIG_SOUTHBRIDGE_AMD_SR5650=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set + +# +# Super I/O +# +CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE=y +CONFIG_SUPERIO_WINBOND_W83667HG_A=y + +# +# Embedded Controllers +# +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_POSTCAR_STAGE is not set + +# +# Devices +# +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +# CONFIG_VGA_ROM_RUN is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +CONFIG_SMBUS_HAS_AUX_CHANNELS=y +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_CLK_PM=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_ATOMIC_SEQUENCING=y +CONFIG_SPI_FLASH_MEMORY_MAPPED=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_DRIVERS_ASPEED_AST2050=y +CONFIG_DEVICE_SPECIFIC_OPTIONS=y +CONFIG_DRIVERS_ASPEED_AST_COMMON=y +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_I2C_W83795=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y +CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y +CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +# CONFIG_HAVE_SMI_HANDLER is not set +CONFIG_PCI_IO_CFG_EXT=y +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KCMA-D8" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_CAR=y +# CONFIG_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +CONFIG_ENABLE_APIC_EXT_ID=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_DEBUG_BOOT_STATE is not set diff --git a/resources/libreboot/config/grub/kcma-d8/vbootrevision b/resources/libreboot/config/grub/kcma-d8/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/kcma-d8/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/kgpe-d16/architecture b/resources/libreboot/config/grub/kgpe-d16/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/kgpe-d16/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/kgpe-d16/cbrevision b/resources/libreboot/config/grub/kgpe-d16/cbrevision new file mode 100644 index 00000000..a4c248f2 --- /dev/null +++ b/resources/libreboot/config/grub/kgpe-d16/cbrevision @@ -0,0 +1 @@ +eee0e229764e965996479d7eb07e6086176b8bf0 diff --git a/resources/libreboot/config/grub/kgpe-d16/config b/resources/libreboot/config/grub/kgpe-d16/config new file mode 100644 index 00000000..3a847cbc --- /dev/null +++ b/resources/libreboot/config/grub/kgpe-d16/config @@ -0,0 +1,602 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +CONFIG_FLASHMAP_OFFSET=0 +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_ACPI_SATA_GENERATOR is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +CONFIG_VENDOR_ASUS=y +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="asus/kgpe-d16" +CONFIG_MAINBOARD_PART_NUMBER="KGPE-D16" +CONFIG_IRQ_SLOT_COUNT=13 +CONFIG_MAINBOARD_VENDOR="ASUS" +CONFIG_APIC_ID_OFFSET=0 +CONFIG_HW_MEM_HOLE_SIZEK=0x100000 +CONFIG_MAX_CPUS=32 +CONFIG_MAX_PHYSICAL_CPUS=4 +# CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC is not set +CONFIG_HT_CHAIN_END_UNITID_BASE=0x20 +CONFIG_HT_CHAIN_UNITID_BASE=0x0 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_DCACHE_RAM_BASE=0xc2000 +CONFIG_DCACHE_RAM_SIZE=0x1e000 +CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" +# CONFIG_BOARD_ASUS_A8N_E is not set +# CONFIG_BOARD_ASUS_A8N_SLI is not set +# CONFIG_BOARD_ASUS_A8V_E_DELUXE is not set +# CONFIG_BOARD_ASUS_A8V_E_SE is not set +# CONFIG_BOARD_ASUS_DSBF is not set +# CONFIG_BOARD_ASUS_F2A85_M is not set +# CONFIG_BOARD_ASUS_F2A85_M_LE is not set +# CONFIG_BOARD_ASUS_K8V_X is not set +# CONFIG_BOARD_ASUS_KCMA_D8 is not set +# CONFIG_BOARD_ASUS_KFSN4_DRE is not set +# CONFIG_BOARD_ASUS_KFSN4_DRE_K8 is not set +CONFIG_BOARD_ASUS_KGPE_D16=y +# CONFIG_BOARD_ASUS_M2N_E is not set +# CONFIG_BOARD_ASUS_M2V_MX_SE is not set +# CONFIG_BOARD_ASUS_M2V is not set +# CONFIG_BOARD_ASUS_M4A78_EM is not set +# CONFIG_BOARD_ASUS_M4A785M is not set +# CONFIG_BOARD_ASUS_M4A785TM is not set +# CONFIG_BOARD_ASUS_M5A88_V is not set +# CONFIG_BOARD_ASUS_MEW_AM is not set +# CONFIG_BOARD_ASUS_MEW_VM is not set +# CONFIG_BOARD_ASUS_P2B_D is not set +# CONFIG_BOARD_ASUS_P2B_DS is not set +# CONFIG_BOARD_ASUS_P2B_F is not set +# CONFIG_BOARD_ASUS_P2B_LS is not set +# CONFIG_BOARD_ASUS_P2B is not set +# CONFIG_BOARD_ASUS_P3B_F is not set +# CONFIG_POST_IO is not set +CONFIG_AGP_APERTURE_SIZE=0x4000000 +CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/asus/kgpe-d16/bootblock.c" +CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD=0x3f +CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL=y +CONFIG_MAX_REBOOT_CNT=10 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_RAMTOP=0x400000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x200000 +# CONFIG_POST_DEVICE is not set +CONFIG_BOOT_MEDIA_SPI_BUS=0 +CONFIG_CONSOLE_POST=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_CPU_ADDR_BITS=48 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_FMDFILE="" +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/amd/amdfam10/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/sb700/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_HEAP_SIZE=0xc0000 +CONFIG_CONSOLE_CBMEM=y +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_DCACHE_BSP_STACK_SLUSH=0x4000 +CONFIG_DCACHE_AP_STACK_SIZE=0x500 +CONFIG_CPU_SOCKET_TYPE=0x15 +# CONFIG_EXT_RT_TBL_SUPPORT is not set +CONFIG_CBB=0x0 +CONFIG_CDB=0x18 +CONFIG_XIP_ROM_SIZE=0x80000 +CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA=y +CONFIG_DIMM_SUPPORT=0x0005 +CONFIG_LIFT_BSP_APIC_ID=y +CONFIG_SET_FIDVID=y +CONFIG_SET_FIDVID_DEBUG=y +# CONFIG_SET_FIDVID_CORE0_ONLY is not set +CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST=y +CONFIG_CPU_AMD_MODEL_10XXX=y +CONFIG_USE_LARGE_DCACHE=y +CONFIG_NUM_IPI_STARTS=1 +CONFIG_SET_FIDVID_CORE_RANGE=0 +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_S3_DATA_POS=0x0 +CONFIG_S3_DATA_SIZE=32768 +# CONFIG_CPU_AMD_PI is not set +CONFIG_EXT_CONF_SUPPORT=y +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +CONFIG_PARALLEL_CPU_INIT=y +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +# CONFIG_LAPIC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +CONFIG_TSC_SYNC_LFENCE=y +# CONFIG_TSC_SYNC_MFENCE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +CONFIG_X86_AMD_FIXED_MTRRS=y +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +CONFIG_MMCONF_BUS_NUMBER=256 +CONFIG_NORTHBRIDGE_AMD_AMDFAM10=y +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=y +# CONFIG_HT_CHAIN_DISTRIBUTE is not set +# CONFIG_DIMM_FBDIMM is not set +# CONFIG_DIMM_DDR2 is not set +CONFIG_DIMM_DDR3=y +CONFIG_DIMM_REGISTERED=y +CONFIG_DIMM_VOLTAGE_SET_SUPPORT=y +# CONFIG_SVI_HIGH_FREQ is not set + +# +# HyperTransport setup +# +# CONFIG_LIMIT_HT_DOWN_WIDTH_8 is not set +CONFIG_LIMIT_HT_DOWN_WIDTH_16=y +# CONFIG_LIMIT_HT_UP_WIDTH_8 is not set +CONFIG_LIMIT_HT_UP_WIDTH_16=y +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_HPET_MIN_TICKS=0x14 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_AMD_SB700=y +CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100=y +# CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT is not set +CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA=y +CONFIG_SOUTHBRIDGE_AMD_SR5650=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set + +# +# Super I/O +# +CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE=y +CONFIG_SUPERIO_WINBOND_W83667HG_A=y + +# +# Embedded Controllers +# +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_POSTCAR_STAGE is not set + +# +# Devices +# +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +# CONFIG_VGA_ROM_RUN is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +CONFIG_SMBUS_HAS_AUX_CHANNELS=y +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_CLK_PM=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_ATOMIC_SEQUENCING=y +CONFIG_SPI_FLASH_MEMORY_MAPPED=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_DRIVERS_ASPEED_AST2050=y +CONFIG_DEVICE_SPECIFIC_OPTIONS=y +CONFIG_DRIVERS_ASPEED_AST_COMMON=y +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_I2C_W83795=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y +CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y +CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +# CONFIG_HAVE_SMI_HANDLER is not set +CONFIG_PCI_IO_CFG_EXT=y +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KGPE-D16" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_CAR=y +# CONFIG_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +CONFIG_ENABLE_APIC_EXT_ID=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_DEBUG_BOOT_STATE is not set diff --git a/resources/libreboot/config/grub/kgpe-d16/vbootrevision b/resources/libreboot/config/grub/kgpe-d16/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/kgpe-d16/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/macbook21/architecture b/resources/libreboot/config/grub/macbook21/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/macbook21/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/macbook21/cbrevision b/resources/libreboot/config/grub/macbook21/cbrevision new file mode 100644 index 00000000..1ab8299e --- /dev/null +++ b/resources/libreboot/config/grub/macbook21/cbrevision @@ -0,0 +1 @@ +2a3434757ef425dbdfedf1fc69e1a033a6e7310d diff --git a/resources/libreboot/config/grub/macbook21/config b/resources/libreboot/config/grub/macbook21/config new file mode 100644 index 00000000..84db8770 --- /dev/null +++ b/resources/libreboot/config/grub/macbook21/config @@ -0,0 +1,524 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION=" MB21.88Z.00A5.B07.0706270922" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +# CONFIG_COMPRESS_PRERAM_STAGES is not set +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +CONFIG_FLASHMAP_OFFSET=0x0 +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_ACPI_SATA_GENERATOR is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +CONFIG_VENDOR_APPLE=y +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="apple/macbook21" +CONFIG_MAINBOARD_PART_NUMBER="MacBook2,1" +CONFIG_MAINBOARD_VENDOR="Apple" +CONFIG_MAX_CPUS=2 +CONFIG_VGA_BIOS_ID="8086,27a2" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +# CONFIG_UDELAY_IO is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="W8724XXXXXX" +CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +# CONFIG_BOARD_APPLE_MACBOOK11 is not set +CONFIG_BOARD_APPLE_MACBOOK21=y +# CONFIG_BOARD_APPLE_MACBOOKAIR4_2 is not set +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Apple Inc." +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_RAMTOP=0x200000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x200000 +CONFIG_POST_DEVICE=y +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_POST is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_FMDFILE="" +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_HEAP_SIZE=0x4000 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set +# CONFIG_VRAM_SIZE_1MB is not set +# CONFIG_VRAM_SIZE_4MB is not set +# CONFIG_VRAM_SIZE_8MB is not set +# CONFIG_VRAM_SIZE_16MB is not set +# CONFIG_VRAM_SIZE_32MB is not set +# CONFIG_VRAM_SIZE_48MB is not set +CONFIG_VRAM_SIZE_64MB=y +CONFIG_VRAM_SIZE=0x70 +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +CONFIG_AP_IN_SIPI_WAIT=y +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_COMPILE_IN_DSDT is not set +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_PXE_ROM is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_RTC=y +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_COMMON_FADT=y +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_DEBUG_BOOT_STATE is not set diff --git a/resources/libreboot/config/grub/macbook21/vbootrevision b/resources/libreboot/config/grub/macbook21/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/macbook21/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/qemu_i440fx_piix4/architecture b/resources/libreboot/config/grub/qemu_i440fx_piix4/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/qemu_i440fx_piix4/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/qemu_i440fx_piix4/cbrevision b/resources/libreboot/config/grub/qemu_i440fx_piix4/cbrevision new file mode 100644 index 00000000..1ab8299e --- /dev/null +++ b/resources/libreboot/config/grub/qemu_i440fx_piix4/cbrevision @@ -0,0 +1 @@ +2a3434757ef425dbdfedf1fc69e1a033a6e7310d diff --git a/resources/libreboot/config/grub/qemu_i440fx_piix4/config b/resources/libreboot/config/grub/qemu_i440fx_piix4/config new file mode 100644 index 00000000..cdef35a8 --- /dev/null +++ b/resources/libreboot/config/grub/qemu_i440fx_piix4/config @@ -0,0 +1,498 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +# CONFIG_COMPRESS_PRERAM_STAGES is not set +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +CONFIG_FLASHMAP_OFFSET=0x0 +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_ACPI_SATA_GENERATOR is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +CONFIG_VENDOR_EMULATION=y +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="emulation/qemu-i440fx" +CONFIG_MAINBOARD_PART_NUMBER="QEMU x86 i440fx/piix4" +CONFIG_IRQ_SLOT_COUNT=6 +CONFIG_MAINBOARD_VENDOR="Emulation" +CONFIG_MAX_CPUS=1 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_UDELAY_IO=y +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_DCACHE_RAM_BASE=0xd0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Emulation" +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set +CONFIG_BOARD_EMULATION_QEMU_X86_I440FX=y +# CONFIG_BOARD_EMULATION_QEMU_POWER8 is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_Q35 is not set +# CONFIG_BOARD_EMULATION_QEMU_UCB_RISCV is not set +# CONFIG_BOARD_EMULATION_SPIKE_UCB_RISCV is not set +CONFIG_BOARD_EMULATION_QEMU_X86=y +CONFIG_RAMTOP=0x200000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x800000 +CONFIG_POST_DEVICE=y +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_256=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_FMDFILE="" +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82371eb/bootblock.c" +CONFIG_HEAP_SIZE=0x4000 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_SSE2 is not set +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_QEMU_X86=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_UDELAY_LAPIC is not set +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +# CONFIG_TSC_SYNC_MFENCE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82371EB=y + +# +# Super I/O +# + +# +# Embedded Controllers +# +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_COMPILE_IN_DSDT is not set +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_PXE_ROM is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +CONFIG_DRIVERS_EMULATION_QEMU_BOCHS=y +CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES=800 +CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES=600 +# CONFIG_GIC is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_HAVE_USBDEBUG is not set +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_RTC=y +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +# CONFIG_MMCONF_SUPPORT_DEFAULT is not set +# CONFIG_MMCONF_SUPPORT is not set +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_CONSOLE_QEMU_DEBUGCON=y +CONFIG_CONSOLE_QEMU_DEBUGCON_PORT=0x402 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +# CONFIG_HAVE_ACPI_RESUME is not set +# CONFIG_HAVE_HARD_RESET is not set +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +# CONFIG_HAVE_SMI_HANDLER is not set +# CONFIG_PCI_IO_CFG_EXT is not set +# CONFIG_IOAPIC is not set +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_PIRQ_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="QEMU x86 i440fx/piix4" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_DEBUG_BOOT_STATE is not set diff --git a/resources/libreboot/config/grub/qemu_i440fx_piix4/vbootrevision b/resources/libreboot/config/grub/qemu_i440fx_piix4/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/qemu_i440fx_piix4/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/qemu_q35_ich9/architecture b/resources/libreboot/config/grub/qemu_q35_ich9/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/qemu_q35_ich9/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/qemu_q35_ich9/cbrevision b/resources/libreboot/config/grub/qemu_q35_ich9/cbrevision new file mode 100644 index 00000000..1ab8299e --- /dev/null +++ b/resources/libreboot/config/grub/qemu_q35_ich9/cbrevision @@ -0,0 +1 @@ +2a3434757ef425dbdfedf1fc69e1a033a6e7310d diff --git a/resources/libreboot/config/grub/qemu_q35_ich9/config b/resources/libreboot/config/grub/qemu_q35_ich9/config new file mode 100644 index 00000000..6896e432 --- /dev/null +++ b/resources/libreboot/config/grub/qemu_q35_ich9/config @@ -0,0 +1,500 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +# CONFIG_COMPRESS_PRERAM_STAGES is not set +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +CONFIG_FLASHMAP_OFFSET=0x0 +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_ACPI_SATA_GENERATOR is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +CONFIG_VENDOR_EMULATION=y +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="emulation/qemu-q35" +CONFIG_MAINBOARD_PART_NUMBER="QEMU x86 q35/ich9" +CONFIG_MAINBOARD_VENDOR="Emulation" +CONFIG_MAX_CPUS=1 +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_UDELAY_IO=y +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_DCACHE_RAM_BASE=0xd0000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_MMCONF_BASE_ADDRESS=0xb0000000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Emulation" +CONFIG_POST_IO=y +CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/emulation/qemu-q35/bootblock.c" +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set +# CONFIG_BOARD_EMULATION_QEMU_POWER8 is not set +CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y +# CONFIG_BOARD_EMULATION_QEMU_UCB_RISCV is not set +# CONFIG_BOARD_EMULATION_SPIKE_UCB_RISCV is not set +CONFIG_BOARD_EMULATION_QEMU_X86=y +CONFIG_RAMTOP=0x200000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x800000 +CONFIG_POST_DEVICE=y +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_256=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_FMDFILE="" +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_HEAP_SIZE=0x4000 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_SSE2 is not set +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +CONFIG_CPU_QEMU_X86=y +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_UDELAY_LAPIC is not set +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +# CONFIG_TSC_SYNC_MFENCE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# + +# +# Embedded Controllers +# +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS=y +# CONFIG_COMPILE_IN_DSDT is not set +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_PXE_ROM is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +CONFIG_DRIVERS_EMULATION_QEMU_BOCHS=y +CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_XRES=800 +CONFIG_DRIVERS_EMULATION_QEMU_BOCHS_YRES=600 +# CONFIG_GIC is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_RTC=y +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_CONSOLE_QEMU_DEBUGCON=y +CONFIG_CONSOLE_QEMU_DEBUGCON_PORT=0x402 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +# CONFIG_HAVE_ACPI_RESUME is not set +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +# CONFIG_HAVE_OPTION_TABLE is not set +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +# CONFIG_GENERATE_MP_TABLE is not set +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="QEMU x86 q35/ich9" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_DEBUG_BOOT_STATE is not set diff --git a/resources/libreboot/config/grub/qemu_q35_ich9/vbootrevision b/resources/libreboot/config/grub/qemu_q35_ich9/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/qemu_q35_ich9/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/r400_16mb/architecture b/resources/libreboot/config/grub/r400_16mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/r400_16mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/r400_16mb/cbrevision b/resources/libreboot/config/grub/r400_16mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/r400_16mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/r400_16mb/config b/resources/libreboot/config/grub/r400_16mb/config new file mode 100644 index 00000000..99ba52bf --- /dev/null +++ b/resources/libreboot/config/grub/r400_16mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad R400" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0xFFD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +CONFIG_BOARD_LENOVO_R400=y +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/r400_16mb/vbootrevision b/resources/libreboot/config/grub/r400_16mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/r400_16mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/r400_4mb/architecture b/resources/libreboot/config/grub/r400_4mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/r400_4mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/r400_4mb/cbrevision b/resources/libreboot/config/grub/r400_4mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/r400_4mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/r400_4mb/config b/resources/libreboot/config/grub/r400_4mb/config new file mode 100644 index 00000000..14462e59 --- /dev/null +++ b/resources/libreboot/config/grub/r400_4mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad R400" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x3FD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +CONFIG_BOARD_LENOVO_R400=y +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/r400_4mb/vbootrevision b/resources/libreboot/config/grub/r400_4mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/r400_4mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/r400_8mb/architecture b/resources/libreboot/config/grub/r400_8mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/r400_8mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/r400_8mb/cbrevision b/resources/libreboot/config/grub/r400_8mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/r400_8mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/r400_8mb/config b/resources/libreboot/config/grub/r400_8mb/config new file mode 100644 index 00000000..cc9561ea --- /dev/null +++ b/resources/libreboot/config/grub/r400_8mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad R400" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x7FD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +CONFIG_BOARD_LENOVO_R400=y +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/r400_8mb/vbootrevision b/resources/libreboot/config/grub/r400_8mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/r400_8mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/t400_16mb/architecture b/resources/libreboot/config/grub/t400_16mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/t400_16mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/t400_16mb/cbrevision b/resources/libreboot/config/grub/t400_16mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/t400_16mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/t400_16mb/config b/resources/libreboot/config/grub/t400_16mb/config new file mode 100644 index 00000000..30e4cc15 --- /dev/null +++ b/resources/libreboot/config/grub/t400_16mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T400" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0xFFD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +CONFIG_BOARD_LENOVO_T400=y +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/t400_16mb/vbootrevision b/resources/libreboot/config/grub/t400_16mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/t400_16mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/t400_4mb/architecture b/resources/libreboot/config/grub/t400_4mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/t400_4mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/t400_4mb/cbrevision b/resources/libreboot/config/grub/t400_4mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/t400_4mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/t400_4mb/config b/resources/libreboot/config/grub/t400_4mb/config new file mode 100644 index 00000000..0517f1e7 --- /dev/null +++ b/resources/libreboot/config/grub/t400_4mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T400" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x3FD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +CONFIG_BOARD_LENOVO_T400=y +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/t400_4mb/vbootrevision b/resources/libreboot/config/grub/t400_4mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/t400_4mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/t400_8mb/architecture b/resources/libreboot/config/grub/t400_8mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/t400_8mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/t400_8mb/cbrevision b/resources/libreboot/config/grub/t400_8mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/t400_8mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/t400_8mb/config b/resources/libreboot/config/grub/t400_8mb/config new file mode 100644 index 00000000..be9f61cf --- /dev/null +++ b/resources/libreboot/config/grub/t400_8mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T400" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x7FD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +CONFIG_BOARD_LENOVO_T400=y +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/t400_8mb/vbootrevision b/resources/libreboot/config/grub/t400_8mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/t400_8mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/t500_16mb/architecture b/resources/libreboot/config/grub/t500_16mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/t500_16mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/t500_16mb/cbrevision b/resources/libreboot/config/grub/t500_16mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/t500_16mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/t500_16mb/config b/resources/libreboot/config/grub/t500_16mb/config new file mode 100644 index 00000000..c7227761 --- /dev/null +++ b/resources/libreboot/config/grub/t500_16mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T500" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0xFFD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +CONFIG_BOARD_LENOVO_T500=y +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/t500_16mb/vbootrevision b/resources/libreboot/config/grub/t500_16mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/t500_16mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/t500_4mb/architecture b/resources/libreboot/config/grub/t500_4mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/t500_4mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/t500_4mb/cbrevision b/resources/libreboot/config/grub/t500_4mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/t500_4mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/t500_4mb/config b/resources/libreboot/config/grub/t500_4mb/config new file mode 100644 index 00000000..1a09b085 --- /dev/null +++ b/resources/libreboot/config/grub/t500_4mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T500" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x3FD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +CONFIG_BOARD_LENOVO_T500=y +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/t500_4mb/vbootrevision b/resources/libreboot/config/grub/t500_4mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/t500_4mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/t500_8mb/architecture b/resources/libreboot/config/grub/t500_8mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/t500_8mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/t500_8mb/cbrevision b/resources/libreboot/config/grub/t500_8mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/t500_8mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/t500_8mb/config b/resources/libreboot/config/grub/t500_8mb/config new file mode 100644 index 00000000..b24f8e5b --- /dev/null +++ b/resources/libreboot/config/grub/t500_8mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T500" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x7FD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +CONFIG_BOARD_LENOVO_T500=y +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/t500_8mb/vbootrevision b/resources/libreboot/config/grub/t500_8mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/t500_8mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/t60/architecture b/resources/libreboot/config/grub/t60/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/t60/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/t60/cbrevision b/resources/libreboot/config/grub/t60/cbrevision new file mode 100644 index 00000000..1ab8299e --- /dev/null +++ b/resources/libreboot/config/grub/t60/cbrevision @@ -0,0 +1 @@ +2a3434757ef425dbdfedf1fc69e1a033a6e7310d diff --git a/resources/libreboot/config/grub/t60/config b/resources/libreboot/config/grub/t60/config new file mode 100644 index 00000000..31ca0d51 --- /dev/null +++ b/resources/libreboot/config/grub/t60/config @@ -0,0 +1,540 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="79ETE7WW (2.27 )" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +# CONFIG_COMPRESS_PRERAM_STAGES is not set +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +CONFIG_FLASHMAP_OFFSET=0x0 +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_ACPI_SATA_GENERATOR is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t60" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad T60" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_VGA_BIOS_ID="8086,27a2" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +# CONFIG_UDELAY_IO is not set +CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_RAMTOP=0x200000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x200000 +CONFIG_POST_DEVICE=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +CONFIG_BOARD_LENOVO_T60=y +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_POST is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_FMDFILE="" +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_HEAP_SIZE=0x4000 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set +# CONFIG_VRAM_SIZE_1MB is not set +# CONFIG_VRAM_SIZE_4MB is not set +# CONFIG_VRAM_SIZE_8MB is not set +# CONFIG_VRAM_SIZE_16MB is not set +# CONFIG_VRAM_SIZE_32MB is not set +# CONFIG_VRAM_SIZE_48MB is not set +CONFIG_VRAM_SIZE_64MB=y +CONFIG_VRAM_SIZE=0x70 +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_TI_PCI1X2X=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87384=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_DOCK_EARLY_INIT=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +CONFIG_AP_IN_SIPI_WAIT=y +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_COMPILE_IN_DSDT is not set +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_PXE_ROM is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_RTC=y +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_COMMON_FADT=y +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_DEBUG_BOOT_STATE is not set diff --git a/resources/libreboot/config/grub/t60/vbootrevision b/resources/libreboot/config/grub/t60/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/t60/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/x200_16mb/architecture b/resources/libreboot/config/grub/x200_16mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/x200_16mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/x200_16mb/cbrevision b/resources/libreboot/config/grub/x200_16mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/x200_16mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/x200_16mb/config b/resources/libreboot/config/grub/x200_16mb/config new file mode 100644 index 00000000..b50d32b1 --- /dev/null +++ b/resources/libreboot/config/grub/x200_16mb/config @@ -0,0 +1,545 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x200" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X200" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0xFFD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +# CONFIG_DRIVERS_UART_8250IO is not set +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_BOARD_LENOVO_X200=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +CONFIG_DRIVERS_LENOVO_WACOM=y +# CONFIG_DIGITIZER_AUTODETECT is not set +CONFIG_DIGITIZER_PRESENT=y +# CONFIG_DIGITIZER_ABSENT is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/x200_16mb/vbootrevision b/resources/libreboot/config/grub/x200_16mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/x200_16mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/x200_4mb/architecture b/resources/libreboot/config/grub/x200_4mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/x200_4mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/x200_4mb/cbrevision b/resources/libreboot/config/grub/x200_4mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/x200_4mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/x200_4mb/config b/resources/libreboot/config/grub/x200_4mb/config new file mode 100644 index 00000000..38812ee7 --- /dev/null +++ b/resources/libreboot/config/grub/x200_4mb/config @@ -0,0 +1,545 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x200" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X200" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x3FD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +# CONFIG_DRIVERS_UART_8250IO is not set +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_BOARD_LENOVO_X200=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +CONFIG_DRIVERS_LENOVO_WACOM=y +# CONFIG_DIGITIZER_AUTODETECT is not set +CONFIG_DIGITIZER_PRESENT=y +# CONFIG_DIGITIZER_ABSENT is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/x200_4mb/vbootrevision b/resources/libreboot/config/grub/x200_4mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/x200_4mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/x200_8mb/architecture b/resources/libreboot/config/grub/x200_8mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/x200_8mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/x200_8mb/cbrevision b/resources/libreboot/config/grub/x200_8mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/x200_8mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/x200_8mb/config b/resources/libreboot/config/grub/x200_8mb/config new file mode 100644 index 00000000..94636c64 --- /dev/null +++ b/resources/libreboot/config/grub/x200_8mb/config @@ -0,0 +1,545 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x200" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X200" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x7FD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +# CONFIG_DRIVERS_UART_8250IO is not set +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_BOARD_LENOVO_X200=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +CONFIG_DRIVERS_LENOVO_WACOM=y +# CONFIG_DIGITIZER_AUTODETECT is not set +CONFIG_DIGITIZER_PRESENT=y +# CONFIG_DIGITIZER_ABSENT is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/x200_8mb/vbootrevision b/resources/libreboot/config/grub/x200_8mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/x200_8mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/x60/architecture b/resources/libreboot/config/grub/x60/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/x60/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/x60/cbrevision b/resources/libreboot/config/grub/x60/cbrevision new file mode 100644 index 00000000..1ab8299e --- /dev/null +++ b/resources/libreboot/config/grub/x60/cbrevision @@ -0,0 +1 @@ +2a3434757ef425dbdfedf1fc69e1a033a6e7310d diff --git a/resources/libreboot/config/grub/x60/config b/resources/libreboot/config/grub/x60/config new file mode 100644 index 00000000..76c2f6c8 --- /dev/null +++ b/resources/libreboot/config/grub/x60/config @@ -0,0 +1,546 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +# CONFIG_COMPRESS_PRERAM_STAGES is not set +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +CONFIG_FLASHMAP_OFFSET=0x0 +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_ACPI_SATA_GENERATOR is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x60" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X60" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_VGA_BIOS_ID="8086,27a2" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +# CONFIG_UDELAY_IO is not set +CONFIG_DCACHE_RAM_BASE=0xffdf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_RAMTOP=0x200000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x200000 +CONFIG_POST_DEVICE=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +# CONFIG_BOARD_LENOVO_T500 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +CONFIG_BOARD_LENOVO_X60=y +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_POST is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_FMDFILE="" +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_HEAP_SIZE=0x4000 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_6EX=y +CONFIG_CPU_INTEL_MODEL_6FX=y +CONFIG_CPU_INTEL_SOCKET_MFCPGA478=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC is not set +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +# CONFIG_CHECK_SLFRCS_ON_RESUME is not set +# CONFIG_VRAM_SIZE_1MB is not set +# CONFIG_VRAM_SIZE_4MB is not set +# CONFIG_VRAM_SIZE_8MB is not set +# CONFIG_VRAM_SIZE_16MB is not set +# CONFIG_VRAM_SIZE_32MB is not set +# CONFIG_VRAM_SIZE_48MB is not set +CONFIG_VRAM_SIZE_64MB=y +CONFIG_VRAM_SIZE=0x70 +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y +CONFIG_SOUTHBRIDGE_RICOH_RL5C476=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y +CONFIG_SUPERIO_NSC_PC87392=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_H8_DOCK_EARLY_INIT=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +CONFIG_AP_IN_SIPI_WAIT=y +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_COMPILE_IN_DSDT is not set +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_PXE_ROM is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_IPMI_KCS is not set +CONFIG_DRIVERS_LENOVO_WACOM=y +# CONFIG_DIGITIZER_AUTODETECT is not set +CONFIG_DIGITIZER_PRESENT=y +# CONFIG_DIGITIZER_ABSENT is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_UART is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_RTC=y +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y +CONFIG_COMMON_FADT=y +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_DEBUG_BOOT_STATE is not set diff --git a/resources/libreboot/config/grub/x60/vbootrevision b/resources/libreboot/config/grub/x60/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/x60/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/seabios/d945gclf/architecture b/resources/libreboot/config/seabios/d945gclf/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/seabios/d945gclf/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/seabios/d945gclf/cbrevision b/resources/libreboot/config/seabios/d945gclf/cbrevision new file mode 100644 index 00000000..f6e726f0 --- /dev/null +++ b/resources/libreboot/config/seabios/d945gclf/cbrevision @@ -0,0 +1 @@ +36d405268f040208cd26902f3c0b5346f7d4d25b diff --git a/resources/libreboot/config/seabios/d945gclf/config b/resources/libreboot/config/seabios/d945gclf/config new file mode 100644 index 00000000..11151e71 --- /dev/null +++ b/resources/libreboot/config/seabios/d945gclf/config @@ -0,0 +1,598 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +# CONFIG_STATIC_OPTION_TABLE is not set +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_EARLY_CBMEM_LIST is not set +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +CONFIG_DEVICETREE="devicetree.cb" +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +CONFIG_VENDOR_INTEL=y +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="intel/d945gclf" +CONFIG_MAINBOARD_PART_NUMBER="D945GCLF" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="Intel" +CONFIG_MAX_CPUS=4 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x80000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_VGA_BIOS_ID="8086,27a2" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +# CONFIG_HAS_LVDS is not set +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel" +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set +# CONFIG_BOARD_EMULATION_QEMU_POWER8 is not set +# CONFIG_BOARD_EMULATION_QEMU_X86_Q35 is not set +# CONFIG_BOARD_EMULATION_QEMU_UCB_RISCV is not set +# CONFIG_BOARD_EMULATION_SPIKE_UCB_RISCV is not set +CONFIG_POST_DEVICE=y +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_TTYS0_LCS=3 +# CONFIG_BOARD_INTEL_AMENIA is not set +# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set +# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set +# CONFIG_BOARD_INTEL_BAKERSPORT_FSP is not set +# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set +# CONFIG_BOARD_INTEL_BAYLEYBAY_FSP is not set +# CONFIG_BOARD_INTEL_CAMELBACKMOUNTAIN_FSP is not set +# CONFIG_BOARD_INTEL_COUGAR_CANYON2 is not set +# CONFIG_BOARD_INTEL_D510MO is not set +# CONFIG_BOARD_INTEL_D810E2CB is not set +CONFIG_BOARD_INTEL_D945GCLF=y +# CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set +# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set +# CONFIG_BOARD_INTEL_GALILEO is not set +# CONFIG_BOARD_INTEL_KUNIMITSU is not set +# CONFIG_BOARD_INTEL_LITTLEPLAINS is not set +# CONFIG_BOARD_INTEL_MINNOWMAX is not set +# CONFIG_BOARD_INTEL_MOHONPEAK is not set +# CONFIG_BOARD_INTEL_MTARVON is not set +# CONFIG_BOARD_INTEL_STARGO2 is not set +# CONFIG_BOARD_INTEL_STRAGO is not set +# CONFIG_BOARD_INTEL_TRUXTON is not set +# CONFIG_BOARD_INTEL_WTM2 is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_CPU_ADDR_BITS=32 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_NO_POST is not set +CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0 +CONFIG_BOARD_ROMSIZE_KB_512=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +CONFIG_COREBOOT_ROMSIZE_KB_512=y +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=512 +CONFIG_ROM_SIZE=0x80000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_SOCKET_SPECIFIC_OPTIONS=y +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_106CX=y +CONFIG_SSE2=y +CONFIG_CPU_INTEL_SOCKET_441=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +CONFIG_SERIALIZED_SMM_INITIALIZATION=y +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_I945=y +CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y +# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM is not set +CONFIG_CHANNEL_XOR_RANDOMIZATION=y +# CONFIG_OVERRIDE_CLOCK_DISABLE is not set +CONFIG_CHECK_SLFRCS_ON_RESUME=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y + +# +# Super I/O +# +CONFIG_SUPERIO_SMSC_LPC47M15X=y + +# +# Embedded Controllers +# +CONFIG_VBOOT_VBNV_OFFSET=0x26 +# CONFIG_VBOOT_VBNV_CMOS is not set +# CONFIG_VBOOT_VBNV_EC is not set +# CONFIG_VBOOT is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +CONFIG_AP_IN_SIPI_WAIT=y +CONFIG_SIPI_VECTOR_IN_ROM=y +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +# CONFIG_HAVE_CMOS_DEFAULT is not set +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +# CONFIG_INTEL_INT15 is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +CONFIG_DRIVERS_INTEL_WIFI=y +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y +CONFIG_COMMON_FADT=y +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +# CONFIG_SEABIOS_STABLE is not set +# CONFIG_SEABIOS_MASTER is not set +# CONFIG_SEABIOS_REVISION is not set +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/seabios/d945gclf/vbootrevision b/resources/libreboot/config/seabios/d945gclf/vbootrevision new file mode 100644 index 00000000..67bdb13d --- /dev/null +++ b/resources/libreboot/config/seabios/d945gclf/vbootrevision @@ -0,0 +1 @@ +f7559e4b4652134b1e15de3ce31ee50a3de00f69 diff --git a/resources/libreboot/config/seabios/kcma-d8/architecture b/resources/libreboot/config/seabios/kcma-d8/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/seabios/kcma-d8/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/seabios/kcma-d8/cbrevision b/resources/libreboot/config/seabios/kcma-d8/cbrevision new file mode 100644 index 00000000..a4c248f2 --- /dev/null +++ b/resources/libreboot/config/seabios/kcma-d8/cbrevision @@ -0,0 +1 @@ +eee0e229764e965996479d7eb07e6086176b8bf0 diff --git a/resources/libreboot/config/seabios/kcma-d8/config b/resources/libreboot/config/seabios/kcma-d8/config new file mode 100644 index 00000000..abc6efbb --- /dev/null +++ b/resources/libreboot/config/seabios/kcma-d8/config @@ -0,0 +1,614 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +CONFIG_FLASHMAP_OFFSET=0 +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_ACPI_SATA_GENERATOR is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +CONFIG_VENDOR_ASUS=y +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="asus/kcma-d8" +CONFIG_MAINBOARD_PART_NUMBER="KCMA-D8" +CONFIG_IRQ_SLOT_COUNT=13 +CONFIG_MAINBOARD_VENDOR="ASUS" +CONFIG_APIC_ID_OFFSET=0 +CONFIG_HW_MEM_HOLE_SIZEK=0x100000 +CONFIG_MAX_CPUS=16 +CONFIG_MAX_PHYSICAL_CPUS=2 +# CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC is not set +CONFIG_HT_CHAIN_END_UNITID_BASE=0x20 +CONFIG_HT_CHAIN_UNITID_BASE=0x0 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_DCACHE_RAM_BASE=0xc2000 +CONFIG_DCACHE_RAM_SIZE=0x1e000 +CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" +# CONFIG_BOARD_ASUS_A8N_E is not set +# CONFIG_BOARD_ASUS_A8N_SLI is not set +# CONFIG_BOARD_ASUS_A8V_E_DELUXE is not set +# CONFIG_BOARD_ASUS_A8V_E_SE is not set +# CONFIG_BOARD_ASUS_DSBF is not set +# CONFIG_BOARD_ASUS_F2A85_M is not set +# CONFIG_BOARD_ASUS_F2A85_M_LE is not set +# CONFIG_BOARD_ASUS_K8V_X is not set +CONFIG_BOARD_ASUS_KCMA_D8=y +# CONFIG_BOARD_ASUS_KFSN4_DRE is not set +# CONFIG_BOARD_ASUS_KFSN4_DRE_K8 is not set +# CONFIG_BOARD_ASUS_KGPE_D16 is not set +# CONFIG_BOARD_ASUS_M2N_E is not set +# CONFIG_BOARD_ASUS_M2V_MX_SE is not set +# CONFIG_BOARD_ASUS_M2V is not set +# CONFIG_BOARD_ASUS_M4A78_EM is not set +# CONFIG_BOARD_ASUS_M4A785M is not set +# CONFIG_BOARD_ASUS_M4A785TM is not set +# CONFIG_BOARD_ASUS_M5A88_V is not set +# CONFIG_BOARD_ASUS_MEW_AM is not set +# CONFIG_BOARD_ASUS_MEW_VM is not set +# CONFIG_BOARD_ASUS_P2B_D is not set +# CONFIG_BOARD_ASUS_P2B_DS is not set +# CONFIG_BOARD_ASUS_P2B_F is not set +# CONFIG_BOARD_ASUS_P2B_LS is not set +# CONFIG_BOARD_ASUS_P2B is not set +# CONFIG_BOARD_ASUS_P3B_F is not set +# CONFIG_POST_IO is not set +CONFIG_AGP_APERTURE_SIZE=0x4000000 +CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/asus/kcma-d8/bootblock.c" +CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD=0x3f +CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL=y +CONFIG_MAX_REBOOT_CNT=10 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_RAMTOP=0x400000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x200000 +# CONFIG_POST_DEVICE is not set +CONFIG_BOOT_MEDIA_SPI_BUS=0 +CONFIG_TTYS0_LCS=3 +CONFIG_CONSOLE_POST=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_CPU_ADDR_BITS=48 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_DRIVERS_PS2_KEYBOARD=y +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_FMDFILE="" +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/amd/amdfam10/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/sb700/bootblock.c" +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_HEAP_SIZE=0xc0000 +CONFIG_CONSOLE_CBMEM=y +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_DCACHE_BSP_STACK_SLUSH=0x4000 +CONFIG_DCACHE_AP_STACK_SIZE=0x500 +CONFIG_CPU_SOCKET_TYPE=0x14 +# CONFIG_EXT_RT_TBL_SUPPORT is not set +CONFIG_CBB=0x0 +CONFIG_CDB=0x18 +CONFIG_XIP_ROM_SIZE=0x80000 +CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA=y +CONFIG_DIMM_SUPPORT=0x0005 +CONFIG_LIFT_BSP_APIC_ID=y +CONFIG_SET_FIDVID=y +CONFIG_SET_FIDVID_DEBUG=y +# CONFIG_SET_FIDVID_CORE0_ONLY is not set +CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST=y +CONFIG_CPU_AMD_MODEL_10XXX=y +CONFIG_USE_LARGE_DCACHE=y +CONFIG_NUM_IPI_STARTS=1 +CONFIG_SET_FIDVID_CORE_RANGE=0 +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_S3_DATA_POS=0x0 +CONFIG_S3_DATA_SIZE=32768 +# CONFIG_CPU_AMD_PI is not set +# CONFIG_EXT_CONF_SUPPORT is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +CONFIG_PARALLEL_CPU_INIT=y +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +# CONFIG_LAPIC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +CONFIG_TSC_SYNC_LFENCE=y +# CONFIG_TSC_SYNC_MFENCE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +CONFIG_X86_AMD_FIXED_MTRRS=y +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +CONFIG_MMCONF_BUS_NUMBER=256 +CONFIG_NORTHBRIDGE_AMD_AMDFAM10=y +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=y +# CONFIG_HT_CHAIN_DISTRIBUTE is not set +# CONFIG_DIMM_FBDIMM is not set +# CONFIG_DIMM_DDR2 is not set +CONFIG_DIMM_DDR3=y +CONFIG_DIMM_REGISTERED=y +CONFIG_DIMM_VOLTAGE_SET_SUPPORT=y +# CONFIG_SVI_HIGH_FREQ is not set + +# +# HyperTransport setup +# +# CONFIG_LIMIT_HT_DOWN_WIDTH_8 is not set +CONFIG_LIMIT_HT_DOWN_WIDTH_16=y +# CONFIG_LIMIT_HT_UP_WIDTH_8 is not set +CONFIG_LIMIT_HT_UP_WIDTH_16=y +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_HPET_MIN_TICKS=0x14 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_AMD_SB700=y +CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100=y +# CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT is not set +CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA=y +CONFIG_SOUTHBRIDGE_AMD_SR5650=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set + +# +# Super I/O +# +CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE=y +CONFIG_SUPERIO_WINBOND_W83667HG_A=y + +# +# Embedded Controllers +# +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_POSTCAR_STAGE is not set + +# +# Devices +# +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +# CONFIG_VGA_ROM_RUN is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +CONFIG_SMBUS_HAS_AUX_CHANNELS=y +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_CLK_PM=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_ATOMIC_SEQUENCING=y +CONFIG_SPI_FLASH_MEMORY_MAPPED=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_DRIVERS_ASPEED_AST2050=y +CONFIG_DEVICE_SPECIFIC_OPTIONS=y +CONFIG_DRIVERS_ASPEED_AST_COMMON=y +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_I2C_W83795=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y +CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y +CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +# CONFIG_HAVE_SMI_HANDLER is not set +CONFIG_PCI_IO_CFG_EXT=y +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KCMA-D8" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_CAR=y +# CONFIG_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +CONFIG_ENABLE_APIC_EXT_ID=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_DEBUG_BOOT_STATE is not set diff --git a/resources/libreboot/config/seabios/kcma-d8/vbootrevision b/resources/libreboot/config/seabios/kcma-d8/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/seabios/kcma-d8/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/seabios/kfsn4-dre/architecture b/resources/libreboot/config/seabios/kfsn4-dre/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/seabios/kfsn4-dre/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/seabios/kfsn4-dre/cbrevision b/resources/libreboot/config/seabios/kfsn4-dre/cbrevision new file mode 100644 index 00000000..fabe7537 --- /dev/null +++ b/resources/libreboot/config/seabios/kfsn4-dre/cbrevision @@ -0,0 +1 @@ +15fca66bf08db45937ce88b950491963654805b9 diff --git a/resources/libreboot/config/seabios/kfsn4-dre/config b/resources/libreboot/config/seabios/kfsn4-dre/config new file mode 100644 index 00000000..4939e17a --- /dev/null +++ b/resources/libreboot/config/seabios/kfsn4-dre/config @@ -0,0 +1,610 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +CONFIG_FLASHMAP_OFFSET=0 +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_ACPI_SATA_GENERATOR is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +CONFIG_VENDOR_ASUS=y +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="asus/kfsn4-dre" +CONFIG_MAINBOARD_PART_NUMBER="KFSN4-DRE" +CONFIG_IRQ_SLOT_COUNT=13 +CONFIG_MAINBOARD_VENDOR="ASUS" +CONFIG_APIC_ID_OFFSET=0 +CONFIG_HW_MEM_HOLE_SIZEK=0x100000 +CONFIG_MAX_CPUS=12 +CONFIG_MAX_PHYSICAL_CPUS=2 +# CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC is not set +CONFIG_HT_CHAIN_END_UNITID_BASE=0x20 +CONFIG_HT_CHAIN_UNITID_BASE=0x0 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_DCACHE_RAM_BASE=0xc4000 +CONFIG_DCACHE_RAM_SIZE=0x0c000 +CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" +# CONFIG_BOARD_ASUS_A8N_E is not set +# CONFIG_BOARD_ASUS_A8N_SLI is not set +# CONFIG_BOARD_ASUS_A8V_E_DELUXE is not set +# CONFIG_BOARD_ASUS_A8V_E_SE is not set +# CONFIG_BOARD_ASUS_DSBF is not set +# CONFIG_BOARD_ASUS_F2A85_M is not set +# CONFIG_BOARD_ASUS_F2A85_M_LE is not set +# CONFIG_BOARD_ASUS_K8V_X is not set +# CONFIG_BOARD_ASUS_KCMA_D8 is not set +CONFIG_BOARD_ASUS_KFSN4_DRE=y +# CONFIG_BOARD_ASUS_KFSN4_DRE_K8 is not set +# CONFIG_BOARD_ASUS_KGPE_D16 is not set +# CONFIG_BOARD_ASUS_M2N_E is not set +# CONFIG_BOARD_ASUS_M2V_MX_SE is not set +# CONFIG_BOARD_ASUS_M2V is not set +# CONFIG_BOARD_ASUS_M4A78_EM is not set +# CONFIG_BOARD_ASUS_M4A785M is not set +# CONFIG_BOARD_ASUS_M4A785TM is not set +# CONFIG_BOARD_ASUS_M5A88_V is not set +# CONFIG_BOARD_ASUS_MEW_AM is not set +# CONFIG_BOARD_ASUS_MEW_VM is not set +# CONFIG_BOARD_ASUS_P2B_D is not set +# CONFIG_BOARD_ASUS_P2B_DS is not set +# CONFIG_BOARD_ASUS_P2B_F is not set +# CONFIG_BOARD_ASUS_P2B_LS is not set +# CONFIG_BOARD_ASUS_P2B is not set +# CONFIG_BOARD_ASUS_P3B_F is not set +CONFIG_POST_IO=y +CONFIG_AGP_APERTURE_SIZE=0x4000000 +CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/asus/kfsn4-dre/bootblock.c" +CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL=y +CONFIG_MAX_REBOOT_CNT=10 +CONFIG_CK804_PCI_E_X=1 +CONFIG_CK804_PCIE_PME_WAKE=y +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_RAMTOP=0x400000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x100000 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=0 +CONFIG_TTYS0_LCS=3 +CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_CPU_ADDR_BITS=48 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +CONFIG_USBDEBUG=y +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_DRIVERS_PS2_KEYBOARD=y +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_POST is not set +CONFIG_CK804_NUM=1 +CONFIG_BOARD_ROMSIZE_KB_1024=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +CONFIG_COREBOOT_ROMSIZE_KB_1024=y +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=1024 +CONFIG_ROM_SIZE=0x100000 +CONFIG_FMDFILE="" +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/amd/amdfam10/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/nvidia/ck804/bootblock.c" +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_HEAP_SIZE=0xc0000 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_DCACHE_BSP_STACK_SLUSH=0x1000 +CONFIG_DCACHE_AP_STACK_SIZE=0x500 +CONFIG_CPU_SOCKET_TYPE=0x10 +# CONFIG_EXT_RT_TBL_SUPPORT is not set +CONFIG_CBB=0x0 +CONFIG_CDB=0x18 +CONFIG_XIP_ROM_SIZE=0x80000 +CONFIG_CPU_AMD_SOCKET_F_1207=y +CONFIG_DIMM_SUPPORT=0x0104 +CONFIG_LIFT_BSP_APIC_ID=y +CONFIG_SET_FIDVID=y +CONFIG_SET_FIDVID_DEBUG=y +# CONFIG_SET_FIDVID_CORE0_ONLY is not set +CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST=y +CONFIG_CPU_AMD_MODEL_10XXX=y +# CONFIG_USE_LARGE_DCACHE is not set +CONFIG_NUM_IPI_STARTS=1 +CONFIG_SET_FIDVID_CORE_RANGE=0 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +CONFIG_PARALLEL_CPU_INIT=y +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +# CONFIG_LAPIC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +CONFIG_TSC_SYNC_LFENCE=y +# CONFIG_TSC_SYNC_MFENCE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +CONFIG_X86_AMD_FIXED_MTRRS=y +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +CONFIG_MMCONF_BUS_NUMBER=256 +CONFIG_NORTHBRIDGE_AMD_AMDFAM10=y +# CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY is not set +# CONFIG_HT_CHAIN_DISTRIBUTE is not set +# CONFIG_DIMM_FBDIMM is not set +CONFIG_DIMM_DDR2=y +# CONFIG_DIMM_DDR3 is not set +CONFIG_DIMM_REGISTERED=y +# CONFIG_DIMM_VOLTAGE_SET_SUPPORT is not set +# CONFIG_SVI_HIGH_FREQ is not set + +# +# HyperTransport setup +# +# CONFIG_LIMIT_HT_DOWN_WIDTH_8 is not set +CONFIG_LIMIT_HT_DOWN_WIDTH_16=y +# CONFIG_LIMIT_HT_UP_WIDTH_8 is not set +CONFIG_LIMIT_HT_UP_WIDTH_16=y +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_HPET_MIN_TICKS=0xfa +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_NVIDIA_CK804=y +# CONFIG_CK804_USE_NIC is not set +# CONFIG_CK804_USE_ACI is not set +CONFIG_CK804B_PCI_E_X=4 + +# +# Super I/O +# +CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE=y +CONFIG_SUPERIO_WINBOND_W83627THG=y + +# +# Embedded Controllers +# +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_COMPILE_IN_DSDT is not set +CONFIG_VERSTAGE_ADDR=0x2000000 + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +# CONFIG_NATIVE_VGA_INIT_USE_EDID is not set +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_CLK_PM=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_PXE_ROM is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +CONFIG_DEVICE_SPECIFIC_OPTIONS=y +# CONFIG_GIC is not set +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_I2C_W83793=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +CONFIG_DRIVERS_UART=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +# CONFIG_HAVE_USBDEBUG_OPTIONS is not set +CONFIG_USBDEBUG_IN_ROMSTAGE=y +CONFIG_USBDEBUG_DEFAULT_PORT=0 +CONFIG_USBDEBUG_DONGLE_STD=y +# CONFIG_USBDEBUG_DONGLE_BEAGLEBONE is not set +# CONFIG_USBDEBUG_DONGLE_BEAGLEBONE_BLACK is not set +# CONFIG_USBDEBUG_DONGLE_FTDI_FT232H is not set +CONFIG_USBDEBUG_OPTIONAL_HUB_PORT=0 +CONFIG_DRIVERS_XGI_Z79_COMMON=y +CONFIG_DRIVERS_XGI_Z9S=y +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_RTC=y +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +CONFIG_CONSOLE_USB=y +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +# CONFIG_HAVE_ACPI_RESUME is not set +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +# CONFIG_HAVE_SMI_HANDLER is not set +CONFIG_PCI_IO_CFG_EXT=y +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KFSN4-DRE" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_CAR=y +# CONFIG_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_USBDEBUG is not set +# CONFIG_TRACE is not set +CONFIG_ENABLE_APIC_EXT_ID=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_DEBUG_BOOT_STATE is not set diff --git a/resources/libreboot/config/seabios/kfsn4-dre/vbootrevision b/resources/libreboot/config/seabios/kfsn4-dre/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/seabios/kfsn4-dre/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/seabios/kgpe-d16/architecture b/resources/libreboot/config/seabios/kgpe-d16/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/seabios/kgpe-d16/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/seabios/kgpe-d16/cbrevision b/resources/libreboot/config/seabios/kgpe-d16/cbrevision new file mode 100644 index 00000000..a4c248f2 --- /dev/null +++ b/resources/libreboot/config/seabios/kgpe-d16/cbrevision @@ -0,0 +1 @@ +eee0e229764e965996479d7eb07e6086176b8bf0 diff --git a/resources/libreboot/config/seabios/kgpe-d16/config b/resources/libreboot/config/seabios/kgpe-d16/config new file mode 100644 index 00000000..eb414a31 --- /dev/null +++ b/resources/libreboot/config/seabios/kgpe-d16/config @@ -0,0 +1,614 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +CONFIG_FLASHMAP_OFFSET=0 +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set +# CONFIG_ACPI_SATA_GENERATOR is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +CONFIG_VENDOR_ASUS=y +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="asus/kgpe-d16" +CONFIG_MAINBOARD_PART_NUMBER="KGPE-D16" +CONFIG_IRQ_SLOT_COUNT=13 +CONFIG_MAINBOARD_VENDOR="ASUS" +CONFIG_APIC_ID_OFFSET=0 +CONFIG_HW_MEM_HOLE_SIZEK=0x100000 +CONFIG_MAX_CPUS=32 +CONFIG_MAX_PHYSICAL_CPUS=4 +# CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC is not set +CONFIG_HT_CHAIN_END_UNITID_BASE=0x20 +CONFIG_HT_CHAIN_UNITID_BASE=0x0 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_VGA_BIOS is not set +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_DCACHE_RAM_BASE=0xc2000 +CONFIG_DCACHE_RAM_SIZE=0x1e000 +CONFIG_MMCONF_BASE_ADDRESS=0xc0000000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" +# CONFIG_BOARD_ASUS_A8N_E is not set +# CONFIG_BOARD_ASUS_A8N_SLI is not set +# CONFIG_BOARD_ASUS_A8V_E_DELUXE is not set +# CONFIG_BOARD_ASUS_A8V_E_SE is not set +# CONFIG_BOARD_ASUS_DSBF is not set +# CONFIG_BOARD_ASUS_F2A85_M is not set +# CONFIG_BOARD_ASUS_F2A85_M_LE is not set +# CONFIG_BOARD_ASUS_K8V_X is not set +# CONFIG_BOARD_ASUS_KCMA_D8 is not set +# CONFIG_BOARD_ASUS_KFSN4_DRE is not set +# CONFIG_BOARD_ASUS_KFSN4_DRE_K8 is not set +CONFIG_BOARD_ASUS_KGPE_D16=y +# CONFIG_BOARD_ASUS_M2N_E is not set +# CONFIG_BOARD_ASUS_M2V_MX_SE is not set +# CONFIG_BOARD_ASUS_M2V is not set +# CONFIG_BOARD_ASUS_M4A78_EM is not set +# CONFIG_BOARD_ASUS_M4A785M is not set +# CONFIG_BOARD_ASUS_M4A785TM is not set +# CONFIG_BOARD_ASUS_M5A88_V is not set +# CONFIG_BOARD_ASUS_MEW_AM is not set +# CONFIG_BOARD_ASUS_MEW_VM is not set +# CONFIG_BOARD_ASUS_P2B_D is not set +# CONFIG_BOARD_ASUS_P2B_DS is not set +# CONFIG_BOARD_ASUS_P2B_F is not set +# CONFIG_BOARD_ASUS_P2B_LS is not set +# CONFIG_BOARD_ASUS_P2B is not set +# CONFIG_BOARD_ASUS_P3B_F is not set +# CONFIG_POST_IO is not set +CONFIG_AGP_APERTURE_SIZE=0x4000000 +CONFIG_BOOTBLOCK_MAINBOARD_INIT="mainboard/asus/kgpe-d16/bootblock.c" +CONFIG_SOUTHBRIDGE_AMD_SB700_SATA_PORT_COUNT_BITFIELD=0x3f +CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL=y +CONFIG_MAX_REBOOT_CNT=10 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_RAMTOP=0x400000 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x200000 +# CONFIG_POST_DEVICE is not set +CONFIG_BOOT_MEDIA_SPI_BUS=0 +CONFIG_TTYS0_LCS=3 +CONFIG_CONSOLE_POST=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_CPU_ADDR_BITS=48 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_DRIVERS_PS2_KEYBOARD=y +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +CONFIG_COREBOOT_ROMSIZE_KB_2048=y +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=2048 +CONFIG_ROM_SIZE=0x200000 +CONFIG_FMDFILE="" +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_DCACHE_BSP_STACK_SIZE=0x4000 +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/amd/amdfam10/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/sb700/bootblock.c" +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_HEAP_SIZE=0xc0000 +CONFIG_CONSOLE_CBMEM=y +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_DCACHE_BSP_STACK_SLUSH=0x4000 +CONFIG_DCACHE_AP_STACK_SIZE=0x500 +CONFIG_CPU_SOCKET_TYPE=0x15 +# CONFIG_EXT_RT_TBL_SUPPORT is not set +CONFIG_CBB=0x0 +CONFIG_CDB=0x18 +CONFIG_XIP_ROM_SIZE=0x80000 +CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA=y +CONFIG_DIMM_SUPPORT=0x0005 +CONFIG_LIFT_BSP_APIC_ID=y +CONFIG_SET_FIDVID=y +CONFIG_SET_FIDVID_DEBUG=y +# CONFIG_SET_FIDVID_CORE0_ONLY is not set +CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST=y +CONFIG_CPU_AMD_MODEL_10XXX=y +CONFIG_USE_LARGE_DCACHE=y +CONFIG_NUM_IPI_STARTS=1 +CONFIG_SET_FIDVID_CORE_RANGE=0 +# CONFIG_CPU_AMD_AGESA is not set +CONFIG_S3_DATA_POS=0x0 +CONFIG_S3_DATA_SIZE=32768 +# CONFIG_CPU_AMD_PI is not set +CONFIG_EXT_CONF_SUPPORT=y +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +CONFIG_PARALLEL_CPU_INIT=y +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +# CONFIG_LAPIC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +CONFIG_TSC_SYNC_LFENCE=y +# CONFIG_TSC_SYNC_MFENCE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +CONFIG_X86_AMD_FIXED_MTRRS=y +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +CONFIG_MMCONF_BUS_NUMBER=256 +CONFIG_NORTHBRIDGE_AMD_AMDFAM10=y +CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=y +# CONFIG_HT_CHAIN_DISTRIBUTE is not set +# CONFIG_DIMM_FBDIMM is not set +# CONFIG_DIMM_DDR2 is not set +CONFIG_DIMM_DDR3=y +CONFIG_DIMM_REGISTERED=y +CONFIG_DIMM_VOLTAGE_SET_SUPPORT=y +# CONFIG_SVI_HIGH_FREQ is not set + +# +# HyperTransport setup +# +# CONFIG_LIMIT_HT_DOWN_WIDTH_8 is not set +CONFIG_LIMIT_HT_DOWN_WIDTH_16=y +# CONFIG_LIMIT_HT_UP_WIDTH_8 is not set +CONFIG_LIMIT_HT_UP_WIDTH_16=y +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_HPET_MIN_TICKS=0x14 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_AMD_SB700=y +CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100=y +# CONFIG_SOUTHBRIDGE_AMD_SB700_SKIP_ISA_DMA_INIT is not set +CONFIG_SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA=y +CONFIG_SOUTHBRIDGE_AMD_SR5650=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set + +# +# Super I/O +# +CONFIG_SUPERIO_WINBOND_COMMON_ROMSTAGE=y +CONFIG_SUPERIO_WINBOND_W83667HG_A=y + +# +# Embedded Controllers +# +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_POSTCAR_STAGE is not set + +# +# Devices +# +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +# CONFIG_VGA_ROM_RUN is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +CONFIG_SMBUS_HAS_AUX_CHANNELS=y +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT=y +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_CLK_PM=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_ELOG is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +CONFIG_SPI_FLASH=y +CONFIG_SPI_ATOMIC_SEQUENCING=y +CONFIG_SPI_FLASH_MEMORY_MAPPED=y +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +CONFIG_DRIVERS_ASPEED_AST2050=y +CONFIG_DEVICE_SPECIFIC_OPTIONS=y +CONFIG_DRIVERS_ASPEED_AST_COMMON=y +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_I2C_W83795=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK=y +CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK=y +CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK=y +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +# CONFIG_HAVE_SMI_HANDLER is not set +CONFIG_PCI_IO_CFG_EXT=y +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="KGPE-D16" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +CONFIG_HAVE_DEBUG_CAR=y +# CONFIG_DEBUG_CAR is not set +# CONFIG_DEBUG_PIRQ is not set +CONFIG_HAVE_DEBUG_SMBUS=y +# CONFIG_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +CONFIG_ENABLE_APIC_EXT_ID=y +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_DEBUG_BOOT_STATE is not set diff --git a/resources/libreboot/config/seabios/kgpe-d16/vbootrevision b/resources/libreboot/config/seabios/kgpe-d16/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/seabios/kgpe-d16/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch new file mode 100644 index 00000000..2fde12f4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch @@ -0,0 +1,89 @@ +From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Tue, 8 Mar 2016 07:21:33 +0000 +Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates + +There were build issues in libreboot. We don't use microcode updates anyway. +When selecting no microcode updates in menuconfig, build failed because +coreboot for these boards was still trying to add microcode. +--- + src/cpu/Makefile.inc | 34 +------------------------- + src/cpu/amd/family_10h-family_15h/Kconfig | 1 - + src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- + 3 files changed, 1 insertion(+), 44 deletions(-) + +diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc +index 046c418..ef0e236 100644 +--- a/src/cpu/Makefile.inc ++++ b/src/cpu/Makefile.inc +@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) + ## Rules for building the microcode blob in CBFS + ################################################################################ + +-ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) +-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin +-endif +- +-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) +-cbfs-files-y += cpu_microcode_blob.bin +-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin +- +-$(objgenerated)/microcode.bin: +- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" +- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) +-endif +- +-# We just mash all microcode binaries together into one binary to rule them all. +-# This approach assumes that the microcode binaries are properly padded, and +-# their headers specify the correct size. This works fairly well on isolatied +-# updates, such as Intel and some AMD microcode, but won't work very well if the +-# updates are wrapped in a container, like AMD's microcode update container. If +-# there is only one microcode binary (i.e. one container), then we don't have +-# this issue, and this rule will continue to work. +-$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) +- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" +- @echo $(cpu_microcode_bins) +- cat /dev/null $+ > $@ +- +-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin +-cpu_microcode_blob.bin-type := microcode +- +-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +-cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) +-else +-cpu_microcode_blob.bin-align := 16 +-endif ++# What? Nope! We don't do that in libreboot. +diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig +index 14ab1cd..3f873a1 100644 +--- a/src/cpu/amd/family_10h-family_15h/Kconfig ++++ b/src/cpu/amd/family_10h-family_15h/Kconfig +@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX + select UDELAY_LAPIC + select HAVE_MONOTONIC_TIMER + select SUPPORT_CPU_UCODE_IN_CBFS +- select CPU_MICROCODE_MULTIPLE_FILES + + if CPU_AMD_MODEL_10XXX + +diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc +index f10f732..a295475 100644 +--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc ++++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc +@@ -9,13 +9,3 @@ romstage-y += ram_calc.c + ramstage-y += ram_calc.c + ramstage-y += monotonic_timer.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c +- +-# Microcode for Family 10h, 11h, 12h, and 14h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin +-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin +-microcode_amd.bin-type := microcode +- +-# Microcode for Family 15h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-type := microcode +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch new file mode 100644 index 00000000..2fde12f4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch @@ -0,0 +1,89 @@ +From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Tue, 8 Mar 2016 07:21:33 +0000 +Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates + +There were build issues in libreboot. We don't use microcode updates anyway. +When selecting no microcode updates in menuconfig, build failed because +coreboot for these boards was still trying to add microcode. +--- + src/cpu/Makefile.inc | 34 +------------------------- + src/cpu/amd/family_10h-family_15h/Kconfig | 1 - + src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- + 3 files changed, 1 insertion(+), 44 deletions(-) + +diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc +index 046c418..ef0e236 100644 +--- a/src/cpu/Makefile.inc ++++ b/src/cpu/Makefile.inc +@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) + ## Rules for building the microcode blob in CBFS + ################################################################################ + +-ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) +-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin +-endif +- +-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) +-cbfs-files-y += cpu_microcode_blob.bin +-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin +- +-$(objgenerated)/microcode.bin: +- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" +- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) +-endif +- +-# We just mash all microcode binaries together into one binary to rule them all. +-# This approach assumes that the microcode binaries are properly padded, and +-# their headers specify the correct size. This works fairly well on isolatied +-# updates, such as Intel and some AMD microcode, but won't work very well if the +-# updates are wrapped in a container, like AMD's microcode update container. If +-# there is only one microcode binary (i.e. one container), then we don't have +-# this issue, and this rule will continue to work. +-$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) +- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" +- @echo $(cpu_microcode_bins) +- cat /dev/null $+ > $@ +- +-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin +-cpu_microcode_blob.bin-type := microcode +- +-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +-cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) +-else +-cpu_microcode_blob.bin-align := 16 +-endif ++# What? Nope! We don't do that in libreboot. +diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig +index 14ab1cd..3f873a1 100644 +--- a/src/cpu/amd/family_10h-family_15h/Kconfig ++++ b/src/cpu/amd/family_10h-family_15h/Kconfig +@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX + select UDELAY_LAPIC + select HAVE_MONOTONIC_TIMER + select SUPPORT_CPU_UCODE_IN_CBFS +- select CPU_MICROCODE_MULTIPLE_FILES + + if CPU_AMD_MODEL_10XXX + +diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc +index f10f732..a295475 100644 +--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc ++++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc +@@ -9,13 +9,3 @@ romstage-y += ram_calc.c + ramstage-y += ram_calc.c + ramstage-y += monotonic_timer.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c +- +-# Microcode for Family 10h, 11h, 12h, and 14h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin +-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin +-microcode_amd.bin-type := microcode +- +-# Microcode for Family 15h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-type := microcode +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch new file mode 100644 index 00000000..2fde12f4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch @@ -0,0 +1,89 @@ +From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Tue, 8 Mar 2016 07:21:33 +0000 +Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates + +There were build issues in libreboot. We don't use microcode updates anyway. +When selecting no microcode updates in menuconfig, build failed because +coreboot for these boards was still trying to add microcode. +--- + src/cpu/Makefile.inc | 34 +------------------------- + src/cpu/amd/family_10h-family_15h/Kconfig | 1 - + src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- + 3 files changed, 1 insertion(+), 44 deletions(-) + +diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc +index 046c418..ef0e236 100644 +--- a/src/cpu/Makefile.inc ++++ b/src/cpu/Makefile.inc +@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) + ## Rules for building the microcode blob in CBFS + ################################################################################ + +-ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) +-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin +-endif +- +-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) +-cbfs-files-y += cpu_microcode_blob.bin +-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin +- +-$(objgenerated)/microcode.bin: +- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" +- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) +-endif +- +-# We just mash all microcode binaries together into one binary to rule them all. +-# This approach assumes that the microcode binaries are properly padded, and +-# their headers specify the correct size. This works fairly well on isolatied +-# updates, such as Intel and some AMD microcode, but won't work very well if the +-# updates are wrapped in a container, like AMD's microcode update container. If +-# there is only one microcode binary (i.e. one container), then we don't have +-# this issue, and this rule will continue to work. +-$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) +- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" +- @echo $(cpu_microcode_bins) +- cat /dev/null $+ > $@ +- +-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin +-cpu_microcode_blob.bin-type := microcode +- +-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +-cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) +-else +-cpu_microcode_blob.bin-align := 16 +-endif ++# What? Nope! We don't do that in libreboot. +diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig +index 14ab1cd..3f873a1 100644 +--- a/src/cpu/amd/family_10h-family_15h/Kconfig ++++ b/src/cpu/amd/family_10h-family_15h/Kconfig +@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX + select UDELAY_LAPIC + select HAVE_MONOTONIC_TIMER + select SUPPORT_CPU_UCODE_IN_CBFS +- select CPU_MICROCODE_MULTIPLE_FILES + + if CPU_AMD_MODEL_10XXX + +diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc +index f10f732..a295475 100644 +--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc ++++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc +@@ -9,13 +9,3 @@ romstage-y += ram_calc.c + ramstage-y += ram_calc.c + ramstage-y += monotonic_timer.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c +- +-# Microcode for Family 10h, 11h, 12h, and 14h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin +-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin +-microcode_amd.bin-type := microcode +- +-# Microcode for Family 15h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-type := microcode +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch new file mode 100644 index 00000000..884b2829 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch @@ -0,0 +1,174 @@ +From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Fri, 2 Sep 2016 22:35:32 +0200 +Subject: [PATCH 1/2] i945/gma.c use latest linux code to calculate divisors. + +The code to compute n, m1, m2, p1 divisors is not correct in coreboot and +on some targets hits a working mode at lower refresh rate, which is why +display is working on some targets. +This patch also fixes reference frequency. + +This patch reuses linux code to correctly compute divisors. + +The result is that some previously not working displays (Lenovo T60 with +1024x786, 1400x1050, 2048x1536) + +TESTED on T60 with 1024x786. + +Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- + 1 file changed, 38 insertions(+), 44 deletions(-) + +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index 02caa0a..3f0b5b4 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -26,6 +26,8 @@ + #include <string.h> + #include <pc80/vga.h> + #include <pc80/vga_io.h> ++#include <commonlib/helpers.h> ++ + + #include "i945.h" + #include "chip.h" +@@ -43,7 +45,7 @@ + #define PGETBL_CTL 0x2020 + #define PGETBL_ENABLED 0x00000001 + +-#define BASE_FREQUENCY 120000 ++#define BASE_FREQUENCY 100000 + + #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + +@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + u8 edid_data[128]; + unsigned long temp; + int hpolarity, vpolarity; +- u32 candp1, candn; +- u32 best_delta = 0xffffffff; ++ u32 smallest_err = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; ++ u32 pixel_p2; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; +@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); + write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); + +- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock +- : (2 * mode->pixel_clock); +- +- /* Find suitable divisors. */ +- for (candp1 = 1; candp1 <= 8; candp1++) { +- for (candn = 5; candn <= 10; candn++) { +- u32 cur_frequency; +- u32 m; /* 77 - 131. */ +- u32 denom; /* 35 - 560. */ +- u32 current_delta; +- +- denom = candn * candp1 * 7; +- /* Doesnt overflow for up to +- 5000000 kHz = 5 GHz. */ +- m = (target_frequency * denom +- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; +- +- if (m < 77 || m > 131) +- continue; +- +- cur_frequency = (BASE_FREQUENCY * m) / denom; +- if (target_frequency > cur_frequency) +- current_delta = target_frequency - cur_frequency; +- else +- current_delta = cur_frequency - target_frequency; +- +- if (best_delta > current_delta) { +- best_delta = current_delta; +- pixel_n = candn; +- pixel_p1 = candp1; +- pixel_m2 = ((m + 3) % 5) + 7; +- pixel_m1 = (m - pixel_m2) / 5; ++ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; ++ target_frequency = mode->pixel_clock; ++ ++ /* Find suitable divisors, m1, m2, p1, n. */ ++ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ ++ /* should be closest to target frequency as possible */ ++ u32 candn, candm1, candm2, candp1; ++ for (candm1 = 8; candm1 <= 18; candm1++) { ++ for (candm2 = 3; candm2 <= 7; candm2++) { ++ for (candn = 1; candn <= 6; candn++) { ++ for (candp1 = 1; candp1 <= 8; candp1++) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * pixel_p2; ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if ((m < 70) || (m > 120)) ++ continue; ++ if (this_err < smallest_err) { ++ smallest_err = this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } + } + } + } + +- if (best_delta == 0xffffffff) { ++ if (smallest_err == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } +@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", +- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n +- / (pixel_p1 * 7)); ++ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / ++ (pixel_n + 2) / (pixel_p1 * pixel_p2)); + + #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(1), +- ((pixel_n - 2) << 16) +- | ((pixel_m1 - 2) << 8) | pixel_m2); ++ (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS +@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + | (conf->gpu_lvds_use_spread_spectrum_clock + ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV + : 0) +- | (pixel_p1 << 16) +- | (pixel_p1)); ++ | (0x10000 << pixel_p1)); + mdelay(1); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | +@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) +- | (pixel_p1 << 16) +- | (pixel_p1)); ++ | (0x10000 << pixel_p1)); + mdelay(1); + write32(pmmio + HTOTAL(1), + ((hactive + right_border + hblank - 1) << 16) +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0006-i945-gma.c-add-native-VGA-init.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0006-i945-gma.c-add-native-VGA-init.patch new file mode 100644 index 00000000..26eed5b4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0006-i945-gma.c-add-native-VGA-init.patch @@ -0,0 +1,241 @@ +From 7ed0951bcf59dfd8b1893232b674455ff8f03f83 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 5 Sep 2016 22:46:11 +0200 +Subject: [PATCH 2/2] i945/gma.c: add native VGA init + +This reuses the Intel Pineview native graphic initialization +to have output on the VGA connector of i945 devices. + +The behavior is the same as with the vendor VBIOS BLOB. +It uses the external VGA display if it is connected. + +Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/i945/gma.c | 196 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 194 insertions(+), 2 deletions(-) + +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index 3f0b5b4..ac19d5a 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase) + return 0; + } + +-static int intel_gma_init(struct northbridge_intel_i945_config *conf, ++static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, + unsigned int pphysbase, unsigned int piobase, + void *pmmio, unsigned int pgfx) + { +@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + #endif + return 0; + } ++ ++static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, ++ unsigned int pphysbase, unsigned int piobase, ++ void *pmmio, unsigned int pgfx) ++{ ++ int i; ++ u32 hactive, vactive; ++ u16 reg16; ++ u32 uma_size; ++ ++ printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", ++ (u32)pmmio, piobase, pphysbase); ++ ++ gtt_setup(pmmio); ++ ++ /* Disable VGA. */ ++ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); ++ ++ /* Disable pipes. */ ++ write32(pmmio + PIPECONF(0), 0); ++ write32(pmmio + PIPECONF(1), 0); ++ ++ write32(pmmio + INSTPM, 0x800); ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(pmmio + VGA0, 0x200074); ++ write32(pmmio + VGA1, 0x200074); ++ ++ write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); ++ write32(pmmio + DSPCLK_GATE_D, 0); ++ write32(pmmio + FW_BLC, 0x03060106); ++ write32(pmmio + FW_BLC2, 0x00000306); ++ ++ write32(pmmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(pmmio + 0x7041c, 0x0); ++ ++ write32(pmmio + DPLL_MD(0), 0x3); ++ write32(pmmio + DPLL_MD(1), 0x3); ++ write32(pmmio + DSPCNTR(1), 0x1000000); ++ write32(pmmio + PIPESRC(1), 0x027f01df); ++ ++ vga_misc_write(0x67); ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ // Disable screen memory to prevent garbage from appearing. ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(pmmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_VGA_MODE_DIS ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x400601 ++ ); ++ mdelay(1); ++ write32(pmmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_VGA_MODE_DIS ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x400601 ++ ); ++ ++ write32(pmmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(pmmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(pmmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(pmmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(pmmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(pmmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(pmmio + PF_WIN_POS(0), 0); ++ ++ write32(pmmio + PIPESRC(0), (639 << 16) | 399); ++ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(pmmio + PFIT_CONTROL, 0x0); ++ ++ mdelay(1); ++ ++ write32(pmmio + FDI_RX_CTL(0), 0x00002040); ++ mdelay(1); ++ write32(pmmio + FDI_RX_CTL(0), 0x80002050); ++ write32(pmmio + FDI_TX_CTL(0), 0x00044000); ++ mdelay(1); ++ write32(pmmio + FDI_TX_CTL(0), 0x80044000); ++ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(pmmio + VGACNTRL, 0x0); ++ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(pmmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(pmmio + DSPFW3, 0x7f3f00c1); ++ write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); ++ write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); ++ write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); ++ ++ /* Set up GTT. */ ++ ++ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); ++ uma_size = 0; ++ if (!(reg16 & 2)) { ++ uma_size = decode_igd_memory_size((reg16 >> 4) & 7); ++ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); ++ } ++ ++ for (i = 0; i < (uma_size - 256) / 4; i++) ++ { ++ outl((i << 2) | 1, piobase); ++ outl(pphysbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ /* Clear interrupts. */ ++ write32(pmmio + DEIIR, 0xffffffff); ++ write32(pmmio + SDEIIR, 0xffffffff); ++ write32(pmmio + IIR, 0xffffffff); ++ write32(pmmio + IMR, 0xffffffff); ++ write32(pmmio + EIR, 0xffffffff); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ return 0; ++ ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should have a correct header */ ++static int vga_connected(u8 *pmmio) { ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(pmmio + GMBUS0); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + #endif + + static void gma_func0_init(struct device *dev) +@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev) + ); + + int err; +- err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, ++ if (vga_connected(mmiobase)) ++ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, ++ iobase, mmiobase, graphics_base); ++ else ++ err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, + iobase, mmiobase, graphics_base); + if (err == 0) + gfx_set_init_done(1); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0007-i945-gma.c-generate-fake-VBT.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0007-i945-gma.c-generate-fake-VBT.patch new file mode 100644 index 00000000..6f0272fd --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0007-i945-gma.c-generate-fake-VBT.patch @@ -0,0 +1,43 @@ +From 60cc2c4532f63a40486b7c4e891fb87fb6d4ab7f Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Wed, 7 Sep 2016 22:10:57 +0200 +Subject: [PATCH] i945/gma.c: generate fake VBT + +This generates a fake VBT for the Intel i945 graphic device. +i945 supports both the mobile chipset 945gm (calistoga) +and the desktop chipset 945gc (lakeport), +which is why a VBT with a different id string +needs to be created for each target. + +The VBT id string is obtained from the vbios blob in the following way: +"strings vbios.bin | grep VBT". + +Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/i945/gma.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index 02caa0a..f0944b9 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -433,6 +433,15 @@ static void gma_func0_init(struct device *dev) + iobase, mmiobase, graphics_base); + if (err == 0) + gfx_set_init_done(1); ++ /* Linux relies on VBT for panel info. */ ++ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { ++ generate_fake_intel_oprom(&conf->gfx, dev, ++ "$VBT CALISTOGA "); ++ } ++ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { ++ generate_fake_intel_oprom(&conf->gfx, dev, ++ "$VBT LAKEPORT-G "); ++ } + #endif + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/reused.list b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/reused.list new file mode 100644 index 00000000..5dd5800f --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/reused.list @@ -0,0 +1,2 @@ +/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-i945-Enable-changing-VRAM-size.patch +/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-Enable-brightness-controls-native-graphic.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-Enable-brightness-controls-native-graphic.patch new file mode 100644 index 00000000..2e3ee65b --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-Enable-brightness-controls-native-graphic.patch @@ -0,0 +1,36 @@ +From 770021ce66a0fddebb9639c4df0696ecfca45488 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Mon, 15 Jun 2015 19:59:46 +0100 +Subject: [PATCH 4/9] lenovo/t60: Enable brightness controls (native graphics) + +This makes the Fn Home/End keys work for controlling the +brightness of the display. Value obtained by reading +BLC_PWM_CTL when running the VBIOS (option ROM). + +On i945 legacy brightness control is enabled by a single +bit in BLC_PWM_CTL. It's bit 16 or bit 0 (the other one +reverses polarity). Set the bit to enable brightness +controls. + +Change-Id: I22e261f2ce28ec81cd208a73e6311ec67146eb72 +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/mainboard/lenovo/t60/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb +index b28f1ad..9e6ce02 100644 +--- a/src/mainboard/lenovo/t60/devicetree.cb ++++ b/src/mainboard/lenovo/t60/devicetree.cb +@@ -26,7 +26,7 @@ chip northbridge/intel/i945 + + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "1" +- register "gpu_backlight" = "0x1280128" ++ register "gpu_backlight" = "0x58BF58BE" + + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch new file mode 100644 index 00000000..0b8e146a --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch @@ -0,0 +1,53 @@ +From bbd04909524d7b9fd2e2b4dbd804801bbde66e44 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Wed, 7 Sep 2016 21:16:21 +0200 +Subject: [PATCH] lenovo/t60: add hda_verb.c + +This creates a config for the Lenovo T60 sound card based +on values taken from vendor bios +(in /sys/class/sound/hwC0D0/init_pin_configs on linux 3.16). +The sound card configuration on the vendor bios is the same +as the one on the Lenovo x60. + +It improves the default behavior of the sound card: +- internal microphone is chosen by default +- when jack is inserted it is chosen instead of internal speaker + +Change-Id: I44e3eaac437fe4ad97ff2b0eb32d36b33222c09b +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/mainboard/lenovo/t60/hda_verb.c | 19 +++++++++++++++++-- + 1 file changed, 17 insertions(+), 2 deletions(-) + +diff --git a/src/mainboard/lenovo/t60/hda_verb.c b/src/mainboard/lenovo/t60/hda_verb.c +index 072a306..dee3e80 100644 +--- a/src/mainboard/lenovo/t60/hda_verb.c ++++ b/src/mainboard/lenovo/t60/hda_verb.c +@@ -1,7 +1,22 @@ + #include <device/azalia_device.h> + +-const u32 cim_verb_data[0] = {}; ++const u32 cim_verb_data[] = { ++ 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ ++ 0x17aa2025, /* Subsystem ID */ ++ 0x0000000b, /* Number of 4 dword sets */ + +-const u32 pc_beep_verbs[0] = {}; ++ AZALIA_SUBVENDOR(0x0, 0x17aa2025), + ++ AZALIA_PIN_CFG(0, 0x05, 0xc3014110), ++ AZALIA_PIN_CFG(0, 0x06, 0x4221401f), ++ AZALIA_PIN_CFG(0, 0x07, 0x591311f0), ++ AZALIA_PIN_CFG(0, 0x08, 0xc3a15020), ++ AZALIA_PIN_CFG(0, 0x09, 0x41813021), ++ AZALIA_PIN_CFG(0, 0x0a, 0x014470f0), ++ AZALIA_PIN_CFG(0, 0x16, 0x59f311f0), ++ AZALIA_PIN_CFG(0, 0x17, 0x59931122), ++ AZALIA_PIN_CFG(0, 0x18, 0x41a19023), ++ AZALIA_PIN_CFG(0, 0x19, 0x9933e12e) ++}; ++const u32 pc_beep_verbs[0] = {}; + AZALIA_ARRAY_SIZES; +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch new file mode 100644 index 00000000..86bd6cb0 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch @@ -0,0 +1,174 @@ +From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Fri, 2 Sep 2016 22:35:32 +0200 +Subject: [PATCH] i945/gma.c use latest linux code to calculate divisors. + +The code to compute n, m1, m2, p1 divisors is not correct in coreboot and +on some targets hits a working mode at lower refresh rate, which is why +display is working on some targets. +This patch also fixes reference frequency. + +This patch reuses linux code to correctly compute divisors. + +The result is that some previously not working displays (Lenovo T60 with +1024x786, 1400x1050, 2048x1536) + +TESTED on T60 with 1024x786. + +Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- + 1 file changed, 38 insertions(+), 44 deletions(-) + +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index 02caa0a..3f0b5b4 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -26,6 +26,8 @@ + #include <string.h> + #include <pc80/vga.h> + #include <pc80/vga_io.h> ++#include <commonlib/helpers.h> ++ + + #include "i945.h" + #include "chip.h" +@@ -43,7 +45,7 @@ + #define PGETBL_CTL 0x2020 + #define PGETBL_ENABLED 0x00000001 + +-#define BASE_FREQUENCY 120000 ++#define BASE_FREQUENCY 100000 + + #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + +@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + u8 edid_data[128]; + unsigned long temp; + int hpolarity, vpolarity; +- u32 candp1, candn; +- u32 best_delta = 0xffffffff; ++ u32 smallest_err = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; ++ u32 pixel_p2; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; +@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); + write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); + +- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock +- : (2 * mode->pixel_clock); +- +- /* Find suitable divisors. */ +- for (candp1 = 1; candp1 <= 8; candp1++) { +- for (candn = 5; candn <= 10; candn++) { +- u32 cur_frequency; +- u32 m; /* 77 - 131. */ +- u32 denom; /* 35 - 560. */ +- u32 current_delta; +- +- denom = candn * candp1 * 7; +- /* Doesnt overflow for up to +- 5000000 kHz = 5 GHz. */ +- m = (target_frequency * denom +- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; +- +- if (m < 77 || m > 131) +- continue; +- +- cur_frequency = (BASE_FREQUENCY * m) / denom; +- if (target_frequency > cur_frequency) +- current_delta = target_frequency - cur_frequency; +- else +- current_delta = cur_frequency - target_frequency; +- +- if (best_delta > current_delta) { +- best_delta = current_delta; +- pixel_n = candn; +- pixel_p1 = candp1; +- pixel_m2 = ((m + 3) % 5) + 7; +- pixel_m1 = (m - pixel_m2) / 5; ++ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; ++ target_frequency = mode->pixel_clock; ++ ++ /* Find suitable divisors, m1, m2, p1, n. */ ++ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ ++ /* should be closest to target frequency as possible */ ++ u32 candn, candm1, candm2, candp1; ++ for (candm1 = 8; candm1 <= 18; candm1++) { ++ for (candm2 = 3; candm2 <= 7; candm2++) { ++ for (candn = 1; candn <= 6; candn++) { ++ for (candp1 = 1; candp1 <= 8; candp1++) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * pixel_p2; ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if ((m < 70) || (m > 120)) ++ continue; ++ if (this_err < smallest_err) { ++ smallest_err = this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } + } + } + } + +- if (best_delta == 0xffffffff) { ++ if (smallest_err == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } +@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", +- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n +- / (pixel_p1 * 7)); ++ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / ++ (pixel_n + 2) / (pixel_p1 * pixel_p2)); + + #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(1), +- ((pixel_n - 2) << 16) +- | ((pixel_m1 - 2) << 8) | pixel_m2); ++ (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS +@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + | (conf->gpu_lvds_use_spread_spectrum_clock + ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV + : 0) +- | (pixel_p1 << 16) +- | (pixel_p1)); ++ | (0x10000 << pixel_p1)); + mdelay(1); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | +@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) +- | (pixel_p1 << 16) +- | (pixel_p1)); ++ | (0x10000 << pixel_p1)); + mdelay(1); + write32(pmmio + HTOTAL(1), + ((hactive + right_border + hblank - 1) << 16) +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch new file mode 100644 index 00000000..884b2829 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch @@ -0,0 +1,174 @@ +From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Fri, 2 Sep 2016 22:35:32 +0200 +Subject: [PATCH 1/2] i945/gma.c use latest linux code to calculate divisors. + +The code to compute n, m1, m2, p1 divisors is not correct in coreboot and +on some targets hits a working mode at lower refresh rate, which is why +display is working on some targets. +This patch also fixes reference frequency. + +This patch reuses linux code to correctly compute divisors. + +The result is that some previously not working displays (Lenovo T60 with +1024x786, 1400x1050, 2048x1536) + +TESTED on T60 with 1024x786. + +Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- + 1 file changed, 38 insertions(+), 44 deletions(-) + +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index 02caa0a..3f0b5b4 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -26,6 +26,8 @@ + #include <string.h> + #include <pc80/vga.h> + #include <pc80/vga_io.h> ++#include <commonlib/helpers.h> ++ + + #include "i945.h" + #include "chip.h" +@@ -43,7 +45,7 @@ + #define PGETBL_CTL 0x2020 + #define PGETBL_ENABLED 0x00000001 + +-#define BASE_FREQUENCY 120000 ++#define BASE_FREQUENCY 100000 + + #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + +@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + u8 edid_data[128]; + unsigned long temp; + int hpolarity, vpolarity; +- u32 candp1, candn; +- u32 best_delta = 0xffffffff; ++ u32 smallest_err = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; ++ u32 pixel_p2; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; +@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); + write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); + +- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock +- : (2 * mode->pixel_clock); +- +- /* Find suitable divisors. */ +- for (candp1 = 1; candp1 <= 8; candp1++) { +- for (candn = 5; candn <= 10; candn++) { +- u32 cur_frequency; +- u32 m; /* 77 - 131. */ +- u32 denom; /* 35 - 560. */ +- u32 current_delta; +- +- denom = candn * candp1 * 7; +- /* Doesnt overflow for up to +- 5000000 kHz = 5 GHz. */ +- m = (target_frequency * denom +- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; +- +- if (m < 77 || m > 131) +- continue; +- +- cur_frequency = (BASE_FREQUENCY * m) / denom; +- if (target_frequency > cur_frequency) +- current_delta = target_frequency - cur_frequency; +- else +- current_delta = cur_frequency - target_frequency; +- +- if (best_delta > current_delta) { +- best_delta = current_delta; +- pixel_n = candn; +- pixel_p1 = candp1; +- pixel_m2 = ((m + 3) % 5) + 7; +- pixel_m1 = (m - pixel_m2) / 5; ++ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; ++ target_frequency = mode->pixel_clock; ++ ++ /* Find suitable divisors, m1, m2, p1, n. */ ++ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ ++ /* should be closest to target frequency as possible */ ++ u32 candn, candm1, candm2, candp1; ++ for (candm1 = 8; candm1 <= 18; candm1++) { ++ for (candm2 = 3; candm2 <= 7; candm2++) { ++ for (candn = 1; candn <= 6; candn++) { ++ for (candp1 = 1; candp1 <= 8; candp1++) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * pixel_p2; ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if ((m < 70) || (m > 120)) ++ continue; ++ if (this_err < smallest_err) { ++ smallest_err = this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } + } + } + } + +- if (best_delta == 0xffffffff) { ++ if (smallest_err == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } +@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", +- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n +- / (pixel_p1 * 7)); ++ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / ++ (pixel_n + 2) / (pixel_p1 * pixel_p2)); + + #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(1), +- ((pixel_n - 2) << 16) +- | ((pixel_m1 - 2) << 8) | pixel_m2); ++ (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS +@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + | (conf->gpu_lvds_use_spread_spectrum_clock + ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV + : 0) +- | (pixel_p1 << 16) +- | (pixel_p1)); ++ | (0x10000 << pixel_p1)); + mdelay(1); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | +@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) +- | (pixel_p1 << 16) +- | (pixel_p1)); ++ | (0x10000 << pixel_p1)); + mdelay(1); + write32(pmmio + HTOTAL(1), + ((hactive + right_border + hblank - 1) << 16) +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0006-i945-gma.c-add-native-VGA-init.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0006-i945-gma.c-add-native-VGA-init.patch new file mode 100644 index 00000000..26eed5b4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0006-i945-gma.c-add-native-VGA-init.patch @@ -0,0 +1,241 @@ +From 7ed0951bcf59dfd8b1893232b674455ff8f03f83 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 5 Sep 2016 22:46:11 +0200 +Subject: [PATCH 2/2] i945/gma.c: add native VGA init + +This reuses the Intel Pineview native graphic initialization +to have output on the VGA connector of i945 devices. + +The behavior is the same as with the vendor VBIOS BLOB. +It uses the external VGA display if it is connected. + +Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/i945/gma.c | 196 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 194 insertions(+), 2 deletions(-) + +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index 3f0b5b4..ac19d5a 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase) + return 0; + } + +-static int intel_gma_init(struct northbridge_intel_i945_config *conf, ++static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, + unsigned int pphysbase, unsigned int piobase, + void *pmmio, unsigned int pgfx) + { +@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + #endif + return 0; + } ++ ++static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, ++ unsigned int pphysbase, unsigned int piobase, ++ void *pmmio, unsigned int pgfx) ++{ ++ int i; ++ u32 hactive, vactive; ++ u16 reg16; ++ u32 uma_size; ++ ++ printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", ++ (u32)pmmio, piobase, pphysbase); ++ ++ gtt_setup(pmmio); ++ ++ /* Disable VGA. */ ++ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); ++ ++ /* Disable pipes. */ ++ write32(pmmio + PIPECONF(0), 0); ++ write32(pmmio + PIPECONF(1), 0); ++ ++ write32(pmmio + INSTPM, 0x800); ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(pmmio + VGA0, 0x200074); ++ write32(pmmio + VGA1, 0x200074); ++ ++ write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); ++ write32(pmmio + DSPCLK_GATE_D, 0); ++ write32(pmmio + FW_BLC, 0x03060106); ++ write32(pmmio + FW_BLC2, 0x00000306); ++ ++ write32(pmmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(pmmio + 0x7041c, 0x0); ++ ++ write32(pmmio + DPLL_MD(0), 0x3); ++ write32(pmmio + DPLL_MD(1), 0x3); ++ write32(pmmio + DSPCNTR(1), 0x1000000); ++ write32(pmmio + PIPESRC(1), 0x027f01df); ++ ++ vga_misc_write(0x67); ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ // Disable screen memory to prevent garbage from appearing. ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(pmmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_VGA_MODE_DIS ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x400601 ++ ); ++ mdelay(1); ++ write32(pmmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_VGA_MODE_DIS ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x400601 ++ ); ++ ++ write32(pmmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(pmmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(pmmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(pmmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(pmmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(pmmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(pmmio + PF_WIN_POS(0), 0); ++ ++ write32(pmmio + PIPESRC(0), (639 << 16) | 399); ++ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(pmmio + PFIT_CONTROL, 0x0); ++ ++ mdelay(1); ++ ++ write32(pmmio + FDI_RX_CTL(0), 0x00002040); ++ mdelay(1); ++ write32(pmmio + FDI_RX_CTL(0), 0x80002050); ++ write32(pmmio + FDI_TX_CTL(0), 0x00044000); ++ mdelay(1); ++ write32(pmmio + FDI_TX_CTL(0), 0x80044000); ++ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(pmmio + VGACNTRL, 0x0); ++ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(pmmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(pmmio + DSPFW3, 0x7f3f00c1); ++ write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); ++ write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); ++ write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); ++ ++ /* Set up GTT. */ ++ ++ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); ++ uma_size = 0; ++ if (!(reg16 & 2)) { ++ uma_size = decode_igd_memory_size((reg16 >> 4) & 7); ++ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); ++ } ++ ++ for (i = 0; i < (uma_size - 256) / 4; i++) ++ { ++ outl((i << 2) | 1, piobase); ++ outl(pphysbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ /* Clear interrupts. */ ++ write32(pmmio + DEIIR, 0xffffffff); ++ write32(pmmio + SDEIIR, 0xffffffff); ++ write32(pmmio + IIR, 0xffffffff); ++ write32(pmmio + IMR, 0xffffffff); ++ write32(pmmio + EIR, 0xffffffff); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ return 0; ++ ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should have a correct header */ ++static int vga_connected(u8 *pmmio) { ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(pmmio + GMBUS0); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + #endif + + static void gma_func0_init(struct device *dev) +@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev) + ); + + int err; +- err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, ++ if (vga_connected(mmiobase)) ++ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, ++ iobase, mmiobase, graphics_base); ++ else ++ err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, + iobase, mmiobase, graphics_base); + if (err == 0) + gfx_set_init_done(1); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0007-i945-gma.c-generate-fake-VBT.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0007-i945-gma.c-generate-fake-VBT.patch new file mode 100644 index 00000000..6f0272fd --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0007-i945-gma.c-generate-fake-VBT.patch @@ -0,0 +1,43 @@ +From 60cc2c4532f63a40486b7c4e891fb87fb6d4ab7f Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Wed, 7 Sep 2016 22:10:57 +0200 +Subject: [PATCH] i945/gma.c: generate fake VBT + +This generates a fake VBT for the Intel i945 graphic device. +i945 supports both the mobile chipset 945gm (calistoga) +and the desktop chipset 945gc (lakeport), +which is why a VBT with a different id string +needs to be created for each target. + +The VBT id string is obtained from the vbios blob in the following way: +"strings vbios.bin | grep VBT". + +Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/i945/gma.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index 02caa0a..f0944b9 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -433,6 +433,15 @@ static void gma_func0_init(struct device *dev) + iobase, mmiobase, graphics_base); + if (err == 0) + gfx_set_init_done(1); ++ /* Linux relies on VBT for panel info. */ ++ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { ++ generate_fake_intel_oprom(&conf->gfx, dev, ++ "$VBT CALISTOGA "); ++ } ++ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { ++ generate_fake_intel_oprom(&conf->gfx, dev, ++ "$VBT LAKEPORT-G "); ++ } + #endif + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/INFO b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/INFO new file mode 100644 index 00000000..cb543aae --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/INFO @@ -0,0 +1,3 @@ +printf "lenovo/t60: Enable brightness controls (native graphics)\n" +git am "../resources/libreboot/patch/misc/0004-lenovo-t60-Enable-brightness-controls-native-graphic.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/52/10552/2 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/reused.list b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/reused.list new file mode 100644 index 00000000..157e1cf6 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/reused.list @@ -0,0 +1,3 @@ +/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-i945-Enable-changing-VRAM-size.patch +/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch new file mode 100644 index 00000000..6f8b5307 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch @@ -0,0 +1,88 @@ +From 1024b5e6c476dcc195dca742746735277f63236b Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Mon, 13 Oct 2014 00:14:53 +0100 +Subject: [PATCH 5/9] NOTFORMERGE: ec/lenovo/h8: + wlan/trackpoint/touchpad/bluetooth/wwan + +Permanently enable them. + +Change-Id: Ic76ab9ab9c865f30312378e18af58bece6c3260a +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/ec/lenovo/h8/h8.c | 21 +++++++++++---------- + src/ec/lenovo/pmh7/pmh7.c | 11 ++++------- + 2 files changed, 15 insertions(+), 17 deletions(-) + +diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c +index 2cafc88..a6cb6b6 100644 +--- a/src/ec/lenovo/h8/h8.c ++++ b/src/ec/lenovo/h8/h8.c +@@ -255,9 +255,11 @@ static void h8_enable(struct device *dev) + + ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); + +- if (get_option(&val, "wlan") != CB_SUCCESS) +- val = 1; +- h8_wlan_enable(val); ++ // Permanently enable wifi ++ // Intel wifi could be a security risk because it uses firmware. Wlan chip has DMA ++ // and could leak data over a side-channel. Using another manufacturer is recommended. ++ // see http://libreboot.org/docs/index.html#recommended_wifi ++ h8_wlan_enable(1); + + h8_trackpoint_enable(1); + h8_usb_power_enable(1); +@@ -265,14 +267,13 @@ static void h8_enable(struct device *dev) + if (get_option(&val, "volume") == CB_SUCCESS) + ec_write(H8_VOLUME_CONTROL, val); + +- if (get_option(&val, "bluetooth") != CB_SUCCESS) +- val = 1; +- h8_bluetooth_enable(val); +- +- if (get_option(&val, "wwan") != CB_SUCCESS) +- val = 1; ++ // Permanently enable bluetooth. ++ // NOTE: bluetooth is a potential security risk. Physical removal of the bluetooth module is recommended. ++ h8_bluetooth_enable(1); + +- h8_wwan_enable(val); ++ // Permanently enable wwan. ++ // NOTE: wwan is a security risk (remove access plus DMA). Physical removal of both the wwan and sim card is recommended. ++ h8_wwan_enable(1); + + if (conf->has_uwb) { + if (get_option(&val, "uwb") != CB_SUCCESS) +diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c +index cc6e891..38aef16 100644 +--- a/src/ec/lenovo/pmh7/pmh7.c ++++ b/src/ec/lenovo/pmh7/pmh7.c +@@ -106,7 +106,6 @@ static void enable_dev(struct device *dev) + { + struct ec_lenovo_pmh7_config *conf = dev->chip_info; + struct resource *resource; +- u8 val; + + resource = new_resource(dev, EC_LENOVO_PMH7_INDEX); + resource->flags = IORESOURCE_IO | IORESOURCE_FIXED; +@@ -118,13 +117,11 @@ static void enable_dev(struct device *dev) + pmh7_backlight_enable(conf->backlight_enable); + pmh7_dock_event_enable(conf->dock_event_enable); + +- if (get_option(&val, "touchpad") != CB_SUCCESS) +- val = 1; +- pmh7_touchpad_enable(val); ++ // Permanently enable touchpad ++ pmh7_touchpad_enable(1); + +- if (get_option(&val, "trackpoint") != CB_SUCCESS) +- val = 1; +- pmh7_trackpoint_enable(val); ++ // Permanently enable trackpoint ++ pmh7_trackpoint_enable(1); + } + + struct chip_operations ec_lenovo_pmh7_ops = { +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-i945-Enable-changing-VRAM-size.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-i945-Enable-changing-VRAM-size.patch new file mode 100644 index 00000000..ce1d37c0 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-i945-Enable-changing-VRAM-size.patch @@ -0,0 +1,158 @@ +From 44b3d02a49bc25dc8e9119a11bd948db2c37a931 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sun, 15 May 2016 02:17:12 +0200 +Subject: [PATCH] i945: Enable changing VRAM size + +On i945 the vram size was the default 8mb. It was also possible +to set it 1mb or 0mb hardcoding the GGC register in early_init.c + +The intel documentation on i945 only documents those three options. +They are set using 3 bits. The documententation also makes mention +of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it. + +The other non documented (straight forward) bit combinations allows +to change the VRAM size to those other states. + +Change-Id: I5e510e81322a4c8315c01b7963ac4b5f7f58a17e +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> + +diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig +index 6e8d35b..484ed78 100644 +--- a/src/northbridge/intel/i945/Kconfig ++++ b/src/northbridge/intel/i945/Kconfig +@@ -72,3 +72,56 @@ config CHECK_SLFRCS_ON_RESUME + effectively making it impossible to resume. + + endif ++ ++config VRAM_CHOICE ++ bool ++choice ++ prompt "VRAM Size" ++ depends on NORTHBRIDGE_INTEL_I945 ++ default VRAM_SIZE_8MB ++ help ++ Set the size of vram that the integrated graphic device can use ++ for a framebuffer. ++ ++config VRAM_SIZE_1MB ++ bool "1 MB" ++ help ++ Set VRAM size to 1MB. ++config VRAM_SIZE_4MB ++ bool "4 MB" ++ help ++ Set VRAM size to 4MB. ++config VRAM_SIZE_8MB ++ bool "8 MB" ++ help ++ Set VRAM size to 8MB. ++config VRAM_SIZE_16MB ++ bool "16 MB" ++ help ++ Set VRAM size to 16MB. ++config VRAM_SIZE_32MB ++ bool "32 MB" ++ help ++ Set VRAM size to 32MB. ++config VRAM_SIZE_48MB ++ bool "48 MB" ++ help ++ Set VRAM size to 48MB. ++config VRAM_SIZE_64MB ++ bool "64 MB" ++ help ++ Set VRAM size to 64MB. ++ ++endchoice ++ ++config VRAM_SIZE ++ hex ++ default 0x10 if VRAM_SIZE_1MB ++ default 0x20 if VRAM_SIZE_4MB ++ default 0x30 if VRAM_SIZE_8MB ++ default 0x40 if VRAM_SIZE_16MB ++ default 0x50 if VRAM_SIZE_32MB ++ default 0x60 if VRAM_SIZE_48MB ++ default 0x70 if VRAM_SIZE_64MB ++ help ++ map the vram sizes to an integer. +diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c +index 475e88a..bd062ad 100644 +--- a/src/northbridge/intel/i945/early_init.c ++++ b/src/northbridge/intel/i945/early_init.c +@@ -177,11 +177,8 @@ static void i945_setup_bars(void) + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); + +- /* Hardware default is 8MB UMA. If someone wants to make this a +- * CMOS or compile time option, send a patch. +- * pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x30); +- */ +- ++ /* Sets up VRAM size from the build option VRAM_SIZE */ ++ pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, CONFIG_VRAM_SIZE); + /* Set C0000-FFFFF to access RAM on both reads and writes */ + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index df13ef4..f853cc8 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -359,9 +359,24 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + case 1: + uma_size = 1024; + break; ++ case 2: ++ uma_size = 4096; ++ break; + case 3: + uma_size = 8192; + break; ++ case 4: ++ uma_size = 16384; ++ break; ++ case 5: ++ uma_size = 32768; ++ break; ++ case 6: ++ uma_size = 49152; ++ break; ++ case 7: ++ uma_size = 65536; ++ break; + } + + printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); +diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c +index 514f88c..4be9827 100644 +--- a/src/northbridge/intel/i945/northbridge.c ++++ b/src/northbridge/intel/i945/northbridge.c +@@ -112,9 +112,24 @@ static void pci_domain_set_resources(device_t dev) + case 1: + uma_size = 1024; + break; ++ case 2: ++ uma_size = 4096; ++ break; + case 3: + uma_size = 8192; + break; ++ case 4: ++ uma_size = 16384; ++ break; ++ case 5: ++ uma_size = 32768; ++ break; ++ case 6: ++ uma_size = 49152; ++ break; ++ case 7: ++ uma_size = 65536; ++ break; + } + + printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); +-- +2.8.2 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-lenovo-x60-add-hda_verb.c.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-lenovo-x60-add-hda_verb.c.patch new file mode 100644 index 00000000..80eda28b --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-lenovo-x60-add-hda_verb.c.patch @@ -0,0 +1,65 @@ +From 4f3452fc544d4e799445c3271b1022496932473c Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Fri, 3 Jun 2016 18:37:38 +0200 +Subject: [PATCH] lenovo/x60: add hda_verb.c + +This creates a config for the x60 audio based +on values taken from vendor bios. + +What is improved: +- internal microphone is chosen by default +- when jack is inserted it chosen instead of internal speaker + +Before this had to be done manually. + +Change-Id: Id3b700fd84905a72cc1f69e7d8bfa6145f231756 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> + +diff --git a/src/mainboard/lenovo/x60/hda_verb.c b/src/mainboard/lenovo/x60/hda_verb.c +index 072a306..c4b1f3a 100644 +--- a/src/mainboard/lenovo/x60/hda_verb.c ++++ b/src/mainboard/lenovo/x60/hda_verb.c +@@ -1,7 +1,38 @@ ++/* ++ * This file is part of the coreboot project. ++ * ++ * Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; version 2 of ++ * the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ + #include <device/azalia_device.h> + +-const u32 cim_verb_data[0] = {}; ++const u32 cim_verb_data[] = { ++ 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ ++ 0x17aa2025, /* Subsystem ID */ ++ 0x0000000b, /* Number of 4 dword sets */ + +-const u32 pc_beep_verbs[0] = {}; ++ AZALIA_SUBVENDOR(0x0, 0x17aa2025), + ++ AZALIA_PIN_CFG(0, 0x05, 0xc3014110), ++ AZALIA_PIN_CFG(0, 0x06, 0x4221401f), ++ AZALIA_PIN_CFG(0, 0x07, 0x591311f0), ++ AZALIA_PIN_CFG(0, 0x08, 0xc3a15020), ++ AZALIA_PIN_CFG(0, 0x09, 0x41813021), ++ AZALIA_PIN_CFG(0, 0x0a, 0x014470f0), ++ AZALIA_PIN_CFG(0, 0x16, 0x59f311f0), ++ AZALIA_PIN_CFG(0, 0x17, 0x59931122), ++ AZALIA_PIN_CFG(0, 0x18, 0x41a19023), ++ AZALIA_PIN_CFG(0, 0x19, 0x9933e12e) ++}; ++const u32 pc_beep_verbs[0] = {}; + AZALIA_ARRAY_SIZES; +-- +2.8.3 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0002-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0002-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch new file mode 100644 index 00000000..7470dd60 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0002-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch @@ -0,0 +1,31 @@ +From e4b5b65c93122126344771f2042f8d7a3468be19 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Mon, 22 Jun 2015 17:37:06 +0100 +Subject: [PATCH 3/9] lenovo/x60: use correct BLC_PWM_CTL value + +Bit 16 in BLC_PWM_CTL enables brightness controls, but the +current value is generic. Use the proper value, obtained +by reading BLC_PWM_CTL while running the VBIOS. + +Change-Id: Ib273359e1c285b405a9bb26fc217c2f7e255b99f +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/mainboard/lenovo/x60/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb +index b4d1144..4d62116 100644 +--- a/src/mainboard/lenovo/x60/devicetree.cb ++++ b/src/mainboard/lenovo/x60/devicetree.cb +@@ -26,7 +26,7 @@ chip northbridge/intel/i945 + + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "1" +- register "gpu_backlight" = "0x1290128" ++ register "gpu_backlight" = "0x879F879E" + + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch new file mode 100644 index 00000000..14f809a9 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch @@ -0,0 +1,50 @@ +From 483bbb3ec7965ca2416fda9e11687bcd655d078d Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Tue, 31 May 2016 16:51:59 +0200 +Subject: [PATCH] model_6ex: enable C2E, C4E, dynamic lvl 2 cache. + +Change-Id: Ie538d2145640c7b50ac0a0fa432d98ae2c4be060 + +diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c +index 6fa6d3a..8ff276a 100644 +--- a/src/cpu/intel/model_6ex/model_6ex_init.c ++++ b/src/cpu/intel/model_6ex/model_6ex_init.c +@@ -67,9 +67,10 @@ static void configure_c_states(void) + + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr.lo |= (1 << 15); // config lock until next reset. ++ msr.lo |= (1 << 14); // Deeper Sleep + msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States + msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk +- // TODO Do we want Deep C4 and Dynamic L2 shrinking? ++ msr.lo |= (1 << 3); // Dynamic L2 + + /* Number of supported C-States */ + msr.lo &= ~7; +@@ -94,16 +95,20 @@ static void configure_misc(void) + msr_t msr; + + msr = rdmsr(IA32_MISC_ENABLE); +- msr.lo |= (1 << 3); /* TM1 enable */ ++ msr.lo |= (1 << 3); /* TM1 enable */ + msr.lo |= (1 << 13); /* TM2 enable */ + msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ + + msr.lo |= (1 << 10); /* FERR# multiplexing */ + +- // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ ++ /* Enable C2E */ ++ msr.lo |= (1 << 26); ++ ++ /* Enable C4E */ ++ msr.hi |= (1 << (32 - 32)); // C4E ++ msr.hi |= (1 << (33 - 32)); // Hard C4E + +- // TODO Do we want Deep C4 and Dynamic L2 shrinking? + wrmsr(IA32_MISC_ENABLE, msr); + + msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ +-- +2.8.3 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch new file mode 100644 index 00000000..884b2829 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch @@ -0,0 +1,174 @@ +From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Fri, 2 Sep 2016 22:35:32 +0200 +Subject: [PATCH 1/2] i945/gma.c use latest linux code to calculate divisors. + +The code to compute n, m1, m2, p1 divisors is not correct in coreboot and +on some targets hits a working mode at lower refresh rate, which is why +display is working on some targets. +This patch also fixes reference frequency. + +This patch reuses linux code to correctly compute divisors. + +The result is that some previously not working displays (Lenovo T60 with +1024x786, 1400x1050, 2048x1536) + +TESTED on T60 with 1024x786. + +Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- + 1 file changed, 38 insertions(+), 44 deletions(-) + +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index 02caa0a..3f0b5b4 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -26,6 +26,8 @@ + #include <string.h> + #include <pc80/vga.h> + #include <pc80/vga_io.h> ++#include <commonlib/helpers.h> ++ + + #include "i945.h" + #include "chip.h" +@@ -43,7 +45,7 @@ + #define PGETBL_CTL 0x2020 + #define PGETBL_ENABLED 0x00000001 + +-#define BASE_FREQUENCY 120000 ++#define BASE_FREQUENCY 100000 + + #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + +@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + u8 edid_data[128]; + unsigned long temp; + int hpolarity, vpolarity; +- u32 candp1, candn; +- u32 best_delta = 0xffffffff; ++ u32 smallest_err = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; ++ u32 pixel_p2; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; +@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); + write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); + +- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock +- : (2 * mode->pixel_clock); +- +- /* Find suitable divisors. */ +- for (candp1 = 1; candp1 <= 8; candp1++) { +- for (candn = 5; candn <= 10; candn++) { +- u32 cur_frequency; +- u32 m; /* 77 - 131. */ +- u32 denom; /* 35 - 560. */ +- u32 current_delta; +- +- denom = candn * candp1 * 7; +- /* Doesnt overflow for up to +- 5000000 kHz = 5 GHz. */ +- m = (target_frequency * denom +- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; +- +- if (m < 77 || m > 131) +- continue; +- +- cur_frequency = (BASE_FREQUENCY * m) / denom; +- if (target_frequency > cur_frequency) +- current_delta = target_frequency - cur_frequency; +- else +- current_delta = cur_frequency - target_frequency; +- +- if (best_delta > current_delta) { +- best_delta = current_delta; +- pixel_n = candn; +- pixel_p1 = candp1; +- pixel_m2 = ((m + 3) % 5) + 7; +- pixel_m1 = (m - pixel_m2) / 5; ++ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; ++ target_frequency = mode->pixel_clock; ++ ++ /* Find suitable divisors, m1, m2, p1, n. */ ++ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ ++ /* should be closest to target frequency as possible */ ++ u32 candn, candm1, candm2, candp1; ++ for (candm1 = 8; candm1 <= 18; candm1++) { ++ for (candm2 = 3; candm2 <= 7; candm2++) { ++ for (candn = 1; candn <= 6; candn++) { ++ for (candp1 = 1; candp1 <= 8; candp1++) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * pixel_p2; ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if ((m < 70) || (m > 120)) ++ continue; ++ if (this_err < smallest_err) { ++ smallest_err = this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } + } + } + } + +- if (best_delta == 0xffffffff) { ++ if (smallest_err == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } +@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", +- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n +- / (pixel_p1 * 7)); ++ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / ++ (pixel_n + 2) / (pixel_p1 * pixel_p2)); + + #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(1), +- ((pixel_n - 2) << 16) +- | ((pixel_m1 - 2) << 8) | pixel_m2); ++ (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS +@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + | (conf->gpu_lvds_use_spread_spectrum_clock + ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV + : 0) +- | (pixel_p1 << 16) +- | (pixel_p1)); ++ | (0x10000 << pixel_p1)); + mdelay(1); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | +@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) +- | (pixel_p1 << 16) +- | (pixel_p1)); ++ | (0x10000 << pixel_p1)); + mdelay(1); + write32(pmmio + HTOTAL(1), + ((hactive + right_border + hblank - 1) << 16) +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch new file mode 100644 index 00000000..26eed5b4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch @@ -0,0 +1,241 @@ +From 7ed0951bcf59dfd8b1893232b674455ff8f03f83 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 5 Sep 2016 22:46:11 +0200 +Subject: [PATCH 2/2] i945/gma.c: add native VGA init + +This reuses the Intel Pineview native graphic initialization +to have output on the VGA connector of i945 devices. + +The behavior is the same as with the vendor VBIOS BLOB. +It uses the external VGA display if it is connected. + +Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/i945/gma.c | 196 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 194 insertions(+), 2 deletions(-) + +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index 3f0b5b4..ac19d5a 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase) + return 0; + } + +-static int intel_gma_init(struct northbridge_intel_i945_config *conf, ++static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, + unsigned int pphysbase, unsigned int piobase, + void *pmmio, unsigned int pgfx) + { +@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + #endif + return 0; + } ++ ++static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, ++ unsigned int pphysbase, unsigned int piobase, ++ void *pmmio, unsigned int pgfx) ++{ ++ int i; ++ u32 hactive, vactive; ++ u16 reg16; ++ u32 uma_size; ++ ++ printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", ++ (u32)pmmio, piobase, pphysbase); ++ ++ gtt_setup(pmmio); ++ ++ /* Disable VGA. */ ++ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); ++ ++ /* Disable pipes. */ ++ write32(pmmio + PIPECONF(0), 0); ++ write32(pmmio + PIPECONF(1), 0); ++ ++ write32(pmmio + INSTPM, 0x800); ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(pmmio + VGA0, 0x200074); ++ write32(pmmio + VGA1, 0x200074); ++ ++ write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); ++ write32(pmmio + DSPCLK_GATE_D, 0); ++ write32(pmmio + FW_BLC, 0x03060106); ++ write32(pmmio + FW_BLC2, 0x00000306); ++ ++ write32(pmmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(pmmio + 0x7041c, 0x0); ++ ++ write32(pmmio + DPLL_MD(0), 0x3); ++ write32(pmmio + DPLL_MD(1), 0x3); ++ write32(pmmio + DSPCNTR(1), 0x1000000); ++ write32(pmmio + PIPESRC(1), 0x027f01df); ++ ++ vga_misc_write(0x67); ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ // Disable screen memory to prevent garbage from appearing. ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(pmmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_VGA_MODE_DIS ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x400601 ++ ); ++ mdelay(1); ++ write32(pmmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_VGA_MODE_DIS ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x400601 ++ ); ++ ++ write32(pmmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(pmmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(pmmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(pmmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(pmmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(pmmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(pmmio + PF_WIN_POS(0), 0); ++ ++ write32(pmmio + PIPESRC(0), (639 << 16) | 399); ++ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(pmmio + PFIT_CONTROL, 0x0); ++ ++ mdelay(1); ++ ++ write32(pmmio + FDI_RX_CTL(0), 0x00002040); ++ mdelay(1); ++ write32(pmmio + FDI_RX_CTL(0), 0x80002050); ++ write32(pmmio + FDI_TX_CTL(0), 0x00044000); ++ mdelay(1); ++ write32(pmmio + FDI_TX_CTL(0), 0x80044000); ++ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(pmmio + VGACNTRL, 0x0); ++ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(pmmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(pmmio + DSPFW3, 0x7f3f00c1); ++ write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); ++ write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); ++ write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); ++ ++ /* Set up GTT. */ ++ ++ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); ++ uma_size = 0; ++ if (!(reg16 & 2)) { ++ uma_size = decode_igd_memory_size((reg16 >> 4) & 7); ++ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); ++ } ++ ++ for (i = 0; i < (uma_size - 256) / 4; i++) ++ { ++ outl((i << 2) | 1, piobase); ++ outl(pphysbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ /* Clear interrupts. */ ++ write32(pmmio + DEIIR, 0xffffffff); ++ write32(pmmio + SDEIIR, 0xffffffff); ++ write32(pmmio + IIR, 0xffffffff); ++ write32(pmmio + IMR, 0xffffffff); ++ write32(pmmio + EIR, 0xffffffff); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ return 0; ++ ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should have a correct header */ ++static int vga_connected(u8 *pmmio) { ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(pmmio + GMBUS0); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + #endif + + static void gma_func0_init(struct device *dev) +@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev) + ); + + int err; +- err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, ++ if (vga_connected(mmiobase)) ++ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, ++ iobase, mmiobase, graphics_base); ++ else ++ err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, + iobase, mmiobase, graphics_base); + if (err == 0) + gfx_set_init_done(1); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch new file mode 100644 index 00000000..6f0272fd --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch @@ -0,0 +1,43 @@ +From 60cc2c4532f63a40486b7c4e891fb87fb6d4ab7f Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Wed, 7 Sep 2016 22:10:57 +0200 +Subject: [PATCH] i945/gma.c: generate fake VBT + +This generates a fake VBT for the Intel i945 graphic device. +i945 supports both the mobile chipset 945gm (calistoga) +and the desktop chipset 945gc (lakeport), +which is why a VBT with a different id string +needs to be created for each target. + +The VBT id string is obtained from the vbios blob in the following way: +"strings vbios.bin | grep VBT". + +Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/i945/gma.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index 02caa0a..f0944b9 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -433,6 +433,15 @@ static void gma_func0_init(struct device *dev) + iobase, mmiobase, graphics_base); + if (err == 0) + gfx_set_init_done(1); ++ /* Linux relies on VBT for panel info. */ ++ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { ++ generate_fake_intel_oprom(&conf->gfx, dev, ++ "$VBT CALISTOGA "); ++ } ++ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { ++ generate_fake_intel_oprom(&conf->gfx, dev, ++ "$VBT LAKEPORT-G "); ++ } + #endif + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/INFO b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/INFO new file mode 100644 index 00000000..4f5931f9 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/INFO @@ -0,0 +1,7 @@ +printf "lenovo/x60: use correct BLC_PWM_CTL value\n" +git am "../resources/libreboot/patch/misc/0003-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/24/10624/2 && git cherry-pick FETCH_HEAD + +printf "ec/lenovo/h8: permanently enable wifi/trackpoint/touchpad/bluetooth/wwan\n" +git am "../resources/libreboot/patch/misc/0005-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/58/7058/9 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-mb-intel-d945gclf-Disable-combined-mode-to-fix-SATA.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-mb-intel-d945gclf-Disable-combined-mode-to-fix-SATA.patch new file mode 100644 index 00000000..4c75bcd5 --- /dev/null +++ b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-mb-intel-d945gclf-Disable-combined-mode-to-fix-SATA.patch @@ -0,0 +1,31 @@ +From b6b2f9a9775029305f88f927f93e95046594f9b9 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 25 Aug 2016 09:24:15 +0200 +Subject: [PATCH] mb/intel/d945gclf: Disable combined mode to fix SATA + +Similarly to 2b2f465fcb1afe4960c613b8ca91e868c64592d4 +"mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA" +SATA must function in "plain" mode because it does not work in +"combined" mode. + +Tested on d945gclf + +Change-Id: I2e051a632a1341c4932cf86855006ae517dbf064 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> + +diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb +index 823a240..aa8c441 100644 +--- a/src/mainboard/intel/d945gclf/devicetree.cb ++++ b/src/mainboard/intel/d945gclf/devicetree.cb +@@ -45,7 +45,7 @@ chip northbridge/intel/i945 + register "gpi13_routing" = "1" + register "gpe0_en" = "0x20000601" + +- register "ide_legacy_combined" = "0x1" ++ register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-move-DIV_ROUND-macros-to-commonlib.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-move-DIV_ROUND-macros-to-commonlib.patch new file mode 100644 index 00000000..ea4db001 --- /dev/null +++ b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-move-DIV_ROUND-macros-to-commonlib.patch @@ -0,0 +1,93 @@ +From c82d4fa874322d70dec0e9d28c050e4c351de157 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Fri, 2 Sep 2016 23:14:54 +0200 +Subject: [PATCH 1/5] move DIV_ROUND macros to commonlib + +DIV_ROUND_CLOSEST and DIV_ROUND_UP are useful macros for other +architectures. This patch moves them from soc/nvidia/tegra/types.h +to commonlib/include/commonlib/helpers.h . + +Change-Id: I54521d9b197934cef8e352f9a5c4823015d85f01 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> + +diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h +index 0318e44..0b2395b 100644 +--- a/src/commonlib/include/commonlib/helpers.h ++++ b/src/commonlib/include/commonlib/helpers.h +@@ -34,6 +34,22 @@ + #define ABS(a) (((a) < 0) ? (-(a)) : (a)) + #define CEIL_DIV(a, b) (((a) + (b) - 1) / (b)) + #define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0) ++#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) ++/* ++ * Divide positive or negative dividend by positive divisor and round ++ * to closest integer. Result is undefined for negative divisors and ++ * for negative dividends if the divisor variable type is unsigned. ++ */ ++#define DIV_ROUND_CLOSEST(x, divisor)( \ ++{ \ ++ typeof(x) __x = x; \ ++ typeof(divisor) __d = divisor; \ ++ (((typeof(x))-1) > 0 || \ ++ ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ ++ (((__x) + ((__d) / 2)) / (__d)) : \ ++ (((__x) - ((__d) / 2)) / (__d)); \ ++} \ ++) + + /* Standard units. */ + #define KiB (1<<10) +diff --git a/src/soc/nvidia/tegra/types.h b/src/soc/nvidia/tegra/types.h +index dab474d..bfeebae 100644 +--- a/src/soc/nvidia/tegra/types.h ++++ b/src/soc/nvidia/tegra/types.h +@@ -51,22 +51,4 @@ + (type *)( (char *)__mptr - offsetof(type,member) );}) + #endif + +-#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) +- +-/* +- * Divide positive or negative dividend by positive divisor and round +- * to closest integer. Result is undefined for negative divisors and +- * for negative dividends if the divisor variable type is unsigned. +- */ +-#define DIV_ROUND_CLOSEST(x, divisor)( \ +-{ \ +- typeof(x) __x = x; \ +- typeof(divisor) __d = divisor; \ +- (((typeof(x))-1) > 0 || \ +- ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ +- (((__x) + ((__d) / 2)) / (__d)) : \ +- (((__x) - ((__d) / 2)) / (__d)); \ +-} \ +-) +- + #endif /* __TEGRA_MISC_TYPES_H__ */ +diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c +index e803e1b..b47c5c5 100644 +--- a/src/soc/nvidia/tegra210/addressmap.c ++++ b/src/soc/nvidia/tegra210/addressmap.c +@@ -23,6 +23,7 @@ + #include <stdlib.h> + #include <symbols.h> + #include <soc/nvidia/tegra/types.h> ++#include <commonlib/helpers.h> + + static uintptr_t tz_base_mib; + static const size_t tz_size_mib = CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; +diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c +index 3b771c9..5504b4d 100644 +--- a/src/soc/nvidia/tegra210/dsi.c ++++ b/src/soc/nvidia/tegra210/dsi.c +@@ -32,6 +32,7 @@ + #include <soc/tegra_dsi.h> + #include <soc/mipi-phy.h> + #include "jdi_25x18_display/panel-jdi-lpm102a188a.h" ++#include <commonlib/helpers.h> + + struct tegra_mipi_device mipi_device_data[NUM_DSI]; + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0002-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0002-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch new file mode 100644 index 00000000..6a8b9920 --- /dev/null +++ b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0002-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch @@ -0,0 +1,171 @@ +From f09ce5870025a98b6e497fd232adffde468c735a Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Fri, 2 Sep 2016 22:35:32 +0200 +Subject: [PATCH 2/5] i945/gma.c use latest linux code to calculate divisors. + +The code to compute n, m1, m2, p1 divisors is not correct in coreboot and +on some targets hits a working mode at lower refresh rate, which is why +display is working on some targets. +This patch also fixes reference frequency. + +This patch reuses linux code to correctly compute divisors. + +The result is that some previously not working displays (Lenovo T60 with +1024x786, 1400x1050, 2048x1536) + +TESTED on T60 with 1024x786. + +Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> + +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index 02caa0a..d1d68d4 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -26,6 +26,8 @@ + #include <string.h> + #include <pc80/vga.h> + #include <pc80/vga_io.h> ++#include <commonlib/helpers.h> ++ + + #include "i945.h" + #include "chip.h" +@@ -43,7 +45,7 @@ + #define PGETBL_CTL 0x2020 + #define PGETBL_ENABLED 0x00000001 + +-#define BASE_FREQUENCY 120000 ++#define BASE_FREQUENCY 100000 + + #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + +@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + u8 edid_data[128]; + unsigned long temp; + int hpolarity, vpolarity; +- u32 candp1, candn; +- u32 best_delta = 0xffffffff; ++ u32 err_most = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; ++ u32 pixel_p2; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; +@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); + write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); + +- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock +- : (2 * mode->pixel_clock); +- +- /* Find suitable divisors. */ +- for (candp1 = 1; candp1 <= 8; candp1++) { +- for (candn = 5; candn <= 10; candn++) { +- u32 cur_frequency; +- u32 m; /* 77 - 131. */ +- u32 denom; /* 35 - 560. */ +- u32 current_delta; +- +- denom = candn * candp1 * 7; +- /* Doesnt overflow for up to +- 5000000 kHz = 5 GHz. */ +- m = (target_frequency * denom +- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; +- +- if (m < 77 || m > 131) +- continue; +- +- cur_frequency = (BASE_FREQUENCY * m) / denom; +- if (target_frequency > cur_frequency) +- current_delta = target_frequency - cur_frequency; +- else +- current_delta = cur_frequency - target_frequency; +- +- if (best_delta > current_delta) { +- best_delta = current_delta; +- pixel_n = candn; +- pixel_p1 = candp1; +- pixel_m2 = ((m + 3) % 5) + 7; +- pixel_m1 = (m - pixel_m2) / 5; ++ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; ++ target_frequency = mode->pixel_clock; ++ ++ /* Find suitable divisors, m1, m2, p1, n. */ ++ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ ++ /* should be closest to target frequency as possible */ ++ u32 candn, candm1, candm2, candp1; ++ for (candm1 = 8; candm1 <= 18; candm1++) { ++ for (candm2 = 3; candm2 <= 7; candm2++) { ++ for (candn = 1; candn <= 6; candn++) { ++ for (candp1 = 1; candp1 <= 8; candp1++) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * pixel_p2; ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if ((m < 70) || (m > 120)) ++ continue; ++ if (this_err < err_most) { ++ err_most = this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } + } + } + } + +- if (best_delta == 0xffffffff) { ++ if (err_most == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } +@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", +- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n +- / (pixel_p1 * 7)); ++ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / ++ (pixel_n + 2) / (pixel_p1 * pixel_p2)); + + #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(1), +- ((pixel_n - 2) << 16) +- | ((pixel_m1 - 2) << 8) | pixel_m2); ++ (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS +@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + | (conf->gpu_lvds_use_spread_spectrum_clock + ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV + : 0) +- | (pixel_p1 << 16) +- | (pixel_p1)); ++ | (0x10000 << pixel_p1)); + mdelay(1); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | +@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) +- | (pixel_p1 << 16) +- | (pixel_p1)); ++ | (0x10000 << pixel_p1)); + mdelay(1); + write32(pmmio + HTOTAL(1), + ((hactive + right_border + hblank - 1) << 16) +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0003-i945-gma.c-add-native-VGA-init.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0003-i945-gma.c-add-native-VGA-init.patch new file mode 100644 index 00000000..24a01442 --- /dev/null +++ b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0003-i945-gma.c-add-native-VGA-init.patch @@ -0,0 +1,238 @@ +From 09546d389511350d1b33b3c6bd9230de8bbbe317 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 5 Sep 2016 22:46:11 +0200 +Subject: [PATCH 3/5] i945/gma.c: add native VGA init + +This reuses the intel pineview native graphic initialization +to have output on the VGA connector of i945 devices. + +The behavior is the same as with the vbios blob. +It uses the external VGA display if it is connected. + +Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> + +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index d1d68d4..37674d7 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase) + return 0; + } + +-static int intel_gma_init(struct northbridge_intel_i945_config *conf, ++static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, + unsigned int pphysbase, unsigned int piobase, + void *pmmio, unsigned int pgfx) + { +@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + #endif + return 0; + } ++ ++static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, ++ unsigned int pphysbase, unsigned int piobase, ++ void *pmmio, unsigned int pgfx) ++{ ++ int i; ++ u32 hactive, vactive; ++ u16 reg16; ++ u32 uma_size; ++ ++ printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", ++ (u32)pmmio, piobase, pphysbase); ++ ++ gtt_setup(pmmio); ++ ++ /* Disable VGA. */ ++ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); ++ ++ /* Disable pipes. */ ++ write32(pmmio + PIPECONF(0), 0); ++ write32(pmmio + PIPECONF(1), 0); ++ ++ write32(pmmio + INSTPM, 0x800); ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(pmmio + VGA0, 0x200074); ++ write32(pmmio + VGA1, 0x200074); ++ ++ write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); ++ write32(pmmio + DSPCLK_GATE_D, 0); ++ write32(pmmio + FW_BLC, 0x03060106); ++ write32(pmmio + FW_BLC2, 0x00000306); ++ ++ write32(pmmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(pmmio + 0x7041c, 0x0); ++ ++ write32(pmmio + DPLL_MD(0), 0x3); ++ write32(pmmio + DPLL_MD(1), 0x3); ++ write32(pmmio + DSPCNTR(1), 0x1000000); ++ write32(pmmio + PIPESRC(1), 0x027f01df); ++ ++ vga_misc_write(0x67); ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ // Disable screen memory to prevent garbage from appearing. ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(pmmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_VGA_MODE_DIS ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x400601 ++ ); ++ mdelay(1); ++ write32(pmmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_VGA_MODE_DIS ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x400601 ++ ); ++ ++ write32(pmmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(pmmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(pmmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(pmmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(pmmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(pmmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(pmmio + PF_WIN_POS(0), 0); ++ ++ write32(pmmio + PIPESRC(0), (639 << 16) | 399); ++ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(pmmio + PFIT_CONTROL, 0x0); ++ ++ mdelay(1); ++ ++ write32(pmmio + FDI_RX_CTL(0), 0x00002040); ++ mdelay(1); ++ write32(pmmio + FDI_RX_CTL(0), 0x80002050); ++ write32(pmmio + FDI_TX_CTL(0), 0x00044000); ++ mdelay(1); ++ write32(pmmio + FDI_TX_CTL(0), 0x80044000); ++ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(pmmio + VGACNTRL, 0x0); ++ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(pmmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(pmmio + DSPFW3, 0x7f3f00c1); ++ write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); ++ write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); ++ write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); ++ ++ /* Set up GTT. */ ++ ++ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); ++ uma_size = 0; ++ if (!(reg16 & 2)) { ++ uma_size = decode_igd_memory_size((reg16 >> 4) & 7); ++ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); ++ } ++ ++ for (i = 0; i < (uma_size - 256) / 4; i++) ++ { ++ outl((i << 2) | 1, piobase); ++ outl(pphysbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ /* Clear interrupts. */ ++ write32(pmmio + DEIIR, 0xffffffff); ++ write32(pmmio + SDEIIR, 0xffffffff); ++ write32(pmmio + IIR, 0xffffffff); ++ write32(pmmio + IMR, 0xffffffff); ++ write32(pmmio + EIR, 0xffffffff); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ return 0; ++ ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should have a correct header */ ++static int vga_connected(u8 *pmmio) { ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(pmmio + GMBUS0); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + #endif + + static void gma_func0_init(struct device *dev) +@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev) + ); + + int err; +- err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, ++ if (vga_connected(mmiobase)) ++ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, ++ iobase, mmiobase, graphics_base); ++ else ++ err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, + iobase, mmiobase, graphics_base); + if (err == 0) + gfx_set_init_done(1); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0004-mb-intel-d945gclf-Allow-use-of-native-graphic-init.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0004-mb-intel-d945gclf-Allow-use-of-native-graphic-init.patch new file mode 100644 index 00000000..bda565f9 --- /dev/null +++ b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0004-mb-intel-d945gclf-Allow-use-of-native-graphic-init.patch @@ -0,0 +1,40 @@ +From d80a39744d7aad734e8d53f2b2d6cb6b5eeee834 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Tue, 6 Sep 2016 23:03:04 +0200 +Subject: [PATCH 4/5] mb/intel/d945gclf: Allow use of native graphic init + +Adds pci device id to native graphic init and add a Native graphic init +option in Kconfig. + +Change-Id: I136122daef70547830bcc87f568406be7162461f +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> + +diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig +index 429a304..a83e613 100644 +--- a/src/mainboard/intel/d945gclf/Kconfig ++++ b/src/mainboard/intel/d945gclf/Kconfig +@@ -29,6 +29,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy + select HAVE_ACPI_RESUME + select BOARD_ROMSIZE_KB_512 + select CHANNEL_XOR_RANDOMIZATION ++ select MAINBOARD_HAS_NATIVE_VGA_INIT ++ select INTEL_EDID + + config MAINBOARD_DIR + string +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index 37674d7..abe7dd6 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -716,7 +716,7 @@ static struct device_operations gma_func1_ops = { + .ops_pci = &gma_pci_ops, + }; + +-static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0 }; ++static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0x2772, 0 }; + + static const struct pci_driver i945_gma_func0_driver __pci_driver = { + .ops = &gma_func0_ops, +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0005-i945-gma.c-Only-init-LVDS-if-it-is-present-on-the-de.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0005-i945-gma.c-Only-init-LVDS-if-it-is-present-on-the-de.patch new file mode 100644 index 00000000..3155ef90 --- /dev/null +++ b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0005-i945-gma.c-Only-init-LVDS-if-it-is-present-on-the-de.patch @@ -0,0 +1,97 @@ +From 603387a7650a80c92f1064f17fbbf06d60c06f30 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Tue, 6 Sep 2016 23:53:32 +0200 +Subject: [PATCH 5/5] i945/gma.c: Only init LVDS if it is present on the device + +Some devices have no LVDS output but if no VGA is connected or +no edid can be found, it will try to init LVDS. + +This patch makes sure only devices that have an LVDS connector can use LVDS +graphic initialisation. + +Change-Id: Ie15631514535bab6c881c1f52e9edbfb8aaa5db7 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> + +diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig +index e653c08..8ba3d77 100644 +--- a/src/mainboard/apple/macbook21/Kconfig ++++ b/src/mainboard/apple/macbook21/Kconfig +@@ -35,6 +35,10 @@ config DCACHE_RAM_SIZE + hex + default 0x8000 + ++config HAS_LVDS ++ bool ++ default y ++ + if BOARD_APPLE_MACBOOK21 + + config MAINBOARD_PART_NUMBER +diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig +index ea68bed..e74b70c 100644 +--- a/src/mainboard/getac/p470/Kconfig ++++ b/src/mainboard/getac/p470/Kconfig +@@ -64,4 +64,8 @@ config VGA_BIOS_FILE + string + default "getac-pci8086,27a2.rom" + ++config HAS_LVDS ++ bool ++ default y ++ + endif # BOARD_GETAC_P470 +diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig +index 52eeda3..e5a7554 100644 +--- a/src/mainboard/lenovo/t60/Kconfig ++++ b/src/mainboard/lenovo/t60/Kconfig +@@ -54,4 +54,8 @@ config SEABIOS_PS2_TIMEOUT + int + default 3000 + ++config HAS_LVDS ++ bool ++ default y ++ + endif +diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig +index ab4b58e..152e6b2 100644 +--- a/src/mainboard/lenovo/x60/Kconfig ++++ b/src/mainboard/lenovo/x60/Kconfig +@@ -61,4 +61,8 @@ config SEABIOS_PS2_TIMEOUT + int + default 3000 + ++config HAS_LVDS ++ bool ++ default y ++ + endif +diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig +index 6e8d35b..ae7961f 100644 +--- a/src/northbridge/intel/i945/Kconfig ++++ b/src/northbridge/intel/i945/Kconfig +@@ -71,4 +71,8 @@ config CHECK_SLFRCS_ON_RESUME + On other boards the check always creates a false positive, + effectively making it impossible to resume. + ++config HAS_LVDS ++ bool ++ default n ++ + endif +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index abe7dd6..be299f4 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -611,7 +611,7 @@ static void gma_func0_init(struct device *dev) + ); + + int err; +- if (vga_connected(mmiobase)) ++ if (!CONFIG_HAS_LVDS || vga_connected(mmiobase)) + err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, + iobase, mmiobase, graphics_base); + else +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch b/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch new file mode 100644 index 00000000..187dbc9a --- /dev/null +++ b/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch @@ -0,0 +1,415 @@ +From 9659556d9edbba6c3530ed1d0630add30419210f Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sun, 4 Sep 2016 16:01:11 +0200 +Subject: [PATCH 1/2] x4x/gma.c: Add VESA native resolution mode + +This patch implements native resolution, VESA mode, on the VGA output of +x4x. + +It relies on EDID to modeset, but has a fallback-mode (640 x 480 @ +60Hz) if this is no EDID could be found. This fallback mode only works in textmode +since in VESA mode some payloads (grub2) rely on VBE info, which is being +generated from an EDID. + +Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/x4x/gma.c | 282 ++++++++++++++++++++++++++++++++++------ + 1 file changed, 242 insertions(+), 40 deletions(-) + +diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c +index 2679026..118f98d 100644 +--- a/src/northbridge/intel/x4x/gma.c ++++ b/src/northbridge/intel/x4x/gma.c +@@ -26,24 +26,68 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" + #include "x4x.h" + #include <drivers/intel/gma/intel_bios.h> ++#include <drivers/intel/gma/edid.h> + #include <drivers/intel/gma/i915.h> + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUENCY 96000 ++ ++static u8 edid_is_null(u8 *edid, u32 edid_size) ++{ ++ u32 i; ++ for (i = 0; i < edid_size; i++) { ++ if (*(edid + i) != 0) ++ return 0; ++ } ++ return 1; ++} + static void intel_gma_init(const struct northbridge_intel_x4x_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + ++ + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u8 edid_not_found; ++ ++ /* Initialise mode variables for 640 x 480 @ 60Hz */ ++ u32 hactive = 640, vactive = 480; ++ u32 right_border = 0, bottom_border = 0; ++ int hpolarity = 0, vpolarity = 0; ++ u32 hsync = 96, vsync = 2; ++ u32 hblank = 160, vblank = 45; ++ u32 hfront_porch = 16, vfront_porch = 10; ++ u32 target_frequency = 25175; ++ ++ u32 err_most = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Set up GTT */ ++ for (i = 0; i < 0x1000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -73,107 +117,258 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ edid_not_found = edid_is_null(edid_data, sizeof(edid_data)); ++ if (!edid_not_found) { ++ printk(BIOS_DEBUG, "EDID is not null"); ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ } else ++ printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode"); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 16; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST( ++ BASE_FREQUENCY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < err_most) { ++ err_most = this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (err_most == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / ++ (pixel_n + 2) / (pixel_p1 * 10)); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ hactive * vactive * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } + } + + static void native_init(struct device *dev) + { ++ struct resource *lfb_res; ++ struct resource *pio_res; ++ u32 physbase; + struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + struct northbridge_intel_x4x_config *conf = dev->chip_info; + ++ lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); ++ pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); ++ physbase = pci_read_config32(dev, 0x5c) & ~0xf; ++ + if (gtt_res && gtt_res->base) { + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0)); ++ intel_gma_init(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +@@ -182,6 +377,7 @@ static void native_init(struct device *dev) + + static void gma_func0_init(struct device *dev) + { ++ u16 reg16; + u32 reg32; + + /* IGD needs to be Bus Master */ +@@ -189,6 +385,12 @@ static void gma_func0_init(struct device *dev) + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + ++ /* configure GMBUSFREQ */ ++ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc); ++ reg16 &= ~0x1ff; ++ reg16 |= 0xbc; ++ pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc, reg16); ++ + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + native_init(dev); + else +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch b/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch new file mode 100644 index 00000000..d579df55 --- /dev/null +++ b/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch @@ -0,0 +1,30 @@ +From f9a84edfc672424c9dcaa0a71ad0751c2355c3d0 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 5 Sep 2016 12:07:57 +0200 +Subject: [PATCH 2/2] gigabyte/ga-g41m-es2l: add VESA mode to Kconfig + +This patch adds MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG to the +gigabyte/ga-g41m-es2l Kconfig to allow selecting between textmode and +vesamode in menuconfig. + +Change-Id: I84b61118fa0419d49d2498b66029711cdce97576 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +index 6452f4d..281d498 100644 +--- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig ++++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS + select BOARD_ROMSIZE_KB_1024 + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT ++ select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch new file mode 100644 index 00000000..26632b7d --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch @@ -0,0 +1,212 @@ +From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 22 Aug 2016 17:58:46 +0200 +Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected + +The intel x4x and gm45 have very similar integrated graphic devices. +Currently the x4x native graphic init enables VGA, while gm45 can output +on LVDS. + +This patch reuses the x4x graphic initialisation code +to enable output on VGA in gm45 in a way that the behavior is similar to vbios: +If no VGA display is connected the internal LVDS screen is used. +If an external screen is detected on the VGA port it will be used instead. + +Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 153 insertions(+), 4 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..74c9bc3 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) + write32(res2mmio(gtt_res, reg, 0), data); + } + +-static void intel_gma_init(const struct northbridge_intel_gm45_config *info, ++static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + +@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + sizeof(edid_data), &edid); + mode = &edid.mode; + +- /* Disable screen memory to prevent garbage from appearing. */ ++ /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; +@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + } + } + ++static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ++ u8 *mmio) ++{ ++ ++ int i; ++ u32 hactive, vactive; ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(mmio + VGA0, 0x31108); ++ write32(mmio + VGA1, 0x31406); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + 0x7041c, 0x0); ++ write32(mmio + DPLL_MD(0), 0x3); ++ write32(mmio + DPLL_MD(1), 0x3); ++ ++ vga_misc_write(0x67); ++ ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ /* Disable screen memory to prevent garbage from appearing. */ ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(mmio + FP0(0), 0x31108); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ mdelay(1); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); ++ ++ write32(mmio + PF_WIN_POS(0), 0); ++ ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0xa0000000); ++ ++ mdelay(1); ++ ++ write32(mmio + 0x000f000c, 0x00002040); ++ mdelay(1); ++ write32(mmio + 0x000f000c, 0x00002050); ++ write32(mmio + 0x00060100, 0x00044000); ++ mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_ENABLE ++ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(mmio + VGACNTRL, 0x0); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ /* Clear interrupts. */ ++ write32(mmio + DEIIR, 0xffffffff); ++ write32(mmio + SDEIIR, 0xffffffff); ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should not have a correct header */ ++static u8 vga_connected(u8 *mmio) ++{ ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + static void gma_pm_init_post_vbios(struct device *const dev) + { + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; +@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, +- pio_res->base, lfb_res->base); ++ if (vga_connected(res2mmio(gtt_res, 0, 0))) ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ else ++ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch new file mode 100644 index 00000000..ef42f3e8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch @@ -0,0 +1,379 @@ +From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sat, 27 Aug 2016 01:09:19 +0200 +Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output + +This implements "Keep VESA framebuffer" behavior on VGA output of gm45. +This patch reuses Linux code to compute vga divisors. + +Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- + 1 file changed, 209 insertions(+), 42 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index 74c9bc3..efaa210 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -25,6 +25,7 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" +@@ -35,6 +36,8 @@ + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUECY 96000 ++ + static struct resource *gtt_res = NULL; + + u32 gtt_read(u32 reg) +@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + } + + static void gma_init_vga(const struct northbridge_intel_gm45_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u32 hactive, vactive, right_border, bottom_border; ++ int hpolarity, vpolarity; ++ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; ++ u32 target_frequency; ++ u32 smallest_err = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Setup GTT. */ ++ for (i = 0; i < 0x2000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE +- | ADPA_DPMS_ON +- ); ++ | ADPA_DPMS_ON); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); +@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 17; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < smallest_err) { ++ smallest_err= this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (smallest_err == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) ++ / (pixel_p1 * 10))); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ edid.x_resolution * edid.y_resolution * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } ++ ++ + } + + /* compare the header of the vga edid header */ +@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(mmio + GMBUS0); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); +@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) +- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch new file mode 100644 index 00000000..fb30c4c2 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch @@ -0,0 +1,31 @@ +From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 8 Sep 2016 22:21:54 +0200 +Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT + +The correct id string for gm45 is "$VBT CANTIGA ". +This can be found in the gm45 option rom: +"strings vbios.bin | grep VBT". + +Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..19bd944 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, +- "$VBT IRONLAKE-MOBILE"); ++ "$VBT CANTIGA "); + } + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/INFO b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/INFO new file mode 100644 index 00000000..ad7d12f4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/INFO @@ -0,0 +1,4 @@ +# NOTE: remove this when updating coreboot. This has been merged upstream +printf "ThinkPad R400 support (clone of the T400)\n" +git am "../resources/libreboot/patch/misc/0007-lenovo-r400-Add-clone-of-Lenovo-T400.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/93/8393/5 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list new file mode 100644 index 00000000..451d1b75 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb//0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch new file mode 100644 index 00000000..26632b7d --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch @@ -0,0 +1,212 @@ +From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 22 Aug 2016 17:58:46 +0200 +Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected + +The intel x4x and gm45 have very similar integrated graphic devices. +Currently the x4x native graphic init enables VGA, while gm45 can output +on LVDS. + +This patch reuses the x4x graphic initialisation code +to enable output on VGA in gm45 in a way that the behavior is similar to vbios: +If no VGA display is connected the internal LVDS screen is used. +If an external screen is detected on the VGA port it will be used instead. + +Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 153 insertions(+), 4 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..74c9bc3 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) + write32(res2mmio(gtt_res, reg, 0), data); + } + +-static void intel_gma_init(const struct northbridge_intel_gm45_config *info, ++static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + +@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + sizeof(edid_data), &edid); + mode = &edid.mode; + +- /* Disable screen memory to prevent garbage from appearing. */ ++ /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; +@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + } + } + ++static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ++ u8 *mmio) ++{ ++ ++ int i; ++ u32 hactive, vactive; ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(mmio + VGA0, 0x31108); ++ write32(mmio + VGA1, 0x31406); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + 0x7041c, 0x0); ++ write32(mmio + DPLL_MD(0), 0x3); ++ write32(mmio + DPLL_MD(1), 0x3); ++ ++ vga_misc_write(0x67); ++ ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ /* Disable screen memory to prevent garbage from appearing. */ ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(mmio + FP0(0), 0x31108); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ mdelay(1); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); ++ ++ write32(mmio + PF_WIN_POS(0), 0); ++ ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0xa0000000); ++ ++ mdelay(1); ++ ++ write32(mmio + 0x000f000c, 0x00002040); ++ mdelay(1); ++ write32(mmio + 0x000f000c, 0x00002050); ++ write32(mmio + 0x00060100, 0x00044000); ++ mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_ENABLE ++ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(mmio + VGACNTRL, 0x0); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ /* Clear interrupts. */ ++ write32(mmio + DEIIR, 0xffffffff); ++ write32(mmio + SDEIIR, 0xffffffff); ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should not have a correct header */ ++static u8 vga_connected(u8 *mmio) ++{ ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + static void gma_pm_init_post_vbios(struct device *const dev) + { + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; +@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, +- pio_res->base, lfb_res->base); ++ if (vga_connected(res2mmio(gtt_res, 0, 0))) ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ else ++ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch new file mode 100644 index 00000000..ef42f3e8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch @@ -0,0 +1,379 @@ +From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sat, 27 Aug 2016 01:09:19 +0200 +Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output + +This implements "Keep VESA framebuffer" behavior on VGA output of gm45. +This patch reuses Linux code to compute vga divisors. + +Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- + 1 file changed, 209 insertions(+), 42 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index 74c9bc3..efaa210 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -25,6 +25,7 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" +@@ -35,6 +36,8 @@ + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUECY 96000 ++ + static struct resource *gtt_res = NULL; + + u32 gtt_read(u32 reg) +@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + } + + static void gma_init_vga(const struct northbridge_intel_gm45_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u32 hactive, vactive, right_border, bottom_border; ++ int hpolarity, vpolarity; ++ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; ++ u32 target_frequency; ++ u32 smallest_err = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Setup GTT. */ ++ for (i = 0; i < 0x2000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE +- | ADPA_DPMS_ON +- ); ++ | ADPA_DPMS_ON); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); +@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 17; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < smallest_err) { ++ smallest_err= this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (smallest_err == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) ++ / (pixel_p1 * 10))); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ edid.x_resolution * edid.y_resolution * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } ++ ++ + } + + /* compare the header of the vga edid header */ +@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(mmio + GMBUS0); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); +@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) +- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch new file mode 100644 index 00000000..fb30c4c2 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch @@ -0,0 +1,31 @@ +From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 8 Sep 2016 22:21:54 +0200 +Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT + +The correct id string for gm45 is "$VBT CANTIGA ". +This can be found in the gm45 option rom: +"strings vbios.bin | grep VBT". + +Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..19bd944 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, +- "$VBT IRONLAKE-MOBILE"); ++ "$VBT CANTIGA "); + } + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list new file mode 100644 index 00000000..59e0a36a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch new file mode 100644 index 00000000..26632b7d --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch @@ -0,0 +1,212 @@ +From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 22 Aug 2016 17:58:46 +0200 +Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected + +The intel x4x and gm45 have very similar integrated graphic devices. +Currently the x4x native graphic init enables VGA, while gm45 can output +on LVDS. + +This patch reuses the x4x graphic initialisation code +to enable output on VGA in gm45 in a way that the behavior is similar to vbios: +If no VGA display is connected the internal LVDS screen is used. +If an external screen is detected on the VGA port it will be used instead. + +Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 153 insertions(+), 4 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..74c9bc3 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) + write32(res2mmio(gtt_res, reg, 0), data); + } + +-static void intel_gma_init(const struct northbridge_intel_gm45_config *info, ++static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + +@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + sizeof(edid_data), &edid); + mode = &edid.mode; + +- /* Disable screen memory to prevent garbage from appearing. */ ++ /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; +@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + } + } + ++static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ++ u8 *mmio) ++{ ++ ++ int i; ++ u32 hactive, vactive; ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(mmio + VGA0, 0x31108); ++ write32(mmio + VGA1, 0x31406); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + 0x7041c, 0x0); ++ write32(mmio + DPLL_MD(0), 0x3); ++ write32(mmio + DPLL_MD(1), 0x3); ++ ++ vga_misc_write(0x67); ++ ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ /* Disable screen memory to prevent garbage from appearing. */ ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(mmio + FP0(0), 0x31108); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ mdelay(1); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); ++ ++ write32(mmio + PF_WIN_POS(0), 0); ++ ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0xa0000000); ++ ++ mdelay(1); ++ ++ write32(mmio + 0x000f000c, 0x00002040); ++ mdelay(1); ++ write32(mmio + 0x000f000c, 0x00002050); ++ write32(mmio + 0x00060100, 0x00044000); ++ mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_ENABLE ++ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(mmio + VGACNTRL, 0x0); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ /* Clear interrupts. */ ++ write32(mmio + DEIIR, 0xffffffff); ++ write32(mmio + SDEIIR, 0xffffffff); ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should not have a correct header */ ++static u8 vga_connected(u8 *mmio) ++{ ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + static void gma_pm_init_post_vbios(struct device *const dev) + { + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; +@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, +- pio_res->base, lfb_res->base); ++ if (vga_connected(res2mmio(gtt_res, 0, 0))) ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ else ++ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch new file mode 100644 index 00000000..ef42f3e8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch @@ -0,0 +1,379 @@ +From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sat, 27 Aug 2016 01:09:19 +0200 +Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output + +This implements "Keep VESA framebuffer" behavior on VGA output of gm45. +This patch reuses Linux code to compute vga divisors. + +Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- + 1 file changed, 209 insertions(+), 42 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index 74c9bc3..efaa210 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -25,6 +25,7 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" +@@ -35,6 +36,8 @@ + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUECY 96000 ++ + static struct resource *gtt_res = NULL; + + u32 gtt_read(u32 reg) +@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + } + + static void gma_init_vga(const struct northbridge_intel_gm45_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u32 hactive, vactive, right_border, bottom_border; ++ int hpolarity, vpolarity; ++ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; ++ u32 target_frequency; ++ u32 smallest_err = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Setup GTT. */ ++ for (i = 0; i < 0x2000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE +- | ADPA_DPMS_ON +- ); ++ | ADPA_DPMS_ON); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); +@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 17; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < smallest_err) { ++ smallest_err= this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (smallest_err == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) ++ / (pixel_p1 * 10))); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ edid.x_resolution * edid.y_resolution * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } ++ ++ + } + + /* compare the header of the vga edid header */ +@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(mmio + GMBUS0); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); +@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) +- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch new file mode 100644 index 00000000..fb30c4c2 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch @@ -0,0 +1,31 @@ +From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 8 Sep 2016 22:21:54 +0200 +Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT + +The correct id string for gm45 is "$VBT CANTIGA ". +This can be found in the gm45 option rom: +"strings vbios.bin | grep VBT". + +Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..19bd944 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, +- "$VBT IRONLAKE-MOBILE"); ++ "$VBT CANTIGA "); + } + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/INFO b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/INFO new file mode 100644 index 00000000..ad7d12f4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/INFO @@ -0,0 +1,4 @@ +# NOTE: remove this when updating coreboot. This has been merged upstream +printf "ThinkPad R400 support (clone of the T400)\n" +git am "../resources/libreboot/patch/misc/0007-lenovo-r400-Add-clone-of-Lenovo-T400.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/93/8393/5 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list new file mode 100644 index 00000000..59e0a36a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch new file mode 100644 index 00000000..26632b7d --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch @@ -0,0 +1,212 @@ +From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 22 Aug 2016 17:58:46 +0200 +Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected + +The intel x4x and gm45 have very similar integrated graphic devices. +Currently the x4x native graphic init enables VGA, while gm45 can output +on LVDS. + +This patch reuses the x4x graphic initialisation code +to enable output on VGA in gm45 in a way that the behavior is similar to vbios: +If no VGA display is connected the internal LVDS screen is used. +If an external screen is detected on the VGA port it will be used instead. + +Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 153 insertions(+), 4 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..74c9bc3 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) + write32(res2mmio(gtt_res, reg, 0), data); + } + +-static void intel_gma_init(const struct northbridge_intel_gm45_config *info, ++static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + +@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + sizeof(edid_data), &edid); + mode = &edid.mode; + +- /* Disable screen memory to prevent garbage from appearing. */ ++ /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; +@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + } + } + ++static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ++ u8 *mmio) ++{ ++ ++ int i; ++ u32 hactive, vactive; ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(mmio + VGA0, 0x31108); ++ write32(mmio + VGA1, 0x31406); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + 0x7041c, 0x0); ++ write32(mmio + DPLL_MD(0), 0x3); ++ write32(mmio + DPLL_MD(1), 0x3); ++ ++ vga_misc_write(0x67); ++ ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ /* Disable screen memory to prevent garbage from appearing. */ ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(mmio + FP0(0), 0x31108); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ mdelay(1); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); ++ ++ write32(mmio + PF_WIN_POS(0), 0); ++ ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0xa0000000); ++ ++ mdelay(1); ++ ++ write32(mmio + 0x000f000c, 0x00002040); ++ mdelay(1); ++ write32(mmio + 0x000f000c, 0x00002050); ++ write32(mmio + 0x00060100, 0x00044000); ++ mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_ENABLE ++ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(mmio + VGACNTRL, 0x0); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ /* Clear interrupts. */ ++ write32(mmio + DEIIR, 0xffffffff); ++ write32(mmio + SDEIIR, 0xffffffff); ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should not have a correct header */ ++static u8 vga_connected(u8 *mmio) ++{ ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + static void gma_pm_init_post_vbios(struct device *const dev) + { + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; +@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, +- pio_res->base, lfb_res->base); ++ if (vga_connected(res2mmio(gtt_res, 0, 0))) ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ else ++ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch new file mode 100644 index 00000000..ef42f3e8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch @@ -0,0 +1,379 @@ +From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sat, 27 Aug 2016 01:09:19 +0200 +Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output + +This implements "Keep VESA framebuffer" behavior on VGA output of gm45. +This patch reuses Linux code to compute vga divisors. + +Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- + 1 file changed, 209 insertions(+), 42 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index 74c9bc3..efaa210 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -25,6 +25,7 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" +@@ -35,6 +36,8 @@ + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUECY 96000 ++ + static struct resource *gtt_res = NULL; + + u32 gtt_read(u32 reg) +@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + } + + static void gma_init_vga(const struct northbridge_intel_gm45_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u32 hactive, vactive, right_border, bottom_border; ++ int hpolarity, vpolarity; ++ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; ++ u32 target_frequency; ++ u32 smallest_err = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Setup GTT. */ ++ for (i = 0; i < 0x2000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE +- | ADPA_DPMS_ON +- ); ++ | ADPA_DPMS_ON); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); +@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 17; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < smallest_err) { ++ smallest_err= this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (smallest_err == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) ++ / (pixel_p1 * 10))); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ edid.x_resolution * edid.y_resolution * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } ++ ++ + } + + /* compare the header of the vga edid header */ +@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(mmio + GMBUS0); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); +@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) +- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch new file mode 100644 index 00000000..fb30c4c2 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch @@ -0,0 +1,31 @@ +From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 8 Sep 2016 22:21:54 +0200 +Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT + +The correct id string for gm45 is "$VBT CANTIGA ". +This can be found in the gm45 option rom: +"strings vbios.bin | grep VBT". + +Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..19bd944 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, +- "$VBT IRONLAKE-MOBILE"); ++ "$VBT CANTIGA "); + } + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/INFO b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/INFO new file mode 100644 index 00000000..9ef6d54a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/INFO @@ -0,0 +1,8 @@ +# NOTE: merged upstream already +printf "mainboard/lenovo/t400: Add initial hybrid graphics support\n" +git am "../resources/libreboot/patch/misc/0001-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/19/9319/18 && git cherry-pick FETCH_HEAD + +printf "NOTFORMERGE: lenovo/t400: hard-code enable integrated-only video\n" +git am "../resources/libreboot/patch/misc/0002-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/50/10550/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list new file mode 100644 index 00000000..59e0a36a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch new file mode 100644 index 00000000..26632b7d --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch @@ -0,0 +1,212 @@ +From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 22 Aug 2016 17:58:46 +0200 +Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected + +The intel x4x and gm45 have very similar integrated graphic devices. +Currently the x4x native graphic init enables VGA, while gm45 can output +on LVDS. + +This patch reuses the x4x graphic initialisation code +to enable output on VGA in gm45 in a way that the behavior is similar to vbios: +If no VGA display is connected the internal LVDS screen is used. +If an external screen is detected on the VGA port it will be used instead. + +Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 153 insertions(+), 4 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..74c9bc3 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) + write32(res2mmio(gtt_res, reg, 0), data); + } + +-static void intel_gma_init(const struct northbridge_intel_gm45_config *info, ++static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + +@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + sizeof(edid_data), &edid); + mode = &edid.mode; + +- /* Disable screen memory to prevent garbage from appearing. */ ++ /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; +@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + } + } + ++static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ++ u8 *mmio) ++{ ++ ++ int i; ++ u32 hactive, vactive; ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(mmio + VGA0, 0x31108); ++ write32(mmio + VGA1, 0x31406); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + 0x7041c, 0x0); ++ write32(mmio + DPLL_MD(0), 0x3); ++ write32(mmio + DPLL_MD(1), 0x3); ++ ++ vga_misc_write(0x67); ++ ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ /* Disable screen memory to prevent garbage from appearing. */ ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(mmio + FP0(0), 0x31108); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ mdelay(1); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); ++ ++ write32(mmio + PF_WIN_POS(0), 0); ++ ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0xa0000000); ++ ++ mdelay(1); ++ ++ write32(mmio + 0x000f000c, 0x00002040); ++ mdelay(1); ++ write32(mmio + 0x000f000c, 0x00002050); ++ write32(mmio + 0x00060100, 0x00044000); ++ mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_ENABLE ++ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(mmio + VGACNTRL, 0x0); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ /* Clear interrupts. */ ++ write32(mmio + DEIIR, 0xffffffff); ++ write32(mmio + SDEIIR, 0xffffffff); ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should not have a correct header */ ++static u8 vga_connected(u8 *mmio) ++{ ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + static void gma_pm_init_post_vbios(struct device *const dev) + { + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; +@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, +- pio_res->base, lfb_res->base); ++ if (vga_connected(res2mmio(gtt_res, 0, 0))) ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ else ++ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch new file mode 100644 index 00000000..ef42f3e8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch @@ -0,0 +1,379 @@ +From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sat, 27 Aug 2016 01:09:19 +0200 +Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output + +This implements "Keep VESA framebuffer" behavior on VGA output of gm45. +This patch reuses Linux code to compute vga divisors. + +Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- + 1 file changed, 209 insertions(+), 42 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index 74c9bc3..efaa210 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -25,6 +25,7 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" +@@ -35,6 +36,8 @@ + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUECY 96000 ++ + static struct resource *gtt_res = NULL; + + u32 gtt_read(u32 reg) +@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + } + + static void gma_init_vga(const struct northbridge_intel_gm45_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u32 hactive, vactive, right_border, bottom_border; ++ int hpolarity, vpolarity; ++ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; ++ u32 target_frequency; ++ u32 smallest_err = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Setup GTT. */ ++ for (i = 0; i < 0x2000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE +- | ADPA_DPMS_ON +- ); ++ | ADPA_DPMS_ON); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); +@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 17; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < smallest_err) { ++ smallest_err= this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (smallest_err == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) ++ / (pixel_p1 * 10))); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ edid.x_resolution * edid.y_resolution * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } ++ ++ + } + + /* compare the header of the vga edid header */ +@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(mmio + GMBUS0); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); +@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) +- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch new file mode 100644 index 00000000..fb30c4c2 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch @@ -0,0 +1,31 @@ +From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 8 Sep 2016 22:21:54 +0200 +Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT + +The correct id string for gm45 is "$VBT CANTIGA ". +This can be found in the gm45 option rom: +"strings vbios.bin | grep VBT". + +Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..19bd944 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, +- "$VBT IRONLAKE-MOBILE"); ++ "$VBT CANTIGA "); + } + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list new file mode 100644 index 00000000..59e0a36a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch new file mode 100644 index 00000000..67420ca7 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch @@ -0,0 +1,601 @@ +From fbbc8d6a278c733eca475c17cbf95a8946e2c173 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 4 Aug 2016 11:00:13 +0200 +Subject: [PATCH 1/3] Revert "drivers/lenovo: Add hybrid graphics driver" + +This reverts commit 5919ba42ed0ce5b1b13717514698444232c6036c. + +Change-Id: I027581ef769ca8232e72f89738c1bdec13f62687 + +diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig +index f8eddf2..f20f3b2 100644 +--- a/src/drivers/lenovo/Kconfig ++++ b/src/drivers/lenovo/Kconfig +@@ -27,16 +27,3 @@ config DIGITIZER_ABSENT + endchoice + + endif +- +-config DRIVERS_LENOVO_HYBRID_GRAPHICS +- bool +- default n +- +-config HYBRID_GRAPHICS_GPIO_NUM +- depends on DRIVERS_LENOVO_HYBRID_GRAPHICS +- int +- default 52 +- help +- Set a default GPIO that sets the panel LVDS signal routing to +- integrated or discrete GPU. +- +diff --git a/src/drivers/lenovo/Makefile.inc b/src/drivers/lenovo/Makefile.inc +index 66f8594..c50db5b 100644 +--- a/src/drivers/lenovo/Makefile.inc ++++ b/src/drivers/lenovo/Makefile.inc +@@ -1,2 +1 @@ + ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c +-ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c +diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c +deleted file mode 100644 +index 9b46646..0000000 +--- a/src/drivers/lenovo/hybrid_graphics.c ++++ /dev/null +@@ -1,125 +0,0 @@ +-/* +- * This file is part of the coreboot project. +- * +- * Copyright (C) 2015-2016 Patrick Rudolph +- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include <types.h> +-#include <string.h> +-#include <option.h> +-#include <device/device.h> +-#include <device/pci_def.h> +-#include <device/pci_ops.h> +-#include <device/pci_ids.h> +-#include <device/pci.h> +-#include <console/console.h> +-#include <southbridge/intel/common/gpio.h> +- +-/* Hybrid graphics allows to connect LVDS interface to either iGPU +- * or dGPU depending on GPIO level. +- * Nvidia is calling this functionality "muxed Optimus". +- * Some devices, like T430s, only support "muxless Optimus" where the +- * Intel GPU is always connected to the panel. +- * As it is only linked on lenovo and only executed if the GPU exists +- * we know for sure that the dGPU is there and connected to first PEG slot. +- * +- * Note: Once native gfx init is done for AMD or Nvida graphic +- * cards, merge this code. +- */ +- +-#define HYBRID_GRAPHICS_INTEGRATED 0 +-#define HYBRID_GRAPHICS_DISCRETE 1 +- +-static void hybrid_graphics_disable_peg(struct device *dev) +-{ +- struct device *peg_dev; +- +- /* connect LVDS interface to iGPU */ +- set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); +- printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); +- dev->enabled = 0; +- +- /* Disable PEG10 */ +- peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); +- if (peg_dev) +- peg_dev->enabled = 0; +- +- printk(BIOS_DEBUG, "Hybrid graphics: Disabled PEG10.\n"); +-} +- +-/* Called before VGA enable bits are set and only if dGPU +- * is present. Enable/disable VGA devices here. */ +-static void hybrid_graphics_enable_peg(struct device *dev) +-{ +- u8 hybrid_graphics_mode; +- +- hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; +- get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); +- +- if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { +- /* connect LVDS interface to dGPU */ +- set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); +- printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); +- dev->enabled = 1; +- +- /* Disable IGD */ +- dev = dev_find_slot(0, PCI_DEVFN(2, 0)); +- if (dev && dev->ops->disable) +- dev->ops->disable(dev); +- dev->enabled = 0; +- +- printk(BIOS_DEBUG, "Hybrid graphics: Disabled IGD.\n"); +- } else +- hybrid_graphics_disable_peg(dev); +-} +- +-static struct pci_operations pci_dev_ops_pci = { +- .set_subsystem = pci_dev_set_subsystem, +-}; +- +-struct device_operations hybrid_graphics_ops = { +- .read_resources = pci_dev_read_resources, +- .set_resources = pci_dev_set_resources, +- .enable_resources = pci_dev_enable_resources, +- .init = pci_dev_init, +- .scan_bus = 0, +- .enable = hybrid_graphics_enable_peg, +- .disable = hybrid_graphics_disable_peg, +- .ops_pci = &pci_dev_ops_pci, +-}; +- +-static const unsigned short pci_device_ids_nvidia[] = { +- 0x0ffc, /* Nvidia NVS Quadro K1000m Lenovo W530 */ +- 0x0def, /* NVidia NVS 5400m Lenovo T430/T530 */ +- 0x0dfc, /* NVidia NVS 5200m Lenovo T430s */ +- 0x1056, /* NVidia NVS 4200m Lenovo T420/T520 */ +- 0x1057, /* NVidia NVS 4200m Lenovo T420/T520 */ +- 0x0a6c, /* NVidia NVS 3100m Lenovo T410/T510 */ +- 0 }; +- +-static const struct pci_driver hybrid_peg_nvidia __pci_driver = { +- .ops = &hybrid_graphics_ops, +- .vendor = PCI_VENDOR_ID_NVIDIA, +- .devices = pci_device_ids_nvidia, +-}; +- +-static const unsigned short pci_device_ids_amd[] = { +- 0x9591, /* ATI Mobility Radeon HD 3650 Lenovo T500/W500 */ +- 0x95c4, /* ATI Mobility Radeon HD 3470 Lenovo T400/R400 */ +- 0 }; +- +-static const struct pci_driver hybrid_peg_amd __pci_driver = { +- .ops = &hybrid_graphics_ops, +- .vendor = PCI_VENDOR_ID_ATI, +- .devices = pci_device_ids_amd, +-}; +diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig +index a444bf8..d74a813 100644 +--- a/src/mainboard/lenovo/t400/Kconfig ++++ b/src/mainboard/lenovo/t400/Kconfig +@@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select INTEL_INT15 + select SUPERIO_NSC_PC87382 +- select DRIVERS_LENOVO_HYBRID_GRAPHICS + + config MAINBOARD_DIR + string +diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default +index 5cf3e63..ac9f96d 100644 +--- a/src/mainboard/lenovo/t400/cmos.default ++++ b/src/mainboard/lenovo/t400/cmos.default +@@ -13,5 +13,3 @@ sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI +-hybrid_graphics_mode=Integrated Only +-gfx_uma_size=32M +\ No newline at end of file +diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout +index b4b7766..e1a088d 100644 +--- a/src/mainboard/lenovo/t400/cmos.layout ++++ b/src/mainboard/lenovo/t400/cmos.layout +@@ -77,8 +77,7 @@ entries + 940 1 e 1 uwb + + # coreboot config options: northbridge +-944 2 e 12 hybrid_graphics_mode +-946 4 e 11 gfx_uma_size ++941 4 e 11 gfx_uma_size + + # coreboot config options: EC + 952 8 h 0 volume +diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default +index 3a82c97..1b8e212 100644 +--- a/src/mainboard/lenovo/t420/cmos.default ++++ b/src/mainboard/lenovo/t420/cmos.default +@@ -14,4 +14,3 @@ fn_ctrl_swap=Disable + sticky_fn=Disable + trackpoint=Enable + hyper_threading=Enable +-hybrid_graphics_mode=Integrated Only +\ No newline at end of file +diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout +index 58a4abe..bf0f195 100644 +--- a/src/mainboard/lenovo/t420/cmos.layout ++++ b/src/mainboard/lenovo/t420/cmos.layout +@@ -77,8 +77,7 @@ entries + + # coreboot config options: northbridge + 432 3 e 11 gfx_uma_size +-435 2 e 12 hybrid_graphics_mode +-#437 3 r 0 unused ++#435 5 r 0 unused + + 440 8 h 0 volume + +@@ -136,8 +135,6 @@ enumerations + 11 4 160M + 11 5 192M + 11 6 224M +-12 0 Integrated Only +-12 1 Discrete Only + + # ----------------------------------------------------------------- + checksums +diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig +index feacb51..935e659 100644 +--- a/src/mainboard/lenovo/t420s/Kconfig ++++ b/src/mainboard/lenovo/t420s/Kconfig +@@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy + select INTEL_INT15 + select SANDYBRIDGE_IVYBRIDGE_LVDS + select MAINBOARD_HAS_LPC_TPM +- select DRIVERS_LENOVO_HYBRID_GRAPHICS + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE +diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default +index 3a82c97..1b8e212 100644 +--- a/src/mainboard/lenovo/t420s/cmos.default ++++ b/src/mainboard/lenovo/t420s/cmos.default +@@ -14,4 +14,3 @@ fn_ctrl_swap=Disable + sticky_fn=Disable + trackpoint=Enable + hyper_threading=Enable +-hybrid_graphics_mode=Integrated Only +\ No newline at end of file +diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout +index 3521849..43628406 100644 +--- a/src/mainboard/lenovo/t420s/cmos.layout ++++ b/src/mainboard/lenovo/t420s/cmos.layout +@@ -77,8 +77,7 @@ entries + + # coreboot config options: northbridge + 432 3 e 11 gfx_uma_size +-435 2 e 12 hybrid_graphics_mode +-#437 3 r 0 unused ++#435 5 r 0 unused + + 440 8 h 0 volume + +@@ -136,8 +135,6 @@ enumerations + 11 4 160M + 11 5 192M + 11 6 224M +-12 0 Integrated Only +-12 1 Discrete Only + + # ----------------------------------------------------------------- + checksums +diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig +index ee5dd81..c70581a 100644 +--- a/src/mainboard/lenovo/t520/Kconfig ++++ b/src/mainboard/lenovo/t520/Kconfig +@@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy + select INTEL_INT15 + select SANDYBRIDGE_IVYBRIDGE_LVDS + select MAINBOARD_HAS_LPC_TPM +- select DRIVERS_LENOVO_HYBRID_GRAPHICS + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE +diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default +index ad7dcf5..00e8863 100644 +--- a/src/mainboard/lenovo/t520/cmos.default ++++ b/src/mainboard/lenovo/t520/cmos.default +@@ -15,4 +15,3 @@ sticky_fn=Disable + trackpoint=Enable + hyper_threading=Enable + backlight=Both +-hybrid_graphics_mode=Integrated Only +\ No newline at end of file +diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout +index 044c310..2cf3629 100644 +--- a/src/mainboard/lenovo/t520/cmos.layout ++++ b/src/mainboard/lenovo/t520/cmos.layout +@@ -77,8 +77,7 @@ entries + + # coreboot config options: northbridge + 432 3 e 11 gfx_uma_size +-435 2 e 12 hybrid_graphics_mode +-#437 3 r 0 unused ++#435 5 r 0 unused + 440 8 h 0 volume + + # SandyBridge MRC Scrambler Seed values +@@ -135,8 +134,6 @@ enumerations + 11 4 160M + 11 5 192M + 11 6 224M +-12 0 Integrated Only +-12 1 Discrete Only + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig +index 76147fc..030c01f 100644 +--- a/src/mainboard/lenovo/t530/Kconfig ++++ b/src/mainboard/lenovo/t530/Kconfig +@@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy + select SANDYBRIDGE_IVYBRIDGE_LVDS + select ENABLE_VMX + select MAINBOARD_HAS_LPC_TPM +- select DRIVERS_LENOVO_HYBRID_GRAPHICS + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE +diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default +index ad7dcf5..00e8863 100644 +--- a/src/mainboard/lenovo/t530/cmos.default ++++ b/src/mainboard/lenovo/t530/cmos.default +@@ -15,4 +15,3 @@ sticky_fn=Disable + trackpoint=Enable + hyper_threading=Enable + backlight=Both +-hybrid_graphics_mode=Integrated Only +\ No newline at end of file +diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout +index 0e28bdd..e21c197 100644 +--- a/src/mainboard/lenovo/t530/cmos.layout ++++ b/src/mainboard/lenovo/t530/cmos.layout +@@ -77,8 +77,7 @@ entries + + # coreboot config options: northbridge + 432 3 e 11 gfx_uma_size +-435 2 e 12 hybrid_graphics_mode +-#437 3 r 0 unused ++#435 5 r 0 unused + + 440 8 h 0 volume + +@@ -136,9 +135,6 @@ enumerations + 11 4 160M + 11 5 192M + 11 6 224M +-12 0 Integrated Only +-12 1 Discrete Only +- + # ----------------------------------------------------------------- + checksums + +diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig +index b3e5069..2822774 100644 +--- a/src/southbridge/intel/i82801ix/Kconfig ++++ b/src/southbridge/intel/i82801ix/Kconfig +@@ -23,7 +23,6 @@ config SOUTHBRIDGE_INTEL_I82801IX + select USE_WATCHDOG_ON_BOOT + select HAVE_SMI_HANDLER + select HAVE_USBDEBUG_OPTIONS +- select SOUTHBRIDGE_INTEL_COMMON_GPIO + + if SOUTHBRIDGE_INTEL_I82801IX + +-- +2.9.2 + +From 90f5f34629ff88506bb803988da1552f3373d4f0 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 4 Aug 2016 11:01:53 +0200 +Subject: [PATCH 2/3] Revert "Revert "mainboard/lenovo/t400: Add initial hybrid + graphics support"" + +This reverts commit 14d1a93e444b91311eeed2a25953bf6c0779cdcb. + +Change-Id: I965ea55bddb7cf919e7b02ecf8e160c9ad3ea3d4 + +diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default +index ac9f96d..98ce970 100644 +--- a/src/mainboard/lenovo/t400/cmos.default ++++ b/src/mainboard/lenovo/t400/cmos.default +@@ -13,3 +13,4 @@ sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI ++hybrid_graphics_mode=Integrated Only +\ No newline at end of file +diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout +index e1a088d..b4b7766 100644 +--- a/src/mainboard/lenovo/t400/cmos.layout ++++ b/src/mainboard/lenovo/t400/cmos.layout +@@ -77,7 +77,8 @@ entries + 940 1 e 1 uwb + + # coreboot config options: northbridge +-941 4 e 11 gfx_uma_size ++944 2 e 12 hybrid_graphics_mode ++946 4 e 11 gfx_uma_size + + # coreboot config options: EC + 952 8 h 0 volume +diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c +index f518775..fcc545b 100644 +--- a/src/mainboard/lenovo/t400/romstage.c ++++ b/src/mainboard/lenovo/t400/romstage.c +@@ -1,6 +1,7 @@ + /* + * This file is part of the coreboot project. + * ++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or +@@ -34,6 +35,118 @@ + #define LPC_DEV PCI_DEV(0, 0x1f, 0) + #define MCH_DEV PCI_DEV(0, 0, 0) + ++#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 ++#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 ++#define HYBRID_GRAPHICS_SWITCHABLE 2 ++ ++#define HYBRID_GRAPHICS_GP_LVL_BITS 0x004a0000 ++#define HYBRID_GRAPHICS_GP_LVL2_BITS 0x00020000 ++ ++#define HYBRID_GRAPHICS_DETECT_GP_BITS 0x00000010 ++ ++#define HYBRID_GRAPHICS_INT_CLAIM_VGA 0x2 ++#define HYBRID_GRAPHICS_SEC_VGA_EN 0x2 ++ ++static void hybrid_graphics_configure_switchable_graphics(bool enable) ++{ ++ uint32_t tmp; ++ ++ if (enable) { ++ /* Disable integrated graphics legacy VGA cycles */ ++ tmp = pci_read_config16(MCH_DEV, D0F0_GGC); ++ pci_write_config16(MCH_DEV, D0F0_GGC, tmp | HYBRID_GRAPHICS_INT_CLAIM_VGA); ++ ++ /* Enable secondary VGA controller */ ++ tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); ++ pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp | HYBRID_GRAPHICS_SEC_VGA_EN); ++ } ++ else { ++ /* Enable integrated graphics legacy VGA cycles */ ++ tmp = pci_read_config16(MCH_DEV, D0F0_GGC); ++ pci_write_config16(MCH_DEV, D0F0_GGC, tmp & ~HYBRID_GRAPHICS_INT_CLAIM_VGA); ++ ++ /* Disable secondary VGA controller */ ++ tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); ++ pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp & ~HYBRID_GRAPHICS_SEC_VGA_EN); ++ } ++} ++ ++static void hybrid_graphics_set_up_gpio(void) ++{ ++ uint32_t tmp; ++ ++ /* Enable hybrid graphics GPIO lines */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL); ++ tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL); ++ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL2); ++ tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); ++ ++ /* Set hybrid graphics control GPIO lines to output */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); ++ tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); ++ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL2); ++ tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL2); ++ ++ /* Set hybrid graphics detect GPIO lines to input */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); ++ tmp = tmp | HYBRID_GRAPHICS_DETECT_GP_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); ++} ++ ++static bool hybrid_graphics_installed(void) ++{ ++ if (inl(DEFAULT_GPIOBASE + GP_LVL) & HYBRID_GRAPHICS_DETECT_GP_BITS) ++ return false; ++ else ++ return true; ++} ++ ++static void hybrid_graphics_switch_to_integrated_graphics(void) ++{ ++ uint32_t tmp; ++ ++ /* Disable switchable graphics */ ++ hybrid_graphics_configure_switchable_graphics(false); ++ ++ /* Configure muxes */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_LVL); ++ tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_LVL); ++ ++ tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); ++ tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); ++} ++ ++static void hybrid_graphics_switch_to_discrete_graphics(void) ++{ ++ uint32_t tmp; ++ ++ /* Disable switchable graphics */ ++ hybrid_graphics_configure_switchable_graphics(false); ++ ++ /* Configure muxes */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_LVL); ++ tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_LVL); ++ ++ tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); ++ tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); ++} ++ ++static void hybrid_graphics_switch_to_dual_graphics(void) ++{ ++ /* Enable switchable graphics */ ++ hybrid_graphics_configure_switchable_graphics(true); ++} ++ + static void default_southbridge_gpio_setup(void) + { + outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); +@@ -95,6 +208,31 @@ void mainboard_romstage_entry(unsigned long bist) + + default_southbridge_gpio_setup(); + ++ uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; ++ get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); ++ ++ /* Set up hybrid graphics */ ++ hybrid_graphics_set_up_gpio(); ++ if (hybrid_graphics_installed()) { ++ /* Select appropriate hybrid graphics device */ ++ printk(BIOS_DEBUG, "Hybrid graphics available, setting mode %d\n", hybrid_graphics_mode); ++ if (hybrid_graphics_mode == HYBRID_GRAPHICS_INTEGRATED_ONLY) ++ hybrid_graphics_switch_to_integrated_graphics(); ++ else if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE_ONLY) ++ hybrid_graphics_switch_to_discrete_graphics(); ++ else if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) ++ hybrid_graphics_switch_to_integrated_graphics(); ++ /* Switchable graphics are fully enabled after raminit */ ++ /* FIXME ++ * Enabling switchable graphics prevents bootup! ++ * Debug and fix appropriately... ++ */ ++ } ++ else { ++ printk(BIOS_DEBUG, "Hybrid graphics not installed\n"); ++ hybrid_graphics_switch_to_integrated_graphics(); ++ } ++ + /* ASPM related setting, set early by original BIOS. */ + DMIBAR16(0x204) &= ~(3 << 10); + +@@ -174,6 +312,11 @@ void mainboard_romstage_entry(unsigned long bist) + outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38); + + cbmem_initted = !cbmem_recovery(s3resume); ++ ++ if (hybrid_graphics_installed()) ++ if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) ++ hybrid_graphics_switch_to_dual_graphics(); ++ + #if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. +-- +2.9.2 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch new file mode 100644 index 00000000..26632b7d --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch @@ -0,0 +1,212 @@ +From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 22 Aug 2016 17:58:46 +0200 +Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected + +The intel x4x and gm45 have very similar integrated graphic devices. +Currently the x4x native graphic init enables VGA, while gm45 can output +on LVDS. + +This patch reuses the x4x graphic initialisation code +to enable output on VGA in gm45 in a way that the behavior is similar to vbios: +If no VGA display is connected the internal LVDS screen is used. +If an external screen is detected on the VGA port it will be used instead. + +Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 153 insertions(+), 4 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..74c9bc3 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) + write32(res2mmio(gtt_res, reg, 0), data); + } + +-static void intel_gma_init(const struct northbridge_intel_gm45_config *info, ++static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + +@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + sizeof(edid_data), &edid); + mode = &edid.mode; + +- /* Disable screen memory to prevent garbage from appearing. */ ++ /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; +@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + } + } + ++static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ++ u8 *mmio) ++{ ++ ++ int i; ++ u32 hactive, vactive; ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(mmio + VGA0, 0x31108); ++ write32(mmio + VGA1, 0x31406); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + 0x7041c, 0x0); ++ write32(mmio + DPLL_MD(0), 0x3); ++ write32(mmio + DPLL_MD(1), 0x3); ++ ++ vga_misc_write(0x67); ++ ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ /* Disable screen memory to prevent garbage from appearing. */ ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(mmio + FP0(0), 0x31108); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ mdelay(1); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); ++ ++ write32(mmio + PF_WIN_POS(0), 0); ++ ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0xa0000000); ++ ++ mdelay(1); ++ ++ write32(mmio + 0x000f000c, 0x00002040); ++ mdelay(1); ++ write32(mmio + 0x000f000c, 0x00002050); ++ write32(mmio + 0x00060100, 0x00044000); ++ mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_ENABLE ++ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(mmio + VGACNTRL, 0x0); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ /* Clear interrupts. */ ++ write32(mmio + DEIIR, 0xffffffff); ++ write32(mmio + SDEIIR, 0xffffffff); ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should not have a correct header */ ++static u8 vga_connected(u8 *mmio) ++{ ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + static void gma_pm_init_post_vbios(struct device *const dev) + { + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; +@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, +- pio_res->base, lfb_res->base); ++ if (vga_connected(res2mmio(gtt_res, 0, 0))) ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ else ++ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch new file mode 100644 index 00000000..49b9549a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch @@ -0,0 +1,35 @@ +From 873402fb594f06e748563ebf3abc7970613b9bda Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 8 Aug 2016 23:55:13 +0200 +Subject: [PATCH] make 256M vram the default for gm45 laptops + +Change-Id: Id213807d1ed3260846118f69b459bcad7a146c30 + +diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default +index 98ce970..90d796f 100644 +--- a/src/mainboard/lenovo/t400/cmos.default ++++ b/src/mainboard/lenovo/t400/cmos.default +@@ -13,4 +13,5 @@ sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI +-hybrid_graphics_mode=Integrated Only +\ No newline at end of file ++hybrid_graphics_mode=Integrated Only ++gfx_uma_size=256M +\ No newline at end of file +diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default +index 1d7b420..ec7ab46 100644 +--- a/src/mainboard/lenovo/x200/cmos.default ++++ b/src/mainboard/lenovo/x200/cmos.default +@@ -13,4 +13,4 @@ sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI +-gfx_uma_size=32M +\ No newline at end of file ++gfx_uma_size=256M +\ No newline at end of file +-- +2.9.2 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch new file mode 100644 index 00000000..76463937 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch @@ -0,0 +1,27 @@ +From 99b8fb271fd244d8e349ca956819c7e1b3420d80 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 8 Aug 2016 21:51:34 +0200 +Subject: [PATCH] hardcode use on intel integrated graphic device on t400 + +Change-Id: I2ff2d93b024866063715d26aedf510a9753a5445 +--- + src/mainboard/lenovo/t400/romstage.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c +index 147131f..1316d69 100644 +--- a/src/mainboard/lenovo/t400/romstage.c ++++ b/src/mainboard/lenovo/t400/romstage.c +@@ -208,7 +208,8 @@ void main(unsigned long bist) + default_southbridge_gpio_setup(); + + uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; +- get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); ++ /* hardcode use of integrated graphic device for libreboot */ ++ /* get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); */ + + /* Set up hybrid graphics */ + hybrid_graphics_set_up_gpio(); +-- +2.9.2 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch new file mode 100644 index 00000000..ef42f3e8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch @@ -0,0 +1,379 @@ +From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sat, 27 Aug 2016 01:09:19 +0200 +Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output + +This implements "Keep VESA framebuffer" behavior on VGA output of gm45. +This patch reuses Linux code to compute vga divisors. + +Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- + 1 file changed, 209 insertions(+), 42 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index 74c9bc3..efaa210 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -25,6 +25,7 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" +@@ -35,6 +36,8 @@ + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUECY 96000 ++ + static struct resource *gtt_res = NULL; + + u32 gtt_read(u32 reg) +@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + } + + static void gma_init_vga(const struct northbridge_intel_gm45_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u32 hactive, vactive, right_border, bottom_border; ++ int hpolarity, vpolarity; ++ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; ++ u32 target_frequency; ++ u32 smallest_err = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Setup GTT. */ ++ for (i = 0; i < 0x2000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE +- | ADPA_DPMS_ON +- ); ++ | ADPA_DPMS_ON); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); +@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 17; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < smallest_err) { ++ smallest_err= this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (smallest_err == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) ++ / (pixel_p1 * 10))); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ edid.x_resolution * edid.y_resolution * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } ++ ++ + } + + /* compare the header of the vga edid header */ +@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(mmio + GMBUS0); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); +@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) +- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch new file mode 100644 index 00000000..fb30c4c2 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch @@ -0,0 +1,31 @@ +From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 8 Sep 2016 22:21:54 +0200 +Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT + +The correct id string for gm45 is "$VBT CANTIGA ". +This can be found in the gm45 option rom: +"strings vbios.bin | grep VBT". + +Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..19bd944 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, +- "$VBT IRONLAKE-MOBILE"); ++ "$VBT CANTIGA "); + } + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/INFO b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/INFO new file mode 100644 index 00000000..9ef6d54a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/INFO @@ -0,0 +1,8 @@ +# NOTE: merged upstream already +printf "mainboard/lenovo/t400: Add initial hybrid graphics support\n" +git am "../resources/libreboot/patch/misc/0001-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/19/9319/18 && git cherry-pick FETCH_HEAD + +printf "NOTFORMERGE: lenovo/t400: hard-code enable integrated-only video\n" +git am "../resources/libreboot/patch/misc/0002-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/50/10550/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list new file mode 100644 index 00000000..4ea9a7ad --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list @@ -0,0 +1,4 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch new file mode 100644 index 00000000..26632b7d --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch @@ -0,0 +1,212 @@ +From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 22 Aug 2016 17:58:46 +0200 +Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected + +The intel x4x and gm45 have very similar integrated graphic devices. +Currently the x4x native graphic init enables VGA, while gm45 can output +on LVDS. + +This patch reuses the x4x graphic initialisation code +to enable output on VGA in gm45 in a way that the behavior is similar to vbios: +If no VGA display is connected the internal LVDS screen is used. +If an external screen is detected on the VGA port it will be used instead. + +Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 153 insertions(+), 4 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..74c9bc3 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) + write32(res2mmio(gtt_res, reg, 0), data); + } + +-static void intel_gma_init(const struct northbridge_intel_gm45_config *info, ++static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + +@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + sizeof(edid_data), &edid); + mode = &edid.mode; + +- /* Disable screen memory to prevent garbage from appearing. */ ++ /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; +@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + } + } + ++static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ++ u8 *mmio) ++{ ++ ++ int i; ++ u32 hactive, vactive; ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(mmio + VGA0, 0x31108); ++ write32(mmio + VGA1, 0x31406); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + 0x7041c, 0x0); ++ write32(mmio + DPLL_MD(0), 0x3); ++ write32(mmio + DPLL_MD(1), 0x3); ++ ++ vga_misc_write(0x67); ++ ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ /* Disable screen memory to prevent garbage from appearing. */ ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(mmio + FP0(0), 0x31108); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ mdelay(1); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); ++ ++ write32(mmio + PF_WIN_POS(0), 0); ++ ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0xa0000000); ++ ++ mdelay(1); ++ ++ write32(mmio + 0x000f000c, 0x00002040); ++ mdelay(1); ++ write32(mmio + 0x000f000c, 0x00002050); ++ write32(mmio + 0x00060100, 0x00044000); ++ mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_ENABLE ++ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(mmio + VGACNTRL, 0x0); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ /* Clear interrupts. */ ++ write32(mmio + DEIIR, 0xffffffff); ++ write32(mmio + SDEIIR, 0xffffffff); ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should not have a correct header */ ++static u8 vga_connected(u8 *mmio) ++{ ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + static void gma_pm_init_post_vbios(struct device *const dev) + { + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; +@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, +- pio_res->base, lfb_res->base); ++ if (vga_connected(res2mmio(gtt_res, 0, 0))) ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ else ++ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch new file mode 100644 index 00000000..ef42f3e8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch @@ -0,0 +1,379 @@ +From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sat, 27 Aug 2016 01:09:19 +0200 +Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output + +This implements "Keep VESA framebuffer" behavior on VGA output of gm45. +This patch reuses Linux code to compute vga divisors. + +Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- + 1 file changed, 209 insertions(+), 42 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index 74c9bc3..efaa210 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -25,6 +25,7 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" +@@ -35,6 +36,8 @@ + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUECY 96000 ++ + static struct resource *gtt_res = NULL; + + u32 gtt_read(u32 reg) +@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + } + + static void gma_init_vga(const struct northbridge_intel_gm45_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u32 hactive, vactive, right_border, bottom_border; ++ int hpolarity, vpolarity; ++ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; ++ u32 target_frequency; ++ u32 smallest_err = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Setup GTT. */ ++ for (i = 0; i < 0x2000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE +- | ADPA_DPMS_ON +- ); ++ | ADPA_DPMS_ON); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); +@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 17; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < smallest_err) { ++ smallest_err= this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (smallest_err == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) ++ / (pixel_p1 * 10))); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ edid.x_resolution * edid.y_resolution * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } ++ ++ + } + + /* compare the header of the vga edid header */ +@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(mmio + GMBUS0); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); +@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) +- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch new file mode 100644 index 00000000..fb30c4c2 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch @@ -0,0 +1,31 @@ +From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 8 Sep 2016 22:21:54 +0200 +Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT + +The correct id string for gm45 is "$VBT CANTIGA ". +This can be found in the gm45 option rom: +"strings vbios.bin | grep VBT". + +Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..19bd944 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, +- "$VBT IRONLAKE-MOBILE"); ++ "$VBT CANTIGA "); + } + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/INFO b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/INFO new file mode 100644 index 00000000..0537bbc8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/INFO @@ -0,0 +1,4 @@ +# NOTE: remove this when updating coreboot. This has been merged upstream +printf "ThinkPad T500 (depends on T400 patch)\n" +git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list new file mode 100644 index 00000000..59e0a36a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch new file mode 100644 index 00000000..26632b7d --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch @@ -0,0 +1,212 @@ +From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 22 Aug 2016 17:58:46 +0200 +Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected + +The intel x4x and gm45 have very similar integrated graphic devices. +Currently the x4x native graphic init enables VGA, while gm45 can output +on LVDS. + +This patch reuses the x4x graphic initialisation code +to enable output on VGA in gm45 in a way that the behavior is similar to vbios: +If no VGA display is connected the internal LVDS screen is used. +If an external screen is detected on the VGA port it will be used instead. + +Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 153 insertions(+), 4 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..74c9bc3 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) + write32(res2mmio(gtt_res, reg, 0), data); + } + +-static void intel_gma_init(const struct northbridge_intel_gm45_config *info, ++static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + +@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + sizeof(edid_data), &edid); + mode = &edid.mode; + +- /* Disable screen memory to prevent garbage from appearing. */ ++ /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; +@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + } + } + ++static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ++ u8 *mmio) ++{ ++ ++ int i; ++ u32 hactive, vactive; ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(mmio + VGA0, 0x31108); ++ write32(mmio + VGA1, 0x31406); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + 0x7041c, 0x0); ++ write32(mmio + DPLL_MD(0), 0x3); ++ write32(mmio + DPLL_MD(1), 0x3); ++ ++ vga_misc_write(0x67); ++ ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ /* Disable screen memory to prevent garbage from appearing. */ ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(mmio + FP0(0), 0x31108); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ mdelay(1); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); ++ ++ write32(mmio + PF_WIN_POS(0), 0); ++ ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0xa0000000); ++ ++ mdelay(1); ++ ++ write32(mmio + 0x000f000c, 0x00002040); ++ mdelay(1); ++ write32(mmio + 0x000f000c, 0x00002050); ++ write32(mmio + 0x00060100, 0x00044000); ++ mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_ENABLE ++ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(mmio + VGACNTRL, 0x0); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ /* Clear interrupts. */ ++ write32(mmio + DEIIR, 0xffffffff); ++ write32(mmio + SDEIIR, 0xffffffff); ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should not have a correct header */ ++static u8 vga_connected(u8 *mmio) ++{ ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + static void gma_pm_init_post_vbios(struct device *const dev) + { + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; +@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, +- pio_res->base, lfb_res->base); ++ if (vga_connected(res2mmio(gtt_res, 0, 0))) ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ else ++ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch new file mode 100644 index 00000000..ef42f3e8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch @@ -0,0 +1,379 @@ +From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sat, 27 Aug 2016 01:09:19 +0200 +Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output + +This implements "Keep VESA framebuffer" behavior on VGA output of gm45. +This patch reuses Linux code to compute vga divisors. + +Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- + 1 file changed, 209 insertions(+), 42 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index 74c9bc3..efaa210 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -25,6 +25,7 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" +@@ -35,6 +36,8 @@ + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUECY 96000 ++ + static struct resource *gtt_res = NULL; + + u32 gtt_read(u32 reg) +@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + } + + static void gma_init_vga(const struct northbridge_intel_gm45_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u32 hactive, vactive, right_border, bottom_border; ++ int hpolarity, vpolarity; ++ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; ++ u32 target_frequency; ++ u32 smallest_err = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Setup GTT. */ ++ for (i = 0; i < 0x2000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE +- | ADPA_DPMS_ON +- ); ++ | ADPA_DPMS_ON); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); +@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 17; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < smallest_err) { ++ smallest_err= this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (smallest_err == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) ++ / (pixel_p1 * 10))); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ edid.x_resolution * edid.y_resolution * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } ++ ++ + } + + /* compare the header of the vga edid header */ +@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(mmio + GMBUS0); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); +@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) +- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch new file mode 100644 index 00000000..fb30c4c2 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch @@ -0,0 +1,31 @@ +From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 8 Sep 2016 22:21:54 +0200 +Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT + +The correct id string for gm45 is "$VBT CANTIGA ". +This can be found in the gm45 option rom: +"strings vbios.bin | grep VBT". + +Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..19bd944 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, +- "$VBT IRONLAKE-MOBILE"); ++ "$VBT CANTIGA "); + } + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list new file mode 100644 index 00000000..59e0a36a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch new file mode 100644 index 00000000..26632b7d --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch @@ -0,0 +1,212 @@ +From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 22 Aug 2016 17:58:46 +0200 +Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected + +The intel x4x and gm45 have very similar integrated graphic devices. +Currently the x4x native graphic init enables VGA, while gm45 can output +on LVDS. + +This patch reuses the x4x graphic initialisation code +to enable output on VGA in gm45 in a way that the behavior is similar to vbios: +If no VGA display is connected the internal LVDS screen is used. +If an external screen is detected on the VGA port it will be used instead. + +Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 153 insertions(+), 4 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..74c9bc3 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) + write32(res2mmio(gtt_res, reg, 0), data); + } + +-static void intel_gma_init(const struct northbridge_intel_gm45_config *info, ++static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + +@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + sizeof(edid_data), &edid); + mode = &edid.mode; + +- /* Disable screen memory to prevent garbage from appearing. */ ++ /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; +@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + } + } + ++static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ++ u8 *mmio) ++{ ++ ++ int i; ++ u32 hactive, vactive; ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(mmio + VGA0, 0x31108); ++ write32(mmio + VGA1, 0x31406); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + 0x7041c, 0x0); ++ write32(mmio + DPLL_MD(0), 0x3); ++ write32(mmio + DPLL_MD(1), 0x3); ++ ++ vga_misc_write(0x67); ++ ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ /* Disable screen memory to prevent garbage from appearing. */ ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(mmio + FP0(0), 0x31108); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ mdelay(1); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); ++ ++ write32(mmio + PF_WIN_POS(0), 0); ++ ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0xa0000000); ++ ++ mdelay(1); ++ ++ write32(mmio + 0x000f000c, 0x00002040); ++ mdelay(1); ++ write32(mmio + 0x000f000c, 0x00002050); ++ write32(mmio + 0x00060100, 0x00044000); ++ mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_ENABLE ++ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(mmio + VGACNTRL, 0x0); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ /* Clear interrupts. */ ++ write32(mmio + DEIIR, 0xffffffff); ++ write32(mmio + SDEIIR, 0xffffffff); ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should not have a correct header */ ++static u8 vga_connected(u8 *mmio) ++{ ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + static void gma_pm_init_post_vbios(struct device *const dev) + { + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; +@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, +- pio_res->base, lfb_res->base); ++ if (vga_connected(res2mmio(gtt_res, 0, 0))) ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ else ++ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch new file mode 100644 index 00000000..ef42f3e8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch @@ -0,0 +1,379 @@ +From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sat, 27 Aug 2016 01:09:19 +0200 +Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output + +This implements "Keep VESA framebuffer" behavior on VGA output of gm45. +This patch reuses Linux code to compute vga divisors. + +Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- + 1 file changed, 209 insertions(+), 42 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index 74c9bc3..efaa210 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -25,6 +25,7 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" +@@ -35,6 +36,8 @@ + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUECY 96000 ++ + static struct resource *gtt_res = NULL; + + u32 gtt_read(u32 reg) +@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + } + + static void gma_init_vga(const struct northbridge_intel_gm45_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u32 hactive, vactive, right_border, bottom_border; ++ int hpolarity, vpolarity; ++ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; ++ u32 target_frequency; ++ u32 smallest_err = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Setup GTT. */ ++ for (i = 0; i < 0x2000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE +- | ADPA_DPMS_ON +- ); ++ | ADPA_DPMS_ON); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); +@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 17; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < smallest_err) { ++ smallest_err= this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (smallest_err == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) ++ / (pixel_p1 * 10))); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ edid.x_resolution * edid.y_resolution * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } ++ ++ + } + + /* compare the header of the vga edid header */ +@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(mmio + GMBUS0); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); +@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) +- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch new file mode 100644 index 00000000..fb30c4c2 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch @@ -0,0 +1,31 @@ +From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 8 Sep 2016 22:21:54 +0200 +Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT + +The correct id string for gm45 is "$VBT CANTIGA ". +This can be found in the gm45 option rom: +"strings vbios.bin | grep VBT". + +Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..19bd944 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, +- "$VBT IRONLAKE-MOBILE"); ++ "$VBT CANTIGA "); + } + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/INFO b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/INFO new file mode 100644 index 00000000..0537bbc8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/INFO @@ -0,0 +1,4 @@ +# NOTE: remove this when updating coreboot. This has been merged upstream +printf "ThinkPad T500 (depends on T400 patch)\n" +git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list new file mode 100644 index 00000000..59e0a36a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch new file mode 100644 index 00000000..26632b7d --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch @@ -0,0 +1,212 @@ +From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 22 Aug 2016 17:58:46 +0200 +Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected + +The intel x4x and gm45 have very similar integrated graphic devices. +Currently the x4x native graphic init enables VGA, while gm45 can output +on LVDS. + +This patch reuses the x4x graphic initialisation code +to enable output on VGA in gm45 in a way that the behavior is similar to vbios: +If no VGA display is connected the internal LVDS screen is used. +If an external screen is detected on the VGA port it will be used instead. + +Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 153 insertions(+), 4 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..74c9bc3 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) + write32(res2mmio(gtt_res, reg, 0), data); + } + +-static void intel_gma_init(const struct northbridge_intel_gm45_config *info, ++static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + +@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + sizeof(edid_data), &edid); + mode = &edid.mode; + +- /* Disable screen memory to prevent garbage from appearing. */ ++ /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; +@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + } + } + ++static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ++ u8 *mmio) ++{ ++ ++ int i; ++ u32 hactive, vactive; ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(mmio + VGA0, 0x31108); ++ write32(mmio + VGA1, 0x31406); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + 0x7041c, 0x0); ++ write32(mmio + DPLL_MD(0), 0x3); ++ write32(mmio + DPLL_MD(1), 0x3); ++ ++ vga_misc_write(0x67); ++ ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ /* Disable screen memory to prevent garbage from appearing. */ ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(mmio + FP0(0), 0x31108); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ mdelay(1); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); ++ ++ write32(mmio + PF_WIN_POS(0), 0); ++ ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0xa0000000); ++ ++ mdelay(1); ++ ++ write32(mmio + 0x000f000c, 0x00002040); ++ mdelay(1); ++ write32(mmio + 0x000f000c, 0x00002050); ++ write32(mmio + 0x00060100, 0x00044000); ++ mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_ENABLE ++ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(mmio + VGACNTRL, 0x0); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ /* Clear interrupts. */ ++ write32(mmio + DEIIR, 0xffffffff); ++ write32(mmio + SDEIIR, 0xffffffff); ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should not have a correct header */ ++static u8 vga_connected(u8 *mmio) ++{ ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + static void gma_pm_init_post_vbios(struct device *const dev) + { + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; +@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, +- pio_res->base, lfb_res->base); ++ if (vga_connected(res2mmio(gtt_res, 0, 0))) ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ else ++ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch new file mode 100644 index 00000000..ef42f3e8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch @@ -0,0 +1,379 @@ +From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sat, 27 Aug 2016 01:09:19 +0200 +Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output + +This implements "Keep VESA framebuffer" behavior on VGA output of gm45. +This patch reuses Linux code to compute vga divisors. + +Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- + 1 file changed, 209 insertions(+), 42 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index 74c9bc3..efaa210 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -25,6 +25,7 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" +@@ -35,6 +36,8 @@ + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUECY 96000 ++ + static struct resource *gtt_res = NULL; + + u32 gtt_read(u32 reg) +@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + } + + static void gma_init_vga(const struct northbridge_intel_gm45_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u32 hactive, vactive, right_border, bottom_border; ++ int hpolarity, vpolarity; ++ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; ++ u32 target_frequency; ++ u32 smallest_err = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Setup GTT. */ ++ for (i = 0; i < 0x2000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE +- | ADPA_DPMS_ON +- ); ++ | ADPA_DPMS_ON); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); +@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 17; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < smallest_err) { ++ smallest_err= this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (smallest_err == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) ++ / (pixel_p1 * 10))); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ edid.x_resolution * edid.y_resolution * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } ++ ++ + } + + /* compare the header of the vga edid header */ +@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(mmio + GMBUS0); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); +@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) +- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch new file mode 100644 index 00000000..fb30c4c2 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch @@ -0,0 +1,31 @@ +From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 8 Sep 2016 22:21:54 +0200 +Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT + +The correct id string for gm45 is "$VBT CANTIGA ". +This can be found in the gm45 option rom: +"strings vbios.bin | grep VBT". + +Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..19bd944 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, +- "$VBT IRONLAKE-MOBILE"); ++ "$VBT CANTIGA "); + } + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/INFO b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/INFO new file mode 100644 index 00000000..220b8583 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/INFO @@ -0,0 +1,5 @@ +# NOTE: remove this when updating to the latest version of coreboot. this patch +# makes the patch below redundant: https://review.coreboot.org/#/c/12814/ +printf "northbridge/gm45/raminit.c: enable GS45 high-perf (i.e. add X200S support to libreboot)\n" +git am "../resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/35/11135/3 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list new file mode 100644 index 00000000..8a98e98c --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list @@ -0,0 +1,5 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch new file mode 100644 index 00000000..26632b7d --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch @@ -0,0 +1,212 @@ +From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 22 Aug 2016 17:58:46 +0200 +Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected + +The intel x4x and gm45 have very similar integrated graphic devices. +Currently the x4x native graphic init enables VGA, while gm45 can output +on LVDS. + +This patch reuses the x4x graphic initialisation code +to enable output on VGA in gm45 in a way that the behavior is similar to vbios: +If no VGA display is connected the internal LVDS screen is used. +If an external screen is detected on the VGA port it will be used instead. + +Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 153 insertions(+), 4 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..74c9bc3 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) + write32(res2mmio(gtt_res, reg, 0), data); + } + +-static void intel_gma_init(const struct northbridge_intel_gm45_config *info, ++static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + +@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + sizeof(edid_data), &edid); + mode = &edid.mode; + +- /* Disable screen memory to prevent garbage from appearing. */ ++ /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; +@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + } + } + ++static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ++ u8 *mmio) ++{ ++ ++ int i; ++ u32 hactive, vactive; ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(mmio + VGA0, 0x31108); ++ write32(mmio + VGA1, 0x31406); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + 0x7041c, 0x0); ++ write32(mmio + DPLL_MD(0), 0x3); ++ write32(mmio + DPLL_MD(1), 0x3); ++ ++ vga_misc_write(0x67); ++ ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ /* Disable screen memory to prevent garbage from appearing. */ ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(mmio + FP0(0), 0x31108); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ mdelay(1); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); ++ ++ write32(mmio + PF_WIN_POS(0), 0); ++ ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0xa0000000); ++ ++ mdelay(1); ++ ++ write32(mmio + 0x000f000c, 0x00002040); ++ mdelay(1); ++ write32(mmio + 0x000f000c, 0x00002050); ++ write32(mmio + 0x00060100, 0x00044000); ++ mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_ENABLE ++ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(mmio + VGACNTRL, 0x0); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ /* Clear interrupts. */ ++ write32(mmio + DEIIR, 0xffffffff); ++ write32(mmio + SDEIIR, 0xffffffff); ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should not have a correct header */ ++static u8 vga_connected(u8 *mmio) ++{ ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + static void gma_pm_init_post_vbios(struct device *const dev) + { + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; +@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, +- pio_res->base, lfb_res->base); ++ if (vga_connected(res2mmio(gtt_res, 0, 0))) ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ else ++ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch new file mode 100644 index 00000000..ef42f3e8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch @@ -0,0 +1,379 @@ +From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sat, 27 Aug 2016 01:09:19 +0200 +Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output + +This implements "Keep VESA framebuffer" behavior on VGA output of gm45. +This patch reuses Linux code to compute vga divisors. + +Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- + 1 file changed, 209 insertions(+), 42 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index 74c9bc3..efaa210 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -25,6 +25,7 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" +@@ -35,6 +36,8 @@ + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUECY 96000 ++ + static struct resource *gtt_res = NULL; + + u32 gtt_read(u32 reg) +@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + } + + static void gma_init_vga(const struct northbridge_intel_gm45_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u32 hactive, vactive, right_border, bottom_border; ++ int hpolarity, vpolarity; ++ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; ++ u32 target_frequency; ++ u32 smallest_err = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Setup GTT. */ ++ for (i = 0; i < 0x2000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE +- | ADPA_DPMS_ON +- ); ++ | ADPA_DPMS_ON); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); +@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 17; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < smallest_err) { ++ smallest_err= this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (smallest_err == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) ++ / (pixel_p1 * 10))); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ edid.x_resolution * edid.y_resolution * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } ++ ++ + } + + /* compare the header of the vga edid header */ +@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(mmio + GMBUS0); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); +@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) +- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch new file mode 100644 index 00000000..fb30c4c2 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch @@ -0,0 +1,31 @@ +From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 8 Sep 2016 22:21:54 +0200 +Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT + +The correct id string for gm45 is "$VBT CANTIGA ". +This can be found in the gm45 option rom: +"strings vbios.bin | grep VBT". + +Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..19bd944 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, +- "$VBT IRONLAKE-MOBILE"); ++ "$VBT CANTIGA "); + } + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list new file mode 100644 index 00000000..8a98e98c --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list @@ -0,0 +1,5 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch new file mode 100644 index 00000000..8e5e1dca --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch @@ -0,0 +1,88 @@ +From 63db6e96d846b8cab2df30afdccc6b6b18232e33 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Mon, 13 Oct 2014 00:14:53 +0100 +Subject: [PATCH] NOTFORMERGE: ec/lenovo/h8: + wlan/trackpoint/touchpad/bluetooth/wwan + +Permanently enable them. + +Change-Id: Ic76ab9ab9c865f30312378e18af58bece6c3260a +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/ec/lenovo/h8/h8.c | 21 +++++++++++---------- + src/ec/lenovo/pmh7/pmh7.c | 11 ++++------- + 2 files changed, 15 insertions(+), 17 deletions(-) + +diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c +index 943bdd4..32285ac 100644 +--- a/src/ec/lenovo/h8/h8.c ++++ b/src/ec/lenovo/h8/h8.c +@@ -252,9 +252,11 @@ static void h8_enable(struct device *dev) + + ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); + +- if (get_option(&val, "wlan") != CB_SUCCESS) +- val = 1; +- h8_wlan_enable(val); ++ // Permanently enable wifi ++ // Intel wifi could be a security risk because it uses firmware. Wlan chip has DMA ++ // and could leak data over a side-channel. Using another manufacturer is recommended. ++ // see http://libreboot.org/docs/index.html#recommended_wifi ++ h8_wlan_enable(1); + + h8_trackpoint_enable(1); + h8_usb_power_enable(1); +@@ -262,14 +264,13 @@ static void h8_enable(struct device *dev) + if (get_option(&val, "volume") == CB_SUCCESS && !acpi_is_wakeup_s3()) + ec_write(H8_VOLUME_CONTROL, val); + +- if (get_option(&val, "bluetooth") != CB_SUCCESS) +- val = 1; +- h8_bluetooth_enable(val); +- +- if (get_option(&val, "wwan") != CB_SUCCESS) +- val = 1; ++ // Permanently enable bluetooth. ++ // NOTE: bluetooth is a potential security risk. Physical removal of the bluetooth module is recommended. ++ h8_bluetooth_enable(1); + +- h8_wwan_enable(val); ++ // Permanently enable wwan. ++ // NOTE: wwan is a security risk (remove access plus DMA). Physical removal of both the wwan and sim card is recommended. ++ h8_wwan_enable(1); + + if (conf->has_uwb) { + if (get_option(&val, "uwb") != CB_SUCCESS) +diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c +index b2c3c08..1570cd6 100644 +--- a/src/ec/lenovo/pmh7/pmh7.c ++++ b/src/ec/lenovo/pmh7/pmh7.c +@@ -102,7 +102,6 @@ static void enable_dev(struct device *dev) + { + struct ec_lenovo_pmh7_config *conf = dev->chip_info; + struct resource *resource; +- u8 val; + + resource = new_resource(dev, EC_LENOVO_PMH7_INDEX); + resource->flags = IORESOURCE_IO | IORESOURCE_FIXED; +@@ -114,13 +113,11 @@ static void enable_dev(struct device *dev) + pmh7_backlight_enable(conf->backlight_enable); + pmh7_dock_event_enable(conf->dock_event_enable); + +- if (get_option(&val, "touchpad") != CB_SUCCESS) +- val = 1; +- pmh7_touchpad_enable(val); ++ // Permanently enable touchpad ++ pmh7_touchpad_enable(1); + +- if (get_option(&val, "trackpoint") != CB_SUCCESS) +- val = 1; +- pmh7_trackpoint_enable(val); ++ // Permanently enable trackpoint ++ pmh7_trackpoint_enable(1); + } + + struct chip_operations ec_lenovo_pmh7_ops = { +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch new file mode 100644 index 00000000..046192dd --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch @@ -0,0 +1,45 @@ +From c63113e56ad2d5f6b318a837e4345e0e962a5c1b Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Wed, 4 May 2016 22:49:07 +0200 +Subject: [PATCH 1/1] add acpi c3 / cpu c4 state for gm45 thinpads + +--- + src/mainboard/lenovo/t400/cstates.c | 5 +++++ + src/mainboard/lenovo/x200/cstates.c | 5 +++++ + 2 files changed, 10 insertions(+) + +diff --git a/src/mainboard/lenovo/t400/cstates.c b/src/mainboard/lenovo/t400/cstates.c +index 827f76e..7d92d6f 100644 +--- a/src/mainboard/lenovo/t400/cstates.c ++++ b/src/mainboard/lenovo/t400/cstates.c +@@ -27,6 +27,11 @@ static acpi_cstate_t cst_entries[] = { + /* acpi C2 / cpu C2 */ + 2, 0x01, 500, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } ++ }, ++ { ++ /* acpi C3 / cpu C4 */ ++ 3, 0x02, 300, ++ { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x30, 0 } + }, + }; + +diff --git a/src/mainboard/lenovo/x200/cstates.c b/src/mainboard/lenovo/x200/cstates.c +index 827f76e..7d92d6f 100644 +--- a/src/mainboard/lenovo/x200/cstates.c ++++ b/src/mainboard/lenovo/x200/cstates.c +@@ -27,6 +27,11 @@ static acpi_cstate_t cst_entries[] = { + /* acpi C2 / cpu C2 */ + 2, 0x01, 500, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } ++ }, ++ { ++ /* acpi C3 / cpu C4 */ ++ 3, 0x02, 300, ++ { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x30, 0 } + }, + }; + +-- +2.8.2 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch new file mode 100644 index 00000000..61b36eb6 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch @@ -0,0 +1,229 @@ +From 79f4b168666e484191ed3196dffe691953ee783b Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 15 Aug 2016 00:04:34 +0200 +Subject: [PATCH] gm45/gma.c: clean up some registers +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +According to "G45: Volume 3: Display Register +Intel ® 965G Express Chipset Family and Intel ® +G35 Express Chipset Graphics Controller" some registries +are set incorrectly in gm45/gma.c. + +Some values are changed after comparing them with the values +the i915 linux kernel (3.13 was used) module sets while modesetting. +The values were obtained using 'intel_reg' from intel-gpu-tools, +during a normal boot and with 'nomodeset' as a kernel argument. + +Some registers that don't exist on gm45 are set in gma.c, which is +probably the result of copying code from a more recent intel +northbridge. + +The result is that that gm45 laptops with wxga displays still work as +before. Laptops with wxga+ displays previously did not display anything +and now have a horizontal 20% strip of working display. + +TEST: build with native graphic init and flash on a gm45 target, like +lenovo x200. + +Change-Id: If66b60c7189997c558270f9e474851fe7e2219f1 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 110 +++++++-------------------------------- + 1 file changed, 18 insertions(+), 92 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index a89f9bb..b02c89b 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -47,60 +47,6 @@ void gtt_write(u32 reg, u32 data) + write32(res2mmio(gtt_res, reg, 0), data); + } + +-static void power_port(u8 *mmio) +-{ +- read32(mmio + 0x00061100); // = 0x00000000 +- write32(mmio + 0x00061100, 0x00000000); +- write32(mmio + 0x00061100, 0x00010000); +- read32(mmio + 0x00061100); // = 0x00010000 +- read32(mmio + 0x00061100); // = 0x00010000 +- read32(mmio + 0x00061100); // = 0x00000000 +- write32(mmio + 0x00061100, 0x00000000); +- read32(mmio + 0x00061100); // = 0x00000000 +- read32(mmio + 0x00064200); // = 0x0000001c +- write32(mmio + 0x00064210, 0x8004003e); +- write32(mmio + 0x00064214, 0x80060002); +- write32(mmio + 0x00064218, 0x01000000); +- read32(mmio + 0x00064210); // = 0x5144003e +- write32(mmio + 0x00064210, 0x5344003e); +- read32(mmio + 0x00064210); // = 0x0144003e +- write32(mmio + 0x00064210, 0x8074003e); +- read32(mmio + 0x00064210); // = 0x5144003e +- read32(mmio + 0x00064210); // = 0x5144003e +- write32(mmio + 0x00064210, 0x5344003e); +- read32(mmio + 0x00064210); // = 0x0144003e +- write32(mmio + 0x00064210, 0x8074003e); +- read32(mmio + 0x00064210); // = 0x5144003e +- read32(mmio + 0x00064210); // = 0x5144003e +- write32(mmio + 0x00064210, 0x5344003e); +- read32(mmio + 0x00064210); // = 0x0144003e +- write32(mmio + 0x00064210, 0x8074003e); +- read32(mmio + 0x00064210); // = 0x5144003e +- read32(mmio + 0x00064210); // = 0x5144003e +- write32(mmio + 0x00064210, 0x5344003e); +- write32(mmio + 0x00064f00, 0x0100030c); +- write32(mmio + 0x00064f04, 0x00b8230c); +- write32(mmio + 0x00064f08, 0x06f8930c); +- write32(mmio + 0x00064f0c, 0x09f8e38e); +- write32(mmio + 0x00064f10, 0x00b8030c); +- write32(mmio + 0x00064f14, 0x0b78830c); +- write32(mmio + 0x00064f18, 0x0ff8d3cf); +- write32(mmio + 0x00064f1c, 0x01e8030c); +- write32(mmio + 0x00064f20, 0x0ff863cf); +- write32(mmio + 0x00064f24, 0x0ff803cf); +- write32(mmio + 0x000c4030, 0x00001000); +- read32(mmio + 0x00044000); // = 0x00000000 +- write32(mmio + 0x00044030, 0x00001000); +- read32(mmio + 0x00061150); // = 0x0000001c +- write32(mmio + 0x00061150, 0x0000089c); +- write32(mmio + 0x000fcc00, 0x01986f00); +- write32(mmio + 0x000fcc0c, 0x01986f00); +- write32(mmio + 0x000fcc18, 0x01986f00); +- write32(mmio + 0x000fcc24, 0x01986f00); +- read32(mmio + 0x00044000); // = 0x00000000 +- read32(mmio + LVDS); // = 0x40000002 +-} +- + static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { +@@ -150,8 +96,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + +- power_port(mmio); +- + intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128); + decode_edid(edid_data, + sizeof(edid_data), &edid); +@@ -277,28 +221,32 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + (hpolarity << 20) | (vpolarity << 21) + | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) +- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); ++ | LVDS_ENABLE_DITHER ++ | LVDS_CLOCK_A_POWERUP_ALL ++ | LVDS_PIPE(0)); + mdelay(1); + write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(mmio + FP0(0), + ((pixel_n - 2) << 16) +- | ((pixel_m1 - 2) << 8) | pixel_m2); ++ | ((pixel_m1 - 2) << 8) | (pixel_m2 - 2)); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS ++ | DPLL_VGA_MODE_DIS + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) +- | (0x1 << (pixel_p1 - 1))); ++ | (6 << 9)); + mdelay(1); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS ++ | DPLL_VGA_MODE_DIS + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | (0x10000 << (pixel_p1 - 1)) + | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13) +- | (0x1 << (pixel_p1 - 1))); ++ | (6 << 9)); + /* Re-lock the registers. */ + write32(mmio + PP_CONTROL, + (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); +@@ -307,7 +255,9 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + (hpolarity << 20) | (vpolarity << 21) + | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) +- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); ++ | LVDS_CLOCK_A_POWERUP_ALL ++ | LVDS_ENABLE_DITHER ++ | LVDS_PIPE(0)); + + write32(mmio + HTOTAL(0), + ((hactive + right_border + hblank - 1) << 16) +@@ -324,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- (vactive + bottom_border + vfront_porch + vsync - 1) ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) + | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); +@@ -335,7 +285,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + | (vactive - 1)); + write32(mmio + PF_CTL(0), 0); + write32(mmio + PF_WIN_SZ(0), 0); +- write32(mmio + PFIT_CONTROL, 0x20000000); ++ write32(mmio + PFIT_CONTROL, 0); + } else { + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); +@@ -362,7 +312,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + + if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { +- write32(mmio + VGACNTRL, 0xc4008e | VGA_DISP_DISABLE); ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE + | DISPPLANE_BGRX888); + mdelay(1); +@@ -370,37 +320,13 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + write32(mmio + VGACNTRL, 0xc4008e); + } + +- write32(mmio + TRANS_HTOTAL(0), +- ((hactive + right_border + hblank - 1) << 16) +- | (hactive - 1)); +- write32(mmio + TRANS_HBLANK(0), +- ((hactive + right_border + hblank - 1) << 16) +- | (hactive + right_border - 1)); +- write32(mmio + TRANS_HSYNC(0), +- ((hactive + right_border + hfront_porch + hsync - 1) << 16) +- | (hactive + right_border + hfront_porch - 1)); +- +- write32(mmio + TRANS_VTOTAL(0), +- ((vactive + bottom_border + vblank - 1) << 16) +- | (vactive - 1)); +- write32(mmio + TRANS_VBLANK(0), +- ((vactive + bottom_border + vblank - 1) << 16) +- | (vactive + bottom_border - 1)); +- write32(mmio + TRANS_VSYNC(0), +- (vactive + bottom_border + vfront_porch + vsync - 1) +- | (vactive + bottom_border + vfront_porch - 1)); +- +- write32(mmio + 0x00060100, 0xb01c4000); +- write32(mmio + 0x000f000c, 0xb01a2050); +- mdelay(1); +- write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC +- ); +- write32(mmio + LVDS, +- LVDS_PORT_ENABLE ++ write32(mmio + LVDS, LVDS_PORT_ENABLE + | (hpolarity << 20) | (vpolarity << 21) + | (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL + | LVDS_CLOCK_BOTH_POWERUP_ALL : 0) +- | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); ++ | LVDS_CLOCK_A_POWERUP_ALL ++ | LVDS_ENABLE_DITHER ++ | LVDS_PIPE(0)); + + write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch new file mode 100644 index 00000000..d89e4884 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch @@ -0,0 +1,50 @@ +From 0821d0290e7e17e375ffdb48a86b56504db4f77e Mon Sep 17 00:00:00 2001 +From: Damien Zammit <damien@zamaudio.com> +Date: Sat, 27 Aug 2016 00:35:48 +1000 +Subject: [PATCH] nb/intel/gm45: Fix IOMMU + +Previously the ME was being reported as present in ACPI +even when it's firmware was missing. Now we do a check via the pci device +(HECI) to verify if the ME is there or not. + +Note that this test could fail if ME is present but disabled in devicetree, +but in that case you won't see it in the lspci tree anyway so it shouldn't +be an issue. + +Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0 +Signed-off-by: Damien Zammit <damien@zamaudio.com> +--- + src/northbridge/intel/gm45/acpi.c | 3 ++- + src/northbridge/intel/gm45/iommu.c | 2 ++ + 2 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c +index 8990c3b..b90afca 100644 +--- a/src/northbridge/intel/gm45/acpi.c ++++ b/src/northbridge/intel/gm45/acpi.c +@@ -72,7 +72,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) + + static unsigned long acpi_fill_dmar(unsigned long current) + { +- int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL); ++ int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL) && ++ (pci_read_config8(dev_find_slot(0, PCI_DEVFN(3, 0)), PCI_CLASS_REVISION) != 0xff); + int stepping = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_CLASS_REVISION); + + unsigned long tmp = current; +diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c +index 10548f4..0c3c18e 100644 +--- a/src/northbridge/intel/gm45/iommu.c ++++ b/src/northbridge/intel/gm45/iommu.c +@@ -40,6 +40,8 @@ void init_iommu() + } + if (me_active) { + MCHBAR32(0x10) = IOMMU_BASE3 | 1; /* ME @ 0:3.0-3 */ ++ } else { ++ MCHBAR32(0x10) = 0; /* disable IOMMU for ME */ + } + MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */ + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch new file mode 100644 index 00000000..01124c34 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch @@ -0,0 +1,38 @@ +From c98d8745d4dca650709e76269cf014e5ffbc1443 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Tue, 9 Aug 2016 00:54:37 +0200 +Subject: [PATCH] set default vram to 256M + +Change-Id: Ife906c47f32493d9a647a4f12f25982623eba189 +--- + src/mainboard/lenovo/t400/cmos.default | 2 +- + src/mainboard/lenovo/x200/cmos.default | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default +index 5cf3e63..90d796f 100644 +--- a/src/mainboard/lenovo/t400/cmos.default ++++ b/src/mainboard/lenovo/t400/cmos.default +@@ -14,4 +14,4 @@ power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI + hybrid_graphics_mode=Integrated Only +-gfx_uma_size=32M +\ No newline at end of file ++gfx_uma_size=256M +\ No newline at end of file +diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default +index 1d7b420..ec7ab46 100644 +--- a/src/mainboard/lenovo/x200/cmos.default ++++ b/src/mainboard/lenovo/x200/cmos.default +@@ -13,4 +13,4 @@ sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI +-gfx_uma_size=32M +\ No newline at end of file ++gfx_uma_size=256M +\ No newline at end of file +-- +2.9.2 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch new file mode 100644 index 00000000..26632b7d --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch @@ -0,0 +1,212 @@ +From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 22 Aug 2016 17:58:46 +0200 +Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected + +The intel x4x and gm45 have very similar integrated graphic devices. +Currently the x4x native graphic init enables VGA, while gm45 can output +on LVDS. + +This patch reuses the x4x graphic initialisation code +to enable output on VGA in gm45 in a way that the behavior is similar to vbios: +If no VGA display is connected the internal LVDS screen is used. +If an external screen is detected on the VGA port it will be used instead. + +Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- + 1 file changed, 153 insertions(+), 4 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..74c9bc3 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) + write32(res2mmio(gtt_res, reg, 0), data); + } + +-static void intel_gma_init(const struct northbridge_intel_gm45_config *info, ++static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + +@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + sizeof(edid_data), &edid); + mode = &edid.mode; + +- /* Disable screen memory to prevent garbage from appearing. */ ++ /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = edid.x_resolution; +@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, + } + } + ++static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ++ u8 *mmio) ++{ ++ ++ int i; ++ u32 hactive, vactive; ++ ++ vga_gr_write(0x18, 0); ++ ++ write32(mmio + VGA0, 0x31108); ++ write32(mmio + VGA1, 0x31406); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + 0x7041c, 0x0); ++ write32(mmio + DPLL_MD(0), 0x3); ++ write32(mmio + DPLL_MD(1), 0x3); ++ ++ vga_misc_write(0x67); ++ ++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, ++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, ++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, ++ 0xff ++ }; ++ vga_cr_write(0x11, 0); ++ ++ for (i = 0; i <= 0x18; i++) ++ vga_cr_write(i, cr[i]); ++ ++ /* Disable screen memory to prevent garbage from appearing. */ ++ vga_sr_write(1, vga_sr_read(1) | 0x20); ++ ++ hactive = 640; ++ vactive = 400; ++ ++ mdelay(1); ++ write32(mmio + FP0(0), 0x31108); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ mdelay(1); ++ write32(mmio + DPLL(0), ++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL ++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 ++ | 0x10601 ++ ); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ write32(mmio + HTOTAL(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HBLANK(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ write32(mmio + HSYNC(0), ++ ((hactive - 1) << 16) ++ | (hactive - 1)); ++ ++ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + VSYNC(0), ++ ((vactive - 1) << 16) ++ | (vactive - 1)); ++ ++ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); ++ ++ write32(mmio + PF_WIN_POS(0), 0); ++ ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0xa0000000); ++ ++ mdelay(1); ++ ++ write32(mmio + 0x000f000c, 0x00002040); ++ mdelay(1); ++ write32(mmio + 0x000f000c, 0x00002050); ++ write32(mmio + 0x00060100, 0x00044000); ++ mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_ENABLE ++ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); ++ ++ write32(mmio + VGACNTRL, 0x0); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); ++ mdelay(1); ++ ++ write32(mmio + ADPA, ADPA_DAC_ENABLE ++ | ADPA_PIPE_A_SELECT ++ | ADPA_CRT_HOTPLUG_MONITOR_COLOR ++ | ADPA_CRT_HOTPLUG_ENABLE ++ | ADPA_USE_VGA_HVPOLARITY ++ | ADPA_VSYNC_CNTL_ENABLE ++ | ADPA_HSYNC_CNTL_ENABLE ++ | ADPA_DPMS_ON ++ ); ++ ++ vga_textmode_init(); ++ ++ /* Enable screen memory. */ ++ vga_sr_write(1, vga_sr_read(1) & ~0x20); ++ ++ /* Clear interrupts. */ ++ write32(mmio + DEIIR, 0xffffffff); ++ write32(mmio + SDEIIR, 0xffffffff); ++} ++ ++/* compare the header of the vga edid header */ ++/* if vga is not connected it should not have a correct header */ ++static u8 vga_connected(u8 *mmio) ++{ ++ u8 vga_edid[128]; ++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ for (int i = 0; i < 8; i++) { ++ if (vga_edid[i] != header[i]) { ++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); ++ return 0; ++ } ++ } ++ printk(BIOS_SPEW, "VGA display connected\n"); ++ return 1; ++} ++ + static void gma_pm_init_post_vbios(struct device *const dev) + { + const struct northbridge_intel_gm45_config *const conf = dev->chip_info; +@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); +- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, +- pio_res->base, lfb_res->base); ++ if (vga_connected(res2mmio(gtt_res, 0, 0))) ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ else ++ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch new file mode 100644 index 00000000..ef42f3e8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch @@ -0,0 +1,379 @@ +From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sat, 27 Aug 2016 01:09:19 +0200 +Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output + +This implements "Keep VESA framebuffer" behavior on VGA output of gm45. +This patch reuses Linux code to compute vga divisors. + +Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- + 1 file changed, 209 insertions(+), 42 deletions(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index 74c9bc3..efaa210 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -25,6 +25,7 @@ + #include <cpu/x86/msr.h> + #include <cpu/x86/mtrr.h> + #include <kconfig.h> ++#include <commonlib/helpers.h> + + #include "drivers/intel/gma/i915_reg.h" + #include "chip.h" +@@ -35,6 +36,8 @@ + #include <pc80/vga.h> + #include <pc80/vga_io.h> + ++#define BASE_FREQUECY 96000 ++ + static struct resource *gtt_res = NULL; + + u32 gtt_read(u32 reg) +@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, + } + + static void gma_init_vga(const struct northbridge_intel_gm45_config *info, +- u8 *mmio) ++ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + { + + int i; +- u32 hactive, vactive; ++ u8 edid_data[128]; ++ struct edid edid; ++ struct edid_mode *mode; ++ u32 hactive, vactive, right_border, bottom_border; ++ int hpolarity, vpolarity; ++ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; ++ u32 target_frequency; ++ u32 smallest_err = 0xffffffff; ++ u32 pixel_p1 = 1; ++ u32 pixel_n = 1; ++ u32 pixel_m1 = 1; ++ u32 pixel_m2 = 1; ++ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; ++ u32 data_m1; ++ u32 data_n1 = 0x00800000; ++ u32 link_m1; ++ u32 link_n1 = 0x00040000; ++ + + vga_gr_write(0x18, 0); + ++ /* Setup GTT. */ ++ for (i = 0; i < 0x2000; i++) { ++ outl((i << 2) | 1, piobase); ++ outl(physbase + (i << 12) + 1, piobase + 4); ++ } ++ ++ + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + +@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE +- | ADPA_DPMS_ON +- ); ++ | ADPA_DPMS_ON); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); +@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + ++ udelay(1); ++ ++ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); ++ intel_gmbus_stop(mmio + GMBUS0); ++ decode_edid(edid_data, ++ sizeof(edid_data), &edid); ++ mode = &edid.mode; ++ ++ + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + +- hactive = 640; +- vactive = 400; ++ hactive = edid.x_resolution; ++ vactive = edid.y_resolution; ++ right_border = mode->hborder; ++ bottom_border = mode->vborder; ++ hpolarity = (mode->phsync == '-'); ++ vpolarity = (mode->pvsync == '-'); ++ vsync = mode->vspw; ++ hsync = mode->hspw; ++ vblank = mode->vbl; ++ hblank = mode->hbl; ++ hfront_porch = mode->hso; ++ vfront_porch = mode->vso; ++ target_frequency = mode->pixel_clock; ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ vga_sr_write(1, 1); ++ vga_sr_write(0x2, 0xf); ++ vga_sr_write(0x3, 0x0); ++ vga_sr_write(0x4, 0xe); ++ vga_gr_write(0, 0x0); ++ vga_gr_write(1, 0x0); ++ vga_gr_write(2, 0x0); ++ vga_gr_write(3, 0x0); ++ vga_gr_write(4, 0x0); ++ vga_gr_write(5, 0x0); ++ vga_gr_write(6, 0x5); ++ vga_gr_write(7, 0xf); ++ vga_gr_write(0x10, 0x1); ++ vga_gr_write(0x11, 0); ++ ++ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; ++ ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ write32(mmio + DSPADDR(0), 0); ++ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); ++ write32(mmio + DSPSURF(0), 0); ++ for (i = 0; i < 0x100; i++) ++ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); ++ } else { ++ vga_textmode_init(); ++ } ++ ++ u32 candn, candm1, candm2, candp1; ++ for (candn = 1; candn <= 4; candn++) { ++ for (candm1 = 23; candm1 >= 17; candm1--) { ++ for (candm2 = 11; candm2 >= 5; candm2--) { ++ for (candp1 = 8; candp1 >= 1; candp1--) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * 10; /* 10 == p2 */ ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if (this_err < smallest_err) { ++ smallest_err= this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } ++ } ++ } ++ } ++ ++ if (smallest_err == 0xffffffff) { ++ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); ++ return; ++ } ++ ++ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; ++ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) ++ / (link_frequency * 8 * 4); ++ ++ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", ++ hactive, vactive); ++ printk(BIOS_DEBUG, "Borders %d x %d\n", ++ right_border, bottom_border); ++ printk(BIOS_DEBUG, "Blank %d x %d\n", ++ hblank, vblank); ++ printk(BIOS_DEBUG, "Sync %d x %d\n", ++ hsync, vsync); ++ printk(BIOS_DEBUG, "Front porch %d x %d\n", ++ hfront_porch, vfront_porch); ++ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock ++ ? "Spread spectrum clock\n" : "DREF clock\n")); ++ printk(BIOS_DEBUG, "Polarities %d, %d\n", ++ hpolarity, vpolarity); ++ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", ++ data_m1, data_n1); ++ printk(BIOS_DEBUG, "Link frequency %d kHz\n", ++ link_frequency); ++ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", ++ link_m1, link_n1); ++ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", ++ pixel_n, pixel_m1, pixel_m2, pixel_p1); ++ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", ++ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) ++ / (pixel_p1 * 10))); + + mdelay(1); +- write32(mmio + FP0(0), 0x31108); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + FP0(0), (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); ++ + mdelay(1); +- write32(mmio + DPLL(0), +- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL +- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 +- | 0x10601 +- ); ++ write32(mmio + DPLL(0), DPLL_VCO_ENABLE ++ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL ++ | (0x10000 << (pixel_p1 - 1)) ++ | (6 << 9)); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + + write32(mmio + HTOTAL(0), +- ((hactive - 1) << 16) ++ ((hactive + right_border + hblank - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hblank - 1) << 16) ++ | (hactive + right_border - 1)); + write32(mmio + HSYNC(0), +- ((hactive - 1) << 16) +- | (hactive - 1)); ++ ((hactive + right_border + hfront_porch + hsync - 1) << 16) ++ | (hactive + right_border + hfront_porch - 1)); + +- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) +- | (vactive - 1)); +- write32(mmio + VBLANK(0), ((vactive - 1) << 16) ++ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) + | (vactive - 1)); ++ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) ++ | (vactive + bottom_border - 1)); + write32(mmio + VSYNC(0), +- ((vactive - 1) << 16) +- | (vactive - 1)); ++ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) ++ | (vactive + bottom_border + vfront_porch - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); +- +- write32(mmio + PIPESRC(0), (639 << 16) | 399); +- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); +- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +- write32(mmio + PFIT_CONTROL, 0xa0000000); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) ++ | (vactive - 1)); ++ write32(mmio + PF_CTL(0), 0); ++ write32(mmio + PF_WIN_SZ(0), 0); ++ write32(mmio + PFIT_CONTROL, 0); ++ } else { ++ write32(mmio + PIPESRC(0), (639 << 16) | 399); ++ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); ++ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); ++ write32(mmio + PFIT_CONTROL, 0x80000000); ++ } + + mdelay(1); + ++ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); ++ write32(mmio + PIPE_DATA_N1(0), data_n1); ++ write32(mmio + PIPE_LINK_M1(0), link_m1); ++ write32(mmio + PIPE_LINK_N1(0), link_n1); ++ + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); ++ write32(mmio + 0x000f0008, 0x00000040); ++ write32(mmio + 0x000f000c, 0x00022050); ++ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + +- write32(mmio + VGACNTRL, 0x0); +- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); +- mdelay(1); ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); ++ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE ++ | DISPPLANE_BGRX888); ++ mdelay(1); ++ } else { ++ write32(mmio + VGACNTRL, 0xc4008e); ++ } + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE +- | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON +- ); ++ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : ++ ADPA_VSYNC_ACTIVE_HIGH) ++ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : ++ ADPA_HSYNC_ACTIVE_HIGH)); + +- vga_textmode_init(); ++ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); + +- /* Enable screen memory. */ ++ /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); ++ ++ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { ++ memset((void *) lfb, 0, ++ edid.x_resolution * edid.y_resolution * 4); ++ set_vbe_mode_info_valid(&edid, lfb); ++ } ++ ++ + } + + /* compare the header of the vga edid header */ +@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) + u8 vga_edid[128]; + u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; + intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); ++ intel_gmbus_stop(mmio + GMBUS0); + for (int i = 0; i < 8; i++) { + if (vga_edid[i] != header[i]) { + printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); +@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + if (vga_connected(res2mmio(gtt_res, 0, 0))) +- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); ++ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), ++ physbase, pio_res->base, lfb_res->base); + else + gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), + physbase, pio_res->base, lfb_res->base); +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch new file mode 100644 index 00000000..fb30c4c2 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch @@ -0,0 +1,31 @@ +From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 8 Sep 2016 22:21:54 +0200 +Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT + +The correct id string for gm45 is "$VBT CANTIGA ". +This can be found in the gm45 option rom: +"strings vbios.bin | grep VBT". + +Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/gm45/gma.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c +index d5f6471..19bd944 100644 +--- a/src/northbridge/intel/gm45/gma.c ++++ b/src/northbridge/intel/gm45/gma.c +@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, +- "$VBT IRONLAKE-MOBILE"); ++ "$VBT CANTIGA "); + } + } + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/INFO b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/INFO new file mode 100644 index 00000000..220b8583 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/INFO @@ -0,0 +1,5 @@ +# NOTE: remove this when updating to the latest version of coreboot. this patch +# makes the patch below redundant: https://review.coreboot.org/#/c/12814/ +printf "northbridge/gm45/raminit.c: enable GS45 high-perf (i.e. add X200S support to libreboot)\n" +git am "../resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/35/11135/3 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch new file mode 100644 index 00000000..2fde12f4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch @@ -0,0 +1,89 @@ +From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Tue, 8 Mar 2016 07:21:33 +0000 +Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates + +There were build issues in libreboot. We don't use microcode updates anyway. +When selecting no microcode updates in menuconfig, build failed because +coreboot for these boards was still trying to add microcode. +--- + src/cpu/Makefile.inc | 34 +------------------------- + src/cpu/amd/family_10h-family_15h/Kconfig | 1 - + src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- + 3 files changed, 1 insertion(+), 44 deletions(-) + +diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc +index 046c418..ef0e236 100644 +--- a/src/cpu/Makefile.inc ++++ b/src/cpu/Makefile.inc +@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) + ## Rules for building the microcode blob in CBFS + ################################################################################ + +-ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) +-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin +-endif +- +-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) +-cbfs-files-y += cpu_microcode_blob.bin +-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin +- +-$(objgenerated)/microcode.bin: +- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" +- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) +-endif +- +-# We just mash all microcode binaries together into one binary to rule them all. +-# This approach assumes that the microcode binaries are properly padded, and +-# their headers specify the correct size. This works fairly well on isolatied +-# updates, such as Intel and some AMD microcode, but won't work very well if the +-# updates are wrapped in a container, like AMD's microcode update container. If +-# there is only one microcode binary (i.e. one container), then we don't have +-# this issue, and this rule will continue to work. +-$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) +- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" +- @echo $(cpu_microcode_bins) +- cat /dev/null $+ > $@ +- +-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin +-cpu_microcode_blob.bin-type := microcode +- +-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +-cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) +-else +-cpu_microcode_blob.bin-align := 16 +-endif ++# What? Nope! We don't do that in libreboot. +diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig +index 14ab1cd..3f873a1 100644 +--- a/src/cpu/amd/family_10h-family_15h/Kconfig ++++ b/src/cpu/amd/family_10h-family_15h/Kconfig +@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX + select UDELAY_LAPIC + select HAVE_MONOTONIC_TIMER + select SUPPORT_CPU_UCODE_IN_CBFS +- select CPU_MICROCODE_MULTIPLE_FILES + + if CPU_AMD_MODEL_10XXX + +diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc +index f10f732..a295475 100644 +--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc ++++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc +@@ -9,13 +9,3 @@ romstage-y += ram_calc.c + ramstage-y += ram_calc.c + ramstage-y += monotonic_timer.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c +- +-# Microcode for Family 10h, 11h, 12h, and 14h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin +-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin +-microcode_amd.bin-type := microcode +- +-# Microcode for Family 15h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-type := microcode +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch new file mode 100644 index 00000000..2fde12f4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch @@ -0,0 +1,89 @@ +From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Tue, 8 Mar 2016 07:21:33 +0000 +Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates + +There were build issues in libreboot. We don't use microcode updates anyway. +When selecting no microcode updates in menuconfig, build failed because +coreboot for these boards was still trying to add microcode. +--- + src/cpu/Makefile.inc | 34 +------------------------- + src/cpu/amd/family_10h-family_15h/Kconfig | 1 - + src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- + 3 files changed, 1 insertion(+), 44 deletions(-) + +diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc +index 046c418..ef0e236 100644 +--- a/src/cpu/Makefile.inc ++++ b/src/cpu/Makefile.inc +@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) + ## Rules for building the microcode blob in CBFS + ################################################################################ + +-ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) +-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin +-endif +- +-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) +-cbfs-files-y += cpu_microcode_blob.bin +-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin +- +-$(objgenerated)/microcode.bin: +- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" +- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) +-endif +- +-# We just mash all microcode binaries together into one binary to rule them all. +-# This approach assumes that the microcode binaries are properly padded, and +-# their headers specify the correct size. This works fairly well on isolatied +-# updates, such as Intel and some AMD microcode, but won't work very well if the +-# updates are wrapped in a container, like AMD's microcode update container. If +-# there is only one microcode binary (i.e. one container), then we don't have +-# this issue, and this rule will continue to work. +-$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) +- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" +- @echo $(cpu_microcode_bins) +- cat /dev/null $+ > $@ +- +-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin +-cpu_microcode_blob.bin-type := microcode +- +-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +-cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) +-else +-cpu_microcode_blob.bin-align := 16 +-endif ++# What? Nope! We don't do that in libreboot. +diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig +index 14ab1cd..3f873a1 100644 +--- a/src/cpu/amd/family_10h-family_15h/Kconfig ++++ b/src/cpu/amd/family_10h-family_15h/Kconfig +@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX + select UDELAY_LAPIC + select HAVE_MONOTONIC_TIMER + select SUPPORT_CPU_UCODE_IN_CBFS +- select CPU_MICROCODE_MULTIPLE_FILES + + if CPU_AMD_MODEL_10XXX + +diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc +index f10f732..a295475 100644 +--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc ++++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc +@@ -9,13 +9,3 @@ romstage-y += ram_calc.c + ramstage-y += ram_calc.c + ramstage-y += monotonic_timer.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c +- +-# Microcode for Family 10h, 11h, 12h, and 14h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin +-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin +-microcode_amd.bin-type := microcode +- +-# Microcode for Family 15h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-type := microcode +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch new file mode 100644 index 00000000..2fde12f4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch @@ -0,0 +1,89 @@ +From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Tue, 8 Mar 2016 07:21:33 +0000 +Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates + +There were build issues in libreboot. We don't use microcode updates anyway. +When selecting no microcode updates in menuconfig, build failed because +coreboot for these boards was still trying to add microcode. +--- + src/cpu/Makefile.inc | 34 +------------------------- + src/cpu/amd/family_10h-family_15h/Kconfig | 1 - + src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- + 3 files changed, 1 insertion(+), 44 deletions(-) + +diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc +index 046c418..ef0e236 100644 +--- a/src/cpu/Makefile.inc ++++ b/src/cpu/Makefile.inc +@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) + ## Rules for building the microcode blob in CBFS + ################################################################################ + +-ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) +-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin +-endif +- +-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) +-cbfs-files-y += cpu_microcode_blob.bin +-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin +- +-$(objgenerated)/microcode.bin: +- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" +- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) +-endif +- +-# We just mash all microcode binaries together into one binary to rule them all. +-# This approach assumes that the microcode binaries are properly padded, and +-# their headers specify the correct size. This works fairly well on isolatied +-# updates, such as Intel and some AMD microcode, but won't work very well if the +-# updates are wrapped in a container, like AMD's microcode update container. If +-# there is only one microcode binary (i.e. one container), then we don't have +-# this issue, and this rule will continue to work. +-$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) +- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" +- @echo $(cpu_microcode_bins) +- cat /dev/null $+ > $@ +- +-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin +-cpu_microcode_blob.bin-type := microcode +- +-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +-cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) +-else +-cpu_microcode_blob.bin-align := 16 +-endif ++# What? Nope! We don't do that in libreboot. +diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig +index 14ab1cd..3f873a1 100644 +--- a/src/cpu/amd/family_10h-family_15h/Kconfig ++++ b/src/cpu/amd/family_10h-family_15h/Kconfig +@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX + select UDELAY_LAPIC + select HAVE_MONOTONIC_TIMER + select SUPPORT_CPU_UCODE_IN_CBFS +- select CPU_MICROCODE_MULTIPLE_FILES + + if CPU_AMD_MODEL_10XXX + +diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc +index f10f732..a295475 100644 +--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc ++++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc +@@ -9,13 +9,3 @@ romstage-y += ram_calc.c + ramstage-y += ram_calc.c + ramstage-y += monotonic_timer.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c +- +-# Microcode for Family 10h, 11h, 12h, and 14h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin +-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin +-microcode_amd.bin-type := microcode +- +-# Microcode for Family 15h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-type := microcode +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch new file mode 100644 index 00000000..2fde12f4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch @@ -0,0 +1,89 @@ +From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Tue, 8 Mar 2016 07:21:33 +0000 +Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates + +There were build issues in libreboot. We don't use microcode updates anyway. +When selecting no microcode updates in menuconfig, build failed because +coreboot for these boards was still trying to add microcode. +--- + src/cpu/Makefile.inc | 34 +------------------------- + src/cpu/amd/family_10h-family_15h/Kconfig | 1 - + src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- + 3 files changed, 1 insertion(+), 44 deletions(-) + +diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc +index 046c418..ef0e236 100644 +--- a/src/cpu/Makefile.inc ++++ b/src/cpu/Makefile.inc +@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) + ## Rules for building the microcode blob in CBFS + ################################################################################ + +-ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) +-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin +-endif +- +-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) +-cbfs-files-y += cpu_microcode_blob.bin +-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin +- +-$(objgenerated)/microcode.bin: +- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" +- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) +-endif +- +-# We just mash all microcode binaries together into one binary to rule them all. +-# This approach assumes that the microcode binaries are properly padded, and +-# their headers specify the correct size. This works fairly well on isolatied +-# updates, such as Intel and some AMD microcode, but won't work very well if the +-# updates are wrapped in a container, like AMD's microcode update container. If +-# there is only one microcode binary (i.e. one container), then we don't have +-# this issue, and this rule will continue to work. +-$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) +- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" +- @echo $(cpu_microcode_bins) +- cat /dev/null $+ > $@ +- +-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin +-cpu_microcode_blob.bin-type := microcode +- +-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +-cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) +-else +-cpu_microcode_blob.bin-align := 16 +-endif ++# What? Nope! We don't do that in libreboot. +diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig +index 14ab1cd..3f873a1 100644 +--- a/src/cpu/amd/family_10h-family_15h/Kconfig ++++ b/src/cpu/amd/family_10h-family_15h/Kconfig +@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX + select UDELAY_LAPIC + select HAVE_MONOTONIC_TIMER + select SUPPORT_CPU_UCODE_IN_CBFS +- select CPU_MICROCODE_MULTIPLE_FILES + + if CPU_AMD_MODEL_10XXX + +diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc +index f10f732..a295475 100644 +--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc ++++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc +@@ -9,13 +9,3 @@ romstage-y += ram_calc.c + ramstage-y += ram_calc.c + ramstage-y += monotonic_timer.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c +- +-# Microcode for Family 10h, 11h, 12h, and 14h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin +-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin +-microcode_amd.bin-type := microcode +- +-# Microcode for Family 15h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-type := microcode +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch new file mode 100644 index 00000000..2fde12f4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch @@ -0,0 +1,89 @@ +From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Tue, 8 Mar 2016 07:21:33 +0000 +Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates + +There were build issues in libreboot. We don't use microcode updates anyway. +When selecting no microcode updates in menuconfig, build failed because +coreboot for these boards was still trying to add microcode. +--- + src/cpu/Makefile.inc | 34 +------------------------- + src/cpu/amd/family_10h-family_15h/Kconfig | 1 - + src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- + 3 files changed, 1 insertion(+), 44 deletions(-) + +diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc +index 046c418..ef0e236 100644 +--- a/src/cpu/Makefile.inc ++++ b/src/cpu/Makefile.inc +@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) + ## Rules for building the microcode blob in CBFS + ################################################################################ + +-ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) +-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin +-endif +- +-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) +-cbfs-files-y += cpu_microcode_blob.bin +-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin +- +-$(objgenerated)/microcode.bin: +- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" +- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) +-endif +- +-# We just mash all microcode binaries together into one binary to rule them all. +-# This approach assumes that the microcode binaries are properly padded, and +-# their headers specify the correct size. This works fairly well on isolatied +-# updates, such as Intel and some AMD microcode, but won't work very well if the +-# updates are wrapped in a container, like AMD's microcode update container. If +-# there is only one microcode binary (i.e. one container), then we don't have +-# this issue, and this rule will continue to work. +-$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) +- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" +- @echo $(cpu_microcode_bins) +- cat /dev/null $+ > $@ +- +-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin +-cpu_microcode_blob.bin-type := microcode +- +-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) +-cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) +-else +-cpu_microcode_blob.bin-align := 16 +-endif ++# What? Nope! We don't do that in libreboot. +diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig +index 14ab1cd..3f873a1 100644 +--- a/src/cpu/amd/family_10h-family_15h/Kconfig ++++ b/src/cpu/amd/family_10h-family_15h/Kconfig +@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX + select UDELAY_LAPIC + select HAVE_MONOTONIC_TIMER + select SUPPORT_CPU_UCODE_IN_CBFS +- select CPU_MICROCODE_MULTIPLE_FILES + + if CPU_AMD_MODEL_10XXX + +diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc +index f10f732..a295475 100644 +--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc ++++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc +@@ -9,13 +9,3 @@ romstage-y += ram_calc.c + ramstage-y += ram_calc.c + ramstage-y += monotonic_timer.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c +- +-# Microcode for Family 10h, 11h, 12h, and 14h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin +-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin +-microcode_amd.bin-type := microcode +- +-# Microcode for Family 15h +-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin +-microcode_amd_fam15h.bin-type := microcode +-- +1.9.1 + diff --git a/resources/libreboot/patch/crossgcc/gccfix.diff b/resources/libreboot/patch/crossgcc/gccfix.diff new file mode 100644 index 00000000..49e6227b --- /dev/null +++ b/resources/libreboot/patch/crossgcc/gccfix.diff @@ -0,0 +1,27 @@ +From ea0c2d76c4f16eccaafcb2c0741f76825505bafc Mon Sep 17 00:00:00 2001 +From: Nico Huber <nico.huber@secunet.com> +Date: Thu, 22 Dec 2016 16:05:54 +0100 +Subject: [PATCH] DONOTMERGE buildgcc: Build GMP `--with-pic` if GCC defaults to `-pie` + +Change-Id: I5f3185af9c8d599379a628e18724b217b88be974 +Signed-off-by: Nico Huber <nico.huber@secunet.com> +--- + +diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc +index 97c38b8..4eefd43 100755 +--- a/util/crossgcc/buildgcc ++++ b/util/crossgcc/buildgcc +@@ -515,6 +515,13 @@ + } + + build_GMP() { ++ # Check if GCC enables `-pie` by default (likely on Debian Stretch). ++ # We have to use `--with-pic` then. ++ if "${CC}" -dumpspecs 2>/dev/null | grep -q '[{;][[:space:]]*:-pie\>' ++ then ++ OPTIONS="$OPTIONS --with-pic" ++ fi ++ + CC="$CC" ../${GMP_DIR}/configure --disable-shared --enable-fat \ + --prefix=$TARGETDIR $OPTIONS \ + || touch .failed |