diff options
Diffstat (limited to 'resources')
86 files changed, 1694 insertions, 8113 deletions
diff --git a/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision b/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision index 4f7158f6..e785a260 100644 --- a/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision +++ b/resources/libreboot/config/grub/ga-g41m-es2l/cbrevision @@ -1 +1 @@ -55a54f662e2e793306dc7003afbcb82b49db0a8c +7c2e5396a3d47c64eb5a553fe412aad4c0f8dc1b diff --git a/resources/libreboot/config/grub/ga-g41m-es2l/config b/resources/libreboot/config/grub/ga-g41m-es2l/config index ec4790da..a0c7fc0c 100644 --- a/resources/libreboot/config/grub/ga-g41m-es2l/config +++ b/resources/libreboot/config/grub/ga-g41m-es2l/config @@ -139,7 +139,6 @@ CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y # CONFIG_BOARD_GIGABYTE_MA785GMT is not set # CONFIG_BOARD_GIGABYTE_MA78GM is not set # CONFIG_DRIVERS_PS2_KEYBOARD is not set -CONFIG_DEVICETREE="devicetree.cb" # CONFIG_CONSOLE_POST is not set CONFIG_DRIVERS_UART_8250IO=y CONFIG_CPU_ADDR_BITS=36 diff --git a/resources/libreboot/config/grub/w500_16mb/architecture b/resources/libreboot/config/grub/w500_16mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/w500_16mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/w500_16mb/cbrevision b/resources/libreboot/config/grub/w500_16mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/w500_16mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/w500_16mb/config b/resources/libreboot/config/grub/w500_16mb/config new file mode 100644 index 00000000..1abc3d16 --- /dev/null +++ b/resources/libreboot/config/grub/w500_16mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W500" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0xFFD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +CONFIG_BOARD_LENOVO_T500=y +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +CONFIG_COREBOOT_ROMSIZE_KB_16384=y +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=16384 +CONFIG_ROM_SIZE=0x1000000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/w500_16mb/vbootrevision b/resources/libreboot/config/grub/w500_16mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/w500_16mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/w500_4mb/architecture b/resources/libreboot/config/grub/w500_4mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/w500_4mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/w500_4mb/cbrevision b/resources/libreboot/config/grub/w500_4mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/w500_4mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/w500_4mb/config b/resources/libreboot/config/grub/w500_4mb/config new file mode 100644 index 00000000..e4ddb2a4 --- /dev/null +++ b/resources/libreboot/config/grub/w500_4mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W500" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x3FD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +CONFIG_BOARD_LENOVO_T500=y +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/w500_4mb/vbootrevision b/resources/libreboot/config/grub/w500_4mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/w500_4mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/config/grub/w500_8mb/architecture b/resources/libreboot/config/grub/w500_8mb/architecture new file mode 100644 index 00000000..5a9a476a --- /dev/null +++ b/resources/libreboot/config/grub/w500_8mb/architecture @@ -0,0 +1 @@ +i386 diff --git a/resources/libreboot/config/grub/w500_8mb/cbrevision b/resources/libreboot/config/grub/w500_8mb/cbrevision new file mode 100644 index 00000000..d4e47be8 --- /dev/null +++ b/resources/libreboot/config/grub/w500_8mb/cbrevision @@ -0,0 +1 @@ +d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4 diff --git a/resources/libreboot/config/grub/w500_8mb/config b/resources/libreboot/config/grub/w500_8mb/config new file mode 100644 index 00000000..bd4c48fe --- /dev/null +++ b/resources/libreboot/config/grub/w500_8mb/config @@ -0,0 +1,550 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +# CONFIG_MULTIPLE_CBFS_INSTANCES is not set +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_SCONFIG_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +CONFIG_STATIC_OPTION_TABLE=y +# CONFIG_UNCOMPRESSED_RAMSTAGE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +# CONFIG_NO_XIP_EARLY_STAGES is not set +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +# CONFIG_RELOCATABLE_RAMSTAGE is not set +# CONFIG_NO_STAGE_CACHE is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_GENERIC_GPIO_LIB is not set +# CONFIG_BOARD_ID_AUTO is not set +# CONFIG_BOARD_ID_MANUAL is not set +# CONFIG_RAM_CODE_SUPPORT is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/t400" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad W500" +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x7FD000 +CONFIG_VGA_BIOS_ID="8086,2a42" +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_POST_IO=y +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POST_DEVICE=y +CONFIG_USBDEBUG_HCD_INDEX=2 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_BOARD_LENOVO_G505S is not set +# CONFIG_BOARD_LENOVO_R400 is not set +# CONFIG_BOARD_LENOVO_T400 is not set +# CONFIG_BOARD_LENOVO_T420 is not set +# CONFIG_BOARD_LENOVO_T420S is not set +# CONFIG_BOARD_LENOVO_T430S is not set +CONFIG_BOARD_LENOVO_T500=y +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +# CONFIG_BOARD_LENOVO_X200 is not set +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X220I is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +# CONFIG_USBDEBUG is not set +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +# CONFIG_NO_POST is not set +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_FMDFILE="" +# CONFIG_MAINBOARD_HAS_TPM2 is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +# CONFIG_SOC_BROADCOM_CYGNUS is not set +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_RAMTOP=0x200000 +CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y +CONFIG_UART_PCI_ADDR=0x0 +CONFIG_HPET_MIN_TICKS=0x80 +# CONFIG_SOC_MARVELL_ARMADA38X is not set +# CONFIG_SOC_MARVELL_BG4CD is not set +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA132 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x10000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +# CONFIG_UDELAY_LAPIC is not set +CONFIG_UDELAY_TSC=y +# CONFIG_TSC_CONSTANT_RATE is not set +# CONFIG_TSC_MONOTONIC_TIMER is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +CONFIG_SMM_LAPIC_REMAP_MITIGATION=y +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_USES_MICROCODE_HEADER_FILES is not set +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +CONFIG_VIDEO_MB=0 +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# +CONFIG_SUPERIO_NSC_PC87382=y + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_POWER8 is not set +# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set +# CONFIG_ARCH_VERSTAGE_POWER8 is not set +# CONFIG_ARCH_ROMSTAGE_POWER8 is not set +# CONFIG_ARCH_RAMSTAGE_POWER8 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +# CONFIG_ROMCC is not set +# CONFIG_LATE_CBMEM_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_POSTCAR_STAGE is not set +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_NATIVE_VGA_INIT_USE_EDID=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_CLK_PM is not set +# CONFIG_EARLY_PCI_BRIDGE is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_SOFTWARE_I2C is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_REALTEK_8168_RESET is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +# CONFIG_DRIVERS_UART is not set +CONFIG_NO_UART_ON_SUPERIO=y +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_DRIVERS_GENERIC_IOAPIC=y +CONFIG_SMBIOS_PROVIDED_BY_MOBO=y +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_RTC is not set +# CONFIG_TPM is not set +CONFIG_STACK_SIZE=0x1000 +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +# CONFIG_CONSOLE_SERIAL_115200 is not set +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HAVE_ACPI_RESUME=y +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payload.elf" +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# +# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +# CONFIG_TINT_SECONDARY_PAYLOAD is not set + +# +# Debugging +# +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +CONFIG_IASL_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_CREATE_BOARD_CHECKLIST is not set +# CONFIG_MAKE_CHECKLIST_PUBLIC is not set diff --git a/resources/libreboot/config/grub/w500_8mb/vbootrevision b/resources/libreboot/config/grub/w500_8mb/vbootrevision new file mode 100644 index 00000000..c18bc860 --- /dev/null +++ b/resources/libreboot/config/grub/w500_8mb/vbootrevision @@ -0,0 +1 @@ +d187cd3fc792f8bcefbee4587c83eafbd08441fc diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch deleted file mode 100644 index 884b2829..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Fri, 2 Sep 2016 22:35:32 +0200 -Subject: [PATCH 1/2] i945/gma.c use latest linux code to calculate divisors. - -The code to compute n, m1, m2, p1 divisors is not correct in coreboot and -on some targets hits a working mode at lower refresh rate, which is why -display is working on some targets. -This patch also fixes reference frequency. - -This patch reuses linux code to correctly compute divisors. - -The result is that some previously not working displays (Lenovo T60 with -1024x786, 1400x1050, 2048x1536) - -TESTED on T60 with 1024x786. - -Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- - 1 file changed, 38 insertions(+), 44 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..3f0b5b4 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -26,6 +26,8 @@ - #include <string.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> -+#include <commonlib/helpers.h> -+ - - #include "i945.h" - #include "chip.h" -@@ -43,7 +45,7 @@ - #define PGETBL_CTL 0x2020 - #define PGETBL_ENABLED 0x00000001 - --#define BASE_FREQUENCY 120000 -+#define BASE_FREQUENCY 100000 - - #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - -@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - u8 edid_data[128]; - unsigned long temp; - int hpolarity, vpolarity; -- u32 candp1, candn; -- u32 best_delta = 0xffffffff; -+ u32 smallest_err = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; -+ u32 pixel_p2; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; -@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - -- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock -- : (2 * mode->pixel_clock); -- -- /* Find suitable divisors. */ -- for (candp1 = 1; candp1 <= 8; candp1++) { -- for (candn = 5; candn <= 10; candn++) { -- u32 cur_frequency; -- u32 m; /* 77 - 131. */ -- u32 denom; /* 35 - 560. */ -- u32 current_delta; -- -- denom = candn * candp1 * 7; -- /* Doesnt overflow for up to -- 5000000 kHz = 5 GHz. */ -- m = (target_frequency * denom -- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; -- -- if (m < 77 || m > 131) -- continue; -- -- cur_frequency = (BASE_FREQUENCY * m) / denom; -- if (target_frequency > cur_frequency) -- current_delta = target_frequency - cur_frequency; -- else -- current_delta = cur_frequency - target_frequency; -- -- if (best_delta > current_delta) { -- best_delta = current_delta; -- pixel_n = candn; -- pixel_p1 = candp1; -- pixel_m2 = ((m + 3) % 5) + 7; -- pixel_m1 = (m - pixel_m2) / 5; -+ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; -+ target_frequency = mode->pixel_clock; -+ -+ /* Find suitable divisors, m1, m2, p1, n. */ -+ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ -+ /* should be closest to target frequency as possible */ -+ u32 candn, candm1, candm2, candp1; -+ for (candm1 = 8; candm1 <= 18; candm1++) { -+ for (candm2 = 3; candm2 <= 7; candm2++) { -+ for (candn = 1; candn <= 6; candn++) { -+ for (candp1 = 1; candp1 <= 8; candp1++) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * pixel_p2; -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if ((m < 70) || (m > 120)) -+ continue; -+ if (this_err < smallest_err) { -+ smallest_err = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } - } - } - } - -- if (best_delta == 0xffffffff) { -+ if (smallest_err == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return -1; - } -@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n -- / (pixel_p1 * 7)); -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * pixel_p2)); - - #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(pmmio + FP0(1), -- ((pixel_n - 2) << 16) -- | ((pixel_m1 - 2) << 8) | pixel_m2); -+ (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS -@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (conf->gpu_lvds_use_spread_spectrum_clock - ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV - : 0) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | -@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + HTOTAL(1), - ((hactive + right_border + hblank - 1) << 16) --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0006-i945-gma.c-add-native-VGA-init.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0006-i945-gma.c-add-native-VGA-init.patch deleted file mode 100644 index 26eed5b4..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0006-i945-gma.c-add-native-VGA-init.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 7ed0951bcf59dfd8b1893232b674455ff8f03f83 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 5 Sep 2016 22:46:11 +0200 -Subject: [PATCH 2/2] i945/gma.c: add native VGA init - -This reuses the Intel Pineview native graphic initialization -to have output on the VGA connector of i945 devices. - -The behavior is the same as with the vendor VBIOS BLOB. -It uses the external VGA display if it is connected. - -Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 196 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 194 insertions(+), 2 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 3f0b5b4..ac19d5a 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase) - return 0; - } - --static int intel_gma_init(struct northbridge_intel_i945_config *conf, -+static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, - unsigned int pphysbase, unsigned int piobase, - void *pmmio, unsigned int pgfx) - { -@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - #endif - return 0; - } -+ -+static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, -+ unsigned int pphysbase, unsigned int piobase, -+ void *pmmio, unsigned int pgfx) -+{ -+ int i; -+ u32 hactive, vactive; -+ u16 reg16; -+ u32 uma_size; -+ -+ printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", -+ (u32)pmmio, piobase, pphysbase); -+ -+ gtt_setup(pmmio); -+ -+ /* Disable VGA. */ -+ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); -+ -+ /* Disable pipes. */ -+ write32(pmmio + PIPECONF(0), 0); -+ write32(pmmio + PIPECONF(1), 0); -+ -+ write32(pmmio + INSTPM, 0x800); -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(pmmio + VGA0, 0x200074); -+ write32(pmmio + VGA1, 0x200074); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); -+ write32(pmmio + DSPCLK_GATE_D, 0); -+ write32(pmmio + FW_BLC, 0x03060106); -+ write32(pmmio + FW_BLC2, 0x00000306); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + 0x7041c, 0x0); -+ -+ write32(pmmio + DPLL_MD(0), 0x3); -+ write32(pmmio + DPLL_MD(1), 0x3); -+ write32(pmmio + DSPCNTR(1), 0x1000000); -+ write32(pmmio + PIPESRC(1), 0x027f01df); -+ -+ vga_misc_write(0x67); -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ // Disable screen memory to prevent garbage from appearing. -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(pmmio + PF_WIN_POS(0), 0); -+ -+ write32(pmmio + PIPESRC(0), (639 << 16) | 399); -+ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(pmmio + PFIT_CONTROL, 0x0); -+ -+ mdelay(1); -+ -+ write32(pmmio + FDI_RX_CTL(0), 0x00002040); -+ mdelay(1); -+ write32(pmmio + FDI_RX_CTL(0), 0x80002050); -+ write32(pmmio + FDI_TX_CTL(0), 0x00044000); -+ mdelay(1); -+ write32(pmmio + FDI_TX_CTL(0), 0x80044000); -+ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(pmmio + VGACNTRL, 0x0); -+ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1); -+ write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); -+ write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); -+ write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); -+ -+ /* Set up GTT. */ -+ -+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); -+ uma_size = 0; -+ if (!(reg16 & 2)) { -+ uma_size = decode_igd_memory_size((reg16 >> 4) & 7); -+ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); -+ } -+ -+ for (i = 0; i < (uma_size - 256) / 4; i++) -+ { -+ outl((i << 2) | 1, piobase); -+ outl(pphysbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ /* Clear interrupts. */ -+ write32(pmmio + DEIIR, 0xffffffff); -+ write32(pmmio + SDEIIR, 0xffffffff); -+ write32(pmmio + IIR, 0xffffffff); -+ write32(pmmio + IMR, 0xffffffff); -+ write32(pmmio + EIR, 0xffffffff); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ return 0; -+ -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should have a correct header */ -+static int vga_connected(u8 *pmmio) { -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(pmmio + GMBUS0); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - #endif - - static void gma_func0_init(struct device *dev) -@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev) - ); - - int err; -- err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ if (vga_connected(mmiobase)) -+ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ iobase, mmiobase, graphics_base); -+ else -+ err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0007-i945-gma.c-generate-fake-VBT.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0007-i945-gma.c-generate-fake-VBT.patch deleted file mode 100644 index 6f0272fd..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/0007-i945-gma.c-generate-fake-VBT.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 60cc2c4532f63a40486b7c4e891fb87fb6d4ab7f Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Wed, 7 Sep 2016 22:10:57 +0200 -Subject: [PATCH] i945/gma.c: generate fake VBT - -This generates a fake VBT for the Intel i945 graphic device. -i945 supports both the mobile chipset 945gm (calistoga) -and the desktop chipset 945gc (lakeport), -which is why a VBT with a different id string -needs to be created for each target. - -The VBT id string is obtained from the vbios blob in the following way: -"strings vbios.bin | grep VBT". - -Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..f0944b9 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -433,6 +433,15 @@ static void gma_func0_init(struct device *dev) - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); -+ /* Linux relies on VBT for panel info. */ -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT CALISTOGA "); -+ } -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT LAKEPORT-G "); -+ } - #endif - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch deleted file mode 100644 index 0b8e146a..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch +++ /dev/null @@ -1,53 +0,0 @@ -From bbd04909524d7b9fd2e2b4dbd804801bbde66e44 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Wed, 7 Sep 2016 21:16:21 +0200 -Subject: [PATCH] lenovo/t60: add hda_verb.c - -This creates a config for the Lenovo T60 sound card based -on values taken from vendor bios -(in /sys/class/sound/hwC0D0/init_pin_configs on linux 3.16). -The sound card configuration on the vendor bios is the same -as the one on the Lenovo x60. - -It improves the default behavior of the sound card: -- internal microphone is chosen by default -- when jack is inserted it is chosen instead of internal speaker - -Change-Id: I44e3eaac437fe4ad97ff2b0eb32d36b33222c09b -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/mainboard/lenovo/t60/hda_verb.c | 19 +++++++++++++++++-- - 1 file changed, 17 insertions(+), 2 deletions(-) - -diff --git a/src/mainboard/lenovo/t60/hda_verb.c b/src/mainboard/lenovo/t60/hda_verb.c -index 072a306..dee3e80 100644 ---- a/src/mainboard/lenovo/t60/hda_verb.c -+++ b/src/mainboard/lenovo/t60/hda_verb.c -@@ -1,7 +1,22 @@ - #include <device/azalia_device.h> - --const u32 cim_verb_data[0] = {}; -+const u32 cim_verb_data[] = { -+ 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ -+ 0x17aa2025, /* Subsystem ID */ -+ 0x0000000b, /* Number of 4 dword sets */ - --const u32 pc_beep_verbs[0] = {}; -+ AZALIA_SUBVENDOR(0x0, 0x17aa2025), - -+ AZALIA_PIN_CFG(0, 0x05, 0xc3014110), -+ AZALIA_PIN_CFG(0, 0x06, 0x4221401f), -+ AZALIA_PIN_CFG(0, 0x07, 0x591311f0), -+ AZALIA_PIN_CFG(0, 0x08, 0xc3a15020), -+ AZALIA_PIN_CFG(0, 0x09, 0x41813021), -+ AZALIA_PIN_CFG(0, 0x0a, 0x014470f0), -+ AZALIA_PIN_CFG(0, 0x16, 0x59f311f0), -+ AZALIA_PIN_CFG(0, 0x17, 0x59931122), -+ AZALIA_PIN_CFG(0, 0x18, 0x41a19023), -+ AZALIA_PIN_CFG(0, 0x19, 0x9933e12e) -+}; -+const u32 pc_beep_verbs[0] = {}; - AZALIA_ARRAY_SIZES; --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch deleted file mode 100644 index 86bd6cb0..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Fri, 2 Sep 2016 22:35:32 +0200 -Subject: [PATCH] i945/gma.c use latest linux code to calculate divisors. - -The code to compute n, m1, m2, p1 divisors is not correct in coreboot and -on some targets hits a working mode at lower refresh rate, which is why -display is working on some targets. -This patch also fixes reference frequency. - -This patch reuses linux code to correctly compute divisors. - -The result is that some previously not working displays (Lenovo T60 with -1024x786, 1400x1050, 2048x1536) - -TESTED on T60 with 1024x786. - -Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- - 1 file changed, 38 insertions(+), 44 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..3f0b5b4 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -26,6 +26,8 @@ - #include <string.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> -+#include <commonlib/helpers.h> -+ - - #include "i945.h" - #include "chip.h" -@@ -43,7 +45,7 @@ - #define PGETBL_CTL 0x2020 - #define PGETBL_ENABLED 0x00000001 - --#define BASE_FREQUENCY 120000 -+#define BASE_FREQUENCY 100000 - - #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - -@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - u8 edid_data[128]; - unsigned long temp; - int hpolarity, vpolarity; -- u32 candp1, candn; -- u32 best_delta = 0xffffffff; -+ u32 smallest_err = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; -+ u32 pixel_p2; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; -@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - -- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock -- : (2 * mode->pixel_clock); -- -- /* Find suitable divisors. */ -- for (candp1 = 1; candp1 <= 8; candp1++) { -- for (candn = 5; candn <= 10; candn++) { -- u32 cur_frequency; -- u32 m; /* 77 - 131. */ -- u32 denom; /* 35 - 560. */ -- u32 current_delta; -- -- denom = candn * candp1 * 7; -- /* Doesnt overflow for up to -- 5000000 kHz = 5 GHz. */ -- m = (target_frequency * denom -- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; -- -- if (m < 77 || m > 131) -- continue; -- -- cur_frequency = (BASE_FREQUENCY * m) / denom; -- if (target_frequency > cur_frequency) -- current_delta = target_frequency - cur_frequency; -- else -- current_delta = cur_frequency - target_frequency; -- -- if (best_delta > current_delta) { -- best_delta = current_delta; -- pixel_n = candn; -- pixel_p1 = candp1; -- pixel_m2 = ((m + 3) % 5) + 7; -- pixel_m1 = (m - pixel_m2) / 5; -+ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; -+ target_frequency = mode->pixel_clock; -+ -+ /* Find suitable divisors, m1, m2, p1, n. */ -+ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ -+ /* should be closest to target frequency as possible */ -+ u32 candn, candm1, candm2, candp1; -+ for (candm1 = 8; candm1 <= 18; candm1++) { -+ for (candm2 = 3; candm2 <= 7; candm2++) { -+ for (candn = 1; candn <= 6; candn++) { -+ for (candp1 = 1; candp1 <= 8; candp1++) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * pixel_p2; -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if ((m < 70) || (m > 120)) -+ continue; -+ if (this_err < smallest_err) { -+ smallest_err = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } - } - } - } - -- if (best_delta == 0xffffffff) { -+ if (smallest_err == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return -1; - } -@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n -- / (pixel_p1 * 7)); -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * pixel_p2)); - - #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(pmmio + FP0(1), -- ((pixel_n - 2) << 16) -- | ((pixel_m1 - 2) << 8) | pixel_m2); -+ (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS -@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (conf->gpu_lvds_use_spread_spectrum_clock - ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV - : 0) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | -@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + HTOTAL(1), - ((hactive + right_border + hblank - 1) << 16) --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch deleted file mode 100644 index 884b2829..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Fri, 2 Sep 2016 22:35:32 +0200 -Subject: [PATCH 1/2] i945/gma.c use latest linux code to calculate divisors. - -The code to compute n, m1, m2, p1 divisors is not correct in coreboot and -on some targets hits a working mode at lower refresh rate, which is why -display is working on some targets. -This patch also fixes reference frequency. - -This patch reuses linux code to correctly compute divisors. - -The result is that some previously not working displays (Lenovo T60 with -1024x786, 1400x1050, 2048x1536) - -TESTED on T60 with 1024x786. - -Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- - 1 file changed, 38 insertions(+), 44 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..3f0b5b4 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -26,6 +26,8 @@ - #include <string.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> -+#include <commonlib/helpers.h> -+ - - #include "i945.h" - #include "chip.h" -@@ -43,7 +45,7 @@ - #define PGETBL_CTL 0x2020 - #define PGETBL_ENABLED 0x00000001 - --#define BASE_FREQUENCY 120000 -+#define BASE_FREQUENCY 100000 - - #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - -@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - u8 edid_data[128]; - unsigned long temp; - int hpolarity, vpolarity; -- u32 candp1, candn; -- u32 best_delta = 0xffffffff; -+ u32 smallest_err = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; -+ u32 pixel_p2; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; -@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - -- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock -- : (2 * mode->pixel_clock); -- -- /* Find suitable divisors. */ -- for (candp1 = 1; candp1 <= 8; candp1++) { -- for (candn = 5; candn <= 10; candn++) { -- u32 cur_frequency; -- u32 m; /* 77 - 131. */ -- u32 denom; /* 35 - 560. */ -- u32 current_delta; -- -- denom = candn * candp1 * 7; -- /* Doesnt overflow for up to -- 5000000 kHz = 5 GHz. */ -- m = (target_frequency * denom -- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; -- -- if (m < 77 || m > 131) -- continue; -- -- cur_frequency = (BASE_FREQUENCY * m) / denom; -- if (target_frequency > cur_frequency) -- current_delta = target_frequency - cur_frequency; -- else -- current_delta = cur_frequency - target_frequency; -- -- if (best_delta > current_delta) { -- best_delta = current_delta; -- pixel_n = candn; -- pixel_p1 = candp1; -- pixel_m2 = ((m + 3) % 5) + 7; -- pixel_m1 = (m - pixel_m2) / 5; -+ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; -+ target_frequency = mode->pixel_clock; -+ -+ /* Find suitable divisors, m1, m2, p1, n. */ -+ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ -+ /* should be closest to target frequency as possible */ -+ u32 candn, candm1, candm2, candp1; -+ for (candm1 = 8; candm1 <= 18; candm1++) { -+ for (candm2 = 3; candm2 <= 7; candm2++) { -+ for (candn = 1; candn <= 6; candn++) { -+ for (candp1 = 1; candp1 <= 8; candp1++) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * pixel_p2; -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if ((m < 70) || (m > 120)) -+ continue; -+ if (this_err < smallest_err) { -+ smallest_err = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } - } - } - } - -- if (best_delta == 0xffffffff) { -+ if (smallest_err == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return -1; - } -@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n -- / (pixel_p1 * 7)); -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * pixel_p2)); - - #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(pmmio + FP0(1), -- ((pixel_n - 2) << 16) -- | ((pixel_m1 - 2) << 8) | pixel_m2); -+ (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS -@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (conf->gpu_lvds_use_spread_spectrum_clock - ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV - : 0) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | -@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + HTOTAL(1), - ((hactive + right_border + hblank - 1) << 16) --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0006-i945-gma.c-add-native-VGA-init.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0006-i945-gma.c-add-native-VGA-init.patch deleted file mode 100644 index 26eed5b4..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0006-i945-gma.c-add-native-VGA-init.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 7ed0951bcf59dfd8b1893232b674455ff8f03f83 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 5 Sep 2016 22:46:11 +0200 -Subject: [PATCH 2/2] i945/gma.c: add native VGA init - -This reuses the Intel Pineview native graphic initialization -to have output on the VGA connector of i945 devices. - -The behavior is the same as with the vendor VBIOS BLOB. -It uses the external VGA display if it is connected. - -Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 196 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 194 insertions(+), 2 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 3f0b5b4..ac19d5a 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase) - return 0; - } - --static int intel_gma_init(struct northbridge_intel_i945_config *conf, -+static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, - unsigned int pphysbase, unsigned int piobase, - void *pmmio, unsigned int pgfx) - { -@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - #endif - return 0; - } -+ -+static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, -+ unsigned int pphysbase, unsigned int piobase, -+ void *pmmio, unsigned int pgfx) -+{ -+ int i; -+ u32 hactive, vactive; -+ u16 reg16; -+ u32 uma_size; -+ -+ printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", -+ (u32)pmmio, piobase, pphysbase); -+ -+ gtt_setup(pmmio); -+ -+ /* Disable VGA. */ -+ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); -+ -+ /* Disable pipes. */ -+ write32(pmmio + PIPECONF(0), 0); -+ write32(pmmio + PIPECONF(1), 0); -+ -+ write32(pmmio + INSTPM, 0x800); -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(pmmio + VGA0, 0x200074); -+ write32(pmmio + VGA1, 0x200074); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); -+ write32(pmmio + DSPCLK_GATE_D, 0); -+ write32(pmmio + FW_BLC, 0x03060106); -+ write32(pmmio + FW_BLC2, 0x00000306); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + 0x7041c, 0x0); -+ -+ write32(pmmio + DPLL_MD(0), 0x3); -+ write32(pmmio + DPLL_MD(1), 0x3); -+ write32(pmmio + DSPCNTR(1), 0x1000000); -+ write32(pmmio + PIPESRC(1), 0x027f01df); -+ -+ vga_misc_write(0x67); -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ // Disable screen memory to prevent garbage from appearing. -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(pmmio + PF_WIN_POS(0), 0); -+ -+ write32(pmmio + PIPESRC(0), (639 << 16) | 399); -+ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(pmmio + PFIT_CONTROL, 0x0); -+ -+ mdelay(1); -+ -+ write32(pmmio + FDI_RX_CTL(0), 0x00002040); -+ mdelay(1); -+ write32(pmmio + FDI_RX_CTL(0), 0x80002050); -+ write32(pmmio + FDI_TX_CTL(0), 0x00044000); -+ mdelay(1); -+ write32(pmmio + FDI_TX_CTL(0), 0x80044000); -+ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(pmmio + VGACNTRL, 0x0); -+ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1); -+ write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); -+ write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); -+ write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); -+ -+ /* Set up GTT. */ -+ -+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); -+ uma_size = 0; -+ if (!(reg16 & 2)) { -+ uma_size = decode_igd_memory_size((reg16 >> 4) & 7); -+ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); -+ } -+ -+ for (i = 0; i < (uma_size - 256) / 4; i++) -+ { -+ outl((i << 2) | 1, piobase); -+ outl(pphysbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ /* Clear interrupts. */ -+ write32(pmmio + DEIIR, 0xffffffff); -+ write32(pmmio + SDEIIR, 0xffffffff); -+ write32(pmmio + IIR, 0xffffffff); -+ write32(pmmio + IMR, 0xffffffff); -+ write32(pmmio + EIR, 0xffffffff); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ return 0; -+ -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should have a correct header */ -+static int vga_connected(u8 *pmmio) { -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(pmmio + GMBUS0); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - #endif - - static void gma_func0_init(struct device *dev) -@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev) - ); - - int err; -- err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ if (vga_connected(mmiobase)) -+ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ iobase, mmiobase, graphics_base); -+ else -+ err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0007-i945-gma.c-generate-fake-VBT.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0007-i945-gma.c-generate-fake-VBT.patch deleted file mode 100644 index 6f0272fd..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0007-i945-gma.c-generate-fake-VBT.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 60cc2c4532f63a40486b7c4e891fb87fb6d4ab7f Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Wed, 7 Sep 2016 22:10:57 +0200 -Subject: [PATCH] i945/gma.c: generate fake VBT - -This generates a fake VBT for the Intel i945 graphic device. -i945 supports both the mobile chipset 945gm (calistoga) -and the desktop chipset 945gc (lakeport), -which is why a VBT with a different id string -needs to be created for each target. - -The VBT id string is obtained from the vbios blob in the following way: -"strings vbios.bin | grep VBT". - -Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..f0944b9 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -433,6 +433,15 @@ static void gma_func0_init(struct device *dev) - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); -+ /* Linux relies on VBT for panel info. */ -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT CALISTOGA "); -+ } -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT LAKEPORT-G "); -+ } - #endif - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch deleted file mode 100644 index 884b2829..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Fri, 2 Sep 2016 22:35:32 +0200 -Subject: [PATCH 1/2] i945/gma.c use latest linux code to calculate divisors. - -The code to compute n, m1, m2, p1 divisors is not correct in coreboot and -on some targets hits a working mode at lower refresh rate, which is why -display is working on some targets. -This patch also fixes reference frequency. - -This patch reuses linux code to correctly compute divisors. - -The result is that some previously not working displays (Lenovo T60 with -1024x786, 1400x1050, 2048x1536) - -TESTED on T60 with 1024x786. - -Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- - 1 file changed, 38 insertions(+), 44 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..3f0b5b4 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -26,6 +26,8 @@ - #include <string.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> -+#include <commonlib/helpers.h> -+ - - #include "i945.h" - #include "chip.h" -@@ -43,7 +45,7 @@ - #define PGETBL_CTL 0x2020 - #define PGETBL_ENABLED 0x00000001 - --#define BASE_FREQUENCY 120000 -+#define BASE_FREQUENCY 100000 - - #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - -@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - u8 edid_data[128]; - unsigned long temp; - int hpolarity, vpolarity; -- u32 candp1, candn; -- u32 best_delta = 0xffffffff; -+ u32 smallest_err = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; -+ u32 pixel_p2; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; -@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - -- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock -- : (2 * mode->pixel_clock); -- -- /* Find suitable divisors. */ -- for (candp1 = 1; candp1 <= 8; candp1++) { -- for (candn = 5; candn <= 10; candn++) { -- u32 cur_frequency; -- u32 m; /* 77 - 131. */ -- u32 denom; /* 35 - 560. */ -- u32 current_delta; -- -- denom = candn * candp1 * 7; -- /* Doesnt overflow for up to -- 5000000 kHz = 5 GHz. */ -- m = (target_frequency * denom -- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; -- -- if (m < 77 || m > 131) -- continue; -- -- cur_frequency = (BASE_FREQUENCY * m) / denom; -- if (target_frequency > cur_frequency) -- current_delta = target_frequency - cur_frequency; -- else -- current_delta = cur_frequency - target_frequency; -- -- if (best_delta > current_delta) { -- best_delta = current_delta; -- pixel_n = candn; -- pixel_p1 = candp1; -- pixel_m2 = ((m + 3) % 5) + 7; -- pixel_m1 = (m - pixel_m2) / 5; -+ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; -+ target_frequency = mode->pixel_clock; -+ -+ /* Find suitable divisors, m1, m2, p1, n. */ -+ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ -+ /* should be closest to target frequency as possible */ -+ u32 candn, candm1, candm2, candp1; -+ for (candm1 = 8; candm1 <= 18; candm1++) { -+ for (candm2 = 3; candm2 <= 7; candm2++) { -+ for (candn = 1; candn <= 6; candn++) { -+ for (candp1 = 1; candp1 <= 8; candp1++) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * pixel_p2; -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if ((m < 70) || (m > 120)) -+ continue; -+ if (this_err < smallest_err) { -+ smallest_err = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } - } - } - } - -- if (best_delta == 0xffffffff) { -+ if (smallest_err == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return -1; - } -@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n -- / (pixel_p1 * 7)); -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * pixel_p2)); - - #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(pmmio + FP0(1), -- ((pixel_n - 2) << 16) -- | ((pixel_m1 - 2) << 8) | pixel_m2); -+ (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS -@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (conf->gpu_lvds_use_spread_spectrum_clock - ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV - : 0) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | -@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + HTOTAL(1), - ((hactive + right_border + hblank - 1) << 16) --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch deleted file mode 100644 index 26eed5b4..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 7ed0951bcf59dfd8b1893232b674455ff8f03f83 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 5 Sep 2016 22:46:11 +0200 -Subject: [PATCH 2/2] i945/gma.c: add native VGA init - -This reuses the Intel Pineview native graphic initialization -to have output on the VGA connector of i945 devices. - -The behavior is the same as with the vendor VBIOS BLOB. -It uses the external VGA display if it is connected. - -Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 196 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 194 insertions(+), 2 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 3f0b5b4..ac19d5a 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase) - return 0; - } - --static int intel_gma_init(struct northbridge_intel_i945_config *conf, -+static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, - unsigned int pphysbase, unsigned int piobase, - void *pmmio, unsigned int pgfx) - { -@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - #endif - return 0; - } -+ -+static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, -+ unsigned int pphysbase, unsigned int piobase, -+ void *pmmio, unsigned int pgfx) -+{ -+ int i; -+ u32 hactive, vactive; -+ u16 reg16; -+ u32 uma_size; -+ -+ printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", -+ (u32)pmmio, piobase, pphysbase); -+ -+ gtt_setup(pmmio); -+ -+ /* Disable VGA. */ -+ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); -+ -+ /* Disable pipes. */ -+ write32(pmmio + PIPECONF(0), 0); -+ write32(pmmio + PIPECONF(1), 0); -+ -+ write32(pmmio + INSTPM, 0x800); -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(pmmio + VGA0, 0x200074); -+ write32(pmmio + VGA1, 0x200074); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); -+ write32(pmmio + DSPCLK_GATE_D, 0); -+ write32(pmmio + FW_BLC, 0x03060106); -+ write32(pmmio + FW_BLC2, 0x00000306); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + 0x7041c, 0x0); -+ -+ write32(pmmio + DPLL_MD(0), 0x3); -+ write32(pmmio + DPLL_MD(1), 0x3); -+ write32(pmmio + DSPCNTR(1), 0x1000000); -+ write32(pmmio + PIPESRC(1), 0x027f01df); -+ -+ vga_misc_write(0x67); -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ // Disable screen memory to prevent garbage from appearing. -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(pmmio + PF_WIN_POS(0), 0); -+ -+ write32(pmmio + PIPESRC(0), (639 << 16) | 399); -+ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(pmmio + PFIT_CONTROL, 0x0); -+ -+ mdelay(1); -+ -+ write32(pmmio + FDI_RX_CTL(0), 0x00002040); -+ mdelay(1); -+ write32(pmmio + FDI_RX_CTL(0), 0x80002050); -+ write32(pmmio + FDI_TX_CTL(0), 0x00044000); -+ mdelay(1); -+ write32(pmmio + FDI_TX_CTL(0), 0x80044000); -+ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(pmmio + VGACNTRL, 0x0); -+ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1); -+ write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); -+ write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); -+ write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); -+ -+ /* Set up GTT. */ -+ -+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); -+ uma_size = 0; -+ if (!(reg16 & 2)) { -+ uma_size = decode_igd_memory_size((reg16 >> 4) & 7); -+ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); -+ } -+ -+ for (i = 0; i < (uma_size - 256) / 4; i++) -+ { -+ outl((i << 2) | 1, piobase); -+ outl(pphysbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ /* Clear interrupts. */ -+ write32(pmmio + DEIIR, 0xffffffff); -+ write32(pmmio + SDEIIR, 0xffffffff); -+ write32(pmmio + IIR, 0xffffffff); -+ write32(pmmio + IMR, 0xffffffff); -+ write32(pmmio + EIR, 0xffffffff); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ return 0; -+ -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should have a correct header */ -+static int vga_connected(u8 *pmmio) { -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(pmmio + GMBUS0); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - #endif - - static void gma_func0_init(struct device *dev) -@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev) - ); - - int err; -- err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ if (vga_connected(mmiobase)) -+ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ iobase, mmiobase, graphics_base); -+ else -+ err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch deleted file mode 100644 index 6f0272fd..00000000 --- a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 60cc2c4532f63a40486b7c4e891fb87fb6d4ab7f Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Wed, 7 Sep 2016 22:10:57 +0200 -Subject: [PATCH] i945/gma.c: generate fake VBT - -This generates a fake VBT for the Intel i945 graphic device. -i945 supports both the mobile chipset 945gm (calistoga) -and the desktop chipset 945gc (lakeport), -which is why a VBT with a different id string -needs to be created for each target. - -The VBT id string is obtained from the vbios blob in the following way: -"strings vbios.bin | grep VBT". - -Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..f0944b9 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -433,6 +433,15 @@ static void gma_func0_init(struct device *dev) - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); -+ /* Linux relies on VBT for panel info. */ -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT CALISTOGA "); -+ } -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT LAKEPORT-G "); -+ } - #endif - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch b/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch deleted file mode 100644 index 187dbc9a..00000000 --- a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch +++ /dev/null @@ -1,415 +0,0 @@ -From 9659556d9edbba6c3530ed1d0630add30419210f Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sun, 4 Sep 2016 16:01:11 +0200 -Subject: [PATCH 1/2] x4x/gma.c: Add VESA native resolution mode - -This patch implements native resolution, VESA mode, on the VGA output of -x4x. - -It relies on EDID to modeset, but has a fallback-mode (640 x 480 @ -60Hz) if this is no EDID could be found. This fallback mode only works in textmode -since in VESA mode some payloads (grub2) rely on VBE info, which is being -generated from an EDID. - -Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/x4x/gma.c | 282 ++++++++++++++++++++++++++++++++++------ - 1 file changed, 242 insertions(+), 40 deletions(-) - -diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c -index 2679026..118f98d 100644 ---- a/src/northbridge/intel/x4x/gma.c -+++ b/src/northbridge/intel/x4x/gma.c -@@ -26,24 +26,68 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" - #include "x4x.h" - #include <drivers/intel/gma/intel_bios.h> -+#include <drivers/intel/gma/edid.h> - #include <drivers/intel/gma/i915.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUENCY 96000 -+ -+static u8 edid_is_null(u8 *edid, u32 edid_size) -+{ -+ u32 i; -+ for (i = 0; i < edid_size; i++) { -+ if (*(edid + i) != 0) -+ return 0; -+ } -+ return 1; -+} - static void intel_gma_init(const struct northbridge_intel_x4x_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -+ - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u8 edid_not_found; -+ -+ /* Initialise mode variables for 640 x 480 @ 60Hz */ -+ u32 hactive = 640, vactive = 480; -+ u32 right_border = 0, bottom_border = 0; -+ int hpolarity = 0, vpolarity = 0; -+ u32 hsync = 96, vsync = 2; -+ u32 hblank = 160, vblank = 45; -+ u32 hfront_porch = 16, vfront_porch = 10; -+ u32 target_frequency = 25175; -+ -+ u32 err_most = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Set up GTT */ -+ for (i = 0; i < 0x1000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -73,107 +117,258 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ edid_not_found = edid_is_null(edid_data, sizeof(edid_data)); -+ if (!edid_not_found) { -+ printk(BIOS_DEBUG, "EDID is not null"); -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ } else -+ printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode"); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 16; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST( -+ BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < err_most) { -+ err_most = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (err_most == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * 10)); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ hactive * vactive * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } - } - - static void native_init(struct device *dev) - { -+ struct resource *lfb_res; -+ struct resource *pio_res; -+ u32 physbase; - struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); - struct northbridge_intel_x4x_config *conf = dev->chip_info; - -+ lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); -+ pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); -+ physbase = pci_read_config32(dev, 0x5c) & ~0xf; -+ - if (gtt_res && gtt_res->base) { - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0)); -+ intel_gma_init(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ -@@ -182,6 +377,7 @@ static void native_init(struct device *dev) - - static void gma_func0_init(struct device *dev) - { -+ u16 reg16; - u32 reg32; - - /* IGD needs to be Bus Master */ -@@ -189,6 +385,12 @@ static void gma_func0_init(struct device *dev) - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - -+ /* configure GMBUSFREQ */ -+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc); -+ reg16 &= ~0x1ff; -+ reg16 |= 0xbc; -+ pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc, reg16); -+ - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) - native_init(dev); - else --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch b/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch deleted file mode 100644 index d579df55..00000000 --- a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch +++ /dev/null @@ -1,30 +0,0 @@ -From f9a84edfc672424c9dcaa0a71ad0751c2355c3d0 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 5 Sep 2016 12:07:57 +0200 -Subject: [PATCH 2/2] gigabyte/ga-g41m-es2l: add VESA mode to Kconfig - -This patch adds MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG to the -gigabyte/ga-g41m-es2l Kconfig to allow selecting between textmode and -vesamode in menuconfig. - -Change-Id: I84b61118fa0419d49d2498b66029711cdce97576 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig -index 6452f4d..281d498 100644 ---- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig -+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig -@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS - select BOARD_ROMSIZE_KB_1024 - select INTEL_EDID - select MAINBOARD_HAS_NATIVE_VGA_INIT -+ select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list index 451d1b75..145d6c30 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list index 4ea9a7ad..0ed8edc9 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list @@ -1,4 +1,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list index 59e0a36a..30301d55 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list @@ -4,4 +4,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch index 26632b7d..26632b7d 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch index ef42f3e8..ef42f3e8 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch index fb30c4c2..fb30c4c2 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/INFO b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/INFO new file mode 100644 index 00000000..0537bbc8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/INFO @@ -0,0 +1,4 @@ +# NOTE: remove this when updating coreboot. This has been merged upstream +printf "ThinkPad T500 (depends on T400 patch)\n" +git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/reused.list new file mode 100644 index 00000000..59e0a36a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch index 26632b7d..26632b7d 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch index ef42f3e8..ef42f3e8 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch index fb30c4c2..fb30c4c2 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/reused.list new file mode 100644 index 00000000..59e0a36a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch index 26632b7d..26632b7d 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch index ef42f3e8..ef42f3e8 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch index fb30c4c2..fb30c4c2 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/INFO b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/INFO new file mode 100644 index 00000000..0537bbc8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/INFO @@ -0,0 +1,4 @@ +# NOTE: remove this when updating coreboot. This has been merged upstream +printf "ThinkPad T500 (depends on T400 patch)\n" +git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/reused.list new file mode 100644 index 00000000..59e0a36a --- /dev/null +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/reused.list @@ -0,0 +1,7 @@ +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch +/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list index 8a98e98c..71fc4dfc 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list @@ -2,4 +2,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list index 8a98e98c..71fc4dfc 100644 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list +++ b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list @@ -2,4 +2,3 @@ /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch /resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch -/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch deleted file mode 100644 index d89e4884..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 0821d0290e7e17e375ffdb48a86b56504db4f77e Mon Sep 17 00:00:00 2001 -From: Damien Zammit <damien@zamaudio.com> -Date: Sat, 27 Aug 2016 00:35:48 +1000 -Subject: [PATCH] nb/intel/gm45: Fix IOMMU - -Previously the ME was being reported as present in ACPI -even when it's firmware was missing. Now we do a check via the pci device -(HECI) to verify if the ME is there or not. - -Note that this test could fail if ME is present but disabled in devicetree, -but in that case you won't see it in the lspci tree anyway so it shouldn't -be an issue. - -Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0 -Signed-off-by: Damien Zammit <damien@zamaudio.com> ---- - src/northbridge/intel/gm45/acpi.c | 3 ++- - src/northbridge/intel/gm45/iommu.c | 2 ++ - 2 files changed, 4 insertions(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c -index 8990c3b..b90afca 100644 ---- a/src/northbridge/intel/gm45/acpi.c -+++ b/src/northbridge/intel/gm45/acpi.c -@@ -72,7 +72,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) - - static unsigned long acpi_fill_dmar(unsigned long current) - { -- int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL); -+ int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL) && -+ (pci_read_config8(dev_find_slot(0, PCI_DEVFN(3, 0)), PCI_CLASS_REVISION) != 0xff); - int stepping = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_CLASS_REVISION); - - unsigned long tmp = current; -diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c -index 10548f4..0c3c18e 100644 ---- a/src/northbridge/intel/gm45/iommu.c -+++ b/src/northbridge/intel/gm45/iommu.c -@@ -40,6 +40,8 @@ void init_iommu() - } - if (me_active) { - MCHBAR32(0x10) = IOMMU_BASE3 | 1; /* ME @ 0:3.0-3 */ -+ } else { -+ MCHBAR32(0x10) = 0; /* disable IOMMU for ME */ - } - MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */ - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/scripts/helpers/build/roms/withgrub b/resources/scripts/helpers/build/roms/withgrub index d4b6529b..28f35736 100755 --- a/resources/scripts/helpers/build/roms/withgrub +++ b/resources/scripts/helpers/build/roms/withgrub @@ -95,7 +95,7 @@ done # Then put them in the ROM images. if [ -d "bin/grub/" ]; then cd "bin/grub/" - for board in "x200" "r400" "t400" "t500" + for board in "x200" "r400" "t400" "t500" "w500" do for romsize in "4m" "8m" "16m" do diff --git a/resources/scripts/helpers/build/roms/withgrub_helper b/resources/scripts/helpers/build/roms/withgrub_helper index c4e14b29..26d69f0b 100755 --- a/resources/scripts/helpers/build/roms/withgrub_helper +++ b/resources/scripts/helpers/build/roms/withgrub_helper @@ -88,7 +88,7 @@ fi for romtype in txtmode vesafb do - if [ "${boardtarget}" = "kgpe-d16" ] || [ "${boardtarget}" = "kcma-d8" ] || [ "${boardtarget}" = "d510mo" ]; then + if [ "${boardtarget}" = "kgpe-d16" ] || [ "${boardtarget}" = "ga-g41m-es2l" ] || [ "${boardtarget}" = "kcma-d8" ] || [ "${boardtarget}" = "d510mo" ]; then if [ "${romtype}" = "vesafb" ]; then printf "Only text-mode is reported to work on KGPE-D16, KCMA-D8, D510MO and ga-g41m-es2l\n" printf "TODO: get tpearson to fix it\n" @@ -150,7 +150,8 @@ do # Add the background image if [ "$romtype" = "vesafb" ] then - if [ "$1" = "macbook21" ] || [ "$1" = "x200_4mb" ] || [ "$1" = "x200_8mb" ] || [ "$1" = "x200_16mb" ] || [ "$1" = "r400_4mb" ] || [ "$1" = "r400_8mb" ] || [ "$1" = "r400_16mb" ] || [ "$1" = "t400_4mb" ] || [ "$1" = "t400_8mb" ] || [ "$1" = "t400_16mb" ] || [ "$1" = "t500_4mb" ] || [ "$1" = "t500_8mb" ] || [ "$1" = "t500_16mb" ] + if [ "$1" = "macbook21" ] || [ "$1" = "x200_4mb" ] || [ "$1" = "x200_8mb" ] || [ "$1" = "x200_16mb" ] || [ "$1" = "r400_4mb" ] || [ "$1" = "r400_8mb" ] || [ "$1" = "r400_16mb" ] || [ "$1" = "t400_4mb" ] || [ "$1" = "t400_8mb" ] || [ "$1" = "t400_16mb" ] || [ "$1" = "t500_4mb" ] || [ "$1" = "t500_8mb" ] || [ "$1" = "t500_16mb" ] || [ "$1" = "w500_4mb" ] || [ "$1" = "w500_8mb" ] || [ "$1" = "w500_16mb" ] + then ./util/cbfstool/cbfstool "${boardtarget}_${romtype}.rom" add -f ../../../resources/grub/background/background1280x800.png -n background.png -t raw else diff --git a/resources/scripts/helpers/download/flashrom b/resources/scripts/helpers/download/flashrom index e7a58949..a706e9ee 100755 --- a/resources/scripts/helpers/download/flashrom +++ b/resources/scripts/helpers/download/flashrom @@ -49,7 +49,7 @@ git reset --hard # Apply patches # ------------------------------------------------------------------------------ -printf "Enabling whitelist for X200S, X200 Tablet, T400, T500 and R400\n" +printf "Enabling whitelist for X200S, X200 Tablet, T400, T500, W500 and R400\n" git am "../resources/flashrom/patch/0001-New-laptops-whitelisted-ThinkPad-R400-and-ThinkPad-T.patch" printf "Enabling whitelist for Libiquity Taurinus X200\n" diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/blobs.list b/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/blobs.list deleted file mode 100644 index a8a9a964..00000000 --- a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/blobs.list +++ /dev/null @@ -1,52 +0,0 @@ -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c -src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c -src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c -src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000f.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c -src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c -src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c -src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c 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-src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h -src/vendorcode/amd/cimx/rd890/HotplugFirmware.h -src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc -src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h -src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h -src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h -src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h -src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs.list b/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs.list deleted file mode 100644 index 6f672156..00000000 --- a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs.list +++ /dev/null @@ -1,335 +0,0 @@ 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-src/cpu/intel/fsp_model_406dx/acpi.c -src/northbridge/intel/fsp_sandybridge/fsp/Kconfig -src/drivers/aspeed/common/ast_dram_tables.h -src/drivers/aspeed/common/ast_tables.h -src/mainboard/intel/cougar_canyon2/Kconfig -src/cpu/amd/family_10h-family_15h/processor_name.c -src/cpu/amd/family_10h-family_15h/init_cpus.c -src/cpu/intel/fsp_model_206ax/acpi.c diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs_notes b/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs_notes deleted file mode 100644 index 551da4a8..00000000 --- a/resources/utilities/coreboot-libre/blobs/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/nonblobs_notes +++ /dev/null @@ -1,15 +0,0 @@ -.spd.hex files - serial presence detect. These are not blobs -see JEDEC standard or https://en.wikipedia.org/wiki/Serial_presence_detect -These are added to the nonblobs file - -src/northbridge/intel/nehalem/raminit_tables.c" -src/northbridge/intel/sandybridge/raminit_patterns.h -These are used by native raminit for the relevant platforms, and are not blobs - -"src/southbridge/nvidia/mcp55/early_setup_ss.h" \ -"src/southbridge/nvidia/ck804/early_setup_ss.h" \ -"src/southbridge/sis/sis966/early_setup_ss.h" -not blobs - -The text in this file is CC-BY-SA 4.0 or higher. All contributions to it must -be made under the same license. |