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| * | | Amend path to SeaBIOS payload in coreboot configsAndrew Robbins2018-11-2456-56/+56
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| * | | Place built SeaBIOS files in its build directoryAndrew Robbins2018-11-241-2/+1
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| * | | Consolidate SeaBIOS configsAndrew Robbins2018-11-246-103/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The only difference between the previous "bios" and "vgabios" targets was whether or not a VGA BIOS binary was built along with SeaBIOS. It seemed needless to compile twice in the event that you want both the SeaBIOS payload and its VGA BIOS when you can compile once and make the decision yourself whether to use the produced vgabios.bin
| * | | Bump SeaBIOS revision and update configsAndrew Robbins2018-11-243-1/+5
|/ / / | | | | | | | | | | | | | | | New options enabled (set to their default values): CONFIG_NVME=y CONFIG_SERCON=y
* | | Merge branch 'new-boards' of and_who/libreboot into masterSwift Geek2018-11-2416-0/+705
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| * | | Create SeaBIOS/GRUB targets for Z61t corebootAndrew Robbins2018-11-166-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Z61t ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot z61t textmode 2mb seabios'
| * | | Create 2,16MiB Coreboot configs/targets for Z61tAndrew Robbins2018-11-164-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 2MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Z61t Coreboot ROMs can be built with, e.g.: './libreboot build coreboot z61t textmode 2mb'
| * | | Add Z61t coreboot targetAndrew Robbins2018-11-163-0/+676
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| * | | Add iMac5,2 as MacBook2,1 variantAndrew Robbins2018-11-164-0/+9
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* | | | Merge branch 'depthcharge-libpayload' of and_who/libreboot into masterSwift Geek2018-11-243-3/+21
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| * | | Add function depthcharge_libpayload_build_path()Andrew Robbins2018-11-222-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function will return the correct build path for libpayload built for depthcharge targets nyan and veyron. Without this function, and using project_build_path() instead, LIBPAYLOAD_DIR would be set to "$root/$BUILD/libpayload-depthcharge-nyan-big" instead of the proper "$root/$BUILD/libpayload-depthcharge-nyan", for example.
| * | | Remove libpayload's veyron subtarget targets fileAndrew Robbins2018-11-221-2/+0
|/ / / | | | | | | | | | | | | There's no need to build for each supported veyron model since the libpayload veyron config is just for veyron in general.
* | | Merge branch 'cros-ec' of and_who/libreboot into masterSwift Geek2018-11-162-0/+94
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| * | | Patch CrOS-EC veyron to avoid compilation errorsAndrew Robbins2018-11-152-0/+94
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* | | Merge branch 'master' of Kaiapuni/libreboot into masterLeah Rowe2018-11-141-1/+2
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| * | | Added Toshiba Matsushita LTD121KC9B to known working LCD panelsLouis Roseguo2018-11-131-1/+2
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* | | | Merge branch 'elefaq' of swiftgeek/libreboot into masterAndrew Robbins2018-11-141-0/+2
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| * | | | Fail and Fail OftenSebastian 'Swift Geek' Grzywna2018-11-141-0/+2
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* | | | Merge branch 'cros-ec' of and_who/libreboot into masterSwift Geek2018-11-081-80/+100
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| * | | | Update CrOS-EC context switching patchAndrew Robbins2018-11-061-80/+100
| | | | | | | | | | | | | | | | | | | | This is the final version of the patch which was merged upstream.
* | | | | Merge branch 'kcma-d8' of and_who/libreboot into masterSwift Geek2018-11-071-3/+3
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| * | | | Note correct form factor in KCMA-D8 docsAndrew Robbins2018-11-071-3/+3
| | | | | | | | | | | | | | | | | | | | The KCMA-D8 board is ATX, not E-ATX or SSI EEB 3.61.
* | | | | Merge branch 'cros-ec' of and_who/libreboot into masterSwift Geek2018-11-064-31/+2
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| * | | | | Remove obsolete CrOS-EC Veyron patch for math_util.cAndrew Robbins2018-11-052-29/+0
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| * | | | | Revert to older CrOS-EC revision for Veyron boardsAndrew Robbins2018-11-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support was removed for Veyron Speedy/Minnie in the more recent revision.
| * | | | | Revert to older CrOS-EC revision for Nyan boardsAndrew Robbins2018-11-051-1/+1
|/ / / / / | | | | | | | | | | | | | | | Support was removed for Nyan Big/Blaze in the more recent revision.
* | | | | Merge branch 'docfix' of specing/libreboot into masterSwift Geek2018-11-056-38/+112
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| * | | | | Reword againFedja Beader2018-11-021-8/+8
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| * | | | | Reword the GM45 introductory section on the MAC address page.Fedja Beader2018-11-021-8/+17
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| * | | | | Reword the section on obtaining the MAC address and remove unnecessaryFedja Beader2018-11-021-10/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | images .. but do not unlink them
| * | | | | Move MAC address parts into its own document, signal that modifying itFedja Beader2018-10-246-38/+104
| | |_|/ / | |/| | | | | | | | | | | | | is optional and in addition tell users how to do so in their operating system.
* | | | | Merge branch 'doc_panic' of specing/libreboot into masterSwift Geek2018-11-051-0/+81
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| * | | | Add information about panics/freezes on some *00 laptops.Fedja Beader2018-11-031-0/+15
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| * | | | Add kernel panic/netconsole info to FAQFedja Beader2018-11-031-0/+66
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* | | | Merge branch 'cyberbits' of infertux/libreboot into masterAndrew Robbins2018-11-041-0/+4
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| * | | | Add mirror.cyberbits.eu to download pageCédric Félizard2018-11-031-0/+4
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* | | | make freenode a linkLeah Rowe2018-11-021-6/+6
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* | | | typofixes on last news article, per swiftgeek and JohnMH suggestionsLeah Rowe2018-11-021-5/+5
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* | | | news post about freenode 2018 libreboot workshopLeah Rowe2018-11-022-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PR would have been unwise for this, because it's urgent that this is merged right away swiftgeek and and_who: if you disapprove, feel free to revert this commit and I'll put it to pull request instead
* | | | Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-3033-3/+61
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| * | | | Create Coreboot Depthcharge target for Veyron SpeedyAndrew Robbins2018-10-304-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Veyron Speedy ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron speedy corebootfb 4mb depthcharge'
| * | | | Create 4,16MiB Coreboot configs/targets for Veyron SpeedyAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Speedy Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron speedy corebootfb 4mb'
| * | | | Correct CBFS_SIZE in Veyron Speedy Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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| * | | | Create Coreboot Depthcharge target for Veyron MinnieAndrew Robbins2018-10-304-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Veyron Minnie ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron minnie corebootfb 4mb depthcharge'
| * | | | Create 4,16MiB Coreboot configs/targets for Veyron MinnieAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Minnie Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron minnie corebootfb 4mb'
| * | | | Correct CBFS_SIZE in Veyron Minnie Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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| * | | | Create Coreboot Depthcharge target for Veyron MickeyAndrew Robbins2018-10-302-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Veyron Mickey ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron mickey corebootfb 4mb depthcharge'
| * | | | Create 4MiB Coreboot config/target for Veyron MickeyAndrew Robbins2018-10-303-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is not included (yet) as I was unable to find a teardown of this device (Asus Chromebit CS10) online to be sure that reassembly is possible. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Mickey Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron mickey corebootfb 4mb'
| * | | | Create Coreboot Depthcharge target for Veyron JerryAndrew Robbins2018-10-304-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Veyron Jerry ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron jerry corebootfb 4mb depthcharge'
| * | | | Create 4,16MiB Coreboot configs/targets for Veyron JerryAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Jerry Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron jerry corebootfb 4mb'
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