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* | Merge branch 'coreboot-rework' of and_who/libreboot into masterLeah Rowe2018-10-254-7/+2887
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| * Enable additional options in Veyron Mickey configAndrew Robbins2018-10-251-4/+4
| | | | | | | | | | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
| * Update Veyron Mickey Coreboot configAndrew Robbins2018-10-251-0/+710
| | | | | | | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
| * Enable additional options in Veyron Jerry configAndrew Robbins2018-10-251-3/+3
| | | | | | | | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" # CONFIG_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is not set
| * Update Veyron Jerry Coreboot configAndrew Robbins2018-10-251-2/+722
| | | | | | | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
| * Enable additional options in Veyron Speedy configAndrew Robbins2018-10-251-4/+4
| | | | | | | | | | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
| * Update Veyron Speedy Coreboot configAndrew Robbins2018-10-251-2/+727
| | | | | | | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
| * Enable additional options in Veyron Minnie configAndrew Robbins2018-10-251-4/+4
| | | | | | | | | | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
| * Update Veyron Minnie Coreboot configAndrew Robbins2018-10-251-2/+727
|/ | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-2310-0/+20
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| * Create SeaBIOS/GRUB targets for D510MO CorebootAndrew Robbins2018-10-226-0/+8
| | | | | | | | | | | | | | D510MO ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot d510mo textmode 1mb seabios'
| * Create 1,16MiB Coreboot configs/targets for D510MOAndrew Robbins2018-10-224-0/+12
|/ | | | | | | | | | | | | | 1MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. D510MO Coreboot ROMs can be built with, e.g.: './libreboot build coreboot d510mo textmode 1mb'
* Merge branch 'coreboot-rework' of and_who/libreboot into masterLeah Rowe2018-10-228-0/+17
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| * Create SeaBIOS/GRUB targets for D945GCLF CorebootAndrew Robbins2018-10-215-0/+6
| | | | | | | | | | | | | | | | | | | | | | Due to the limited flash space on the board, SeaBIOS is currently the sole payload option when building 512KiB-sized ROMs. D945GCLF ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot d945gclf textmode 512kb seabios', or './libreboot build coreboot d945gclf textmode 16mb grub'
| * Create 512KiB,16MiB Coreboot configs/targets for D945GCLFAndrew Robbins2018-10-213-0/+11
|/ | | | | | | | | | | | | | 512KiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. D945GCLF Coreboot ROMs can be built with, e.g.: './libreboot build coreboot d945gclf textmode 512kb'
* Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-2121-0/+44
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| * Create SeaBIOS/GRUB targets for GA-G41M-ES2L CorebootAndrew Robbins2018-10-2012-0/+16
| | | | | | | | | | | | | | GA-G41M-ES2L ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot ga-g41m-es2l corebootfb 1mb seabios'
| * Create 1,16MiB Coreboot configs/targets for GA-G41M-ES2LAndrew Robbins2018-10-206-0/+22
| | | | | | | | | | | | | | | | 1MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with larger flash chips. GA-G41M-ES2L Coreboot ROMs can be built with, e.g.: './libreboot build coreboot ga-g41m-es2l textmode 1mb'
| * Create GA-G41M-ES2L corebootfb/textmode Coreboot targetsAndrew Robbins2018-10-203-0/+6
|/ | | | | | | | | | | | | | | The corebootfb ROM will use Coreboot's framebuffer for display while the textmode ROM will use the legacy VGA text mode which is necessary for payloads such as Memtest86+. Options (and their values) changed in the new corebootfb config: #CONFIG_VGA_TEXT_FRAMEBUFFER is not set CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y CONFIG_LINEAR_FRAMEBUFFER=y GA-G41M-ES2L Coreboot ROMs can now be built with './libreboot build coreboot ga-g41m-es2l corebootfb' or './libreboot build coreboot ga-g41m-es2l textmode', respectively.
* Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-2110-0/+20
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| * Create SeaBIOS/GRUB targets for KCMA-D8 CorebootAndrew Robbins2018-10-206-0/+8
| | | | | | | | | | | | | | KCMA-D8 ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot kcma-d8 textmode 2mb seabios'
| * Create 2mb,16mb Coreboot configs/targets for KCMA-D8Andrew Robbins2018-10-204-0/+12
|/ | | | | | | | | | Text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. KCMA-D8 Coreboot ROMs can be built with, e.g.: './libreboot build coreboot kcma-d8 textmode 2mb'
* Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-2021-0/+44
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| * Create SeaBIOS/GRUB targets for KFSN4-DRE CorebootAndrew Robbins2018-10-2012-0/+16
| | | | | | | | | | | | | | KFSN4-DRE ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot kfsn4-dre textmode 2mb seabios'
| * Create 1,2mb Coreboot configs/targets for KFSN4-DREAndrew Robbins2018-10-206-0/+22
| | | | | | | | | | | | | | | | 1MiB flash is the default for this board but can be upgraded to 2MiB, thus the inclusion of the 2MiB config. KFSN4-DRE Coreboot ROMs can be built with, e.g.: './libreboot build coreboot kfsn4-dre textmode 2mb'
| * Create KFSN4-DRE corebootfb/textmode Coreboot targetsAndrew Robbins2018-10-203-0/+6
|/ | | | | | | | | | | | | | | The corebootfb ROM will use Coreboot's framebuffer for display while the textmode ROM will use the legacy VGA text mode which is necessary for payloads such as Memtest86+. Options (and their values) changed in the new corebootfb config: #CONFIG_VGA_TEXT_FRAMEBUFFER is not set CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y CONFIG_LINEAR_FRAMEBUFFER=y KFSN4-DRE Coreboot ROMs can now be built with './libreboot build coreboot kfsn4-dre corebootfb' or './libreboot build coreboot kfsn4-dre textmode', respectively.
* Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-2010-0/+20
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| * Create SeaBIOS/GRUB targets for KGPE-D16 CorebootAndrew Robbins2018-10-206-0/+8
| | | | | | | | | | | | | | KGPE-D16 ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot kgpe-d16 textmode 2mb seabios'
| * Create 2mb,16mb Coreboot configs/targets for KGPE-D16Andrew Robbins2018-10-204-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. The 16mb target is included as an example. KGPE-D16 Coreboot ROMs can be built with, e.g.: './libreboot build coreboot kgpe-d16 textmode 2mb'
* | Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-1921-0/+44
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| * Create SeaBIOS/GRUB targets for Macbook2,1 CorebootAndrew Robbins2018-10-1812-0/+16
| | | | | | | | | | | | | | Macbook2,1 ROM can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot macbook21 textmode 2mb seabios'
| * Create 2mb,16mb Coreboot configs/targets for Macbook2,1Andrew Robbins2018-10-186-0/+22
| | | | | | | | | | | | | | The 16mb target is included as an example. Macbook2,1 Coreboot ROMs can be built with, e.g.: './libreboot build coreboot macbook21 corebootfb 2mb'
| * Create Macbook2,1 corebootfb/textmode Coreboot targetsAndrew Robbins2018-10-183-0/+6
|/ | | | | | | | | | | | | | | The corebootfb ROM will use Coreboot's framebuffer for display while the textmode ROM will use the legacy VGA text mode which is necessary for payloads such as Memtest86+. Options (and their values) changed in the new corebootfb config: #CONFIG_VGA_TEXT_FRAMEBUFFER is not set CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y CONFIG_LINEAR_FRAMEBUFFER=y Macbook2,1 Coreboot ROMs can now be built with './libreboot build coreboot macbook21 corebootfb' or './libreboot build coreboot macbook21 textmode', respectively.
* Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-1921-0/+44
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| * Create SeaBIOS/GRUB targets for T60 CorebootAndrew Robbins2018-10-1812-0/+16
| | | | | | | | | | | | | | T60 ROM can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot t60 textmode 2mb seabios'
| * Create 2mb,16mb Coreboot configs/targets for T60Andrew Robbins2018-10-186-0/+22
| | | | | | | | | | | | | | The 16mb target is included as an example. T60 Coreboot ROMs can be built with, e.g.: './libreboot build coreboot t60 corebootfb 2mb'
| * Create T60 corebootfb/textmode Coreboot targetsAndrew Robbins2018-10-183-0/+6
|/ | | | | | | | | | | | | | | The corebootfb ROM will use Coreboot's framebuffer for display while the textmode ROM will use the legacy VGA text mode which is necessary for payloads such as Memtest86+. Options (and their values) changed in the new corebootfb config: #CONFIG_VGA_TEXT_FRAMEBUFFER is not set CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y CONFIG_LINEAR_FRAMEBUFFER=y T60 Coreboot ROMs can now be built with './libreboot build coreboot t60 corebootfb' or './libreboot build coreboot t60 textmode', respectively.
* Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-1721-0/+44
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| * Create SeaBIOS/GRUB targets for X60 CorebootAndrew Robbins2018-10-1612-0/+16
| | | | | | | | | | | | | | X60 ROM can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot x60 textmode 2mb seabios'
| * Create 2mb,16mb Coreboot configs/targets for X60Andrew Robbins2018-10-166-0/+22
| | | | | | | | | | | | | | | | | | | | | | These configurations will be read and supplied to make as command-line arguments and override those defined in the config at projects/coreboot/configs/x60/config The 16mb target is included as an example. X60 Coreboot ROMs can be built with, e.g.: './libreboot build coreboot x60 corebootfb 2mb'
| * Create X60 corebootfb/textmode Coreboot targetsAndrew Robbins2018-10-163-0/+6
|/ | | | | | | | | | | | | | | The corebootfb ROM will use Coreboot's framebuffer for display while the textmode ROM will use the legacy VGA text mode which is necessary for payloads such as Memtest86+. Options (and their values) changed in the new corebootfb config: #CONFIG_VGA_TEXT_FRAMEBUFFER is not set CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y CONFIG_LINEAR_FRAMEBUFFER=y X60 Coreboot ROMs can now be built with './libreboot build coreboot x60 corebootfb' or './libreboot build coreboot x60 textmode', respectively.
* Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-1737-1266/+76
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| * Test $variant_config_path and load config if non-nullAndrew Robbins2018-10-161-1/+3
| | | | | | | | | | This avoids an error being printed about a non-existent path when building Coreboot for boards without variants.
| * Remove obsolete x200_*mb Coreboot project targetsAndrew Robbins2018-10-167-1896/+0
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| * Create SeaBIOS/GRUB targets for X200 CorebootAndrew Robbins2018-10-1618-0/+24
| | | | | | | | | | | | | | X200 can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot x200 textmode 16mb seabios'
| * Create 4,8,16mb Coreboot configs/targets for X200Andrew Robbins2018-10-168-0/+42
| | | | | | | | | | | | | | | | | | These configurations will be read and supplied to make as command-line arguments and override those defined in the config at projects/coreboot/configs/x200/config X200 Coreboot ROMs can be built with, e.g.: './libreboot build coreboot x200 corebootfb 8mb'
| * Create X200 corebootfb/textmode Coreboot targetsAndrew Robbins2018-10-163-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The corebootfb ROM will use Coreboot's framebuffer for display while the textmode ROM will use the legacy VGA text mode which is necessary for payloads such as Memtest86+. Options (and their values) changed in the new corebootfb config: CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y CONFIG_LINEAR_FRAMEBUFFER=y X200 Coreboot ROMs can now be built with './libreboot build coreboot x200 corebootfb' or './libreboot build coreboot x200 textmode', respectively.
| * Create x200 Coreboot targetAndrew Robbins2018-10-163-0/+632
|/ | | | | The 8mb X200 config from projects/coreboot/configs/x200_8mb/config is used as the base config for the x200 target.
* Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-1721-1262/+657
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| * Create SeaBIOS/GRUB targets for T400 CorebootAndrew Robbins2018-10-1618-0/+24
| | | | | | | | | | | | | | T400 (and variants) can now be built with either SeaBIOS or GRUB as default payloads, e.g.: './libreboot build coreboot t400 textmode 16mb seabios'
generated by cgit v1.2.3-70-g09d2 (git 2.47.1) at 2024-12-22 07:32:01 +0000