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* Veyron Speedy: use proper binary prefix for flash sizeAndrew Robbins2019-03-0511-2/+2
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* X200: use proper binary prefix for flash sizeAndrew Robbins2019-03-0543-3/+3
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* X60: use proper binary prefix for flash sizeAndrew Robbins2019-03-0529-2/+2
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* Z61t: use proper binary prefix for flash sizeAndrew Robbins2019-03-0515-2/+2
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* Declare project dependencies for coreboot depthcharge targetsAndrew Robbins2019-01-2211-0/+11
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* Declare project dependencies for coreboot seabios targetsAndrew Robbins2019-01-2243-0/+43
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* Declare project dependencies for coreboot grub targetsAndrew Robbins2019-01-2242-0/+42
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* Declare minimum project dependencies for all boardsAndrew Robbins2019-01-2216-0/+20
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* Support declaring dependencies for coreboot targetsAndrew Robbins2019-01-221-0/+1
| | | | | | | | | | | Projects listed in projects/coreboot/configs/dependencies are the minimum required by all boards. Dependencies required by a target in addition to those specified in parent dependencies files may be declared in the target's directory, e.g: projects/coreboot/configs/x200/dependencies
* Restructure Z61t coreboot target directoriesAndrew Robbins2019-01-1412-3/+4
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure X60 coreboot target directoriesAndrew Robbins2019-01-1425-15/+10
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure X200 coreboot target directoriesAndrew Robbins2019-01-1436-26/+17
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure Veyron Speedy coreboot target directoriesAndrew Robbins2019-01-1410-3/+4
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure Veyron Minnie coreboot target directoriesAndrew Robbins2019-01-1410-3/+4
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure Veyron Mickey coreboot target directoriesAndrew Robbins2019-01-146-2/+2
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure Veyron Jerry coreboot target directoriesAndrew Robbins2019-01-1410-3/+4
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure T60 coreboot target directoriesAndrew Robbins2019-01-1425-15/+10
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure T400 coreboot target directoriesAndrew Robbins2019-01-1436-26/+17
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure Nyan Blaze coreboot target directoriesAndrew Robbins2019-01-1410-3/+4
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure Nyan Big coreboot target directoriesAndrew Robbins2019-01-1410-3/+4
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure Macbook2,1 coreboot target directoriesAndrew Robbins2019-01-1425-15/+10
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure KGPE-D16 coreboot target directoriesAndrew Robbins2019-01-1412-3/+4
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure KFSN4-DRE coreboot target directoriesAndrew Robbins2019-01-1425-15/+10
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure KCMA-D8 coreboot target directoriesAndrew Robbins2019-01-1412-3/+4
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure GA-G41M-ES2L coreboot target directoriesAndrew Robbins2019-01-1425-15/+10
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure D945GCLF coreboot target directoriesAndrew Robbins2019-01-1415-0/+3
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Restructure D510MO coreboot target directoriesAndrew Robbins2019-01-1412-3/+4
| | | | | | | | The intent is to create a simple rule of thumb where arguments are given beginning with those that relate to the device's physical attributes, such as flash chip size, continuing with arguments on how to use the hardware (e.g. display mode), and ending with anything else.
* Create SeaBIOS/GRUB targets for D945GCLF corebootAndrew Robbins2019-01-123-0/+4
| | | | | | | D945GCLF ROMs can now be built with either SeaBIOS or GRUB as a default payload for use with a 1MiB flash, e.g.: './libreboot build coreboot d945gclf textmode 1mb seabios'
* Create 1MiB coreboot config/target for D945GCLFAndrew Robbins2019-01-122-0/+6
| | | | | | | | | Previously it was thought that only boards with 512KiB flash chips were produced but JohnMH (in #libreboot) ran across one with an SST25LF080A 1MiB flash. D945GCLF Coreboot ROMs can be built with, e.g.: './libreboot build coreboot d945gclf textmode 1mb'
* Bump coreboot revision to pull in buildgcc v1.53Andrew Robbins2018-12-071-1/+1
| | | | | | | The revision currently used has an issue building crossgcc due to a libelf bug. Upstream no longer depends on libelf when building crossgcc (since afda56e1ad8719a1) so using a more recent revision sidesteps this issue.
* Amend path to SeaBIOS payload in coreboot configsAndrew Robbins2018-11-2456-56/+56
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* Create SeaBIOS/GRUB targets for Z61t corebootAndrew Robbins2018-11-166-0/+8
| | | | | | | Z61t ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot z61t textmode 2mb seabios'
* Create 2,16MiB Coreboot configs/targets for Z61tAndrew Robbins2018-11-164-0/+12
| | | | | | | | | | | | | | 2MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Z61t Coreboot ROMs can be built with, e.g.: './libreboot build coreboot z61t textmode 2mb'
* Add Z61t coreboot targetAndrew Robbins2018-11-163-0/+676
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* Add iMac5,2 as MacBook2,1 variantAndrew Robbins2018-11-164-0/+9
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* Create Coreboot Depthcharge target for Veyron SpeedyAndrew Robbins2018-10-304-0/+4
| | | | | | | Veyron Speedy ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron speedy corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Veyron SpeedyAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Speedy Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron speedy corebootfb 4mb'
* Correct CBFS_SIZE in Veyron Speedy Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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* Create Coreboot Depthcharge target for Veyron MinnieAndrew Robbins2018-10-304-0/+4
| | | | | | | Veyron Minnie ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron minnie corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Veyron MinnieAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Minnie Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron minnie corebootfb 4mb'
* Correct CBFS_SIZE in Veyron Minnie Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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* Create Coreboot Depthcharge target for Veyron MickeyAndrew Robbins2018-10-302-0/+2
| | | | | | | Veyron Mickey ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron mickey corebootfb 4mb depthcharge'
* Create 4MiB Coreboot config/target for Veyron MickeyAndrew Robbins2018-10-303-0/+6
| | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is not included (yet) as I was unable to find a teardown of this device (Asus Chromebit CS10) online to be sure that reassembly is possible. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Mickey Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron mickey corebootfb 4mb'
* Create Coreboot Depthcharge target for Veyron JerryAndrew Robbins2018-10-304-0/+4
| | | | | | | Veyron Jerry ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron jerry corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Veyron JerryAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Jerry Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron jerry corebootfb 4mb'
* Correct CBFS_SIZE in Veyron Jerry Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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* Create Coreboot Depthcharge target for Nyan BlazeAndrew Robbins2018-10-294-0/+4
| | | | | | | Nyan Blaze ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot nyan blaze corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Nyan BlazeAndrew Robbins2018-10-294-0/+12
| | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Nyan Blaze Coreboot ROMs can be built with, e.g.: './libreboot build coreboot nyan blaze corebootfb 4mb'
* Create Coreboot Depthcharge target for Nyan BigAndrew Robbins2018-10-294-0/+4
| | | | | | Nyan Big ROMs are built with Depthcharge as its default payload, e.g.: './libreboot build coreboot nyan big corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Nyan BigAndrew Robbins2018-10-294-0/+12
| | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Nyan Big Coreboot ROMs can be built with, e.g.: './libreboot build coreboot nyan big corebootfb 4mb'
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