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* Update Coreboot config for board x60Andrew Robbins2018-01-141-103/+210
| | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * VGA_TEXT_FRAMEBUFFER=y * UART_PCI_ADDR=0x0
* Update Coreboot config for board x200_8mbAndrew Robbins2018-01-141-62/+147
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board x200_4mbAndrew Robbins2018-01-141-62/+147
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board x200_16mbAndrew Robbins2018-01-141-62/+147
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board w500_8mbAndrew Robbins2018-01-141-74/+156
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board w500_4mbAndrew Robbins2018-01-141-74/+156
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board w500_16mbAndrew Robbins2018-01-141-74/+156
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board t60Andrew Robbins2018-01-141-101/+208
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * VGA_TEXT_FRAMEBUFFER=y * UART_PCI_ADDR=0x0 Previously configured options which were changed with this commit: * LOCALVERSION=""
* Update Coreboot config for board t500_8mbAndrew Robbins2018-01-141-73/+155
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board t500_4mbAndrew Robbins2018-01-141-73/+155
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board t500_16mbAndrew Robbins2018-01-141-73/+155
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board t400_8mbAndrew Robbins2018-01-141-73/+155
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board t400_4mbAndrew Robbins2018-01-141-73/+155
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board t400_16mbAndrew Robbins2018-01-141-73/+155
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board r400_8mbAndrew Robbins2018-01-141-73/+155
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board r400_4mbAndrew Robbins2018-01-141-73/+155
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_4m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board r400_16mbAndrew Robbins2018-01-141-73/+155
| | | | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * H8_BEEP_ON_DEATH=y * H8_FLASH_LEDS_ON_DEATH=y * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_16m.bin" * VGA_TEXT_FRAMEBUFFER=y The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board qemu_q35_ich9Andrew Robbins2018-01-141-94/+183
| | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * HAVE_IFD_BIN=y * IFD_BIN_PATH="$(obj)/../ich9gen/ich9fdgbe_8m.bin" * VGA_TEXT_FRAMEBUFFER=y * UART_PCI_ADDR=0x0 The Intel Firmware Descriptor (IFD) will be generated by ich9gen in Libreboot's new build system.
* Update Coreboot config for board qemu_i440fx_piix4Andrew Robbins2018-01-141-89/+167
| | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * VGA_TEXT_FRAMEBUFFER=y * UART_PCI_ADDR=0x0
* Update Coreboot config for board macbook2,1Andrew Robbins2018-01-141-101/+201
| | | | | | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * VGA_TEXT_FRAMEBUFFER=y * UART_PCI_ADDR=0x0 Previously configured options which were changed with this commit: * LOCALVERSION=""
* Update Coreboot config for board kgpe-d16Andrew Robbins2018-01-141-71/+146
| | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * SOUTHBRIDGE_AMD_SB700_33MHZ_SPI=y * UART_PCI_ADDR=0x0
* Update Coreboot config for board kfsn4-dreAndrew Robbins2018-01-141-87/+173
| | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * VGA_TEXT_FRAMEBUFFER=y * UART_PCI_ADDR=0x0
* Update Coreboot config for board kcma-d8Andrew Robbins2018-01-141-70/+143
| | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * SOUTHBRIDGE_AMD_SB700_33MHZ_SPI=y * UART_PCI_ADDR=0x0
* Update Coreboot config for board ga-g41m-es2lAndrew Robbins2018-01-141-72/+160
| | | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * VGA_TEXT_FRAMEBUFFER=y * REALTEK_8168_MACADDRESS="00:f5:f0:40:71:fe"
* Update Coreboot config for board d945gclfAndrew Robbins2018-01-121-77/+152
| | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y
* Update Coreboot config for board d510moAndrew Robbins2018-01-121-95/+217
| | | | | | | | | | This config was updated using Coreboot's 'oldconfig' make target. New configuration options enabled with this commit: * ENABLE_VMX=y * SET_VMX_LOCK_BIT=y * UART_PCI_ADDR=0x0
* Delete board-specific Coreboot revision filesAndrew Robbins2017-12-2226-26/+0
| | | | | | | Testing needs to be done on the revision specified at 'projects/coreboot/configs/revision', thus all board-specific revision files should be removed in order to avoid checking out an older commit in the meantime.
* Bump Coreboot revision to current upstream HEADAndrew Robbins2017-12-211-1/+1
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* Update 'projects/coreboot/configs/seabios/w500_8mb/config'CoreShoe2017-12-051-1/+1
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* Update 'projects/coreboot/configs/seabios/w500_4mb/config'CoreShoe2017-12-051-1/+1
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* Update 'projects/coreboot/configs/seabios/w500_16mb/config'CoreShoe2017-12-051-1/+1
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* Update 'projects/coreboot/configs/seabios/t500_8mb/config'CoreShoe2017-12-051-1/+1
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* Update 'projects/coreboot/configs/seabios/t500_4mb/config'CoreShoe2017-12-051-1/+1
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* Update 'projects/coreboot/configs/seabios/t500_16mb/config'CoreShoe2017-12-051-1/+1
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* Update 'projects/coreboot/configs/seabios/t400_8mb/config'CoreShoe2017-12-051-1/+1
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* Update 'projects/coreboot/configs/seabios/t400_4mb/config'CoreShoe2017-12-051-1/+1
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* Update 'projects/coreboot/configs/seabios/t400_16mb/config'CoreShoe2017-12-051-1/+1
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* Update 'projects/coreboot/configs/seabios/r400_8mb/config'CoreShoe2017-12-051-1/+1
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* Update 'projects/coreboot/configs/seabios/r400_4mb/config'CoreShoe2017-12-051-1/+1
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* Update 'projects/coreboot/configs/seabios/r400_16mb/config'CoreShoe2017-12-051-1/+1
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* Add SeaBIOS target to Coreboot targets fileAndrew Robbins2017-10-011-0/+1
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* Modify payload path in Coreboot configsAndrew Robbins2017-09-1826-26/+26
| | | | | It makes things easier if the makefiles fetch the default payload from its build directory, which should have a stable name.
* Add file listing Coreboot SeaBIOS subtargetsAndrew Robbins2017-09-181-0/+26
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* Delete vbootrevision files in Coreboot target dirsAndrew Robbins2017-09-1826-26/+0
| | | | | There is a separate vboot project, so those revision files related to it should be placed in its configs directory instead.
* Rename Coreboot config files named 'cbrevision'Andrew Robbins2017-09-1826-0/+0
| | | | | The new build system simply uses 'revision' to refer to the git revision that should be used.
* Rename Coreboot config files named 'architecture'Andrew Robbins2017-09-1826-0/+0
| | | | The new build system uses the shortened version: arch
* Copy Coreboot configurations to new build systemAndrew Robbins2017-09-18104-0/+14397
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* Update coreboot and depthcharge revisionsPaul Kocialkowski2017-01-151-1/+1
| | | | Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* Paper build system initial import into LibrebootPaul Kocialkowski2017-01-1521-0/+585
This is the initial import of the Paper build system into Libreboot. It was written as a flexible and painless replacement for the Libreboot build system, allowing to support many different configurations. It currently only supports the following CrOS devices: * Chromebook 13 CB5-311 (nyan big) * Chromebook 14 (nyan blaze) * Chromebook 11 (HiSense) (veyron jerry) * Chromebit CS10 (veyron mickey) * Chromebook Flip C100PA (veyron minnie) * Chromebook C201PA (veyron speedy) The build system also supports building various tools and provides various scripts to ease the installation on CrOS devices. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
generated by cgit v1.2.3-70-g09d2 (git 2.47.0) at 2024-11-05 08:06:14 +0000