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* Bump coreboot revision to pull in buildgcc v1.53Andrew Robbins2018-12-071-1/+1
| | | | | | | The revision currently used has an issue building crossgcc due to a libelf bug. Upstream no longer depends on libelf when building crossgcc (since afda56e1ad8719a1) so using a more recent revision sidesteps this issue.
* Amend path to SeaBIOS payload in coreboot configsAndrew Robbins2018-11-2456-56/+56
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* Place built SeaBIOS files in its build directoryAndrew Robbins2018-11-241-2/+1
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* Consolidate SeaBIOS configsAndrew Robbins2018-11-246-103/+2
| | | | | | | | | | | The only difference between the previous "bios" and "vgabios" targets was whether or not a VGA BIOS binary was built along with SeaBIOS. It seemed needless to compile twice in the event that you want both the SeaBIOS payload and its VGA BIOS when you can compile once and make the decision yourself whether to use the produced vgabios.bin
* Bump SeaBIOS revision and update configsAndrew Robbins2018-11-243-1/+5
| | | | | | New options enabled (set to their default values): CONFIG_NVME=y CONFIG_SERCON=y
* Merge branch 'new-boards' of and_who/libreboot into masterSwift Geek2018-11-2416-0/+705
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| * Create SeaBIOS/GRUB targets for Z61t corebootAndrew Robbins2018-11-166-0/+8
| | | | | | | | | | | | | | Z61t ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot z61t textmode 2mb seabios'
| * Create 2,16MiB Coreboot configs/targets for Z61tAndrew Robbins2018-11-164-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 2MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Z61t Coreboot ROMs can be built with, e.g.: './libreboot build coreboot z61t textmode 2mb'
| * Add Z61t coreboot targetAndrew Robbins2018-11-163-0/+676
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| * Add iMac5,2 as MacBook2,1 variantAndrew Robbins2018-11-164-0/+9
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* | Add function depthcharge_libpayload_build_path()Andrew Robbins2018-11-222-1/+21
| | | | | | | | | | | | | | | | | | This function will return the correct build path for libpayload built for depthcharge targets nyan and veyron. Without this function, and using project_build_path() instead, LIBPAYLOAD_DIR would be set to "$root/$BUILD/libpayload-depthcharge-nyan-big" instead of the proper "$root/$BUILD/libpayload-depthcharge-nyan", for example.
* | Remove libpayload's veyron subtarget targets fileAndrew Robbins2018-11-221-2/+0
|/ | | | | There's no need to build for each supported veyron model since the libpayload veyron config is just for veyron in general.
* Patch CrOS-EC veyron to avoid compilation errorsAndrew Robbins2018-11-152-0/+94
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* Update CrOS-EC context switching patchAndrew Robbins2018-11-061-80/+100
| | | | This is the final version of the patch which was merged upstream.
* Remove obsolete CrOS-EC Veyron patch for math_util.cAndrew Robbins2018-11-052-29/+0
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* Revert to older CrOS-EC revision for Veyron boardsAndrew Robbins2018-11-051-1/+1
| | | | | Support was removed for Veyron Speedy/Minnie in the more recent revision.
* Revert to older CrOS-EC revision for Nyan boardsAndrew Robbins2018-11-051-1/+1
| | | | Support was removed for Nyan Big/Blaze in the more recent revision.
* Create Coreboot Depthcharge target for Veyron SpeedyAndrew Robbins2018-10-304-0/+4
| | | | | | | Veyron Speedy ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron speedy corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Veyron SpeedyAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Speedy Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron speedy corebootfb 4mb'
* Correct CBFS_SIZE in Veyron Speedy Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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* Create Coreboot Depthcharge target for Veyron MinnieAndrew Robbins2018-10-304-0/+4
| | | | | | | Veyron Minnie ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron minnie corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Veyron MinnieAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Minnie Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron minnie corebootfb 4mb'
* Correct CBFS_SIZE in Veyron Minnie Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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* Create Coreboot Depthcharge target for Veyron MickeyAndrew Robbins2018-10-302-0/+2
| | | | | | | Veyron Mickey ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron mickey corebootfb 4mb depthcharge'
* Create 4MiB Coreboot config/target for Veyron MickeyAndrew Robbins2018-10-303-0/+6
| | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is not included (yet) as I was unable to find a teardown of this device (Asus Chromebit CS10) online to be sure that reassembly is possible. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Mickey Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron mickey corebootfb 4mb'
* Create Coreboot Depthcharge target for Veyron JerryAndrew Robbins2018-10-304-0/+4
| | | | | | | Veyron Jerry ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron jerry corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Veyron JerryAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Jerry Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron jerry corebootfb 4mb'
* Correct CBFS_SIZE in Veyron Jerry Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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* Add Veyron Jerry/Mickey Depthcharge targetsAndrew Robbins2018-10-301-0/+2
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* Create Coreboot Depthcharge target for Nyan BlazeAndrew Robbins2018-10-294-0/+4
| | | | | | | Nyan Blaze ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot nyan blaze corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Nyan BlazeAndrew Robbins2018-10-294-0/+12
| | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Nyan Blaze Coreboot ROMs can be built with, e.g.: './libreboot build coreboot nyan blaze corebootfb 4mb'
* Create Coreboot Depthcharge target for Nyan BigAndrew Robbins2018-10-294-0/+4
| | | | | | Nyan Big ROMs are built with Depthcharge as its default payload, e.g.: './libreboot build coreboot nyan big corebootfb 4mb depthcharge'
* Create 4,16MiB Coreboot configs/targets for Nyan BigAndrew Robbins2018-10-294-0/+12
| | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Nyan Big Coreboot ROMs can be built with, e.g.: './libreboot build coreboot nyan big corebootfb 4mb'
* Add targets file for Nyan Depthcharge targetAndrew Robbins2018-10-291-0/+2
| | | | | Necessary to build Depthcharge for Nyan Big and Nyan Blaze with their respective defconfig.
* Enable additional options in Nyan Blaze configAndrew Robbins2018-10-251-2/+2
| | | | | | Options updated (with new values): CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" # CONFIG_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is not set
* Update Nyan Blaze Coreboot configAndrew Robbins2018-10-251-2/+726
| | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Enable additional options in Nyan Big configAndrew Robbins2018-10-251-3/+3
| | | | | | | Options updated (with new values): CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
* Update Nyan Big Coreboot configAndrew Robbins2018-10-251-2/+731
| | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Enable additional options in Veyron Mickey configAndrew Robbins2018-10-251-4/+4
| | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
* Update Veyron Mickey Coreboot configAndrew Robbins2018-10-251-0/+710
| | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Enable additional options in Veyron Jerry configAndrew Robbins2018-10-251-3/+3
| | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" # CONFIG_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is not set
* Update Veyron Jerry Coreboot configAndrew Robbins2018-10-251-2/+722
| | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Enable additional options in Veyron Speedy configAndrew Robbins2018-10-251-4/+4
| | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
* Update Veyron Speedy Coreboot configAndrew Robbins2018-10-251-2/+727
| | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Enable additional options in Veyron Minnie configAndrew Robbins2018-10-251-4/+4
| | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
* Update Veyron Minnie Coreboot configAndrew Robbins2018-10-251-2/+727
| | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Create SeaBIOS/GRUB targets for D510MO CorebootAndrew Robbins2018-10-226-0/+8
| | | | | | | D510MO ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot d510mo textmode 1mb seabios'
* Create 1,16MiB Coreboot configs/targets for D510MOAndrew Robbins2018-10-224-0/+12
| | | | | | | | | | | | | | 1MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. D510MO Coreboot ROMs can be built with, e.g.: './libreboot build coreboot d510mo textmode 1mb'
* Create SeaBIOS/GRUB targets for D945GCLF CorebootAndrew Robbins2018-10-215-0/+6
| | | | | | | | | | | Due to the limited flash space on the board, SeaBIOS is currently the sole payload option when building 512KiB-sized ROMs. D945GCLF ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot d945gclf textmode 512kb seabios', or './libreboot build coreboot d945gclf textmode 16mb grub'
* Create 512KiB,16MiB Coreboot configs/targets for D945GCLFAndrew Robbins2018-10-213-0/+11
| | | | | | | | | | | | | | 512KiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. D945GCLF Coreboot ROMs can be built with, e.g.: './libreboot build coreboot d945gclf textmode 512kb'
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