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This time under her chosen name.
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Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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Use NPROC=foo
Replace "foo" with a number. By default, the build system uses $(nproc).
This patch allows the user to specify any number of cores. This is useful
on some systems, or certain chroot environments.
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This will speed up the build process. The plan is to, if possible,
always use 1 revision.
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The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.
At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.
Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.
For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.
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We now tell coreboot's build system what version string to use.
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This is one of the things needed, for building coreboot in a
reproducible fashion.
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Not all CrOS devices are Chromebooks (laptops) or run on ARM, not all RK3288
CrOS devices are Chromebooks, either.
We want to support more CrOS devices, including some that are not Chromebooks,
such as the ASUS Chromebit!
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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This introduces Libreboot support for the Asus Chromebook C201 (codename
veyron_speedy). At this point, this produces a standalone Libreboot image that
can be flashed to the RO Coreboot partition of the SPI flash, as well as the
Libreboot version that can be flash to the RO Firmware ID partition.
Libreboot on the Chromebook C201 uses the depthcharge bootloader, modified to
display text messages instead of ChromeOS bitmaps (that encourage the use of
ChromeOS).
For convenience, an installation script, chromebook-flash-replace, is provided
along with a description of the flash layout, to ease the replacement of the
Coreboot and RO Firmware ID partitions on the full SPI flash image.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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