From 59201912928ffcdbc4c7143548ceba490dea021a Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Mon, 1 Jun 2015 20:35:42 -0500 Subject: [PATCH 038/146] amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup on Fam15h --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index c73cb26..3eb6b17 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1839,11 +1839,13 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, if (nv_DQSTrainCTL) { mctHookBeforeAnyTraining(pMCTstat, pDCTstatA); - /* TODO: should be in mctHookBeforeAnyTraining */ - _WRMSR(0x26C, 0x04040404, 0x04040404); - _WRMSR(0x26D, 0x04040404, 0x04040404); - _WRMSR(0x26E, 0x04040404, 0x04040404); - _WRMSR(0x26F, 0x04040404, 0x04040404); + if (!is_fam15h()) { + /* TODO: should be in mctHookBeforeAnyTraining */ + _WRMSR(0x26C, 0x04040404, 0x04040404); + _WRMSR(0x26D, 0x04040404, 0x04040404); + _WRMSR(0x26E, 0x04040404, 0x04040404); + _WRMSR(0x26F, 0x04040404, 0x04040404); + } mct_WriteLevelization_HW(pMCTstat, pDCTstatA, FirstPass); if (is_fam15h()) { -- 1.7.9.5