diff options
| author | Francis Rowe <info@gluglug.org.uk> | 2014-11-28 10:07:04 +0000 |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2014-12-11 23:23:16 +0000 |
| commit | 137aee12fb6f8c2c682268c6894110d486c12caa (patch) | |
| tree | 4237b42d1978e163caa4491b6a80f5e7a1092e40 | |
| parent | e1839b53737ba6058a864fcc6d1c50f5784c9866 (diff) | |
| download | librebootfr-137aee12fb6f8c2c682268c6894110d486c12caa.tar.gz librebootfr-137aee12fb6f8c2c682268c6894110d486c12caa.zip | |
ThinkPad X200 support added to libreboot
36 files changed, 5270 insertions, 102 deletions
@@ -10,3 +10,7 @@ /powertop/ /libreboot_src.tar.xz /libreboot_bin.tar.xz +/resources/utilities/ich9deblob/factory.rom +/resources/utilities/ich9deblob/deblobbed_descriptor.bin +/resources/utilities/ich9deblob/libreboot.rom +/resources/utilities/ich9deblob/ich9deblob diff --git a/addseabios b/addseabios deleted file mode 100755 index 1cc1aad3..00000000 --- a/addseabios +++ /dev/null @@ -1,83 +0,0 @@ -#!/bin/bash - -# addseabios script: add SeaBIOS to the ROM images. -# This also adds SeaVGABIOS, SeaBIOS's free/libre video bios "wrapper" for coreboot native graphics -# -# Copyright (C) 2014 Francis Rowe <info@gluglug.org.uk> -# -# This program is free software: you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation, either version 3 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program. If not, see <http://www.gnu.org/licenses/>. -# - -set -u -e -v - -echo "Adding SeaBIOS and SeaVGABIOS to the ROM's" - -# Because the DEBLOB script isn't included in the binary archives. -# This is how we know. -if [ -f "DEBLOB" ]; then - echo "Do not run this in meta/src directory. Do it in binary archive, either with libreboot-supplied ROM images or your own binary archive created with 'build-release'." - exit 1 -fi - -if [ $(uname -i) = "i686" ] || [ $(uname -i) = "i686" ] - then - echo "You are on an i686 host" - if [ ! -f "cbfstool/i686/cbfstool" ]; then - echo "cbfstool binary not found. You will need to build it from source and put it in cbfstool/i686/" - exit 1 - fi - $cbfstool = "../cbfstool/i686/cbfstool" -elif [ $(uname -i) = "x86_64" ] || [ $(uname -i) = "x86_64" ] - then - echo "You are on an x86_64 host" - if [ ! -f "cbfstool/x86_64/cbfstool" ]; then - echo "cbfstool binary not found. You will need to build it from source and put it in cbfstool/x86_64/" - exit 1 - fi - $cbfstool = "../cbfstool/x86_64/cbfstool" -else - echo "You need to run this script on an i686 or x86_64 host" - exit 1 -fi - -# Add SeaBIOS and SeaVGABIOS to *all* ROM's -cd bin/ -for rom in $(find -type f) -do - # Add them - $cbfstool $rom add -f ../vgabios.bin -n vgaroms/vgabios.bin -t raw - $cbfstool $rom add -f ../bios.bin.elf -n bios.bin.elf -t raw - - # Modify the GRUB configuration - for config in grub.cfg grubtest.cfg - do - # Extract (dump) the config - $cbfstool $rom extract -n $config -f $config - - # Delete it from the ROM - $cbfstool $rom remove -n $config - - # Add the menuentry for loading SeaBIOS - cat seabios.cfg >> $config - - # Re-add the newly modified GRUB configuration to the ROM - $cbfstool $rom add -f $config -n $config -t raw - - # The GRUB configuration is no longer needed - rm -rf $config - done -done -cd ../ - -echo "DONE! All of the ROM's under bin/ have been modified to include SeaBIOS/SeaVGABIOS and include a GRUB menuentry for it." @@ -52,7 +52,7 @@ done cd ../ # Build ROM images for supported boards -for board in x60 t60 x60t macbook21 +for board in x60 x60t t60 x200_4mb x200_8mb macbook21 do ./buildrom-withgrub $board done diff --git a/build-release b/build-release index 4c47b5d4..0d676a50 100755 --- a/build-release +++ b/build-release @@ -198,7 +198,7 @@ mv flashrom_ flashrom # build cbfstool, compiled (statically linked) and include the binary cd coreboot/util/ cp -r cbfstool cbfstool_ -cd cbfstool +cd cbfstool/ make clean make SHARED=0 CC='gcc -static' mkdir ../../../libreboot_bin/cbfstool @@ -226,6 +226,36 @@ rm -rf cbfstool mv cbfstool_ cbfstool cd ../../ +# ---------------- +# ich9deblob related +# ---------------- +# build ich9deblob, compiled (statically linked) and include the binary +cd resources/utilities/ +cp -r ich9deblob ich9deblob_ +cd ich9deblob/ +rm -f ich9deblob +gcc -static -o ich9deblob ich9deblob.c ich9desc.c -I. +mkdir ../../../libreboot_bin/ich9deblob +if [ $(uname -i) = "i686" ] || [ $(uname -m) = "i686" ] + then + # User is building on 32-bit host. Build only 32-bit binaries + mkdir ../../../libreboot_bin/ich9deblob/i686 + mv ich9deblob ../../../libreboot_bin/ich9deblob/i686/ +elif [ $(uname -i) = "x86_64" ] || $(uname -m) = "x86_64" + then + # Build the 64-bit binaries + mkdir ../../../libreboot_bin/ich9deblob/x86_64 + mv ich9deblob ../../../libreboot_bin/ich9deblob/x86_64/ + # Now build 32-bit binaries + gcc -static -m32 -o ich9deblob ich9deblob.c ich9desc.c -I. + mkdir ../../../libreboot_bin/ich9deblob/i686 + mv ich9deblob ../../../libreboot_bin/ich9deblob/i686/ +fi +cd ../ +rm -rf ich9deblob +mv ich9deblob_ ich9deblob +cd ../../ + # ----------------- # nvramtool related # ----------------- @@ -18,10 +18,6 @@ # along with this program. If not, see <http://www.gnu.org/licenses/>. # -# MAKE SURE THAT YOU RAN "./builddeb" BEFORE RUNNING THIS! -# IF YOUR DISTRO DOESN'T USE "apt-get", ADAPT WHAT YOU SEE IN "builddeb" -# AND INSTALL THE BUILD DEPENDENCIES NEEDED TO RUN THIS BUILD SCRIPT! - set -u -e -v # Clean old builds first: @@ -60,6 +60,11 @@ set -u -e -v ./builddeps-i945pwm +# Build ich9deblob utility +# -------------------------------------------------------------------- + +./builddeps-ich9deblob + # ------------------- DONE ---------------------- diff --git a/builddeps-bucts b/builddeps-bucts index 7a11a3c1..ead751ba 100755 --- a/builddeps-bucts +++ b/builddeps-bucts @@ -21,11 +21,6 @@ # This script is used by the main "builddeps" script in libreboot src/meta archives. # The reason it is seperated here is so that bucts can be built separately aswell. -# To build bucts, you will need the dependencies in "builddeb". -# Run it, or adapt it if you do not use an "apt-get" distro. - -# "getbucts" script also makes use of this script. - set -u -e -v # Build BUC.TS utility (needed for flashing ROM's on X60/T60 while Lenovo BIOS is running) diff --git a/builddeps-coreboot b/builddeps-coreboot index 6b5794f3..d70c7984 100755 --- a/builddeps-coreboot +++ b/builddeps-coreboot @@ -21,11 +21,6 @@ # This script is used by the main "builddeps" script in libreboot src/meta archives. # The reason it is seperated here is so that coreboot can be built separately aswell. -# To use this script, you will need the dependencies in "builddeb". -# Run it, or adapt it if you do not use an "apt-get" distro. - -# This is also used by the "getcb" script. - set -u -e -v # Build utilities needed in coreboot directory diff --git a/builddeps-ich9deblob b/builddeps-ich9deblob new file mode 100755 index 00000000..506462a3 --- /dev/null +++ b/builddeps-ich9deblob @@ -0,0 +1,40 @@ +#!/bin/bash + +# builddeps-ich9deblob: builds ich9deblob source code +# +# Copyright (C) 2014 Francis Rowe <info@gluglug.org.uk> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +# This script is used by the main "builddeps" script in libreboot src/meta archives. +# The reason it is seperated here is so that ich9deblob can be built separately aswell. + +set -u -e -v + +# Build ich9deblob utility +# -------------------------------------------------------------------- + +cd resources/utilities/ich9deblob + +# clean it first +rm -f ich9deblob + +# build ich9deblob +gcc -o ich9deblob ich9deblob.c ich9desc.c -I. + +# done. go back to main directory +cd ../../../ + +# ------------------- DONE ---------------------- @@ -119,6 +119,11 @@ cd ../ rm -f resources/utilities/i945-pwm/i945-pwm +# clean ich9deblob utility +# -------------------------------------------------------------------- + +rm -f resources/utilities/ich9deblob/ich9deblob + # a few more things to do last # -------------------------------------------------------- diff --git a/docs/git/index.html b/docs/git/index.html index 5aa38b4b..c3286b9b 100644 --- a/docs/git/index.html +++ b/docs/git/index.html @@ -33,6 +33,7 @@ <li><a href="#config_x60">ThinkPad X60</a></li> <li><a href="#config_x60t">ThinkPad X60 Tablet</a></li> <li><a href="#config_t60">ThinkPad T60</a></li> + <li><a href="#config_x200">ThinkPad X200</a></li> <li><a href="#config_macbook21">MacBook2,1</a></li> </ul> </li> @@ -384,6 +385,48 @@ It is believed that the motherboards on 14.1" and 15.1" T60's are the same, so the same configuration is used on both the 14.1" and 15.1" T60's. </p> + + <h2 id="config_x200"> + ThinkPad X200 configuration (file: resources/libreboot/config/x200_4mb/config and resources/libreboot/config/x200_8mb/config) + </h2> + <p> + These are saved as two configs, because there are 2 size flash chips: 4MB or 8MB. + </p> + <ul> + <li>General / Expert mode = <i>enable</i></li> + <li>Mainboard / Mainboard vendor = <i>Lenovo</i></li> + <li>Mainboard / Mainboard model = <i>ThinkPad X200</i></li> + <li>Mainboard / ROM chip size = <i>4096 KB (4 MB)</i> or <i>8192 KB (8 MB)</i> depending on flash chip size</li> + <li>Chipset / Include CPU microcode in CBFS = <i>Do not include microcode updates</i></li> + <li>Chipset / Size of CBFS filesystem in ROM = byte size <i>0x7FD000</i> (for 8MB flash chip) or <i>3FD000</i> (for 4MB flash chip)</li> + <li>Devices / Use native graphics initialization = <i>enable</i></li> + <li> + Display / Keep VESA framebuffer = <i>disable</i> (disable for text-mode graphics, enable for coreboot vesa framebuffer) + <ul> + <li>Libreboot provides this with text-mode enabled by default, but it automatically patches a copy of the config at build time + to enable coreboot framebuffer for a separate set of ROM images, in each machine.</li> + </ul> + </li> + <li>Generic Drivers / USB 2.0 EHCI debug dongle support = <i>Enable</i></li> + <li>Generic Drivers / Enable early (pre-RAM) usbdebug = <i>Enable</i></li> + <li>Generic Drivers / Type of dongle = <i>BeagleBone Black</i></li> + <li>Console / Send console output to a CBMEM buffer = <i>enable</i></li> + <li>Console / USB dongle log output = <i>enable</i></li> + <li>Payload / Add a payload = <i>An ELF executable payload</i></li> + <li>Payload / Payload path and filename = <i>grub.elf</i></li> + </ul> + <p> + Go back and disable option ROM's: + </p> + <ul> + <li>Devices / Run VGA Option ROMs = <i>disable</i></li> + <li>Devices / Run Option ROMs on PCI devices = <i>disable</i></li> + </ul> + <p> + The resulting .config file was saved as resources/libreboot/config/<b>x200_8mb/config</b> and + resources/libreboot/config/<b>x200_4mb/config</b> and is used by the build + scripts for this machine. + </p> <h2 id="config_macbook21"> MacBook2,1 configuration (file: resources/libreboot/config/macbook21/config) @@ -475,11 +518,11 @@ <p> If you are building on an i686 host, this will include statically linked 32-bit binaries in the binary release archive that you created, - for: <b>nvramtool, cbfstool, bucts, flashrom</b>. + for: <b>nvramtool, cbfstool, bucts, flashrom, ich9deblob</b>. </p> <p> - If you are building on an x86_64 host, this will include statically linked 32- and 64-bit binaries for <b>cbfstool</b> and <b>nvramtool</b>, while <b>flashrom</b> + If you are building on an x86_64 host, this will include statically linked 32- and 64-bit binaries for <b>ich9deblob</b>, <b>cbfstool</b> and <b>nvramtool</b>, while <b>flashrom</b> and <b>bucts</b> will be included only as 64-bit statically linked binaries. <b>To include a statically linked flashrom and bucts for i686, you will need to build them on a chroot, a virtual machine or a real 32-bit system. You can find the build dependencies for these packages listed in deps-*</b> </p> diff --git a/docs/hcl/images/x200/gpio33_location.jpg b/docs/hcl/images/x200/gpio33_location.jpg Binary files differnew file mode 100644 index 00000000..417ae288 --- /dev/null +++ b/docs/hcl/images/x200/gpio33_location.jpg diff --git a/docs/hcl/index.html b/docs/hcl/index.html index 3ffaea8d..429f1251 100644 --- a/docs/hcl/index.html +++ b/docs/hcl/index.html @@ -26,6 +26,7 @@ <li><a href="#supported_x60_list">List of supported ThinkPad X60/X60s</a></li> <li><a href="#supported_x60t_list">List of supported ThinkPad X60 Tablets</a></li> <li><a href="#supported_t60_list">List of supported ThinkPad T60's</a></li> + <li><a href="x200.html">List of supported ThinkPad X200's</a></li> <li><a href="#t60_ati_intel">ThinkPad T60 (ATI GPU) and ThinkPad T60 (Intel GPU) differences.</a></li> <li><a href="#macbook11">Information about the Macbook1,1</a></li> <li><a href="#macbook21">Information about the Macbook2,1</a></li> @@ -42,6 +43,7 @@ <li><a href="#supported_x60_list">Lenovo ThinkPad X60/X60s</a></li> <li><a href="#supported_x60t_list">Lenovo ThinkPad X60 Tablet</a></li> <li><a href="#supported_t60_list">Lenovo ThinkPad T60</a> (there are exceptions. see link)</li> + <li><a href="x200.html">Lenovo ThinkPad X200</a></li> <li><a href="#macbook11">Apple MacBook1,1</a></li> <li><a href="#macbook21">Apple MacBook2,1</a></li> </ul> diff --git a/docs/hcl/text/r400/r400_dmidecode.txt b/docs/hcl/text/r400/r400_dmidecode.txt new file mode 100644 index 00000000..0c0ca2a9 --- /dev/null +++ b/docs/hcl/text/r400/r400_dmidecode.txt @@ -0,0 +1,628 @@ +# dmidecode 2.11 +SMBIOS 2.4 present. +74 structures occupying 2511 bytes. +Table at 0x000E0010. + +Handle 0x0000, DMI type 0, 24 bytes +BIOS Information + Vendor: LENOVO + Version: 7UET48WW (1.18 ) + Release Date: 10/09/2008 + Address: 0xE0000 + Runtime Size: 128 kB + ROM Size: 8192 kB + Characteristics: + PCI is supported + PC Card (PCMCIA) is supported + PNP is supported + BIOS is upgradeable + BIOS shadowing is allowed + ESCD support is available + Boot from CD is supported + Selectable boot is supported + BIOS ROM is socketed + EDD is supported + ACPI is supported + USB legacy is supported + BIOS boot specification is supported + Targeted content distribution is supported + BIOS Revision: 1.24 + Firmware Revision: 1.1 + +Handle 0x0001, DMI type 1, 27 bytes +System Information + Manufacturer: LENOVO + Product Name: 7439W3Q + Version: ThinkPad R400 + Serial Number: L3ACC2H + UUID: 85D49681-4A1D-11CB-B11C-ACDC80D4983E + Wake-up Type: Power Switch + SKU Number: Not Specified + Family: ThinkPad R400 + +Handle 0x0002, DMI type 2, 8 bytes +Base Board Information + Manufacturer: LENOVO + Product Name: 7439W3Q + Version: Not Available + Serial Number: VF22T89V14J + +Handle 0x0003, DMI type 3, 13 bytes +Chassis Information + Manufacturer: LENOVO + Type: Notebook + Lock: Not Present + Version: Not Available + Serial Number: Not Available + Asset Tag: No Asset Information + Boot-up State: Unknown + Power Supply State: Unknown + Thermal State: Unknown + Security Status: Unknown + +Handle 0x0004, DMI type 126, 13 bytes +Inactive + +Handle 0x0005, DMI type 126, 13 bytes +Inactive + +Handle 0x0006, DMI type 4, 35 bytes +Processor Information + Socket Designation: None + Type: Central Processor + Family: Other + Manufacturer: GenuineIntel + ID: 76 06 01 00 FF FB EB BF + Signature: Type 0, Family 6, Model 23, Stepping 6 + Flags: + FPU (Floating-point unit on-chip) + VME (Virtual mode extension) + DE (Debugging extension) + PSE (Page size extension) + TSC (Time stamp counter) + MSR (Model specific registers) + PAE (Physical address extension) + MCE (Machine check exception) + CX8 (CMPXCHG8 instruction supported) + APIC (On-chip APIC hardware supported) + SEP (Fast system call) + MTRR (Memory type range registers) + PGE (Page global enable) + MCA (Machine check architecture) + CMOV (Conditional move instruction supported) + PAT (Page attribute table) + PSE-36 (36-bit page size extension) + CLFSH (CLFLUSH instruction supported) + DS (Debug store) + ACPI (ACPI supported) + MMX (MMX technology supported) + FXSR (FXSAVE and FXSTOR instructions supported) + SSE (Streaming SIMD extensions) + SSE2 (Streaming SIMD extensions 2) + SS (Self-snoop) + HTT (Multi-threading) + TM (Thermal monitor supported) + PBE (Pending break enabled) + Version: Intel(R) Core(TM)2 Duo CPU P8600 @ 2.40GHz + Voltage: 1.2 V + External Clock: 266 MHz + Max Speed: 2400 MHz + Current Speed: 2400 MHz + Status: Populated, Enabled + Upgrade: None + L1 Cache Handle: 0x000A + L2 Cache Handle: 0x000C + L3 Cache Handle: Not Provided + Serial Number: Not Specified + Asset Tag: Not Specified + Part Number: Not Specified + +Handle 0x0007, DMI type 5, 20 bytes +Memory Controller Information + Error Detecting Method: None + Error Correcting Capabilities: + None + Supported Interleave: One-way Interleave + Current Interleave: One-way Interleave + Maximum Memory Module Size: 4096 MB + Maximum Total Memory Size: 8192 MB + Supported Speeds: + Other + Supported Memory Types: + DIMM + SDRAM + Memory Module Voltage: 2.9 V + Associated Memory Slots: 2 + 0x0008 + 0x0009 + Enabled Error Correcting Capabilities: + Unknown + +Handle 0x0008, DMI type 6, 12 bytes +Memory Module Information + Socket Designation: DIMM Slot 1 + Bank Connections: 0 1 + Current Speed: 155 ns + Type: DIMM SDRAM + Installed Size: 4096 MB (Double-bank Connection) + Enabled Size: 4096 MB (Double-bank Connection) + Error Status: OK + +Handle 0x0009, DMI type 6, 12 bytes +Memory Module Information + Socket Designation: DIMM Slot 2 + Bank Connections: 2 3 + Current Speed: 155 ns + Type: DIMM SDRAM + Installed Size: 4096 MB (Double-bank Connection) + Enabled Size: 4096 MB (Double-bank Connection) + Error Status: OK + +Handle 0x000A, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L1 Cache + Configuration: Enabled, Socketed, Level 1 + Operational Mode: Write Back + Location: Internal + Installed Size: 64 kB + Maximum Size: 64 kB + Supported SRAM Types: + Synchronous + Installed SRAM Type: Synchronous + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Instruction + Associativity: 8-way Set-associative + +Handle 0x000B, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L1 Cache + Configuration: Enabled, Socketed, Level 1 + Operational Mode: Write Back + Location: Internal + Installed Size: 64 kB + Maximum Size: 64 kB + Supported SRAM Types: + Synchronous + Installed SRAM Type: Synchronous + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Data + Associativity: 8-way Set-associative + +Handle 0x000C, DMI type 7, 19 bytes +Cache Information + Socket Designation: Internal L2 Cache + Configuration: Enabled, Socketed, Level 2 + Operational Mode: Write Back + Location: Internal + Installed Size: 3072 kB + Maximum Size: 3072 kB + Supported SRAM Types: + Burst + Installed SRAM Type: Burst + Speed: Unknown + Error Correction Type: Single-bit ECC + System Type: Unified + Associativity: 8-way Set-associative + +Handle 0x000D, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: External Monitor + External Connector Type: DB-15 female + Port Type: Video Port + +Handle 0x000E, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Microphone Jack + External Connector Type: Mini Jack (headphones) + Port Type: Audio Port + +Handle 0x000F, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Headphone Jack + External Connector Type: Mini Jack (headphones) + Port Type: Audio Port + +Handle 0x0010, DMI type 126, 9 bytes +Inactive + +Handle 0x0011, DMI type 126, 9 bytes +Inactive + +Handle 0x0012, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Modem + External Connector Type: RJ-11 + Port Type: Modem Port + +Handle 0x0013, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: Ethernet + External Connector Type: RJ-45 + Port Type: Network Port + +Handle 0x0014, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 1 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0015, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 2 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0016, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: USB 3 + External Connector Type: Access Bus (USB) + Port Type: USB + +Handle 0x0017, DMI type 126, 9 bytes +Inactive + +Handle 0x0018, DMI type 126, 9 bytes +Inactive + +Handle 0x0019, DMI type 126, 9 bytes +Inactive + +Handle 0x001A, DMI type 126, 9 bytes +Inactive + +Handle 0x001B, DMI type 126, 9 bytes +Inactive + +Handle 0x001C, DMI type 126, 9 bytes +Inactive + +Handle 0x001D, DMI type 126, 9 bytes +Inactive + +Handle 0x001E, DMI type 126, 9 bytes +Inactive + +Handle 0x001F, DMI type 8, 9 bytes +Port Connector Information + Internal Reference Designator: Not Available + Internal Connector Type: None + External Reference Designator: IEEE1394 + External Connector Type: IEEE 1394 + Port Type: Firewire (IEEE P1394) + +Handle 0x0020, DMI type 9, 13 bytes +System Slot Information + Designation: ExpressCard Slot 1 + Type: x1 PCI Express + Current Usage: Available + Length: Other + ID: 0 + Characteristics: + Hot-plug devices are supported + +Handle 0x0021, DMI type 9, 13 bytes +System Slot Information + Designation: CardBus Slot 1 + Type: 32-bit PC Card (PCMCIA) + Current Usage: Available + Length: Other + ID: Adapter 1, Socket 0 + Characteristics: + 5.0 V is provided + 3.3 V is provided + PC Card-16 is supported + Cardbus is supported + Zoom Video is supported + Modem ring resume is supported + PME signal is supported + Hot-plug devices are supported + +Handle 0x0022, DMI type 126, 13 bytes +Inactive + +Handle 0x0023, DMI type 126, 13 bytes +Inactive + +Handle 0x0024, DMI type 9, 13 bytes +System Slot Information + Designation: Media Card Slot 1 + Type: Other + Current Usage: Available + Length: Other + Characteristics: + Hot-plug devices are supported + +Handle 0x0025, DMI type 126, 13 bytes +Inactive + +Handle 0x0026, DMI type 126, 13 bytes +Inactive + +Handle 0x0027, DMI type 10, 6 bytes +On Board Device Information + Type: Other + Status: Enabled + Description: IBM Embedded Security hardware + +Handle 0x0028, DMI type 11, 5 bytes +OEM Strings + String 1: IBM ThinkPad Embedded Controller -[7VHT12WW-1.01 ]- + +Handle 0x0029, DMI type 13, 22 bytes +BIOS Language Information + Language Description Format: Abbreviated + Installable Languages: 1 + enUS + Currently Installed Language: enUS + +Handle 0x002A, DMI type 15, 25 bytes +System Event Log + Area Length: 0 bytes + Header Start Offset: 0x0000 + Header Length: 16 bytes + Data Start Offset: 0x0010 + Access Method: General-purpose non-volatile data functions + Access Address: 0x0000 + Status: Valid, Not Full + Change Token: 0x00000070 + Header Format: Type 1 + Supported Log Type Descriptors: 1 + Descriptor 1: POST error + Data Format 1: POST results bitmap + +Handle 0x002B, DMI type 16, 15 bytes +Physical Memory Array + Location: System Board Or Motherboard + Use: System Memory + Error Correction Type: None + Maximum Capacity: 4 GB + Error Information Handle: Not Provided + Number Of Devices: 2 + +Handle 0x002C, DMI type 17, 27 bytes +Memory Device + Array Handle: 0x002B + Error Information Handle: No Error + Total Width: 64 bits + Data Width: 64 bits + Size: 4096 MB + Form Factor: SODIMM + Set: None + Locator: DIMM 1 + Bank Locator: Bank 0/1 + Type: DDR2 + Type Detail: Synchronous + Speed: 667 MHz + Manufacturer: Not Specified + Serial Number: Not Specified + Asset Tag: Not Specified + Part Number: Not Specified + +Handle 0x002D, DMI type 17, 27 bytes +Memory Device + Array Handle: 0x002B + Error Information Handle: No Error + Total Width: 64 bits + Data Width: 64 bits + Size: 4096 MB + Form Factor: SODIMM + Set: None + Locator: DIMM 2 + Bank Locator: Bank 2/3 + Type: DDR2 + Type Detail: Synchronous + Speed: 667 MHz + Manufacturer: Not Specified + Serial Number: Not Specified + Asset Tag: Not Specified + Part Number: Not Specified + +Handle 0x002E, DMI type 18, 23 bytes +32-bit Memory Error Information + Type: OK + Granularity: Unknown + Operation: Unknown + Vendor Syndrome: Unknown + Memory Array Address: Unknown + Device Address: Unknown + Resolution: Unknown + +Handle 0x002F, DMI type 19, 15 bytes +Memory Array Mapped Address + Starting Address: 0x00000000000 + Ending Address: 0x001FFFFFFFF + Range Size: 8 GB + Physical Array Handle: 0x002B + Partition Width: 2 + +Handle 0x0030, DMI type 20, 19 bytes +Memory Device Mapped Address + Starting Address: 0x00000000000 + Ending Address: 0x000FFFFFFFF + Range Size: 4 GB + Physical Device Handle: 0x002C + Memory Array Mapped Address Handle: 0x002F + Partition Row Position: 1 + +Handle 0x0031, DMI type 20, 19 bytes +Memory Device Mapped Address + Starting Address: 0x00100000000 + Ending Address: 0x001FFFFFFFF + Range Size: 4 GB + Physical Device Handle: 0x002D + Memory Array Mapped Address Handle: 0x002F + Partition Row Position: 1 + +Handle 0x0032, DMI type 21, 7 bytes +Built-in Pointing Device + Type: Track Point + Interface: PS/2 + Buttons: 3 + +Handle 0x0033, DMI type 21, 7 bytes +Built-in Pointing Device + Type: Touch Pad + Interface: PS/2 + Buttons: 0 + +Handle 0x0034, DMI type 22, 26 bytes +Portable Battery + Location: Rear + Manufacturer: Panasonic + Name: 42T4532 + Design Capacity: 84240 mWh + Design Voltage: 10800 mV + SBDS Version: 03.01 + Maximum Error: Unknown + SBDS Serial Number: 02C2 + SBDS Manufacture Date: 2008-10-15 + SBDS Chemistry: LION + OEM-specific Information: 0x00000000 + +Handle 0x0035, DMI type 126, 26 bytes +Inactive + +Handle 0x0036, DMI type 24, 5 bytes +Hardware Security + Power-On Password Status: Enabled + Keyboard Password Status: Disabled + Administrator Password Status: Enabled + Front Panel Reset Status: Unknown + +Handle 0x0037, DMI type 32, 11 bytes +System Boot Information + Status: No errors detected + +Handle 0x0038, DMI type 131, 17 bytes +OEM-specific Type + Header and Data: + 83 11 38 00 01 02 03 FF FF 1F 00 00 00 00 00 02 + 00 + Strings: + BOOTINF 20h + BOOTDEV 21h + KEYPTRS 23h + +Handle 0x0039, DMI type 131, 22 bytes +OEM-specific Type + Header and Data: + 83 16 39 00 01 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 01 + Strings: + TVT-Enablement + +Handle 0x003A, DMI type 132, 7 bytes +OEM-specific Type + Header and Data: + 84 07 3A 00 02 DA 36 + +Handle 0x003B, DMI type 133, 5 bytes +OEM-specific Type + Header and Data: + 85 05 3B 00 01 + Strings: + KHOIHGIUCCHHII + +Handle 0x003C, DMI type 134, 13 bytes +OEM-specific Type + Header and Data: + 86 0D 3C 00 04 11 08 20 00 00 00 00 00 + +Handle 0x003D, DMI type 134, 16 bytes +OEM-specific Type + Header and Data: + 86 10 3D 00 00 49 4E 54 43 01 01 00 00 03 01 02 + Strings: + TPM INFO + System Reserved + +Handle 0x003E, DMI type 135, 13 bytes +OEM-specific Type + Header and Data: + 87 0D 3E 00 54 50 07 00 01 00 00 00 00 + +Handle 0x003F, DMI type 135, 18 bytes +OEM-specific Type + Header and Data: + 87 12 3F 00 54 50 07 01 01 B8 00 00 00 00 00 00 + 00 00 + +Handle 0x0040, DMI type 135, 35 bytes +OEM-specific Type + Header and Data: + 87 23 40 00 54 50 07 02 42 41 59 20 49 2F 4F 20 + 01 00 02 00 00 0B 00 48 1C 3E 18 02 00 0B 00 40 + 1C 3A 18 + +Handle 0x0041, DMI type 135, 34 bytes +OEM-specific Type + Header and Data: + 87 22 41 00 54 50 07 04 01 06 01 01 02 00 02 01 + 02 00 03 01 02 00 04 01 02 00 05 01 02 00 06 01 + 02 00 + +Handle 0x0042, DMI type 136, 6 bytes +OEM-specific Type + Header and Data: + 88 06 42 00 5A 5A + +Handle 0x0043, DMI type 126, 28 bytes +Inactive + +Handle 0x0044, DMI type 138, 40 bytes +OEM-specific Type + Header and Data: + 8A 28 44 00 14 01 02 01 40 02 01 40 02 01 40 02 + 01 40 01 40 42 49 4F 53 20 50 61 73 73 77 6F 72 + 64 20 46 6F 72 6D 61 74 + +Handle 0x0045, DMI type 139, 37 bytes +OEM-specific Type + Header and Data: + 8B 25 45 00 11 01 0A 00 00 00 00 00 00 00 00 00 + 00 50 57 4D 53 20 4B 65 79 20 49 6E 66 6F 72 6D + 61 74 69 6F 6E + +Handle 0x0046, DMI type 129, 8 bytes +OEM-specific Type + Header and Data: + 81 08 46 00 01 01 02 00 + Strings: + Intel_ASF + Intel_ASF_001 + +Handle 0x0047, DMI type 130, 20 bytes +OEM-specific Type + Header and Data: + 82 14 47 00 24 41 4D 54 01 00 00 00 00 00 00 00 + 00 00 00 00 + +Handle 0x0048, DMI type 131, 64 bytes +OEM-specific Type + Header and Data: + 83 40 48 00 3C 00 00 00 00 00 40 2A 0A 00 00 00 + F8 00 17 29 00 00 00 00 0F 00 00 00 00 00 04 00 + 64 04 03 00 03 00 01 15 C8 00 F5 10 00 00 00 00 + 00 00 00 00 07 00 00 00 76 50 72 6F 00 00 00 00 + +Handle 0x0049, DMI type 127, 4 bytes +End Of Table + diff --git a/docs/hcl/text/x200s/cblog00.txt b/docs/hcl/text/x200s/cblog00.txt new file mode 100644 index 00000000..331cb643 --- /dev/null +++ b/docs/hcl/text/x200s/cblog00.txt @@ -0,0 +1,196 @@ +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +WARNING: Ignoring S4-assertion-width violation. +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using low power mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 14 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 15 + Max clock: 533 MHz + CAS: 0x01c0 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +SFF platform unsupported in RCOMP initialization. +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +Interrupted RAM init, reset required. +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using low power mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 14 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 15 + Max clock: 533 MHz + CAS: 0x01c0 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +SFF platform unsupported in RCOMP initialization. +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +Interrupted RAM init, reset required. +USB + + +coreboot-4.0-7318-g129462d Mon Dec 8 22:08:18 GMT 2014 starting... +running main(bist = 0) +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using low power mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 14 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 15 + Max clock: 533 MHz + CAS: 0x01c0 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +SFF platform unsupported in RCOMP initialization. diff --git a/docs/hcl/text/x200s/cblog01.txt b/docs/hcl/text/x200s/cblog01.txt new file mode 100644 index 00000000..afad2fed --- /dev/null +++ b/docs/hcl/text/x200s/cblog01.txt @@ -0,0 +1,1569 @@ +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +WARNING: Ignoring S4-assertion-width violation. +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using high performance mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Bank 1 populated: + Raw card type: F + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +DIMMs support 666 MHz, but chipset only runs at up to 533. Limiting... +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +Memory configured in dual-channel assymetric mode. +Memory map: +TOM = 512MB +TOLUD = 512MB +TOUUD = 512MB +REMAP: base = 65535MB + limit = 0MB +usedMEsize: 0MB +Performing Jedec initialization at address 0x00000000. +Performing Jedec initialization at address 0x08000000. +Performing Jedec initialization at address 0x10000000. +Performing Jedec initialization at address 0x18000000. +Final timings for group 0 on channel 0: 6.1.0.2.2 +Final timings for group 1 on channel 0: 6.0.2.6.1 +Final timings for group 2 on channel 0: 6.1.0.8.7 +Final timings for group 3 on channel 0: 6.1.0.7.1 +Final timings for group 0 on channel 1: 6.1.0.0.6 +Final timings for group 1 on channel 1: 6.0.2.3.4 +Final timings for group 2 on channel 1: 6.1.0.6.6 +Final timings for group 3 on channel 1: 6.1.0.3.6 +Lower bound for byte lane 0 on channel 0: 0.0 +Upper bound for byte lane 0 on channel 0: 10.1 +Final timings for byte lane 0 on channel 0: 5.0 +Lower bound for byte lane 1 on channel 0: 0.0 +Upper bound for byte lane 1 on channel 0: 11.1 +Final timings for byte lane 1 on channel 0: 5.4 +Lower bound for byte lane 2 on channel 0: 0.0 +Upper bound for byte lane 2 on channel 0: 11.3 +Final timings for byte lane 2 on channel 0: 5.5 +Lower bound for byte lane 3 on channel 0: 0.0 +Upper bound for byte lane 3 on channel 0: 10.2 +Final timings for byte lane 3 on channel 0: 5.1 +Lower bound for byte lane 4 on channel 0: 0.0 +Upper bound for byte lane 4 on channel 0: 10.2 +Final timings for byte lane 4 on channel 0: 5.1 +Lower bound for byte lane 5 on channel 0: 0.0 +Upper bound for byte lane 5 on channel 0: 8.6 +Final timings for byte lane 5 on channel 0: 4.3 +Lower bound for byte lane 6 on channel 0: 0.0 +Upper bound for byte lane 6 on channel 0: 11.2 +Final timings for byte lane 6 on channel 0: 5.5 +Lower bound for byte lane 7 on channel 0: 0.0 +Upper bound for byte lane 7 on channel 0: 9.3 +Final timings for byte lane 7 on channel 0: 4.5 +Lower bound for byte lane 0 on channel 1: 0.0 +Upper bound for byte lane 0 on channel 1: 10.0 +Final timings for byte lane 0 on channel 1: 5.0 +Lower bound for byte lane 1 on channel 1: 0.0 +Upper bound for byte lane 1 on channel 1: 11.2 +Final timings for byte lane 1 on channel 1: 5.5 +Lower bound for byte lane 2 on channel 1: 0.0 +Upper bound for byte lane 2 on channel 1: 10.3 +Final timings for byte lane 2 on channel 1: 5.1 +Lower bound for byte lane 3 on channel 1: 0.0 +Upper bound for byte lane 3 on channel 1: 9.6 +Final timings for byte lane 3 on channel 1: 4.7 +Lower bound for byte lane 4 on channel 1: 0.0 +Upper bound for byte lane 4 on channel 1: 11.3 +Final timings for byte lane 4 on channel 1: 5.5 +Lower bound for byte lane 5 on channel 1: 0.0 +Upper bound for byte lane 5 on channel 1: 8.4 +Final timings for byte lane 5 on channel 1: 4.2 +Lower bound for byte lane 6 on channel 1: 0.0 +Upper bound for byte lane 6 on channel 1: 11.2 +Final timings for byte lane 6 on channel 1: 5.5 +Lower bound for byte lane 7 on channel 1: 0.0 +Upper bound for byte lane 7 on channel 1: 9.4 +Final timings for byte lane 7 on channel 1: 4.6 +Lower bound for group 0 on channel 0: 1.6.3 +Upper bound for group 0 on channel 0: 2.2.7 +Final timings for group 0 on channel 0: 1.10.5 +Lower bound for group 1 on channel 0: 1.5.5 +Upper bound for group 1 on channel 0: 2.1.6 +Final timings for group 1 on channel 0: 1.9.5 +Lower bound for group 2 on channel 0: 2.0.0 +Upper bound for group 2 on channel 0: 2.8.7 +Final timings for group 2 on channel 0: 2.4.3 +Lower bound for group 3 on channel 0: 2.4.2 +Upper bound for group 3 on channel 0: 3.0.4 +Final timings for group 3 on channel 0: 2.8.3 +IGD decoded, subtracting 32M UMA and 4M GTT +Memory configured in dual-channel interleaved mode. +Memory map: +TOM = 8192MB +TOLUD = 3072MB +TOUUD = 9216MB +REMAP: base = 8192MB + limit = 9152MB +usedMEsize: 0MB +Enabling IGD. +Finally disabling PEG in favor of IGD. +PEG x1 disabled, SDVO disabled +ICH9 waits for VC1 negotiation... done. +ICH9 waits for port arbitration table update... done. +CBMEM: root @ bdbff000 254 entries. +exit main() +Trying CBFS ramstage loader. +CBFS: loading stage fallback/ramstage @ 0x100000 (290876 bytes), entry @ 0x100000 +EHCI debug port found in CBMEM. +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 booting... +BS: Entering BS_PRE_DEVICE state. +CBMEM: recovering 6/254 entries from root @ bdbff000 +Moving GDT to bdbda000...ok +BS: Exiting BS_PRE_DEVICE state. +BS: Entering BS_DEV_INIT_CHIPS state. +Initializing i82801ix southbridge... +BS: Exiting BS_DEV_INIT_CHIPS state. +BS: Entering BS_DEV_ENUMERATE state. +Enumerating buses... +Show all devs...Before device enumeration. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +APIC: acac: enabled 0 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:03.0: enabled 1 +PCI: 00:03.1: enabled 0 +PCI: 00:03.2: enabled 0 +PCI: 00:03.3: enabled 0 +IOAPIC: 02: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:1a.0: enabled 1 +PCI: 00:1a.1: enabled 1 +PCI: 00:1a.2: enabled 1 +PCI: 00:1a.7: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1c.4: enabled 0 +PCI: 00:1c.5: enabled 0 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 00:54: enabled 1 +I2C: 00:55: enabled 1 +I2C: 00:56: enabled 1 +I2C: 00:57: enabled 1 +I2C: 00:5c: enabled 1 +I2C: 00:5d: enabled 1 +I2C: 00:5e: enabled 1 +I2C: 00:5f: enabled 1 +PCI: 00:1f.5: enabled 0 +PCI: 00:1f.6: enabled 0 +Compare with tree... +Root Device: enabled 1 + CPU_CLUSTER: 0: enabled 1 + APIC: 00: enabled 1 + APIC: acac: enabled 0 + DOMAIN: 0000: enabled 1 + PCI: 00:00.0: enabled 1 + PCI: 00:02.0: enabled 1 + PCI: 00:02.1: enabled 1 + PCI: 00:03.0: enabled 1 + PCI: 00:03.1: enabled 0 + PCI: 00:03.2: enabled 0 + PCI: 00:03.3: enabled 0 + IOAPIC: 02: enabled 1 + PCI: 00:19.0: enabled 1 + PCI: 00:1a.0: enabled 1 + PCI: 00:1a.1: enabled 1 + PCI: 00:1a.2: enabled 1 + PCI: 00:1a.7: enabled 1 + PCI: 00:1b.0: enabled 1 + PCI: 00:1c.0: enabled 1 + PCI: 00:1c.1: enabled 1 + PCI: 00:1c.2: enabled 1 + PCI: 00:1c.3: enabled 1 + PCI: 00:1c.4: enabled 0 + PCI: 00:1c.5: enabled 0 + PCI: 00:1d.0: enabled 1 + PCI: 00:1d.1: enabled 1 + PCI: 00:1d.2: enabled 1 + PCI: 00:1d.7: enabled 1 + PCI: 00:1e.0: enabled 1 + PCI: 00:1f.0: enabled 1 + PNP: 00ff.1: enabled 1 + PNP: 00ff.2: enabled 1 + PCI: 00:1f.2: enabled 1 + PCI: 00:1f.3: enabled 1 + I2C: 00:54: enabled 1 + I2C: 00:55: enabled 1 + I2C: 00:56: enabled 1 + I2C: 00:57: enabled 1 + I2C: 00:5c: enabled 1 + I2C: 00:5d: enabled 1 + I2C: 00:5e: enabled 1 + I2C: 00:5f: enabled 1 + PCI: 00:1f.5: enabled 0 + PCI: 00:1f.6: enabled 0 +scan_static_bus for Root Device +CPU_CLUSTER: 0 enabled +Normal boot. +DOMAIN: 0000 enabled +DOMAIN: 0000 scanning... +PCI: pci_scan_bus for bus 00 +PCI: 00:00.0 [8086/2a40] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:02.0 [8086/0000] ops +PCI: 00:02.0 [8086/2a42] enabled +PCI: 00:02.1 [8086/2a43] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: Static device PCI: 00:03.0 not found, disabling it. +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:19.0 [8086/10f5] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1a.0 [8086/2937] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1a.1 [8086/2938] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1a.2 [8086/2939] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:1a.7 [8086/0000] ops +PCI: 00:1a.7 [8086/293c] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1b.0 [8086/293e] ops +PCI: 00:1b.0 [8086/293e] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1c.0 [8086/0000] bus ops +PCI: 00:1c.0 [8086/2940] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1c.1 [8086/0000] bus ops +PCI: 00:1c.1 [8086/2942] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1c.2 [8086/0000] bus ops +PCI: 00:1c.2 [8086/2944] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1c.3 [8086/0000] bus ops +PCI: 00:1c.3 [8086/2946] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:1d.0 [8086/2934] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1d.1 [8086/2935] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1d.2 [8086/2936] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:1d.7 [8086/0000] ops +PCI: 00:1d.7 [8086/293a] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1e.0 [8086/0000] bus ops +PCI: 00:1e.0 [8086/2448] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1f.0 [8086/0000] bus ops +PCI: 00:1f.0 [8086/2917] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: 00:1f.2 [8086/0000] ops +PCI: 00:1f.2 [8086/2928] enabled +child IOAPIC: 02 not a PCI device +PCI: 00:1f.3 [8086/0000] bus ops +PCI: 00:1f.3 [8086/2930] enabled +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +child IOAPIC: 02 not a PCI device +PCI: Left over static devices: +IOAPIC: 02 +PCI: Check your devicetree.cb. +do_pci_scan_bridge for PCI: 00:1c.0 +PCI: pci_scan_bus for bus 01 +PCI: pci_scan_bus returning with max=001 +do_pci_scan_bridge returns max 1 +do_pci_scan_bridge for PCI: 00:1c.1 +PCI: pci_scan_bus for bus 02 +PCI: pci_scan_bus returning with max=002 +do_pci_scan_bridge returns max 2 +do_pci_scan_bridge for PCI: 00:1c.2 +PCI: pci_scan_bus for bus 03 +PCI: pci_scan_bus returning with max=003 +do_pci_scan_bridge returns max 3 +do_pci_scan_bridge for PCI: 00:1c.3 +PCI: pci_scan_bus for bus 04 +PCI: pci_scan_bus returning with max=004 +do_pci_scan_bridge returns max 4 +do_pci_scan_bridge for PCI: 00:1e.0 +PCI: pci_scan_bus for bus 05 +PCI: pci_scan_bus returning with max=005 +do_pci_scan_bridge returns max 5 +scan_static_bus for PCI: 00:1f.0 +WARNING: No CMOS option 'touchpad'. +PNP: 00ff.1 enabled +recv_ec_data: 0x37 +recv_ec_data: 0x58 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x32 +recv_ec_data: 0x32 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x06 +recv_ec_data: 0x03 +recv_ec_data: 0x40 +recv_ec_data: 0x10 +EC Firmware ID 7XHT22WW-3.6, Version 4.01A +recv_ec_data: 0x00 +recv_ec_data: 0x10 +recv_ec_data: 0x20 +recv_ec_data: 0x30 +recv_ec_data: 0x00 +recv_ec_data: 0x00 +recv_ec_data: 0xa6 +recv_ec_data: 0x01 +recv_ec_data: 0x70 +dock is not connected +PNP: 00ff.2 enabled +scan_static_bus for PCI: 00:1f.0 done +scan_static_bus for PCI: 00:1f.3 +smbus: PCI: 00:1f.3[0]->I2C: 01:54 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:55 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:56 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:57 enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5c enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5d enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5e enabled +smbus: PCI: 00:1f.3[0]->I2C: 01:5f enabled +scan_static_bus for PCI: 00:1f.3 done +PCI: pci_scan_bus returning with max=005 +scan_static_bus for Root Device done +done +BS: Exiting BS_DEV_ENUMERATE state. +BS: Entering BS_DEV_RESOURCES state. +found VGA at PCI: 00:02.0 +Setting up VGA for PCI: 00:02.0 +Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 +Setting PCI_BRIDGE_CTL_VGA for bridge Root Device +Allocating resources... +Reading resources... +Root Device read_resources bus 0 link: 0 +CPU_CLUSTER: 0 read_resources bus 0 link: 0 +APIC: 00 missing read_resources +CPU_CLUSTER: 0 read_resources bus 0 link: 0 done +TOUUD 0x240000000 TOLUD 0xc0000000 TOM 0x200000000 +IGD decoded, subtracting 32M UMA and 4M GTT +Available memory below 4GB: 3036M +Available memory above 4GB: 5120M +Adding UMA memory area base=0xbdc00000 size=0x2400000 +Adding PCIe config bar base=0xf0000000 size=0x4000000 +DOMAIN: 0000 read_resources bus 0 link: 0 +More than one caller of pci_ehci_read_resources from PCI: 00:1a.7 +PCI: 00:1c.0 read_resources bus 1 link: 0 +PCI: 00:1c.0 read_resources bus 1 link: 0 done +PCI: 00:1c.1 read_resources bus 2 link: 0 +PCI: 00:1c.1 read_resources bus 2 link: 0 done +PCI: 00:1c.2 read_resources bus 3 link: 0 +PCI: 00:1c.2 read_resources bus 3 link: 0 done +PCI: 00:1c.3 read_resources bus 4 link: 0 +PCI: 00:1c.3 read_resources bus 4 link: 0 done +PCI: 00:1d.7 EHCI BAR hook registered +PCI: 00:1e.0 read_resources bus 5 link: 0 +PCI: 00:1e.0 read_resources bus 5 link: 0 done +PCI: 00:1f.0 read_resources bus 0 link: 0 +PNP: 00ff.1 missing read_resources +PNP: 00ff.2 missing read_resources +PCI: 00:1f.0 read_resources bus 0 link: 0 done +PCI: 00:1f.3 read_resources bus 1 link: 0 +PCI: 00:1f.3 read_resources bus 1 link: 0 done +DOMAIN: 0000 read_resources bus 0 link: 0 done +Root Device read_resources bus 0 link: 0 done +Done reading resources. +Show resources in subtree (Root Device)...After reading. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: acac + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bdb40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base 100000000 size 140000000 align 0 gran 0 limit 0 flags e0004200 index 5 + DOMAIN: 0000 resource base bdc00000 size 2400000 align 0 gran 0 limit 0 flags f0000200 index 6 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:02.0 + PCI: 00:02.0 resource base 0 size 400000 align 22 gran 22 limit ffffffffffffffff flags 201 index 10 + PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 + PCI: 00:02.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 20 + PCI: 00:02.1 + PCI: 00:02.1 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 10 + PCI: 00:03.0 + PCI: 00:03.1 + PCI: 00:03.2 + PCI: 00:03.3 + PCI: 00:19.0 + PCI: 00:19.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 + PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 + PCI: 00:19.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 18 + PCI: 00:1a.0 + PCI: 00:1a.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1a.1 + PCI: 00:1a.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1a.2 + PCI: 00:1a.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1a.7 + PCI: 00:1a.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 + PCI: 00:1c.0 + PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.1 + PCI: 00:1c.1 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.1 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1c.3Unknown device path type: 0 + child on link 0 + PCI: 00:1c.3 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1c.3 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 +Unknown device path type: 0 + +Unknown device path type: 0 + resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 200 index 10 +Unknown device path type: 0 + resource base 0 size 800000 align 22 gran 22 limit ffffffff flags 1200 index 14 +Unknown device path type: 0 + resource base 0 size 1000 align 12 gran 12 limit ffff flags 100 index 18 + PCI: 00:1c.4 + PCI: 00:1c.5 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base 0 size 400 align 10 gran 10 limit ffffffff flags 200 index 10 + PCI: 00:1e.0 + PCI: 00:1e.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 + PCI: 00:1e.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 10 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 14 + PCI: 00:1f.2 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18 + PCI: 00:1f.2 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c + PCI: 00:1f.2 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20 + PCI: 00:1f.2 resource base 0 size 800 align 11 gran 11 limit ffffffff flags 200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:54 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + PCI: 00:1f.3 resource base 0 size 100 align 8 gran 8 limit ffffffffffffffff flags 201 index 10 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f + PCI: 00:1f.5 + PCI: 00:1f.6 +DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.1 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1c.2 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +Unknown device path type: 0 + 18 * [0x0 - 0xfff] io +PCI: 00:1c.3 compute_resources_io: base: 1000 size: 1000 align: 12 gran: 12 limit: ffff done +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff +PCI: 00:1e.0 compute_resources_io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done +PCI: 00:1c.3 1c * [0x0 - 0xfff] io +PCI: 00:19.0 18 * [0x1000 - 0x101f] io +PCI: 00:1a.0 20 * [0x1020 - 0x103f] io +PCI: 00:1a.1 20 * [0x1040 - 0x105f] io +PCI: 00:1a.2 20 * [0x1060 - 0x107f] io +PCI: 00:1d.0 20 * [0x1080 - 0x109f] io +PCI: 00:1d.1 20 * [0x10a0 - 0x10bf] io +PCI: 00:1d.2 20 * [0x10c0 - 0x10df] io +PCI: 00:1f.2 20 * [0x10e0 - 0x10ff] io +PCI: 00:02.0 20 * [0x1400 - 0x1407] io +PCI: 00:1f.2 10 * [0x1408 - 0x140f] io +PCI: 00:1f.2 18 * [0x1410 - 0x1417] io +PCI: 00:1f.2 14 * [0x1418 - 0x141b] io +PCI: 00:1f.2 1c * [0x141c - 0x141f] io +DOMAIN: 0000 compute_resources_io: base: 1420 size: 1420 align: 12 gran: 0 limit: ffff done +DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.1 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.1 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1c.2 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1c.2 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +Unknown device path type: 0 + 14 * [0x0 - 0x7fffff] prefmem +PCI: 00:1c.3 compute_resources_prefmem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done +PCI: 00:1c.3 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +Unknown device path type: 0 + 10 * [0x0 - 0x7fffff] mem +PCI: 00:1c.3 compute_resources_mem: base: 800000 size: 800000 align: 22 gran: 20 limit: ffffffff done +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff +PCI: 00:1e.0 compute_resources_prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff +PCI: 00:1e.0 compute_resources_mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff done +PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem +PCI: 00:1c.3 24 * [0x10000000 - 0x107fffff] prefmem +PCI: 00:1c.3 20 * [0x10800000 - 0x10ffffff] mem +PCI: 00:02.0 10 * [0x11000000 - 0x113fffff] mem +PCI: 00:02.1 10 * [0x11400000 - 0x114fffff] mem +PCI: 00:19.0 10 * [0x11500000 - 0x1151ffff] mem +PCI: 00:1b.0 10 * [0x11520000 - 0x11523fff] mem +PCI: 00:19.0 14 * [0x11524000 - 0x11524fff] mem +PCI: 00:1f.2 24 * [0x11525000 - 0x115257ff] mem +PCI: 00:1a.7 10 * [0x11525800 - 0x11525bff] mem +PCI: 00:1d.7 10 * [0x11525c00 - 0x11525fff] mem +PCI: 00:1f.3 10 * [0x11526000 - 0x115260ff] mem +DOMAIN: 0000 compute_resources_mem: base: 11526100 size: 11526100 align: 28 gran: 0 limit: ffffffff done +avoid_fixed_resources: DOMAIN: 0000 +avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff +avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff +constrain_resources: DOMAIN: 0000 +constrain_resources: PCI: 00:00.0 +constrain_resources: PCI: 00:02.0 +constrain_resources: PCI: 00:02.1 +constrain_resources: PCI: 00:19.0 +constrain_resources: PCI: 00:1a.0 +constrain_resources: PCI: 00:1a.1 +constrain_resources: PCI: 00:1a.2 +constrain_resources: PCI: 00:1a.7 +constrain_resources: PCI: 00:1b.0 +constrain_resources: PCI: 00:1c.0 +constrain_resources: PCI: 00:1c.1 +constrain_resources: PCI: 00:1c.2 +constrain_resources: PCI: 00:1c.3 +Unknown device path type: 0 +constrain_resources: +constrain_resources: PCI: 00:1d.0 +constrain_resources: PCI: 00:1d.1 +constrain_resources: PCI: 00:1d.2 +constrain_resources: PCI: 00:1d.7 +constrain_resources: PCI: 00:1e.0 +constrain_resources: PCI: 00:1f.0 +constrain_resources: PNP: 00ff.1 +constrain_resources: PNP: 00ff.2 +skipping PNP: 00ff.2@60 fixed resource, size=0! +skipping PNP: 00ff.2@62 fixed resource, size=0! +skipping PNP: 00ff.2@64 fixed resource, size=0! +skipping PNP: 00ff.2@66 fixed resource, size=0! +constrain_resources: PCI: 00:1f.2 +constrain_resources: PCI: 00:1f.3 +constrain_resources: I2C: 01:54 +constrain_resources: I2C: 01:55 +constrain_resources: I2C: 01:56 +constrain_resources: I2C: 01:57 +constrain_resources: I2C: 01:5c +constrain_resources: I2C: 01:5d +constrain_resources: I2C: 01:5e +constrain_resources: I2C: 01:5f +avoid_fixed_resources2: DOMAIN: 0000@10000000 limit 0000ffff + lim->base 000015f0 lim->limit 0000ffff +avoid_fixed_resources2: DOMAIN: 0000@10000100 limit ffffffff + lim->base c0000000 lim->limit efffffff +Setting resources... +DOMAIN: 0000 allocate_resources_io: base:15f0 size:1420 align:12 gran:0 limit:ffff +Assigned: PCI: 00:1c.3 1c * [0x2000 - 0x2fff] io +Assigned: PCI: 00:19.0 18 * [0x3000 - 0x301f] io +Assigned: PCI: 00:1a.0 20 * [0x3020 - 0x303f] io +Assigned: PCI: 00:1a.1 20 * [0x3040 - 0x305f] io +Assigned: PCI: 00:1a.2 20 * [0x3060 - 0x307f] io +Assigned: PCI: 00:1d.0 20 * [0x3080 - 0x309f] io +Assigned: PCI: 00:1d.1 20 * [0x30a0 - 0x30bf] io +Assigned: PCI: 00:1d.2 20 * [0x30c0 - 0x30df] io +Assigned: PCI: 00:1f.2 20 * [0x30e0 - 0x30ff] io +Assigned: PCI: 00:02.0 20 * [0x3400 - 0x3407] io +Assigned: PCI: 00:1f.2 10 * [0x3408 - 0x340f] io +Assigned: PCI: 00:1f.2 18 * [0x3410 - 0x3417] io +Assigned: PCI: 00:1f.2 14 * [0x3418 - 0x341b] io +Assigned: PCI: 00:1f.2 1c * [0x341c - 0x341f] io +DOMAIN: 0000 allocate_resources_io: next_base: 3420 size: 1420 align: 12 gran: 0 done +PCI: 00:1c.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.1 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.1 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.2 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1c.2 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +PCI: 00:1c.3 allocate_resources_io: base:2000 size:1000 align:12 gran:12 limit:ffff +Unknown device path type: 0 +Assigned: 18 * [0x2000 - 0x2fff] io +PCI: 00:1c.3 allocate_resources_io: next_base: 3000 size: 1000 align: 12 gran: 12 done +PCI: 00:1e.0 allocate_resources_io: base:ffff size:0 align:12 gran:12 limit:ffff +PCI: 00:1e.0 allocate_resources_io: next_base: ffff size: 0 align: 12 gran: 12 done +DOMAIN: 0000 allocate_resources_mem: base:d0000000 size:11526100 align:28 gran:0 limit:efffffff +Assigned: PCI: 00:02.0 18 * [0xd0000000 - 0xdfffffff] prefmem +Assigned: PCI: 00:1c.3 24 * [0xe0000000 - 0xe07fffff] prefmem +Assigned: PCI: 00:1c.3 20 * [0xe0800000 - 0xe0ffffff] mem +Assigned: PCI: 00:02.0 10 * [0xe1000000 - 0xe13fffff] mem +Assigned: PCI: 00:02.1 10 * [0xe1400000 - 0xe14fffff] mem +Assigned: PCI: 00:19.0 10 * [0xe1500000 - 0xe151ffff] mem +Assigned: PCI: 00:1b.0 10 * [0xe1520000 - 0xe1523fff] mem +Assigned: PCI: 00:19.0 14 * [0xe1524000 - 0xe1524fff] mem +Assigned: PCI: 00:1f.2 24 * [0xe1525000 - 0xe15257ff] mem +Assigned: PCI: 00:1a.7 10 * [0xe1525800 - 0xe1525bff] mem +Assigned: PCI: 00:1d.7 10 * [0xe1525c00 - 0xe1525fff] mem +Assigned: PCI: 00:1f.3 10 * [0xe1526000 - 0xe15260ff] mem +DOMAIN: 0000 allocate_resources_mem: next_base: e1526100 size: 11526100 align: 28 gran: 0 done +PCI: 00:1c.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.0 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.0 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.1 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.1 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.2 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1c.2 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1c.3 allocate_resources_prefmem: base:e0000000 size:800000 align:22 gran:20 limit:efffffff +Unknown device path type: 0 +Assigned: 14 * [0xe0000000 - 0xe07fffff] prefmem +PCI: 00:1c.3 allocate_resources_prefmem: next_base: e0800000 size: 800000 align: 22 gran: 20 done +PCI: 00:1c.3 allocate_resources_mem: base:e0800000 size:800000 align:22 gran:20 limit:efffffff +Unknown device path type: 0 +Assigned: 10 * [0xe0800000 - 0xe0ffffff] mem +PCI: 00:1c.3 allocate_resources_mem: next_base: e1000000 size: 800000 align: 22 gran: 20 done +PCI: 00:1e.0 allocate_resources_prefmem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1e.0 allocate_resources_prefmem: next_base: efffffff size: 0 align: 20 gran: 20 done +PCI: 00:1e.0 allocate_resources_mem: base:efffffff size:0 align:20 gran:20 limit:efffffff +PCI: 00:1e.0 allocate_resources_mem: next_base: efffffff size: 0 align: 20 gran: 20 done +Root Device assign_resources, bus 0 link: 0 +DOMAIN: 0000 03 <- [0x0000000000 - 0x000009ffff] size 0x000a0000 gran 0x00 mem +DOMAIN: 0000 04 <- [0x00000c0000 - 0x00bdbfffff] size 0xbdb40000 gran 0x00 mem +DOMAIN: 0000 05 <- [0x0100000000 - 0x023fffffff] size 0x140000000 gran 0x00 mem +DOMAIN: 0000 06 <- [0x00bdc00000 - 0x00bfffffff] size 0x02400000 gran 0x00 mem +DOMAIN: 0000 07 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x00 mem +DOMAIN: 0000 assign_resources, bus 0 link: 0 +PCI: 00:02.0 10 <- [0x00e1000000 - 0x00e13fffff] size 0x00400000 gran 0x16 mem64 +PCI: 00:02.0 18 <- [0x00d0000000 - 0x00dfffffff] size 0x10000000 gran 0x1c prefmem64 +PCI: 00:02.0 20 <- [0x0000003400 - 0x0000003407] size 0x00000008 gran 0x03 io +PCI: 00:02.1 10 <- [0x00e1400000 - 0x00e14fffff] size 0x00100000 gran 0x14 mem64 +PCI: 00:19.0 10 <- [0x00e1500000 - 0x00e151ffff] size 0x00020000 gran 0x11 mem +PCI: 00:19.0 14 <- [0x00e1524000 - 0x00e1524fff] size 0x00001000 gran 0x0c mem +PCI: 00:19.0 18 <- [0x0000003000 - 0x000000301f] size 0x00000020 gran 0x05 io +PCI: 00:1a.0 20 <- [0x0000003020 - 0x000000303f] size 0x00000020 gran 0x05 io +PCI: 00:1a.1 20 <- [0x0000003040 - 0x000000305f] size 0x00000020 gran 0x05 io +PCI: 00:1a.2 20 <- [0x0000003060 - 0x000000307f] size 0x00000020 gran 0x05 io +PCI: 00:1a.7 10 <- [0x00e1525800 - 0x00e1525bff] size 0x00000400 gran 0x0a mem +PCI: 00:1b.0 10 <- [0x00e1520000 - 0x00e1523fff] size 0x00004000 gran 0x0e mem64 +PCI: 00:1c.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io +PCI: 00:1c.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 prefmem +PCI: 00:1c.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 01 mem +PCI: 00:1c.1 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io +PCI: 00:1c.1 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 prefmem +PCI: 00:1c.1 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 02 mem +PCI: 00:1c.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 03 io +PCI: 00:1c.2 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 prefmem +PCI: 00:1c.2 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 03 mem +PCI: 00:1c.3 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 04 io +PCI: 00:1c.3 24 <- [0x00e0000000 - 0x00e07fffff] size 0x00800000 gran 0x14 bus 04 prefmem +PCI: 00:1c.3 20 <- [0x00e0800000 - 0x00e0ffffff] size 0x00800000 gran 0x14 bus 04 mem +PCI: 00:1c.3 assign_resources, bus 4 link: 0 +Unknown device path type: 0 + missing set_resources +PCI: 00:1c.3 assign_resources, bus 4 link: 0 +PCI: 00:1d.0 20 <- [0x0000003080 - 0x000000309f] size 0x00000020 gran 0x05 io +PCI: 00:1d.1 20 <- [0x00000030a0 - 0x00000030bf] size 0x00000020 gran 0x05 io +PCI: 00:1d.2 20 <- [0x00000030c0 - 0x00000030df] size 0x00000020 gran 0x05 io +PCI: 00:1d.7 EHCI Debug Port hook triggered +PCI: 00:1d.7 10 <- [0x00e1525c00 - 0x00e1525fff] size 0x00000400 gran 0x0a mem +PCI: 00:1d.7 EHCI Debug Port relocated +PCI: 00:1e.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 05 io +PCI: 00:1e.0 24 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 05 prefmem +PCI: 00:1e.0 20 <- [0x00efffffff - 0x00effffffe] size 0x00000000 gran 0x14 bus 05 mem +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PNP: 00ff.1 missing set_resources +PNP: 00ff.2 missing set_resources +PCI: 00:1f.0 assign_resources, bus 0 link: 0 +PCI: 00:1f.2 10 <- [0x0000003408 - 0x000000340f] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 14 <- [0x0000003418 - 0x000000341b] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 18 <- [0x0000003410 - 0x0000003417] size 0x00000008 gran 0x03 io +PCI: 00:1f.2 1c <- [0x000000341c - 0x000000341f] size 0x00000004 gran 0x02 io +PCI: 00:1f.2 20 <- [0x00000030e0 - 0x00000030ff] size 0x00000020 gran 0x05 io +PCI: 00:1f.2 24 <- [0x00e1525000 - 0x00e15257ff] size 0x00000800 gran 0x0b mem +PCI: 00:1f.3 10 <- [0x00e1526000 - 0x00e15260ff] size 0x00000100 gran 0x08 mem64 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +PCI: 00:1f.3 assign_resources, bus 1 link: 0 +DOMAIN: 0000 assign_resources, bus 0 link: 0 +Root Device assign_resources, bus 0 link: 0 +Done setting resources. +Show resources in subtree (Root Device)...After assigning values. + Root Device child on link 0 CPU_CLUSTER: 0 + CPU_CLUSTER: 0 child on link 0 APIC: 00 + APIC: 00 + APIC: acac + DOMAIN: 0000 child on link 0 PCI: 00:00.0 + DOMAIN: 0000 resource base 15f0 size 1420 align 12 gran 0 limit ffff flags 40040100 index 10000000 + DOMAIN: 0000 resource base d0000000 size 11526100 align 28 gran 0 limit efffffff flags 40040200 index 10000100 + DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 3 + DOMAIN: 0000 resource base c0000 size bdb40000 align 0 gran 0 limit 0 flags e0004200 index 4 + DOMAIN: 0000 resource base 100000000 size 140000000 align 0 gran 0 limit 0 flags e0004200 index 5 + DOMAIN: 0000 resource base bdc00000 size 2400000 align 0 gran 0 limit 0 flags f0000200 index 6 + DOMAIN: 0000 resource base f0000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index 7 + PCI: 00:00.0 + PCI: 00:02.0 + PCI: 00:02.0 resource base e1000000 size 400000 align 22 gran 22 limit efffffff flags 60000201 index 10 + PCI: 00:02.0 resource base d0000000 size 10000000 align 28 gran 28 limit efffffff flags 60001201 index 18 + PCI: 00:02.0 resource base 3400 size 8 align 3 gran 3 limit ffff flags 60000100 index 20 + PCI: 00:02.1 + PCI: 00:02.1 resource base e1400000 size 100000 align 20 gran 20 limit efffffff flags 60000201 index 10 + PCI: 00:03.0 + PCI: 00:03.1 + PCI: 00:03.2 + PCI: 00:03.3 + PCI: 00:19.0 + PCI: 00:19.0 resource base e1500000 size 20000 align 17 gran 17 limit efffffff flags 60000200 index 10 + PCI: 00:19.0 resource base e1524000 size 1000 align 12 gran 12 limit efffffff flags 60000200 index 14 + PCI: 00:19.0 resource base 3000 size 20 align 5 gran 5 limit ffff flags 60000100 index 18 + PCI: 00:1a.0 + PCI: 00:1a.0 resource base 3020 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1a.1 + PCI: 00:1a.1 resource base 3040 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1a.2 + PCI: 00:1a.2 resource base 3060 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1a.7 + PCI: 00:1a.7 resource base e1525800 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1b.0 + PCI: 00:1b.0 resource base e1520000 size 4000 align 14 gran 14 limit efffffff flags 60000201 index 10 + PCI: 00:1c.0 + PCI: 00:1c.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.1 + PCI: 00:1c.1 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.1 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.2 + PCI: 00:1c.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.2 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1c.3Unknown device path type: 0 + child on link 0 + PCI: 00:1c.3 resource base 2000 size 1000 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1c.3 resource base e0000000 size 800000 align 22 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1c.3 resource base e0800000 size 800000 align 22 gran 20 limit efffffff flags 60080202 index 20 +Unknown device path type: 0 + +Unknown device path type: 0 + resource base e0800000 size 800000 align 22 gran 22 limit efffffff flags 40000200 index 10 +Unknown device path type: 0 + resource base e0000000 size 800000 align 22 gran 22 limit efffffff flags 40001200 index 14 +Unknown device path type: 0 + resource base 2000 size 1000 align 12 gran 12 limit ffff flags 40000100 index 18 + PCI: 00:1c.4 + PCI: 00:1c.5 + PCI: 00:1d.0 + PCI: 00:1d.0 resource base 3080 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.1 + PCI: 00:1d.1 resource base 30a0 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.2 + PCI: 00:1d.2 resource base 30c0 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1d.7 + PCI: 00:1d.7 resource base e1525c00 size 400 align 10 gran 10 limit efffffff flags 60000200 index 10 + PCI: 00:1e.0 + PCI: 00:1e.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c + PCI: 00:1e.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60081202 index 24 + PCI: 00:1e.0 resource base efffffff size 0 align 20 gran 20 limit efffffff flags 60080202 index 20 + PCI: 00:1f.0 child on link 0 PNP: 00ff.1 + PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 + PCI: 00:1f.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0040200 index 10000100 + PCI: 00:1f.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 + PNP: 00ff.1 + PNP: 00ff.1 resource base 15e0 size 10 align 5 gran 5 limit 0 flags 80000100 index 77 + PNP: 00ff.2 + PNP: 00ff.2 resource base 62 size 0 align 0 gran 0 limit 0 flags c0000100 index 60 + PNP: 00ff.2 resource base 66 size 0 align 0 gran 0 limit 0 flags c0000100 index 62 + PNP: 00ff.2 resource base 1600 size 0 align 0 gran 0 limit 0 flags c0000100 index 64 + PNP: 00ff.2 resource base 1604 size 0 align 0 gran 0 limit 0 flags c0000100 index 66 + PCI: 00:1f.2 + PCI: 00:1f.2 resource base 3408 size 8 align 3 gran 3 limit ffff flags 60000100 index 10 + PCI: 00:1f.2 resource base 3418 size 4 align 2 gran 2 limit ffff flags 60000100 index 14 + PCI: 00:1f.2 resource base 3410 size 8 align 3 gran 3 limit ffff flags 60000100 index 18 + PCI: 00:1f.2 resource base 341c size 4 align 2 gran 2 limit ffff flags 60000100 index 1c + PCI: 00:1f.2 resource base 30e0 size 20 align 5 gran 5 limit ffff flags 60000100 index 20 + PCI: 00:1f.2 resource base e1525000 size 800 align 11 gran 11 limit efffffff flags 60000200 index 24 + PCI: 00:1f.3 child on link 0 I2C: 01:54 + PCI: 00:1f.3 resource base 400 size 20 align 0 gran 0 limit 41f flags f0000100 index 20 + PCI: 00:1f.3 resource base e1526000 size 100 align 8 gran 8 limit efffffff flags 60000201 index 10 + I2C: 01:54 + I2C: 01:55 + I2C: 01:56 + I2C: 01:57 + I2C: 01:5c + I2C: 01:5d + I2C: 01:5e + I2C: 01:5f + PCI: 00:1f.5 + PCI: 00:1f.6 +Done allocating resources. +BS: Exiting BS_DEV_RESOURCES state. +BS: Entering BS_DEV_ENABLE state. +Enabling resources... +PCI: 00:00.0 subsystem <- 17aa/20e0 +PCI: 00:00.0 cmd <- 06 +PCI: 00:02.0 subsystem <- 17aa/20e4 +PCI: 00:02.0 cmd <- 03 +PCI: 00:02.1 subsystem <- 17aa/20e4 +PCI: 00:02.1 cmd <- 02 +PCI: 00:19.0 subsystem <- 0000/0000 +PCI: 00:19.0 cmd <- 103 +PCI: 00:1a.0 subsystem <- 17aa/20f0 +PCI: 00:1a.0 cmd <- 01 +PCI: 00:1a.1 subsystem <- 17aa/20f0 +PCI: 00:1a.1 cmd <- 01 +PCI: 00:1a.2 subsystem <- 17aa/20f0 +PCI: 00:1a.2 cmd <- 01 +PCI: 00:1a.7 subsystem <- 17aa/20f1 +PCI: 00:1a.7 cmd <- 102 +PCI: 00:1b.0 subsystem <- 17aa/20f2 +PCI: 00:1b.0 cmd <- 102 +PCI: 00:1c.0 bridge ctrl <- 0003 +PCI: 00:1c.0 subsystem <- 17aa/20f3 +PCI: 00:1c.0 cmd <- 100 +PCI: 00:1c.1 bridge ctrl <- 0003 +PCI: 00:1c.1 subsystem <- 17aa/20f3 +PCI: 00:1c.1 cmd <- 100 +PCI: 00:1c.2 bridge ctrl <- 0003 +PCI: 00:1c.2 subsystem <- 17aa/20f3 +PCI: 00:1c.2 cmd <- 100 +PCI: 00:1c.3 bridge ctrl <- 0003 +PCI: 00:1c.3 subsystem <- 17aa/20f3 +PCI: 00:1c.3 cmd <- 107 +PCI: 00:1d.0 subsystem <- 17aa/20f0 +PCI: 00:1d.0 cmd <- 01 +PCI: 00:1d.1 subsystem <- 17aa/20f0 +PCI: 00:1d.1 cmd <- 01 +PCI: 00:1d.2 subsystem <- 17aa/20f0 +PCI: 00:1d.2 cmd <- 01 +PCI: 00:1d.7 subsystem <- 17aa/20f1 +PCI: 00:1d.7 cmd <- 102 +PCI: 00:1e.0 bridge ctrl <- 0003 +PCI: 00:1e.0 subsystem <- 17aa/20f4 +PCI: 00:1e.0 cmd <- 100 +PCI: 00:1f.0 subsystem <- 17aa/20f5 +PCI: 00:1f.0 cmd <- 107 +PCI: 00:1f.2 subsystem <- 17aa/20f8 +PCI: 00:1f.2 cmd <- 03 +PCI: 00:1f.3 subsystem <- 17aa/20f9 +PCI: 00:1f.3 cmd <- 103 +done. +BS: Exiting BS_DEV_ENABLE state. +BS: Entering BS_DEV_INIT state. +Initializing devices... +Root Device init +Keyboard init... +No PS/2 keyboard detected. +CPU_CLUSTER: 0 init +start_eip=0x00001000, code_size=0x00000031 +Initializing SMM handler... ... pmbase = 0x0600 + +SMI_STS: MCSMI +PM1_STS: +GPE0_STS: GPIO14 GPIO13 GPIO11 GPIO10 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 +ALT_GP_SMI_STS: GPI14 GPI13 GPI11 GPI10 GPI9 GPI8 GPI7 GPI6 GPI5 GPI4 GPI3 GPI2 GPI1 GPI0 +TCO_STS: + ... raise SMI# +Initializing CPU #0 +CPU: vendor Intel device 1067a +CPU: family 06, model 17, stepping 0a +Enabling cache +microcode: sig=0x1067a pf=0x80 revision=0x0 +microcode: updated to revision 0xa0b date=2010-09-28 +CPU: Intel(R) Core(TM)2 Duo CPU L9400 @ 1.86GHz. +MTRR: Physical address space: +0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 +0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 +0x00000000000c0000 - 0x00000000bdc00000 size 0xbdb40000 type 6 +0x00000000bdc00000 - 0x00000000d0000000 size 0x12400000 type 0 +0x00000000d0000000 - 0x00000000e0000000 size 0x10000000 type 1 +0x00000000e0000000 - 0x0000000100000000 size 0x20000000 type 0 +0x0000000100000000 - 0x0000000240000000 size 0x140000000 type 6 +MTRR addr 0x0-0x10 set to 6 type @ 0 +MTRR addr 0x10-0x20 set to 6 type @ 1 +MTRR addr 0x20-0x30 set to 6 type @ 2 +MTRR addr 0x30-0x40 set to 6 type @ 3 +MTRR addr 0x40-0x50 set to 6 type @ 4 +MTRR addr 0x50-0x60 set to 6 type @ 5 +MTRR addr 0x60-0x70 set to 6 type @ 6 +MTRR addr 0x70-0x80 set to 6 type @ 7 +MTRR addr 0x80-0x84 set to 6 type @ 8 +MTRR addr 0x84-0x88 set to 6 type @ 9 +MTRR addr 0x88-0x8c set to 6 type @ 10 +MTRR addr 0x8c-0x90 set to 6 type @ 11 +MTRR addr 0x90-0x94 set to 6 type @ 12 +MTRR addr 0x94-0x98 set to 6 type @ 13 +MTRR addr 0x98-0x9c set to 6 type @ 14 +MTRR addr 0x9c-0xa0 set to 6 type @ 15 +MTRR addr 0xa0-0xa4 set to 0 type @ 16 +MTRR addr 0xa4-0xa8 set to 0 type @ 17 +MTRR addr 0xa8-0xac set to 0 type @ 18 +MTRR addr 0xac-0xb0 set to 0 type @ 19 +MTRR addr 0xb0-0xb4 set to 0 type @ 20 +MTRR addr 0xb4-0xb8 set to 0 type @ 21 +MTRR addr 0xb8-0xbc set to 0 type @ 22 +MTRR addr 0xbc-0xc0 set to 0 type @ 23 +MTRR addr 0xc0-0xc1 set to 6 type @ 24 +MTRR addr 0xc1-0xc2 set to 6 type @ 25 +MTRR addr 0xc2-0xc3 set to 6 type @ 26 +MTRR addr 0xc3-0xc4 set to 6 type @ 27 +MTRR addr 0xc4-0xc5 set to 6 type @ 28 +MTRR addr 0xc5-0xc6 set to 6 type @ 29 +MTRR addr 0xc6-0xc7 set to 6 type @ 30 +MTRR addr 0xc7-0xc8 set to 6 type @ 31 +MTRR addr 0xc8-0xc9 set to 6 type @ 32 +MTRR addr 0xc9-0xca set to 6 type @ 33 +MTRR addr 0xca-0xcb set to 6 type @ 34 +MTRR addr 0xcb-0xcc set to 6 type @ 35 +MTRR addr 0xcc-0xcd set to 6 type @ 36 +MTRR addr 0xcd-0xce set to 6 type @ 37 +MTRR addr 0xce-0xcf set to 6 type @ 38 +MTRR addr 0xcf-0xd0 set to 6 type @ 39 +MTRR addr 0xd0-0xd1 set to 6 type @ 40 +MTRR addr 0xd1-0xd2 set to 6 type @ 41 +MTRR addr 0xd2-0xd3 set to 6 type @ 42 +MTRR addr 0xd3-0xd4 set to 6 type @ 43 +MTRR addr 0xd4-0xd5 set to 6 type @ 44 +MTRR addr 0xd5-0xd6 set to 6 type @ 45 +MTRR addr 0xd6-0xd7 set to 6 type @ 46 +MTRR addr 0xd7-0xd8 set to 6 type @ 47 +MTRR addr 0xd8-0xd9 set to 6 type @ 48 +MTRR addr 0xd9-0xda set to 6 type @ 49 +MTRR addr 0xda-0xdb set to 6 type @ 50 +MTRR addr 0xdb-0xdc set to 6 type @ 51 +MTRR addr 0xdc-0xdd set to 6 type @ 52 +MTRR addr 0xdd-0xde set to 6 type @ 53 +MTRR addr 0xde-0xdf set to 6 type @ 54 +MTRR addr 0xdf-0xe0 set to 6 type @ 55 +MTRR addr 0xe0-0xe1 set to 6 type @ 56 +MTRR addr 0xe1-0xe2 set to 6 type @ 57 +MTRR addr 0xe2-0xe3 set to 6 type @ 58 +MTRR addr 0xe3-0xe4 set to 6 type @ 59 +MTRR addr 0xe4-0xe5 set to 6 type @ 60 +MTRR addr 0xe5-0xe6 set to 6 type @ 61 +MTRR addr 0xe6-0xe7 set to 6 type @ 62 +MTRR addr 0xe7-0xe8 set to 6 type @ 63 +MTRR addr 0xe8-0xe9 set to 6 type @ 64 +MTRR addr 0xe9-0xea set to 6 type @ 65 +MTRR addr 0xea-0xeb set to 6 type @ 66 +MTRR addr 0xeb-0xec set to 6 type @ 67 +MTRR addr 0xec-0xed set to 6 type @ 68 +MTRR addr 0xed-0xee set to 6 type @ 69 +MTRR addr 0xee-0xef set to 6 type @ 70 +MTRR addr 0xef-0xf0 set to 6 type @ 71 +MTRR addr 0xf0-0xf1 set to 6 type @ 72 +MTRR addr 0xf1-0xf2 set to 6 type @ 73 +MTRR addr 0xf2-0xf3 set to 6 type @ 74 +MTRR addr 0xf3-0xf4 set to 6 type @ 75 +MTRR addr 0xf4-0xf5 set to 6 type @ 76 +MTRR addr 0xf5-0xf6 set to 6 type @ 77 +MTRR addr 0xf6-0xf7 set to 6 type @ 78 +MTRR addr 0xf7-0xf8 set to 6 type @ 79 +MTRR addr 0xf8-0xf9 set to 6 type @ 80 +MTRR addr 0xf9-0xfa set to 6 type @ 81 +MTRR addr 0xfa-0xfb set to 6 type @ 82 +MTRR addr 0xfb-0xfc set to 6 type @ 83 +MTRR addr 0xfc-0xfd set to 6 type @ 84 +MTRR addr 0xfd-0xfe set to 6 type @ 85 +MTRR addr 0xfe-0xff set to 6 type @ 86 +MTRR addr 0xff-0x100 set to 6 type @ 87 +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 36 bits +MTRR: default type WB/UC MTRR counts: 5/7. +MTRR: WB selected as default type. +MTRR: 0 base 0x00000000bdc00000 mask 0x0000000fffc00000 type 0 +MTRR: 1 base 0x00000000be000000 mask 0x0000000ffe000000 type 0 +MTRR: 2 base 0x00000000c0000000 mask 0x0000000ff0000000 type 0 +MTRR: 3 base 0x00000000d0000000 mask 0x0000000ff0000000 type 1 +MTRR: 4 base 0x00000000e0000000 mask 0x0000000fe0000000 type 0 + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x00 done. +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 0: 0, 0, 7, 0x21, 35000; encoded: 0x0721 +WARNING: No CMOS option 'hyper_threading'. +CPU: 0 2 siblings +CPU: 0 has sibling 1 +CPU #0 initialized +CPU1: stack_base 00141000, stack_end 00141ff8 +Asserting INIT. +Waiting for send to finish... ++Deasserting INIT. +Waiting for send to finish... ++#startup loops: 2. +Sending STARTUP #1 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++Sending STARTUP #2 to 1. +After apic_write. +Startup point 1. +Waiting for send to finish... ++After Startup. +Initializing CPU #1 +Waiting for 1 CPUS to stop +CPU: vendor Intel device 1067a +CPU: family 06, model 17, stepping 0a +Enabling cache +microcode: sig=0x1067a pf=0x80 revision=0x0 +microcode: updated to revision 0xa0b date=2010-09-28 +CPU: Intel(R) Core(TM)2 Duo CPU L9400 @ 1.86GHz. +MTRR: Fixed MSR 0x250 0x0606060606060606 +MTRR: Fixed MSR 0x258 0x0606060606060606 +MTRR: Fixed MSR 0x259 0x0000000000000000 +MTRR: Fixed MSR 0x268 0x0606060606060606 +MTRR: Fixed MSR 0x269 0x0606060606060606 +MTRR: Fixed MSR 0x26a 0x0606060606060606 +MTRR: Fixed MSR 0x26b 0x0606060606060606 +MTRR: Fixed MSR 0x26c 0x0606060606060606 +MTRR: Fixed MSR 0x26d 0x0606060606060606 +MTRR: Fixed MSR 0x26e 0x0606060606060606 +MTRR: Fixed MSR 0x26f 0x0606060606060606 +call enable_fixed_mtrr() +CPU physical address size: 36 bits + +MTRR check +Fixed MTRRs : Enabled +Variable MTRRs: Enabled + +Setting up local apic... apic_id: 0x01 done. +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 2: 0, 0, 6, 0x17, 15000; encoded: 0x0617 +writing P-State 1: 0, 0, 7, 0x21, 35000; encoded: 0x0721 +CPU: 1 2 siblings +CPU #1 initialized +All AP CPUs stopped (4540 loops) +CPU1: stack: 00141000 - 00142000, lowest used address 00141b6c, stack used: 1172 bytes +DOMAIN: 0000 init +PCI: 00:00.0 init +PCI: 00:02.0 init +Initializing VGA without OPROM. MMIO 0xe1000000 +EDID: +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +Extracted contents: +header: 00 00 00 00 00 00 00 00 +serial number: 00 00 00 00 00 00 00 00 00 00 +version: 00 00 +basic params: 00 00 00 00 00 +chroma info: 00 00 00 00 00 00 00 00 00 00 +established: 00 00 00 +standard: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +descriptor 1: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +descriptor 3: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +descriptor 4: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +extensions: 00 +checksum: 00 + +No header found +Couldn't find GFX clock divisors +PCI: 00:02.1 init +PCI: 00:19.0 init +PCI: 00:1a.0 init +PCI: 00:1a.1 init +PCI: 00:1a.2 init +PCI: 00:1a.7 init +EHCI: Setting up controller.. done. +PCI: 00:1b.0 init +Azalia: base = e1520000 +Azalia: No codec! +PCI: 00:1c.0 init +Initializing ICH9 PCIe root port. +PCI: 00:1c.1 init +Initializing ICH9 PCIe root port. +PCI: 00:1c.2 init +Initializing ICH9 PCIe root port. +PCI: 00:1c.3 init +Initializing ICH9 PCIe root port. +PCI: 00:1d.0 init +PCI: 00:1d.1 init +PCI: 00:1d.2 init +PCI: 00:1d.7 init +EHCI: Setting up controller.. done. +PCI: 00:1e.0 init +PCI: 00:1f.0 init +i82801ix: lpc_init +IOAPIC: Initializing IOAPIC at 0xfec00000 +IOAPIC: Bootstrap Processor Local APIC = 0x00 +IOAPIC: ID = 0x02 +IOAPIC: Dumping registers + reg 0x0000: 0x02000000 + reg 0x0001: 0x00170020 + reg 0x0002: 0x00170020 +IOAPIC: 24 interrupts +IOAPIC: Enabling interrupts on FSB +IOAPIC: reg 0x00000000 value 0x00000000 0x00000700 +IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 +IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 +IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 +IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 +WARNING: No CMOS option 'power_on_after_fail'. +Set power on after power failure. +WARNING: No CMOS option 'nmi'. +NMI sources disabled. +rtc_failed = 0x4 +RTC Init +RTC: Clear requested +Disabling ACPI via APMC: +done. +Locking SMM. +PCI: 00:1f.2 init +i82801ix_sata: initializing... +SATA controller in AHCI mode. +ABAR: E1525000 +PCI: 00:1f.3 init +smbus: PCI: 00:1f.3[0]->I2C: 01:54 init +smbus: PCI: 00:1f.3[0]->I2C: 01:55 init +smbus: PCI: 00:1f.3[0]->I2C: 01:56 init +smbus: PCI: 00:1f.3[0]->I2C: 01:57 init +smbus: PCI: 00:1f.3[0]->I2C: 01:5c init +Locking EEPROM RFID +init EEPROM done +smbus: PCI: 00:1f.3[0]->I2C: 01:5d init +smbus: PCI: 00:1f.3[0]->I2C: 01:5e init +smbus: PCI: 00:1f.3[0]->I2C: 01:5f init +Devices initialized +Show all devs...After init. +Root Device: enabled 1 +CPU_CLUSTER: 0: enabled 1 +APIC: 00: enabled 1 +APIC: acac: enabled 0 +DOMAIN: 0000: enabled 1 +PCI: 00:00.0: enabled 1 +PCI: 00:02.0: enabled 1 +PCI: 00:02.1: enabled 1 +PCI: 00:03.0: enabled 0 +PCI: 00:03.1: enabled 0 +PCI: 00:03.2: enabled 0 +PCI: 00:03.3: enabled 0 +IOAPIC: 02: enabled 1 +PCI: 00:19.0: enabled 1 +PCI: 00:1a.0: enabled 1 +PCI: 00:1a.1: enabled 1 +PCI: 00:1a.2: enabled 1 +PCI: 00:1a.7: enabled 1 +PCI: 00:1b.0: enabled 1 +PCI: 00:1c.0: enabled 1 +PCI: 00:1c.1: enabled 1 +PCI: 00:1c.2: enabled 1 +PCI: 00:1c.3: enabled 1 +PCI: 00:1c.4: enabled 0 +PCI: 00:1c.5: enabled 0 +PCI: 00:1d.0: enabled 1 +PCI: 00:1d.1: enabled 1 +PCI: 00:1d.2: enabled 1 +PCI: 00:1d.7: enabled 1 +PCI: 00:1e.0: enabled 1 +PCI: 00:1f.0: enabled 1 +PNP: 00ff.1: enabled 1 +PNP: 00ff.2: enabled 1 +PCI: 00:1f.2: enabled 1 +PCI: 00:1f.3: enabled 1 +I2C: 01:54: enabled 1 +I2C: 01:55: enabled 1 +I2C: 01:56: enabled 1 +I2C: 01:57: enabled 1 +I2C: 01:5c: enabled 1 +I2C: 01:5d: enabled 1 +I2C: 01:5e: enabled 1 +I2C: 01:5f: enabled 1 +PCI: 00:1f.5: enabled 0 +PCI: 00:1f.6: enabled 0 +Unknown device path type: 0 +: enabled 1 +APIC: 01: enabled 1 +BS: Exiting BS_DEV_INIT state. +BS: Entering BS_POST_DEVICE state. +Finalize devices... +Devices finalized +BS: Exiting BS_POST_DEVICE state. +BS: Entering BS_OS_RESUME_CHECK state. +BS: Exiting BS_OS_RESUME_CHECK state. +BS: Entering BS_WRITE_TABLES state. +Writing ISA IRQs +no IRQ found for PCI: 00:00.0 +fixed IRQ entry for: PCI: 00:02.0: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:02.1 +no IRQ found for PCI: 00:19.0 +fixed IRQ entry for: PCI: 00:1a.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1a.1: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1a.2: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1a.7: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1b.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1c.0: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:1c.1 +no IRQ found for PCI: 00:1c.2 +no IRQ found for PCI: 00:1c.3 +fixed IRQ entry for: PCI: 00:1d.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1d.1: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1d.2: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1d.7: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:1e.0 +no IRQ found for PCI: 00:1f.0 +fixed IRQ entry for: PCI: 00:1f.2: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1f.3: INTC# -> IOAPIC 2 PIN 18 +Wrote the mp table end at: 000f0010 - 000f0194 +MPTABLE len: 404 +Writing ISA IRQs +no IRQ found for PCI: 00:00.0 +fixed IRQ entry for: PCI: 00:02.0: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:02.1 +no IRQ found for PCI: 00:19.0 +fixed IRQ entry for: PCI: 00:1a.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1a.1: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1a.2: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1a.7: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1b.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1c.0: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:1c.1 +no IRQ found for PCI: 00:1c.2 +no IRQ found for PCI: 00:1c.3 +fixed IRQ entry for: PCI: 00:1d.0: INTA# -> IOAPIC 2 PIN 16 +fixed IRQ entry for: PCI: 00:1d.1: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1d.2: INTC# -> IOAPIC 2 PIN 18 +fixed IRQ entry for: PCI: 00:1d.7: INTA# -> IOAPIC 2 PIN 16 +no IRQ found for PCI: 00:1e.0 +no IRQ found for PCI: 00:1f.0 +fixed IRQ entry for: PCI: 00:1f.2: INTB# -> IOAPIC 2 PIN 17 +fixed IRQ entry for: PCI: 00:1f.3: INTC# -> IOAPIC 2 PIN 18 +Wrote the mp table end at: bdad9010 - bdad9194 +MPTABLE len: 404 +MP table: 404 bytes. +ACPI: Writing ACPI tables at bdab5000. +ACPI: * FACS +ACPI: * DSDT +ACPI: * FADT +ACPI: added table 1/32, length now 40 +ACPI: * SSDT +Found 1 CPU(s) with 2 core(s) each. +clocks between 800 and 2133 MHz. +adding 4 P-States between busratio 6 and 8, incl. P0 +PSS: 1867MHz power 35000 control 0x829 status 0x829 +PSS: 1866MHz power 35000 control 0x721 status 0x721 +PSS: 1600MHz power 15000 control 0x617 status 0x617 +PSS: 800MHz power 12000 control 0x8611 status 0x8611 +clocks between 800 and 2133 MHz. +adding 4 P-States between busratio 6 and 8, incl. P0 +PSS: 1867MHz power 35000 control 0x829 status 0x829 +PSS: 1866MHz power 35000 control 0x721 status 0x721 +PSS: 1600MHz power 15000 control 0x617 status 0x617 +PSS: 800MHz power 12000 control 0x8611 status 0x8611 +ACPI: added table 2/32, length now 44 +ACPI: * MCFG +ACPI: added table 3/32, length now 48 +ACPI: * MADT +ACPI: added table 4/32, length now 52 +current = bdab8e40 +ACPI: * DMAR +ACPI: added table 5/32, length now 56 +current = bdab8ef0 +ACPI: * HPET +ACPI: added table 6/32, length now 60 +ACPI: done. +ACPI tables: 16176 bytes. +smbios_write_tables: bdab3000 +recv_ec_data: 0x37 +recv_ec_data: 0x58 +recv_ec_data: 0x48 +recv_ec_data: 0x54 +recv_ec_data: 0x32 +recv_ec_data: 0x32 +recv_ec_data: 0x57 +recv_ec_data: 0x57 +recv_ec_data: 0x06 +recv_ec_data: 0x03 +Root Device (LENOVO ThinkPad X200) +CPU_CLUSTER: 0 (Intel GM45 Northbridge) +APIC: 00 (Socket BGA956 CPU) +APIC: acac (Intel Penryn CPU) +DOMAIN: 0000 (Intel GM45 Northbridge) +PCI: 00:00.0 (Intel GM45 Northbridge) +PCI: 00:02.0 (Intel GM45 Northbridge) +PCI: 00:02.1 (Intel GM45 Northbridge) +PCI: 00:03.0 (Intel GM45 Northbridge) +PCI: 00:03.1 (Intel GM45 Northbridge) +PCI: 00:03.2 (Intel GM45 Northbridge) +PCI: 00:03.3 (Intel GM45 Northbridge) +IOAPIC: 02 (IOAPIC) +PCI: 00:19.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1a.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1a.1 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1a.2 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1a.7 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1b.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.1 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.2 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.3 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.4 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1c.5 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1d.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1d.1 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1d.2 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1d.7 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1e.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1f.0 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PNP: 00ff.1 (Lenovo Power Management Hardware Hub 7) +PNP: 00ff.2 (Lenovo H8 EC) +PCI: 00:1f.2 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1f.3 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +I2C: 01:54 (AT24RF08C) +I2C: 01:55 (AT24RF08C) +I2C: 01:56 (AT24RF08C) +I2C: 01:57 (AT24RF08C) +I2C: 01:5c (AT24RF08C) +I2C: 01:5d (AT24RF08C) +I2C: 01:5e (AT24RF08C) +I2C: 01:5f (AT24RF08C) +PCI: 00:1f.5 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +PCI: 00:1f.6 (Intel ICH9/ICH9-M (82801Ix) Series Southbridge) +Unknown device path type: 0 + (unknown) +APIC: 01 (unknown) +SMBIOS tables: 436 bytes. +Writing table forward entry at 0x00000500 +Wrote coreboot table at: 00000500, 0x10 bytes, checksum 9233 +Table forward entry ends at 0x00000528. +... aligned to 0x00001000 +Writing coreboot table at 0xbdaab000 +rom_table_end = 0xbdaab000 +... aligned to 0xbdab0000 + 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES + 1. 0000000000001000-000000000009ffff: RAM + 2. 00000000000c0000-00000000bdaaafff: RAM + 3. 00000000bdaab000-00000000bdbfffff: CONFIGURATION TABLES + 4. 00000000bdc00000-00000000bfffffff: RESERVED + 5. 00000000f0000000-00000000f3ffffff: RESERVED + 6. 0000000100000000-000000023fffffff: RAM +Wrote coreboot table at: bdaab000, 0x8c8 bytes, checksum f79a +coreboot table: 2272 bytes. +CBMEM ROOT 0. bdbff000 00001000 +CAR GLOBALS 1. bdbfe000 00001000 +USBDEBUG 2. bdbfd000 00001000 +CONSOLE 3. bdbdd000 00020000 +TIME STAMP 4. bdbdc000 00001000 +ROMSTAGE 5. bdbdb000 00001000 +GDT 6. bdbda000 00001000 +ACPI RESUME 7. bdada000 00100000 +SMP TABLE 8. bdad9000 00001000 +ACPI 9. bdab5000 00024000 +ACPI GNVS 10. bdab4000 00001000 +SMBIOS 11. bdab3000 00001000 +COREBOOT 12. bdaab000 00008000 +BS: Exiting BS_WRITE_TABLES state. +BS: Entering BS_PAYLOAD_LOAD state. +CBFS: located payload @ ff8341b8, 542448 bytes. +Loading segment from rom address 0xff8341b8 + code (compression=1) + New segment dstaddr 0x8200 memsize 0x17e48 srcaddr 0xff83420c filesize 0x83fc + (cleaned up) New segment addr 0x8200 size 0x17e48 offset 0xff83420c filesize 0x83fc +Loading segment from rom address 0xff8341d4 + code (compression=1) + New segment dstaddr 0x100000 memsize 0x201538 srcaddr 0xff83c608 filesize 0x7c2a0 + (cleaned up) New segment addr 0x100000 size 0x201538 offset 0xff83c608 filesize 0x7c2a0 +Loading segment from rom address 0xff8341f0 + Entry Point 0x00008200 +Bounce Buffer at bd862000, 2393460 bytes +Loading Segment: addr: 0x0000000000008200 memsz: 0x0000000000017e48 filesz: 0x00000000000083fc +lb: [0x0000000000100000, 0x000000000014703c) +Post relocation: addr: 0x0000000000008200 memsz: 0x0000000000017e48 filesz: 0x00000000000083fc +using LZMA +[ 0x00008200, 00018717, 0x00020048) <- ff83420c +Clearing Segment: addr: 0x0000000000018717 memsz: 0x0000000000007931 +dest 00008200, end 00020048, bouncebuffer bd862000 +Loading Segment: addr: 0x0000000000100000 memsz: 0x0000000000201538 filesz: 0x000000000007c2a0 +lb: [0x0000000000100000, 0x000000000014703c) +segment: [0x0000000000100000, 0x000000000017c2a0, 0x0000000000301538) + bounce: [0x00000000bd862000, 0x00000000bd8de2a0, 0x00000000bda63538) +Post relocation: addr: 0x00000000bd862000 memsz: 0x0000000000201538 filesz: 0x000000000007c2a0 +using LZMA +[ 0xbd862000, bda63538, 0xbda63538) <- ff83c608 +dest bd862000, end bda63538, bouncebuffer bd862000 +move suffix around: from bd8a903c, to 14703c, amount: 1ba4fc +Loaded segments +BS: Exiting BS_PAYLOAD_LOAD state. +BS: Entering BS_PAYLOAD_BOOT state. +ICH7 watchdog disabled +Jumping to boot code at 00008200 +CPU0: stack: 00142000 - 00143000, lowest used address 00142a28, stack used: 1496 bytes +entry = 0x00008200 +lb_start = 0x00100000 +lb_size = 0x0004703c +buffer = 0xbd862000 diff --git a/docs/hcl/text/x200s/cblog02.txt b/docs/hcl/text/x200s/cblog02.txt new file mode 100644 index 00000000..3a590dc2 --- /dev/null +++ b/docs/hcl/text/x200s/cblog02.txt @@ -0,0 +1,77 @@ +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +WARNING: Ignoring S4-assertion-width violation. +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using high performance mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:b +2:51:b +DDR mask 5, DDR 3 +Bank 0 populated: + Raw card type: F + Row addr bits: 14 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 2 + tAAmin: 105 + tCKmin: 15 + Max clock: 533 MHz + CAS: 0x01c0 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +Memory configured in dual-channel assymetric mode. +Memory map: +TOM = 384MB +TOLUD = 384MB +TOUUD = 384MB +REMAP: base = 65535MB + limit = 0MB +usedMEsize: 0MB +Performing Jedec initialization at address 0x00000000. +Performing Jedec initialization at address 0x08000000. +Performing Jedec initialization at address 0x10000000. +Final timings for group 0 on channel 0: 6.1.0.3.2 +Final timings for group 1 on channel 0: 6.0.2.6.3 +Final timings for group 2 on channel 0: 6.1.2.0.1 +Final timings for group 3 on channel 0: 6.1.0.7.3 +Timing under-/overflow during receive-enable calibration. diff --git a/docs/hcl/text/x200s/cblog03.txt b/docs/hcl/text/x200s/cblog03.txt new file mode 100644 index 00000000..d078a48a --- /dev/null +++ b/docs/hcl/text/x200s/cblog03.txt @@ -0,0 +1,158 @@ +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +WARNING: Ignoring S4-assertion-width violation. +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using high performance mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:ff +2:51:b +DDR mask 4, DDR 3 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +DIMMs support 666 MHz, but chipset only runs at up to 533. Limiting... +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Changing memory frequency: old 3, new 6. +Setting IGD memory frequencies for VCO #1. +Memory configured in single-channel mode. +Memory map: +TOM = 128MB +TOLUD = 128MB +TOUUD = 128MB +REMAP: base = 65535MB + limit = 0MB +usedMEsize: 0MB +Performing Jedec initialization at address 0x00000000. +Final timings for group 0 on channel 1: 6.0.2.6.4 +Final timings for group 1 on channel 1: 6.0.2.6.4 +Final timings for group 2 on channel 1: 6.0.2.8.3 +Final timings for group 3 on channel 1: 6.0.2.8.6 +Lower bound for byte lane 0 on channel 1: 0.0 +Upper bound for byte lane 0 on channel 1: 10.4 +Final timings for byte lane 0 on channel 1: 5.2 +Lower bound for byte lane 1 on channel 1: 0.0 +Upper bound for byte lane 1 on channel 1: 11.2 +Final timings for byte lane 1 on channel 1: 5.5 +Lower bound for byte lane 2 on channel 1: 0.0 +Upper bound for byte lane 2 on channel 1: 10.5 +Final timings for byte lane 2 on channel 1: 5.2 +Lower bound for byte lane 3 on channel 1: 0.0 +Upper bound for byte lane 3 on channel 1: 9.7 +Final timings for byte lane 3 on channel 1: 4.7 +Timing overflow during read training. +Read training failure: lower bound. +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +Interrupted RAM init, reset required. +USB + + +coreboot-4.0-7551-ge420139-dirty Wed Dec 10 16:34:05 GMT 2014 starting... +running main(bist = 0) +Stepping B3 +2 CPU cores +AMT enabled +capable of DDR2 of 800 MHz or lower +VT-d enabled +GMCH: GS45, using high performance mode by default +TXT enabled +Render frequency: 533 MHz +IGD enabled +PCIe-to-GMCH enabled +GMCH supports DDR3 with 1067 MT or less +GMCH supports FSB with up to 1067 MHz +SMBus controller enabled. +0:50:ff +2:51:b +DDR mask 4, DDR 3 +Bank 1 populated: + Raw card type: B + Row addr bits: 15 + Col addr bits: 10 + byte width: 1 + page size: 1024 + banks: 8 + ranks: 1 + tAAmin: 105 + tCKmin: 12 + Max clock: 666 MHz + CAS: 0x07e0 +DIMMs support 666 MHz, but chipset only runs at up to 533. Limiting... +Trying CAS 7, tCK 15. +Found compatible clock / CAS pair: 533 / 7. +Timing values: + tCLK: 15 + tRAS: 20 + tRP: 7 + tRCD: 7 + tRFC: 104 + tWR: 8 + tRD: 11 + tRRD: 4 + tFAW: 20 + tWL: 6 +Setting IGD memory frequencies for VCO #1. +Memory configured in single-channel mode. +Memory map: +TOM = 128MB +TOLUD = 128MB +TOUUD = 128MB +REMAP: base = 65535MB + limit = 0MB +usedMEsize: 0MB +Performing Jedec initialization at address 0x00000000. +Final timings for group 0 on channel 1: 6.0.2.7.6 +Final timings for group 1 on channel 1: 6.0.2.6.6 +Final timings for group 2 on channel 1: 6.0.2.8.7 +Final timings for group 3 on channel 1: 6.1.0.2.5 +Lower bound for byte lane 0 on channel 1: 0.0 +Upper bound for byte lane 0 on channel 1: 10.3 +Final timings for byte lane 0 on channel 1: 5.1 +Lower bound for byte lane 1 on channel 1: 0.0 +Upper bound for byte lane 1 on channel 1: 11.3 +Final timings for byte lane 1 on channel 1: 5.5 +Lower bound for byte lane 2 on channel 1: 0.0 +Upper bound for byte lane 2 on channel 1: 10.5 +Final timings for byte lane 2 on channel 1: 5.2 +Lower bound for byte lane 3 on channel 1: 0.0 +Upper bound for byte lane 3 on channel 1: 9.6 +Final timings for byte lane 3 on channel 1: 4.7 +Timing overflow during read training. +Read training failure: lower bound. diff --git a/docs/hcl/x200.html b/docs/hcl/x200.html new file mode 100644 index 00000000..e7dbc290 --- /dev/null +++ b/docs/hcl/x200.html @@ -0,0 +1,175 @@ +<!DOCTYPE html> +<html> +<head> + <meta charset="utf-8"> + <meta name="viewport" content="width=device-width, initial-scale=1"> + + <style type="text/css"> + @import url('../css/main.css'); + </style> + + <title>ThinkPad X200</title> +</head> + +<body> + + <h1 id="pagetop">ThinkPad X200</h1> + <p> + This sections relates to known hardware compatibility in libreboot. + </p> + <p> + Or <a href="index.html">back to main index</a>. + </p> + + <p> + It is believed that all X200 laptops are compatible. X200s and X200t may also work, + but require soldering (for the initial installation/flashing of a ROM image, or + dumping the current firmware). <b>Only the X200 is tested so far.</b> + </p> + <p> + It *might* be possible to put an X200 motherboard in an X201 chassis, though this is currently untested + by the libreboot project. The same may also apply between X200s and X201s; again, this is untested. + <b>It's most likely true.</b> + </p> + + <p> + There are two possible flash chip sizes for the X200: 4MiB (32Mbit) or 8MiB (64Mbit). + This can be identified by the type of flash chip below the palmrest: 4MiB is SOIC-8, 8MiB + is SOIC-16. + </p> + + <p> + <b>The X200 laptops come with ME (and sometimes AMT) before flashing libreboot. Libreboot disables and removes it + by using a modified descriptor: see <a href="x200_remove_me.html">x200_remove_me.html</a></b> (contains notes, plus + instructions) + </p> + + <p> + Flashing instructions can be found at <a href="../install/index.html#flashrom_x200">../install/index.html#flashrom_x200</a> + </p> + +<hr/> + + <h1 id="lcd_supported_list">LCD compatibility list</h1> + <p> + Unless otherwise noted (italic styling, underlined), these are CCFL 1280x800 screens with TN panels inside. + Please do advise if you spot mistakes here. + </p> + <p> + Use the instructions at <a href="../misc/index.html#get_edid_panelname">../misc/index.html#get_edid_panelname</a> + to get the name of your panel, then check it against the list below. If your panel is untested, then by all means + try it! (and get in touch with the libreboot project to advise whether or not it worked). + </p> + <p> + AUO = AU Optronics. List of panels below based on + <a href="http://www.thinkwiki.org/wiki/TFT_display">http://www.thinkwiki.org/wiki/TFT_display</a> + </p> + <p> + Tested LCD panels (confirmed working): + </p> + <ul> + <li>X200/X200s: LG-Philips LP121WX3-TLC1 (sgsit on IRC has this panel) (LED backlight)</li> + <li>X200/X200s: Samsung LTN121AT03 (phcoder on IRC has this panel)</li> + <li>X200/X200s: AUO B121EW03 V.6 (fchmmr on IRC has this panel)</li> + </ul> + <p> + Untested LCD panels (status unknown): + </p> + <ul> + <li>X200 Tablet: TMD-Toshiba LTD121KX6B (LED backlight)</li> + <li>X200/X200s: TMD-Toshiba LTD121EWVB</li> + <li>X200/X200s: AOU B121EW09 V.2 (LED backlight)</li> + <li>X200/X200s: FRU 42T0715 (no manufacturer/model given) (LED backlight)</li> + <li>X200/X200s: LG-Philips LP121WX3-TLA1 (LED backlight)</li> + <li>X200/X200s: 42T0713 FRU (no model/manufacturer given) (LED backlight)</li> + <li>X200s (not X200): TMD-Toshiba LTD121EQ3B (1440x900 resolution) (LED backlight)</li> + </ul> + <p> + <a href="#pagetop">Back to top of page.</a> + </p> + + <h2 id="ips"> + AFFS/IPS panels + </h2> + <h3>X200</h3> + <p> + Adapted from <a href="https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-X200">https://github.com/bibanon/Coreboot-ThinkPads/wiki/ThinkPad-X200</a> + </p> + <p> + Look at wikipedia for difference between TN and IPS panels. IPS have much better colour/contrast than + a regular TN, and will typically have good viewing angles. + </p> + <p> + These seem to be from the X200 tablet. You need to find one without the glass touchscreen protection on it + (might be able to remove it, though). It also must not have a digitizer on it (again, might be possible to + just simply remove the digitizer). + </p> + <ul> + <li>BOE-Hydis HV121WX4-120, HV121WX4-110 or HV121WX4-100 - cheap-ish, might be hard to find</li> + <li>Samsung LTN121AP02-001 - common to find, cheap</li> + </ul> + <p> + <b>If your X200 has an LED backlit panel in it, then you also need to get an inverter and harness cable + that is compatible with the CCFL panels. To see which panel type you have, see + <a href="#led_howtotell">#led_howtotell</a>. If you need the inverter/cable, here are part numbers: + 44C9909 for CCFL LVDS cable with bluetooth and camera connections, and 42W8009 or 42W8010 for the + inverter.</b> + </p> + <p> + There are glossy and matte versions of these. Matte means anti-glare, which is what you want (in this authors opinion). + </p> + <p> + Refer to the HMM (hardware maintenance manual) for how to replace the screen. + </p> + <p>Sources:</p> + <ul> + <li><a href="http://forum.thinkpads.com/viewtopic.php?f=2&t=84941">ThinkPad Forums - Matte AFFS Panel on X200</a></li> + <li><a href="http://forum.thinkpads.com/viewtopic.php?p=660662#p660662">ThinkPad Forums - Parts for X200 AFFS Mod</a></li> + <li><a href="http://thinkwiki.de/X200_Displayumbau">ThinkWiki.de - X200 Displayumbau</a> (achtung: du musst lesen und/oder spreche deutsch; + oder ein freund fur hilfe)</li> + </ul> + <h3>X200s</h3> + <p> + <a href="http://forum.thinkpads.com/viewtopic.php?p=618928#p618928">http://forum.thinkpads.com/viewtopic.php?p=618928#p618928</a> + explains that the X200s screens/assemblies are thinner. You need to replace the whole lid with one from a normal X200/X201. + </p> + + <p> + <a href="#pagetop">Back to top of page.</a> + </p> + +<hr/> + + <h1 id="led_howtotell">How to tell if it has an LED or CCFL?</h1> + + <p> + Some X200's have a CCFL backlight and some have an LED backlight, in their LCD panel. This + also means that the inverters will vary, so you must be careful if ever replacing either + the panel and/or inverter. (a CCFL inverter is high-voltage and will destroy an LED backlit panel). + </p> + <p> + CCFL's contain mercury. An X200 with a CCFL backlight will (<b></b>unless it has been changed to an LED, + with the correct inverter. Check with your supplier!</b>) the following: <i>"This product + contains Lithium Ion Battery, Lithium Battery and a lamp which contains mercury; dispose according to + local, state or federal laws"</i> (one with an LED backlit panel will say something different). + </p> + <p> + <a href="#pagetop">Back to top of page.</a> + </p> + +<hr/> + + <p> + Copyright © 2014 Francis Rowe <info@gluglug.org.uk><br/> + This document is released under the Creative Commons Attribution-ShareAlike 4.0 International Public License and all future versions. + A copy of the license can be found at <a href="../license.txt">../license.txt</a>. + </p> + + <p> + This document is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See <a href="../license.txt">../../license.txt</a> for more information. + </p> + +</body> +</html> diff --git a/docs/hcl/x200_remove_me.html b/docs/hcl/x200_remove_me.html new file mode 100644 index 00000000..97937375 --- /dev/null +++ b/docs/hcl/x200_remove_me.html @@ -0,0 +1,563 @@ +<!DOCTYPE html> +<html> +<head> + <meta charset="utf-8"> + <meta name="viewport" content="width=device-width, initial-scale=1"> + + <style type="text/css"> + @import url('../css/main.css'); + </style> + + <title>ThinkPad X200: remove the ME (manageability engine)</title> +</head> + +<body> + + <h1 id="pagetop">ThinkPad X200: remove the ME (manageability engine)</h1> + <p> + This sections relates to disabling and removing the ME (Intel <b>M</b>anagement <b>E</b>ngine) + on the ThinkPad X200. + </p> + <p> + The ME is a blob that typically must be left inside the flash chip (in the ME region, as outlined + by the default descriptor). On the X200, it is possible to remove it without any ill effects. All + other parts of coreboot on the X200 can be blob-free, so removing the ME was the last obstacle to + get X200 support in libreboot (the machine can also work without the microcode blobs). + </p> + <p> + Or <a href="x200.html">back to main X200 compatibility page (x200.html)</a>. + </p> + +<hr/> + + <h1 id="ich9deblob">ICH9 deblob utility</h1> + + <p> + This is what you will use to generate the deblobbed descriptor+gbe regions for your libreboot ROM image. + </p> + <p> + If you are working with libreboot_src (or git), you can find the source under resources/utilities/ich9deblob/ + and will already be compiled if you ran ./builddeps or ./builddeps-ich9deblob from the main directory (./), + otherwise you can build it like so:<br/> + $ <b>./builddeps-ich9deblob</b><br/> + An executable file named <b>ich9deblob</b> will now appear under resources/utilities/ich9deblob/ + </p> + <p> + If you are working with libreboot_bin release archive, you can find the utility included, statically compiled + (for i686 and x86_64 on GNU/Linux) under ./ich9deblob/. + </p> + + <p> + Place the factory.rom from your X200 + (can be obtained using the guide at <a href="../install/x200_external.html">../install/x200_external.html</a>) in + the directory where you have your ich9deblob executable, then run the tool:<br/> + $ <b>./ich9deblob</b> + </p> + <p> + A 12kiB file named <b>deblobbed_descriptor.bin</b> will now appear. <b>Keep this and the factory.rom stored in a safe location!</b> + The first 4KiB contains the descriptor data region for your machine, and the next 8KiB contains the gbe region (config data for your + gigabit NIC). These 2 regions could actually be separate files, but they are joined into 1 file in this case. + </p> + + <p> + Assuming that your X200 libreboot image is named <b>libreboot.rom</b>, copy + the <b>deblobbed_descriptor.bin</b> file to where <b>libreboot.rom</b> is located + and then run:<br/> + $ <b>dd if=deblobbed_descriptor.bin of=libreboot.rom bs=1 count=12k conv=notrunc</b> + </p> + + <p> + You should now have a <b>libreboot.rom</b> image containing the correct 4K descriptor and 8K gbe regions, which + will then be safe to flash. Refer back to <a href="../install/index.html#flashrom_x200">../install/index.html#flashrom_x200</a> + for how to flash it. + </p> + +<hr/> + + <p> + The sections below are adapted from (mostly) IRC logs related to early development getting the ME removed on the X200. + They are useful for background information. This could not have been done without sgsit's help. + </p> + + <div class="section"> + + <h2 id="early_notes">Early notes</h2> + + <ul> + <li> + <a href="http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-10-family-datasheet.pdf">http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-10-family-datasheet.pdf</a> + page 230 mentions about descriptor and non-descriptor mode (which wipes out gbe and ME/AMT). + </li> + <li> + <s><b>See reference to HDA_SDO (disable descriptor security)</b></s> + strap connected GPIO33 pin is it on ICH9-M (X200). HDA_SDO applies to later chipsets (series 6 or higher). + Disabling descriptor security also disables the ethernet according to sgsit. sgsit's method + involves use of 'soft straps' (see IRC logs below) instead of disabling the descriptor. + </li> + <li> + <b>and the location of GPIO33 on the x200s: (was an external link. Putting it here instead)</b> + <a href="images/x200/gpio33_location.jpg">images/x200/gpio33_location.jpg</a> + - it's above the number 7 on TP37 (which is above the big intel chip at the bottom) + </li> + <li> + The ME datasheet may not be for the mobile chipsets but it doesn't vary that much. + This one gives some detail and covers QM67 which is what the X201 uses: + <a href="http://www.intel.co.uk/content/dam/www/public/us/en/documents/datasheets/6-chipset-c200-chipset-datasheet.pdf">http://www.intel.co.uk/content/dam/www/public/us/en/documents/datasheets/6-chipset-c200-chipset-datasheet.pdf</a> + </li> + </ul> + + </div> + + <div class="section"> + + <h2 id="flashchips">Flash chips</h2> + + <ul> + <li> + Schematics for X200 laptop: <a href="http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006075.pdf">http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006075.pdf</a> + <b><s>- Page 20 and page 9 refer to SDA_HDO or SDA_HDOUT</s></b> only on series 6 or higher chipsets. ICH9-M (X200) does it with a strap connected to GPIO33 pin (see IRC notes below)<br/> + - According to page 29, the X200 can have any of the following flash chips: + <ul> + <li>ATMEL AT26DF321-SU 72.26321.A01 - this is a 32Mb (4MiB) chip</li> + <li>MXIC (Macronix?) MX25L3205DM2I-12G 72.25325.A01 - another 32Mb (4MiB) chip</li> + <li>MXIC (Macronix?) MX25L6405DMI-12G 41R0820AA - this is a 64Mb (8MiB) chip</li> + <li>Winbond W25X64VSFIG 41R0820BA - another 64Mb (8MiB) chip</li> + </ul> + sgsit says that the X200's with the 64Mb flash chips are (probably) the ones with AMT (alongside the ME), whereas + the 32Mb chips contain only the ME. + </li> + <li> + Schematics for X200s laptop: <a href="http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006104.pdf">http://pdf.datasheetarchive.com/indexerfiles/Datasheets-USER/DSAUPLD00006104.pdf</a>. + </li> + </ul> + + </div> + + <div class="section"> + + <h2 id="compatibility">Compatibility (without blobs)</h2> + + <p>sgsit said this: There are problems with the DMAR table and I get a kernel panic with KVM but day to day it's fine with no ME or microcode.</p> + + <p>Usual limitations apply for native graphics initialization (no VBT and/or INT10H and only GRUB works so no BIOS, so no DOS/Windows support + - who cares? There is no system but GNU, and Linux is one of it's kernels).</p> + + <p>When connecting the AC adapter while system is powered off, system will then power on. This probably happens in coreboot aswell. + It's a minor annoyance, but it should be fixed (if it's not already fixed by now).</p> + + <p>This method of disabling the ME leaves the flash descriptor and gbe in place (non-functional data, fully documented) + and disables the ME using soft straps. This means that the gigabit ethernet will still work (putting the machine in + non-descriptor mode would wipe it out, not to mention require hardware modifications that most users will be unwilling to make).</p> + + </div> + + <div class="section"> + + <h2 id="early_development_notes">Early development notes</h2> + + <p> + There is a tool called FITC which contains all the descriptor manipulation tools. This is what sgsit used initially; + it's proprietary software, for Windows, but it was useful for liberating the X200 and making it a real target in + libreboot. End justified means, and the software is no longer needed. + </p> + +<pre> +<sgsit> here's some output: +<b>Was a paste link. putting it here instead:</b> +<i> +Start (hex) End (hex) Length (hex) Area Name +----------- --------- ------------ --------- +00000000 003FFFFF 00400000 Flash Image + +00000000 00000FFF 00001000 Descriptor Region +00000004 0000000F 0000000C Descriptor Map +00000010 0000001B 0000000C Component Section +00000040 0000004F 00000010 Region Section +00000060 0000006B 0000000C Master Access Section +00000060 00000063 00000004 CPU/BIOS +00000064 00000067 00000004 Manageability Engine (ME) +00000068 0000006B 00000004 GbE LAN +00000100 00000103 00000004 ICH Strap 0 +00000104 00000107 00000004 ICH Strap 1 +00000200 00000203 00000004 MCH Strap 0 +00000EFC 00000EFF 00000004 Descriptor Map 2 +00000ED0 00000EF7 00000028 ME VSCC Table +00000ED0 00000ED7 00000008 Flash device 1 +00000ED8 00000EDF 00000008 Flash device 2 +00000EE0 00000EE7 00000008 Flash device 3 +00000EE8 00000EEF 00000008 Flash device 4 +00000EF0 00000EF7 00000008 Flash device 5 +00000F00 00000FFF 00000100 OEM Section +00001000 001F5FFF 001F5000 ME Region +001F6000 001F7FFF 00002000 GbE Region +001F8000 001FFFFF 00008000 PDR Region +00200000 003FFFFF 00200000 BIOS Region +</i> + +<sgsit> this is the one that's running on my machine at the moment: +<b>Was a paste link. Putting here instead:</b> +<i> +Start (hex) End (hex) Length (hex) Area Name +----------- --------- ------------ --------- +00000000 003FFFFF 00400000 Flash Image + +00000000 00000FFF 00001000 Descriptor Region +00000004 0000000F 0000000C Descriptor Map +00000010 0000001B 0000000C Component Section +00000040 0000004F 00000010 Region Section +00000060 0000006B 0000000C Master Access Section +00000060 00000063 00000004 CPU/BIOS +00000064 00000067 00000004 Manageability Engine (ME) +00000068 0000006B 00000004 GbE LAN +00000100 00000103 00000004 ICH Strap 0 +00000104 00000107 00000004 ICH Strap 1 +00000200 00000203 00000004 MCH Strap 0 +00000ED0 00000EF7 00000028 ME VSCC Table +00000ED0 00000ED7 00000008 Flash device 1 +00000ED8 00000EDF 00000008 Flash device 2 +00000EE0 00000EE7 00000008 Flash device 3 +00000EE8 00000EEF 00000008 Flash device 4 +00000EF0 00000EF7 00000008 Flash device 5 +00000EFC 00000EFF 00000004 Descriptor Map 2 +00000F00 00000FFF 00000100 OEM Section +00001000 00002FFF 00002000 GbE Region +00003000 00202FFF 00200000 BIOS Region + +Build Settings +-------------- +Flash Erase Size = 0x1000 + +</i> + +Tool used: +<sgsit> it's called 'Flash Image Tool' from the 4.x package +<sgsit> you drag a complete image into it and the the tool decomposes the various components +<sgsit> and allows you to set the soft straps + +This tool is proprietary, for Windows only, but was used to deblob the X200. End justified by means, and +the utility is no longer needed (sgsit's ich9deblob utility documented at the top of the page is now +used to create deblobbed descriptors). + +</pre> + + </div> + + <div class="section"> + + <h2 class="gbe_region"> + GBE (gigabit ethernet) region in SPI flash + </h2> + + <p> + Of the 8K, about 95% is 0xFF. + The data is the gbe region is fully documented in this public datasheet: + <a href="http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf">http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf</a> + </p> + +<pre> +<sgsit> this is the only content: +<b>Was a paste link. putting it here instead:</b> +<i> +00 1F 1F 1F 1F 1F 00 08 FF FF 83 10 FF FF FF FF +08 10 FF FF C3 10 EE 20 AA 17 F5 10 86 80 00 00 +01 0D 00 00 00 00 05 06 20 30 00 0A 00 00 8B 8D +02 06 40 2B 43 00 00 00 F5 10 AD BA F5 10 BF 10 +AD BA CB 10 AD BA AD BA 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 01 00 40 28 12 07 40 FF FF FF FF FF FF FF FF +FF FF FF FF FF FF FF FF FF FF FF FF FF FF D9 F0 +20 60 1F 00 02 00 13 00 00 80 1D 00 FF 00 16 00 +DD CC 18 00 11 20 17 00 DD DD 18 00 12 20 17 00 +00 80 1D 00 00 00 1F +</i> +<sgsit> the first part is the MAC address which I've set to all 0x1F +<sgsit> it's repeated half way through the 8k area. the rest is 0xFF +<sgsit> <b>it's not a blob - i've just found the intel docs with the full spec of the data there</b> +<sgsit> <b>thanks to mtjm: <a href="http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf">http://www.intel.co.uk/content/dam/doc/application-note/i-o-controller-hub-9m-82567lf-lm-v-nvm-map-appl-note.pdf</a></b> +<sgsit> so we have a mostly functional libre x200 +<sgsit> just need to sort some ACPI issues +</pre> + + <p> + The GBe region starts at 0x20A000 bytes from the *end* of a factory image and is 0x2000 bytes long. + In libreboot (deblobbed) the descriptor is set to put it directly after the initial 4K flash descriptor. + So the first 4K of the ROM is the descriptor, and then the next 8K is the gbe region. + </p> + +<pre> +<sgsit> interesting fact about the gbe checksum: it's supposed to add up to 0xBABA (in honour of Baba O'Reilly apparently) but it is actually 0x3ABA +<sgsit> either the checksum doesn't matter or the MSB of the checksum isn't checked. strange though +<sgsit> <a href="https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums">https://communities.intel.com/community/wired/blog/2010/10/14/how-to-basic-eeprom-checksums</a> +<sgsit> "One of those engineers loves classic rock music, so he selected 0xBABA" +<sgsit> 0xBABA and 0x3ABA only differ by the most significant bit. + +<sgsit> the checksum in the GBe region of my X200S is 0x34BA +<sgsit> when it should be 0xBABA +34BA is BABA in L33T speak. 3=B and 4=A. Thus, 34BA=BABA +Apparently these intel people have a sense of humour. +</pre> + + </div> + + <div class="section"> + + <h2 id="flash_descriptor_region">Flash descriptor region</h2> + + <p> + <a href="http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datasheet.pdf">http://www.intel.co.uk/content/dam/doc/datasheet/io-controller-hub-9-datasheet.pdf</a> + from page 850 onwards. This explains everything that is in the flash descriptor, which can be used to understand what libreboot + is doing about modifying it. + </p> + + <p> + How to deblob: + </p> + <ul> + <li>patch the number of regions present in the descriptor from 5 - 3</li> + <li>originally descriptor + bios + me + gbe + platform</li> + <li>modified = descriptor + bios + gbe</li> + <li>the next stage is to patch the part of the descriptor which defines the start and end point of each section</li> + <li>then cut out the gbe region and insert it just after the region</li> + <li>all this can be substantiated with public docs (ICH9 datasheet)</li> + <li>the final part is flipping 2 bits. Halting the ME via 1 MCH soft strap and 1 ICH soft strap</li> + <li>the part of the descriptor described there gives the base address and length of each region (bits 12:24 of each address)</li> + <li>to disable a region, you set the base address to 0xFFF and the length to 0</li> + <li>and you change the number of regions from 4 (zero based) to 2</li> + </ul> + + <p> + There's an interesting parameter called 'ME Alternate disable', which allows the ME to only handle hardware errata in the southbridge, + but disables any other functionality. This is similar to the 'ignition' in the 5 series and higher but using the standard firmware + instead of a small 128K version. Useless for libreboot, though. + </p> + + <p> + To deblob the x200, you chop out the platform and ME regions and correct the addresses in flReg1-4. + Then you set meDisable to 1 in ICHSTRAP0 and MCHSTRAP0. + </p> + + <p>How to patch the descriptor from the factory.rom dump</p> + <ul> + <li>map the first 4k into the struct (minus the gbe region)</li> + <li>set NR in FLMAP0 to 2 (from 4)</li> + <li>adjust BASE and LIMIT in flReg1,2,3,4 to reflect the new location of each region (or remove them in the case of Platform and ME)</li> + <li>set meDisable to 1/true in ICHSTRAP0 and MCHSTRAP0</li> + <li>extract the 8k GBe region and append that to the end of the 4k descriptor</li> + <li>output the 12k concatenated chunk</li> + <li>Then it can be dd'd into the first 12K part of a coreboot image.</li> + <li>the GBe region always starts 0x20A000 bytes from the end of the ROM</li> + </ul> + +<pre> +<sgsit> the data in the descriptor is little endian +<sgsit> and it represents bits 24:12 of the address (bits 12-24. written as 24:12 since bit 24 is more nearer to left than bit 12) +<sgsit> so x << 12 = address +-- +<sgsit> if it is in descriptor mode, the first 4 bytes will be 5A A5 F0 0F +-- +<fchmmr> so there are just 3 regions in libreboot (X200) rom then: +<fchmmr> * descriptor (4K) +<fchmmr> * gbe (8K) +<fchmmr> * bios (rest of flash chip. CBFS also set to occupy this whole size) +</pre> + + </div> + + <div class="section"> + + <h2 id="platform_data_region">platform data partition in boot flash (factory.rom / lenovo bios)</h2> + + <p> + Basically useless for libreboot. Removing it didn't cause any issues. + </p> + +<pre> +<mtjm> sgsit: thanks; have you checked what platform data partition has? my notes state that it has only a 448 byte fragment different from 0x00 or 0xff +<sgsit> mtjm: the contents of mine from the stock rom are here: +<b>Was a paste link. Moving it here:</b> +<i> +53 FC 75 06 91 CA FA 62 91 27 D9 BF 59 93 A6 03 +38 FA 2E 96 02 8C BD 1D F5 5F A6 6A 87 30 47 45 +25 70 9A 60 B9 62 FD 9D 64 E1 88 37 FB 59 17 C2 +91 B0 A5 25 26 9B 36 44 85 09 E4 02 CC 91 28 8F +01 FF 22 D9 7B AA 61 97 5B E6 EE 7D CD F2 7F B1 +83 74 36 88 6B 4C 4F D5 DF 11 1E DF C0 D9 87 48 +CA DC 57 B7 F9 65 E4 E5 78 BA 90 78 D7 1E CB 3B +C3 8E 34 27 B9 B7 29 3D AA 53 96 0B 7D F7 47 82 +C6 E2 08 CD 94 49 10 C4 6D BD B2 2F BD 84 1B 20 +EC 8C 7E 33 6A B0 20 8D A4 7C 10 61 AD 11 66 BA +8F B1 07 B1 52 C2 F0 B7 88 BB 3A 6F 27 8F C1 EA +F7 BF 82 11 92 39 44 51 AB 19 25 2B 8A 7A D1 66 +2B 82 FF CE C7 EC 78 E2 9F 47 BE C2 37 F7 5A 2E +A6 57 B6 B3 66 2B 2D 33 20 C6 4D F7 26 41 57 70 +DC 04 42 39 BD B8 96 71 3E B1 9C 13 76 BF E2 AC +DD 65 E1 82 D6 46 F3 39 EA B5 FE F6 56 3F B9 67 +DE 5E 08 8B 00 77 D9 94 D0 16 F0 97 BF A6 44 3A +C1 27 22 E1 7C DD 2F 15 A1 D5 53 61 2A 37 F8 E1 +94 8E 1F 3D 8F 79 08 37 09 45 AC 1B 33 75 FB 3D +1D 6E 67 22 3D C3 90 B4 F8 9E 31 09 6F 70 1F BC +9E 48 29 A0 1F 29 5E 1B B5 D3 C3 D7 6C 14 AE 63 +FE F3 3A 23 98 78 4C C9 7E 9E F0 A4 72 9F FF 25 +CC 6F 2B D1 41 27 00 A5 79 4A 37 D3 83 63 32 89 +FB 03 2C AE 6B 33 31 1A 5A A2 A8 C5 5E 1F A5 BD +40 A7 76 7D A9 AC AC 18 21 6D F6 74 7D 18 19 C4 +DE 6D D1 55 A0 C9 2C FD 6A 56 BB 1B 08 C1 B6 60 +16 B7 EB D3 8B D8 BC 41 5F D6 86 A5 45 F8 A7 99 +68 6E EA 4D EA B6 39 6E 9B 5D 0E 58 9B D8 00 00 +</i> +<sgsit> i've removed it - doesn't seem to have had any ill effect +<sgsit> the region is 32k but like yours the rest of it is 0x00 or 0xFF +<mtjm> mine is different; maybe it's just something that the BIOS used +<sgsit> i think that's the case +</pre> + + </div> + + <div class="section"> + + <h2 id="new_targets">New targets</h2> + +<pre> +R400, R500 +T400, T400s, T500 +W500 +X200, X200s, X200 Tablet, X301 +^ these are other gm45 targets for coreboot (not yet ported at the time of writing) that could be in libreboot one day +^ some of them have ATI or Intel graphics. Avoid ATI (proprietary video bios rom needed) + +<sgsit> from the mailing list where somebody was enquiring abouy an R400 port: +<sgsit> Your dmidecode.log shows that you have DDR2 memory. +<sgsit> Sadly, our current GM45 chipset code does only support DDR3 (which is used in the Roda RK9). +<sgsit> If this isn't a fault in your DMI tables and you really have DDR2 memory, porting coreboot will be especially hard (some more month of extra) +<sgsit> re DDR3 on the R400, that's really weird +<sgsit> mtjm will be able to confirm but maybe there's something messed up in the HW of the R400 because it reports DDR2 +<a href="text/r400/r400_dmidecode.txt">text/r400/r400_dmidecode.txt</a> is dmidecode output from factory bios on R400. + +Some of them use DDR2 memory, or DDR3 memory that is detected as DDR2, or they are GS45 chipset. Basically, some of +them involve the hell of getting raminit right. but these are all fine targets that could be ported to coreboot +based on the X200 port. +</pre> + + </div> + + <div class="section"> + + <h2 id="unsorted">Unsorted notes</h2> + +<pre> +<sgsit> do you know if it's possible to flash thinkpads over the LPC debug connector at the front edge? +<sgsit> that would make life much easier for machines like this +<sgsit> all the Wistron manufactured machines have this thing called a "golden finger", normally at the front edge of the board +<sgsit> you can plug a board in which gives diagnostic codes but i'm wondering whether it is capable of more +<sgsit> <a href="http://www.endeer.cz/bios.tools/bios.html">http://www.endeer.cz/bios.tools/bios.html</a> +</pre> + + <p> + sgsit couldn't use vt-x without microcode updates. setting vm to have 1 core made vm kernel panic. + setting vm to use 2 cores made host kernel panic. Might be possible to workaround this in qemu. + according to sgsit (if not, just use software-only virtualization, no acceleration) + <a href="http://download.intel.com/design/mobile/specupdt/320121.pdf">http://download.intel.com/design/mobile/specupdt/320121.pdf</a> + </p> + + </div> + + <div class="section"> + + <h2 class="x200s">X200S and X200T</h2> + + <p> + Only X200 is known to work so far. X200S and X200 Tablet have raminit issues at the time of writing + (GS45 chipset. X200 is GM45). + </p> + +<pre> +X200S issues (X200T probably also affected): +<sgsit> fchmmr: some light reading - <a href="https://www.cs.cmu.edu/~410/doc/minimal_boot.pdf">https://www.cs.cmu.edu/~410/doc/minimal_boot.pdf</a> +<sgsit> mentions RCOMP which is the current stumbling block +<sgsit> oh god - SFF platform unsupported in write i/o initialization. +<sgsit> i think the X200S is doomed +<sgsit> hi. i've just flashed the X200 image to an X200S and i'm getting the error "SFF platform unsupported in RCOMP initialization." after "Setting IGD memory frequencies for VCO #1.". can anyone point me in the right direction to resolve this? +<sgsit> full log here: <a href="text/x200s/cblog00.txt">text/x200s/cblog00.txt</a> +<sgsit> i've tried many different SODIMM combinations +<PaulePanter> sgsit: src/northbridge/intel/gm45/raminit.c: die("SFF platform unsupported in RCOMP initialization.\n"); +<PaulePanter> sgsit: Check the source why it gets there. Found with `git grep "SFF platform"`. +<sgsit> PaulePanter: thanks, i'll investigate +<sgsit> PaulePanter: damn, looks like GS45 is unsupported +<sgsit> pgeorgi: do you know if adding RCOMP and write i/o init support to GS45 is going to be a nightmare? or is it a matter of studying datasheets? did you write the GM45 raminit code? +<pgeorgi> sgsit: I helped write some parts, but nico was the principal author +<pgeorgi> sgsit: I think the ddr3 side is pretty complete +<fchmmr> nico_h ? +<sgsit> pgeorgi: is it possible that GM45 is marked as unsupported because it wasn't able to be tested? +<sgsit> *GS45 +<pgeorgi> sgsit: we wrote that specifically for gm45. gs45 is unsupported because nobody ever cared for it +<sgsit> i know that GS45 only supports 1066/1333 and GM45 supports 800 too. i wonder if that points to big differences in the ram init code +<pgeorgi> fchmmr: nico_h, yes +<sgsit> sorry i meant 667/800/1066 +<pgeorgi> sgsit: everything is possible. my approach on this (absent reasonable datasheet access) would be to trace the vendor bios with serialice, then compare against the gm45 code, since it's probably somewhat similar +<sgsit> pgeorgi: thanks for the advice. you've given me hope +<pgeorgi> of course, after testing that the current gm45 code isn't just blocked by something trivial (eg. a pci id test) +<sgsit> yes, i was going to try removing the die command first.. the laptop i'm working on has a WSON-8 flash chip so i'm going to have to get the soldering iron out again. boo +<kmalkki> sgsit: some lenovo boards have WSON-8 and SOIC-8 layout on the PCB in parallel +<kmalkki> sgsit: does the silk screen have SPI1 and SPI2 ? +<sgsit> kmalkki: on the X200S the land array can take a SOIC-8 too. i don't (yet) have a hot air rework tool though +<sgsit> only thing is the supported SOIC-8 chips on that board are all 4MiB +<kmalkki> sgsit: you can switch from WSON-8 to SOIC-8 if you have matching IDs on the SPI flash part +<kmalkki> vendor bios might care, but for coreboot and flashrom you can switch to different SPI part entirely +<sgsit> but i was looking forward to having loads of free space to do interesting things with +<kmalkki> several options for 8MiB in SOIC-8 +<sgsit> kmalkki: sorry, i hadn't realised the significance of what you were saying. i actually have some new MX25L6445EM2I-10G here which i could probably swap over then. would flashing internally, using the ICH be a problem? +<kmalkki> sgsit: change of SPI flash part may confuse vendor BIOS and may require (simple) coreboot and flashrom development work +<kmalkki> sgsit: internal flashing is only issue once your system boots to OS +<sgsit> fchmmr: i have renewed hope for the X200S. after digging through the datasheet, i've discovered that the GS45 operates in 2 modes. +<sgsit> low and high performance +<sgsit> low performance uses the SU range of ultra-low voltage chips eg SU9400 +<sgsit> my X200S has an SL9400 which is in the high-performance category +<sgsit> from the docs, the GS45 behaves just like the GM45 when it's in high performance mode. +<sgsit> i expect / hope that the coreboot devs were wary of the other mode. with any luck, if i remove the checks (or hardcode the sff param to 0) the board may just boot up. i may have time to try this later +<sgsit> <fchmmr> I take it that the low-performance ones still wouldn't work, so for now you'd have to be careful to get one that has a particular cpu in it. +<sgsit> that's my assumption +<sgsit> orly_owl: no, i don't think so. the ulv cpus run at a different voltage. this is good news though, unless you buy an SUxxxx model +<sgsit> fchmmr: my hand crafted and untested patch for raminit.c: +<sgsit> --- +<sgsit> 113 +<sgsit> +++ sysinfo->gs45_low_power_mode = 1; +<sgsit> 113 sysinfo->gs45_low_power_mode = 0; +<sgsit> --- +<sgsit> 1696 const int sff = sysinfo->gfx_type == GMCH_GS45; +<sgsit> +++ +<sgsit> 1696 const int sff = sysinfo->gfx_type == GMCH_GS45 && sysinfo->gs45_low_power_mode = 1; +<sgsit> * 1696 const int sff = sysinfo->gfx_type == GMCH_GS45 && sysinfo->gs45_low_power_mode == 1; +<sgsit> i'll try it later +<sgsit> it assumes that GS45 is in high performance mode rather than low power which is no good for the masses +<sgsit> fchmmr: progress ;) +<sgsit> <a href="text/x200s/cblog01.txt">text/x200s/cblog01.txt</a> +<sgsit> doesn't like my 2GB dimms but it at least boots with 2x4GB +<sgsit> haven't put it back together yet so no idea if it's stable +<sgsit> note line 12 - GMCH: GS45, using high performance mode by default +<sgsit> with the patch i wrote blind earlier +<sgsit> needs testing +<sgsit> may be barely functional +<sgsit> and has problems with some SODIMMS +<sgsit> <a href="text/x200s/cblog02.txt">text/x200s/cblog02.txt</a> (2x2GB) +<sgsit> <a href="text/x200s/cblog03.txt">text/x200s/cblog03.txt</a> (1x2GB) +<sgsit> the GS45 in high performance mode is just a shrunken GM45 afaict +</pre> + + </div> + +<hr/> + + <p> + Copyright © 2014 Francis Rowe <info@gluglug.org.uk><br/> + This document is released under the Creative Commons Attribution-ShareAlike 4.0 International Public License and all future versions. + A copy of the license can be found at <a href="../license.txt">../license.txt</a>. + </p> + + <p> + This document is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See <a href="../license.txt">../../license.txt</a> for more information. + </p> + +</body> +</html> diff --git a/docs/install/images/x200/5252_bbb0.jpg b/docs/install/images/x200/5252_bbb0.jpg Binary files differnew file mode 100644 index 00000000..8232d8dd --- /dev/null +++ b/docs/install/images/x200/5252_bbb0.jpg diff --git a/docs/install/images/x200/5252_bbb1.jpg b/docs/install/images/x200/5252_bbb1.jpg Binary files differnew file mode 100644 index 00000000..a4e72e24 --- /dev/null +++ b/docs/install/images/x200/5252_bbb1.jpg diff --git a/docs/install/images/x200/mat.jpg b/docs/install/images/x200/mat.jpg Binary files differnew file mode 100644 index 00000000..6a62f4ec --- /dev/null +++ b/docs/install/images/x200/mat.jpg diff --git a/docs/install/images/x200/psu_jumper_leads.jpg b/docs/install/images/x200/psu_jumper_leads.jpg Binary files differnew file mode 100644 index 00000000..04bbf301 --- /dev/null +++ b/docs/install/images/x200/psu_jumper_leads.jpg diff --git a/docs/install/images/x200/psu_power.jpg b/docs/install/images/x200/psu_power.jpg Binary files differnew file mode 100644 index 00000000..c85bb344 --- /dev/null +++ b/docs/install/images/x200/psu_power.jpg diff --git a/docs/install/images/x200/psu_screws_removed.jpg b/docs/install/images/x200/psu_screws_removed.jpg Binary files differnew file mode 100644 index 00000000..e9ab9d7f --- /dev/null +++ b/docs/install/images/x200/psu_screws_removed.jpg diff --git a/docs/install/images/x200/strap.jpg b/docs/install/images/x200/strap.jpg Binary files differnew file mode 100644 index 00000000..39a23b18 --- /dev/null +++ b/docs/install/images/x200/strap.jpg diff --git a/docs/install/images/x200/stripped_jumper_lead.jpg b/docs/install/images/x200/stripped_jumper_lead.jpg Binary files differnew file mode 100644 index 00000000..54373a04 --- /dev/null +++ b/docs/install/images/x200/stripped_jumper_lead.jpg diff --git a/docs/install/images/x200/wson_soldered.jpg b/docs/install/images/x200/wson_soldered.jpg Binary files differnew file mode 100644 index 00000000..9a964a20 --- /dev/null +++ b/docs/install/images/x200/wson_soldered.jpg diff --git a/docs/install/images/x200/x200_pomona.jpg b/docs/install/images/x200/x200_pomona.jpg Binary files differnew file mode 100644 index 00000000..602fe1b5 --- /dev/null +++ b/docs/install/images/x200/x200_pomona.jpg diff --git a/docs/install/index.html b/docs/install/index.html index bfae94e7..7bd670d8 100644 --- a/docs/install/index.html +++ b/docs/install/index.html @@ -26,6 +26,7 @@ <li><a href="#flashrom_lenovobios">X60/X60S/X60T/T60: How to flash your ROM (if running Lenovo BIOS firmware)</a></li> <li><a href="#flashrom_macbook21">macbook21: How to flash your ROM (if running Apple EFI firmware)</a></li> <li><a href="#flashrom">X60/X60S/X60T/T60/macbook21: How to flash your ROM (if running libreboot or coreboot already)</a></li> + <li><a href="#flashrom_x200">X200: Flashing libreboot (hardware or software)</a></li> </ul> <h2>Installing libreboot (hardware)</h2> @@ -46,6 +47,7 @@ <li>ThinkPad X60, X60s: <b>bin/x60/</b></li> <li>ThinkPad X60 Tablet: <b>bin/x60t/</b></li> <li>ThinkPad T60: <b>bin/t60/</b> (note, see <a href="../hcl/index.html#supported_t60_list">../hcl/index.html#supported_t60_list</a>)</li> + <li>ThinkPad X200: <b>bin/x200_8mb/</b> (8MiB flash chip) or <b>bin/x200_4mb</b> (4MiB flash chip) (see <a href="../hcl/x200.html">../hcl/x200.html</a>)</li> <li>Apple MacBook2,1: <b>bin/macbook21/</b></li> <li>Apple MacBook1,1: <b>bin/macbook21/</b> (it's not a typo; the same ROM's work)</li> </ul> @@ -75,7 +77,7 @@ <p> <b><i>boardname</i></b> should be replaced with one of the following: <b>macbook21</b>, <b>t60</b>, - <b>x60</b> or <b>x60t</b>. + <b>x60</b>, <b>x60t</b>, <b>x200_8mb</b> or <b>x200_4mb</b>. </p> <p> @@ -398,6 +400,23 @@ </p> <p><a href="#pagetop">Back to top of page</a></p> + +<hr/> + + <h1 id="flashrom_x200">X200: Flashing libreboot (hardware or software)</h1> + + <p> + If your X200 is running the original firmware (Lenovo BIOS), follow the instructions at + <a href="x200_external.html">x200_external.html</a> first. + </p> + + <p> + Software flashing instructions not written yet (TODO). + </p> + + <p> + <a href="#pagetop">Back to top of page.</a> + </p> <hr/> diff --git a/docs/install/x200_external.html b/docs/install/x200_external.html new file mode 100644 index 00000000..4b990a0c --- /dev/null +++ b/docs/install/x200_external.html @@ -0,0 +1,444 @@ +<!DOCTYPE html> +<html> +<head> + <meta charset="utf-8"> + <meta name="viewport" content="width=device-width, initial-scale=1"> + + <style type="text/css"> + @import url('../css/main.css'); + </style> + + <title>ThinkPad X200: flashing tutorial (BeagleBone Black)</title> +</head> + +<body> + + <header> + <h1 id="pagetop">Flashing the X200 with a BeagleBone Black</h1> + <aside>Initial flashing instructions for X200.</aside> + </header> + + <p> + This guide is for those who want libreboot on their ThinkPad X200 + while they still have the original Lenovo BIOS present. This guide + can also be followed (adapted) if you brick your X200, to know how + to recover. + </p> + + <p> + The X200S is also briefly covered (image showing soldering joints, wired up + to a BBB). Note, the X200S and X200T are unsupported both in coreboot an libreboot at the time of writing (raminit doesn't work). This info +is just for future reference. <b>Only the X200 is supported.</b> + </p> + + <p> + Before following this section, please make sure to setup your libreboot ROM properly first. + Although ROM images are provided pre-built in libreboot, there are some modifications that + you need to make to the one you chose before flashing. (instructions referenced later in + this guide) + </p> + + <p>Or go <a href="index.html">back to main index</a></p> + +<hr/> + + <h1 id="hardware_requirements">Hardware requirements</h1> + + <p> + There are two possible flash chip sizes for the X200: 4MiB + (32Mbit) or 8MiB (64Mbit). This can be identified by the type + of flash chip below the palmrest: 4MiB is SOIC-8 (8 pins), 8MiB + is SOIC-16 (16 pins). The X200S uses a WSON package and has the same + pinout as SOIC-8 (covered briefly later on in this guide) but + the chip is on the underside of the board (disassembly required). + </p> + + <p> + Shopping list (pictures of this hardware is shown later): + </p> + <ul> + <li> + External SPI programmer: <b>BeagleBone Black</b> (rev. C) + is highly recommended. Sometimes referred to as 'BBB'. + </li> + <li> + Clip for connecting to the flash chip: <b>Pomona 5250</b> + (SOIC-8) or <b>Pomona 5250</b> (SOIC-16) is recommended + </li> + <li> + <b>External 3.3V DC power supply</b>. The one used by this + author has the label HF100W-SF-3.3 on it, but any decent + supply will be fine. Some people use the 3.3V from an ATX + PSU for instance (the kind that you get on a typical + Intel/AMD desktop computer. 6A supply should be fine, + the one used by this author is 20A (it won't actually use + that, it's just what the PSU is capable of). + </li> + <li> + Dupont <b>jumper cables</b> (the kinds of cables that you see + used on the pins on a raspberry pi - note: the pi is + proprietary and not endorsed by libreboot, merely refered + to in this instance to let you know the type of cables. + You should get male-male, male-female and female-female + cables in 10cm and 20cm sizes. + </li> + <li> + <b>Mini USB A-B cable</b> (the BeagleBone probably already comes + with one.) + </li> + <li> + <b>FTDI serial board</b>, for unbricking the BeagleBone if + necessary. + </li> + <li> + <b>5V DC power supply</b> (from wall outlet to the BeagleBone). + The BeagleBone can have power supplied via USB, but a + dedicated power supply is recommended. + </li> + </ul> + + <p> + <a href="#pagetop">Back to top of page.</a> + </p> + +<hr/> + + <h1 id="configure_bbb">Configuring the BeagleBone Black</h1> + + <h2>Setting up the 3.3V DC PSU</h2> + <p> + With my PSU, first I had wire up the mains power cable. Any clover or kettle lead will do. Cut the end off (not the one + that goes in the wall, but the kettle/clover connector). + Strip the protection away by a decent length, then strip the wires inside so that a decent amount of + copper is shown. Then wire up earth/live/neutral. This will vary according to what country you live in + and/or the colour codes that your cable uses inside. <b>Make sure to get this right, as a botched job + could result in extreme damage to you and your surroundings. Here's what mine looks like after wiring up + the power cable: <a href="images/x200/psu_power.jpg">images/x200/psu_power.jpg</a> - also, make sure + that the plug (for the wall) has the correct fuse. In my case I had a 240V wall socket, and the device + says that it accepts 1.5A at that voltage, so I used the smallest fuse available (3A). For 110-120V the device + says it needs 2.8A.</b> Also, if yours looks like in the image linked above, make sure to wrap electrical tape (lots) + around it for safety. (otherwise, don't touch the terminals while the PSU is plugged in). + </p> + <p> + Now take a red and black 20cm female-female jumper lead, and cut one of the ends off. Strip away the bare copper by about 1 or + 1.5cm so you get this: <a href="images/x200/stripped_jumper_lead.jpg">images/x200/stripped_jumper_lead.jpg</a>. + </p> + <p> + Black goes on -V, red goes on +V. In my case, I removed those screws from my PSU like this: + <a href="images/x200/psu_screws_removed.jpg">images/x200/psu_screws_removed.jpg</a>. Then, + </p> + <p> + Then I twisted the exposed copper on the jumper leads (so that they don't fray), and wrapped each to one of the + screws each, around it near the head. I then screwed them in: + <a href="images/x200/psu_jumper_leads.jpg">images/x200/psu_jumper_leads.jpg</a>. + </p> + <p> + If you are using a different PSU, then the steps will change from those above. Anyway, once you are satisfied, + continue reading... + </p> + <h2>Setting up the BBB</h2> + <p> + Since it's a bare board (no case) and you are also touching inside your X200, you should be earthed/grounded. + <a href="images/x200/strap.jpg">images/x200/strap.jpg</a> shows how I earthed myself. This is to prevent you + from causing any ESD damage. The surface that you place components on should also be earthed/grounded. + (for this, I used a shielded ESD bag with a wire, copper exposed, attached from the bag to the exposed metal + part on a radiator, which was earthed - not professional, but it should work. see <a href="images/x200/mat.jpg">images/x200/mat.jpg</a>). + Most people ignore this advice and don't ground/earth themselves, at their own risk. You should also store the BBB + in a shielded anti-static bag when you are finished with it. + (the principles above apply to any computer components, since they are extremely sensitive te ESD). + </p> + <p> + These instructions may or may not work for you. They are simply the steps that this author took. + </p> + <p> + setting up SPIDEV on the BBB: <a href="http://elinux.org/BeagleBone_Black_Enable_SPIDEV#SPI0">http://elinux.org/BeagleBone_Black_Enable_SPIDEV#SPI0</a> + - If you only setup SPI0, you don't have to disable the HDMI out. (you only need one). + That guide is for seting up the device overlay for SPIDEV, last part is to make it persist across reboots. + Needed to turn the BBB into an SPI flasher. + </p> + <p> + Don't bother modifying uEnv.txt. it won't work; + use the workaround here instead: <a href="http://elinux.org/Beagleboard:BeagleBoneBlack_Debian#Loading_custom_capes">http://elinux.org/Beagleboard:BeagleBoneBlack_Debian#Loading_custom_capes</a>. + </p> + <p> + Follow the instructions at <a href="http://elinux.org/BeagleBone_Black_Enable_SPIDEV#SPI0">http://elinux.org/BeagleBone_Black_Enable_SPIDEV#SPI0</a> + up to (and excluding) the point where it tells you to modify uEnv.txt + </p> + <p> + You need to update the software on the BBB first. Before being able to use apt-get, + I had to use the workaround defined <a href="https://groups.google.com/forum/?_escaped_fragment_=msg/beagleboard/LPjCn4LEY2I/alozBGsbTJMJ#!msg/beagleboard/LPjCn4LEY2I/alozBGsbTJMJ">here</a>:<br/> + - Replace the contents of /etc/init.d/led_aging.sh with: + </p> +<pre> +#!/bin/sh -e +### BEGIN INIT INFO +# Provides: led_aging.sh +# Required-Start: $local_fs +# Required-Stop: $local_fs +# Default-Start: 2 3 4 5 +# Default-Stop: 0 1 6 +# Short-Description: Start LED aging +# Description: Starts LED aging (whatever that is) +### END INIT INFO + +x=$(/bin/ps -ef | /bin/grep "[l]ed_acc") +if [ ! -n "$x" -a -x /usr/bin/led_acc ]; then + /usr/bin/led_acc & +fi +</pre> + </p> + Run <b>apt-get update</b> and <b>apt-get upgrade</b> then reboot the BBB, before continuing. + </p> + <p> + Run those commands:<br/> + # <b>echo BB-SPI0-01 > /sys/devices/bone_capemgr.*/slots</b><br/> + Then I did:<br/> + # <b>ls -al /dev/spidev0.*</b><br/> + <i>ls: cannot access /dev/spidev0.*: No such file or directory</i><br/> + Then I rebooted and did:<br/> + # <b>cat /sys/devices/bone_capemgr.*/slots</b><br/> + Output: + </p> +<pre> + 0: 54:PF--- + 1: 55:PF--- + 2: 56:PF--- + 3: 57:PF--- + 4: ff:P-O-L Bone-LT-eMMC-2G,00A0,Texas Instrument,BB-BONE-EMMC-2G + 5: ff:P-O-L Bone-Black-HDMI,00A0,Texas Instrument,BB-BONELT-HDMI +</pre> + <p> + And then:<br/> + # <b>ls /lib/firmware/BB-SPI0-01-00A0.*</b><br/> + Output: + </p> +<pre> +/lib/firmware/BB-SPI0-01-00A0.dtbo +</pre> + <p> + Then:<br/> + # <b>echo BB-SPI0-01 > /sys/devices/bone_capemgr.*/slots</b><br/> + # <b>cat /sys/devices/bone_capemgr.*/slots</b><br/> + Output: + </p> +<pre> + 0: 54:PF--- + 1: 55:PF--- + 2: 56:PF--- + 3: 57:PF--- + 4: ff:P-O-L Bone-LT-eMMC-2G,00A0,Texas Instrument,BB-BONE-EMMC-2G + 5: ff:P-O-L Bone-Black-HDMI,00A0,Texas Instrument,BB-BONELT-HDMI + 7: ff:P-O-L Override Board Name,00A0,Override Manuf,BB-SPI0-01 +</pre> + <p> + Then check if the device exists:<br/> + # <b>ls -al /dev/spidev0.*</b><br/> + Output: + </p> +<pre> +ls: cannot access /dev/spidev0.*: No such file or directory +</pre> + <p> + It didn't exist under that name, but I then did:<br/> + # <b>ls -al /dev/spid*</b><br/> + Output: + </p> +<pre> +crw-rw---T 1 root spi 153, 0 Nov 19 21:07 /dev/spidev1.0 +</pre> + <p> + Now the BBB is ready to be used for flashing. Make this persist + across reboots:<br/> + In /etc/default/capemgr add <b>CAPE=BB-SPI0-01</b> at the end + (or change the existing <b>CAPE=</b> entry to say that, if an + entry already exists. + </p> + <p> + Now you will download and build <b>flashrom</b> on the BBB.<br/> + # <b>apt-get install libpci-dev pciutils zlib1g-dev libftdi-dev build-essential subversion</b><br/> + # <b>svn co svn://flashrom.org/flashrom/trunk flashrom</b><br/> + # <b>cd flashrom/</b><br/> + # <b>make</b> + </p> + + <p> + Now test flashrom:<br/> + # <b>./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512</b><br/> + Output: + </p> +<pre> +Calibrating delay loop... OK. +No EEPROM/flash device found. +Note: flashrom can never write if the flash chip isn't found automatically. +</pre> + + <p> + This means that it's working (the clip isn't connected to any flash chip, + so the error is fine). + </p> + <h2> + Connecting the Pomona 5250/5252 + </h2> + <p> + Use this image for reference when connecting the pomona to the BBB: + <a href="http://beagleboard.org/Support/bone101#headers">http://beagleboard.org/Support/bone101#headers</a> + (D0 = MISO or connects to MISO). + </p> + + <p> + The following shows how to connect clip to the BBB (on the P9 header), for SOIC-16 (clip: Pomona 5252): + </p> +<pre> +=== front (display) ==== + NC - - 21 + 1 - - 17 + NC - - NC + NC - - NC + NC - - NC + NC - - NC + 18 - - 3.3V PSU RED + 22 - - NC - this is pin 1 on the flash chip +=== back (palmrest) === +<i>This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack.</i> +</pre> + <p> + The following shows how to connect clip to the BBB (on the P9 header), for SOIC-8 (clip: Pomona 5250): + </p> +<pre> +=== front (display) ==== + 18 - - 1 + 22 - - NC + NC - - 21 + 3.3V PSU RED - - 17 - this is pin 1 on the flash chip +=== back (palmrest) === +<i>This is how you will connect. Numbers refer to pin numbers on the BBB, on the plugs near the DC jack.</i> +<b>On the X200S (not fully covered in this guide) the flash chip is underneath the board, in a WSON package. +The pinout is very much the same as a SOIC-8, except you need to solder (there are no clips available). +<a href="images/x200/wson_soldered.jpg">images/x200/wson_soldered.jpg</a> (image copyright (C) 2014 <a href="mailto:sgsit@libreboot.org">Steve Shenton</a> under CC-BY-SA 4.0 +or higher, same license that this document uses) shows it wired (soldered) and +connected to a BBB. Note, the X200S and X200T are unsupported both in coreboot an libreboot at the time of writing (raminit doesn't work). This info +is just for future reference.</b> +</pre> + <p> + <b>NC = no connection</b> + </p> + <p> + <b><u>DO NOT</u> connect 3.3V PSU RED yet. ONLY connect this once the pomona is connected to the flash chip.</b> + </p> + <p> + <b>You also need to connect the BLACK wire from the 3.3V PSU to pin 2 on the BBB (P9 header). It is safe to install this now.</b> + </p> + <p> + if you need to extend the 3.3v psu leads, just use the same colour M-F leads, <b>but</b> keep all other + leads short (10cm or less) + </p> + + <p> + <a href="images/x200/5252_bbb0.jpg">images/x200/5252_bbb0.jpg</a> and + <a href="images/x200/5252_bbb1.jpg">images/x200/5252_bbb1.jpg</a> shows a properly wired up BBB with Pomona + 5252 before being connected to the flash chip on the X200. + </p> + + <h2> + Connect Pomona 5252/5250 to the X200 flash chip, and dump/flash + </h2> + <p> + <a href="images/x200/x200_pomona.jpg">images/x200/x200_pomona.jpg</a> + shows everything connected. In this picture, the X200 is being flashed + with the BBB. + </p> + <p> + Remove the battery from your X200, then remove all the screws on + the bottom (underside) of the machine. Then remove the keyboard and palmrest. + The flash chip is below the palm rest. Lift back the tape that goes over it, + and then connect your 5252/5250 (make sure to get it the right way round). + Then connect the 3.3v PSU wire (red one) and make sure that everything else is connected. + </p> + <p> + I did:<br/> + # <b>./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512</b><br/> + In my case, the output was: + </p> +<pre> +flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) +flashrom is free software, get the source code at http://www.flashrom.org +Calibrating delay loop... OK. +Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. +Found Macronix flash chip "MX25L6406E/MX25L6436E" (8192 kB, SPI) on linux_spi. +Found Macronix flash chip "MX25L6445E/MX25L6473E" (8192 kB, SPI) on linux_spi. +Multiple flash chip definitions match the detected chip(s): "MX25L6405(D)", "MX25L6406E/MX25L6436E", "MX25L6445E/MX25L6473E" +Please specify which chip definition to use with the -c <chipname> option. +</pre> + <p> + This is just to test that it's working. In my case, I had to define which chip to use, like so (in your case + it may be different, depending on what flash chip you have):<br/> + # <b>./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -c "MX25L6405(D)"</b> + </p> + <p> + At this point, you need to create a copy of the original lenovo firmware that is currently flashed. + This is so that you can extract the gbe (gigabit ethernet) and flash descriptor regions for use in libreboot. <b>These + are not blobs, they only contain non-functional data (configuration details, fully readable) which is fully documented in public datasheets.</b> + The descriptor will need to be modified + to disable the ME (also disable AMT) so that you can flash a ROM that excludes it. + </p> + <p> + How to backup factory.rom (change the -c option as neeed, for your flash chip):<br/> + # <b>./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -c "MX25L6405(D)" -r factory.rom</b><br/> + # <b>./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -c "MX25L6405(D)" -r factory1.rom</b><br/> + # <b>./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -c "MX25L6405(D)" -r factory2.rom</b><br/> + Now compare the 3 images:<br/> + # <b>sha512sum factory*.rom</b><br/> + If the hashes match, then just copy one of them (the factory.rom) to a safe place (on a drive connected to another machine, not + the BBB). You will need it later for part of the deblobbing. + </p> + <p> + Information about the descriptor and gbe can be found in the notes linked at + <a href="../hcl/x200_remove_me.html">../hcl/x200_remove_me.html</a> - also shows how to modify them to disable and remove the ME/AMT blob. + <span style="font-size:1.5em; background:#ccc;"><b><u><i>MAKE SURE TO FOLLOW THE GUIDE IN THIS LINK, BEFORE CONTINUING. + FAILURE TO DO SO WILL RESULT IN A BRICKED MACHINE.</i></u></b></span> + </p> + <p> + Assuming that your libreboot ROM image is properly setup (modified descriptor plus gbe region included in the ROM), + then you can flash (assuming that the filename is <b>libreboot.rom</b>) for example I had to do:<br/> + # <b>./flashrom -p linux_spi:dev=/dev/spidev1.0,spispeed=512 -c "MX25L6405(D)" -w libreboot.rom</b> + </p> + <p> + You might see errors, but if it says <b>Verifying flash... VERIFIED</b> at the end, then it's flashed and should boot. + Test it! (boot your X200) + </p> + <p> + My output when running the command above: + </p> +<pre> +flashrom v0.9.7-r1854 on Linux 3.8.13-bone47 (armv7l) +flashrom is free software, get the source code at http://www.flashrom.org +Calibrating delay loop... OK. +Found Macronix flash chip "MX25L6405(D)" (8192 kB, SPI) on linux_spi. +Reading old flash chip contents... done. +Erasing and writing flash chip... FAILED at 0x00001000! Expected=0xff, Found=0x00, failed byte count from 0x00000000-0x0000ffff: 0xd716 +ERASE FAILED! +Reading current flash chip contents... done. Looking for another erase function. +Erase/write done. +Verifying flash... VERIFIED. +</pre> + + <p> + <a href="#pagetop">Back to top of page.</a> + </p> + +<hr/> + + <p> + Copyright © 2014 Francis Rowe <info@gluglug.org.uk><br/> + This document is released under the Creative Commons Attribution-ShareAlike 4.0 International Public License and all future versions. + A copy of the license can be found at <a href="../license.txt">../license.txt</a>. + </p> + + <p> + This document is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See <a href="../license.txt">../license.txt</a> for more information. + </p> + +</body> +</html> diff --git a/resources/libreboot/config/x200_4mb/config b/resources/libreboot/config/x200_4mb/config new file mode 100644 index 00000000..a58ca2fe --- /dev/null +++ b/resources/libreboot/config/x200_4mb/config @@ -0,0 +1,460 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_EXPERT=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_USE_OPTION_TABLE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_BROKEN_CAR_MIGRATE is not set +CONFIG_DYNAMIC_CBMEM=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_UPDATE_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_ADVANTECH is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARIMA is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASI is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AXUS is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_EAGLELION is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NEWISYS is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_TECHNOLOGIC is not set +# CONFIG_VENDOR_TELEVIDEO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x200" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X200" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_VGA_BIOS_ID="8086,2a42" +CONFIG_DRIVERS_PS2_KEYBOARD=y +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_UDELAY_IO=y +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_ACPI_SSDTX_NUM=0 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +# CONFIG_PCI_64BIT_PREF_MEM is not set +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x3FD000 +CONFIG_POST_IO=y +CONFIG_POST_DEVICE=y +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_X200=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_SEABIOS_PS2_TIMEOUT=0 +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +CONFIG_USBDEBUG=y +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_IOMMU=y +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +CONFIG_COREBOOT_ROMSIZE_KB_4096=y +# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=4096 +CONFIG_ROM_SIZE=0x400000 +CONFIG_ARCH_X86=y +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_ARM64 is not set +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0x100000 +CONFIG_STACK_SIZE=0x1000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_ROMCC is not set +CONFIG_PC80_SYSTEM=y +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_HPET_ADDRESS=0xfed00000 +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARM_BOOTBLOCK_CUSTOM is not set +# CONFIG_CPU_HAS_BOOTBLOCK_INIT is not set +# CONFIG_MAINBOARD_HAS_BOOTBLOCK_INIT is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM_V8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM_V8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM_V8_64 is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_CPU_TI_AM335X is not set +CONFIG_XIP_ROM_SIZE=0x10000 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_SMM_TSEG_SIZE=0 +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_UDELAY_LAPIC is not set +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_MODULES is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +CONFIG_HEAP_SIZE=0x4000 +CONFIG_VIDEO_MB=0 +CONFIG_RAMTOP=0x200000 +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_EHCI_BAR=0xfef00000 +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y + +# +# SoC +# +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_ON_DEVICE_ROM_RUN is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_AGP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCI_BUS_SEGN_BITS=0 +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_PXE_ROM is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +CONFIG_DRIVERS_GENERIC_IOAPIC=y +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_I2C_TPM is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_LPC_TPM is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +CONFIG_DRIVERS_UART=y +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_USBDEBUG_IN_ROMSTAGE=y +CONFIG_USBDEBUG_DEFAULT_PORT=0 +# CONFIG_USBDEBUG_DONGLE_STD is not set +# CONFIG_USBDEBUG_DONGLE_BEAGLEBONE is not set +CONFIG_USBDEBUG_DONGLE_BEAGLEBONE_BLACK=y +CONFIG_USBDEBUG_OPTIONAL_HUB_PORT=0 +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_TPM is not set +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +CONFIG_CONSOLE_USB=y +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_CONSOLE_PRERAM_BUFFER_SIZE=0xc00 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_HAVE_ACPI_SLIC is not set +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_PER_DEVICE_ACPI_TABLES=y +# CONFIG_COMMON_FADT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X200" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +# CONFIG_SEABIOS_VGA_COREBOOT is not set +CONFIG_PAYLOAD_FILE="grub.elf" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_USBDEBUG is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +CONFIG_MAX_REBOOT_CNT=3 diff --git a/resources/libreboot/config/x200_8mb/config b/resources/libreboot/config/x200_8mb/config new file mode 100644 index 00000000..ca1363de --- /dev/null +++ b/resources/libreboot/config/x200_8mb/config @@ -0,0 +1,460 @@ +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_EXPERT=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_SCONFIG_GENPARSER is not set +# CONFIG_USE_OPTION_TABLE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_EARLY_CBMEM_INIT=y +# CONFIG_BROKEN_CAR_MIGRATE is not set +CONFIG_DYNAMIC_CBMEM=y +# CONFIG_COLLECT_TIMESTAMPS is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_RELOCATABLE_MODULES is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +# CONFIG_UPDATE_IMAGE is not set + +# +# Mainboard +# +# CONFIG_VENDOR_AAEON is not set +# CONFIG_VENDOR_ABIT is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_ADVANTECH is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ARIMA is not set +# CONFIG_VENDOR_ARTECGROUP is not set +# CONFIG_VENDOR_ASI is not set +# CONFIG_VENDOR_ASROCK is not set +# CONFIG_VENDOR_ASUS is not set +# CONFIG_VENDOR_A_TREND is not set +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_AXUS is not set +# CONFIG_VENDOR_AZZA is not set +# CONFIG_VENDOR_BACHMANN is not set +# CONFIG_VENDOR_BCOM is not set +# CONFIG_VENDOR_BIFFEROS is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_BROADCOM is not set +# CONFIG_VENDOR_COMPAQ is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_DIGITALLOGIC is not set +# CONFIG_VENDOR_DMP is not set +# CONFIG_VENDOR_EAGLELION is not set +# CONFIG_VENDOR_ECS is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IBM is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_IWAVE is not set +# CONFIG_VENDOR_IWILL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LANNER is not set +CONFIG_VENDOR_LENOVO=y +# CONFIG_VENDOR_LINUTOP is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MITAC is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_NEC is not set +# CONFIG_VENDOR_NEWISYS is not set +# CONFIG_VENDOR_NOKIA is not set +# CONFIG_VENDOR_NVIDIA is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_RCA is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SOYO is not set +# CONFIG_VENDOR_SUNW is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TECHNEXION is not set +# CONFIG_VENDOR_TECHNOLOGIC is not set +# CONFIG_VENDOR_TELEVIDEO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_THOMSON is not set +# CONFIG_VENDOR_TRAVERSE is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_VIA is not set +# CONFIG_VENDOR_WINENT is not set +# CONFIG_VENDOR_WYSE is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="lenovo/x200" +CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X200" +CONFIG_IRQ_SLOT_COUNT=18 +CONFIG_MAINBOARD_VENDOR="LENOVO" +CONFIG_MAX_CPUS=2 +CONFIG_VGA_BIOS_ID="8086,2a42" +CONFIG_DRIVERS_PS2_KEYBOARD=y +# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set +# CONFIG_VGA_BIOS is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_UDELAY_IO=y +CONFIG_DCACHE_RAM_BASE=0xffaf8000 +CONFIG_DCACHE_RAM_SIZE=0x8000 +CONFIG_ACPI_SSDTX_NUM=0 +CONFIG_MMCONF_BASE_ADDRESS=0xf0000000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="LENOVO" +# CONFIG_PCI_64BIT_PREF_MEM is not set +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_CACHE_ROM_SIZE_OVERRIDE=0 +CONFIG_CBFS_SIZE=0x7FD000 +CONFIG_POST_IO=y +CONFIG_POST_DEVICE=y +# CONFIG_BOARD_LENOVO_X60 is not set +CONFIG_BOARD_LENOVO_X200=y +# CONFIG_BOARD_LENOVO_X201 is not set +# CONFIG_BOARD_LENOVO_X220 is not set +# CONFIG_BOARD_LENOVO_X230 is not set +# CONFIG_BOARD_LENOVO_T520 is not set +# CONFIG_BOARD_LENOVO_T530 is not set +# CONFIG_BOARD_LENOVO_T60 is not set +CONFIG_SEABIOS_PS2_TIMEOUT=0 +CONFIG_USBDEBUG_HCD_INDEX=2 +CONFIG_CPU_ADDR_BITS=36 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +CONFIG_USBDEBUG=y +CONFIG_MAINBOARD_VERSION="1.0" +CONFIG_IOMMU=y +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +CONFIG_ARCH_X86=y +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_ARM64 is not set +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0x100000 +CONFIG_STACK_SIZE=0x1000 +CONFIG_NUM_IPI_STARTS=2 +# CONFIG_ROMCC is not set +CONFIG_PC80_SYSTEM=y +CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/gm45/bootblock.c" +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801ix/bootblock.c" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +CONFIG_HPET_ADDRESS=0xfed00000 +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARM_BOOTBLOCK_CUSTOM is not set +# CONFIG_CPU_HAS_BOOTBLOCK_INIT is not set +# CONFIG_MAINBOARD_HAS_BOOTBLOCK_INIT is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM_V8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM_V8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM_V8_64 is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +CONFIG_SYSTEM_TYPE_LAPTOP=y + +# +# Chipset +# + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_CPU_TI_AM335X is not set +CONFIG_XIP_ROM_SIZE=0x10000 +# CONFIG_CPU_AMD_AGESA is not set +# CONFIG_CPU_AMD_PI is not set +CONFIG_CPU_INTEL_MODEL_1067X=y +CONFIG_SMM_TSEG_SIZE=0 +CONFIG_CPU_INTEL_SOCKET_BGA956=y +CONFIG_SSE2=y +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_UDELAY_LAPIC is not set +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +# CONFIG_TSC_CALIBRATE_WITH_IO is not set +# CONFIG_TSC_SYNC_LFENCE is not set +CONFIG_TSC_SYNC_MFENCE=y +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_MODULES is not set +# CONFIG_X86_AMD_FIXED_MTRRS is not set +# CONFIG_PLATFORM_USES_FSP is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_SMP=y +CONFIG_AP_SIPI_VECTOR=0xfffff000 +CONFIG_MMX=y +CONFIG_SSE=y +CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y +# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set +# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set +CONFIG_CPU_MICROCODE_CBFS_NONE=y + +# +# Northbridge +# +CONFIG_HEAP_SIZE=0x4000 +CONFIG_VIDEO_MB=0 +CONFIG_RAMTOP=0x200000 +# CONFIG_NORTHBRIDGE_AMD_AGESA is not set +# CONFIG_AMD_NB_CIMX is not set +# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_NORTHBRIDGE_INTEL_GM45=y +CONFIG_HPET_MIN_TICKS=0x80 +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_EHCI_BAR=0xfef00000 +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +CONFIG_SOUTHBRIDGE_INTEL_COMMON=y +CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y + +# +# Super I/O +# + +# +# Embedded Controllers +# +CONFIG_EC_ACPI=y +CONFIG_EC_LENOVO_H8=y +CONFIG_EC_LENOVO_PMH7=y + +# +# SoC +# +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set + +# +# Devices +# +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y +CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG=y +CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y +# CONFIG_VGA_ROM_RUN is not set +# CONFIG_ON_DEVICE_ROM_RUN is not set +# CONFIG_MULTIPLE_VGA_ADAPTERS is not set +# CONFIG_SPD_CACHE is not set +CONFIG_PCI=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +CONFIG_AGP_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +# CONFIG_PCIEXP_COMMON_CLOCK is not set +# CONFIG_PCIEXP_ASPM is not set +CONFIG_PCI_BUS_SEGN_BITS=0 +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_PXE_ROM is not set + +# +# Display +# +# CONFIG_FRAMEBUFFER_KEEP_VESA_MODE is not set + +# +# Generic Drivers +# +CONFIG_DRIVERS_GENERIC_IOAPIC=y +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_I2C_TPM is not set +CONFIG_DRIVERS_ICS_954309=y +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +CONFIG_INTEL_INT15=y +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_LPC_TPM is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_SPI_FLASH is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +CONFIG_DRIVERS_UART=y +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +CONFIG_USBDEBUG_IN_ROMSTAGE=y +CONFIG_USBDEBUG_DEFAULT_PORT=0 +# CONFIG_USBDEBUG_DONGLE_STD is not set +# CONFIG_USBDEBUG_DONGLE_BEAGLEBONE is not set +CONFIG_USBDEBUG_DONGLE_BEAGLEBONE_BLACK=y +CONFIG_USBDEBUG_OPTIONAL_HUB_PORT=0 +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_TPM is not set +CONFIG_MMCONF_SUPPORT_DEFAULT=y +CONFIG_MMCONF_SUPPORT=y +# CONFIG_BOOTMODE_STRAPS is not set + +# +# Console +# +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y + +# +# I/O mapped, 8250-compatible +# +CONFIG_TTYS0_BASE=0x3f8 +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +CONFIG_TTYS0_LCS=3 +# CONFIG_SPKMODEM is not set +CONFIG_CONSOLE_USB=y +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_CONSOLE_PRERAM_BUFFER_SIZE=0xc00 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO_PORT=0x80 +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_HAVE_ACPI_SLIC is not set +CONFIG_HAVE_HARD_RESET=y +# CONFIG_HAVE_MONOTONIC_TIMER is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +CONFIG_HAVE_SMI_HANDLER=y +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +CONFIG_USE_WATCHDOG_ON_BOOT=y +CONFIG_VGA=y +# CONFIG_GFXUMA is not set +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_PER_DEVICE_ACPI_TABLES=y +# CONFIG_COMMON_FADT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +# CONFIG_GENERATE_PIRQ_TABLE is not set +CONFIG_GENERATE_SMBIOS_TABLES=y +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="ThinkPad X200" + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +CONFIG_PAYLOAD_ELF=y +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_SEABIOS is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +# CONFIG_SEABIOS_VGA_COREBOOT is not set +CONFIG_PAYLOAD_FILE="grub.elf" +CONFIG_COMPRESSED_PAYLOAD_LZMA=y + +# +# Debugging +# +# CONFIG_GDB_STUB is not set +# CONFIG_DEBUG_CBFS is not set +CONFIG_HAVE_DEBUG_RAM_SETUP=y +# CONFIG_DEBUG_RAM_SETUP is not set +# CONFIG_HAVE_DEBUG_CAR is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_SMI is not set +# CONFIG_DEBUG_SMM_RELOCATION is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_USBDEBUG is not set +# CONFIG_TRACE is not set +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +CONFIG_MAX_REBOOT_CNT=3 diff --git a/resources/utilities/ich9deblob/ich9deblob.c b/resources/utilities/ich9deblob/ich9deblob.c new file mode 100644 index 00000000..612c75d4 --- /dev/null +++ b/resources/utilities/ich9deblob/ich9deblob.c @@ -0,0 +1,187 @@ +/* + * ich9deblob.c + * + * gcc -o ich9deblob ich9deblob.c ich9desc.c -I. + * + * Copyright (C) 2014 Steve Shenton <sgsit@libreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + + +#include <stdio.h> +#include <string.h> +#include "ich9desc.c" + +#define DESCRIPTORREGIONSIZE 0x1000 +#define GBEREGIONSIZE 0x2000 + +unsigned short GetChecksum(char* buffer, unsigned short desiredValue); +unsigned short GetRegionWord(int i, char* buffer); + +int main(int argc, char *argv[]) +{ + // check compiler bit-packs in a compatible way + struct DESCRIPTORREGIONRECORD descriptorRegion; + unsigned int descriptorRegionStructSize = sizeof(descriptorRegion); + + if (DESCRIPTORREGIONSIZE != descriptorRegionStructSize){ + printf("\nerror: compiler incompatibility: descriptor struct length is %i bytes (should be %i)\n", descriptorRegionStructSize, DESCRIPTORREGIONSIZE); + return 1; + } + + char* factoryRomFilename = "factory.rom"; + char* deblobbedDescriptorFilename = "deblobbed_descriptor.bin"; + + FILE* fp = NULL; + fp = fopen(factoryRomFilename, "rb"); + + if (NULL == fp) + { + printf("\nerror: could not open factory.rom\n"); + return 1; + } + + printf("\nfactory.rom opened successfully\n"); + + char descriptorBuffer[DESCRIPTORREGIONSIZE]; + + unsigned int readLen; + readLen = fread(descriptorBuffer, sizeof(char), DESCRIPTORREGIONSIZE, fp); + if (DESCRIPTORREGIONSIZE != readLen) + { + printf("\nerror: could not read descriptor from factory.rom (%i) bytes read\n", readLen); + return 1; + } + + printf("\ndescriptor region read successfully\n"); + + // copy descriptor buffer into descriptor struct memory + memcpy(&descriptorRegion, &descriptorBuffer, DESCRIPTORREGIONSIZE); + + // get original GBe region location + unsigned int flRegionBitShift = 12; + unsigned int gbeRegionLocation = descriptorRegion.regionSection.flReg3.BASE << flRegionBitShift; + + fseek(fp, gbeRegionLocation, SEEK_SET); + + char gbeBuffer[GBEREGIONSIZE]; + + readLen = fread(gbeBuffer, sizeof(char), GBEREGIONSIZE, fp); + if (GBEREGIONSIZE != readLen) + { + printf("\nerror: could not read GBe region from factory.rom (%i) bytes read\n", readLen); + return 1; + } + + // get rom size + fseek(fp, 0L, SEEK_END); + int romSize = ftell(fp); + + printf("\nfactory.rom size: [%i] bytes\n", romSize); + + fclose(fp); + + printf("\nOriginal Descriptor start block: %08x ; Descriptor end block: %08x\n", descriptorRegion.regionSection.flReg0.BASE << flRegionBitShift, descriptorRegion.regionSection.flReg0.LIMIT << flRegionBitShift); + printf("Original BIOS start block: %08x ; BIOS end block: %08x\n", descriptorRegion.regionSection.flReg1.BASE << flRegionBitShift, descriptorRegion.regionSection.flReg1.LIMIT << flRegionBitShift); + printf("Original ME start block: %08x ; ME end block: %08x\n", descriptorRegion.regionSection.flReg2.BASE << flRegionBitShift, descriptorRegion.regionSection.flReg2.LIMIT << flRegionBitShift); + printf("Original GBe start block: %08x ; GBe end block: %08x\n", gbeRegionLocation, descriptorRegion.regionSection.flReg3.LIMIT << flRegionBitShift); + + // set number of regions from 4 -> 2 (0 based) + descriptorRegion.flMaps.flMap0.NR = 2; + + // make descriptor writable from OS. + descriptorRegion.masterAccessSection.flMstr1.fdRegionWriteAccess = 1; + + // relocate BIOS region and increase size to fill image + descriptorRegion.regionSection.flReg1.BASE = 3; + descriptorRegion.regionSection.flReg1.LIMIT = ((romSize / 0x1000) - 1); + + // set ME region size to 0 + descriptorRegion.regionSection.flReg2.BASE = 0xFFF; + descriptorRegion.regionSection.flReg2.LIMIT = 0; + + // relocate Gbe region + descriptorRegion.regionSection.flReg3.BASE = 1; + descriptorRegion.regionSection.flReg3.LIMIT = 2; + + // set Platform region size to 0 + descriptorRegion.regionSection.flReg4.BASE = 0xFFF; + descriptorRegion.regionSection.flReg4.LIMIT = 0; + + // disable ME in ICHSTRAP0 + descriptorRegion.ichStraps.ichStrap0.meDisable = 1; + + // disable ME and TPM in MCHSTRAP0 + descriptorRegion.mchStraps.mchStrap0.meDisable = 1; + descriptorRegion.mchStraps.mchStrap0.tpmDisable = 1; + + // disable ME, apart from chipset bugfixes (ME region still required) + //descriptorRegion.mchStraps.mchStrap0.meAlternateDisable = 1; + + + printf("\nRelocated Descriptor start block: %08x ; Descriptor end block: %08x\n", descriptorRegion.regionSection.flReg0.BASE << flRegionBitShift, descriptorRegion.regionSection.flReg0.LIMIT << flRegionBitShift); + printf("Relocated BIOS start block: %08x ; BIOS end block: %08x\n", descriptorRegion.regionSection.flReg1.BASE << flRegionBitShift, descriptorRegion.regionSection.flReg1.LIMIT << flRegionBitShift); + printf("Relocated ME start block: %08x ; ME end block: %08x\n", descriptorRegion.regionSection.flReg2.BASE << flRegionBitShift, descriptorRegion.regionSection.flReg2.LIMIT << flRegionBitShift); + printf("Relocated GBe start block: %08x ; GBe end block: %08x\n", descriptorRegion.regionSection.flReg3.BASE << flRegionBitShift, descriptorRegion.regionSection.flReg3.LIMIT << flRegionBitShift); + + + char deblobbedDescriptorBuffer[DESCRIPTORREGIONSIZE]; + memcpy(&deblobbedDescriptorBuffer, &descriptorRegion, DESCRIPTORREGIONSIZE); + + remove(deblobbedDescriptorFilename); + fp = fopen(deblobbedDescriptorFilename, "ab"); + + if (DESCRIPTORREGIONSIZE != fwrite(deblobbedDescriptorBuffer, sizeof(char), DESCRIPTORREGIONSIZE, fp)) + { + printf("\nerror: writing descriptor region failed\n"); + return 1; + } + + if (GBEREGIONSIZE != fwrite(gbeBuffer, sizeof(char), GBEREGIONSIZE, fp)) + { + printf("\nerror: writing GBe region failed\n"); + return 1; + } + + fclose(fp); + + printf("\ndeblobbed descriptor successfully created: deblobbed_descriptor.bin \n"); + + unsigned short gbeCalculatedChecksum = GetChecksum(gbeBuffer, 0xBABA); // observed values 0xBABA 0x3ABA 0x34BA. spec defined as 0xBABA. + unsigned short gbeChecksum = GetRegionWord(0x3F, gbeBuffer); + + printf("\ncalculated Gbe checksum: 0x%hx actual GBe checksum: 0x%hx\n", gbeCalculatedChecksum, gbeChecksum); + + return 0; +} + +unsigned short GetChecksum(char* regionData, unsigned short desiredValue) +{ + unsigned short regionWord; + unsigned short checksum = 0; + + int i; + for (i = 0; i < 0x3F; i++) { + regionWord = GetRegionWord(i, regionData); + checksum += regionWord; + } + checksum = desiredValue - checksum; + return checksum; +} + +unsigned short GetRegionWord(int index, char* regionData) +{ + return *((unsigned short*)(regionData + (index * 2))); +} diff --git a/resources/utilities/ich9deblob/ich9desc.c b/resources/utilities/ich9deblob/ich9desc.c new file mode 100644 index 00000000..f467be72 --- /dev/null +++ b/resources/utilities/ich9deblob/ich9desc.c @@ -0,0 +1,200 @@ +/* + * ich9desc.c + * + * Copyright (C) 2014 Steve Shenton <sgsit@libreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +struct FLVALSIG{ + unsigned int signature; +}; + +struct FLMAP0 { + unsigned char FCBA : 8; + unsigned char NC : 2; + unsigned char : 6; + unsigned char FRBA : 8; + unsigned char NR : 3; + unsigned char : 5; +}; + +struct FLMAP1 { + unsigned char FMBA : 8; + unsigned char NM : 3; + unsigned char : 5; + unsigned char FISBA : 8; + unsigned char ISL : 8; +}; + +struct FLMAP2 { + unsigned char FMSBA : 8; + unsigned char MSL : 8; + unsigned short : 16; +}; + +struct FLMAPS { + struct FLMAP0 flMap0; + struct FLMAP1 flMap1; + struct FLMAP2 flMap2; +}; + +struct FLCOMP { + unsigned char component1Density : 3; + unsigned char component2Density : 3; + unsigned char : 2; + unsigned char : 8; + unsigned char : 1; + unsigned char readClockFrequency : 3; + unsigned char fastReadSupport : 1; + unsigned char fastreadClockFrequency : 3; + unsigned char writeEraseClockFrequency : 3; + unsigned char readStatusClockFrequency : 3; + unsigned char : 2; +}; + +struct COMPONENTSECTIONRECORD { + struct FLCOMP flcomp; + unsigned int flill; + unsigned int flpb; + unsigned char padding[36]; +}; + +struct FLREG { + unsigned short BASE : 13; + unsigned short : 3; + unsigned short LIMIT : 13; + unsigned short : 3; +}; + +struct REGIONSECTIONRECORD { + struct FLREG flReg0; // Descriptor + struct FLREG flReg1; // BIOS + struct FLREG flReg2; // ME + struct FLREG flReg3; // Gbe + struct FLREG flReg4; // Platform + unsigned char padding[12]; +}; + +struct FLMSTR { + unsigned short requesterId : 16; + unsigned char fdRegionReadAccess : 1; + unsigned char biosRegionReadAccess : 1; + unsigned char meRegionReadAccess : 1; + unsigned char gbeRegionReadAccess : 1; + unsigned char pdRegionReadAccess : 1; + unsigned char reserved1 : 3; + unsigned char fdRegionWriteAccess : 1; + unsigned char biosRegionWriteAccess : 1; + unsigned char meRegionWriteAccess : 1; + unsigned char gbeRegionWriteAccess : 1; + unsigned char pdRegionWriteAccess : 1; + unsigned char reserved2 : 3; +}; + + +struct MASTERACCESSSECTIONRECORD { + struct FLMSTR flMstr1; + struct FLMSTR flMstr2; + struct FLMSTR flMstr3; + unsigned char padding[148]; +}; + +struct ICHSTRAP0 { + // todo: add MeSmBus2Sel (boring setting) + unsigned char meDisable : 1; // If true, ME is disabled. + unsigned char : 6; + unsigned char tcoMode : 1; // TCO Mode: (Legacy,TCO Mode) The TCO Mode, along with the BMCMODE strap, determines the behavior of the IAMT SmBus controller. + unsigned char smBusAddress : 7; // The ME SmBus 7-bit address. + unsigned char bmcMode : 1; // BMC mode: If true, device is in BMC mode. If Intel(R) AMT or ASF using Intel integrated LAN then this should be false. + unsigned char tripPointSelect : 1; // Trip Point Select: false the NJCLK input buffer is matched to 3.3v signal from the external PHY device, true is matched to 1.8v. + unsigned char : 2; + unsigned char integratedGbe : 1; // Integrated GbE or PCI Express select: (PCI Express,,Integrated GbE) Defines what PCIe Port 6 is used for. + unsigned char lanPhy : 1; // LANPHYPC_GP12_SEL: Set to 0 for GP12 to be used as GPIO (General Purpose Input/Output), or 1 for GP12 to be used for native mode as LAN_PHYPC for 82566 LCD device + unsigned char : 3; + unsigned char dmiRequesterId : 1; // DMI requestor ID security check disable: The primary purpose of this strap is to support server environments with multiple CPUs that each have a different RequesterID that can access the Flash. + unsigned char smBus2Address : 7; // The ME SmBus 2 7-bit address. +}; + +struct ICHSTRAP1 { + unsigned char northMlink : 1; // North MLink Dynamic Clock Gate Disable : Sets the default value for the South MLink Dynamic Clock Gate Enable registers. + unsigned char southMlink : 1; // South MLink Dynamic Clock Gate Enable : Sets the default value for the South MLink Dynamic Clock Gate Enable registers. + unsigned char meSmbus : 1; // ME SmBus Dynamic Clock Gate Enable : Sets the default value for the ME SMBus Dynamic Clock Gate Enable for both the ME SmBus controllers. + unsigned char sstDynamic : 1; // SST Dynamic Clock Gate Enable : Sets the default value for the SST Clock Gate Enable registers. + unsigned char : 4; + unsigned char northMlink2 : 1; // North MLink 2 Non-Posted Enable : 'true':North MLink supports two downstream non-posted requests. 'false':North MLink supports one downstream non-posted requests. + unsigned char : 7; + unsigned short : 16; +}; + + +struct ICHSTRAPSRECORD { + struct ICHSTRAP0 ichStrap0; + struct ICHSTRAP1 ichStrap1; + unsigned char padding[248]; +}; + +struct MCHSTRAP0 { + unsigned char meDisable : 1; // If true, ME is disabled. + unsigned char meBootFromFlash : 1; // ME boot from Flash - guessed location + unsigned char tpmDisable : 1; // iTPM Disable : When set true, iTPM Host Interface is disabled. When set false (default), iTPM is enabled. + unsigned char : 3; + unsigned char spiFingerprint : 1; // SPI Fingerprint Sensor Present: Indicates if an SPI Fingerprint sensor is present at CS#1. + unsigned char meAlternateDisable : 1; // ME Alternate Disable: Setting this bit allows ME to perform critical chipset functions but prevents loading of any ME FW applications. + unsigned char : 8; + unsigned short : 16; +}; + +struct MCHSTRAPSRECORD { + struct MCHSTRAP0 mchStrap0; + unsigned char padding[3292]; +}; + +struct MEVSCCTABLERECORD { + unsigned int jid0; + unsigned int vscc0; + unsigned int jid1; + unsigned int vscc1; + unsigned int jid2; + unsigned int vscc2; + unsigned char padding[4]; +}; + +struct DESCRIPTORMAP2RECORD { + unsigned char meVsccTableBaseAddress : 8; + unsigned char meVsccTableLength : 8; + unsigned short : 16; +}; + +struct OEMSECTIONRECORD { + unsigned char magicString[8]; + unsigned char padding[248]; +}; + +struct GBEREGIONRECORD { + unsigned char gbeRegion[8192]; //todo: implement and document this +}; + +struct DESCRIPTORREGIONRECORD { + struct FLVALSIG flValSig; + struct FLMAPS flMaps; + struct COMPONENTSECTIONRECORD componentSection; + struct REGIONSECTIONRECORD regionSection; + struct MASTERACCESSSECTIONRECORD masterAccessSection; + struct ICHSTRAPSRECORD ichStraps; + struct MCHSTRAPSRECORD mchStraps; + struct MEVSCCTABLERECORD meVsccTable; + struct DESCRIPTORMAP2RECORD descriptor2Map; + struct OEMSECTIONRECORD oemSection; +}; |
