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| author | Alyssa Rosenzweig <alyssa@rosenzweig.io> | 2017-05-25 16:55:18 -0700 |
|---|---|---|
| committer | Leah Rowe <info@minifree.org> | 2017-05-27 21:50:36 +0100 |
| commit | abb8c1db38c7a8e1cd298c5fb75bdf8da9c4c4a7 (patch) | |
| tree | 5e487e833d09d1b3df6ecc63f63754c881df671c /docs/hardware/kfsn4-dre.md | |
| parent | 4587f4646eeb38938eff434f9fb88f2cd9cc138b (diff) | |
| download | librebootfr-abb8c1db38c7a8e1cd298c5fb75bdf8da9c4c4a7.tar.gz librebootfr-abb8c1db38c7a8e1cd298c5fb75bdf8da9c4c4a7.zip | |
Manual typographic fixes
Diffstat (limited to 'docs/hardware/kfsn4-dre.md')
| -rw-r--r-- | docs/hardware/kfsn4-dre.md | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/docs/hardware/kfsn4-dre.md b/docs/hardware/kfsn4-dre.md index 4efc4648..944098e0 100644 --- a/docs/hardware/kfsn4-dre.md +++ b/docs/hardware/kfsn4-dre.md @@ -24,9 +24,9 @@ SST49LF080A is the default that the board uses. SST49LF016C is an example of a 2MiB (16Mbits) chip, which might work. It is believed that 2MiB (16Mbits) is the maximum size available for the flash chip. -**DO NOT hot-swap the chip with your bare hands. Use a PLCC chip +*DO NOT hot-swap the chip with your bare hands. Use a PLCC chip extractor. These can be found online. See -<http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools>** +<http://www.coreboot.org/Developer_Manual/Tools#Chip_removal_tools>* Native graphics initialization {#graphics} ============================== |