link to french version of gplv3 at the top of i18n/fr_FR/COPYING . Also, we remove files that we haven't translated yet, it weights a lot.

author: Libreboot Contributor <contributor@libreboot.org> 2020-04-02 20:59:23 +0200
committer: Libreboot Contributor <contributor@libreboot.org> 2020-04-02 20:59:43 +0200
commit: a2f4bef6de0e1f5770d489e861c78890f81229c1 (patch)
tree: bc74ce87d44cfcae1eecff62c0fbf6a97b1812fc /i18n/fr_FR/resources/libreboot/patch
parent: c6cb6cf4769cd535eee9abfd41fbf717a51d067c (diff)
download: librebootfr-a2f4bef6de0e1f5770d489e861c78890f81229c1.tar.gz
librebootfr-a2f4bef6de0e1f5770d489e861c78890f81229c1.zip
58 files changed, 0 insertions, 3235 deletions
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
deleted file mode 100644
index 2fde12f4..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 8 Mar 2016 07:21:33 +0000
-Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates
-
-There were build issues in libreboot. We don't use microcode updates anyway.
-When selecting no microcode updates in menuconfig, build failed because
-coreboot for these boards was still trying to add microcode.
----
- src/cpu/Makefile.inc                           | 34 +-------------------------
- src/cpu/amd/family_10h-family_15h/Kconfig      |  1 -
- src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 --------
- 3 files changed, 1 insertion(+), 44 deletions(-)
-
-diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
-index 046c418..ef0e236 100644
---- a/src/cpu/Makefile.inc
-+++ b/src/cpu/Makefile.inc
-@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
- ## Rules for building the microcode blob in CBFS
- ################################################################################
- 
--ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
--cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += cpu_microcode_blob.bin
--endif
--
--ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
--cbfs-files-y  += cpu_microcode_blob.bin
--cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
--
--$(objgenerated)/microcode.bin:
--	echo "   util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
--	util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
--endif
--
--# We just mash all microcode binaries together into one binary to rule them all.
--# This approach assumes that the microcode binaries are properly padded, and
--# their headers specify the correct size. This works fairly well on isolatied
--# updates, such as Intel and some AMD microcode, but won't work very well if the
--# updates are wrapped in a container, like AMD's microcode update container. If
--# there is only one microcode binary (i.e. one container), then we don't have
--# this issue, and this rule will continue to work.
--$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
--	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
--	@echo $(cpu_microcode_bins)
--	cat /dev/null $+ > $@
--
--cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
--cpu_microcode_blob.bin-type := microcode
--
--ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
--cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
--else
--cpu_microcode_blob.bin-align := 16
--endif
-+# What? Nope! We don't do that in libreboot.
-diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
-index 14ab1cd..3f873a1 100644
---- a/src/cpu/amd/family_10h-family_15h/Kconfig
-+++ b/src/cpu/amd/family_10h-family_15h/Kconfig
-@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX
- 	select UDELAY_LAPIC
- 	select HAVE_MONOTONIC_TIMER
- 	select SUPPORT_CPU_UCODE_IN_CBFS
--	select CPU_MICROCODE_MULTIPLE_FILES
- 
- if CPU_AMD_MODEL_10XXX
- 
-diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-index f10f732..a295475 100644
---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
-+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-@@ -9,13 +9,3 @@ romstage-y += ram_calc.c
- ramstage-y += ram_calc.c
- ramstage-y += monotonic_timer.c
- ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
--
--# Microcode for Family 10h, 11h, 12h, and 14h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
--microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
--microcode_amd.bin-type := microcode
--
--# Microcode for Family 15h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-type := microcode
--- 
-1.9.1
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
deleted file mode 100644
index 2fde12f4..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 8 Mar 2016 07:21:33 +0000
-Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates
-
-There were build issues in libreboot. We don't use microcode updates anyway.
-When selecting no microcode updates in menuconfig, build failed because
-coreboot for these boards was still trying to add microcode.
----
- src/cpu/Makefile.inc                           | 34 +-------------------------
- src/cpu/amd/family_10h-family_15h/Kconfig      |  1 -
- src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 --------
- 3 files changed, 1 insertion(+), 44 deletions(-)
-
-diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
-index 046c418..ef0e236 100644
---- a/src/cpu/Makefile.inc
-+++ b/src/cpu/Makefile.inc
-@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
- ## Rules for building the microcode blob in CBFS
- ################################################################################
- 
--ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
--cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += cpu_microcode_blob.bin
--endif
--
--ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
--cbfs-files-y  += cpu_microcode_blob.bin
--cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
--
--$(objgenerated)/microcode.bin:
--	echo "   util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
--	util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
--endif
--
--# We just mash all microcode binaries together into one binary to rule them all.
--# This approach assumes that the microcode binaries are properly padded, and
--# their headers specify the correct size. This works fairly well on isolatied
--# updates, such as Intel and some AMD microcode, but won't work very well if the
--# updates are wrapped in a container, like AMD's microcode update container. If
--# there is only one microcode binary (i.e. one container), then we don't have
--# this issue, and this rule will continue to work.
--$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
--	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
--	@echo $(cpu_microcode_bins)
--	cat /dev/null $+ > $@
--
--cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
--cpu_microcode_blob.bin-type := microcode
--
--ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
--cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
--else
--cpu_microcode_blob.bin-align := 16
--endif
-+# What? Nope! We don't do that in libreboot.
-diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
-index 14ab1cd..3f873a1 100644
---- a/src/cpu/amd/family_10h-family_15h/Kconfig
-+++ b/src/cpu/amd/family_10h-family_15h/Kconfig
-@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX
- 	select UDELAY_LAPIC
- 	select HAVE_MONOTONIC_TIMER
- 	select SUPPORT_CPU_UCODE_IN_CBFS
--	select CPU_MICROCODE_MULTIPLE_FILES
- 
- if CPU_AMD_MODEL_10XXX
- 
-diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-index f10f732..a295475 100644
---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
-+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-@@ -9,13 +9,3 @@ romstage-y += ram_calc.c
- ramstage-y += ram_calc.c
- ramstage-y += monotonic_timer.c
- ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
--
--# Microcode for Family 10h, 11h, 12h, and 14h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
--microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
--microcode_amd.bin-type := microcode
--
--# Microcode for Family 15h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-type := microcode
--- 
-1.9.1
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
deleted file mode 100644
index 2fde12f4..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 8 Mar 2016 07:21:33 +0000
-Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates
-
-There were build issues in libreboot. We don't use microcode updates anyway.
-When selecting no microcode updates in menuconfig, build failed because
-coreboot for these boards was still trying to add microcode.
----
- src/cpu/Makefile.inc                           | 34 +-------------------------
- src/cpu/amd/family_10h-family_15h/Kconfig      |  1 -
- src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 --------
- 3 files changed, 1 insertion(+), 44 deletions(-)
-
-diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
-index 046c418..ef0e236 100644
---- a/src/cpu/Makefile.inc
-+++ b/src/cpu/Makefile.inc
-@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
- ## Rules for building the microcode blob in CBFS
- ################################################################################
- 
--ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
--cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += cpu_microcode_blob.bin
--endif
--
--ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
--cbfs-files-y  += cpu_microcode_blob.bin
--cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
--
--$(objgenerated)/microcode.bin:
--	echo "   util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
--	util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
--endif
--
--# We just mash all microcode binaries together into one binary to rule them all.
--# This approach assumes that the microcode binaries are properly padded, and
--# their headers specify the correct size. This works fairly well on isolatied
--# updates, such as Intel and some AMD microcode, but won't work very well if the
--# updates are wrapped in a container, like AMD's microcode update container. If
--# there is only one microcode binary (i.e. one container), then we don't have
--# this issue, and this rule will continue to work.
--$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
--	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
--	@echo $(cpu_microcode_bins)
--	cat /dev/null $+ > $@
--
--cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
--cpu_microcode_blob.bin-type := microcode
--
--ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
--cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
--else
--cpu_microcode_blob.bin-align := 16
--endif
-+# What? Nope! We don't do that in libreboot.
-diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
-index 14ab1cd..3f873a1 100644
---- a/src/cpu/amd/family_10h-family_15h/Kconfig
-+++ b/src/cpu/amd/family_10h-family_15h/Kconfig
-@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX
- 	select UDELAY_LAPIC
- 	select HAVE_MONOTONIC_TIMER
- 	select SUPPORT_CPU_UCODE_IN_CBFS
--	select CPU_MICROCODE_MULTIPLE_FILES
- 
- if CPU_AMD_MODEL_10XXX
- 
-diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-index f10f732..a295475 100644
---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
-+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-@@ -9,13 +9,3 @@ romstage-y += ram_calc.c
- ramstage-y += ram_calc.c
- ramstage-y += monotonic_timer.c
- ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
--
--# Microcode for Family 10h, 11h, 12h, and 14h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
--microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
--microcode_amd.bin-type := microcode
--
--# Microcode for Family 15h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-type := microcode
--- 
-1.9.1
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/reused.list
deleted file mode 100644
index 5dd5800f..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/macbook21/reused.list
+++ /dev/null
@@ -1,2 +0,0 @@
-/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-i945-Enable-changing-VRAM-size.patch
-/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-Enable-brightness-controls-native-graphic.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-Enable-brightness-controls-native-graphic.patch
deleted file mode 100644
index 2e3ee65b..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/0001-lenovo-t60-Enable-brightness-controls-native-graphic.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 770021ce66a0fddebb9639c4df0696ecfca45488 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Mon, 15 Jun 2015 19:59:46 +0100
-Subject: [PATCH 4/9] lenovo/t60: Enable brightness controls (native graphics)
-
-This makes the Fn Home/End keys work for controlling the
-brightness of the display. Value obtained by reading
-BLC_PWM_CTL when running the VBIOS (option ROM).
-
-On i945 legacy brightness control is enabled by a single
-bit in BLC_PWM_CTL. It's bit 16 or bit 0 (the other one
-reverses polarity). Set the bit to enable brightness
-controls.
-
-Change-Id: I22e261f2ce28ec81cd208a73e6311ec67146eb72
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/mainboard/lenovo/t60/devicetree.cb | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb
-index b28f1ad..9e6ce02 100644
---- a/src/mainboard/lenovo/t60/devicetree.cb
-+++ b/src/mainboard/lenovo/t60/devicetree.cb
-@@ -26,7 +26,7 @@ chip northbridge/intel/i945
- 
- 	register "gpu_hotplug" = "0x00000220"
- 	register "gpu_lvds_use_spread_spectrum_clock" = "1"
--	register "gpu_backlight" = "0x1280128"
-+	register "gpu_backlight" = "0x58BF58BE"
- 
- 	device cpu_cluster 0 on
- 		chip cpu/intel/socket_mFCPGA478
--- 
-1.9.1
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/INFO b/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/INFO
deleted file mode 100644
index cb543aae..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/INFO
+++ /dev/null
@@ -1,3 +0,0 @@
-printf "lenovo/t60: Enable brightness controls (native graphics)\n"
-git am "../resources/libreboot/patch/misc/0004-lenovo-t60-Enable-brightness-controls-native-graphic.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/52/10552/2 && git cherry-pick FETCH_HEAD
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/reused.list
deleted file mode 100644
index 157e1cf6..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/t60/reused.list
+++ /dev/null
@@ -1,3 +0,0 @@
-/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-i945-Enable-changing-VRAM-size.patch
-/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
deleted file mode 100644
index 6f8b5307..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From 1024b5e6c476dcc195dca742746735277f63236b Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Mon, 13 Oct 2014 00:14:53 +0100
-Subject: [PATCH 5/9] NOTFORMERGE: ec/lenovo/h8:
- wlan/trackpoint/touchpad/bluetooth/wwan
-
-Permanently enable them.
-
-Change-Id: Ic76ab9ab9c865f30312378e18af58bece6c3260a
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/ec/lenovo/h8/h8.c     | 21 +++++++++++----------
- src/ec/lenovo/pmh7/pmh7.c | 11 ++++-------
- 2 files changed, 15 insertions(+), 17 deletions(-)
-
-diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
-index 2cafc88..a6cb6b6 100644
---- a/src/ec/lenovo/h8/h8.c
-+++ b/src/ec/lenovo/h8/h8.c
-@@ -255,9 +255,11 @@ static void h8_enable(struct device *dev)
- 
- 	ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO);
- 
--	if (get_option(&val, "wlan") != CB_SUCCESS)
--		val = 1;
--	h8_wlan_enable(val);
-+	// Permanently enable wifi
-+	// Intel wifi could be a security risk because it uses firmware. Wlan chip has DMA
-+	// and could leak data over a side-channel. Using another manufacturer is recommended.
-+	// see http://libreboot.org/docs/index.html#recommended_wifi
-+	h8_wlan_enable(1);
- 
- 	h8_trackpoint_enable(1);
- 	h8_usb_power_enable(1);
-@@ -265,14 +267,13 @@ static void h8_enable(struct device *dev)
- 	if (get_option(&val, "volume") == CB_SUCCESS)
- 		ec_write(H8_VOLUME_CONTROL, val);
- 
--	if (get_option(&val, "bluetooth") != CB_SUCCESS)
--		val = 1;
--	h8_bluetooth_enable(val);
--
--	if (get_option(&val, "wwan") != CB_SUCCESS)
--		val = 1;
-+	// Permanently enable bluetooth.
-+	// NOTE: bluetooth is a potential security risk. Physical removal of the bluetooth module is recommended.
-+	h8_bluetooth_enable(1);
- 
--	h8_wwan_enable(val);
-+	// Permanently enable wwan.
-+	// NOTE: wwan is a security risk (remove access plus DMA). Physical removal of both the wwan and sim card is recommended.
-+	h8_wwan_enable(1);
- 
- 	if (conf->has_uwb) {
- 		if (get_option(&val, "uwb") != CB_SUCCESS)
-diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c
-index cc6e891..38aef16 100644
---- a/src/ec/lenovo/pmh7/pmh7.c
-+++ b/src/ec/lenovo/pmh7/pmh7.c
-@@ -106,7 +106,6 @@ static void enable_dev(struct device *dev)
- {
- 	struct ec_lenovo_pmh7_config *conf = dev->chip_info;
- 	struct resource *resource;
--	u8 val;
- 
- 	resource = new_resource(dev, EC_LENOVO_PMH7_INDEX);
- 	resource->flags = IORESOURCE_IO | IORESOURCE_FIXED;
-@@ -118,13 +117,11 @@ static void enable_dev(struct device *dev)
- 	pmh7_backlight_enable(conf->backlight_enable);
- 	pmh7_dock_event_enable(conf->dock_event_enable);
- 
--	if (get_option(&val, "touchpad") != CB_SUCCESS)
--		val = 1;
--	pmh7_touchpad_enable(val);
-+	// Permanently enable touchpad
-+	pmh7_touchpad_enable(1);
- 
--	if (get_option(&val, "trackpoint") != CB_SUCCESS)
--		val = 1;
--	pmh7_trackpoint_enable(val);
-+	// Permanently enable trackpoint
-+	pmh7_trackpoint_enable(1);
- }
- 
- struct chip_operations ec_lenovo_pmh7_ops = {
--- 
-1.9.1
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-i945-Enable-changing-VRAM-size.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-i945-Enable-changing-VRAM-size.patch
deleted file mode 100644
index ce1d37c0..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-i945-Enable-changing-VRAM-size.patch
+++ /dev/null
@@ -1,158 +0,0 @@
-From 44b3d02a49bc25dc8e9119a11bd948db2c37a931 Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Sun, 15 May 2016 02:17:12 +0200
-Subject: [PATCH] i945: Enable changing VRAM size
-
-On i945 the vram size was the default 8mb. It was also possible
-to set it 1mb or 0mb hardcoding the GGC register in early_init.c
-
-The intel documentation on i945 only documents those three options.
-They are set using 3 bits. The documententation also makes mention
-of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it.
-
-The other non documented (straight forward) bit combinations allows
-to change the VRAM size to those other states.
-
-Change-Id: I5e510e81322a4c8315c01b7963ac4b5f7f58a17e
-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
-
-diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
-index 6e8d35b..484ed78 100644
---- a/src/northbridge/intel/i945/Kconfig
-+++ b/src/northbridge/intel/i945/Kconfig
-@@ -72,3 +72,56 @@ config CHECK_SLFRCS_ON_RESUME
- 	  effectively making it impossible to resume.
- 
- endif
-+
-+config VRAM_CHOICE
-+        bool
-+choice
-+	prompt "VRAM Size"
-+	depends on NORTHBRIDGE_INTEL_I945
-+	default VRAM_SIZE_8MB
-+	help
-+	  Set the size of vram that the integrated graphic device can use
-+	  for a framebuffer.
-+
-+config VRAM_SIZE_1MB
-+	bool "1 MB"
-+	help
-+	  Set VRAM size to 1MB.
-+config VRAM_SIZE_4MB
-+	bool "4 MB"
-+	help
-+	  Set VRAM size to 4MB.
-+config VRAM_SIZE_8MB
-+	bool "8 MB"
-+	help
-+	  Set VRAM size to 8MB.
-+config VRAM_SIZE_16MB
-+	bool "16 MB"
-+	help
-+	  Set VRAM size to 16MB.
-+config VRAM_SIZE_32MB
-+	bool "32 MB"
-+	help
-+	  Set VRAM size to 32MB.
-+config VRAM_SIZE_48MB
-+	bool "48 MB"
-+	help
-+	  Set VRAM size to 48MB.
-+config VRAM_SIZE_64MB
-+	bool "64 MB"
-+	help
-+	  Set VRAM size to 64MB.
-+
-+endchoice
-+
-+config VRAM_SIZE
-+	hex
-+	default 0x10 if VRAM_SIZE_1MB
-+	default 0x20 if VRAM_SIZE_4MB
-+	default 0x30 if VRAM_SIZE_8MB
-+	default 0x40 if VRAM_SIZE_16MB
-+	default 0x50 if VRAM_SIZE_32MB
-+	default 0x60 if VRAM_SIZE_48MB
-+	default 0x70 if VRAM_SIZE_64MB
-+	help
-+	 map the vram sizes to an integer.
-diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
-index 475e88a..bd062ad 100644
---- a/src/northbridge/intel/i945/early_init.c
-+++ b/src/northbridge/intel/i945/early_init.c
-@@ -177,11 +177,8 @@ static void i945_setup_bars(void)
- 	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1);
- 	pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);
- 
--	/* Hardware default is 8MB UMA. If someone wants to make this a
--	 * CMOS or compile time option, send a patch.
--	 * pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x30);
--	 */
--
-+	/* Sets up VRAM size from the build option VRAM_SIZE */
-+	pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, CONFIG_VRAM_SIZE);
- 	/* Set C0000-FFFFF to access RAM on both reads and writes */
- 	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
- 	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);
-diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
-index df13ef4..f853cc8 100644
---- a/src/northbridge/intel/i945/gma.c
-+++ b/src/northbridge/intel/i945/gma.c
-@@ -359,9 +359,24 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
- 		case 1:
- 			uma_size = 1024;
- 			break;
-+		case 2:
-+			uma_size = 4096;
-+			break;
- 		case 3:
- 			uma_size = 8192;
- 			break;
-+		case 4:
-+			uma_size = 16384;
-+			break;
-+		case 5:
-+			uma_size = 32768;
-+			break;
-+		case 6:
-+			uma_size = 49152;
-+			break;
-+		case 7:
-+			uma_size = 65536;
-+			break;
- 		}
- 
- 		printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
-diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
-index 514f88c..4be9827 100644
---- a/src/northbridge/intel/i945/northbridge.c
-+++ b/src/northbridge/intel/i945/northbridge.c
-@@ -112,9 +112,24 @@ static void pci_domain_set_resources(device_t dev)
- 		case 1:
- 			uma_size = 1024;
- 			break;
-+		case 2:
-+			uma_size = 4096;
-+			break;
- 		case 3:
- 			uma_size = 8192;
- 			break;
-+		case 4:
-+			uma_size = 16384;
-+			break;
-+		case 5:
-+			uma_size = 32768;
-+			break;
-+		case 6:
-+			uma_size = 49152;
-+			break;
-+		case 7:
-+			uma_size = 65536;
-+			break;
- 		}
- 
- 		printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
--- 
-2.8.2
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-lenovo-x60-add-hda_verb.c.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-lenovo-x60-add-hda_verb.c.patch
deleted file mode 100644
index 80eda28b..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0001-lenovo-x60-add-hda_verb.c.patch
+++ /dev/null
@@ -1,65 +0,0 @@
-From 4f3452fc544d4e799445c3271b1022496932473c Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Fri, 3 Jun 2016 18:37:38 +0200
-Subject: [PATCH] lenovo/x60: add hda_verb.c
-
-This creates a config for the x60 audio based
-on values taken from vendor bios.
-
-What is improved:
-- internal microphone is chosen by default
-- when jack is inserted it chosen instead of internal speaker
-
-Before this had to be done manually.
-
-Change-Id: Id3b700fd84905a72cc1f69e7d8bfa6145f231756
-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
-
-diff --git a/src/mainboard/lenovo/x60/hda_verb.c b/src/mainboard/lenovo/x60/hda_verb.c
-index 072a306..c4b1f3a 100644
---- a/src/mainboard/lenovo/x60/hda_verb.c
-+++ b/src/mainboard/lenovo/x60/hda_verb.c
-@@ -1,7 +1,38 @@
-+/*
-+ * This file is part of the coreboot project.
-+ *
-+ * Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz>
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; version 2 of
-+ * the License.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ */
-+
- #include <device/azalia_device.h>
- 
--const u32 cim_verb_data[0] = {};
-+const u32 cim_verb_data[] = {
-+	0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */
-+	0x17aa2025, /* Subsystem ID */
-+	0x0000000b, /* Number of 4 dword sets */
- 
--const u32 pc_beep_verbs[0] = {};
-+	AZALIA_SUBVENDOR(0x0, 0x17aa2025),
- 
-+	AZALIA_PIN_CFG(0, 0x05, 0xc3014110),
-+	AZALIA_PIN_CFG(0, 0x06, 0x4221401f),
-+	AZALIA_PIN_CFG(0, 0x07, 0x591311f0),
-+	AZALIA_PIN_CFG(0, 0x08, 0xc3a15020),
-+	AZALIA_PIN_CFG(0, 0x09, 0x41813021),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x014470f0),
-+	AZALIA_PIN_CFG(0, 0x16, 0x59f311f0),
-+	AZALIA_PIN_CFG(0, 0x17, 0x59931122),
-+	AZALIA_PIN_CFG(0, 0x18, 0x41a19023),
-+	AZALIA_PIN_CFG(0, 0x19, 0x9933e12e)
-+};
-+const u32 pc_beep_verbs[0] = {};
- AZALIA_ARRAY_SIZES;
--- 
-2.8.3
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0002-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0002-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch
deleted file mode 100644
index 7470dd60..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0002-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From e4b5b65c93122126344771f2042f8d7a3468be19 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Mon, 22 Jun 2015 17:37:06 +0100
-Subject: [PATCH 3/9] lenovo/x60: use correct BLC_PWM_CTL value
-
-Bit 16 in BLC_PWM_CTL enables brightness controls, but the
-current value is generic. Use the proper value, obtained
-by reading BLC_PWM_CTL while running the VBIOS.
-
-Change-Id: Ib273359e1c285b405a9bb26fc217c2f7e255b99f
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/mainboard/lenovo/x60/devicetree.cb | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb
-index b4d1144..4d62116 100644
---- a/src/mainboard/lenovo/x60/devicetree.cb
-+++ b/src/mainboard/lenovo/x60/devicetree.cb
-@@ -26,7 +26,7 @@ chip northbridge/intel/i945
- 
- 	register "gpu_hotplug" = "0x00000220"
- 	register "gpu_lvds_use_spread_spectrum_clock" = "1"
--	register "gpu_backlight" = "0x1290128"
-+	register "gpu_backlight" = "0x879F879E"
- 
- 	device cpu_cluster 0 on
- 		chip cpu/intel/socket_mFCPGA478
--- 
-1.9.1
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch
deleted file mode 100644
index 14f809a9..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From 483bbb3ec7965ca2416fda9e11687bcd655d078d Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Tue, 31 May 2016 16:51:59 +0200
-Subject: [PATCH] model_6ex: enable C2E, C4E, dynamic lvl 2 cache.
-
-Change-Id: Ie538d2145640c7b50ac0a0fa432d98ae2c4be060
-
-diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
-index 6fa6d3a..8ff276a 100644
---- a/src/cpu/intel/model_6ex/model_6ex_init.c
-+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
-@@ -67,9 +67,10 @@ static void configure_c_states(void)
- 
- 	msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
- 	msr.lo |= (1 << 15); // config lock until next reset.
-+	msr.lo |= (1 << 14); // Deeper Sleep
- 	msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States
- 	msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
--	// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
-+	msr.lo |= (1 << 3); // Dynamic L2
- 
- 	/* Number of supported C-States */
- 	msr.lo &= ~7;
-@@ -94,16 +95,20 @@ static void configure_misc(void)
- 	msr_t msr;
- 
- 	msr = rdmsr(IA32_MISC_ENABLE);
--	msr.lo |= (1 << 3); 	/* TM1 enable */
-+	msr.lo |= (1 << 3);	/* TM1 enable */
- 	msr.lo |= (1 << 13);	/* TM2 enable */
- 	msr.lo |= (1 << 17);	/* Bidirectional PROCHOT# */
- 
- 	msr.lo |= (1 << 10);	/* FERR# multiplexing */
- 
--	// TODO: Only if  IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
- 	msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
-+	/* Enable C2E */
-+	msr.lo |= (1 << 26);
-+
-+	/* Enable C4E */
-+	msr.hi |= (1 << (32 - 32)); // C4E
-+	msr.hi |= (1 << (33 - 32)); // Hard C4E
- 
--	// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
- 	wrmsr(IA32_MISC_ENABLE, msr);
- 
- 	msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
--- 
-2.8.3
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/INFO b/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/INFO
deleted file mode 100644
index 4f5931f9..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/x60/INFO
+++ /dev/null
@@ -1,7 +0,0 @@
-printf "lenovo/x60: use correct BLC_PWM_CTL value\n"
-git am "../resources/libreboot/patch/misc/0003-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/24/10624/2 && git cherry-pick FETCH_HEAD
-
-printf "ec/lenovo/h8: permanently enable wifi/trackpoint/touchpad/bluetooth/wwan\n"
-git am "../resources/libreboot/patch/misc/0005-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/58/7058/9 && git cherry-pick FETCH_HEAD
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-mb-intel-d945gclf-Disable-combined-mode-to-fix-SATA.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-mb-intel-d945gclf-Disable-combined-mode-to-fix-SATA.patch
deleted file mode 100644
index 4c75bcd5..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-mb-intel-d945gclf-Disable-combined-mode-to-fix-SATA.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From b6b2f9a9775029305f88f927f93e95046594f9b9 Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Thu, 25 Aug 2016 09:24:15 +0200
-Subject: [PATCH] mb/intel/d945gclf: Disable combined mode to fix SATA
-
-Similarly to 2b2f465fcb1afe4960c613b8ca91e868c64592d4
-"mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA"
-SATA must function in "plain" mode because it does not work in
-"combined" mode.
-
-Tested on d945gclf
-
-Change-Id: I2e051a632a1341c4932cf86855006ae517dbf064
-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
-
-diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
-index 823a240..aa8c441 100644
---- a/src/mainboard/intel/d945gclf/devicetree.cb
-+++ b/src/mainboard/intel/d945gclf/devicetree.cb
-@@ -45,7 +45,7 @@ chip northbridge/intel/i945
- 			register "gpi13_routing" = "1"
- 			register "gpe0_en" = "0x20000601"
- 
--                        register "ide_legacy_combined" = "0x1"
-+                        register "ide_legacy_combined" = "0x0"
-                         register "ide_enable_primary" = "0x1"
-                         register "ide_enable_secondary" = "0x0"
-                         register "sata_ahci" = "0x0"
--- 
-2.9.3
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-move-DIV_ROUND-macros-to-commonlib.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-move-DIV_ROUND-macros-to-commonlib.patch
deleted file mode 100644
index ea4db001..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-move-DIV_ROUND-macros-to-commonlib.patch
+++ /dev/null
@@ -1,93 +0,0 @@
-From c82d4fa874322d70dec0e9d28c050e4c351de157 Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Fri, 2 Sep 2016 23:14:54 +0200
-Subject: [PATCH 1/5] move DIV_ROUND macros to commonlib
-
-DIV_ROUND_CLOSEST and DIV_ROUND_UP are useful macros for other
-architectures. This patch moves them from soc/nvidia/tegra/types.h
-to commonlib/include/commonlib/helpers.h .
-
-Change-Id: I54521d9b197934cef8e352f9a5c4823015d85f01
-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
-
-diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
-index 0318e44..0b2395b 100644
---- a/src/commonlib/include/commonlib/helpers.h
-+++ b/src/commonlib/include/commonlib/helpers.h
-@@ -34,6 +34,22 @@
- #define ABS(a) (((a) < 0) ? (-(a)) : (a))
- #define CEIL_DIV(a, b)  (((a) + (b) - 1) / (b))
- #define IS_POWER_OF_2(x)  (((x) & ((x) - 1)) == 0)
-+#define DIV_ROUND_UP(x, y)  (((x) + (y) - 1) / (y))
-+/*
-+ * Divide positive or negative dividend by positive divisor and round
-+ * to closest integer. Result is undefined for negative divisors and
-+ * for negative dividends if the divisor variable type is unsigned.
-+ */
-+#define DIV_ROUND_CLOSEST(x, divisor)(			\
-+{							\
-+	typeof(x) __x = x;				\
-+	typeof(divisor) __d = divisor;			\
-+	(((typeof(x))-1) > 0 ||				\
-+	 ((typeof(divisor))-1) > 0 || (__x) > 0) ?	\
-+		(((__x) + ((__d) / 2)) / (__d)) :	\
-+		(((__x) - ((__d) / 2)) / (__d));	\
-+}							\
-+)
- 
- /* Standard units. */
- #define KiB (1<<10)
-diff --git a/src/soc/nvidia/tegra/types.h b/src/soc/nvidia/tegra/types.h
-index dab474d..bfeebae 100644
---- a/src/soc/nvidia/tegra/types.h
-+++ b/src/soc/nvidia/tegra/types.h
-@@ -51,22 +51,4 @@
- 	(type *)( (char *)__mptr - offsetof(type,member) );})
- #endif
- 
--#define DIV_ROUND_UP(x, y)  (((x) + (y) - 1) / (y))
--
--/*
-- * Divide positive or negative dividend by positive divisor and round
-- * to closest integer. Result is undefined for negative divisors and
-- * for negative dividends if the divisor variable type is unsigned.
-- */
--#define DIV_ROUND_CLOSEST(x, divisor)(			\
--{							\
--	typeof(x) __x = x;				\
--	typeof(divisor) __d = divisor;			\
--	(((typeof(x))-1) > 0 ||				\
--	 ((typeof(divisor))-1) > 0 || (__x) > 0) ?	\
--		(((__x) + ((__d) / 2)) / (__d)) :	\
--		(((__x) - ((__d) / 2)) / (__d));	\
--}							\
--)
--
- #endif /* __TEGRA_MISC_TYPES_H__ */
-diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c
-index e803e1b..b47c5c5 100644
---- a/src/soc/nvidia/tegra210/addressmap.c
-+++ b/src/soc/nvidia/tegra210/addressmap.c
-@@ -23,6 +23,7 @@
- #include <stdlib.h>
- #include <symbols.h>
- #include <soc/nvidia/tegra/types.h>
-+#include <commonlib/helpers.h>
- 
- static uintptr_t tz_base_mib;
- static const size_t tz_size_mib = CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB;
-diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c
-index 3b771c9..5504b4d 100644
---- a/src/soc/nvidia/tegra210/dsi.c
-+++ b/src/soc/nvidia/tegra210/dsi.c
-@@ -32,6 +32,7 @@
- #include <soc/tegra_dsi.h>
- #include <soc/mipi-phy.h>
- #include "jdi_25x18_display/panel-jdi-lpm102a188a.h"
-+#include <commonlib/helpers.h>
- 
- struct tegra_mipi_device mipi_device_data[NUM_DSI];
- 
--- 
-2.9.3
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0002-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0002-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch
deleted file mode 100644
index 6a8b9920..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0002-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch
+++ /dev/null
@@ -1,171 +0,0 @@
-From f09ce5870025a98b6e497fd232adffde468c735a Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Fri, 2 Sep 2016 22:35:32 +0200
-Subject: [PATCH 2/5] i945/gma.c use latest linux code to calculate divisors.
-
-The code to compute n, m1, m2, p1 divisors is not correct in coreboot and
-on some targets hits a working mode at lower refresh rate, which is why
-display is working on some targets.
-This patch also fixes reference frequency.
-
-This patch reuses linux code to correctly compute divisors.
-
-The result is that some previously not working displays (Lenovo T60 with
-1024x786, 1400x1050, 2048x1536)
-
-TESTED on T60 with 1024x786.
-
-Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e
-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
-
-diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
-index 02caa0a..d1d68d4 100644
---- a/src/northbridge/intel/i945/gma.c
-+++ b/src/northbridge/intel/i945/gma.c
-@@ -26,6 +26,8 @@
- #include <string.h>
- #include <pc80/vga.h>
- #include <pc80/vga_io.h>
-+#include <commonlib/helpers.h>
-+
- 
- #include "i945.h"
- #include "chip.h"
-@@ -43,7 +45,7 @@
- #define PGETBL_CTL	0x2020
- #define PGETBL_ENABLED	0x00000001
- 
--#define BASE_FREQUENCY 120000
-+#define BASE_FREQUENCY 100000
- 
- #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
- 
-@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
- 	u8 edid_data[128];
- 	unsigned long temp;
- 	int hpolarity, vpolarity;
--	u32 candp1, candn;
--	u32 best_delta = 0xffffffff;
-+	u32 err_most = 0xffffffff;
- 	u32 target_frequency;
- 	u32 pixel_p1 = 1;
-+	u32 pixel_p2;
- 	u32 pixel_n = 1;
- 	u32 pixel_m1 = 1;
- 	u32 pixel_m2 = 1;
-@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
- 	write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug);
- 	write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS);
- 
--	target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
--		: (2 * mode->pixel_clock);
--
--	/* Find suitable divisors.  */
--	for (candp1 = 1; candp1 <= 8; candp1++) {
--		for (candn = 5; candn <= 10; candn++) {
--			u32 cur_frequency;
--			u32 m; /* 77 - 131.  */
--			u32 denom; /* 35 - 560.  */
--			u32 current_delta;
--
--			denom = candn * candp1 * 7;
--			/* Doesnt overflow for up to
--			   5000000 kHz = 5 GHz.  */
--			m = (target_frequency * denom
--			     + BASE_FREQUENCY / 2) / BASE_FREQUENCY;
--
--			if (m < 77 || m > 131)
--				continue;
--
--			cur_frequency = (BASE_FREQUENCY * m) / denom;
--			if (target_frequency > cur_frequency)
--				current_delta = target_frequency - cur_frequency;
--			else
--				current_delta = cur_frequency - target_frequency;
--
--			if (best_delta > current_delta) {
--				best_delta = current_delta;
--				pixel_n = candn;
--				pixel_p1 = candp1;
--				pixel_m2 = ((m + 3) % 5) + 7;
--				pixel_m1 = (m - pixel_m2) / 5;
-+	pixel_p2 = mode->lvds_dual_channel ? 7 : 14;
-+	target_frequency = mode->pixel_clock;
-+
-+	/* Find suitable divisors, m1, m2, p1, n.  */
-+	/* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */
-+	/* should be closest to target frequency as possible */
-+	u32 candn, candm1, candm2, candp1;
-+	for (candm1 = 8; candm1 <= 18; candm1++) {
-+		for (candm2 = 3; candm2 <= 7; candm2++) {
-+			for (candn = 1; candn <= 6; candn++) {
-+				for (candp1 = 1; candp1 <= 8; candp1++) {
-+					u32 m = 5 * (candm1 + 2) + (candm2 + 2);
-+					u32 p = candp1 * pixel_p2;
-+					u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2);
-+					u32 dot = DIV_ROUND_CLOSEST(vco, p);
-+					u32 this_err = ABS(dot - target_frequency);
-+					if ((m < 70) || (m > 120))
-+						continue;
-+					if (this_err < err_most) {
-+						err_most = this_err;
-+						pixel_n = candn;
-+						pixel_m1 = candm1;
-+						pixel_m2 = candm2;
-+						pixel_p1 = candp1;
-+					}
-+				}
- 			}
- 		}
- 	}
- 
--	if (best_delta == 0xffffffff) {
-+	if (err_most == 0xffffffff) {
- 		printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
- 		return -1;
- 	}
-@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
- 	printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
- 	       pixel_n, pixel_m1, pixel_m2, pixel_p1);
- 	printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
--	       BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n
--	       / (pixel_p1 * 7));
-+	       BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
-+	       (pixel_n + 2) / (pixel_p1 * pixel_p2));
- 
- #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
- 	write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16));
-@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
- 	write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS
- 		| (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
- 	write32(pmmio + FP0(1),
--		((pixel_n - 2) << 16)
--		| ((pixel_m1 - 2) << 8) | pixel_m2);
-+		(pixel_n << 16)
-+		| (pixel_m1 << 8) | pixel_m2);
- 	write32(pmmio + DPLL(1),
- 		DPLL_VGA_MODE_DIS |
- 		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
- 		| (conf->gpu_lvds_use_spread_spectrum_clock
- 		   ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV
- 		   : 0)
--		| (pixel_p1 << 16)
--		| (pixel_p1));
-+		| (0x10000 << pixel_p1));
- 	mdelay(1);
- 	write32(pmmio + DPLL(1),
- 		DPLL_VGA_MODE_DIS |
-@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
- 		| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- 		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
- 		| ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13)
--		| (pixel_p1 << 16)
--		| (pixel_p1));
-+		| (0x10000 << pixel_p1));
- 	mdelay(1);
- 	write32(pmmio + HTOTAL(1),
- 		((hactive + right_border + hblank - 1) << 16)
--- 
-2.9.3
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0003-i945-gma.c-add-native-VGA-init.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0003-i945-gma.c-add-native-VGA-init.patch
deleted file mode 100644
index 24a01442..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0003-i945-gma.c-add-native-VGA-init.patch
+++ /dev/null
@@ -1,238 +0,0 @@
-From 09546d389511350d1b33b3c6bd9230de8bbbe317 Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Mon, 5 Sep 2016 22:46:11 +0200
-Subject: [PATCH 3/5] i945/gma.c: add native VGA init
-
-This reuses the intel pineview native graphic initialization
-to have output on the VGA connector of i945 devices.
-
-The behavior is the same as with the vbios blob.
-It uses the external VGA display if it is connected.
-
-Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495
-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
-
-diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
-index d1d68d4..37674d7 100644
---- a/src/northbridge/intel/i945/gma.c
-+++ b/src/northbridge/intel/i945/gma.c
-@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase)
- 	return 0;
- }
- 
--static int intel_gma_init(struct northbridge_intel_i945_config *conf,
-+static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
- 			  unsigned int pphysbase, unsigned int piobase,
- 			  void *pmmio, unsigned int pgfx)
- {
-@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
- #endif
- 	return 0;
- }
-+
-+static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
-+			  unsigned int pphysbase, unsigned int piobase,
-+			  void *pmmio, unsigned int pgfx)
-+{
-+	int i;
-+	u32 hactive, vactive;
-+	u16 reg16;
-+	u32 uma_size;
-+
-+	printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n",
-+		(u32)pmmio, piobase, pphysbase);
-+
-+	gtt_setup(pmmio);
-+
-+	/* Disable VGA.  */
-+	write32(pmmio + VGACNTRL, VGA_DISP_DISABLE);
-+
-+	/* Disable pipes.  */
-+	write32(pmmio + PIPECONF(0), 0);
-+	write32(pmmio + PIPECONF(1), 0);
-+
-+	write32(pmmio + INSTPM, 0x800);
-+
-+	vga_gr_write(0x18, 0);
-+
-+	write32(pmmio + VGA0, 0x200074);
-+	write32(pmmio + VGA1, 0x200074);
-+
-+	write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN);
-+	write32(pmmio + DSPCLK_GATE_D, 0);
-+	write32(pmmio + FW_BLC, 0x03060106);
-+	write32(pmmio + FW_BLC2, 0x00000306);
-+
-+	write32(pmmio + ADPA, ADPA_DAC_ENABLE
-+			| ADPA_PIPE_A_SELECT
-+			| ADPA_USE_VGA_HVPOLARITY
-+			| ADPA_VSYNC_CNTL_ENABLE
-+			| ADPA_HSYNC_CNTL_ENABLE
-+			| ADPA_DPMS_ON
-+			);
-+
-+	write32(pmmio + 0x7041c, 0x0);
-+
-+	write32(pmmio + DPLL_MD(0), 0x3);
-+	write32(pmmio + DPLL_MD(1), 0x3);
-+	write32(pmmio + DSPCNTR(1), 0x1000000);
-+	write32(pmmio + PIPESRC(1), 0x027f01df);
-+
-+	vga_misc_write(0x67);
-+	const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
-+		    0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
-+		    0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
-+		    0xff
-+	};
-+	vga_cr_write(0x11, 0);
-+
-+	for (i = 0; i <= 0x18; i++)
-+		vga_cr_write(i, cr[i]);
-+
-+	// Disable screen memory to prevent garbage from appearing.
-+	vga_sr_write(1, vga_sr_read(1) | 0x20);
-+	hactive = 640;
-+	vactive = 400;
-+
-+	mdelay(1);
-+	write32(pmmio + DPLL(0),
-+		DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
-+		| DPLL_VGA_MODE_DIS
-+		| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
-+		| 0x400601
-+		);
-+	mdelay(1);
-+	write32(pmmio + DPLL(0),
-+		DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
-+		| DPLL_VGA_MODE_DIS
-+		| DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
-+		| 0x400601
-+		);
-+
-+	write32(pmmio + ADPA, ADPA_DAC_ENABLE
-+			| ADPA_PIPE_A_SELECT
-+			| ADPA_USE_VGA_HVPOLARITY
-+			| ADPA_VSYNC_CNTL_ENABLE
-+			| ADPA_HSYNC_CNTL_ENABLE
-+			| ADPA_DPMS_ON
-+			);
-+
-+	write32(pmmio + HTOTAL(0),
-+		((hactive - 1) << 16)
-+		| (hactive - 1));
-+	write32(pmmio + HBLANK(0),
-+		((hactive - 1) << 16)
-+		| (hactive - 1));
-+	write32(pmmio + HSYNC(0),
-+		((hactive - 1) << 16)
-+		| (hactive - 1));
-+
-+	write32(pmmio + VTOTAL(0), ((vactive - 1) << 16)
-+		| (vactive - 1));
-+	write32(pmmio + VBLANK(0), ((vactive - 1) << 16)
-+		| (vactive - 1));
-+	write32(pmmio + VSYNC(0),
-+		((vactive - 1) << 16)
-+		| (vactive - 1));
-+
-+	write32(pmmio + PF_WIN_POS(0), 0);
-+
-+	write32(pmmio + PIPESRC(0), (639 << 16) | 399);
-+	write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
-+	write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16));
-+	write32(pmmio + PFIT_CONTROL, 0x0);
-+
-+	mdelay(1);
-+
-+	write32(pmmio + FDI_RX_CTL(0), 0x00002040);
-+	mdelay(1);
-+	write32(pmmio + FDI_RX_CTL(0), 0x80002050);
-+	write32(pmmio + FDI_TX_CTL(0), 0x00044000);
-+	mdelay(1);
-+	write32(pmmio + FDI_TX_CTL(0), 0x80044000);
-+	write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
-+
-+	write32(pmmio + VGACNTRL, 0x0);
-+	write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
-+	mdelay(1);
-+
-+	write32(pmmio + ADPA, ADPA_DAC_ENABLE
-+			| ADPA_PIPE_A_SELECT
-+			| ADPA_USE_VGA_HVPOLARITY
-+			| ADPA_VSYNC_CNTL_ENABLE
-+			| ADPA_HSYNC_CNTL_ENABLE
-+			| ADPA_DPMS_ON
-+			);
-+
-+	write32(pmmio + DSPFW3, 0x7f3f00c1);
-+	write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH);
-+	write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5));
-+	write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9));
-+
-+	/* Set up GTT.  */
-+
-+	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
-+	uma_size = 0;
-+	if (!(reg16 & 2)) {
-+		uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
-+		printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
-+	}
-+
-+	for (i = 0; i < (uma_size - 256) / 4; i++)
-+	{
-+		outl((i << 2) | 1, piobase);
-+		outl(pphysbase + (i << 12) + 1, piobase + 4);
-+	}
-+
-+	/* Clear interrupts. */
-+	write32(pmmio + DEIIR, 0xffffffff);
-+	write32(pmmio + SDEIIR, 0xffffffff);
-+	write32(pmmio + IIR, 0xffffffff);
-+	write32(pmmio + IMR, 0xffffffff);
-+	write32(pmmio + EIR, 0xffffffff);
-+
-+	vga_textmode_init();
-+
-+	/* Enable screen memory.  */
-+	vga_sr_write(1, vga_sr_read(1) & ~0x20);
-+
-+	return 0;
-+
-+}
-+
-+/* compare the header of the vga edid header */
-+/* if vga is not connected it should have a correct header */
-+static int vga_connected(u8 *pmmio) {
-+	u8 vga_edid[128];
-+	u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00};
-+	intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128);
-+	intel_gmbus_stop(pmmio + GMBUS0);
-+	for (int i = 0; i < 8; i++) {
-+		if (vga_edid[i] != header[i]) {
-+			printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n");
-+			return 0;
-+		}
-+	}
-+	printk(BIOS_SPEW, "VGA display connected\n");
-+	return 1;
-+}
-+
- #endif
- 
- static void gma_func0_init(struct device *dev)
-@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev)
- 	);
- 
- 	int err;
--	err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf,
-+	if (vga_connected(mmiobase))
-+		err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf,
-+					iobase, mmiobase, graphics_base);
-+	else
-+		err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf,
- 			     iobase, mmiobase, graphics_base);
- 	if (err == 0)
- 		gfx_set_init_done(1);
--- 
-2.9.3
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0004-mb-intel-d945gclf-Allow-use-of-native-graphic-init.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0004-mb-intel-d945gclf-Allow-use-of-native-graphic-init.patch
deleted file mode 100644
index bda565f9..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0004-mb-intel-d945gclf-Allow-use-of-native-graphic-init.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From d80a39744d7aad734e8d53f2b2d6cb6b5eeee834 Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Tue, 6 Sep 2016 23:03:04 +0200
-Subject: [PATCH 4/5] mb/intel/d945gclf: Allow use of native graphic init
-
-Adds pci device id to native graphic init and add a Native graphic init
-option in Kconfig.
-
-Change-Id: I136122daef70547830bcc87f568406be7162461f
-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
-
-diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig
-index 429a304..a83e613 100644
---- a/src/mainboard/intel/d945gclf/Kconfig
-+++ b/src/mainboard/intel/d945gclf/Kconfig
-@@ -29,6 +29,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
- 	select HAVE_ACPI_RESUME
- 	select BOARD_ROMSIZE_KB_512
- 	select CHANNEL_XOR_RANDOMIZATION
-+	select MAINBOARD_HAS_NATIVE_VGA_INIT
-+	select INTEL_EDID
- 
- config MAINBOARD_DIR
- 	string
-diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
-index 37674d7..abe7dd6 100644
---- a/src/northbridge/intel/i945/gma.c
-+++ b/src/northbridge/intel/i945/gma.c
-@@ -716,7 +716,7 @@ static struct device_operations gma_func1_ops = {
- 	.ops_pci		= &gma_pci_ops,
- };
- 
--static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0 };
-+static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0x2772, 0 };
- 
- static const struct pci_driver i945_gma_func0_driver __pci_driver = {
- 	.ops	= &gma_func0_ops,
--- 
-2.9.3
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0005-i945-gma.c-Only-init-LVDS-if-it-is-present-on-the-de.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0005-i945-gma.c-Only-init-LVDS-if-it-is-present-on-the-de.patch
deleted file mode 100644
index 3155ef90..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0005-i945-gma.c-Only-init-LVDS-if-it-is-present-on-the-de.patch
+++ /dev/null
@@ -1,97 +0,0 @@
-From 603387a7650a80c92f1064f17fbbf06d60c06f30 Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Tue, 6 Sep 2016 23:53:32 +0200
-Subject: [PATCH 5/5] i945/gma.c: Only init LVDS if it is present on the device
-
-Some devices have no LVDS output but if no VGA is connected or
-no edid can be found, it will try to init LVDS.
-
-This patch makes sure only devices that have an LVDS connector can use LVDS
-graphic initialisation.
-
-Change-Id: Ie15631514535bab6c881c1f52e9edbfb8aaa5db7
-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
-
-diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
-index e653c08..8ba3d77 100644
---- a/src/mainboard/apple/macbook21/Kconfig
-+++ b/src/mainboard/apple/macbook21/Kconfig
-@@ -35,6 +35,10 @@ config DCACHE_RAM_SIZE
- 	hex
- 	default 0x8000
- 
-+config HAS_LVDS
-+	bool
-+	default y
-+
- if BOARD_APPLE_MACBOOK21
- 
- config MAINBOARD_PART_NUMBER
-diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig
-index ea68bed..e74b70c 100644
---- a/src/mainboard/getac/p470/Kconfig
-+++ b/src/mainboard/getac/p470/Kconfig
-@@ -64,4 +64,8 @@ config VGA_BIOS_FILE
- 	string
- 	default "getac-pci8086,27a2.rom"
- 
-+config HAS_LVDS
-+	bool
-+	default y
-+
- endif # BOARD_GETAC_P470
-diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig
-index 52eeda3..e5a7554 100644
---- a/src/mainboard/lenovo/t60/Kconfig
-+++ b/src/mainboard/lenovo/t60/Kconfig
-@@ -54,4 +54,8 @@ config SEABIOS_PS2_TIMEOUT
- 	int
- 	default 3000
- 
-+config HAS_LVDS
-+	bool
-+	default y
-+
- endif
-diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig
-index ab4b58e..152e6b2 100644
---- a/src/mainboard/lenovo/x60/Kconfig
-+++ b/src/mainboard/lenovo/x60/Kconfig
-@@ -61,4 +61,8 @@ config SEABIOS_PS2_TIMEOUT
- 	int
- 	default 3000
- 
-+config HAS_LVDS
-+	bool
-+	default y
-+
- endif
-diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
-index 6e8d35b..ae7961f 100644
---- a/src/northbridge/intel/i945/Kconfig
-+++ b/src/northbridge/intel/i945/Kconfig
-@@ -71,4 +71,8 @@ config CHECK_SLFRCS_ON_RESUME
- 	  On other boards the check always creates a false positive,
- 	  effectively making it impossible to resume.
- 
-+config HAS_LVDS
-+	bool
-+	default n
-+
- endif
-diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
-index abe7dd6..be299f4 100644
---- a/src/northbridge/intel/i945/gma.c
-+++ b/src/northbridge/intel/i945/gma.c
-@@ -611,7 +611,7 @@ static void gma_func0_init(struct device *dev)
- 	);
- 
- 	int err;
--	if (vga_connected(mmiobase))
-+	if (!CONFIG_HAS_LVDS || vga_connected(mmiobase))
- 		err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf,
- 					iobase, mmiobase, graphics_base);
- 	else
--- 
-2.9.3
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/INFO b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/INFO
deleted file mode 100644
index ad7d12f4..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/INFO
+++ /dev/null
@@ -1,4 +0,0 @@
-# NOTE: remove this when updating coreboot. This has been merged upstream
-printf "ThinkPad R400 support (clone of the T400)\n"
-git am "../resources/libreboot/patch/misc/0007-lenovo-r400-Add-clone-of-Lenovo-T400.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/93/8393/5 && git cherry-pick FETCH_HEAD
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list
deleted file mode 100644
index 145d6c30..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_16mb/reused.list
+++ /dev/null
@@ -1,6 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb//0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list
deleted file mode 100644
index 30301d55..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_4mb/reused.list
+++ /dev/null
@@ -1,6 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/INFO b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/INFO
deleted file mode 100644
index ad7d12f4..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/INFO
+++ /dev/null
@@ -1,4 +0,0 @@
-# NOTE: remove this when updating coreboot. This has been merged upstream
-printf "ThinkPad R400 support (clone of the T400)\n"
-git am "../resources/libreboot/patch/misc/0007-lenovo-r400-Add-clone-of-Lenovo-T400.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/93/8393/5 && git cherry-pick FETCH_HEAD
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list
deleted file mode 100644
index 30301d55..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/r400_8mb/reused.list
+++ /dev/null
@@ -1,6 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/INFO b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/INFO
deleted file mode 100644
index 9ef6d54a..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/INFO
+++ /dev/null
@@ -1,8 +0,0 @@
-# NOTE: merged upstream already
-printf "mainboard/lenovo/t400: Add initial hybrid graphics support\n"
-git am "../resources/libreboot/patch/misc/0001-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/19/9319/18 && git cherry-pick FETCH_HEAD
-
-printf "NOTFORMERGE: lenovo/t400: hard-code enable integrated-only video\n"
-git am "../resources/libreboot/patch/misc/0002-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/50/10550/1 && git cherry-pick FETCH_HEAD
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list
deleted file mode 100644
index 30301d55..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_16mb/reused.list
+++ /dev/null
@@ -1,6 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list
deleted file mode 100644
index 30301d55..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_4mb/reused.list
+++ /dev/null
@@ -1,6 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch
deleted file mode 100644
index 67420ca7..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch
+++ /dev/null
@@ -1,601 +0,0 @@
-From fbbc8d6a278c733eca475c17cbf95a8946e2c173 Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Thu, 4 Aug 2016 11:00:13 +0200
-Subject: [PATCH 1/3] Revert "drivers/lenovo: Add hybrid graphics driver"
-
-This reverts commit 5919ba42ed0ce5b1b13717514698444232c6036c.
-
-Change-Id: I027581ef769ca8232e72f89738c1bdec13f62687
-
-diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig
-index f8eddf2..f20f3b2 100644
---- a/src/drivers/lenovo/Kconfig
-+++ b/src/drivers/lenovo/Kconfig
-@@ -27,16 +27,3 @@ config DIGITIZER_ABSENT
- endchoice
- 
- endif
--
--config DRIVERS_LENOVO_HYBRID_GRAPHICS
--	bool
--	default n
--
--config HYBRID_GRAPHICS_GPIO_NUM
--	depends on DRIVERS_LENOVO_HYBRID_GRAPHICS
--	int
--	default 52
--	help
--	  Set a default GPIO that sets the panel LVDS signal routing to
--	  integrated or discrete GPU.
--
-diff --git a/src/drivers/lenovo/Makefile.inc b/src/drivers/lenovo/Makefile.inc
-index 66f8594..c50db5b 100644
---- a/src/drivers/lenovo/Makefile.inc
-+++ b/src/drivers/lenovo/Makefile.inc
-@@ -1,2 +1 @@
- ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c
--ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c
-diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c
-deleted file mode 100644
-index 9b46646..0000000
---- a/src/drivers/lenovo/hybrid_graphics.c
-+++ /dev/null
-@@ -1,125 +0,0 @@
--/*
-- * This file is part of the coreboot project.
-- *
-- * Copyright (C) 2015-2016 Patrick Rudolph
-- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-- *
-- * This program is free software; you can redistribute it and/or modify
-- * it under the terms of the GNU General Public License as published by
-- * the Free Software Foundation; version 2 of the License.
-- *
-- * This program is distributed in the hope that it will be useful,
-- * but WITHOUT ANY WARRANTY; without even the implied warranty of
-- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- * GNU General Public License for more details.
-- */
--
--#include <types.h>
--#include <string.h>
--#include <option.h>
--#include <device/device.h>
--#include <device/pci_def.h>
--#include <device/pci_ops.h>
--#include <device/pci_ids.h>
--#include <device/pci.h>
--#include <console/console.h>
--#include <southbridge/intel/common/gpio.h>
--
--/* Hybrid graphics allows to connect LVDS interface to either iGPU
-- * or dGPU depending on GPIO level.
-- * Nvidia is calling this functionality "muxed Optimus".
-- * Some devices, like T430s, only support "muxless Optimus" where the
-- * Intel GPU is always connected to the panel.
-- * As it is only linked on lenovo and only executed if the GPU exists
-- * we know for sure that the dGPU is there and connected to first PEG slot.
-- *
-- * Note: Once native gfx init is done for AMD or Nvida graphic
-- *       cards, merge this code.
-- */
--
--#define HYBRID_GRAPHICS_INTEGRATED 0
--#define HYBRID_GRAPHICS_DISCRETE 1
--
--static void hybrid_graphics_disable_peg(struct device *dev)
--{
--	struct device *peg_dev;
--
--	/* connect LVDS interface to iGPU */
--	set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH);
--	printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n");
--	dev->enabled = 0;
--
--	/* Disable PEG10 */
--	peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0));
--	if (peg_dev)
--		peg_dev->enabled = 0;
--
--	printk(BIOS_DEBUG, "Hybrid graphics: Disabled PEG10.\n");
--}
--
--/* Called before VGA enable bits are set and only if dGPU
-- * is present. Enable/disable VGA devices here. */
--static void hybrid_graphics_enable_peg(struct device *dev)
--{
--	u8 hybrid_graphics_mode;
--
--	hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED;
--	get_option(&hybrid_graphics_mode, "hybrid_graphics_mode");
--
--	if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) {
--		/* connect LVDS interface to dGPU */
--		set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW);
--		printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n");
--		dev->enabled = 1;
--
--		/* Disable IGD */
--		dev = dev_find_slot(0, PCI_DEVFN(2, 0));
--		if (dev && dev->ops->disable)
--			dev->ops->disable(dev);
--		dev->enabled = 0;
--
--		printk(BIOS_DEBUG, "Hybrid graphics: Disabled IGD.\n");
--	} else
--		hybrid_graphics_disable_peg(dev);
--}
--
--static struct pci_operations pci_dev_ops_pci = {
--	.set_subsystem = pci_dev_set_subsystem,
--};
--
--struct device_operations hybrid_graphics_ops = {
--	.read_resources   = pci_dev_read_resources,
--	.set_resources    = pci_dev_set_resources,
--	.enable_resources = pci_dev_enable_resources,
--	.init             = pci_dev_init,
--	.scan_bus         = 0,
--	.enable           = hybrid_graphics_enable_peg,
--	.disable          = hybrid_graphics_disable_peg,
--	.ops_pci          = &pci_dev_ops_pci,
--};
--
--static const unsigned short pci_device_ids_nvidia[] = {
--		0x0ffc, /* Nvidia NVS Quadro K1000m Lenovo W530 */
--		0x0def, /* NVidia NVS 5400m Lenovo T430/T530 */
--		0x0dfc, /* NVidia NVS 5200m Lenovo T430s */
--		0x1056, /* NVidia NVS 4200m Lenovo T420/T520 */
--		0x1057, /* NVidia NVS 4200m Lenovo T420/T520 */
--		0x0a6c, /* NVidia NVS 3100m Lenovo T410/T510 */
--		0 };
--
--static const struct pci_driver hybrid_peg_nvidia __pci_driver = {
--	.ops	 = &hybrid_graphics_ops,
--	.vendor	 = PCI_VENDOR_ID_NVIDIA,
--	.devices = pci_device_ids_nvidia,
--};
--
--static const unsigned short pci_device_ids_amd[] = {
--		0x9591, /* ATI Mobility Radeon HD 3650 Lenovo T500/W500 */
--		0x95c4, /* ATI Mobility Radeon HD 3470 Lenovo T400/R400 */
--		0 };
--
--static const struct pci_driver hybrid_peg_amd __pci_driver = {
--	.ops	 = &hybrid_graphics_ops,
--	.vendor	 = PCI_VENDOR_ID_ATI,
--	.devices = pci_device_ids_amd,
--};
-diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig
-index a444bf8..d74a813 100644
---- a/src/mainboard/lenovo/t400/Kconfig
-+++ b/src/mainboard/lenovo/t400/Kconfig
-@@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
- 	select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
- 	select INTEL_INT15
- 	select SUPERIO_NSC_PC87382
--	select DRIVERS_LENOVO_HYBRID_GRAPHICS
- 
- config MAINBOARD_DIR
- 	string
-diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
-index 5cf3e63..ac9f96d 100644
---- a/src/mainboard/lenovo/t400/cmos.default
-+++ b/src/mainboard/lenovo/t400/cmos.default
-@@ -13,5 +13,3 @@ sticky_fn=Disable
- power_management_beeps=Enable
- low_battery_beep=Enable
- sata_mode=AHCI
--hybrid_graphics_mode=Integrated Only
--gfx_uma_size=32M
-\ No newline at end of file
-diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout
-index b4b7766..e1a088d 100644
---- a/src/mainboard/lenovo/t400/cmos.layout
-+++ b/src/mainboard/lenovo/t400/cmos.layout
-@@ -77,8 +77,7 @@ entries
- 940         1       e       1        uwb
- 
- # coreboot config options: northbridge
--944         2       e       12       hybrid_graphics_mode
--946         4       e       11       gfx_uma_size
-+941         4       e       11       gfx_uma_size
- 
- # coreboot config options: EC
- 952         8       h       0        volume
-diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
-index 3a82c97..1b8e212 100644
---- a/src/mainboard/lenovo/t420/cmos.default
-+++ b/src/mainboard/lenovo/t420/cmos.default
-@@ -14,4 +14,3 @@ fn_ctrl_swap=Disable
- sticky_fn=Disable
- trackpoint=Enable
- hyper_threading=Enable
--hybrid_graphics_mode=Integrated Only
-\ No newline at end of file
-diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout
-index 58a4abe..bf0f195 100644
---- a/src/mainboard/lenovo/t420/cmos.layout
-+++ b/src/mainboard/lenovo/t420/cmos.layout
-@@ -77,8 +77,7 @@ entries
- 
- # coreboot config options: northbridge
- 432          3       e       11       gfx_uma_size
--435          2        e       12       hybrid_graphics_mode
--#437         3        r       0        unused
-+#435          5       r       0        unused
- 
- 440          8       h       0        volume
- 
-@@ -136,8 +135,6 @@ enumerations
- 11    4     160M
- 11    5     192M
- 11    6     224M
--12    0     Integrated Only
--12    1     Discrete Only
- 
- # -----------------------------------------------------------------
- checksums
-diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig
-index feacb51..935e659 100644
---- a/src/mainboard/lenovo/t420s/Kconfig
-+++ b/src/mainboard/lenovo/t420s/Kconfig
-@@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
- 	select INTEL_INT15
- 	select SANDYBRIDGE_IVYBRIDGE_LVDS
- 	select MAINBOARD_HAS_LPC_TPM
--	select DRIVERS_LENOVO_HYBRID_GRAPHICS
- 
- 	# Workaround for EC/KBC IRQ1.
- 	select SERIRQ_CONTINUOUS_MODE
-diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
-index 3a82c97..1b8e212 100644
---- a/src/mainboard/lenovo/t420s/cmos.default
-+++ b/src/mainboard/lenovo/t420s/cmos.default
-@@ -14,4 +14,3 @@ fn_ctrl_swap=Disable
- sticky_fn=Disable
- trackpoint=Enable
- hyper_threading=Enable
--hybrid_graphics_mode=Integrated Only
-\ No newline at end of file
-diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout
-index 3521849..43628406 100644
---- a/src/mainboard/lenovo/t420s/cmos.layout
-+++ b/src/mainboard/lenovo/t420s/cmos.layout
-@@ -77,8 +77,7 @@ entries
- 
- # coreboot config options: northbridge
- 432          3       e       11       gfx_uma_size
--435          2       e       12       hybrid_graphics_mode
--#437         3       r       0        unused
-+#435         5       r       0        unused
- 
- 440          8       h       0        volume
- 
-@@ -136,8 +135,6 @@ enumerations
- 11    4     160M
- 11    5     192M
- 11    6     224M
--12    0     Integrated Only
--12    1     Discrete Only
- 
- # -----------------------------------------------------------------
- checksums
-diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig
-index ee5dd81..c70581a 100644
---- a/src/mainboard/lenovo/t520/Kconfig
-+++ b/src/mainboard/lenovo/t520/Kconfig
-@@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
- 	select INTEL_INT15
- 	select SANDYBRIDGE_IVYBRIDGE_LVDS
- 	select MAINBOARD_HAS_LPC_TPM
--	select DRIVERS_LENOVO_HYBRID_GRAPHICS
- 
- 	# Workaround for EC/KBC IRQ1.
- 	select SERIRQ_CONTINUOUS_MODE
-diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
-index ad7dcf5..00e8863 100644
---- a/src/mainboard/lenovo/t520/cmos.default
-+++ b/src/mainboard/lenovo/t520/cmos.default
-@@ -15,4 +15,3 @@ sticky_fn=Disable
- trackpoint=Enable
- hyper_threading=Enable
- backlight=Both
--hybrid_graphics_mode=Integrated Only
-\ No newline at end of file
-diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout
-index 044c310..2cf3629 100644
---- a/src/mainboard/lenovo/t520/cmos.layout
-+++ b/src/mainboard/lenovo/t520/cmos.layout
-@@ -77,8 +77,7 @@ entries
- 
- # coreboot config options: northbridge
- 432         3        e      11        gfx_uma_size
--435         2        e       12       hybrid_graphics_mode
--#437        3        r       0        unused
-+#435        5        r       0        unused
- 440         8        h       0        volume
- 
- # SandyBridge MRC Scrambler Seed values
-@@ -135,8 +134,6 @@ enumerations
- 11    4	    160M
- 11    5	    192M
- 11    6	    224M
--12    0     Integrated Only
--12    1     Discrete Only
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig
-index 76147fc..030c01f 100644
---- a/src/mainboard/lenovo/t530/Kconfig
-+++ b/src/mainboard/lenovo/t530/Kconfig
-@@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
- 	select SANDYBRIDGE_IVYBRIDGE_LVDS
- 	select ENABLE_VMX
- 	select MAINBOARD_HAS_LPC_TPM
--	select DRIVERS_LENOVO_HYBRID_GRAPHICS
- 
- 	# Workaround for EC/KBC IRQ1.
- 	select SERIRQ_CONTINUOUS_MODE
-diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
-index ad7dcf5..00e8863 100644
---- a/src/mainboard/lenovo/t530/cmos.default
-+++ b/src/mainboard/lenovo/t530/cmos.default
-@@ -15,4 +15,3 @@ sticky_fn=Disable
- trackpoint=Enable
- hyper_threading=Enable
- backlight=Both
--hybrid_graphics_mode=Integrated Only
-\ No newline at end of file
-diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout
-index 0e28bdd..e21c197 100644
---- a/src/mainboard/lenovo/t530/cmos.layout
-+++ b/src/mainboard/lenovo/t530/cmos.layout
-@@ -77,8 +77,7 @@ entries
- 
- # coreboot config options: northbridge
- 432         3        e      11        gfx_uma_size
--435         2        e       12       hybrid_graphics_mode
--#437        3        r       0        unused
-+#435        5        r       0        unused
- 
- 440          8       h       0        volume
- 
-@@ -136,9 +135,6 @@ enumerations
- 11    4	    160M
- 11    5	    192M
- 11    6	    224M
--12    0     Integrated Only
--12    1     Discrete Only
--
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
-index b3e5069..2822774 100644
---- a/src/southbridge/intel/i82801ix/Kconfig
-+++ b/src/southbridge/intel/i82801ix/Kconfig
-@@ -23,7 +23,6 @@ config SOUTHBRIDGE_INTEL_I82801IX
- 	select USE_WATCHDOG_ON_BOOT
- 	select HAVE_SMI_HANDLER
- 	select HAVE_USBDEBUG_OPTIONS
--	select SOUTHBRIDGE_INTEL_COMMON_GPIO
- 
- if SOUTHBRIDGE_INTEL_I82801IX
- 
--- 
-2.9.2
-
-From 90f5f34629ff88506bb803988da1552f3373d4f0 Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Thu, 4 Aug 2016 11:01:53 +0200
-Subject: [PATCH 2/3] Revert "Revert "mainboard/lenovo/t400: Add initial hybrid
- graphics support""
-
-This reverts commit 14d1a93e444b91311eeed2a25953bf6c0779cdcb.
-
-Change-Id: I965ea55bddb7cf919e7b02ecf8e160c9ad3ea3d4
-
-diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
-index ac9f96d..98ce970 100644
---- a/src/mainboard/lenovo/t400/cmos.default
-+++ b/src/mainboard/lenovo/t400/cmos.default
-@@ -13,3 +13,4 @@ sticky_fn=Disable
- power_management_beeps=Enable
- low_battery_beep=Enable
- sata_mode=AHCI
-+hybrid_graphics_mode=Integrated Only
-\ No newline at end of file
-diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout
-index e1a088d..b4b7766 100644
---- a/src/mainboard/lenovo/t400/cmos.layout
-+++ b/src/mainboard/lenovo/t400/cmos.layout
-@@ -77,7 +77,8 @@ entries
- 940         1       e       1        uwb
- 
- # coreboot config options: northbridge
--941         4       e       11       gfx_uma_size
-+944         2       e       12       hybrid_graphics_mode
-+946         4       e       11       gfx_uma_size
- 
- # coreboot config options: EC
- 952         8       h       0        volume
-diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
-index f518775..fcc545b 100644
---- a/src/mainboard/lenovo/t400/romstage.c
-+++ b/src/mainboard/lenovo/t400/romstage.c
-@@ -1,6 +1,7 @@
- /*
-  * This file is part of the coreboot project.
-  *
-+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
-  * Copyright (C) 2012 secunet Security Networks AG
-  *
-  * This program is free software; you can redistribute it and/or
-@@ -34,6 +35,118 @@
- #define LPC_DEV PCI_DEV(0, 0x1f, 0)
- #define MCH_DEV PCI_DEV(0, 0, 0)
- 
-+#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0
-+#define HYBRID_GRAPHICS_DISCRETE_ONLY 1
-+#define HYBRID_GRAPHICS_SWITCHABLE 2
-+
-+#define HYBRID_GRAPHICS_GP_LVL_BITS 0x004a0000
-+#define HYBRID_GRAPHICS_GP_LVL2_BITS 0x00020000
-+
-+#define HYBRID_GRAPHICS_DETECT_GP_BITS 0x00000010
-+
-+#define HYBRID_GRAPHICS_INT_CLAIM_VGA 0x2
-+#define HYBRID_GRAPHICS_SEC_VGA_EN 0x2
-+
-+static void hybrid_graphics_configure_switchable_graphics(bool enable)
-+{
-+	uint32_t tmp;
-+
-+	if (enable) {
-+		/* Disable integrated graphics legacy VGA cycles */
-+		tmp = pci_read_config16(MCH_DEV, D0F0_GGC);
-+		pci_write_config16(MCH_DEV, D0F0_GGC, tmp | HYBRID_GRAPHICS_INT_CLAIM_VGA);
-+
-+		/* Enable secondary VGA controller */
-+		tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN);
-+		pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp | HYBRID_GRAPHICS_SEC_VGA_EN);
-+	}
-+	else {
-+		/* Enable integrated graphics legacy VGA cycles */
-+		tmp = pci_read_config16(MCH_DEV, D0F0_GGC);
-+		pci_write_config16(MCH_DEV, D0F0_GGC, tmp & ~HYBRID_GRAPHICS_INT_CLAIM_VGA);
-+
-+		/* Disable secondary VGA controller */
-+		tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN);
-+		pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp & ~HYBRID_GRAPHICS_SEC_VGA_EN);
-+	}
-+}
-+
-+static void hybrid_graphics_set_up_gpio(void)
-+{
-+	uint32_t tmp;
-+
-+	/* Enable hybrid graphics GPIO lines */
-+	tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL);
-+	tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS;
-+	outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL);
-+
-+	tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL2);
-+	tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS;
-+	outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL2);
-+
-+	/* Set hybrid graphics control GPIO lines to output */
-+	tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL);
-+	tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS;
-+	outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL);
-+
-+	tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL2);
-+	tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS;
-+	outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL2);
-+
-+	/* Set hybrid graphics detect GPIO lines to input */
-+	tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL);
-+	tmp = tmp | HYBRID_GRAPHICS_DETECT_GP_BITS;
-+	outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL);
-+}
-+
-+static bool hybrid_graphics_installed(void)
-+{
-+	if (inl(DEFAULT_GPIOBASE + GP_LVL) & HYBRID_GRAPHICS_DETECT_GP_BITS)
-+		return false;
-+	else
-+		return true;
-+}
-+
-+static void hybrid_graphics_switch_to_integrated_graphics(void)
-+{
-+	uint32_t tmp;
-+
-+	/* Disable switchable graphics */
-+	hybrid_graphics_configure_switchable_graphics(false);
-+
-+	/* Configure muxes */
-+	tmp = inl(DEFAULT_GPIOBASE + GP_LVL);
-+	tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS;
-+	outl(tmp, DEFAULT_GPIOBASE + GP_LVL);
-+
-+	tmp = inl(DEFAULT_GPIOBASE + GP_LVL2);
-+	tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS;
-+	outl(tmp, DEFAULT_GPIOBASE + GP_LVL2);
-+}
-+
-+static void hybrid_graphics_switch_to_discrete_graphics(void)
-+{
-+	uint32_t tmp;
-+
-+	/* Disable switchable graphics */
-+	hybrid_graphics_configure_switchable_graphics(false);
-+
-+	/* Configure muxes */
-+	tmp = inl(DEFAULT_GPIOBASE + GP_LVL);
-+	tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS;
-+	outl(tmp, DEFAULT_GPIOBASE + GP_LVL);
-+
-+	tmp = inl(DEFAULT_GPIOBASE + GP_LVL2);
-+	tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS;
-+	outl(tmp, DEFAULT_GPIOBASE + GP_LVL2);
-+}
-+
-+static void hybrid_graphics_switch_to_dual_graphics(void)
-+{
-+	/* Enable switchable graphics */
-+	hybrid_graphics_configure_switchable_graphics(true);
-+}
-+
- static void default_southbridge_gpio_setup(void)
- {
- 	outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL);
-@@ -95,6 +208,31 @@ void mainboard_romstage_entry(unsigned long bist)
- 
- 	default_southbridge_gpio_setup();
- 
-+	uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY;
-+	get_option(&hybrid_graphics_mode, "hybrid_graphics_mode");
-+
-+	/* Set up hybrid graphics */
-+	hybrid_graphics_set_up_gpio();
-+	if (hybrid_graphics_installed()) {
-+		/* Select appropriate hybrid graphics device */
-+		printk(BIOS_DEBUG, "Hybrid graphics available, setting mode %d\n", hybrid_graphics_mode);
-+		if (hybrid_graphics_mode == HYBRID_GRAPHICS_INTEGRATED_ONLY)
-+			hybrid_graphics_switch_to_integrated_graphics();
-+		else if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE_ONLY)
-+			hybrid_graphics_switch_to_discrete_graphics();
-+		else if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE)
-+			hybrid_graphics_switch_to_integrated_graphics();
-+			/* Switchable graphics are fully enabled after raminit */
-+			/* FIXME
-+			 * Enabling switchable graphics prevents bootup!
-+			 * Debug and fix appropriately...
-+			 */
-+	}
-+	else {
-+		printk(BIOS_DEBUG, "Hybrid graphics not installed\n");
-+		hybrid_graphics_switch_to_integrated_graphics();
-+	}
-+
- 	/* ASPM related setting, set early by original BIOS. */
- 	DMIBAR16(0x204) &= ~(3 << 10);
- 
-@@ -174,6 +312,11 @@ void mainboard_romstage_entry(unsigned long bist)
- 	outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38);
- 
- 	cbmem_initted = !cbmem_recovery(s3resume);
-+
-+	if (hybrid_graphics_installed())
-+		if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE)
-+			hybrid_graphics_switch_to_dual_graphics();
-+
- #if CONFIG_HAVE_ACPI_RESUME
- 	/* If there is no high memory area, we didn't boot before, so
- 	 * this is not a resume. In that case we just create the cbmem toc.
--- 
-2.9.2
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch
deleted file mode 100644
index 49b9549a..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 873402fb594f06e748563ebf3abc7970613b9bda Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Mon, 8 Aug 2016 23:55:13 +0200
-Subject: [PATCH] make 256M vram the default for gm45 laptops
-
-Change-Id: Id213807d1ed3260846118f69b459bcad7a146c30
-
-diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
-index 98ce970..90d796f 100644
---- a/src/mainboard/lenovo/t400/cmos.default
-+++ b/src/mainboard/lenovo/t400/cmos.default
-@@ -13,4 +13,5 @@ sticky_fn=Disable
- power_management_beeps=Enable
- low_battery_beep=Enable
- sata_mode=AHCI
--hybrid_graphics_mode=Integrated Only
-\ No newline at end of file
-+hybrid_graphics_mode=Integrated Only
-+gfx_uma_size=256M
-\ No newline at end of file
-diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
-index 1d7b420..ec7ab46 100644
---- a/src/mainboard/lenovo/x200/cmos.default
-+++ b/src/mainboard/lenovo/x200/cmos.default
-@@ -13,4 +13,4 @@ sticky_fn=Disable
- power_management_beeps=Enable
- low_battery_beep=Enable
- sata_mode=AHCI
--gfx_uma_size=32M
-\ No newline at end of file
-+gfx_uma_size=256M
-\ No newline at end of file
--- 
-2.9.2
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch
deleted file mode 100644
index 76463937..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 99b8fb271fd244d8e349ca956819c7e1b3420d80 Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Mon, 8 Aug 2016 21:51:34 +0200
-Subject: [PATCH] hardcode use on intel integrated graphic device on t400
-
-Change-Id: I2ff2d93b024866063715d26aedf510a9753a5445
----
- src/mainboard/lenovo/t400/romstage.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c
-index 147131f..1316d69 100644
---- a/src/mainboard/lenovo/t400/romstage.c
-+++ b/src/mainboard/lenovo/t400/romstage.c
-@@ -208,7 +208,8 @@ void main(unsigned long bist)
- 	default_southbridge_gpio_setup();
- 
- 	uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY;
--	get_option(&hybrid_graphics_mode, "hybrid_graphics_mode");
-+	/* hardcode use of integrated graphic device for libreboot */
-+	/* get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); */
- 
- 	/* Set up hybrid graphics */
- 	hybrid_graphics_set_up_gpio();
--- 
-2.9.2
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/INFO b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/INFO
deleted file mode 100644
index 9ef6d54a..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/INFO
+++ /dev/null
@@ -1,8 +0,0 @@
-# NOTE: merged upstream already
-printf "mainboard/lenovo/t400: Add initial hybrid graphics support\n"
-git am "../resources/libreboot/patch/misc/0001-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/19/9319/18 && git cherry-pick FETCH_HEAD
-
-printf "NOTFORMERGE: lenovo/t400: hard-code enable integrated-only video\n"
-git am "../resources/libreboot/patch/misc/0002-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/50/10550/1 && git cherry-pick FETCH_HEAD
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list
deleted file mode 100644
index 0ed8edc9..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/reused.list
+++ /dev/null
@@ -1,3 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/INFO b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/INFO
deleted file mode 100644
index 0537bbc8..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/INFO
+++ /dev/null
@@ -1,4 +0,0 @@
-# NOTE: remove this when updating coreboot. This has been merged upstream
-printf "ThinkPad T500 (depends on T400 patch)\n"
-git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list
deleted file mode 100644
index 30301d55..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_16mb/reused.list
+++ /dev/null
@@ -1,6 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list
deleted file mode 100644
index 30301d55..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_4mb/reused.list
+++ /dev/null
@@ -1,6 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/INFO b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/INFO
deleted file mode 100644
index 0537bbc8..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/INFO
+++ /dev/null
@@ -1,4 +0,0 @@
-# NOTE: remove this when updating coreboot. This has been merged upstream
-printf "ThinkPad T500 (depends on T400 patch)\n"
-git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list
deleted file mode 100644
index 30301d55..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t500_8mb/reused.list
+++ /dev/null
@@ -1,6 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/INFO b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/INFO
deleted file mode 100644
index 0537bbc8..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/INFO
+++ /dev/null
@@ -1,4 +0,0 @@
-# NOTE: remove this when updating coreboot. This has been merged upstream
-printf "ThinkPad T500 (depends on T400 patch)\n"
-git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/reused.list
deleted file mode 100644
index 30301d55..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_16mb/reused.list
+++ /dev/null
@@ -1,6 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/reused.list
deleted file mode 100644
index 30301d55..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_4mb/reused.list
+++ /dev/null
@@ -1,6 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/INFO b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/INFO
deleted file mode 100644
index 0537bbc8..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/INFO
+++ /dev/null
@@ -1,4 +0,0 @@
-# NOTE: remove this when updating coreboot. This has been merged upstream
-printf "ThinkPad T500 (depends on T400 patch)\n"
-git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/reused.list
deleted file mode 100644
index 30301d55..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/w500_8mb/reused.list
+++ /dev/null
@@ -1,6 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0001-Revert-hybrid-driver.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/INFO b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/INFO
deleted file mode 100644
index 220b8583..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/INFO
+++ /dev/null
@@ -1,5 +0,0 @@
-# NOTE: remove this when updating to the latest version of coreboot. this patch
-# makes the patch below redundant: https://review.coreboot.org/#/c/12814/
-printf "northbridge/gm45/raminit.c: enable GS45 high-perf (i.e. add X200S support to libreboot)\n"
-git am "../resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/35/11135/3 && git cherry-pick FETCH_HEAD
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list
deleted file mode 100644
index 71fc4dfc..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_16mb/reused.list
+++ /dev/null
@@ -1,4 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list
deleted file mode 100644
index 71fc4dfc..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_4mb/reused.list
+++ /dev/null
@@ -1,4 +0,0 @@
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch
-/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
deleted file mode 100644
index 8e5e1dca..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch
+++ /dev/null
@@ -1,88 +0,0 @@
-From 63db6e96d846b8cab2df30afdccc6b6b18232e33 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Mon, 13 Oct 2014 00:14:53 +0100
-Subject: [PATCH] NOTFORMERGE: ec/lenovo/h8:
- wlan/trackpoint/touchpad/bluetooth/wwan
-
-Permanently enable them.
-
-Change-Id: Ic76ab9ab9c865f30312378e18af58bece6c3260a
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/ec/lenovo/h8/h8.c     | 21 +++++++++++----------
- src/ec/lenovo/pmh7/pmh7.c | 11 ++++-------
- 2 files changed, 15 insertions(+), 17 deletions(-)
-
-diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c
-index 943bdd4..32285ac 100644
---- a/src/ec/lenovo/h8/h8.c
-+++ b/src/ec/lenovo/h8/h8.c
-@@ -252,9 +252,11 @@ static void h8_enable(struct device *dev)
- 
- 	ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO);
- 
--	if (get_option(&val, "wlan") != CB_SUCCESS)
--		val = 1;
--	h8_wlan_enable(val);
-+	// Permanently enable wifi
-+	// Intel wifi could be a security risk because it uses firmware. Wlan chip has DMA
-+	// and could leak data over a side-channel. Using another manufacturer is recommended.
-+	// see http://libreboot.org/docs/index.html#recommended_wifi
-+	h8_wlan_enable(1);
- 
- 	h8_trackpoint_enable(1);
- 	h8_usb_power_enable(1);
-@@ -262,14 +264,13 @@ static void h8_enable(struct device *dev)
- 	if (get_option(&val, "volume") == CB_SUCCESS && !acpi_is_wakeup_s3())
- 		ec_write(H8_VOLUME_CONTROL, val);
- 
--	if (get_option(&val, "bluetooth") != CB_SUCCESS)
--		val = 1;
--	h8_bluetooth_enable(val);
--
--	if (get_option(&val, "wwan") != CB_SUCCESS)
--		val = 1;
-+	// Permanently enable bluetooth.
-+	// NOTE: bluetooth is a potential security risk. Physical removal of the bluetooth module is recommended.
-+	h8_bluetooth_enable(1);
- 
--	h8_wwan_enable(val);
-+	// Permanently enable wwan.
-+	// NOTE: wwan is a security risk (remove access plus DMA). Physical removal of both the wwan and sim card is recommended.
-+	h8_wwan_enable(1);
- 
- 	if (conf->has_uwb) {
- 		if (get_option(&val, "uwb") != CB_SUCCESS)
-diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c
-index b2c3c08..1570cd6 100644
---- a/src/ec/lenovo/pmh7/pmh7.c
-+++ b/src/ec/lenovo/pmh7/pmh7.c
-@@ -102,7 +102,6 @@ static void enable_dev(struct device *dev)
- {
- 	struct ec_lenovo_pmh7_config *conf = dev->chip_info;
- 	struct resource *resource;
--	u8 val;
- 
- 	resource = new_resource(dev, EC_LENOVO_PMH7_INDEX);
- 	resource->flags = IORESOURCE_IO | IORESOURCE_FIXED;
-@@ -114,13 +113,11 @@ static void enable_dev(struct device *dev)
- 	pmh7_backlight_enable(conf->backlight_enable);
- 	pmh7_dock_event_enable(conf->dock_event_enable);
- 
--	if (get_option(&val, "touchpad") != CB_SUCCESS)
--		val = 1;
--	pmh7_touchpad_enable(val);
-+	// Permanently enable touchpad
-+	pmh7_touchpad_enable(1);
- 
--	if (get_option(&val, "trackpoint") != CB_SUCCESS)
--		val = 1;
--	pmh7_trackpoint_enable(val);
-+	// Permanently enable trackpoint
-+	pmh7_trackpoint_enable(1);
- }
- 
- struct chip_operations ec_lenovo_pmh7_ops = {
--- 
-1.9.1
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
deleted file mode 100644
index 046192dd..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From c63113e56ad2d5f6b318a837e4345e0e962a5c1b Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Wed, 4 May 2016 22:49:07 +0200
-Subject: [PATCH 1/1] add acpi c3 / cpu  c4 state for gm45 thinpads
-
----
- src/mainboard/lenovo/t400/cstates.c | 5 +++++
- src/mainboard/lenovo/x200/cstates.c | 5 +++++
- 2 files changed, 10 insertions(+)
-
-diff --git a/src/mainboard/lenovo/t400/cstates.c b/src/mainboard/lenovo/t400/cstates.c
-index 827f76e..7d92d6f 100644
---- a/src/mainboard/lenovo/t400/cstates.c
-+++ b/src/mainboard/lenovo/t400/cstates.c
-@@ -27,6 +27,11 @@ static acpi_cstate_t cst_entries[] = {
- 		/* acpi C2 / cpu C2 */
- 		2, 0x01,  500,
- 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
-+	},	
-+	{
-+	        /* acpi C3 / cpu C4 */
-+		3, 0x02,  300,
-+		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x30, 0 }		
- 	},
- };
- 
-diff --git a/src/mainboard/lenovo/x200/cstates.c b/src/mainboard/lenovo/x200/cstates.c
-index 827f76e..7d92d6f 100644
---- a/src/mainboard/lenovo/x200/cstates.c
-+++ b/src/mainboard/lenovo/x200/cstates.c
-@@ -27,6 +27,11 @@ static acpi_cstate_t cst_entries[] = {
- 		/* acpi C2 / cpu C2 */
- 		2, 0x01,  500,
- 		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 }
-+	},	
-+	{
-+	        /* acpi C3 / cpu C4 */
-+		3, 0x02,  300,
-+		{ ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x30, 0 }		
- 	},
- };
- 
--- 
-2.8.2
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
deleted file mode 100644
index 61b36eb6..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-gm45-gma.c-clean-up-some-registers.patch
+++ /dev/null
@@ -1,229 +0,0 @@
-From 79f4b168666e484191ed3196dffe691953ee783b Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Mon, 15 Aug 2016 00:04:34 +0200
-Subject: [PATCH] gm45/gma.c: clean up some registers
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-According to "G45: Volume 3: Display Register
-Intel ® 965G Express Chipset Family and Intel ®
-G35 Express Chipset Graphics Controller" some registries
-are set incorrectly in gm45/gma.c.
-
-Some values are changed after comparing them with the values
-the i915 linux kernel (3.13 was used) module sets while modesetting.
-The values were obtained using 'intel_reg' from intel-gpu-tools,
-during a normal boot and with 'nomodeset' as a kernel argument.
-
-Some registers that don't exist on gm45 are set in gma.c, which is
-probably the result of copying code from a more recent intel
-northbridge.
-
-The result is that that gm45 laptops with wxga displays still work as
-before. Laptops with wxga+ displays previously did not display anything
-and now have a horizontal 20% strip of working display.
-
-TEST: build with native graphic init and flash on a gm45 target, like
-lenovo x200.
-
-Change-Id: If66b60c7189997c558270f9e474851fe7e2219f1
-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
----
- src/northbridge/intel/gm45/gma.c | 110 +++++++--------------------------------
- 1 file changed, 18 insertions(+), 92 deletions(-)
-
-diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c
-index a89f9bb..b02c89b 100644
---- a/src/northbridge/intel/gm45/gma.c
-+++ b/src/northbridge/intel/gm45/gma.c
-@@ -47,60 +47,6 @@ void gtt_write(u32 reg, u32 data)
- 	write32(res2mmio(gtt_res, reg, 0), data);
- }
- 
--static void power_port(u8 *mmio)
--{
--	read32(mmio + 0x00061100); // = 0x00000000
--	write32(mmio + 0x00061100, 0x00000000);
--	write32(mmio + 0x00061100, 0x00010000);
--	read32(mmio + 0x00061100); // = 0x00010000
--	read32(mmio + 0x00061100); // = 0x00010000
--	read32(mmio + 0x00061100); // = 0x00000000
--	write32(mmio + 0x00061100, 0x00000000);
--	read32(mmio + 0x00061100); // = 0x00000000
--	read32(mmio + 0x00064200); // = 0x0000001c
--	write32(mmio + 0x00064210, 0x8004003e);
--	write32(mmio + 0x00064214, 0x80060002);
--	write32(mmio + 0x00064218, 0x01000000);
--	read32(mmio + 0x00064210); // = 0x5144003e
--	write32(mmio + 0x00064210, 0x5344003e);
--	read32(mmio + 0x00064210); // = 0x0144003e
--	write32(mmio + 0x00064210, 0x8074003e);
--	read32(mmio + 0x00064210); // = 0x5144003e
--	read32(mmio + 0x00064210); // = 0x5144003e
--	write32(mmio + 0x00064210, 0x5344003e);
--	read32(mmio + 0x00064210); // = 0x0144003e
--	write32(mmio + 0x00064210, 0x8074003e);
--	read32(mmio + 0x00064210); // = 0x5144003e
--	read32(mmio + 0x00064210); // = 0x5144003e
--	write32(mmio + 0x00064210, 0x5344003e);
--	read32(mmio + 0x00064210); // = 0x0144003e
--	write32(mmio + 0x00064210, 0x8074003e);
--	read32(mmio + 0x00064210); // = 0x5144003e
--	read32(mmio + 0x00064210); // = 0x5144003e
--	write32(mmio + 0x00064210, 0x5344003e);
--	write32(mmio + 0x00064f00, 0x0100030c);
--	write32(mmio + 0x00064f04, 0x00b8230c);
--	write32(mmio + 0x00064f08, 0x06f8930c);
--	write32(mmio + 0x00064f0c, 0x09f8e38e);
--	write32(mmio + 0x00064f10, 0x00b8030c);
--	write32(mmio + 0x00064f14, 0x0b78830c);
--	write32(mmio + 0x00064f18, 0x0ff8d3cf);
--	write32(mmio + 0x00064f1c, 0x01e8030c);
--	write32(mmio + 0x00064f20, 0x0ff863cf);
--	write32(mmio + 0x00064f24, 0x0ff803cf);
--	write32(mmio + 0x000c4030, 0x00001000);
--	read32(mmio + 0x00044000); // = 0x00000000
--	write32(mmio + 0x00044030, 0x00001000);
--	read32(mmio + 0x00061150); // = 0x0000001c
--	write32(mmio + 0x00061150, 0x0000089c);
--	write32(mmio + 0x000fcc00, 0x01986f00);
--	write32(mmio + 0x000fcc0c, 0x01986f00);
--	write32(mmio + 0x000fcc18, 0x01986f00);
--	write32(mmio + 0x000fcc24, 0x01986f00);
--	read32(mmio + 0x00044000); // = 0x00000000
--	read32(mmio + LVDS); // = 0x40000002
--}
--
- static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- 			   u8 *mmio, u32 physbase, u16 piobase, u32 lfb)
- {
-@@ -150,8 +96,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- 	for (i = 0; i <= 0x18; i++)
- 		vga_cr_write(i, cr[i]);
- 
--	power_port(mmio);
--
- 	intel_gmbus_read_edid(mmio + GMBUS0, 3, 0x50, edid_data, 128);
- 	decode_edid(edid_data,
- 		    sizeof(edid_data), &edid);
-@@ -277,28 +221,32 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- 		(hpolarity << 20) | (vpolarity << 21)
- 		| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
--		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
-+		| LVDS_ENABLE_DITHER
-+		| LVDS_CLOCK_A_POWERUP_ALL
-+		| LVDS_PIPE(0));
- 	mdelay(1);
- 	write32(mmio + PP_CONTROL, PANEL_UNLOCK_REGS
- 		| (read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
- 	write32(mmio + FP0(0),
- 		((pixel_n - 2) << 16)
--		| ((pixel_m1 - 2) << 8) | pixel_m2);
-+		| ((pixel_m1 - 2) << 8) | (pixel_m2 - 2));
- 	write32(mmio + DPLL(0),
- 		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-+		| DPLL_VGA_MODE_DIS
- 		| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- 		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
- 		| (0x10000 << (pixel_p1 - 1))
- 		| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
--		| (0x1 << (pixel_p1 - 1)));
-+		| (6 << 9));
- 	mdelay(1);
- 	write32(mmio + DPLL(0),
- 		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-+		| DPLL_VGA_MODE_DIS
- 		| (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
- 		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
- 		| (0x10000 << (pixel_p1 - 1))
- 		| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
--		| (0x1 << (pixel_p1 - 1)));
-+		| (6 << 9));
- 	/* Re-lock the registers.  */
- 	write32(mmio + PP_CONTROL,
- 		(read32(mmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
-@@ -307,7 +255,9 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- 		(hpolarity << 20) | (vpolarity << 21)
- 		| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
--		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
-+		| LVDS_CLOCK_A_POWERUP_ALL
-+		| LVDS_ENABLE_DITHER
-+		| LVDS_PIPE(0));
- 
- 	write32(mmio + HTOTAL(0),
- 		((hactive + right_border + hblank - 1) << 16)
-@@ -324,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- 	write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16)
- 		| (vactive + bottom_border - 1));
- 	write32(mmio + VSYNC(0),
--		(vactive + bottom_border + vfront_porch + vsync - 1)
-+		((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
- 		| (vactive + bottom_border + vfront_porch - 1));
- 
- 	write32(mmio + PIPECONF(0), PIPECONF_DISABLE);
-@@ -335,7 +285,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- 			| (vactive - 1));
- 		write32(mmio + PF_CTL(0), 0);
- 		write32(mmio + PF_WIN_SZ(0), 0);
--		write32(mmio + PFIT_CONTROL, 0x20000000);
-+		write32(mmio + PFIT_CONTROL, 0);
- 	} else {
- 		write32(mmio + PIPESRC(0), (639 << 16) | 399);
- 		write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3);
-@@ -362,7 +312,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- 	write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
- 
- 	if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) {
--		write32(mmio + VGACNTRL, 0xc4008e | VGA_DISP_DISABLE);
-+		write32(mmio + VGACNTRL, VGA_DISP_DISABLE);
- 		write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE
- 			| DISPPLANE_BGRX888);
- 		mdelay(1);
-@@ -370,37 +320,13 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
- 		write32(mmio + VGACNTRL, 0xc4008e);
- 	}
- 
--	write32(mmio + TRANS_HTOTAL(0),
--		((hactive + right_border + hblank - 1) << 16)
--		| (hactive - 1));
--	write32(mmio + TRANS_HBLANK(0),
--		((hactive + right_border + hblank - 1) << 16)
--		| (hactive + right_border - 1));
--	write32(mmio + TRANS_HSYNC(0),
--		((hactive + right_border + hfront_porch + hsync - 1) << 16)
--		| (hactive + right_border + hfront_porch - 1));
--
--	write32(mmio + TRANS_VTOTAL(0),
--		((vactive + bottom_border + vblank - 1) << 16)
--		| (vactive - 1));
--	write32(mmio + TRANS_VBLANK(0),
--		((vactive + bottom_border + vblank - 1) << 16)
--		| (vactive + bottom_border - 1));
--	write32(mmio + TRANS_VSYNC(0),
--		(vactive + bottom_border + vfront_porch + vsync - 1)
--		| (vactive + bottom_border + vfront_porch - 1));
--
--	write32(mmio + 0x00060100, 0xb01c4000);
--	write32(mmio + 0x000f000c, 0xb01a2050);
--	mdelay(1);
--	write32(mmio + TRANSCONF(0), TRANS_ENABLE | TRANS_6BPC
--		);
--	write32(mmio + LVDS,
--		LVDS_PORT_ENABLE
-+	write32(mmio + LVDS, LVDS_PORT_ENABLE
- 		| (hpolarity << 20) | (vpolarity << 21)
- 		| (mode->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
- 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
--		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
-+		| LVDS_CLOCK_A_POWERUP_ALL
-+		| LVDS_ENABLE_DITHER
-+		| LVDS_PIPE(0));
- 
- 	write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET);
- 
--- 
-2.9.3
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch
deleted file mode 100644
index 01124c34..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/0001-set-default-vram-to-256M.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From c98d8745d4dca650709e76269cf014e5ffbc1443 Mon Sep 17 00:00:00 2001
-From: Arthur Heymans <arthur@aheymans.xyz>
-Date: Tue, 9 Aug 2016 00:54:37 +0200
-Subject: [PATCH] set default vram to 256M
-
-Change-Id: Ife906c47f32493d9a647a4f12f25982623eba189
----
- src/mainboard/lenovo/t400/cmos.default | 2 +-
- src/mainboard/lenovo/x200/cmos.default | 2 +-
- 2 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
-index 5cf3e63..90d796f 100644
---- a/src/mainboard/lenovo/t400/cmos.default
-+++ b/src/mainboard/lenovo/t400/cmos.default
-@@ -14,4 +14,4 @@ power_management_beeps=Enable
- low_battery_beep=Enable
- sata_mode=AHCI
- hybrid_graphics_mode=Integrated Only
--gfx_uma_size=32M
-\ No newline at end of file
-+gfx_uma_size=256M
-\ No newline at end of file
-diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
-index 1d7b420..ec7ab46 100644
---- a/src/mainboard/lenovo/x200/cmos.default
-+++ b/src/mainboard/lenovo/x200/cmos.default
-@@ -13,4 +13,4 @@ sticky_fn=Disable
- power_management_beeps=Enable
- low_battery_beep=Enable
- sata_mode=AHCI
--gfx_uma_size=32M
-\ No newline at end of file
-+gfx_uma_size=256M
-\ No newline at end of file
--- 
-2.9.2
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/INFO b/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/INFO
deleted file mode 100644
index 220b8583..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/d83b0e9ac4174cca92ac2c3b83a7e8491a9a1ff4/grub/x200_8mb/INFO
+++ /dev/null
@@ -1,5 +0,0 @@
-# NOTE: remove this when updating to the latest version of coreboot. this patch
-# makes the patch below redundant: https://review.coreboot.org/#/c/12814/
-printf "northbridge/gm45/raminit.c: enable GS45 high-perf (i.e. add X200S support to libreboot)\n"
-git am "../resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch"
-# git fetch http://review.coreboot.org/coreboot refs/changes/35/11135/3 && git cherry-pick FETCH_HEAD
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
deleted file mode 100644
index 2fde12f4..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 8 Mar 2016 07:21:33 +0000
-Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates
-
-There were build issues in libreboot. We don't use microcode updates anyway.
-When selecting no microcode updates in menuconfig, build failed because
-coreboot for these boards was still trying to add microcode.
----
- src/cpu/Makefile.inc                           | 34 +-------------------------
- src/cpu/amd/family_10h-family_15h/Kconfig      |  1 -
- src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 --------
- 3 files changed, 1 insertion(+), 44 deletions(-)
-
-diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
-index 046c418..ef0e236 100644
---- a/src/cpu/Makefile.inc
-+++ b/src/cpu/Makefile.inc
-@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
- ## Rules for building the microcode blob in CBFS
- ################################################################################
- 
--ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
--cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += cpu_microcode_blob.bin
--endif
--
--ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
--cbfs-files-y  += cpu_microcode_blob.bin
--cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
--
--$(objgenerated)/microcode.bin:
--	echo "   util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
--	util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
--endif
--
--# We just mash all microcode binaries together into one binary to rule them all.
--# This approach assumes that the microcode binaries are properly padded, and
--# their headers specify the correct size. This works fairly well on isolatied
--# updates, such as Intel and some AMD microcode, but won't work very well if the
--# updates are wrapped in a container, like AMD's microcode update container. If
--# there is only one microcode binary (i.e. one container), then we don't have
--# this issue, and this rule will continue to work.
--$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
--	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
--	@echo $(cpu_microcode_bins)
--	cat /dev/null $+ > $@
--
--cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
--cpu_microcode_blob.bin-type := microcode
--
--ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
--cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
--else
--cpu_microcode_blob.bin-align := 16
--endif
-+# What? Nope! We don't do that in libreboot.
-diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
-index 14ab1cd..3f873a1 100644
---- a/src/cpu/amd/family_10h-family_15h/Kconfig
-+++ b/src/cpu/amd/family_10h-family_15h/Kconfig
-@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX
- 	select UDELAY_LAPIC
- 	select HAVE_MONOTONIC_TIMER
- 	select SUPPORT_CPU_UCODE_IN_CBFS
--	select CPU_MICROCODE_MULTIPLE_FILES
- 
- if CPU_AMD_MODEL_10XXX
- 
-diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-index f10f732..a295475 100644
---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
-+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-@@ -9,13 +9,3 @@ romstage-y += ram_calc.c
- ramstage-y += ram_calc.c
- ramstage-y += monotonic_timer.c
- ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
--
--# Microcode for Family 10h, 11h, 12h, and 14h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
--microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
--microcode_amd.bin-type := microcode
--
--# Microcode for Family 15h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-type := microcode
--- 
-1.9.1
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
deleted file mode 100644
index 2fde12f4..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 8 Mar 2016 07:21:33 +0000
-Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates
-
-There were build issues in libreboot. We don't use microcode updates anyway.
-When selecting no microcode updates in menuconfig, build failed because
-coreboot for these boards was still trying to add microcode.
----
- src/cpu/Makefile.inc                           | 34 +-------------------------
- src/cpu/amd/family_10h-family_15h/Kconfig      |  1 -
- src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 --------
- 3 files changed, 1 insertion(+), 44 deletions(-)
-
-diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
-index 046c418..ef0e236 100644
---- a/src/cpu/Makefile.inc
-+++ b/src/cpu/Makefile.inc
-@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
- ## Rules for building the microcode blob in CBFS
- ################################################################################
- 
--ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
--cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += cpu_microcode_blob.bin
--endif
--
--ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
--cbfs-files-y  += cpu_microcode_blob.bin
--cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
--
--$(objgenerated)/microcode.bin:
--	echo "   util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
--	util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
--endif
--
--# We just mash all microcode binaries together into one binary to rule them all.
--# This approach assumes that the microcode binaries are properly padded, and
--# their headers specify the correct size. This works fairly well on isolatied
--# updates, such as Intel and some AMD microcode, but won't work very well if the
--# updates are wrapped in a container, like AMD's microcode update container. If
--# there is only one microcode binary (i.e. one container), then we don't have
--# this issue, and this rule will continue to work.
--$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
--	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
--	@echo $(cpu_microcode_bins)
--	cat /dev/null $+ > $@
--
--cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
--cpu_microcode_blob.bin-type := microcode
--
--ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
--cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
--else
--cpu_microcode_blob.bin-align := 16
--endif
-+# What? Nope! We don't do that in libreboot.
-diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
-index 14ab1cd..3f873a1 100644
---- a/src/cpu/amd/family_10h-family_15h/Kconfig
-+++ b/src/cpu/amd/family_10h-family_15h/Kconfig
-@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX
- 	select UDELAY_LAPIC
- 	select HAVE_MONOTONIC_TIMER
- 	select SUPPORT_CPU_UCODE_IN_CBFS
--	select CPU_MICROCODE_MULTIPLE_FILES
- 
- if CPU_AMD_MODEL_10XXX
- 
-diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-index f10f732..a295475 100644
---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
-+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-@@ -9,13 +9,3 @@ romstage-y += ram_calc.c
- ramstage-y += ram_calc.c
- ramstage-y += monotonic_timer.c
- ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
--
--# Microcode for Family 10h, 11h, 12h, and 14h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
--microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
--microcode_amd.bin-type := microcode
--
--# Microcode for Family 15h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-type := microcode
--- 
-1.9.1
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
deleted file mode 100644
index 2fde12f4..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 8 Mar 2016 07:21:33 +0000
-Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates
-
-There were build issues in libreboot. We don't use microcode updates anyway.
-When selecting no microcode updates in menuconfig, build failed because
-coreboot for these boards was still trying to add microcode.
----
- src/cpu/Makefile.inc                           | 34 +-------------------------
- src/cpu/amd/family_10h-family_15h/Kconfig      |  1 -
- src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 --------
- 3 files changed, 1 insertion(+), 44 deletions(-)
-
-diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
-index 046c418..ef0e236 100644
---- a/src/cpu/Makefile.inc
-+++ b/src/cpu/Makefile.inc
-@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
- ## Rules for building the microcode blob in CBFS
- ################################################################################
- 
--ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
--cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += cpu_microcode_blob.bin
--endif
--
--ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
--cbfs-files-y  += cpu_microcode_blob.bin
--cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
--
--$(objgenerated)/microcode.bin:
--	echo "   util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
--	util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
--endif
--
--# We just mash all microcode binaries together into one binary to rule them all.
--# This approach assumes that the microcode binaries are properly padded, and
--# their headers specify the correct size. This works fairly well on isolatied
--# updates, such as Intel and some AMD microcode, but won't work very well if the
--# updates are wrapped in a container, like AMD's microcode update container. If
--# there is only one microcode binary (i.e. one container), then we don't have
--# this issue, and this rule will continue to work.
--$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
--	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
--	@echo $(cpu_microcode_bins)
--	cat /dev/null $+ > $@
--
--cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
--cpu_microcode_blob.bin-type := microcode
--
--ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
--cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
--else
--cpu_microcode_blob.bin-align := 16
--endif
-+# What? Nope! We don't do that in libreboot.
-diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
-index 14ab1cd..3f873a1 100644
---- a/src/cpu/amd/family_10h-family_15h/Kconfig
-+++ b/src/cpu/amd/family_10h-family_15h/Kconfig
-@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX
- 	select UDELAY_LAPIC
- 	select HAVE_MONOTONIC_TIMER
- 	select SUPPORT_CPU_UCODE_IN_CBFS
--	select CPU_MICROCODE_MULTIPLE_FILES
- 
- if CPU_AMD_MODEL_10XXX
- 
-diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-index f10f732..a295475 100644
---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
-+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-@@ -9,13 +9,3 @@ romstage-y += ram_calc.c
- ramstage-y += ram_calc.c
- ramstage-y += monotonic_timer.c
- ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
--
--# Microcode for Family 10h, 11h, 12h, and 14h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
--microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
--microcode_amd.bin-type := microcode
--
--# Microcode for Family 15h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-type := microcode
--- 
-1.9.1
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
deleted file mode 100644
index 2fde12f4..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 8 Mar 2016 07:21:33 +0000
-Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates
-
-There were build issues in libreboot. We don't use microcode updates anyway.
-When selecting no microcode updates in menuconfig, build failed because
-coreboot for these boards was still trying to add microcode.
----
- src/cpu/Makefile.inc                           | 34 +-------------------------
- src/cpu/amd/family_10h-family_15h/Kconfig      |  1 -
- src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 --------
- 3 files changed, 1 insertion(+), 44 deletions(-)
-
-diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
-index 046c418..ef0e236 100644
---- a/src/cpu/Makefile.inc
-+++ b/src/cpu/Makefile.inc
-@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
- ## Rules for building the microcode blob in CBFS
- ################################################################################
- 
--ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
--cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += cpu_microcode_blob.bin
--endif
--
--ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
--cbfs-files-y  += cpu_microcode_blob.bin
--cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
--
--$(objgenerated)/microcode.bin:
--	echo "   util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
--	util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
--endif
--
--# We just mash all microcode binaries together into one binary to rule them all.
--# This approach assumes that the microcode binaries are properly padded, and
--# their headers specify the correct size. This works fairly well on isolatied
--# updates, such as Intel and some AMD microcode, but won't work very well if the
--# updates are wrapped in a container, like AMD's microcode update container. If
--# there is only one microcode binary (i.e. one container), then we don't have
--# this issue, and this rule will continue to work.
--$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
--	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
--	@echo $(cpu_microcode_bins)
--	cat /dev/null $+ > $@
--
--cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
--cpu_microcode_blob.bin-type := microcode
--
--ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
--cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
--else
--cpu_microcode_blob.bin-align := 16
--endif
-+# What? Nope! We don't do that in libreboot.
-diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
-index 14ab1cd..3f873a1 100644
---- a/src/cpu/amd/family_10h-family_15h/Kconfig
-+++ b/src/cpu/amd/family_10h-family_15h/Kconfig
-@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX
- 	select UDELAY_LAPIC
- 	select HAVE_MONOTONIC_TIMER
- 	select SUPPORT_CPU_UCODE_IN_CBFS
--	select CPU_MICROCODE_MULTIPLE_FILES
- 
- if CPU_AMD_MODEL_10XXX
- 
-diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-index f10f732..a295475 100644
---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
-+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-@@ -9,13 +9,3 @@ romstage-y += ram_calc.c
- ramstage-y += ram_calc.c
- ramstage-y += monotonic_timer.c
- ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
--
--# Microcode for Family 10h, 11h, 12h, and 14h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
--microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
--microcode_amd.bin-type := microcode
--
--# Microcode for Family 15h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-type := microcode
--- 
-1.9.1
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
deleted file mode 100644
index 2fde12f4..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
+++ /dev/null
@@ -1,89 +0,0 @@
-From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 8 Mar 2016 07:21:33 +0000
-Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates
-
-There were build issues in libreboot. We don't use microcode updates anyway.
-When selecting no microcode updates in menuconfig, build failed because
-coreboot for these boards was still trying to add microcode.
----
- src/cpu/Makefile.inc                           | 34 +-------------------------
- src/cpu/amd/family_10h-family_15h/Kconfig      |  1 -
- src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 --------
- 3 files changed, 1 insertion(+), 44 deletions(-)
-
-diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
-index 046c418..ef0e236 100644
---- a/src/cpu/Makefile.inc
-+++ b/src/cpu/Makefile.inc
-@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
- ## Rules for building the microcode blob in CBFS
- ################################################################################
- 
--ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
--cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += cpu_microcode_blob.bin
--endif
--
--ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
--cbfs-files-y  += cpu_microcode_blob.bin
--cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
--
--$(objgenerated)/microcode.bin:
--	echo "   util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
--	util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
--endif
--
--# We just mash all microcode binaries together into one binary to rule them all.
--# This approach assumes that the microcode binaries are properly padded, and
--# their headers specify the correct size. This works fairly well on isolatied
--# updates, such as Intel and some AMD microcode, but won't work very well if the
--# updates are wrapped in a container, like AMD's microcode update container. If
--# there is only one microcode binary (i.e. one container), then we don't have
--# this issue, and this rule will continue to work.
--$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
--	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
--	@echo $(cpu_microcode_bins)
--	cat /dev/null $+ > $@
--
--cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
--cpu_microcode_blob.bin-type := microcode
--
--ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
--cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
--else
--cpu_microcode_blob.bin-align := 16
--endif
-+# What? Nope! We don't do that in libreboot.
-diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
-index 14ab1cd..3f873a1 100644
---- a/src/cpu/amd/family_10h-family_15h/Kconfig
-+++ b/src/cpu/amd/family_10h-family_15h/Kconfig
-@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX
- 	select UDELAY_LAPIC
- 	select HAVE_MONOTONIC_TIMER
- 	select SUPPORT_CPU_UCODE_IN_CBFS
--	select CPU_MICROCODE_MULTIPLE_FILES
- 
- if CPU_AMD_MODEL_10XXX
- 
-diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-index f10f732..a295475 100644
---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
-+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-@@ -9,13 +9,3 @@ romstage-y += ram_calc.c
- ramstage-y += ram_calc.c
- ramstage-y += monotonic_timer.c
- ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
--
--# Microcode for Family 10h, 11h, 12h, and 14h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
--microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
--microcode_amd.bin-type := microcode
--
--# Microcode for Family 15h
--cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-type := microcode
--- 
-1.9.1
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/crossgcc/buildgcc_hash_patch.diff b/i18n/fr_FR/resources/libreboot/patch/crossgcc/buildgcc_hash_patch.diff
deleted file mode 100644
index 9750795a..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/crossgcc/buildgcc_hash_patch.diff
+++ /dev/null
@@ -1,163 +0,0 @@
-diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 97c38b8d95..d6b11ed0a6 100755
---- a/util/crossgcc/buildgcc
-+++ b/util/crossgcc/buildgcc
-@@ -270,18 +270,6 @@ check_cc() {
- 	fi
- }
- 
--check_sum() {
--	test -z "$CHECKSUM" || \
--	test "$(cat sum/$1.cksum 2>/dev/null | sed -e 's@.*\([0-9a-f]\{40,\}\).*@\1@')" = \
--	"$($CHECKSUM tarballs/$1 2>/dev/null | sed -e 's@.*\([0-9a-f]\{40,\}\).*@\1@')"
--}
--
--compute_sum() {
--	test ! -f sum/$1.cksum && test -f tarballs/$1 && \
--	(test -z "$CHECKSUM" || $CHECKSUM tarballs/$1 > sum/$1.cksum ) && \
--	printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}"
--}
--
- download_showing_percentage() {
- 	url=$1
- 	printf " ..${red}  0%%"
-@@ -293,12 +281,13 @@ download_showing_percentage() {
- 
- download() {
- 	package=$1
--	archive="$(eval echo \$$package"_ARCHIVE")"
-+	archive="$package"_ARCHIVE
-+	archive="${!archive}"
- 
- 	FILE=$(basename $archive)
- 	printf " * $FILE "
- 
--	if test -f tarballs/$FILE && check_sum $FILE ; then
-+	if test -f tarballs/$FILE; then
- 		printf "(cached)"
- 	else
- 		printf "(downloading from $archive)"
-@@ -306,7 +295,6 @@ download() {
- 		cd tarballs
- 		download_showing_percentage $archive
- 		cd ..
--		compute_sum $FILE
- 	fi
- 
- 	if [ ! -f tarballs/$FILE ]; then
-@@ -316,9 +304,100 @@ download() {
- 	printf "\n"
- }
- 
-+# Compute the hash of the package given in $1, and print it raw (just the
-+# hexadecimal hash).
-+compute_hash() {
-+	package=$1
-+	archive="$package"_ARCHIVE
-+	archive="${!archive}"
-+	file="$(basename "$archive")"
-+
-+	if test -z "$CHECKSUM"; then
-+		echo "${RED}\$CHECKSUM program missing. This is bad.${NC}" 1>&2
-+		exit 1
-+	fi
-+
-+	$CHECKSUM "tarballs/$file" 2>/dev/null | sed -e 's@.*\([0-9a-f]\{40,\}\).*@\1@'
-+}
-+
-+error_hash_missing() {
-+	package="$1"
-+	archive="$package"_ARCHIVE
-+	archive="${!archive}"
-+	file="$(basename "$archive")"
-+
-+	fullhashfile="util/crossgcc/sum/$file.cksum"
-+	printf "${RED}hash file missing:${NC}\n\n" 1>&2
-+	printf "Please verify util/crossgcc/tarball/$file carefully\n" 1>&2
-+	printf "(using PGP if possible), and then rename\n" 1>&2
-+	printf "        ${CYAN}${fullhashfile}.calc${NC}\n" 1>&2
-+	printf "     to ${CYAN}${fullhashfile}${NC}\n\n" 1>&2
-+
-+	exit 1
-+}
-+
-+# Read the known hash file of the package given in $1, and print it raw.
-+get_known_hash() {
-+	package=$1
-+	archive="$package"_ARCHIVE
-+	archive="${!archive}"
-+	file="$(basename "$archive")"
-+	hashfile="sum/$file.cksum"
-+
-+	if [ ! -f "$hashfile" ]; then
-+		calc_hash="$(compute_hash "$package")" || exit 1
-+		echo "$calc_hash  tarballs/$file" > "${hashfile}.calc"
-+
-+		error_hash_missing "$package"
-+		exit 1
-+	fi
-+
-+	cat "$hashfile" | sed -e 's@.*\([0-9a-f]\{40,\}\).*@\1@'
-+}
-+
-+error_hash_mismatch() {
-+	package=$1
-+	known_hash="$2"
-+	computed_hash="$3"
-+	archive="$package"_ARCHIVE
-+	archive="${!archive}"
-+	file="$(basename "$archive")"
-+
-+	printf "${RED}hash mismatch:${NC}\n\n"
-+	printf "             expected (known) hash: $known_hash\n"
-+	printf "calculated hash of downloaded file: $computed_hash\n\n"
-+
-+	printf "If you think this is due to a network error, please delete\n"
-+	printf "  ${CYAN}util/crossgcc/tarballs/$file${NC}\n"
-+	printf "and try again. If the problem persists, it may be due to an\n"
-+	printf "administration error on the file server, or you might be\n"
-+	printf "subject to a Man-in-the-Middle attack\n\n"
-+
-+	exit 1
-+}
-+
-+# verify_hash - Check that the hash of the file given in $1 matches the known
-+# hash; Bail out on mismatch or missing hash file.
-+verify_hash() {
-+	package=$1
-+	archive="$package"_ARCHIVE
-+	archive="${!archive}"
-+
-+	known_hash="$(get_known_hash "$package")" || exit "$?"
-+	computed_hash="$(compute_hash "$package")" || exit "$?"
-+
-+	if [ "$known_hash" != "$computed_hash" ]; then
-+		error_hash_mismatch "$package" "$known_hash" "$computed_hash"
-+		exit 1
-+	fi
-+
-+	printf "${GREEN}hash verified ("$known_hash")${NC}\n"
-+}
-+
- unpack_and_patch() {
- 	package=$1
--	archive="$(eval echo \$$package"_ARCHIVE")"
-+	archive="$package"_ARCHIVE
-+	archive="${!archive}"
- 	dir="$(eval echo \$$package"_DIR")"
- 	test -d ${dir} && test -f ${dir}/.unpack_success || (
- 		printf " * $(basename $archive)\n"
-@@ -963,10 +1042,11 @@ export PATH=$DESTDIR$TARGETDIR/bin:$PATH
- 
- # Download, unpack, patch and build all packages
- 
--printf "Downloading tarballs ... \n"
-+printf "Downloading and verifying tarballs... \n"
- mkdir -p tarballs
- for P in $PACKAGES; do
--	download $P
-+	  download "$P" || exit "$?"
-+    verify_hash "$P" || exit "$P"
- done
- printf "Downloaded tarballs ... ${green}ok${NC}\n"
- 
diff --git a/i18n/fr_FR/resources/libreboot/patch/crossgcc/libelf.patch b/i18n/fr_FR/resources/libreboot/patch/crossgcc/libelf.patch
deleted file mode 100644
index af954446..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/crossgcc/libelf.patch
+++ /dev/null
@@ -1,25 +0,0 @@
-From e2896721cff5af4d869a7c900e748c803f25a2ce Mon Sep 17 00:00:00 2001
-From: Andrew Robbins <contact@andrewrobbins.info>
-Date: Thu, 26 Sep 2019 18:19:07 -0500
-Subject: [PATCH] buildgcc: Replace dead libelf archive URI
-
----
- util/crossgcc/buildgcc | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 97c38b8d95..54f87972e6 100755
---- a/util/crossgcc/buildgcc
-+++ b/util/crossgcc/buildgcc
-@@ -57,7 +57,7 @@ MAKE_VERSION=4.2.1
- GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.xz"
- MPFR_ARCHIVE="http://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz"
- MPC_ARCHIVE="http://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
--LIBELF_ARCHIVE="http://www.mr511.de/software/libelf-${LIBELF_VERSION}.tar.gz"
-+LIBELF_ARCHIVE="https://fossies.org/linux/misc/old/libelf-${LIBELF_VERSION}.tar.gz"
- GCC_ARCHIVE="http://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.bz2"
- BINUTILS_ARCHIVE="http://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.bz2"
- GDB_ARCHIVE="http://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz"
--- 
-2.23.0
-
diff --git a/i18n/fr_FR/resources/libreboot/patch/crossgcc/looking_for_pie.patch b/i18n/fr_FR/resources/libreboot/patch/crossgcc/looking_for_pie.patch
deleted file mode 100644
index 942edac2..00000000
--- a/i18n/fr_FR/resources/libreboot/patch/crossgcc/looking_for_pie.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From e64fb0ce10d01d99154fb4bd95529e5cd8dfd4be Mon Sep 17 00:00:00 2001
-From: Andrew Robbins <contact@andrewrobbins.info>
-Date: Fri, 27 Sep 2019 09:38:09 -0500
-Subject: [PATCH] buildgcc: Check for '-pie' when building gmp
-
-The regex formerly used was not flexible enough to catch some
-instances where the '-pie' flag would be enabled.
----
- util/crossgcc/buildgcc | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 97c38b8d95..a6e4728514 100755
---- a/util/crossgcc/buildgcc
-+++ b/util/crossgcc/buildgcc
-@@ -515,6 +515,13 @@ set_hostcflags_from_gmp() {
- }
- 
- build_GMP() {
-+	# Check if GCC enables `-pie` by default (possible since GCC 6).
-+	# We need PIC in all static libraries then.
-+	if $CC -dumpspecs 2>/dev/null | grep -q '[{;][[:space:]]*\(!no-pie\)\?:-pie\>'
-+	then
-+		OPTIONS="$OPTIONS --with-pic"
-+	fi
-+
- 	CC="$CC" ../${GMP_DIR}/configure --disable-shared --enable-fat \
- 		--prefix=$TARGETDIR $OPTIONS \
- 		|| touch .failed
--- 
-2.23.0
-
author	Libreboot Contributor <contributor@libreboot.org>	2020-04-02 20:59:23 +0200
committer	Libreboot Contributor <contributor@libreboot.org>	2020-04-02 20:59:43 +0200
commit	a2f4bef6de0e1f5770d489e861c78890f81229c1 (patch)
tree	bc74ce87d44cfcae1eecff62c0fbf6a97b1812fc /i18n/fr_FR/resources/libreboot/patch
parent	c6cb6cf4769cd535eee9abfd41fbf717a51d067c (diff)
download	librebootfr-a2f4bef6de0e1f5770d489e861c78890f81229c1.tar.gz librebootfr-a2f4bef6de0e1f5770d489e861c78890f81229c1.zip