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| author | Andrew Robbins <contact@andrewrobbins.info> | 2018-10-30 00:56:15 -0400 |
|---|---|---|
| committer | Andrew Robbins <contact@andrewrobbins.info> | 2018-10-30 01:00:25 -0400 |
| commit | db19cee793a882dc1ee6a7be8dc787bf7be93049 (patch) | |
| tree | 8c6e39c06188f69e8f2a997502b2648a96ba2946 /projects/coreboot/configs/veyron | |
| parent | 8be0442ffe018f27c554a0afed627d4b0951e3fa (diff) | |
| download | librebootfr-db19cee793a882dc1ee6a7be8dc787bf7be93049.tar.gz librebootfr-db19cee793a882dc1ee6a7be8dc787bf7be93049.zip | |
Correct CBFS_SIZE in Veyron Speedy Coreboot Config
Diffstat (limited to 'projects/coreboot/configs/veyron')
| -rw-r--r-- | projects/coreboot/configs/veyron/speedy/config | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/projects/coreboot/configs/veyron/speedy/config b/projects/coreboot/configs/veyron/speedy/config index b4a74b9a..27ddca6b 100644 --- a/projects/coreboot/configs/veyron/speedy/config +++ b/projects/coreboot/configs/veyron/speedy/config @@ -110,7 +110,7 @@ CONFIG_MAINBOARD_PART_NUMBER="Veyron_Speedy" CONFIG_MAINBOARD_VENDOR="Google" CONFIG_MAX_CPUS=1 CONFIG_CACHE_ROM_SIZE_OVERRIDE=0x0 -CONFIG_CBFS_SIZE=0x100000 +CONFIG_CBFS_SIZE=0x400000 CONFIG_UART_FOR_CONSOLE=0 CONFIG_DIMM_SPD_SIZE=256 CONFIG_DEVICETREE="devicetree.cb" |