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| author | Andrew Robbins <contact@andrewrobbins.info> | 2018-10-29 23:43:34 -0400 |
|---|---|---|
| committer | Andrew Robbins <contact@andrewrobbins.info> | 2018-10-30 01:00:25 -0400 |
| commit | b87eeca4559e7cd94af1ad4273d082b4f3ecba8b (patch) | |
| tree | e94a18e6c22c0a6b24b9d80f58519e53b8d3061b /projects/cros-ec/patches/veyron/0006-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch | |
| parent | d2aeff186dc6d672acfeb947dc1d35f203755548 (diff) | |
| download | librebootfr-b87eeca4559e7cd94af1ad4273d082b4f3ecba8b.tar.gz librebootfr-b87eeca4559e7cd94af1ad4273d082b4f3ecba8b.zip | |
Create 4,16MiB Coreboot configs/targets for Veyron Jerry
4MiB flash is the default for this board. A 16MiB config is
included for those looking to modify their board with a larger flash
chip.
Also, corebootfb is the only display mode available for this board;
as such, inclusion of the corebootfb subtarget serves only to
explicitly indicate the display mode when packaging ROMs upon
release.
Veyron Jerry Coreboot ROMs can be built with, e.g.:
'./libreboot build coreboot veyron jerry corebootfb 4mb'
Diffstat (limited to 'projects/cros-ec/patches/veyron/0006-cortex-m0-Use-assembly-exception-handlers-for-task-s.patch')
0 files changed, 0 insertions, 0 deletions