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| author | Andrew Robbins <contact@andrewrobbins.info> | 2019-01-12 19:30:37 -0500 |
|---|---|---|
| committer | Andrew Robbins <contact@andrewrobbins.info> | 2019-01-12 19:30:37 -0500 |
| commit | f8cf9dd9488fc3f4ac1993459d05ef99a4e5ba0f (patch) | |
| tree | 996709748d5e34e7fdd09939ee3537e7b91f3135 /projects/cros-ec/patches/veyron | |
| parent | 86ba2c05413b7ea31c475ec7dccc7ec851cf0e8d (diff) | |
| download | librebootfr-f8cf9dd9488fc3f4ac1993459d05ef99a4e5ba0f.tar.gz librebootfr-f8cf9dd9488fc3f4ac1993459d05ef99a4e5ba0f.zip | |
Create 1MiB coreboot config/target for D945GCLF
Previously it was thought that only boards with 512KiB flash chips
were produced but JohnMH (in #libreboot) ran across one with an
SST25LF080A 1MiB flash.
D945GCLF Coreboot ROMs can be built with, e.g.:
'./libreboot build coreboot d945gclf textmode 1mb'
Diffstat (limited to 'projects/cros-ec/patches/veyron')
0 files changed, 0 insertions, 0 deletions