Update coreboot (kgpe-d16,kcma-d8,kfsn4-dre,d510mo,ga-g41m-es2l)

Update to the latest coreboot and vboot versions at the time of writing:
coreboot 2a3434757ef425dbdfedf1fc69e1a033a6e7310d
vboot d187cd3fc792f8bcefbee4587c83eafbd08441fc

3 files changed, 163 insertions, 0 deletions

diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0001-nb-amd-mct_ddr3-Restore-previous-DQS-delay-values-on.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0001-nb-amd-mct_ddr3-Restore-previous-DQS-delay-values-on.patch
new file mode 100644
index 00000000..905d73dd
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0001-nb-amd-mct_ddr3-Restore-previous-DQS-delay-values-on.patch
@@ -0,0 +1,39 @@
+From 9761ddff5c8e47d7b5321a8c98383970b4fb8683 Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Mon, 7 Mar 2016 09:10:31 -0600
+Subject: [PATCH 1/2] nb/amd/mct_ddr3: Restore previous DQS delay values on
+ failed loop
+
+Change-Id: Iacfcd7f379d09a633973b4c3ef3cbb97e6d1f09f
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+index 19a7acb..1a3c7c1 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+@@ -1522,6 +1522,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
+ 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 143 largest read passing region start ", best_pos, 4);
+ 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 144 largest read passing region center (raw hardware value) ", region_center, 4);
+ 			} else {
++				 /* Restore current settings of other (previously trained) lanes to the active array */
++				memcpy(current_read_dqs_delay, initial_read_dqs_delay, sizeof(current_read_dqs_delay));
++
+ 				/* Reprogram the Read DQS Timing Control register with the original settings */
+ 				write_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg);
+ 			}
+@@ -1571,6 +1574,9 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
+ 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 145 largest write passing region ", best_count, 4);
+ 				print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 146 largest write passing region start ", best_pos, 4);
+ 			} else {
++				/* Restore current settings of other (previously trained) lanes to the active array */
++				memcpy(current_write_dqs_delay, initial_write_data_timing, sizeof(current_write_data_delay));
++
+ 				/* Reprogram the Write DQS Timing Control register with the original settings */
+ 				write_dqs_write_data_timing_registers(current_write_dqs_delay, dev, dct, dimm, index_reg);
+ 			}
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch
new file mode 100644
index 00000000..f866dda8
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0002-nb-amd-mct_ddr3-Train-correct-receiver-in-TrainDQSRd.patch
@@ -0,0 +1,35 @@
+From 3119f40c2e0abc36630a92fc5cee58b8d0f9087c Mon Sep 17 00:00:00 2001
+From: Timothy Pearson <tpearson@raptorengineeringinc.com>
+Date: Mon, 7 Mar 2016 13:29:24 -0600
+Subject: [PATCH 2/2] nb/amd/mct_ddr3: Train correct receiver in
+ TrainDQSRdWrPos_D_Fam15
+
+Change-Id: Ia26950a8297f0a7125c21e995c89a3fc68d9d8a9
+Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
+---
+ src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 5 +----
+ 1 file changed, 1 insertion(+), 4 deletions(-)
+
+diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+index 1a3c7c1..ad81c3d 100644
+--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
++++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+@@ -1340,14 +1340,11 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
+ 
+ 	Errors = 0;
+ 	dual_rank = 0;
+-	Receiver = mct_InitReceiver_D(pDCTstat, dct);
+-	if (receiver_start > Receiver)
+-		Receiver = receiver_start;
+ 
+ 	/* There are four receiver pairs, loosely associated with chipselects.
+ 	 * This is essentially looping over each rank within each DIMM.
+ 	 */
+-	for (; Receiver < receiver_end; Receiver++) {
++	for (Receiver = receiver_start; Receiver < receiver_end; Receiver++) {
+ 		dimm = (Receiver >> 1);
+ 		if ((Receiver & 0x1) == 0) {
+ 			/* Even rank of DIMM */
+-- 
+1.9.1
+
diff --git a/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0003-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0003-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
new file mode 100644
index 00000000..64278632
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/2a3434757ef425dbdfedf1fc69e1a033a6e7310d/grub/kfsn4-dre/0003-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch
@@ -0,0 +1,89 @@
+From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001
+From: Francis Rowe <info@gluglug.org.uk>
+Date: Tue, 8 Mar 2016 07:21:33 +0000
+Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates
+
+There were build issues in libreboot. We don't use microcode updates anyway.
+When selecting no microcode updates in menuconfig, build failed because
+coreboot for these boards was still trying to add microcode.
+---
+ src/cpu/Makefile.inc                           | 34 +-------------------------
+ src/cpu/amd/family_10h-family_15h/Kconfig      |  1 -
+ src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 --------
+ 3 files changed, 1 insertion(+), 44 deletions(-)
+
+diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
+index 046c418..ef0e236 100644
+--- a/src/cpu/Makefile.inc
++++ b/src/cpu/Makefile.inc
+@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
+ ## Rules for building the microcode blob in CBFS
+ ################################################################################
+ 
+-ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
+-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE)  += cpu_microcode_blob.bin
+-endif
+-
+-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
+-cbfs-files-y  += cpu_microcode_blob.bin
+-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
+-
+-$(objgenerated)/microcode.bin:
+-	echo "   util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
+-	util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
+-endif
+-
+-# We just mash all microcode binaries together into one binary to rule them all.
+-# This approach assumes that the microcode binaries are properly padded, and
+-# their headers specify the correct size. This works fairly well on isolatied
+-# updates, such as Intel and some AMD microcode, but won't work very well if the
+-# updates are wrapped in a container, like AMD's microcode update container. If
+-# there is only one microcode binary (i.e. one container), then we don't have
+-# this issue, and this rule will continue to work.
+-$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins)
+-	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
+-	@echo $(cpu_microcode_bins)
+-	cat /dev/null $+ > $@
+-
+-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
+-cpu_microcode_blob.bin-type := microcode
+-
+-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
+-cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
+-else
+-cpu_microcode_blob.bin-align := 16
+-endif
++# What? Nope! We don't do that in libreboot.
+diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
+index 14ab1cd..3f873a1 100644
+--- a/src/cpu/amd/family_10h-family_15h/Kconfig
++++ b/src/cpu/amd/family_10h-family_15h/Kconfig
+@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX
+ 	select UDELAY_LAPIC
+ 	select HAVE_MONOTONIC_TIMER
+ 	select SUPPORT_CPU_UCODE_IN_CBFS
+-	select CPU_MICROCODE_MULTIPLE_FILES
+ 
+ if CPU_AMD_MODEL_10XXX
+ 
+diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
+index f10f732..a295475 100644
+--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
++++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
+@@ -9,13 +9,3 @@ romstage-y += ram_calc.c
+ ramstage-y += ram_calc.c
+ ramstage-y += monotonic_timer.c
+ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
+-
+-# Microcode for Family 10h, 11h, 12h, and 14h
+-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin
+-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
+-microcode_amd.bin-type := microcode
+-
+-# Microcode for Family 15h
+-cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin
+-microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
+-microcode_amd_fam15h.bin-type := microcode
+-- 
+1.9.1
+