diff options
| author | Paul Kocialkowski <contact@paulk.fr> | 2016-12-23 14:13:48 +0100 |
|---|---|---|
| committer | Leah Rowe <info@minifree.org> | 2017-01-15 14:24:40 +0000 |
| commit | 3d08effb91acf985bae9c4eb4386937ce7ed92a9 (patch) | |
| tree | 9d890b07e4abf2f885cf9c494a9103bf4b96d891 /resources/libreboot/patch/coreboot | |
| parent | 0698cb38d1e26495c953f01daf9604551b6ed7d5 (diff) | |
| download | librebootfr-3d08effb91acf985bae9c4eb4386937ce7ed92a9.tar.gz librebootfr-3d08effb91acf985bae9c4eb4386937ce7ed92a9.zip | |
Current build system removal
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Diffstat (limited to 'resources/libreboot/patch/coreboot')
60 files changed, 0 insertions, 3873 deletions
diff --git a/resources/libreboot/patch/coreboot/112ab9183754a81c8100fcc37593ef4905a9d3a3/grub/imac52/0001-apple-imac52-add-mainboard.patch b/resources/libreboot/patch/coreboot/112ab9183754a81c8100fcc37593ef4905a9d3a3/grub/imac52/0001-apple-imac52-add-mainboard.patch deleted file mode 100644 index d3c782dd..00000000 --- a/resources/libreboot/patch/coreboot/112ab9183754a81c8100fcc37593ef4905a9d3a3/grub/imac52/0001-apple-imac52-add-mainboard.patch +++ /dev/null @@ -1,67 +0,0 @@ -From a81b83c6e43ff36bb71be7ac88ef2c5a95cf98bc Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sun, 18 Sep 2016 20:15:45 +0200 -Subject: [PATCH] apple/imac52: add mainboard - -The macbook21 rom works on iMac5,2 desktop computer. - -Change-Id: I34c8313c32920b02a2b964d8718e5b2b6b5a6820 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/mainboard/apple/imac52/Kconfig | 7 +++++++ - src/mainboard/apple/imac52/Kconfig.name | 2 ++ - src/mainboard/apple/imac52/board_info.txt | 8 ++++++++ - src/mainboard/apple/macbook21/Kconfig | 2 +- - 4 files changed, 18 insertions(+), 1 deletion(-) - create mode 100644 src/mainboard/apple/imac52/Kconfig - create mode 100644 src/mainboard/apple/imac52/Kconfig.name - create mode 100644 src/mainboard/apple/imac52/board_info.txt - -diff --git a/src/mainboard/apple/imac52/Kconfig b/src/mainboard/apple/imac52/Kconfig -new file mode 100644 -index 0000000..ba2ff95 ---- /dev/null -+++ b/src/mainboard/apple/imac52/Kconfig -@@ -0,0 +1,7 @@ -+if BOARD_APPLE_IMAC52 -+ -+config MAINBOARD_PART_NUMBER -+ string -+ default "iMac5,2" -+ -+endif -diff --git a/src/mainboard/apple/imac52/Kconfig.name b/src/mainboard/apple/imac52/Kconfig.name -new file mode 100644 -index 0000000..034222b ---- /dev/null -+++ b/src/mainboard/apple/imac52/Kconfig.name -@@ -0,0 +1,2 @@ -+config BOARD_APPLE_IMAC52 -+ bool "iMac5,2" -diff --git a/src/mainboard/apple/imac52/board_info.txt b/src/mainboard/apple/imac52/board_info.txt -new file mode 100644 -index 0000000..918d394 ---- /dev/null -+++ b/src/mainboard/apple/imac52/board_info.txt -@@ -0,0 +1,8 @@ -+Board name: iMac5,2 -+Category: desktop -+ROM package: SOIC-8 -+ROM protocol: SPI -+ROM socketed: n -+Flashrom support: n -+Clone of: apple/macbook21 -+Release year: 2007 -diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig -index e653c08..ebf3954 100644 ---- a/src/mainboard/apple/macbook21/Kconfig -+++ b/src/mainboard/apple/macbook21/Kconfig -@@ -1,4 +1,4 @@ --if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 -+if BOARD_APPLE_MACBOOK11 || BOARD_APPLE_MACBOOK21 || BOARD_APPLE_IMAC52 - - config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch deleted file mode 100644 index 2fde12f4..00000000 --- a/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Tue, 8 Mar 2016 07:21:33 +0000 -Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates - -There were build issues in libreboot. We don't use microcode updates anyway. -When selecting no microcode updates in menuconfig, build failed because -coreboot for these boards was still trying to add microcode. ---- - src/cpu/Makefile.inc | 34 +------------------------- - src/cpu/amd/family_10h-family_15h/Kconfig | 1 - - src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- - 3 files changed, 1 insertion(+), 44 deletions(-) - -diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc -index 046c418..ef0e236 100644 ---- a/src/cpu/Makefile.inc -+++ b/src/cpu/Makefile.inc -@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) - ## Rules for building the microcode blob in CBFS - ################################################################################ - --ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) --cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin --endif -- --ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) --cbfs-files-y += cpu_microcode_blob.bin --cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin -- --$(objgenerated)/microcode.bin: -- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" -- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) --endif -- --# We just mash all microcode binaries together into one binary to rule them all. --# This approach assumes that the microcode binaries are properly padded, and --# their headers specify the correct size. This works fairly well on isolatied --# updates, such as Intel and some AMD microcode, but won't work very well if the --# updates are wrapped in a container, like AMD's microcode update container. If --# there is only one microcode binary (i.e. one container), then we don't have --# this issue, and this rule will continue to work. --$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) -- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" -- @echo $(cpu_microcode_bins) -- cat /dev/null $+ > $@ -- --cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin --cpu_microcode_blob.bin-type := microcode -- --ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) --cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) --else --cpu_microcode_blob.bin-align := 16 --endif -+# What? Nope! We don't do that in libreboot. -diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig -index 14ab1cd..3f873a1 100644 ---- a/src/cpu/amd/family_10h-family_15h/Kconfig -+++ b/src/cpu/amd/family_10h-family_15h/Kconfig -@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX - select UDELAY_LAPIC - select HAVE_MONOTONIC_TIMER - select SUPPORT_CPU_UCODE_IN_CBFS -- select CPU_MICROCODE_MULTIPLE_FILES - - if CPU_AMD_MODEL_10XXX - -diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc -index f10f732..a295475 100644 ---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc -+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc -@@ -9,13 +9,3 @@ romstage-y += ram_calc.c - ramstage-y += ram_calc.c - ramstage-y += monotonic_timer.c - ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c -- --# Microcode for Family 10h, 11h, 12h, and 14h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin --microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin --microcode_amd.bin-type := microcode -- --# Microcode for Family 15h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-type := microcode --- -1.9.1 - diff --git a/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch deleted file mode 100644 index 2fde12f4..00000000 --- a/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Tue, 8 Mar 2016 07:21:33 +0000 -Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates - -There were build issues in libreboot. We don't use microcode updates anyway. -When selecting no microcode updates in menuconfig, build failed because -coreboot for these boards was still trying to add microcode. ---- - src/cpu/Makefile.inc | 34 +------------------------- - src/cpu/amd/family_10h-family_15h/Kconfig | 1 - - src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- - 3 files changed, 1 insertion(+), 44 deletions(-) - -diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc -index 046c418..ef0e236 100644 ---- a/src/cpu/Makefile.inc -+++ b/src/cpu/Makefile.inc -@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) - ## Rules for building the microcode blob in CBFS - ################################################################################ - --ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) --cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin --endif -- --ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) --cbfs-files-y += cpu_microcode_blob.bin --cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin -- --$(objgenerated)/microcode.bin: -- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" -- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) --endif -- --# We just mash all microcode binaries together into one binary to rule them all. --# This approach assumes that the microcode binaries are properly padded, and --# their headers specify the correct size. This works fairly well on isolatied --# updates, such as Intel and some AMD microcode, but won't work very well if the --# updates are wrapped in a container, like AMD's microcode update container. If --# there is only one microcode binary (i.e. one container), then we don't have --# this issue, and this rule will continue to work. --$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) -- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" -- @echo $(cpu_microcode_bins) -- cat /dev/null $+ > $@ -- --cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin --cpu_microcode_blob.bin-type := microcode -- --ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) --cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) --else --cpu_microcode_blob.bin-align := 16 --endif -+# What? Nope! We don't do that in libreboot. -diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig -index 14ab1cd..3f873a1 100644 ---- a/src/cpu/amd/family_10h-family_15h/Kconfig -+++ b/src/cpu/amd/family_10h-family_15h/Kconfig -@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX - select UDELAY_LAPIC - select HAVE_MONOTONIC_TIMER - select SUPPORT_CPU_UCODE_IN_CBFS -- select CPU_MICROCODE_MULTIPLE_FILES - - if CPU_AMD_MODEL_10XXX - -diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc -index f10f732..a295475 100644 ---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc -+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc -@@ -9,13 +9,3 @@ romstage-y += ram_calc.c - ramstage-y += ram_calc.c - ramstage-y += monotonic_timer.c - ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c -- --# Microcode for Family 10h, 11h, 12h, and 14h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin --microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin --microcode_amd.bin-type := microcode -- --# Microcode for Family 15h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-type := microcode --- -1.9.1 - diff --git a/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch deleted file mode 100644 index 2fde12f4..00000000 --- a/resources/libreboot/patch/coreboot/15fca66bf08db45937ce88b950491963654805b9/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Tue, 8 Mar 2016 07:21:33 +0000 -Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates - -There were build issues in libreboot. We don't use microcode updates anyway. -When selecting no microcode updates in menuconfig, build failed because -coreboot for these boards was still trying to add microcode. ---- - src/cpu/Makefile.inc | 34 +------------------------- - src/cpu/amd/family_10h-family_15h/Kconfig | 1 - - src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- - 3 files changed, 1 insertion(+), 44 deletions(-) - -diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc -index 046c418..ef0e236 100644 ---- a/src/cpu/Makefile.inc -+++ b/src/cpu/Makefile.inc -@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) - ## Rules for building the microcode blob in CBFS - ################################################################################ - --ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) --cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin --endif -- --ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) --cbfs-files-y += cpu_microcode_blob.bin --cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin -- --$(objgenerated)/microcode.bin: -- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" -- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) --endif -- --# We just mash all microcode binaries together into one binary to rule them all. --# This approach assumes that the microcode binaries are properly padded, and --# their headers specify the correct size. This works fairly well on isolatied --# updates, such as Intel and some AMD microcode, but won't work very well if the --# updates are wrapped in a container, like AMD's microcode update container. If --# there is only one microcode binary (i.e. one container), then we don't have --# this issue, and this rule will continue to work. --$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) -- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" -- @echo $(cpu_microcode_bins) -- cat /dev/null $+ > $@ -- --cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin --cpu_microcode_blob.bin-type := microcode -- --ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) --cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) --else --cpu_microcode_blob.bin-align := 16 --endif -+# What? Nope! We don't do that in libreboot. -diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig -index 14ab1cd..3f873a1 100644 ---- a/src/cpu/amd/family_10h-family_15h/Kconfig -+++ b/src/cpu/amd/family_10h-family_15h/Kconfig -@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX - select UDELAY_LAPIC - select HAVE_MONOTONIC_TIMER - select SUPPORT_CPU_UCODE_IN_CBFS -- select CPU_MICROCODE_MULTIPLE_FILES - - if CPU_AMD_MODEL_10XXX - -diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc -index f10f732..a295475 100644 ---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc -+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc -@@ -9,13 +9,3 @@ romstage-y += ram_calc.c - ramstage-y += ram_calc.c - ramstage-y += monotonic_timer.c - ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c -- --# Microcode for Family 10h, 11h, 12h, and 14h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin --microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin --microcode_amd.bin-type := microcode -- --# Microcode for Family 15h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-type := microcode --- -1.9.1 - diff --git a/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0001-util-xcompile-Detect-toolchains-with-bare-arm-prefix.patch b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0001-util-xcompile-Detect-toolchains-with-bare-arm-prefix.patch deleted file mode 100644 index 1e71ecfa..00000000 --- a/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0001-util-xcompile-Detect-toolchains-with-bare-arm-prefix.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 1a378294fa9afdc4d6d3b0e580ba78d33a62d044 Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski <contact@paulk.fr> -Date: Tue, 19 Apr 2016 12:02:14 +0200 -Subject: [PATCH 1/4] util: xcompile: Detect toolchains with bare arm prefix - -Signed-off-by: Paul Kocialkowski <contact@paulk.fr> ---- - util/xcompile/xcompile | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile -index b0199eb..1765183 100755 ---- a/util/xcompile/xcompile -+++ b/util/xcompile/xcompile -@@ -290,7 +290,7 @@ SUPPORTED_ARCHITECTURES="arm arm64 mipsel riscv x64 x86 power8" - arch_config_arm() { - TARCH="arm" - TBFDARCHS="littlearm" -- TCLIST="armv7-a armv7a" -+ TCLIST="armv7-a armv7a arm" - TWIDTH="32" - TSUPP="arm armv4 armv7 armv7_m" - TABI="eabi" --- -2.8.0 - diff --git a/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0002-libpayload-use-32bit-access-when-accessing-4byte-wid.patch b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0002-libpayload-use-32bit-access-when-accessing-4byte-wid.patch deleted file mode 100644 index b38cf561..00000000 --- a/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0002-libpayload-use-32bit-access-when-accessing-4byte-wid.patch +++ /dev/null @@ -1,48 +0,0 @@ -From be5ba870e006e8e7fe0f1ace2952b540c3aec3d9 Mon Sep 17 00:00:00 2001 -From: Patrick Georgi <pgeorgi@chromium.org> -Date: Mon, 8 Feb 2016 21:17:12 +0100 -Subject: [PATCH 2/4] libpayload: use 32bit access when accessing 4byte wide - uart registers - -This fixes serial on rk3288. - -Change-Id: I3dbf3cc165e516ed7b0132332624f882c0c9b27f -Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> -Reviewed-on: https://review.coreboot.org/13636 -Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> -Tested-by: build bot (Jenkins) ---- - payloads/libpayload/drivers/serial/8250.c | 10 ++++++++-- - 1 file changed, 8 insertions(+), 2 deletions(-) - -diff --git a/payloads/libpayload/drivers/serial/8250.c b/payloads/libpayload/drivers/serial/8250.c -index 7fe9920..0386f23 100644 ---- a/payloads/libpayload/drivers/serial/8250.c -+++ b/payloads/libpayload/drivers/serial/8250.c -@@ -46,7 +46,10 @@ static uint8_t serial_read_reg(int offset) - return inb(IOBASE + offset); - else - #endif -- return readb(MEMBASE + offset); -+ if (lib_sysinfo.serial->regwidth == 4) -+ return readl(MEMBASE + offset) & 0xff; -+ else -+ return readb(MEMBASE + offset); - } - - static void serial_write_reg(uint8_t val, int offset) -@@ -58,7 +61,10 @@ static void serial_write_reg(uint8_t val, int offset) - outb(val, IOBASE + offset); - else - #endif -- writeb(val, MEMBASE + offset); -+ if (lib_sysinfo.serial->regwidth == 4) -+ writel(val & 0xff, MEMBASE + offset); -+ else -+ writeb(val, MEMBASE + offset); - } - - #if IS_ENABLED(CONFIG_LP_SERIAL_SET_SPEED) --- -2.8.0 - diff --git a/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0003-rockchip-rk3288-UART-uses-32bit-wide-registers.patch b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0003-rockchip-rk3288-UART-uses-32bit-wide-registers.patch deleted file mode 100644 index 8a2d2533..00000000 --- a/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0003-rockchip-rk3288-UART-uses-32bit-wide-registers.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 02bc24a863a9b580d5eb32b780296ff8a5c3d2c1 Mon Sep 17 00:00:00 2001 -From: Patrick Georgi <pgeorgi@chromium.org> -Date: Mon, 8 Feb 2016 20:28:32 +0100 -Subject: [PATCH 3/4] rockchip/rk3288: UART uses 32bit wide registers - -Change-Id: I084eb4694a2aa8f66afc1f3148480608ac3ff02b -Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> -Reviewed-on: https://review.coreboot.org/13635 -Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> -Tested-by: build bot (Jenkins) -Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> ---- - src/soc/rockchip/rk3288/uart.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c -index 9847734..8576dc1 100644 ---- a/src/soc/rockchip/rk3288/uart.c -+++ b/src/soc/rockchip/rk3288/uart.c -@@ -155,7 +155,7 @@ void uart_fill_lb(void *data) - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - serial.baud = default_baudrate(); -- serial.regwidth = 1; -+ serial.regwidth = 4; - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); --- -2.8.0 - diff --git a/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0004-chromeos-Allow-disabling-vboot-firmware-verification.patch b/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0004-chromeos-Allow-disabling-vboot-firmware-verification.patch deleted file mode 100644 index 1139490a..00000000 --- a/resources/libreboot/patch/coreboot/1bf5e6409678d04fd15f9625460078853118521c/depthcharge/veyron_speedy/0004-chromeos-Allow-disabling-vboot-firmware-verification.patch +++ /dev/null @@ -1,112 +0,0 @@ -From 1122f7a00ad7b9cab11a548ed2ba24536bfc194e Mon Sep 17 00:00:00 2001 -From: Paul Kocialkowski <contact@paulk.fr> -Date: Sun, 9 Aug 2015 10:23:38 +0200 -Subject: [PATCH 4/4] chromeos: Allow disabling vboot firmware verification - when ChromeOS is enabled - -Some ChromeOS bindings might be wanted without using vboot verification, for -instance to boot up depthcharge from the version of Coreboot installed in the -write-protected part of the SPI flash (without jumping to a RW firmware). - -Vboot firmware verification is still selected by default when ChromeOS is -enabled, but this allows more flexibility since vboot firmware verification is -no longer a hard requirement for ChromeOS (that this particular use case still -allows booting ChromeOS). - -In the future, it would make sense to have all the separate components that -CONFIG_CHROMEOS enables have their own config options, so that they can be -enabled separately. - -Change-Id: Ia4057a56838aa05dcf3cb250ae1a27fd91402ddb -Signed-off-by: Paul Kocialkowski <contact@paulk.fr> ---- - src/lib/bootmode.c | 2 ++ - src/soc/rockchip/rk3288/Kconfig | 2 +- - src/vendorcode/google/chromeos/Kconfig | 4 +--- - src/vendorcode/google/chromeos/vboot2/Kconfig | 4 ++++ - 4 files changed, 8 insertions(+), 4 deletions(-) - -diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c -index 15f7a5a..e4be29e 100644 ---- a/src/lib/bootmode.c -+++ b/src/lib/bootmode.c -@@ -76,8 +76,10 @@ void gfx_set_init_done(int done) - int display_init_required(void) - { - /* For Chrome OS always honor vboot_skip_display_init(). */ -+#if CONFIG_VBOOT_VERIFY_FIRMWARE - if (IS_ENABLED(CONFIG_CHROMEOS)) - return !vboot_skip_display_init(); -+#endif - - /* By default always initialize display. */ - return 1; -diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig -index 65e6dc3..7947514 100644 ---- a/src/soc/rockchip/rk3288/Kconfig -+++ b/src/soc/rockchip/rk3288/Kconfig -@@ -31,7 +31,7 @@ config SOC_ROCKCHIP_RK3288 - - if SOC_ROCKCHIP_RK3288 - --config CHROMEOS -+config VBOOT_VERIFY_FIRMWARE - select VBOOT_STARTS_IN_BOOTBLOCK - select SEPARATE_VERSTAGE - select RETURN_FROM_VERSTAGE -diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig -index d2a42a1..4068419 100644 ---- a/src/vendorcode/google/chromeos/Kconfig -+++ b/src/vendorcode/google/chromeos/Kconfig -@@ -27,7 +27,6 @@ config CHROMEOS - select BOOTMODE_STRAPS - select ELOG if SPI_FLASH - select COLLECT_TIMESTAMPS -- select VBOOT_VERIFY_FIRMWARE - select MULTIPLE_CBFS_INSTANCES - help - Enable ChromeOS specific features like the GPIO sub table in -@@ -96,7 +95,6 @@ config CHROMEOS_RAMOOPS_RAM_SIZE - config EC_SOFTWARE_SYNC - bool "Enable EC software sync" - default n -- depends on VBOOT_VERIFY_FIRMWARE - help - EC software sync is a mechanism where the AP helps the EC verify its - firmware similar to how vboot verifies the main system firmware. This -@@ -120,12 +118,12 @@ config VBOOT_OPROM_MATTERS - config VIRTUAL_DEV_SWITCH - bool "Virtual developer switch support" - default n -- depends on VBOOT_VERIFY_FIRMWARE - help - Whether this platform has a virtual developer switch. - - config VBOOT_VERIFY_FIRMWARE - bool "Verify firmware with vboot." -+ default y if CHROMEOS - default n - depends on HAVE_HARD_RESET - help -diff --git a/src/vendorcode/google/chromeos/vboot2/Kconfig b/src/vendorcode/google/chromeos/vboot2/Kconfig -index 7580d8d..141b636 100644 ---- a/src/vendorcode/google/chromeos/vboot2/Kconfig -+++ b/src/vendorcode/google/chromeos/vboot2/Kconfig -@@ -12,6 +12,8 @@ - ## GNU General Public License for more details. - ## - -+if VBOOT_VERIFY_FIRMWARE -+ - config VBOOT_STARTS_IN_BOOTBLOCK - bool "Vboot starts verifying in bootblock" - default n -@@ -78,3 +80,5 @@ config VBOOT_DYNAMIC_WORK_BUFFER - ram to allocate the vboot work buffer. That means vboot verification - is after memory init and requires main memory to back the work - buffer. -+ -+endif # VBOOT_VERIFY_FIRMWARE --- -2.8.0 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/macbook21/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/macbook21/reused.list deleted file mode 100644 index 66de2acc..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/macbook21/reused.list +++ /dev/null @@ -1,4 +0,0 @@ -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_16mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_16mb/INFO deleted file mode 100644 index ad7d12f4..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_16mb/INFO +++ /dev/null @@ -1,4 +0,0 @@ -# NOTE: remove this when updating coreboot. This has been merged upstream -printf "ThinkPad R400 support (clone of the T400)\n" -git am "../resources/libreboot/patch/misc/0007-lenovo-r400-Add-clone-of-Lenovo-T400.patch" -# git fetch http://review.coreboot.org/coreboot refs/changes/93/8393/5 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_16mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_16mb/reused.list deleted file mode 100644 index 232bc349..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_16mb/reused.list +++ /dev/null @@ -1,6 +0,0 @@ -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_4mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_4mb/reused.list deleted file mode 100644 index 232bc349..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_4mb/reused.list +++ /dev/null @@ -1,6 +0,0 @@ -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_8mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_8mb/INFO deleted file mode 100644 index ad7d12f4..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_8mb/INFO +++ /dev/null @@ -1,4 +0,0 @@ -# NOTE: remove this when updating coreboot. This has been merged upstream -printf "ThinkPad R400 support (clone of the T400)\n" -git am "../resources/libreboot/patch/misc/0007-lenovo-r400-Add-clone-of-Lenovo-T400.patch" -# git fetch http://review.coreboot.org/coreboot refs/changes/93/8393/5 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_8mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_8mb/reused.list deleted file mode 100644 index 232bc349..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_8mb/reused.list +++ /dev/null @@ -1,6 +0,0 @@ -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_16mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_16mb/INFO deleted file mode 100644 index 9ef6d54a..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_16mb/INFO +++ /dev/null @@ -1,8 +0,0 @@ -# NOTE: merged upstream already -printf "mainboard/lenovo/t400: Add initial hybrid graphics support\n" -git am "../resources/libreboot/patch/misc/0001-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch" -# git fetch http://review.coreboot.org/coreboot refs/changes/19/9319/18 && git cherry-pick FETCH_HEAD - -printf "NOTFORMERGE: lenovo/t400: hard-code enable integrated-only video\n" -git am "../resources/libreboot/patch/misc/0002-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch" -# git fetch http://review.coreboot.org/coreboot refs/changes/50/10550/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_16mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_16mb/reused.list deleted file mode 100644 index 232bc349..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_16mb/reused.list +++ /dev/null @@ -1,6 +0,0 @@ -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_4mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_4mb/reused.list deleted file mode 100644 index 232bc349..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_4mb/reused.list +++ /dev/null @@ -1,6 +0,0 @@ -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch deleted file mode 100644 index 49b9549a..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 873402fb594f06e748563ebf3abc7970613b9bda Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 8 Aug 2016 23:55:13 +0200 -Subject: [PATCH] make 256M vram the default for gm45 laptops - -Change-Id: Id213807d1ed3260846118f69b459bcad7a146c30 - -diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default -index 98ce970..90d796f 100644 ---- a/src/mainboard/lenovo/t400/cmos.default -+++ b/src/mainboard/lenovo/t400/cmos.default -@@ -13,4 +13,5 @@ sticky_fn=Disable - power_management_beeps=Enable - low_battery_beep=Enable - sata_mode=AHCI --hybrid_graphics_mode=Integrated Only -\ No newline at end of file -+hybrid_graphics_mode=Integrated Only -+gfx_uma_size=256M -\ No newline at end of file -diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default -index 1d7b420..ec7ab46 100644 ---- a/src/mainboard/lenovo/x200/cmos.default -+++ b/src/mainboard/lenovo/x200/cmos.default -@@ -13,4 +13,4 @@ sticky_fn=Disable - power_management_beeps=Enable - low_battery_beep=Enable - sata_mode=AHCI --gfx_uma_size=32M -\ No newline at end of file -+gfx_uma_size=256M -\ No newline at end of file --- -2.9.2 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch deleted file mode 100644 index 76463937..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +++ /dev/null @@ -1,27 +0,0 @@ -From 99b8fb271fd244d8e349ca956819c7e1b3420d80 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 8 Aug 2016 21:51:34 +0200 -Subject: [PATCH] hardcode use on intel integrated graphic device on t400 - -Change-Id: I2ff2d93b024866063715d26aedf510a9753a5445 ---- - src/mainboard/lenovo/t400/romstage.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c -index 147131f..1316d69 100644 ---- a/src/mainboard/lenovo/t400/romstage.c -+++ b/src/mainboard/lenovo/t400/romstage.c -@@ -208,7 +208,8 @@ void main(unsigned long bist) - default_southbridge_gpio_setup(); - - uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; -- get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); -+ /* hardcode use of integrated graphic device for libreboot */ -+ /* get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); */ - - /* Set up hybrid graphics */ - hybrid_graphics_set_up_gpio(); --- -2.9.2 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/INFO deleted file mode 100644 index 9ef6d54a..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/INFO +++ /dev/null @@ -1,8 +0,0 @@ -# NOTE: merged upstream already -printf "mainboard/lenovo/t400: Add initial hybrid graphics support\n" -git am "../resources/libreboot/patch/misc/0001-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch" -# git fetch http://review.coreboot.org/coreboot refs/changes/19/9319/18 && git cherry-pick FETCH_HEAD - -printf "NOTFORMERGE: lenovo/t400: hard-code enable integrated-only video\n" -git am "../resources/libreboot/patch/misc/0002-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch" -# git fetch http://review.coreboot.org/coreboot refs/changes/50/10550/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/reused.list deleted file mode 100644 index 168e1ca8..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/reused.list +++ /dev/null @@ -1,4 +0,0 @@ -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_16mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_16mb/INFO deleted file mode 100644 index 0537bbc8..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_16mb/INFO +++ /dev/null @@ -1,4 +0,0 @@ -# NOTE: remove this when updating coreboot. This has been merged upstream -printf "ThinkPad T500 (depends on T400 patch)\n" -git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch" -# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_16mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_16mb/reused.list deleted file mode 100644 index 232bc349..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_16mb/reused.list +++ /dev/null @@ -1,6 +0,0 @@ -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_4mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_4mb/reused.list deleted file mode 100644 index 232bc349..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_4mb/reused.list +++ /dev/null @@ -1,6 +0,0 @@ -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_8mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_8mb/INFO deleted file mode 100644 index 0537bbc8..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_8mb/INFO +++ /dev/null @@ -1,4 +0,0 @@ -# NOTE: remove this when updating coreboot. This has been merged upstream -printf "ThinkPad T500 (depends on T400 patch)\n" -git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch" -# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_8mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_8mb/reused.list deleted file mode 100644 index 232bc349..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_8mb/reused.list +++ /dev/null @@ -1,6 +0,0 @@ -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/0001-lenovo-t60-Enable-brightness-controls-native-graphic.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/0001-lenovo-t60-Enable-brightness-controls-native-graphic.patch deleted file mode 100644 index 2e3ee65b..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/0001-lenovo-t60-Enable-brightness-controls-native-graphic.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 770021ce66a0fddebb9639c4df0696ecfca45488 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Mon, 15 Jun 2015 19:59:46 +0100 -Subject: [PATCH 4/9] lenovo/t60: Enable brightness controls (native graphics) - -This makes the Fn Home/End keys work for controlling the -brightness of the display. Value obtained by reading -BLC_PWM_CTL when running the VBIOS (option ROM). - -On i945 legacy brightness control is enabled by a single -bit in BLC_PWM_CTL. It's bit 16 or bit 0 (the other one -reverses polarity). Set the bit to enable brightness -controls. - -Change-Id: I22e261f2ce28ec81cd208a73e6311ec67146eb72 -Signed-off-by: Leah Rowe <info@minifree.org> ---- - src/mainboard/lenovo/t60/devicetree.cb | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb -index b28f1ad..9e6ce02 100644 ---- a/src/mainboard/lenovo/t60/devicetree.cb -+++ b/src/mainboard/lenovo/t60/devicetree.cb -@@ -26,7 +26,7 @@ chip northbridge/intel/i945 - - register "gpu_hotplug" = "0x00000220" - register "gpu_lvds_use_spread_spectrum_clock" = "1" -- register "gpu_backlight" = "0x1280128" -+ register "gpu_backlight" = "0x58BF58BE" - - device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 --- -1.9.1 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch deleted file mode 100644 index 0b8e146a..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch +++ /dev/null @@ -1,53 +0,0 @@ -From bbd04909524d7b9fd2e2b4dbd804801bbde66e44 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Wed, 7 Sep 2016 21:16:21 +0200 -Subject: [PATCH] lenovo/t60: add hda_verb.c - -This creates a config for the Lenovo T60 sound card based -on values taken from vendor bios -(in /sys/class/sound/hwC0D0/init_pin_configs on linux 3.16). -The sound card configuration on the vendor bios is the same -as the one on the Lenovo x60. - -It improves the default behavior of the sound card: -- internal microphone is chosen by default -- when jack is inserted it is chosen instead of internal speaker - -Change-Id: I44e3eaac437fe4ad97ff2b0eb32d36b33222c09b -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/mainboard/lenovo/t60/hda_verb.c | 19 +++++++++++++++++-- - 1 file changed, 17 insertions(+), 2 deletions(-) - -diff --git a/src/mainboard/lenovo/t60/hda_verb.c b/src/mainboard/lenovo/t60/hda_verb.c -index 072a306..dee3e80 100644 ---- a/src/mainboard/lenovo/t60/hda_verb.c -+++ b/src/mainboard/lenovo/t60/hda_verb.c -@@ -1,7 +1,22 @@ - #include <device/azalia_device.h> - --const u32 cim_verb_data[0] = {}; -+const u32 cim_verb_data[] = { -+ 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ -+ 0x17aa2025, /* Subsystem ID */ -+ 0x0000000b, /* Number of 4 dword sets */ - --const u32 pc_beep_verbs[0] = {}; -+ AZALIA_SUBVENDOR(0x0, 0x17aa2025), - -+ AZALIA_PIN_CFG(0, 0x05, 0xc3014110), -+ AZALIA_PIN_CFG(0, 0x06, 0x4221401f), -+ AZALIA_PIN_CFG(0, 0x07, 0x591311f0), -+ AZALIA_PIN_CFG(0, 0x08, 0xc3a15020), -+ AZALIA_PIN_CFG(0, 0x09, 0x41813021), -+ AZALIA_PIN_CFG(0, 0x0a, 0x014470f0), -+ AZALIA_PIN_CFG(0, 0x16, 0x59f311f0), -+ AZALIA_PIN_CFG(0, 0x17, 0x59931122), -+ AZALIA_PIN_CFG(0, 0x18, 0x41a19023), -+ AZALIA_PIN_CFG(0, 0x19, 0x9933e12e) -+}; -+const u32 pc_beep_verbs[0] = {}; - AZALIA_ARRAY_SIZES; --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/INFO deleted file mode 100644 index cb543aae..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/INFO +++ /dev/null @@ -1,3 +0,0 @@ -printf "lenovo/t60: Enable brightness controls (native graphics)\n" -git am "../resources/libreboot/patch/misc/0004-lenovo-t60-Enable-brightness-controls-native-graphic.patch" -# git fetch http://review.coreboot.org/coreboot refs/changes/52/10552/2 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/reused.list deleted file mode 100644 index 169db084..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/reused.list +++ /dev/null @@ -1,5 +0,0 @@ -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_16mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_16mb/INFO deleted file mode 100644 index 220b8583..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_16mb/INFO +++ /dev/null @@ -1,5 +0,0 @@ -# NOTE: remove this when updating to the latest version of coreboot. this patch -# makes the patch below redundant: https://review.coreboot.org/#/c/12814/ -printf "northbridge/gm45/raminit.c: enable GS45 high-perf (i.e. add X200S support to libreboot)\n" -git am "../resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch" -# git fetch http://review.coreboot.org/coreboot refs/changes/35/11135/3 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_16mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_16mb/reused.list deleted file mode 100644 index c6494f25..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_16mb/reused.list +++ /dev/null @@ -1,5 +0,0 @@ -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-set-default-vram-to-256M.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_4mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_4mb/reused.list deleted file mode 100644 index c6494f25..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_4mb/reused.list +++ /dev/null @@ -1,5 +0,0 @@ -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-set-default-vram-to-256M.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch -/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch deleted file mode 100644 index d89e4884..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 0821d0290e7e17e375ffdb48a86b56504db4f77e Mon Sep 17 00:00:00 2001 -From: Damien Zammit <damien@zamaudio.com> -Date: Sat, 27 Aug 2016 00:35:48 +1000 -Subject: [PATCH] nb/intel/gm45: Fix IOMMU - -Previously the ME was being reported as present in ACPI -even when it's firmware was missing. Now we do a check via the pci device -(HECI) to verify if the ME is there or not. - -Note that this test could fail if ME is present but disabled in devicetree, -but in that case you won't see it in the lspci tree anyway so it shouldn't -be an issue. - -Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0 -Signed-off-by: Damien Zammit <damien@zamaudio.com> ---- - src/northbridge/intel/gm45/acpi.c | 3 ++- - src/northbridge/intel/gm45/iommu.c | 2 ++ - 2 files changed, 4 insertions(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c -index 8990c3b..b90afca 100644 ---- a/src/northbridge/intel/gm45/acpi.c -+++ b/src/northbridge/intel/gm45/acpi.c -@@ -72,7 +72,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) - - static unsigned long acpi_fill_dmar(unsigned long current) - { -- int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL); -+ int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL) && -+ (pci_read_config8(dev_find_slot(0, PCI_DEVFN(3, 0)), PCI_CLASS_REVISION) != 0xff); - int stepping = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_CLASS_REVISION); - - unsigned long tmp = current; -diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c -index 10548f4..0c3c18e 100644 ---- a/src/northbridge/intel/gm45/iommu.c -+++ b/src/northbridge/intel/gm45/iommu.c -@@ -40,6 +40,8 @@ void init_iommu() - } - if (me_active) { - MCHBAR32(0x10) = IOMMU_BASE3 | 1; /* ME @ 0:3.0-3 */ -+ } else { -+ MCHBAR32(0x10) = 0; /* disable IOMMU for ME */ - } - MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */ - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-set-default-vram-to-256M.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-set-default-vram-to-256M.patch deleted file mode 100644 index 01124c34..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-set-default-vram-to-256M.patch +++ /dev/null @@ -1,38 +0,0 @@ -From c98d8745d4dca650709e76269cf014e5ffbc1443 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Tue, 9 Aug 2016 00:54:37 +0200 -Subject: [PATCH] set default vram to 256M - -Change-Id: Ife906c47f32493d9a647a4f12f25982623eba189 ---- - src/mainboard/lenovo/t400/cmos.default | 2 +- - src/mainboard/lenovo/x200/cmos.default | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - -diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default -index 5cf3e63..90d796f 100644 ---- a/src/mainboard/lenovo/t400/cmos.default -+++ b/src/mainboard/lenovo/t400/cmos.default -@@ -14,4 +14,4 @@ power_management_beeps=Enable - low_battery_beep=Enable - sata_mode=AHCI - hybrid_graphics_mode=Integrated Only --gfx_uma_size=32M -\ No newline at end of file -+gfx_uma_size=256M -\ No newline at end of file -diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default -index 1d7b420..ec7ab46 100644 ---- a/src/mainboard/lenovo/x200/cmos.default -+++ b/src/mainboard/lenovo/x200/cmos.default -@@ -13,4 +13,4 @@ sticky_fn=Disable - power_management_beeps=Enable - low_battery_beep=Enable - sata_mode=AHCI --gfx_uma_size=32M -\ No newline at end of file -+gfx_uma_size=256M -\ No newline at end of file --- -2.9.2 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch deleted file mode 100644 index 26632b7d..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0002-gm45-gma.c-use-screen-on-vga-connector-if-connected.patch +++ /dev/null @@ -1,212 +0,0 @@ -From 51dc727c71bbb10519a670b83b67a84f704e003a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 22 Aug 2016 17:58:46 +0200 -Subject: [PATCH 1/2] gm45/gma.c: use screen on vga connector if connected - -The intel x4x and gm45 have very similar integrated graphic devices. -Currently the x4x native graphic init enables VGA, while gm45 can output -on LVDS. - -This patch reuses the x4x graphic initialisation code -to enable output on VGA in gm45 in a way that the behavior is similar to vbios: -If no VGA display is connected the internal LVDS screen is used. -If an external screen is detected on the VGA port it will be used instead. - -Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 157 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 153 insertions(+), 4 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..74c9bc3 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -47,7 +47,7 @@ void gtt_write(u32 reg, u32 data) - write32(res2mmio(gtt_res, reg, 0), data); - } - --static void intel_gma_init(const struct northbridge_intel_gm45_config *info, -+static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -@@ -101,7 +101,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - sizeof(edid_data), &edid); - mode = &edid.mode; - -- /* Disable screen memory to prevent garbage from appearing. */ -+ /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - - hactive = edid.x_resolution; -@@ -344,6 +344,152 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, - } - } - -+static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -+ u8 *mmio) -+{ -+ -+ int i; -+ u32 hactive, vactive; -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(mmio + VGA0, 0x31108); -+ write32(mmio + VGA1, 0x31406); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + 0x7041c, 0x0); -+ write32(mmio + DPLL_MD(0), 0x3); -+ write32(mmio + DPLL_MD(1), 0x3); -+ -+ vga_misc_write(0x67); -+ -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ /* Disable screen memory to prevent garbage from appearing. */ -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(mmio + FP0(0), 0x31108); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ mdelay(1); -+ write32(mmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x10601 -+ ); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(mmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(mmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(mmio + PIPECONF(0), PIPECONF_DISABLE); -+ -+ write32(mmio + PF_WIN_POS(0), 0); -+ -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0xa0000000); -+ -+ mdelay(1); -+ -+ write32(mmio + 0x000f000c, 0x00002040); -+ mdelay(1); -+ write32(mmio + 0x000f000c, 0x00002050); -+ write32(mmio + 0x00060100, 0x00044000); -+ mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_ENABLE -+ | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(mmio + VGACNTRL, 0x0); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(mmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_CRT_HOTPLUG_MONITOR_COLOR -+ | ADPA_CRT_HOTPLUG_ENABLE -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ /* Clear interrupts. */ -+ write32(mmio + DEIIR, 0xffffffff); -+ write32(mmio + SDEIIR, 0xffffffff); -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should not have a correct header */ -+static u8 vga_connected(u8 *mmio) -+{ -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - static void gma_pm_init_post_vbios(struct device *const dev) - { - const struct northbridge_intel_gm45_config *const conf = dev->chip_info; -@@ -419,8 +565,11 @@ static void gma_func0_init(struct device *dev) - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, -- pio_res->base, lfb_res->base); -+ if (vga_connected(res2mmio(gtt_res, 0, 0))) -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ else -+ gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch deleted file mode 100644 index ef42f3e8..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0003-nb-gm45-gma.c-enable-VESA-framebuffer-mode-on-VGA-ou.patch +++ /dev/null @@ -1,379 +0,0 @@ -From 44423cb3e0118b04739f89409e71a0ed1622ccd2 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sat, 27 Aug 2016 01:09:19 +0200 -Subject: [PATCH 2/2] nb/gm45/gma.c: enable VESA framebuffer mode on VGA output - -This implements "Keep VESA framebuffer" behavior on VGA output of gm45. -This patch reuses Linux code to compute vga divisors. - -Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 251 ++++++++++++++++++++++++++++++++------- - 1 file changed, 209 insertions(+), 42 deletions(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index 74c9bc3..efaa210 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -25,6 +25,7 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" -@@ -35,6 +36,8 @@ - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUECY 96000 -+ - static struct resource *gtt_res = NULL; - - u32 gtt_read(u32 reg) -@@ -345,14 +348,38 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, - } - - static void gma_init_vga(const struct northbridge_intel_gm45_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u32 hactive, vactive, right_border, bottom_border; -+ int hpolarity, vpolarity; -+ u32 vsync, hsync, vblank, hblank, hfront_porch, vfront_porch; -+ u32 target_frequency; -+ u32 smallest_err = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Setup GTT. */ -+ for (i = 0; i < 0x2000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -363,8 +390,7 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE -- | ADPA_DPMS_ON -- ); -+ | ADPA_DPMS_ON); - - write32(mmio + 0x7041c, 0x0); - write32(mmio + DPLL_MD(0), 0x3); -@@ -382,95 +408,234 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 17; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUECY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < smallest_err) { -+ smallest_err= this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (smallest_err == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUECY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2) / (pixel_n + 2) -+ / (pixel_p1 * 10))); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ edid.x_resolution * edid.y_resolution * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } -+ -+ - } - - /* compare the header of the vga edid header */ -@@ -480,6 +645,7 @@ static u8 vga_connected(u8 *mmio) - u8 vga_edid[128]; - u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; - intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(mmio + GMBUS0); - for (int i = 0; i < 8; i++) { - if (vga_edid[i] != header[i]) { - printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -@@ -566,7 +732,8 @@ static void gma_func0_init(struct device *dev) - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - if (vga_connected(res2mmio(gtt_res, 0, 0))) -- gma_init_vga(conf, res2mmio(gtt_res, 0, 0)); -+ gma_init_vga(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - else - gma_init_lvds(conf, res2mmio(gtt_res, 0, 0), - physbase, pio_res->base, lfb_res->base); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch deleted file mode 100644 index fb30c4c2..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0004-gm45-gma.c-use-correct-id-string-for-fake-VBT.patch +++ /dev/null @@ -1,31 +0,0 @@ -From d7fe366539f2a492b4a64030618506690bfbb232 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 8 Sep 2016 22:21:54 +0200 -Subject: [PATCH] gm45/gma.c: use correct id string for fake VBT - -The correct id string for gm45 is "$VBT CANTIGA ". -This can be found in the gm45 option rom: -"strings vbios.bin | grep VBT". - -Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/gm45/gma.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c -index d5f6471..19bd944 100644 ---- a/src/northbridge/intel/gm45/gma.c -+++ b/src/northbridge/intel/gm45/gma.c -@@ -425,7 +425,7 @@ static void gma_func0_init(struct device *dev) - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, -- "$VBT IRONLAKE-MOBILE"); -+ "$VBT CANTIGA "); - } - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/INFO deleted file mode 100644 index 220b8583..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/INFO +++ /dev/null @@ -1,5 +0,0 @@ -# NOTE: remove this when updating to the latest version of coreboot. this patch -# makes the patch below redundant: https://review.coreboot.org/#/c/12814/ -printf "northbridge/gm45/raminit.c: enable GS45 high-perf (i.e. add X200S support to libreboot)\n" -git am "../resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch" -# git fetch http://review.coreboot.org/coreboot refs/changes/35/11135/3 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0001-lenovo-x60-add-hda_verb.c.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0001-lenovo-x60-add-hda_verb.c.patch deleted file mode 100644 index 80eda28b..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0001-lenovo-x60-add-hda_verb.c.patch +++ /dev/null @@ -1,65 +0,0 @@ -From 4f3452fc544d4e799445c3271b1022496932473c Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Fri, 3 Jun 2016 18:37:38 +0200 -Subject: [PATCH] lenovo/x60: add hda_verb.c - -This creates a config for the x60 audio based -on values taken from vendor bios. - -What is improved: -- internal microphone is chosen by default -- when jack is inserted it chosen instead of internal speaker - -Before this had to be done manually. - -Change-Id: Id3b700fd84905a72cc1f69e7d8bfa6145f231756 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> - -diff --git a/src/mainboard/lenovo/x60/hda_verb.c b/src/mainboard/lenovo/x60/hda_verb.c -index 072a306..c4b1f3a 100644 ---- a/src/mainboard/lenovo/x60/hda_verb.c -+++ b/src/mainboard/lenovo/x60/hda_verb.c -@@ -1,7 +1,38 @@ -+/* -+ * This file is part of the coreboot project. -+ * -+ * Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz> -+ * -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; version 2 of -+ * the License. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ */ -+ - #include <device/azalia_device.h> - --const u32 cim_verb_data[0] = {}; -+const u32 cim_verb_data[] = { -+ 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ -+ 0x17aa2025, /* Subsystem ID */ -+ 0x0000000b, /* Number of 4 dword sets */ - --const u32 pc_beep_verbs[0] = {}; -+ AZALIA_SUBVENDOR(0x0, 0x17aa2025), - -+ AZALIA_PIN_CFG(0, 0x05, 0xc3014110), -+ AZALIA_PIN_CFG(0, 0x06, 0x4221401f), -+ AZALIA_PIN_CFG(0, 0x07, 0x591311f0), -+ AZALIA_PIN_CFG(0, 0x08, 0xc3a15020), -+ AZALIA_PIN_CFG(0, 0x09, 0x41813021), -+ AZALIA_PIN_CFG(0, 0x0a, 0x014470f0), -+ AZALIA_PIN_CFG(0, 0x16, 0x59f311f0), -+ AZALIA_PIN_CFG(0, 0x17, 0x59931122), -+ AZALIA_PIN_CFG(0, 0x18, 0x41a19023), -+ AZALIA_PIN_CFG(0, 0x19, 0x9933e12e) -+}; -+const u32 pc_beep_verbs[0] = {}; - AZALIA_ARRAY_SIZES; --- -2.8.3 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0002-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0002-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch deleted file mode 100644 index 7470dd60..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0002-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch +++ /dev/null @@ -1,31 +0,0 @@ -From e4b5b65c93122126344771f2042f8d7a3468be19 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Mon, 22 Jun 2015 17:37:06 +0100 -Subject: [PATCH 3/9] lenovo/x60: use correct BLC_PWM_CTL value - -Bit 16 in BLC_PWM_CTL enables brightness controls, but the -current value is generic. Use the proper value, obtained -by reading BLC_PWM_CTL while running the VBIOS. - -Change-Id: Ib273359e1c285b405a9bb26fc217c2f7e255b99f -Signed-off-by: Leah Rowe <info@minifree.org> ---- - src/mainboard/lenovo/x60/devicetree.cb | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - -diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb -index b4d1144..4d62116 100644 ---- a/src/mainboard/lenovo/x60/devicetree.cb -+++ b/src/mainboard/lenovo/x60/devicetree.cb -@@ -26,7 +26,7 @@ chip northbridge/intel/i945 - - register "gpu_hotplug" = "0x00000220" - register "gpu_lvds_use_spread_spectrum_clock" = "1" -- register "gpu_backlight" = "0x1290128" -+ register "gpu_backlight" = "0x879F879E" - - device cpu_cluster 0 on - chip cpu/intel/socket_mFCPGA478 --- -1.9.1 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch deleted file mode 100644 index 86bd6cb0..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Fri, 2 Sep 2016 22:35:32 +0200 -Subject: [PATCH] i945/gma.c use latest linux code to calculate divisors. - -The code to compute n, m1, m2, p1 divisors is not correct in coreboot and -on some targets hits a working mode at lower refresh rate, which is why -display is working on some targets. -This patch also fixes reference frequency. - -This patch reuses linux code to correctly compute divisors. - -The result is that some previously not working displays (Lenovo T60 with -1024x786, 1400x1050, 2048x1536) - -TESTED on T60 with 1024x786. - -Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- - 1 file changed, 38 insertions(+), 44 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..3f0b5b4 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -26,6 +26,8 @@ - #include <string.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> -+#include <commonlib/helpers.h> -+ - - #include "i945.h" - #include "chip.h" -@@ -43,7 +45,7 @@ - #define PGETBL_CTL 0x2020 - #define PGETBL_ENABLED 0x00000001 - --#define BASE_FREQUENCY 120000 -+#define BASE_FREQUENCY 100000 - - #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - -@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - u8 edid_data[128]; - unsigned long temp; - int hpolarity, vpolarity; -- u32 candp1, candn; -- u32 best_delta = 0xffffffff; -+ u32 smallest_err = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; -+ u32 pixel_p2; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; -@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - -- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock -- : (2 * mode->pixel_clock); -- -- /* Find suitable divisors. */ -- for (candp1 = 1; candp1 <= 8; candp1++) { -- for (candn = 5; candn <= 10; candn++) { -- u32 cur_frequency; -- u32 m; /* 77 - 131. */ -- u32 denom; /* 35 - 560. */ -- u32 current_delta; -- -- denom = candn * candp1 * 7; -- /* Doesnt overflow for up to -- 5000000 kHz = 5 GHz. */ -- m = (target_frequency * denom -- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; -- -- if (m < 77 || m > 131) -- continue; -- -- cur_frequency = (BASE_FREQUENCY * m) / denom; -- if (target_frequency > cur_frequency) -- current_delta = target_frequency - cur_frequency; -- else -- current_delta = cur_frequency - target_frequency; -- -- if (best_delta > current_delta) { -- best_delta = current_delta; -- pixel_n = candn; -- pixel_p1 = candp1; -- pixel_m2 = ((m + 3) % 5) + 7; -- pixel_m1 = (m - pixel_m2) / 5; -+ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; -+ target_frequency = mode->pixel_clock; -+ -+ /* Find suitable divisors, m1, m2, p1, n. */ -+ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ -+ /* should be closest to target frequency as possible */ -+ u32 candn, candm1, candm2, candp1; -+ for (candm1 = 8; candm1 <= 18; candm1++) { -+ for (candm2 = 3; candm2 <= 7; candm2++) { -+ for (candn = 1; candn <= 6; candn++) { -+ for (candp1 = 1; candp1 <= 8; candp1++) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * pixel_p2; -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if ((m < 70) || (m > 120)) -+ continue; -+ if (this_err < smallest_err) { -+ smallest_err = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } - } - } - } - -- if (best_delta == 0xffffffff) { -+ if (smallest_err == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return -1; - } -@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n -- / (pixel_p1 * 7)); -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * pixel_p2)); - - #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(pmmio + FP0(1), -- ((pixel_n - 2) << 16) -- | ((pixel_m1 - 2) << 8) | pixel_m2); -+ (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS -@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (conf->gpu_lvds_use_spread_spectrum_clock - ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV - : 0) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | -@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + HTOTAL(1), - ((hactive + right_border + hblank - 1) << 16) --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch deleted file mode 100644 index 14f809a9..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 483bbb3ec7965ca2416fda9e11687bcd655d078d Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Tue, 31 May 2016 16:51:59 +0200 -Subject: [PATCH] model_6ex: enable C2E, C4E, dynamic lvl 2 cache. - -Change-Id: Ie538d2145640c7b50ac0a0fa432d98ae2c4be060 - -diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c -index 6fa6d3a..8ff276a 100644 ---- a/src/cpu/intel/model_6ex/model_6ex_init.c -+++ b/src/cpu/intel/model_6ex/model_6ex_init.c -@@ -67,9 +67,10 @@ static void configure_c_states(void) - - msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); - msr.lo |= (1 << 15); // config lock until next reset. -+ msr.lo |= (1 << 14); // Deeper Sleep - msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States - msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk -- // TODO Do we want Deep C4 and Dynamic L2 shrinking? -+ msr.lo |= (1 << 3); // Dynamic L2 - - /* Number of supported C-States */ - msr.lo &= ~7; -@@ -94,16 +95,20 @@ static void configure_misc(void) - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); -- msr.lo |= (1 << 3); /* TM1 enable */ -+ msr.lo |= (1 << 3); /* TM1 enable */ - msr.lo |= (1 << 13); /* TM2 enable */ - msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ - - msr.lo |= (1 << 10); /* FERR# multiplexing */ - -- // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ -+ /* Enable C2E */ -+ msr.lo |= (1 << 26); -+ -+ /* Enable C4E */ -+ msr.hi |= (1 << (32 - 32)); // C4E -+ msr.hi |= (1 << (33 - 32)); // Hard C4E - -- // TODO Do we want Deep C4 and Dynamic L2 shrinking? - wrmsr(IA32_MISC_ENABLE, msr); - - msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ --- -2.8.3 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch deleted file mode 100644 index 884b2829..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0005-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch +++ /dev/null @@ -1,174 +0,0 @@ -From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Fri, 2 Sep 2016 22:35:32 +0200 -Subject: [PATCH 1/2] i945/gma.c use latest linux code to calculate divisors. - -The code to compute n, m1, m2, p1 divisors is not correct in coreboot and -on some targets hits a working mode at lower refresh rate, which is why -display is working on some targets. -This patch also fixes reference frequency. - -This patch reuses linux code to correctly compute divisors. - -The result is that some previously not working displays (Lenovo T60 with -1024x786, 1400x1050, 2048x1536) - -TESTED on T60 with 1024x786. - -Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- - 1 file changed, 38 insertions(+), 44 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..3f0b5b4 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -26,6 +26,8 @@ - #include <string.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> -+#include <commonlib/helpers.h> -+ - - #include "i945.h" - #include "chip.h" -@@ -43,7 +45,7 @@ - #define PGETBL_CTL 0x2020 - #define PGETBL_ENABLED 0x00000001 - --#define BASE_FREQUENCY 120000 -+#define BASE_FREQUENCY 100000 - - #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - -@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - u8 edid_data[128]; - unsigned long temp; - int hpolarity, vpolarity; -- u32 candp1, candn; -- u32 best_delta = 0xffffffff; -+ u32 smallest_err = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; -+ u32 pixel_p2; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; -@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - -- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock -- : (2 * mode->pixel_clock); -- -- /* Find suitable divisors. */ -- for (candp1 = 1; candp1 <= 8; candp1++) { -- for (candn = 5; candn <= 10; candn++) { -- u32 cur_frequency; -- u32 m; /* 77 - 131. */ -- u32 denom; /* 35 - 560. */ -- u32 current_delta; -- -- denom = candn * candp1 * 7; -- /* Doesnt overflow for up to -- 5000000 kHz = 5 GHz. */ -- m = (target_frequency * denom -- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; -- -- if (m < 77 || m > 131) -- continue; -- -- cur_frequency = (BASE_FREQUENCY * m) / denom; -- if (target_frequency > cur_frequency) -- current_delta = target_frequency - cur_frequency; -- else -- current_delta = cur_frequency - target_frequency; -- -- if (best_delta > current_delta) { -- best_delta = current_delta; -- pixel_n = candn; -- pixel_p1 = candp1; -- pixel_m2 = ((m + 3) % 5) + 7; -- pixel_m1 = (m - pixel_m2) / 5; -+ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; -+ target_frequency = mode->pixel_clock; -+ -+ /* Find suitable divisors, m1, m2, p1, n. */ -+ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ -+ /* should be closest to target frequency as possible */ -+ u32 candn, candm1, candm2, candp1; -+ for (candm1 = 8; candm1 <= 18; candm1++) { -+ for (candm2 = 3; candm2 <= 7; candm2++) { -+ for (candn = 1; candn <= 6; candn++) { -+ for (candp1 = 1; candp1 <= 8; candp1++) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * pixel_p2; -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if ((m < 70) || (m > 120)) -+ continue; -+ if (this_err < smallest_err) { -+ smallest_err = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } - } - } - } - -- if (best_delta == 0xffffffff) { -+ if (smallest_err == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return -1; - } -@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n -- / (pixel_p1 * 7)); -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * pixel_p2)); - - #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(pmmio + FP0(1), -- ((pixel_n - 2) << 16) -- | ((pixel_m1 - 2) << 8) | pixel_m2); -+ (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS -@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (conf->gpu_lvds_use_spread_spectrum_clock - ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV - : 0) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | -@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + HTOTAL(1), - ((hactive + right_border + hblank - 1) << 16) --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch deleted file mode 100644 index 26eed5b4..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0006-i945-gma.c-add-native-VGA-init.patch +++ /dev/null @@ -1,241 +0,0 @@ -From 7ed0951bcf59dfd8b1893232b674455ff8f03f83 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 5 Sep 2016 22:46:11 +0200 -Subject: [PATCH 2/2] i945/gma.c: add native VGA init - -This reuses the Intel Pineview native graphic initialization -to have output on the VGA connector of i945 devices. - -The behavior is the same as with the vendor VBIOS BLOB. -It uses the external VGA display if it is connected. - -Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 196 ++++++++++++++++++++++++++++++++++++++- - 1 file changed, 194 insertions(+), 2 deletions(-) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 3f0b5b4..ac19d5a 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase) - return 0; - } - --static int intel_gma_init(struct northbridge_intel_i945_config *conf, -+static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, - unsigned int pphysbase, unsigned int piobase, - void *pmmio, unsigned int pgfx) - { -@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - #endif - return 0; - } -+ -+static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, -+ unsigned int pphysbase, unsigned int piobase, -+ void *pmmio, unsigned int pgfx) -+{ -+ int i; -+ u32 hactive, vactive; -+ u16 reg16; -+ u32 uma_size; -+ -+ printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", -+ (u32)pmmio, piobase, pphysbase); -+ -+ gtt_setup(pmmio); -+ -+ /* Disable VGA. */ -+ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); -+ -+ /* Disable pipes. */ -+ write32(pmmio + PIPECONF(0), 0); -+ write32(pmmio + PIPECONF(1), 0); -+ -+ write32(pmmio + INSTPM, 0x800); -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(pmmio + VGA0, 0x200074); -+ write32(pmmio + VGA1, 0x200074); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); -+ write32(pmmio + DSPCLK_GATE_D, 0); -+ write32(pmmio + FW_BLC, 0x03060106); -+ write32(pmmio + FW_BLC2, 0x00000306); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + 0x7041c, 0x0); -+ -+ write32(pmmio + DPLL_MD(0), 0x3); -+ write32(pmmio + DPLL_MD(1), 0x3); -+ write32(pmmio + DSPCNTR(1), 0x1000000); -+ write32(pmmio + PIPESRC(1), 0x027f01df); -+ -+ vga_misc_write(0x67); -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ // Disable screen memory to prevent garbage from appearing. -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(pmmio + PF_WIN_POS(0), 0); -+ -+ write32(pmmio + PIPESRC(0), (639 << 16) | 399); -+ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(pmmio + PFIT_CONTROL, 0x0); -+ -+ mdelay(1); -+ -+ write32(pmmio + FDI_RX_CTL(0), 0x00002040); -+ mdelay(1); -+ write32(pmmio + FDI_RX_CTL(0), 0x80002050); -+ write32(pmmio + FDI_TX_CTL(0), 0x00044000); -+ mdelay(1); -+ write32(pmmio + FDI_TX_CTL(0), 0x80044000); -+ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(pmmio + VGACNTRL, 0x0); -+ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1); -+ write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); -+ write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); -+ write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); -+ -+ /* Set up GTT. */ -+ -+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); -+ uma_size = 0; -+ if (!(reg16 & 2)) { -+ uma_size = decode_igd_memory_size((reg16 >> 4) & 7); -+ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); -+ } -+ -+ for (i = 0; i < (uma_size - 256) / 4; i++) -+ { -+ outl((i << 2) | 1, piobase); -+ outl(pphysbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ /* Clear interrupts. */ -+ write32(pmmio + DEIIR, 0xffffffff); -+ write32(pmmio + SDEIIR, 0xffffffff); -+ write32(pmmio + IIR, 0xffffffff); -+ write32(pmmio + IMR, 0xffffffff); -+ write32(pmmio + EIR, 0xffffffff); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ return 0; -+ -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should have a correct header */ -+static int vga_connected(u8 *pmmio) { -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(pmmio + GMBUS0); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - #endif - - static void gma_func0_init(struct device *dev) -@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev) - ); - - int err; -- err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ if (vga_connected(mmiobase)) -+ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ iobase, mmiobase, graphics_base); -+ else -+ err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch deleted file mode 100644 index 6f0272fd..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0007-i945-gma.c-generate-fake-VBT.patch +++ /dev/null @@ -1,43 +0,0 @@ -From 60cc2c4532f63a40486b7c4e891fb87fb6d4ab7f Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Wed, 7 Sep 2016 22:10:57 +0200 -Subject: [PATCH] i945/gma.c: generate fake VBT - -This generates a fake VBT for the Intel i945 graphic device. -i945 supports both the mobile chipset 945gm (calistoga) -and the desktop chipset 945gc (lakeport), -which is why a VBT with a different id string -needs to be created for each target. - -The VBT id string is obtained from the vbios blob in the following way: -"strings vbios.bin | grep VBT". - -Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/i945/gma.c | 9 +++++++++ - 1 file changed, 9 insertions(+) - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..f0944b9 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -433,6 +433,15 @@ static void gma_func0_init(struct device *dev) - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); -+ /* Linux relies on VBT for panel info. */ -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT CALISTOGA "); -+ } -+ if (CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC) { -+ generate_fake_intel_oprom(&conf->gfx, dev, -+ "$VBT LAKEPORT-G "); -+ } - #endif - } - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/INFO deleted file mode 100644 index 4f5931f9..00000000 --- a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/INFO +++ /dev/null @@ -1,7 +0,0 @@ -printf "lenovo/x60: use correct BLC_PWM_CTL value\n" -git am "../resources/libreboot/patch/misc/0003-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch" -# git fetch http://review.coreboot.org/coreboot refs/changes/24/10624/2 && git cherry-pick FETCH_HEAD - -printf "ec/lenovo/h8: permanently enable wifi/trackpoint/touchpad/bluetooth/wwan\n" -git am "../resources/libreboot/patch/misc/0005-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch" -# git fetch http://review.coreboot.org/coreboot refs/changes/58/7058/9 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-mb-intel-d945gclf-Disable-combined-mode-to-fix-SATA.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-mb-intel-d945gclf-Disable-combined-mode-to-fix-SATA.patch deleted file mode 100644 index 4c75bcd5..00000000 --- a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-mb-intel-d945gclf-Disable-combined-mode-to-fix-SATA.patch +++ /dev/null @@ -1,31 +0,0 @@ -From b6b2f9a9775029305f88f927f93e95046594f9b9 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Thu, 25 Aug 2016 09:24:15 +0200 -Subject: [PATCH] mb/intel/d945gclf: Disable combined mode to fix SATA - -Similarly to 2b2f465fcb1afe4960c613b8ca91e868c64592d4 -"mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA" -SATA must function in "plain" mode because it does not work in -"combined" mode. - -Tested on d945gclf - -Change-Id: I2e051a632a1341c4932cf86855006ae517dbf064 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> - -diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb -index 823a240..aa8c441 100644 ---- a/src/mainboard/intel/d945gclf/devicetree.cb -+++ b/src/mainboard/intel/d945gclf/devicetree.cb -@@ -45,7 +45,7 @@ chip northbridge/intel/i945 - register "gpi13_routing" = "1" - register "gpe0_en" = "0x20000601" - -- register "ide_legacy_combined" = "0x1" -+ register "ide_legacy_combined" = "0x0" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-move-DIV_ROUND-macros-to-commonlib.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-move-DIV_ROUND-macros-to-commonlib.patch deleted file mode 100644 index ea4db001..00000000 --- a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-move-DIV_ROUND-macros-to-commonlib.patch +++ /dev/null @@ -1,93 +0,0 @@ -From c82d4fa874322d70dec0e9d28c050e4c351de157 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Fri, 2 Sep 2016 23:14:54 +0200 -Subject: [PATCH 1/5] move DIV_ROUND macros to commonlib - -DIV_ROUND_CLOSEST and DIV_ROUND_UP are useful macros for other -architectures. This patch moves them from soc/nvidia/tegra/types.h -to commonlib/include/commonlib/helpers.h . - -Change-Id: I54521d9b197934cef8e352f9a5c4823015d85f01 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> - -diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h -index 0318e44..0b2395b 100644 ---- a/src/commonlib/include/commonlib/helpers.h -+++ b/src/commonlib/include/commonlib/helpers.h -@@ -34,6 +34,22 @@ - #define ABS(a) (((a) < 0) ? (-(a)) : (a)) - #define CEIL_DIV(a, b) (((a) + (b) - 1) / (b)) - #define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0) -+#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) -+/* -+ * Divide positive or negative dividend by positive divisor and round -+ * to closest integer. Result is undefined for negative divisors and -+ * for negative dividends if the divisor variable type is unsigned. -+ */ -+#define DIV_ROUND_CLOSEST(x, divisor)( \ -+{ \ -+ typeof(x) __x = x; \ -+ typeof(divisor) __d = divisor; \ -+ (((typeof(x))-1) > 0 || \ -+ ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ -+ (((__x) + ((__d) / 2)) / (__d)) : \ -+ (((__x) - ((__d) / 2)) / (__d)); \ -+} \ -+) - - /* Standard units. */ - #define KiB (1<<10) -diff --git a/src/soc/nvidia/tegra/types.h b/src/soc/nvidia/tegra/types.h -index dab474d..bfeebae 100644 ---- a/src/soc/nvidia/tegra/types.h -+++ b/src/soc/nvidia/tegra/types.h -@@ -51,22 +51,4 @@ - (type *)( (char *)__mptr - offsetof(type,member) );}) - #endif - --#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y)) -- --/* -- * Divide positive or negative dividend by positive divisor and round -- * to closest integer. Result is undefined for negative divisors and -- * for negative dividends if the divisor variable type is unsigned. -- */ --#define DIV_ROUND_CLOSEST(x, divisor)( \ --{ \ -- typeof(x) __x = x; \ -- typeof(divisor) __d = divisor; \ -- (((typeof(x))-1) > 0 || \ -- ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ -- (((__x) + ((__d) / 2)) / (__d)) : \ -- (((__x) - ((__d) / 2)) / (__d)); \ --} \ --) -- - #endif /* __TEGRA_MISC_TYPES_H__ */ -diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c -index e803e1b..b47c5c5 100644 ---- a/src/soc/nvidia/tegra210/addressmap.c -+++ b/src/soc/nvidia/tegra210/addressmap.c -@@ -23,6 +23,7 @@ - #include <stdlib.h> - #include <symbols.h> - #include <soc/nvidia/tegra/types.h> -+#include <commonlib/helpers.h> - - static uintptr_t tz_base_mib; - static const size_t tz_size_mib = CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB; -diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c -index 3b771c9..5504b4d 100644 ---- a/src/soc/nvidia/tegra210/dsi.c -+++ b/src/soc/nvidia/tegra210/dsi.c -@@ -32,6 +32,7 @@ - #include <soc/tegra_dsi.h> - #include <soc/mipi-phy.h> - #include "jdi_25x18_display/panel-jdi-lpm102a188a.h" -+#include <commonlib/helpers.h> - - struct tegra_mipi_device mipi_device_data[NUM_DSI]; - --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0002-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0002-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch deleted file mode 100644 index 6a8b9920..00000000 --- a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0002-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch +++ /dev/null @@ -1,171 +0,0 @@ -From f09ce5870025a98b6e497fd232adffde468c735a Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Fri, 2 Sep 2016 22:35:32 +0200 -Subject: [PATCH 2/5] i945/gma.c use latest linux code to calculate divisors. - -The code to compute n, m1, m2, p1 divisors is not correct in coreboot and -on some targets hits a working mode at lower refresh rate, which is why -display is working on some targets. -This patch also fixes reference frequency. - -This patch reuses linux code to correctly compute divisors. - -The result is that some previously not working displays (Lenovo T60 with -1024x786, 1400x1050, 2048x1536) - -TESTED on T60 with 1024x786. - -Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 02caa0a..d1d68d4 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -26,6 +26,8 @@ - #include <string.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> -+#include <commonlib/helpers.h> -+ - - #include "i945.h" - #include "chip.h" -@@ -43,7 +45,7 @@ - #define PGETBL_CTL 0x2020 - #define PGETBL_ENABLED 0x00000001 - --#define BASE_FREQUENCY 120000 -+#define BASE_FREQUENCY 100000 - - #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT - -@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - u8 edid_data[128]; - unsigned long temp; - int hpolarity, vpolarity; -- u32 candp1, candn; -- u32 best_delta = 0xffffffff; -+ u32 err_most = 0xffffffff; - u32 target_frequency; - u32 pixel_p1 = 1; -+ u32 pixel_p2; - u32 pixel_n = 1; - u32 pixel_m1 = 1; - u32 pixel_m2 = 1; -@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); - write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); - -- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock -- : (2 * mode->pixel_clock); -- -- /* Find suitable divisors. */ -- for (candp1 = 1; candp1 <= 8; candp1++) { -- for (candn = 5; candn <= 10; candn++) { -- u32 cur_frequency; -- u32 m; /* 77 - 131. */ -- u32 denom; /* 35 - 560. */ -- u32 current_delta; -- -- denom = candn * candp1 * 7; -- /* Doesnt overflow for up to -- 5000000 kHz = 5 GHz. */ -- m = (target_frequency * denom -- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; -- -- if (m < 77 || m > 131) -- continue; -- -- cur_frequency = (BASE_FREQUENCY * m) / denom; -- if (target_frequency > cur_frequency) -- current_delta = target_frequency - cur_frequency; -- else -- current_delta = cur_frequency - target_frequency; -- -- if (best_delta > current_delta) { -- best_delta = current_delta; -- pixel_n = candn; -- pixel_p1 = candp1; -- pixel_m2 = ((m + 3) % 5) + 7; -- pixel_m1 = (m - pixel_m2) / 5; -+ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; -+ target_frequency = mode->pixel_clock; -+ -+ /* Find suitable divisors, m1, m2, p1, n. */ -+ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ -+ /* should be closest to target frequency as possible */ -+ u32 candn, candm1, candm2, candp1; -+ for (candm1 = 8; candm1 <= 18; candm1++) { -+ for (candm2 = 3; candm2 <= 7; candm2++) { -+ for (candn = 1; candn <= 6; candn++) { -+ for (candp1 = 1; candp1 <= 8; candp1++) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * pixel_p2; -+ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if ((m < 70) || (m > 120)) -+ continue; -+ if (this_err < err_most) { -+ err_most = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } - } - } - } - -- if (best_delta == 0xffffffff) { -+ if (err_most == 0xffffffff) { - printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); - return -1; - } -@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", - pixel_n, pixel_m1, pixel_m2, pixel_p1); - printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n -- / (pixel_p1 * 7)); -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * pixel_p2)); - - #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) - write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS - | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); - write32(pmmio + FP0(1), -- ((pixel_n - 2) << 16) -- | ((pixel_m1 - 2) << 8) | pixel_m2); -+ (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | - DPLL_VCO_ENABLE | DPLLB_MODE_LVDS -@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (conf->gpu_lvds_use_spread_spectrum_clock - ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV - : 0) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + DPLL(1), - DPLL_VGA_MODE_DIS | -@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 - : DPLLB_LVDS_P2_CLOCK_DIV_14) - | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) -- | (pixel_p1 << 16) -- | (pixel_p1)); -+ | (0x10000 << pixel_p1)); - mdelay(1); - write32(pmmio + HTOTAL(1), - ((hactive + right_border + hblank - 1) << 16) --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0003-i945-gma.c-add-native-VGA-init.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0003-i945-gma.c-add-native-VGA-init.patch deleted file mode 100644 index 24a01442..00000000 --- a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0003-i945-gma.c-add-native-VGA-init.patch +++ /dev/null @@ -1,238 +0,0 @@ -From 09546d389511350d1b33b3c6bd9230de8bbbe317 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 5 Sep 2016 22:46:11 +0200 -Subject: [PATCH 3/5] i945/gma.c: add native VGA init - -This reuses the intel pineview native graphic initialization -to have output on the VGA connector of i945 devices. - -The behavior is the same as with the vbios blob. -It uses the external VGA display if it is connected. - -Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> - -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index d1d68d4..37674d7 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase) - return 0; - } - --static int intel_gma_init(struct northbridge_intel_i945_config *conf, -+static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, - unsigned int pphysbase, unsigned int piobase, - void *pmmio, unsigned int pgfx) - { -@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, - #endif - return 0; - } -+ -+static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf, -+ unsigned int pphysbase, unsigned int piobase, -+ void *pmmio, unsigned int pgfx) -+{ -+ int i; -+ u32 hactive, vactive; -+ u16 reg16; -+ u32 uma_size; -+ -+ printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n", -+ (u32)pmmio, piobase, pphysbase); -+ -+ gtt_setup(pmmio); -+ -+ /* Disable VGA. */ -+ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE); -+ -+ /* Disable pipes. */ -+ write32(pmmio + PIPECONF(0), 0); -+ write32(pmmio + PIPECONF(1), 0); -+ -+ write32(pmmio + INSTPM, 0x800); -+ -+ vga_gr_write(0x18, 0); -+ -+ write32(pmmio + VGA0, 0x200074); -+ write32(pmmio + VGA1, 0x200074); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN); -+ write32(pmmio + DSPCLK_GATE_D, 0); -+ write32(pmmio + FW_BLC, 0x03060106); -+ write32(pmmio + FW_BLC2, 0x00000306); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + 0x7041c, 0x0); -+ -+ write32(pmmio + DPLL_MD(0), 0x3); -+ write32(pmmio + DPLL_MD(1), 0x3); -+ write32(pmmio + DSPCNTR(1), 0x1000000); -+ write32(pmmio + PIPESRC(1), 0x027f01df); -+ -+ vga_misc_write(0x67); -+ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, -+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, -+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, -+ 0xff -+ }; -+ vga_cr_write(0x11, 0); -+ -+ for (i = 0; i <= 0x18; i++) -+ vga_cr_write(i, cr[i]); -+ -+ // Disable screen memory to prevent garbage from appearing. -+ vga_sr_write(1, vga_sr_read(1) | 0x20); -+ hactive = 640; -+ vactive = 400; -+ -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ mdelay(1); -+ write32(pmmio + DPLL(0), -+ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -+ | DPLL_VGA_MODE_DIS -+ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -+ | 0x400601 -+ ); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + HTOTAL(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HBLANK(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ write32(pmmio + HSYNC(0), -+ ((hactive - 1) << 16) -+ | (hactive - 1)); -+ -+ write32(pmmio + VTOTAL(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VBLANK(0), ((vactive - 1) << 16) -+ | (vactive - 1)); -+ write32(pmmio + VSYNC(0), -+ ((vactive - 1) << 16) -+ | (vactive - 1)); -+ -+ write32(pmmio + PF_WIN_POS(0), 0); -+ -+ write32(pmmio + PIPESRC(0), (639 << 16) | 399); -+ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(pmmio + PFIT_CONTROL, 0x0); -+ -+ mdelay(1); -+ -+ write32(pmmio + FDI_RX_CTL(0), 0x00002040); -+ mdelay(1); -+ write32(pmmio + FDI_RX_CTL(0), 0x80002050); -+ write32(pmmio + FDI_TX_CTL(0), 0x00044000); -+ mdelay(1); -+ write32(pmmio + FDI_TX_CTL(0), 0x80044000); -+ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); -+ -+ write32(pmmio + VGACNTRL, 0x0); -+ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -+ mdelay(1); -+ -+ write32(pmmio + ADPA, ADPA_DAC_ENABLE -+ | ADPA_PIPE_A_SELECT -+ | ADPA_USE_VGA_HVPOLARITY -+ | ADPA_VSYNC_CNTL_ENABLE -+ | ADPA_HSYNC_CNTL_ENABLE -+ | ADPA_DPMS_ON -+ ); -+ -+ write32(pmmio + DSPFW3, 0x7f3f00c1); -+ write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH); -+ write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5)); -+ write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9)); -+ -+ /* Set up GTT. */ -+ -+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC); -+ uma_size = 0; -+ if (!(reg16 & 2)) { -+ uma_size = decode_igd_memory_size((reg16 >> 4) & 7); -+ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); -+ } -+ -+ for (i = 0; i < (uma_size - 256) / 4; i++) -+ { -+ outl((i << 2) | 1, piobase); -+ outl(pphysbase + (i << 12) + 1, piobase + 4); -+ } -+ -+ /* Clear interrupts. */ -+ write32(pmmio + DEIIR, 0xffffffff); -+ write32(pmmio + SDEIIR, 0xffffffff); -+ write32(pmmio + IIR, 0xffffffff); -+ write32(pmmio + IMR, 0xffffffff); -+ write32(pmmio + EIR, 0xffffffff); -+ -+ vga_textmode_init(); -+ -+ /* Enable screen memory. */ -+ vga_sr_write(1, vga_sr_read(1) & ~0x20); -+ -+ return 0; -+ -+} -+ -+/* compare the header of the vga edid header */ -+/* if vga is not connected it should have a correct header */ -+static int vga_connected(u8 *pmmio) { -+ u8 vga_edid[128]; -+ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00}; -+ intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128); -+ intel_gmbus_stop(pmmio + GMBUS0); -+ for (int i = 0; i < 8; i++) { -+ if (vga_edid[i] != header[i]) { -+ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n"); -+ return 0; -+ } -+ } -+ printk(BIOS_SPEW, "VGA display connected\n"); -+ return 1; -+} -+ - #endif - - static void gma_func0_init(struct device *dev) -@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev) - ); - - int err; -- err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ if (vga_connected(mmiobase)) -+ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, -+ iobase, mmiobase, graphics_base); -+ else -+ err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, - iobase, mmiobase, graphics_base); - if (err == 0) - gfx_set_init_done(1); --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0004-mb-intel-d945gclf-Allow-use-of-native-graphic-init.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0004-mb-intel-d945gclf-Allow-use-of-native-graphic-init.patch deleted file mode 100644 index bda565f9..00000000 --- a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0004-mb-intel-d945gclf-Allow-use-of-native-graphic-init.patch +++ /dev/null @@ -1,40 +0,0 @@ -From d80a39744d7aad734e8d53f2b2d6cb6b5eeee834 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Tue, 6 Sep 2016 23:03:04 +0200 -Subject: [PATCH 4/5] mb/intel/d945gclf: Allow use of native graphic init - -Adds pci device id to native graphic init and add a Native graphic init -option in Kconfig. - -Change-Id: I136122daef70547830bcc87f568406be7162461f -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> - -diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig -index 429a304..a83e613 100644 ---- a/src/mainboard/intel/d945gclf/Kconfig -+++ b/src/mainboard/intel/d945gclf/Kconfig -@@ -29,6 +29,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy - select HAVE_ACPI_RESUME - select BOARD_ROMSIZE_KB_512 - select CHANNEL_XOR_RANDOMIZATION -+ select MAINBOARD_HAS_NATIVE_VGA_INIT -+ select INTEL_EDID - - config MAINBOARD_DIR - string -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index 37674d7..abe7dd6 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -716,7 +716,7 @@ static struct device_operations gma_func1_ops = { - .ops_pci = &gma_pci_ops, - }; - --static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0 }; -+static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0x2772, 0 }; - - static const struct pci_driver i945_gma_func0_driver __pci_driver = { - .ops = &gma_func0_ops, --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0005-i945-gma.c-Only-init-LVDS-if-it-is-present-on-the-de.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0005-i945-gma.c-Only-init-LVDS-if-it-is-present-on-the-de.patch deleted file mode 100644 index 3155ef90..00000000 --- a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0005-i945-gma.c-Only-init-LVDS-if-it-is-present-on-the-de.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 603387a7650a80c92f1064f17fbbf06d60c06f30 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Tue, 6 Sep 2016 23:53:32 +0200 -Subject: [PATCH 5/5] i945/gma.c: Only init LVDS if it is present on the device - -Some devices have no LVDS output but if no VGA is connected or -no edid can be found, it will try to init LVDS. - -This patch makes sure only devices that have an LVDS connector can use LVDS -graphic initialisation. - -Change-Id: Ie15631514535bab6c881c1f52e9edbfb8aaa5db7 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> - -diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig -index e653c08..8ba3d77 100644 ---- a/src/mainboard/apple/macbook21/Kconfig -+++ b/src/mainboard/apple/macbook21/Kconfig -@@ -35,6 +35,10 @@ config DCACHE_RAM_SIZE - hex - default 0x8000 - -+config HAS_LVDS -+ bool -+ default y -+ - if BOARD_APPLE_MACBOOK21 - - config MAINBOARD_PART_NUMBER -diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig -index ea68bed..e74b70c 100644 ---- a/src/mainboard/getac/p470/Kconfig -+++ b/src/mainboard/getac/p470/Kconfig -@@ -64,4 +64,8 @@ config VGA_BIOS_FILE - string - default "getac-pci8086,27a2.rom" - -+config HAS_LVDS -+ bool -+ default y -+ - endif # BOARD_GETAC_P470 -diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig -index 52eeda3..e5a7554 100644 ---- a/src/mainboard/lenovo/t60/Kconfig -+++ b/src/mainboard/lenovo/t60/Kconfig -@@ -54,4 +54,8 @@ config SEABIOS_PS2_TIMEOUT - int - default 3000 - -+config HAS_LVDS -+ bool -+ default y -+ - endif -diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig -index ab4b58e..152e6b2 100644 ---- a/src/mainboard/lenovo/x60/Kconfig -+++ b/src/mainboard/lenovo/x60/Kconfig -@@ -61,4 +61,8 @@ config SEABIOS_PS2_TIMEOUT - int - default 3000 - -+config HAS_LVDS -+ bool -+ default y -+ - endif -diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig -index 6e8d35b..ae7961f 100644 ---- a/src/northbridge/intel/i945/Kconfig -+++ b/src/northbridge/intel/i945/Kconfig -@@ -71,4 +71,8 @@ config CHECK_SLFRCS_ON_RESUME - On other boards the check always creates a false positive, - effectively making it impossible to resume. - -+config HAS_LVDS -+ bool -+ default n -+ - endif -diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c -index abe7dd6..be299f4 100644 ---- a/src/northbridge/intel/i945/gma.c -+++ b/src/northbridge/intel/i945/gma.c -@@ -611,7 +611,7 @@ static void gma_func0_init(struct device *dev) - ); - - int err; -- if (vga_connected(mmiobase)) -+ if (!CONFIG_HAS_LVDS || vga_connected(mmiobase)) - err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf, - iobase, mmiobase, graphics_base); - else --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch b/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch deleted file mode 100644 index 187dbc9a..00000000 --- a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0001-x4x-gma.c-Add-VESA-native-resolution-mode.patch +++ /dev/null @@ -1,415 +0,0 @@ -From 9659556d9edbba6c3530ed1d0630add30419210f Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Sun, 4 Sep 2016 16:01:11 +0200 -Subject: [PATCH 1/2] x4x/gma.c: Add VESA native resolution mode - -This patch implements native resolution, VESA mode, on the VGA output of -x4x. - -It relies on EDID to modeset, but has a fallback-mode (640 x 480 @ -60Hz) if this is no EDID could be found. This fallback mode only works in textmode -since in VESA mode some payloads (grub2) rely on VBE info, which is being -generated from an EDID. - -Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/northbridge/intel/x4x/gma.c | 282 ++++++++++++++++++++++++++++++++++------ - 1 file changed, 242 insertions(+), 40 deletions(-) - -diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c -index 2679026..118f98d 100644 ---- a/src/northbridge/intel/x4x/gma.c -+++ b/src/northbridge/intel/x4x/gma.c -@@ -26,24 +26,68 @@ - #include <cpu/x86/msr.h> - #include <cpu/x86/mtrr.h> - #include <kconfig.h> -+#include <commonlib/helpers.h> - - #include "drivers/intel/gma/i915_reg.h" - #include "chip.h" - #include "x4x.h" - #include <drivers/intel/gma/intel_bios.h> -+#include <drivers/intel/gma/edid.h> - #include <drivers/intel/gma/i915.h> - #include <pc80/vga.h> - #include <pc80/vga_io.h> - -+#define BASE_FREQUENCY 96000 -+ -+static u8 edid_is_null(u8 *edid, u32 edid_size) -+{ -+ u32 i; -+ for (i = 0; i < edid_size; i++) { -+ if (*(edid + i) != 0) -+ return 0; -+ } -+ return 1; -+} - static void intel_gma_init(const struct northbridge_intel_x4x_config *info, -- u8 *mmio) -+ u8 *mmio, u32 physbase, u16 piobase, u32 lfb) - { - -+ - int i; -- u32 hactive, vactive; -+ u8 edid_data[128]; -+ struct edid edid; -+ struct edid_mode *mode; -+ u8 edid_not_found; -+ -+ /* Initialise mode variables for 640 x 480 @ 60Hz */ -+ u32 hactive = 640, vactive = 480; -+ u32 right_border = 0, bottom_border = 0; -+ int hpolarity = 0, vpolarity = 0; -+ u32 hsync = 96, vsync = 2; -+ u32 hblank = 160, vblank = 45; -+ u32 hfront_porch = 16, vfront_porch = 10; -+ u32 target_frequency = 25175; -+ -+ u32 err_most = 0xffffffff; -+ u32 pixel_p1 = 1; -+ u32 pixel_n = 1; -+ u32 pixel_m1 = 1; -+ u32 pixel_m2 = 1; -+ u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; -+ u32 data_m1; -+ u32 data_n1 = 0x00800000; -+ u32 link_m1; -+ u32 link_n1 = 0x00040000; -+ - - vga_gr_write(0x18, 0); - -+ /* Set up GTT */ -+ for (i = 0; i < 0x1000; i++) { -+ outl((i << 2) | 1, piobase); -+ outl(physbase + (i << 12) + 1, piobase + 4); -+ } -+ - write32(mmio + VGA0, 0x31108); - write32(mmio + VGA1, 0x31406); - -@@ -73,107 +117,258 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, - for (i = 0; i <= 0x18; i++) - vga_cr_write(i, cr[i]); - -+ udelay(1); -+ -+ intel_gmbus_read_edid(mmio + GMBUS0, 2, 0x50, edid_data, 128); -+ intel_gmbus_stop(mmio + GMBUS0); -+ decode_edid(edid_data, -+ sizeof(edid_data), &edid); -+ mode = &edid.mode; -+ -+ - /* Disable screen memory to prevent garbage from appearing. */ - vga_sr_write(1, vga_sr_read(1) | 0x20); - -- hactive = 640; -- vactive = 400; -+ edid_not_found = edid_is_null(edid_data, sizeof(edid_data)); -+ if (!edid_not_found) { -+ printk(BIOS_DEBUG, "EDID is not null"); -+ hactive = edid.x_resolution; -+ vactive = edid.y_resolution; -+ right_border = mode->hborder; -+ bottom_border = mode->vborder; -+ hpolarity = (mode->phsync == '-'); -+ vpolarity = (mode->pvsync == '-'); -+ vsync = mode->vspw; -+ hsync = mode->hspw; -+ vblank = mode->vbl; -+ hblank = mode->hbl; -+ hfront_porch = mode->hso; -+ vfront_porch = mode->vso; -+ target_frequency = mode->pixel_clock; -+ } else -+ printk(BIOS_DEBUG, "EDID is null, using 640 x 480 @ 60Hz mode"); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ vga_sr_write(1, 1); -+ vga_sr_write(0x2, 0xf); -+ vga_sr_write(0x3, 0x0); -+ vga_sr_write(0x4, 0xe); -+ vga_gr_write(0, 0x0); -+ vga_gr_write(1, 0x0); -+ vga_gr_write(2, 0x0); -+ vga_gr_write(3, 0x0); -+ vga_gr_write(4, 0x0); -+ vga_gr_write(5, 0x0); -+ vga_gr_write(6, 0x5); -+ vga_gr_write(7, 0xf); -+ vga_gr_write(0x10, 0x1); -+ vga_gr_write(0x11, 0); -+ -+ edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; -+ -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ write32(mmio + DSPADDR(0), 0); -+ write32(mmio + DSPSTRIDE(0), edid.bytes_per_line); -+ write32(mmio + DSPSURF(0), 0); -+ for (i = 0; i < 0x100; i++) -+ write32(mmio + LGC_PALETTE(0) + 4 * i, i * 0x010101); -+ } else { -+ vga_textmode_init(); -+ } -+ -+ u32 candn, candm1, candm2, candp1; -+ for (candn = 1; candn <= 4; candn++) { -+ for (candm1 = 23; candm1 >= 16; candm1--) { -+ for (candm2 = 11; candm2 >= 5; candm2--) { -+ for (candp1 = 8; candp1 >= 1; candp1--) { -+ u32 m = 5 * (candm1 + 2) + (candm2 + 2); -+ u32 p = candp1 * 10; /* 10 == p2 */ -+ u32 vco = DIV_ROUND_CLOSEST( -+ BASE_FREQUENCY * m, candn + 2); -+ u32 dot = DIV_ROUND_CLOSEST(vco, p); -+ u32 this_err = ABS(dot - target_frequency); -+ if (this_err < err_most) { -+ err_most = this_err; -+ pixel_n = candn; -+ pixel_m1 = candm1; -+ pixel_m2 = candm2; -+ pixel_p1 = candp1; -+ } -+ } -+ } -+ } -+ } -+ -+ if (err_most == 0xffffffff) { -+ printk(BIOS_ERR, "Couldn't find GFX clock divisors\n"); -+ return; -+ } -+ -+ link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; -+ data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) -+ / (link_frequency * 8 * 4); -+ -+ printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", -+ hactive, vactive); -+ printk(BIOS_DEBUG, "Borders %d x %d\n", -+ right_border, bottom_border); -+ printk(BIOS_DEBUG, "Blank %d x %d\n", -+ hblank, vblank); -+ printk(BIOS_DEBUG, "Sync %d x %d\n", -+ hsync, vsync); -+ printk(BIOS_DEBUG, "Front porch %d x %d\n", -+ hfront_porch, vfront_porch); -+ printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock -+ ? "Spread spectrum clock\n" : "DREF clock\n")); -+ printk(BIOS_DEBUG, "Polarities %d, %d\n", -+ hpolarity, vpolarity); -+ printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", -+ data_m1, data_n1); -+ printk(BIOS_DEBUG, "Link frequency %d kHz\n", -+ link_frequency); -+ printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", -+ link_m1, link_n1); -+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", -+ pixel_n, pixel_m1, pixel_m2, pixel_p1); -+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n", -+ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / -+ (pixel_n + 2) / (pixel_p1 * 10)); - - mdelay(1); -- write32(mmio + FP0(0), 0x31108); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + FP0(0), (pixel_n << 16) -+ | (pixel_m1 << 8) | pixel_m2); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); -+ - mdelay(1); -- write32(mmio + DPLL(0), -- DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL -- | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 -- | 0x10601 -- ); -+ write32(mmio + DPLL(0), DPLL_VCO_ENABLE -+ | DPLL_VGA_MODE_DIS | DPLLB_MODE_DAC_SERIAL -+ | (0x10000 << (pixel_p1 - 1)) -+ | (6 << 9)); - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - - write32(mmio + HTOTAL(0), -- ((hactive - 1) << 16) -+ ((hactive + right_border + hblank - 1) << 16) - | (hactive - 1)); - write32(mmio + HBLANK(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hblank - 1) << 16) -+ | (hactive + right_border - 1)); - write32(mmio + HSYNC(0), -- ((hactive - 1) << 16) -- | (hactive - 1)); -+ ((hactive + right_border + hfront_porch + hsync - 1) << 16) -+ | (hactive + right_border + hfront_porch - 1)); - -- write32(mmio + VTOTAL(0), ((vactive - 1) << 16) -- | (vactive - 1)); -- write32(mmio + VBLANK(0), ((vactive - 1) << 16) -+ write32(mmio + VTOTAL(0), ((vactive + bottom_border + vblank - 1) << 16) - | (vactive - 1)); -+ write32(mmio + VBLANK(0), ((vactive + bottom_border + vblank - 1) << 16) -+ | (vactive + bottom_border - 1)); - write32(mmio + VSYNC(0), -- ((vactive - 1) << 16) -- | (vactive - 1)); -+ ((vactive + bottom_border + vfront_porch + vsync - 1) << 16) -+ | (vactive + bottom_border + vfront_porch - 1)); - - write32(mmio + PIPECONF(0), PIPECONF_DISABLE); - - write32(mmio + PF_WIN_POS(0), 0); -- -- write32(mmio + PIPESRC(0), (639 << 16) | 399); -- write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); -- write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -- write32(mmio + PFIT_CONTROL, 0xa0000000); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + PIPESRC(0), ((hactive - 1) << 16) -+ | (vactive - 1)); -+ write32(mmio + PF_CTL(0), 0); -+ write32(mmio + PF_WIN_SZ(0), 0); -+ write32(mmio + PFIT_CONTROL, 0); -+ } else { -+ write32(mmio + PIPESRC(0), (639 << 16) | 399); -+ write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); -+ write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); -+ write32(mmio + PFIT_CONTROL, 0x80000000); -+ } - - mdelay(1); - -+ write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); -+ write32(mmio + PIPE_DATA_N1(0), data_n1); -+ write32(mmio + PIPE_LINK_M1(0), link_m1); -+ write32(mmio + PIPE_LINK_N1(0), link_n1); -+ - write32(mmio + 0x000f000c, 0x00002040); - mdelay(1); - write32(mmio + 0x000f000c, 0x00002050); - write32(mmio + 0x00060100, 0x00044000); - mdelay(1); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6); -+ write32(mmio + 0x000f0008, 0x00000040); -+ write32(mmio + 0x000f000c, 0x00022050); -+ write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE - | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); - -- write32(mmio + VGACNTRL, 0x0); -- write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); -- mdelay(1); -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -+ write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE -+ | DISPPLANE_BGRX888); -+ mdelay(1); -+ } else { -+ write32(mmio + VGACNTRL, 0xc4008e); -+ } - - write32(mmio + ADPA, ADPA_DAC_ENABLE - | ADPA_PIPE_A_SELECT - | ADPA_CRT_HOTPLUG_MONITOR_COLOR - | ADPA_CRT_HOTPLUG_ENABLE -- | ADPA_USE_VGA_HVPOLARITY - | ADPA_VSYNC_CNTL_ENABLE - | ADPA_HSYNC_CNTL_ENABLE - | ADPA_DPMS_ON -- ); -+ | (vpolarity ? ADPA_VSYNC_ACTIVE_LOW : -+ ADPA_VSYNC_ACTIVE_HIGH) -+ | (hpolarity ? ADPA_HSYNC_ACTIVE_LOW : -+ ADPA_HSYNC_ACTIVE_HIGH)); - -- vga_textmode_init(); -+ write32(mmio + PP_CONTROL, PANEL_POWER_ON | PANEL_POWER_RESET); - -- /* Enable screen memory. */ -+ /* Enable screen memory. */ - vga_sr_write(1, vga_sr_read(1) & ~0x20); - - /* Clear interrupts. */ - write32(mmio + DEIIR, 0xffffffff); - write32(mmio + SDEIIR, 0xffffffff); -+ -+ if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { -+ memset((void *) lfb, 0, -+ hactive * vactive * 4); -+ set_vbe_mode_info_valid(&edid, lfb); -+ } - } - - static void native_init(struct device *dev) - { -+ struct resource *lfb_res; -+ struct resource *pio_res; -+ u32 physbase; - struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); - struct northbridge_intel_x4x_config *conf = dev->chip_info; - -+ lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); -+ pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); -+ physbase = pci_read_config32(dev, 0x5c) & ~0xf; -+ - if (gtt_res && gtt_res->base) { - printk(BIOS_SPEW, - "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); -- intel_gma_init(conf, res2mmio(gtt_res, 0, 0)); -+ intel_gma_init(conf, res2mmio(gtt_res, 0, 0), -+ physbase, pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ -@@ -182,6 +377,7 @@ static void native_init(struct device *dev) - - static void gma_func0_init(struct device *dev) - { -+ u16 reg16; - u32 reg32; - - /* IGD needs to be Bus Master */ -@@ -189,6 +385,12 @@ static void gma_func0_init(struct device *dev) - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); - -+ /* configure GMBUSFREQ */ -+ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc); -+ reg16 &= ~0x1ff; -+ reg16 |= 0xbc; -+ pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x2,0)), 0xcc, reg16); -+ - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) - native_init(dev); - else --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch b/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch deleted file mode 100644 index d579df55..00000000 --- a/resources/libreboot/patch/coreboot/55a54f662e2e793306dc7003afbcb82b49db0a8c/grub/ga-g41m-es2l/0002-gigabyte-ga-g41m-es2l-add-VESA-mode-to-Kconfig.patch +++ /dev/null @@ -1,30 +0,0 @@ -From f9a84edfc672424c9dcaa0a71ad0751c2355c3d0 Mon Sep 17 00:00:00 2001 -From: Arthur Heymans <arthur@aheymans.xyz> -Date: Mon, 5 Sep 2016 12:07:57 +0200 -Subject: [PATCH 2/2] gigabyte/ga-g41m-es2l: add VESA mode to Kconfig - -This patch adds MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG to the -gigabyte/ga-g41m-es2l Kconfig to allow selecting between textmode and -vesamode in menuconfig. - -Change-Id: I84b61118fa0419d49d2498b66029711cdce97576 -Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> ---- - src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig -index 6452f4d..281d498 100644 ---- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig -+++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig -@@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS - select BOARD_ROMSIZE_KB_1024 - select INTEL_EDID - select MAINBOARD_HAS_NATIVE_VGA_INIT -+ select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG - select PCIEXP_ASPM - select PCIEXP_CLK_PM - select PCIEXP_L1_SUB_STATE --- -2.9.3 - diff --git a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch deleted file mode 100644 index 2fde12f4..00000000 --- a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Tue, 8 Mar 2016 07:21:33 +0000 -Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates - -There were build issues in libreboot. We don't use microcode updates anyway. -When selecting no microcode updates in menuconfig, build failed because -coreboot for these boards was still trying to add microcode. ---- - src/cpu/Makefile.inc | 34 +------------------------- - src/cpu/amd/family_10h-family_15h/Kconfig | 1 - - src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- - 3 files changed, 1 insertion(+), 44 deletions(-) - -diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc -index 046c418..ef0e236 100644 ---- a/src/cpu/Makefile.inc -+++ b/src/cpu/Makefile.inc -@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) - ## Rules for building the microcode blob in CBFS - ################################################################################ - --ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) --cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin --endif -- --ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) --cbfs-files-y += cpu_microcode_blob.bin --cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin -- --$(objgenerated)/microcode.bin: -- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" -- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) --endif -- --# We just mash all microcode binaries together into one binary to rule them all. --# This approach assumes that the microcode binaries are properly padded, and --# their headers specify the correct size. This works fairly well on isolatied --# updates, such as Intel and some AMD microcode, but won't work very well if the --# updates are wrapped in a container, like AMD's microcode update container. If --# there is only one microcode binary (i.e. one container), then we don't have --# this issue, and this rule will continue to work. --$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) -- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" -- @echo $(cpu_microcode_bins) -- cat /dev/null $+ > $@ -- --cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin --cpu_microcode_blob.bin-type := microcode -- --ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) --cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) --else --cpu_microcode_blob.bin-align := 16 --endif -+# What? Nope! We don't do that in libreboot. -diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig -index 14ab1cd..3f873a1 100644 ---- a/src/cpu/amd/family_10h-family_15h/Kconfig -+++ b/src/cpu/amd/family_10h-family_15h/Kconfig -@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX - select UDELAY_LAPIC - select HAVE_MONOTONIC_TIMER - select SUPPORT_CPU_UCODE_IN_CBFS -- select CPU_MICROCODE_MULTIPLE_FILES - - if CPU_AMD_MODEL_10XXX - -diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc -index f10f732..a295475 100644 ---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc -+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc -@@ -9,13 +9,3 @@ romstage-y += ram_calc.c - ramstage-y += ram_calc.c - ramstage-y += monotonic_timer.c - ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c -- --# Microcode for Family 10h, 11h, 12h, and 14h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin --microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin --microcode_amd.bin-type := microcode -- --# Microcode for Family 15h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-type := microcode --- -1.9.1 - diff --git a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch deleted file mode 100644 index 2fde12f4..00000000 --- a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/grub/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Tue, 8 Mar 2016 07:21:33 +0000 -Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates - -There were build issues in libreboot. We don't use microcode updates anyway. -When selecting no microcode updates in menuconfig, build failed because -coreboot for these boards was still trying to add microcode. ---- - src/cpu/Makefile.inc | 34 +------------------------- - src/cpu/amd/family_10h-family_15h/Kconfig | 1 - - src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- - 3 files changed, 1 insertion(+), 44 deletions(-) - -diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc -index 046c418..ef0e236 100644 ---- a/src/cpu/Makefile.inc -+++ b/src/cpu/Makefile.inc -@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) - ## Rules for building the microcode blob in CBFS - ################################################################################ - --ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) --cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin --endif -- --ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) --cbfs-files-y += cpu_microcode_blob.bin --cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin -- --$(objgenerated)/microcode.bin: -- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" -- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) --endif -- --# We just mash all microcode binaries together into one binary to rule them all. --# This approach assumes that the microcode binaries are properly padded, and --# their headers specify the correct size. This works fairly well on isolatied --# updates, such as Intel and some AMD microcode, but won't work very well if the --# updates are wrapped in a container, like AMD's microcode update container. If --# there is only one microcode binary (i.e. one container), then we don't have --# this issue, and this rule will continue to work. --$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) -- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" -- @echo $(cpu_microcode_bins) -- cat /dev/null $+ > $@ -- --cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin --cpu_microcode_blob.bin-type := microcode -- --ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) --cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) --else --cpu_microcode_blob.bin-align := 16 --endif -+# What? Nope! We don't do that in libreboot. -diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig -index 14ab1cd..3f873a1 100644 ---- a/src/cpu/amd/family_10h-family_15h/Kconfig -+++ b/src/cpu/amd/family_10h-family_15h/Kconfig -@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX - select UDELAY_LAPIC - select HAVE_MONOTONIC_TIMER - select SUPPORT_CPU_UCODE_IN_CBFS -- select CPU_MICROCODE_MULTIPLE_FILES - - if CPU_AMD_MODEL_10XXX - -diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc -index f10f732..a295475 100644 ---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc -+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc -@@ -9,13 +9,3 @@ romstage-y += ram_calc.c - ramstage-y += ram_calc.c - ramstage-y += monotonic_timer.c - ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c -- --# Microcode for Family 10h, 11h, 12h, and 14h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin --microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin --microcode_amd.bin-type := microcode -- --# Microcode for Family 15h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-type := microcode --- -1.9.1 - diff --git a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch deleted file mode 100644 index 2fde12f4..00000000 --- a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kcma-d8/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Tue, 8 Mar 2016 07:21:33 +0000 -Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates - -There were build issues in libreboot. We don't use microcode updates anyway. -When selecting no microcode updates in menuconfig, build failed because -coreboot for these boards was still trying to add microcode. ---- - src/cpu/Makefile.inc | 34 +------------------------- - src/cpu/amd/family_10h-family_15h/Kconfig | 1 - - src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- - 3 files changed, 1 insertion(+), 44 deletions(-) - -diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc -index 046c418..ef0e236 100644 ---- a/src/cpu/Makefile.inc -+++ b/src/cpu/Makefile.inc -@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) - ## Rules for building the microcode blob in CBFS - ################################################################################ - --ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) --cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin --endif -- --ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) --cbfs-files-y += cpu_microcode_blob.bin --cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin -- --$(objgenerated)/microcode.bin: -- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" -- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) --endif -- --# We just mash all microcode binaries together into one binary to rule them all. --# This approach assumes that the microcode binaries are properly padded, and --# their headers specify the correct size. This works fairly well on isolatied --# updates, such as Intel and some AMD microcode, but won't work very well if the --# updates are wrapped in a container, like AMD's microcode update container. If --# there is only one microcode binary (i.e. one container), then we don't have --# this issue, and this rule will continue to work. --$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) -- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" -- @echo $(cpu_microcode_bins) -- cat /dev/null $+ > $@ -- --cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin --cpu_microcode_blob.bin-type := microcode -- --ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) --cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) --else --cpu_microcode_blob.bin-align := 16 --endif -+# What? Nope! We don't do that in libreboot. -diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig -index 14ab1cd..3f873a1 100644 ---- a/src/cpu/amd/family_10h-family_15h/Kconfig -+++ b/src/cpu/amd/family_10h-family_15h/Kconfig -@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX - select UDELAY_LAPIC - select HAVE_MONOTONIC_TIMER - select SUPPORT_CPU_UCODE_IN_CBFS -- select CPU_MICROCODE_MULTIPLE_FILES - - if CPU_AMD_MODEL_10XXX - -diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc -index f10f732..a295475 100644 ---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc -+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc -@@ -9,13 +9,3 @@ romstage-y += ram_calc.c - ramstage-y += ram_calc.c - ramstage-y += monotonic_timer.c - ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c -- --# Microcode for Family 10h, 11h, 12h, and 14h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin --microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin --microcode_amd.bin-type := microcode -- --# Microcode for Family 15h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-type := microcode --- -1.9.1 - diff --git a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch deleted file mode 100644 index 2fde12f4..00000000 --- a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kfsn4-dre/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Tue, 8 Mar 2016 07:21:33 +0000 -Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates - -There were build issues in libreboot. We don't use microcode updates anyway. -When selecting no microcode updates in menuconfig, build failed because -coreboot for these boards was still trying to add microcode. ---- - src/cpu/Makefile.inc | 34 +------------------------- - src/cpu/amd/family_10h-family_15h/Kconfig | 1 - - src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- - 3 files changed, 1 insertion(+), 44 deletions(-) - -diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc -index 046c418..ef0e236 100644 ---- a/src/cpu/Makefile.inc -+++ b/src/cpu/Makefile.inc -@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) - ## Rules for building the microcode blob in CBFS - ################################################################################ - --ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) --cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin --endif -- --ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) --cbfs-files-y += cpu_microcode_blob.bin --cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin -- --$(objgenerated)/microcode.bin: -- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" -- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) --endif -- --# We just mash all microcode binaries together into one binary to rule them all. --# This approach assumes that the microcode binaries are properly padded, and --# their headers specify the correct size. This works fairly well on isolatied --# updates, such as Intel and some AMD microcode, but won't work very well if the --# updates are wrapped in a container, like AMD's microcode update container. If --# there is only one microcode binary (i.e. one container), then we don't have --# this issue, and this rule will continue to work. --$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) -- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" -- @echo $(cpu_microcode_bins) -- cat /dev/null $+ > $@ -- --cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin --cpu_microcode_blob.bin-type := microcode -- --ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) --cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) --else --cpu_microcode_blob.bin-align := 16 --endif -+# What? Nope! We don't do that in libreboot. -diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig -index 14ab1cd..3f873a1 100644 ---- a/src/cpu/amd/family_10h-family_15h/Kconfig -+++ b/src/cpu/amd/family_10h-family_15h/Kconfig -@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX - select UDELAY_LAPIC - select HAVE_MONOTONIC_TIMER - select SUPPORT_CPU_UCODE_IN_CBFS -- select CPU_MICROCODE_MULTIPLE_FILES - - if CPU_AMD_MODEL_10XXX - -diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc -index f10f732..a295475 100644 ---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc -+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc -@@ -9,13 +9,3 @@ romstage-y += ram_calc.c - ramstage-y += ram_calc.c - ramstage-y += monotonic_timer.c - ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c -- --# Microcode for Family 10h, 11h, 12h, and 14h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin --microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin --microcode_amd.bin-type := microcode -- --# Microcode for Family 15h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-type := microcode --- -1.9.1 - diff --git a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch b/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch deleted file mode 100644 index 2fde12f4..00000000 --- a/resources/libreboot/patch/coreboot/eee0e229764e965996479d7eb07e6086176b8bf0/seabios/kgpe-d16/0001-HOTFIX-AMD-fam10h-fam15h-don-t-use-microcode-updates.patch +++ /dev/null @@ -1,89 +0,0 @@ -From 388f9dbe66f6834013d478eeffe154d59ca6c239 Mon Sep 17 00:00:00 2001 -From: Leah Rowe <info@minifree.org> -Date: Tue, 8 Mar 2016 07:21:33 +0000 -Subject: [PATCH] HOTFIX: AMD fam10h/fam15h: don't use microcode updates - -There were build issues in libreboot. We don't use microcode updates anyway. -When selecting no microcode updates in menuconfig, build failed because -coreboot for these boards was still trying to add microcode. ---- - src/cpu/Makefile.inc | 34 +------------------------- - src/cpu/amd/family_10h-family_15h/Kconfig | 1 - - src/cpu/amd/family_10h-family_15h/Makefile.inc | 10 -------- - 3 files changed, 1 insertion(+), 44 deletions(-) - -diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc -index 046c418..ef0e236 100644 ---- a/src/cpu/Makefile.inc -+++ b/src/cpu/Makefile.inc -@@ -17,36 +17,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32)) - ## Rules for building the microcode blob in CBFS - ################################################################################ - --ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y) --cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += cpu_microcode_blob.bin --endif -- --ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) --cbfs-files-y += cpu_microcode_blob.bin --cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin -- --$(objgenerated)/microcode.bin: -- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\"" -- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES) --endif -- --# We just mash all microcode binaries together into one binary to rule them all. --# This approach assumes that the microcode binaries are properly padded, and --# their headers specify the correct size. This works fairly well on isolatied --# updates, such as Intel and some AMD microcode, but won't work very well if the --# updates are wrapped in a container, like AMD's microcode update container. If --# there is only one microcode binary (i.e. one container), then we don't have --# this issue, and this rule will continue to work. --$(obj)/cpu_microcode_blob.bin: $$(cpu_microcode_bins) -- @printf " MICROCODE $(subst $(obj)/,,$(@))\n" -- @echo $(cpu_microcode_bins) -- cat /dev/null $+ > $@ -- --cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin --cpu_microcode_blob.bin-type := microcode -- --ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),) --cpu_microcode_blob.bin-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC) --else --cpu_microcode_blob.bin-align := 16 --endif -+# What? Nope! We don't do that in libreboot. -diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig -index 14ab1cd..3f873a1 100644 ---- a/src/cpu/amd/family_10h-family_15h/Kconfig -+++ b/src/cpu/amd/family_10h-family_15h/Kconfig -@@ -11,7 +11,6 @@ config CPU_AMD_MODEL_10XXX - select UDELAY_LAPIC - select HAVE_MONOTONIC_TIMER - select SUPPORT_CPU_UCODE_IN_CBFS -- select CPU_MICROCODE_MULTIPLE_FILES - - if CPU_AMD_MODEL_10XXX - -diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc -index f10f732..a295475 100644 ---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc -+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc -@@ -9,13 +9,3 @@ romstage-y += ram_calc.c - ramstage-y += ram_calc.c - ramstage-y += monotonic_timer.c - ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c -- --# Microcode for Family 10h, 11h, 12h, and 14h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd.bin --microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin --microcode_amd.bin-type := microcode -- --# Microcode for Family 15h --cbfs-files-$(CONFIG_CPU_MICROCODE_MULTIPLE_FILES) += microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin --microcode_amd_fam15h.bin-type := microcode --- -1.9.1 - |