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| author | Francis Rowe <info@gluglug.org.uk> | 2015-10-19 00:12:53 +0100 |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2015-10-19 02:32:36 +0100 |
| commit | 0622df6194dbb1b2120743c0fd1cc5e72c380128 (patch) | |
| tree | 4c858b8c5667fe001a9907ae0578b4ec28a8f513 /resources/libreboot/patch/kgpe-d16/0036-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch | |
| parent | 5999dba5f71f1c05040a551d2420ab8c7f3a9da4 (diff) | |
| download | librebootfr-0622df6194dbb1b2120743c0fd1cc5e72c380128.tar.gz librebootfr-0622df6194dbb1b2120743c0fd1cc5e72c380128.zip | |
KGPE-D16: update patch set (also update coreboot and vboot)
Also contains other fixes from coreboot, like:
* 551cff0 Derive lvds_dual_channel from EDID timings.
^ makes single/dual channel LVDS selection on GM45 automatic
* 26fc544 lenovo/t60: Enable native intel gfx init.
^ was being maintained in libreboot, now upstreamed so not needed
Framebuffer mode was disabled for the KGPE-D16, because only
text-mode works at the moment.
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0036-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0036-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0036-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch b/resources/libreboot/patch/kgpe-d16/0036-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch new file mode 100644 index 00000000..cd1a6136 --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0036-amdmct-mct_ddr3-Disable-Fam10h-specific-MTRR-setup-o.patch @@ -0,0 +1,38 @@ +From fd67f1513d362a0a02f999b632c62b7b5c074a50 Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Mon, 1 Jun 2015 20:35:42 -0500 +Subject: [PATCH 036/139] amdmct/mct_ddr3: Disable Fam10h-specific MTRR setup + on Fam15h + +Change-Id: I5c12b5ef8564402601634e9f3528bbf9303e0b33 +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 +++++++----- + 1 file changed, 7 insertions(+), 5 deletions(-) + +diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +index 74066b1..4677c73 100644 +--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c ++++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +@@ -1842,11 +1842,13 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, + + if (nv_DQSTrainCTL) { + mctHookBeforeAnyTraining(pMCTstat, pDCTstatA); +- /* TODO: should be in mctHookBeforeAnyTraining */ +- _WRMSR(0x26C, 0x04040404, 0x04040404); +- _WRMSR(0x26D, 0x04040404, 0x04040404); +- _WRMSR(0x26E, 0x04040404, 0x04040404); +- _WRMSR(0x26F, 0x04040404, 0x04040404); ++ if (!is_fam15h()) { ++ /* TODO: should be in mctHookBeforeAnyTraining */ ++ _WRMSR(0x26C, 0x04040404, 0x04040404); ++ _WRMSR(0x26D, 0x04040404, 0x04040404); ++ _WRMSR(0x26E, 0x04040404, 0x04040404); ++ _WRMSR(0x26F, 0x04040404, 0x04040404); ++ } + mct_WriteLevelization_HW(pMCTstat, pDCTstatA, FirstPass); + + if (is_fam15h()) { +-- +1.9.1 + |