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| author | Francis Rowe <info@gluglug.org.uk> | 2015-11-06 07:45:49 +0000 |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2015-11-06 08:01:51 +0000 |
| commit | 60453ff2cbd1befe24959fba1d24f734406444e3 (patch) | |
| tree | 74a6080455b2b00184fbc4a00503188032773986 /resources/libreboot/patch/kgpe-d16/0061-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch | |
| parent | 51f5487e7d2c8809bdc7690fe26948064257b34d (diff) | |
| download | librebootfr-60453ff2cbd1befe24959fba1d24f734406444e3.tar.gz librebootfr-60453ff2cbd1befe24959fba1d24f734406444e3.zip | |
Update coreboot to new version (use latest stable kgpe-d16 tree)
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0061-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0061-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0061-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch b/resources/libreboot/patch/kgpe-d16/0061-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch new file mode 100644 index 00000000..fa540298 --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0061-southbridge-amd-sb700-Add-option-to-disable-SATA-ALP.patch @@ -0,0 +1,84 @@ +From 59fece51e2abd69a5cf5829096d4f2b55ad994bf Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Thu, 18 Jun 2015 11:48:02 -0500 +Subject: [PATCH 061/143] southbridge/amd/sb700: Add option to disable SATA + ALPM + +Change-Id: I88055cbb4df4d7ba811cef7056c0a6ca2612fcb0 +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/mainboard/asus/kgpe-d16/cmos.default | 1 + + src/mainboard/asus/kgpe-d16/cmos.layout | 7 ++++--- + src/southbridge/amd/sb700/sata.c | 12 ++++++++++++ + 3 files changed, 17 insertions(+), 3 deletions(-) + +diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default +index 73f2a38..9b30b00 100644 +--- a/src/mainboard/asus/kgpe-d16/cmos.default ++++ b/src/mainboard/asus/kgpe-d16/cmos.default +@@ -18,6 +18,7 @@ interleave_memory_channels = Enable + cpu_c_states = Enable + cpu_cc6_state = Enable + sata_ahci_mode = Enable ++sata_alpm = Disable + maximum_p_state_limit = 0xf + ieee1394 = Enable + power_on_after_fail = On +diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout +index 068eaf4..f705af2 100644 +--- a/src/mainboard/asus/kgpe-d16/cmos.layout ++++ b/src/mainboard/asus/kgpe-d16/cmos.layout +@@ -46,9 +46,10 @@ entries + 465 1 e 1 cpu_c_states + 466 1 e 1 cpu_cc6_state + 467 1 e 1 sata_ahci_mode +-468 4 h 0 maximum_p_state_limit +-472 2 e 13 dimm_spd_checksum +-474 1 r 0 allow_spd_nvram_cache_restore ++468 1 e 1 sata_alpm ++469 4 h 0 maximum_p_state_limit ++473 2 e 13 dimm_spd_checksum ++475 1 r 0 allow_spd_nvram_cache_restore + 477 1 e 1 ieee1394 + 728 256 h 0 user_data + 984 16 h 0 check_sum +diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c +index d35f84d..b09ae73 100644 +--- a/src/southbridge/amd/sb700/sata.c ++++ b/src/southbridge/amd/sb700/sata.c +@@ -108,6 +108,7 @@ static void sata_init(struct device *dev) + int i, j; + uint8_t nvram; + uint8_t sata_ahci_mode; ++ uint8_t sata_alpm_enable; + uint8_t port_count; + uint8_t max_port_count; + +@@ -115,6 +116,10 @@ static void sata_init(struct device *dev) + if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS) + sata_ahci_mode = !!nvram; + ++ sata_alpm_enable = 0; ++ if (get_option(&nvram, "sata_alpm") == CB_SUCCESS) ++ sata_alpm_enable = !!nvram; ++ + device_t sm_dev; + /* SATA SMBus Disable */ + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); +@@ -233,6 +238,13 @@ static void sata_init(struct device *dev) + dword &= ~(0x1 << i); + write32(sata_bar5 + 0x0c, dword); + ++ /* Disable ALPM if ALPM support not requested */ ++ if (!sata_alpm_enable) { ++ dword = read32(sata_bar5 + 0xfc); ++ dword &= ~(0x1 << 11); /* Disable ALPM */ ++ write32(sata_bar5 + 0xfc, dword); ++ } ++ + /* Write protect Sub-Class Code */ + byte = pci_read_config8(dev, 0x40); + byte &= ~(1 << 0); +-- +1.7.9.5 + |