diff options
| author | Francis Rowe <info@gluglug.org.uk> | 2015-10-19 00:12:53 +0100 |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2015-10-19 02:32:36 +0100 |
| commit | 0622df6194dbb1b2120743c0fd1cc5e72c380128 (patch) | |
| tree | 4c858b8c5667fe001a9907ae0578b4ec28a8f513 /resources/libreboot/patch/kgpe-d16/0106-cpu-amd-family_10h-family_15h-Set-up-cache-controls-.patch | |
| parent | 5999dba5f71f1c05040a551d2420ab8c7f3a9da4 (diff) | |
| download | librebootfr-0622df6194dbb1b2120743c0fd1cc5e72c380128.tar.gz librebootfr-0622df6194dbb1b2120743c0fd1cc5e72c380128.zip | |
KGPE-D16: update patch set (also update coreboot and vboot)
Also contains other fixes from coreboot, like:
* 551cff0 Derive lvds_dual_channel from EDID timings.
^ makes single/dual channel LVDS selection on GM45 automatic
* 26fc544 lenovo/t60: Enable native intel gfx init.
^ was being maintained in libreboot, now upstreamed so not needed
Framebuffer mode was disabled for the KGPE-D16, because only
text-mode works at the moment.
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0106-cpu-amd-family_10h-family_15h-Set-up-cache-controls-.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0106-cpu-amd-family_10h-family_15h-Set-up-cache-controls-.patch | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0106-cpu-amd-family_10h-family_15h-Set-up-cache-controls-.patch b/resources/libreboot/patch/kgpe-d16/0106-cpu-amd-family_10h-family_15h-Set-up-cache-controls-.patch new file mode 100644 index 00000000..8cfb82cb --- /dev/null +++ b/resources/libreboot/patch/kgpe-d16/0106-cpu-amd-family_10h-family_15h-Set-up-cache-controls-.patch @@ -0,0 +1,43 @@ +From c4c97a2bf72bf0547a6c587a7096620a0e28773d Mon Sep 17 00:00:00 2001 +From: Timothy Pearson <tpearson@raptorengineeringinc.com> +Date: Sat, 8 Aug 2015 20:31:03 -0500 +Subject: [PATCH 106/139] cpu/amd/family_10h-family_15h: Set up cache controls + on Family 15h to improve performance + +Change-Id: I3df571d8091c07ac1ee29bf16b5a68585fa9eed4 +Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> +--- + src/cpu/amd/family_10h-family_15h/defaults.h | 10 ++++++++-- + 1 file changed, 8 insertions(+), 2 deletions(-) + +diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h +index 5ab4335..ce25b25 100644 +--- a/src/cpu/amd/family_10h-family_15h/defaults.h ++++ b/src/cpu/amd/family_10h-family_15h/defaults.h +@@ -139,8 +139,9 @@ static const struct { + 0x00000000, 1 << (42-32)}, /* Bx [PwcDisableWalkerSharing]=1 */ + + { BU_CFG3, AMD_OR_C0, AMD_PTYPE_ALL, +- 1 << 22, 0x00000000, +- 1 << 22, 0x00000000}, /* C0 or above [PfcDoubleStride]=1 */ ++ (0x3 << 20) | (0x1 << 22), 0x00000000, ++ (0x3 << 20) | (0x1 << 22), 0x00000000}, /* C0 or above [PfcDoubleStride]=1, ++ PfcStrideMul]=0x3 */ + + { EX_CFG, AMD_OR_C0, AMD_PTYPE_ALL, + 0x00000000, 1 << (54-32), +@@ -646,6 +647,11 @@ static const struct { + * System software should set F5x88[14] to 1b. */ + { 5, 0x88, AMD_OR_B2, AMD_PTYPE_ALL, + 1 << 14, 1 << 14 }, ++ ++ /* L3 Control 2 */ ++ { 3, 0x1b8, AMD_FAM15_ALL, AMD_PTYPE_ALL, ++ 0x00000090, 0x000001d0 }, /* ImplRdProjDelayThresh = 0x2, ++ ImplRdAnySubUnavail = 0x1 */ + }; + + +-- +1.9.1 + |