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| author | Francis Rowe <info@gluglug.org.uk> | 2015-10-19 00:12:53 +0100 |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2015-10-19 02:32:36 +0100 |
| commit | 0622df6194dbb1b2120743c0fd1cc5e72c380128 (patch) | |
| tree | 4c858b8c5667fe001a9907ae0578b4ec28a8f513 /resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch | |
| parent | 5999dba5f71f1c05040a551d2420ab8c7f3a9da4 (diff) | |
| download | librebootfr-0622df6194dbb1b2120743c0fd1cc5e72c380128.tar.gz librebootfr-0622df6194dbb1b2120743c0fd1cc5e72c380128.zip | |
KGPE-D16: update patch set (also update coreboot and vboot)
Also contains other fixes from coreboot, like:
* 551cff0 Derive lvds_dual_channel from EDID timings.
^ makes single/dual channel LVDS selection on GM45 automatic
* 26fc544 lenovo/t60: Enable native intel gfx init.
^ was being maintained in libreboot, now upstreamed so not needed
Framebuffer mode was disabled for the KGPE-D16, because only
text-mode works at the moment.
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch | 28 |
1 files changed, 0 insertions, 28 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch b/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch deleted file mode 100644 index 0dc6ff3d..00000000 --- a/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch +++ /dev/null @@ -1,28 +0,0 @@ -From da9855ac660e4b527ca0ee754d792ea0ab361fcc Mon Sep 17 00:00:00 2001 -From: Timothy Pearson <kb9vqf@pearsoncomputing.net> -Date: Fri, 14 Aug 2015 02:50:44 -0500 -Subject: [PATCH 118/146] southbridge/amd/sr5650: Use correct PCI - configuration block offset - ---- - src/southbridge/amd/sr5650/acpi/sr5650.asl | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/src/southbridge/amd/sr5650/acpi/sr5650.asl b/src/southbridge/amd/sr5650/acpi/sr5650.asl -index a6ab114..1e0d5b0 100644 ---- a/src/southbridge/amd/sr5650/acpi/sr5650.asl -+++ b/src/southbridge/amd/sr5650/acpi/sr5650.asl -@@ -19,8 +19,8 @@ - */ - - Scope(\) { -- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ -- Name(HPBA, 0xFED00000) /* Base address of HPET table */ -+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -+ Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) --- -1.7.9.5 - |