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| author | Francis Rowe <info@gluglug.org.uk> | 2016-01-02 22:10:32 +0000 |
|---|---|---|
| committer | Francis Rowe <info@gluglug.org.uk> | 2016-01-04 20:28:39 +0000 |
| commit | d1f408f3725aa02bc1d76c4c6aadb4697bd073c0 (patch) | |
| tree | 7eed036543ae1f8c57b56825880a722a8efbedf1 /resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch | |
| parent | 91aec7e72005dcda72d19f2d024a02d8c0f86590 (diff) | |
| download | librebootfr-d1f408f3725aa02bc1d76c4c6aadb4697bd073c0.tar.gz librebootfr-d1f408f3725aa02bc1d76c4c6aadb4697bd073c0.zip | |
Use different coreboot revisions and patches per board
The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.
At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.
Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.
For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch')
| -rw-r--r-- | resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch | 30 |
1 files changed, 0 insertions, 30 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch b/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch deleted file mode 100644 index 27fd1c24..00000000 --- a/resources/libreboot/patch/kgpe-d16/0118-southbridge-amd-sr5650-Use-correct-PCI-configuration.patch +++ /dev/null @@ -1,30 +0,0 @@ -From f5d5d25583a6aee7f725a6de8cc0a51753502666 Mon Sep 17 00:00:00 2001 -From: Timothy Pearson <tpearson@raptorengineeringinc.com> -Date: Fri, 14 Aug 2015 02:50:44 -0500 -Subject: [PATCH 118/143] southbridge/amd/sr5650: Use correct PCI - configuration block offset - -Change-Id: I4277d1788d8f9a501399218544aa6d4d11349ccc -Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> ---- - src/southbridge/amd/sr5650/acpi/sr5650.asl | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/src/southbridge/amd/sr5650/acpi/sr5650.asl b/src/southbridge/amd/sr5650/acpi/sr5650.asl -index a6ab114..1e0d5b0 100644 ---- a/src/southbridge/amd/sr5650/acpi/sr5650.asl -+++ b/src/southbridge/amd/sr5650/acpi/sr5650.asl -@@ -19,8 +19,8 @@ - */ - - Scope(\) { -- Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ -- Name(HPBA, 0xFED00000) /* Base address of HPET table */ -+ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ -+ Name(HPBA, 0xFED00000) /* Base address of HPET table */ - - /* PIC IRQ mapping registers, C00h-C01h */ - OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) --- -1.7.9.5 - |