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authorFrancis Rowe <info@gluglug.org.uk>2015-10-19 00:12:53 +0100
committerFrancis Rowe <info@gluglug.org.uk>2015-10-19 02:32:36 +0100
commit0622df6194dbb1b2120743c0fd1cc5e72c380128 (patch)
tree4c858b8c5667fe001a9907ae0578b4ec28a8f513 /resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch
parent5999dba5f71f1c05040a551d2420ab8c7f3a9da4 (diff)
downloadlibrebootfr-0622df6194dbb1b2120743c0fd1cc5e72c380128.tar.gz
librebootfr-0622df6194dbb1b2120743c0fd1cc5e72c380128.zip
KGPE-D16: update patch set (also update coreboot and vboot)
Also contains other fixes from coreboot, like: * 551cff0 Derive lvds_dual_channel from EDID timings. ^ makes single/dual channel LVDS selection on GM45 automatic * 26fc544 lenovo/t60: Enable native intel gfx init. ^ was being maintained in libreboot, now upstreamed so not needed Framebuffer mode was disabled for the KGPE-D16, because only text-mode works at the moment.
Diffstat (limited to 'resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch')
-rw-r--r--resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch35
1 files changed, 0 insertions, 35 deletions
diff --git a/resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch b/resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch
deleted file mode 100644
index d6788b5c..00000000
--- a/resources/libreboot/patch/kgpe-d16/0126-northbridge-amd-amdmct-mct_ddr3-Fix-a-minor-RDIMM-CS.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 85a652d6f36b200437c86b84cc76304271c14a1e Mon Sep 17 00:00:00 2001
-From: Timothy Pearson <kb9vqf@pearsoncomputing.net>
-Date: Thu, 27 Aug 2015 13:18:53 -0500
-Subject: [PATCH 126/146] northbridge/amd/amdmct/mct_ddr3: Fix a minor RDIMM
- CS select error
-
----
- src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c
-index 624a543..8fd2523 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c
-@@ -236,7 +236,7 @@ void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat,
- for (MrsChipSel = 0; MrsChipSel < 8; MrsChipSel ++, MrsChipSel ++) {
- if (pDCTstat->CSPresent & (1 << MrsChipSel)) {
- val = Get_NB32_DCT(dev, dct, 0xa8);
-- val &= ~(0xf << 8);
-+ val &= ~(0xff << 8);
-
- switch (MrsChipSel) {
- case 0:
-@@ -283,7 +283,7 @@ void FreqChgCtrlWrd(struct MCTStatStruc *pMCTstat,
- /* 2. Program F2x[1, 0]A8[CtrlWordCS]=bit mask for target chip selects. */
- val = Get_NB32_DCT(dev, dct, 0xa8);
- val &= ~(0xff << 8);
-- val |= (0x3 << (MrsChipSel & 0xfe)) << 8;
-+ val |= (0x3 << (MrsChipSel & ~0x1)) << 8;
- Set_NB32_DCT(dev, dct, 0xa8, val);
-
- /* Resend control word 10 */
---
-1.7.9.5
-