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authorFrancis Rowe <info@gluglug.org.uk>2015-06-15 20:15:36 +0100
committerFrancis Rowe <info@gluglug.org.uk>2015-06-16 04:36:26 +0100
commitbd95009839337576c1d7ac6d022228c4ec4248a5 (patch)
tree29622510346a315c5cb0fd766ac883147f3b4b15 /resources/utilities
parent9f8eced929a99b2ad7b10d1b8d237779afdd98d5 (diff)
downloadlibrebootfr-bd95009839337576c1d7ac6d022228c4ec4248a5.tar.gz
librebootfr-bd95009839337576c1d7ac6d022228c4ec4248a5.zip
Update coreboot-libre
Rebase all patches. Remove the ones that are no longer needed. More CPU microcode updates were moved to coreboot's 3rdparty repository, so there are less blobs for libreboot to delete now (because the 3rdparty repository is not checked out in libreboot). Correct HDA verbs used for T400 (also R400, T500) (patch is in coreboot, merged).
Diffstat (limited to 'resources/utilities')
-rwxr-xr-xresources/utilities/coreboot-libre/deblob24
-rw-r--r--resources/utilities/coreboot-libre/nonblobs31
2 files changed, 38 insertions, 17 deletions
diff --git a/resources/utilities/coreboot-libre/deblob b/resources/utilities/coreboot-libre/deblob
index 3ca64bb7..65611b36 100755
--- a/resources/utilities/coreboot-libre/deblob
+++ b/resources/utilities/coreboot-libre/deblob
@@ -31,31 +31,24 @@ cd "coreboot/"
# ---------------------
# Intel SoC (broadwell): CPU microcode updates
# ---------------------
-rm -f \
-"src/soc/intel/broadwell/microcode/microcode-M7240651_0000001C.h" \
-"src/soc/intel/broadwell/microcode/microcode-MF2306D2_FFFF0009.h" \
-"src/soc/intel/broadwell/microcode/microcode-MC0306D3_FFFF0010.h" \
-"src/soc/intel/broadwell/microcode/microcode-MC0306D4_0000000D.h"
# ---------------------
# Intel SoC (baytrail): CPU microcode updates
# ---------------------
-rm -f \
-"src/soc/intel/baytrail/microcode/M0C30678_00000816.h" \
-"src/soc/intel/baytrail/microcode/M0C3067_0000031E.h"
# ---------------------
# AMD: CPU microcode updates
# ---------------------
+
rm -f \
-"src/cpu/amd/model_fxx/microcode_rev_d.h" \
-"src/cpu/amd/model_fxx/microcode_rev_c.h" \
"src/cpu/amd/model_fxx/microcode_rev_e.h" \
-"src/cpu/amd/model_10xxx/mc_patch_01000095.h" \
-"src/cpu/amd/model_10xxx/mc_patch_01000096.h" \
+"src/cpu/amd/model_fxx/microcode_rev_c.h" \
+"src/cpu/amd/model_fxx/microcode_rev_d.h" \
"src/cpu/amd/model_10xxx/mc_patch_010000d9.h" \
+"src/cpu/amd/model_10xxx/mc_patch_01000096.h" \
"src/cpu/amd/model_10xxx/mc_patch_010000dc.h" \
"src/cpu/amd/model_10xxx/mc_patch_010000db.h" \
+"src/cpu/amd/model_10xxx/mc_patch_01000095.h" \
"src/cpu/amd/model_10xxx/mc_patch_010000c7.h" \
"src/cpu/amd/model_10xxx/mc_patch_010000c8.h"
@@ -159,6 +152,13 @@ rm -f \
"src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h" \
"src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h"
+# ----------------------------------
+# Purpose unknown. TODO: investigate
+# ----------------------------------
+
+rm -f \
+"util/broadcom/secimage/misc.c"
+
printf "\n\n"
cd "../"
diff --git a/resources/utilities/coreboot-libre/nonblobs b/resources/utilities/coreboot-libre/nonblobs
index e8bb6af7..a2887186 100644
--- a/resources/utilities/coreboot-libre/nonblobs
+++ b/resources/utilities/coreboot-libre/nonblobs
@@ -1,6 +1,3 @@
-./documentation/codeflow.svg
-./documentation/CorebootBuildingGuide.tex
-./documentation/hypertransport.svg
./payloads/coreinfo/util/kconfig/lex.zconf.c_shipped
./payloads/coreinfo/util/kconfig/zconf.hash.c_shipped
./payloads/coreinfo/util/kconfig/zconf.tab.c_shipped
@@ -195,7 +192,6 @@
./src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c
./src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpkb3.c
./src/vendorcode/amd/cimx/sb800/SATA.c
-./src/vendorcode/amd/pi/00730F01/Kconfig
./src/vendorcode/google/chromeos/build-snow
./util/amdtools/example_input/lspci-cb-48G-667MHz-18.2-20090909e
./util/amdtools/example_input/lspci-prop-48G-667MHz-18.2
@@ -253,6 +249,10 @@
./src/mainboard/google/samus/spd/samsung_8.spd.hex
./src/mainboard/google/samus/spd/elpida_8.spd.hex
./src/mainboard/google/samus/spd/samsung_4.spd.hex
+./src/mainboard/google/auron/spd/Micron_4KTF25664HZ.spd.hex
+./src/mainboard/google/auron/spd/Elpida_EDJ4216EFBG.spd.hex
+./src/mainboard/google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex
+./src/mainboard/google/auron/spd/empty.spd.hex
./src/northbridge/intel/nehalem/raminit_tables.c
./src/northbridge/intel/sandybridge/raminit_patterns.h
./src/southbridge/nvidia/mcp55/early_setup_ss.h
@@ -261,7 +261,6 @@
./util/crossgcc/patches/gcc-4.9.2_riscv.patch
./util/crossgcc/patches/binutils-2.25_riscv.patch
./src/southbridge/amd/pi/hudson/Kconfig
-./src/vendorcode/amd/pi/00630F01/Kconfig
./src/drivers/xgi/common/vb_setmode.c
./src/drivers/xgi/common/vb_table.h
./src/drivers/xgi/common/XGI_main.h
@@ -276,3 +275,25 @@
./src/cpu/amd/microcode/microcode.c
./src/lib/tlcl_structures.h
./util/rockchip/make_idb.py
+./util/autoport/readme.md
+./util/bimgtool/bimgtool.c
+./util/cbfstool/fmd_parser.c_shipped
+./util/cbfstool/fmd_scanner.c_shipped
+./Documentation/CorebootBuildingGuide.tex
+./Documentation/hypertransport.svg
+./Documentation/codeflow.svg
+./src/soc/broadcom/cygnus/ddr_init.c
+./src/soc/broadcom/cygnus/ddr_init_table.c
+./src/soc/qualcomm/ipq806x/lcc.c
+./src/soc/intel/braswell/acpi.c
+./src/soc/intel/braswell/Kconfig
+./src/soc/intel/braswell/romstage/raminit.c
+./src/vendorcode/amd/pi/Kconfig
+./src/drivers/intel/fsp1_1/Kconfig
+./src/drivers/intel/fsp1_1/fsp_gop.c
+./src/drivers/i2c/ww_ring/ww_ring_programs.c
+./src/mainboard/google/auron/spd/spd.c
+./src/mainboard/google/jecht/lan.c
+./src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
+./src/mainboard/amd/lamar/Kconfig
+./src/mainboard/bap/ode_e20XX/Micron_MT41J128M16JT.spd.hex