diff options
Diffstat (limited to 'projects/coreboot')
27 files changed, 995 insertions, 0 deletions
diff --git a/projects/coreboot/configs/blobs b/projects/coreboot/configs/blobs new file mode 100644 index 00000000..80efbe26 --- /dev/null +++ b/projects/coreboot/configs/blobs @@ -0,0 +1,54 @@ +src/cpu/dmp/vortex86ex/dmp_kbd_fw_part1.inc +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000086.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000098.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000f.c +src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h +src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieAlibSsdt.h +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c +src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h +src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c +src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h +src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h +src/vendorcode/amd/cimx/rd890/HotplugFirmware.h +src/vendorcode/google/chromeos/build-snow.sh diff --git a/projects/coreboot/configs/blobs-ignore b/projects/coreboot/configs/blobs-ignore new file mode 100644 index 00000000..b4fab33c --- /dev/null +++ b/projects/coreboot/configs/blobs-ignore @@ -0,0 +1,449 @@ +Documentation/codeflow.svg +Documentation/CorebootBuildingGuide.tex +Documentation/hypertransport.svg +payloads/external/depthcharge/Kconfig +payloads/external/FILO/Kconfig +payloads/external/GRUB2/Kconfig +payloads/external/SeaBIOS/Kconfig +payloads/external/U-Boot/Kconfig +payloads/Kconfig +payloads/libpayload/curses/PDCurses-3.4/demos/worm.c +payloads/libpayload/curses/PDCurses-3.4/sdl1/deffont.h +payloads/libpayload/curses/PDCurses-3.4/sdl1/deficon.h +payloads/libpayload/curses/PDCurses-3.4/win32/pdckbd.c +payloads/libpayload/curses/PDCurses-3.4/x11/big_icon.xbm +payloads/libpayload/curses/PDCurses-3.4/x11/little_icon.xbm +payloads/libpayload/curses/pdcurses-backend/pdcdisp.c +payloads/libpayload/curses/PDCurses/demos/worm.c +payloads/libpayload/curses/PDCurses/sdl1/deffont.h +payloads/libpayload/curses/PDCurses/sdl1/deficon.h +payloads/libpayload/curses/PDCurses/win32/pdckbd.c +payloads/libpayload/curses/PDCurses/x11/big_icon.xbm +payloads/libpayload/curses/PDCurses/x11/little_icon.xbm +payloads/libpayload/curses/tinycurses.c +payloads/libpayload/drivers/keyboard.c +payloads/libpayload/drivers/usb/usbmsc.c +payloads/libpayload/tests/cbfs-x86-test.c +payloads/nvramcui/payload.sh +src/cpu/allwinner/a10/raminit.c +src/cpu/amd/family_10h-family_15h/init_cpus.c +src/cpu/amd/family_10h-family_15h/processor_name.c +src/cpu/amd/geode_gx2/Kconfig +src/cpu/amd/geode_lx/cpureginit.c +src/cpu/amd/geode_lx/Kconfig +src/cpu/amd/microcode/microcode.c +src/cpu/amd/model_10xxx/init_cpus.c +src/cpu/amd/model_10xxx/processor_name.c +src/cpu/amd/model_fxx/model_fxx_update_microcode.c +src/cpu/amd/model_fxx/powernow_acpi.c +src/cpu/intel/fsp_model_206ax/acpi.c +src/cpu/intel/fsp_model_406dx/acpi.c +src/cpu/intel/haswell/acpi.c +src/cpu/intel/microcode/microcode.c +src/cpu/intel/model_2065x/acpi.c +src/cpu/intel/model_206ax/acpi.c +src/cpu/Kconfig +src/cpu/samsung/exynos5250/update-bl1.sh +src/cpu/via/nano/update_ucode.c +src/device/dram/spd_cache.c +src/device/Kconfig +src/device/oprom/yabel/interrupt.c +src/drivers/aspeed/common/ast_dram_tables.h +src/drivers/aspeed/common/ast_tables.h +src/drivers/i2c/ww_ring/ww_ring_programs.c +src/drivers/intel/fsp1_1/car.c +src/drivers/intel/fsp1_1/fsp_gop.c +src/drivers/intel/fsp1_1/Kconfig +src/drivers/intel/fsp1_1/ramstage.c +src/drivers/intel/fsp2_0/graphics.c +src/drivers/intel/fsp2_0/Kconfig +src/drivers/pc80/mc146818rtc.c +src/drivers/pc80/rtc/mc146818rtc.c +src/drivers/pc80/vga/vga_palette.c +src/drivers/siemens/nc_fpga/nc_fpga.c +src/drivers/xgi/common/vb_setmode.c +src/drivers/xgi/common/vb_table.h +src/drivers/xgi/common/XGI_main.h +src/Kconfig +src/lib/coreboot_table.c +src/lib/jpeg.c +src/lib/tlcl_structures.h +src/lib/tpm2_tlcl.c +src/mainboard/adi/rcc-dff/Kconfig +src/mainboard/advansus/a785e-i/mptable.c +src/mainboard/amd/bettong/mptable.c +src/mainboard/amd/bimini_fam10/mptable.c +src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex +src/mainboard/amd/dinar/buildOpts.c +src/mainboard/amd/dinar/Kconfig +src/mainboard/amd/gardenia/OemCustomize.c +src/mainboard/amd/inagua/Kconfig +src/mainboard/amd/lamar/Kconfig +src/mainboard/amd/olivehill/mptable.c +src/mainboard/amd/olivehillplus/mptable.c +src/mainboard/amd/parmer/mptable.c +src/mainboard/amd/persimmon/Kconfig +src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c +src/mainboard/amd/south_station/Kconfig +src/mainboard/amd/south_station/mptable.c +src/mainboard/amd/thatcher/mptable.c +src/mainboard/amd/torpedo/Kconfig +src/mainboard/amd/torpedo/mptable.c +src/mainboard/amd/union_station/Kconfig +src/mainboard/amd/union_station/mptable.c +src/mainboard/apple/macbookair4_2/early_southbridge.c +src/mainboard/asrock/e350m1/mptable.c +src/mainboard/asrock/imb-a180/mptable.c +src/mainboard/asus/f2a85-m/mptable.c +src/mainboard/asus/kfsn4-dre/get_bus_conf.c +src/mainboard/asus/m5a88-v/mptable.c +src/mainboard/avalue/eax-785e/mptable.c +src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex +src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex +src/mainboard/bap/ode_e20XX/BAP_Q7.spd.hex +src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex +src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex +src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex +src/mainboard/bap/ode_e21XX/mptable.c +src/mainboard/digitallogic/adl855pc/irq_tables.c +src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex +src/mainboard/gizmosphere/gizmo/mptable.c +src/mainboard/google/auron_paine/spd/spd.c +src/mainboard/google/auron/spd/Elpida_EDJ4216EFBG.spd.hex +src/mainboard/google/auron/spd/empty.spd.hex +src/mainboard/google/auron/spd/Hynix_HMT425S6AFR6A.spd.hex +src/mainboard/google/auron/spd/Micron_4KTF25664HZ.spd.hex +src/mainboard/google/auron/spd/spd.c +src/mainboard/google/bolt/elpida_4Gb_1600_x16.spd.hex +src/mainboard/google/bolt/micron_4Gb_1600_1.35v_x16.spd.hex +src/mainboard/google/bolt/romstage.c +src/mainboard/google/bolt/samsung_4Gb_1600_1.35v_x16.spd.hex +src/mainboard/google/butterfly/hda_verb.c +src/mainboard/google/butterfly/mainboard.c +src/mainboard/google/chell/spd/empty.spd.hex +src/mainboard/google/chell/spd/hynix_dimm_H9CCNNN8GTMLAR.spd.hex +src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex +src/mainboard/google/chell/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex +src/mainboard/google/chell/spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex +src/mainboard/google/chell/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex +src/mainboard/google/chell/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex +src/mainboard/google/chell/spd/spd.c +src/mainboard/google/cyan/Kconfig +src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex +src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex +src/mainboard/google/cyan/spd/spd.c +src/mainboard/google/enguarde/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +src/mainboard/google/enguarde/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex +src/mainboard/google/enguarde/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex +src/mainboard/google/enguarde/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex +src/mainboard/google/enguarde/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex +src/mainboard/google/enguarde/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex +src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex +src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex +src/mainboard/google/eve/spd/samsung_dimm_K4E8E324EB.spd.hex +src/mainboard/google/eve/spd/empty.spd.hex +src/mainboard/google/eve/spd/samsung_dimm_K4E6E304EB.spd.hex +src/mainboard/google/eve/spd/samsung_dimm_K4EBE304EB.spd.hex +src/mainboard/google/eve/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex +src/mainboard/google/falco/Elpida_EDJ4216EFBG.spd.hex +src/mainboard/google/falco/Hynix_HMT425S6AFR6A.spd.hex +src/mainboard/google/falco/Micron_4KTF25664HZ.spd.hex +src/mainboard/google/falco/romstage.c +src/mainboard/google/falco/Samsung_M471B5674QH0.spd.hex +src/mainboard/google/glados/spd/empty.spd.hex +src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex +src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex +src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex +src/mainboard/google/glados/spd/spd.c +src/mainboard/google/guado/lan.c +src/mainboard/google/jecht/lan.c +src/mainboard/google/lars/spd/empty.spd.hex +src/mainboard/google/lars/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex +src/mainboard/google/lars/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex +src/mainboard/google/lars/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex +src/mainboard/google/lars/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex +src/mainboard/google/lars/spd/spd.c +src/mainboard/google/link/elpida_4Gb_1600_x16.spd.hex +src/mainboard/google/link/hda_verb.c +src/mainboard/google/link/i915.c +src/mainboard/google/link/micron_4Gb_1600_1.35v_x16.spd.hex +src/mainboard/google/link/romstage.c +src/mainboard/google/link/samsung_4Gb_1600_1.35v_x16.spd.hex +src/mainboard/google/ninja/lan.c +src/mainboard/google/ninja/romstage.c +src/mainboard/google/ninja/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex +src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +src/mainboard/google/ninja/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex +src/mainboard/google/ninja/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex +src/mainboard/google/ninja/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex +src/mainboard/google/panther/lan.c +src/mainboard/google/peach_pit/mainboard.c +src/mainboard/google/peppy/Elpida_EDJ4216EFBG.spd.hex +src/mainboard/google/peppy/Hynix_HMT425S6AFR6A.spd.hex +src/mainboard/google/peppy/Micron_4KTF25664HZ.spd.hex +src/mainboard/google/peppy/romstage.c +src/mainboard/google/rambi/romstage.c +src/mainboard/google/rambi/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex +src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +src/mainboard/google/rambi/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex +src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex +src/mainboard/google/rikku/lan.c +src/mainboard/google/rotor/dram_params.c +src/mainboard/google/samus/romstage.c +src/mainboard/google/samus/spd/elpida_16.spd.hex +src/mainboard/google/samus/spd/elpida_4.spd.hex +src/mainboard/google/samus/spd/elpida_8.spd.hex +src/mainboard/google/samus/spd/empty.spd.hex +src/mainboard/google/samus/spd/hynix_16.spd.hex +src/mainboard/google/samus/spd/hynix_4.spd.hex +src/mainboard/google/samus/spd/hynix_8.spd.hex +src/mainboard/google/samus/spd/samsung_4.spd.hex +src/mainboard/google/samus/spd/samsung_8.spd.hex +src/mainboard/google/samus/spd/spd.c +src/mainboard/google/slippy/Hynix_HMT425S6AFR6A.spd.hex +src/mainboard/google/slippy/Micron_4KTF25664HZ.spd.hex +src/mainboard/google/slippy/variants/peppy/spd/Micron_4KTF25664HZ.spd.hex +src/mainboard/google/slippy/variants/peppy/spd/Elpida_EDJ4216EFBG.spd.hex +src/mainboard/google/slippy/variants/peppy/spd/Hynix_HMT425S6AFR6A.spd.hex +src/mainboard/google/slippy/variants/falco/spd/Micron_4KTF25664HZ.spd.hex +src/mainboard/google/slippy/variants/falco/spd/Elpida_EDJ4216EFBG.spd.hex +src/mainboard/google/slippy/variants/falco/spd/Samsung_M471B5674QH0.spd.hex +src/mainboard/google/slippy/variants/falco/spd/Hynix_HMT425S6AFR6A.spd.hex +src/mainboard/google/slippy/variants/leon/spd/Micron_4KTF25664HZ.spd.hex +src/mainboard/google/slippy/variants/leon/spd/Hynix_HMT425S6AFR6A.spd.hex +src/mainboard/google/slippy/variants/leon/spd/Samsung_K4B4G1646Q.spd.hex +src/mainboard/google/slippy/variants/wolf/spd/Micron_4KTF25664HZ.spd.hex +src/mainboard/google/slippy/variants/wolf/spd/Samsung_K4B4G1646B.spd.hex +src/mainboard/google/slippy/variants/wolf/spd/Hynix_HMT425S6AFR6A.spd.hex +src/mainboard/google/slippy/romstage.c +src/mainboard/google/tidus/lan.c +src/mainboard/hp/abm/mptable.c +src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c +src/mainboard/hp/pavilion_m6_1035dx/mptable.c +src/mainboard/ibase/mb899/cmos.layout +src/mainboard/ibase/mb899/superio_hwm.c +src/mainboard/intel/amenia/romstage.c +src/mainboard/intel/apollolake_rvp/romstage.c +src/mainboard/intel/cougar_canyon2/Kconfig +src/mainboard/intel/kblrvp/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex +src/mainboard/intel/kblrvp/spd/empty.spd.hex +src/mainboard/intel/kblrvp/spd/rvp3.spd.hex +src/mainboard/intel/kunimitsu/spd/empty.spd.hex +src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866.spd.hex +src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex +src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTALAR-NUD-2G-1866.spd.hex +src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex +src/mainboard/intel/kunimitsu/spd/mic_dimm_EDF8132A3MA-JD-F-1G-1866.spd.hex +src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E6E304EE-EGCF-2G-1866.spd.hex +src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex +src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E8E304EE-EGCF-1G-1866.spd.hex +src/mainboard/intel/kunimitsu/spd/spd.c +src/mainboard/intel/minnowmax/Kconfig +src/mainboard/intel/mohonpeak/Kconfig +src/mainboard/intel/sklrvp/spd/empty.spd.hex +src/mainboard/intel/sklrvp/spd/rvp3.spd.hex +src/mainboard/intel/sklrvp/spd/spd.c +src/mainboard/intel/strago/Kconfig +src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex +src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex +src/mainboard/intel/strago/spd/spd.c +src/mainboard/intel/wtm2/i915.c +src/mainboard/jetway/nf81-t56n-lf/Kconfig +src/mainboard/kontron/986lcd-m/cmos.layout +src/mainboard/kontron/986lcd-m/mainboard.c +src/mainboard/lenovo/g505s/mptable.c +src/mainboard/lippert/frontrunner-af/Kconfig +src/mainboard/lippert/frontrunner-af/mptable.c +src/mainboard/lippert/toucan-af/Kconfig +src/mainboard/lippert/toucan-af/mptable.c +src/mainboard/msi/ms7721/mptable.c +src/mainboard/msi/ms9652_fam10/get_bus_conf.c +src/mainboard/packardbell/ms2290/mainboard.c +src/mainboard/pcengines/apu1/Kconfig +src/mainboard/samsung/lumpy/romstage.c +src/mainboard/siemens/mc_bdx1/mainboard.c +src/mainboard/siemens/mc_tcu3/lcd_panel.c +src/mainboard/siemens/mc_tcu3/mainboard.c +src/mainboard/siemens/mc_tcu3/modhwinfo.c +src/mainboard/siemens/mc_tcu3/romstage.c +src/mainboard/siemens/sitemp_g1p1/cmos.layout +src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c +src/mainboard/supermicro/h8qgi/buildOpts.c +src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c +src/mainboard/supermicro/h8scm/buildOpts.c +src/mainboard/tyan/s2912_fam10/get_bus_conf.c +src/mainboard/tyan/s4880/irq_tables.c +src/mainboard/tyan/s4882/irq_tables.c +src/mainboard/tyan/s8226/buildOpts.c +src/northbridge/amd/agesa/common/common.c +src/northbridge/amd/amdk8/acpi.c +src/northbridge/amd/amdk8/coherent_ht.c +src/northbridge/amd/amdk8/raminit_test.c +src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c +src/northbridge/amd/amdmct/mct/mctardk3.c +src/northbridge/amd/amdmct/mct/mctardk4.c +src/northbridge/amd/amdmct/mct/mcttmrl.c +src/northbridge/amd/gx2/pll_reset.c +src/northbridge/amd/pi/00630F01/Kconfig +src/northbridge/amd/pi/00660F01/Kconfig +src/northbridge/amd/pi/00730F01/Kconfig +src/northbridge/intel/fsp_rangeley/fsp/Kconfig +src/northbridge/intel/fsp_sandybridge/fsp/Kconfig +src/northbridge/intel/gm45/raminit_rcomp_calibration.c +src/northbridge/intel/gm45/raminit_read_write_training.c +src/northbridge/intel/haswell/Kconfig +src/northbridge/intel/haswell/raminit.c +src/northbridge/intel/i82830/vga.c +src/northbridge/intel/i945/raminit.c +src/northbridge/intel/nehalem/gma.c +src/northbridge/intel/nehalem/raminit.c +src/northbridge/intel/nehalem/raminit_tables.c +src/northbridge/intel/pineview/raminit.c +src/northbridge/intel/sandybridge/gma.c +src/northbridge/intel/sandybridge/Kconfig +src/northbridge/intel/sandybridge/raminit.c +src/northbridge/intel/sandybridge/raminit_mrc.c +src/northbridge/intel/sandybridge/raminit_patterns.h +src/northbridge/intel/x4x/raminit_ddr2.c +src/northbridge/via/cx700/raminit.c +src/northbridge/via/vx800/ide.c +src/northbridge/via/vx800/uma_ram_setting.c +src/northbridge/via/vx900/sata.c +src/soc/broadcom/cygnus/ddr_init.c +src/soc/broadcom/cygnus/ddr_init_table.c +src/soc/intel/apollolake/Kconfig +src/soc/intel/apollolake/nhlt.c +src/soc/intel/baytrail/acpi.c +src/soc/intel/baytrail/Kconfig +src/soc/intel/baytrail/romstage/raminit.c +src/soc/intel/braswell/acpi.c +src/soc/intel/braswell/gpio.c +src/soc/intel/braswell/Kconfig +src/soc/intel/broadwell/acpi.c +src/soc/intel/broadwell/Kconfig +src/soc/intel/broadwell/romstage/raminit.c +src/soc/intel/common/fsp_ramstage.c +src/soc/intel/common/mma.c +src/soc/intel/common/vbt.c +src/soc/intel/fsp_baytrail/acpi.c +src/soc/intel/fsp_baytrail/fsp/Kconfig +src/soc/intel/fsp_baytrail/Kconfig +src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +src/soc/intel/fsp_broadwell_de/fsp/Kconfig +src/soc/intel/quark/Kconfig +src/soc/intel/quark/romstage/romstage.c +src/soc/intel/sch/Kconfig +src/soc/intel/skylake/Kconfig +src/soc/intel/skylake/nhlt/dmic.c +src/soc/intel/skylake/nhlt/max98357.c +src/soc/intel/skylake/nhlt/nau88l25.c +src/soc/intel/skylake/nhlt/ssm4567.c +src/soc/nvidia/tegra210/Kconfig +src/soc/nvidia/tegra210/mtc.c +src/soc/qualcomm/ipq40xx/Kconfig +src/soc/qualcomm/ipq40xx/lcc.c +src/soc/qualcomm/ipq806x/Kconfig +src/soc/qualcomm/ipq806x/lcc.c +src/soc/samsung/exynos5250/clock.c +src/soc/samsung/exynos5420/clock.c +src/southbridge/amd/agesa/hudson/Kconfig +src/southbridge/amd/cimx/sb800/Kconfig +src/southbridge/amd/pi/hudson/Kconfig +src/southbridge/intel/bd82x6x/Kconfig +src/southbridge/intel/bd82x6x/lpc.c +src/southbridge/intel/common/firmware/Kconfig +src/southbridge/intel/i82801ix/dmi_setup.c +src/southbridge/intel/ibexpeak/Kconfig +src/southbridge/intel/lynxpoint/Kconfig +src/southbridge/intel/sch/Kconfig +src/southbridge/nvidia/ck804/early_setup_ss.h +src/southbridge/nvidia/mcp55/early_setup_ss.h +src/southbridge/sis/sis966/early_setup_ss.h +src/southbridge/sis/sis966/early_smbus.c +src/southbridge/sis/sis966/ide.c +src/southbridge/sis/sis966/sata.c +src/southbridge/sis/sis966/usb2.c +src/southbridge/sis/sis966/usb.c +src/superio/via/vt1211/vt1211.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10Dmi.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c +src/vendorcode/amd/agesa/f10/Proc/Mem/Main/muc.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10Dmi.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12Dmi.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/cpuF12WheaInitDataTables.c +src/vendorcode/amd/agesa/f12/Proc/Fch/Hwm/Family/Hudson2/Hudson2HwmLateService.c +src/vendorcode/amd/agesa/f12/Proc/GNB/Gfx/Family/LN/F12GfxServices.c +src/vendorcode/amd/agesa/f12/Proc/Mem/Main/muc.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10Dmi.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c +src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10Dmi.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/cpuF10WheaInitDataTables.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c +src/vendorcode/amd/agesa/f15/Proc/Mem/Main/muc.c +src/vendorcode/amd/agesa/f15/Proc/Mem/Ps/OR/mpor3.c +src/vendorcode/amd/agesa/f15/Proc/Mem/Tech/DDR3/mtlrdimm3.c +src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c +src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c +src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c +src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mptn3.c +src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c +src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c +src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c +src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpkb3.c +src/vendorcode/amd/cimx/sb800/SATA.c +src/vendorcode/amd/pi/Kconfig +src/vendorcode/google/chromeos/build-snow +util/amdtools/example_input/lspci-cb-48G-667MHz-18.2-20090909e +util/amdtools/example_input/lspci-prop-48G-667MHz-18.2 +util/autoport/readme.md +util/bimgtool/bimgtool.c +util/cbfstool/fmd_parser.c_shipped +util/cbfstool/fmd_scanner.c_shipped +util/cbfstool/linux_trampoline.c +util/cbfstool/lz4/lib/lz4.c +util/crossgcc/patches/binutils-2.25_riscv.patch +util/crossgcc/patches/gcc-5.2.0_riscv.patch +util/ifdtool/ifdtool.c +util/intelmetool/intelmetool.c +util/ipqheader/createxbl.py +util/kconfig/zconf.hash.c_shipped +util/kconfig/zconf.lex.c_shipped +util/kconfig/zconf.tab.c_shipped +util/mma/mma_automated_test.sh +util/mtkheader/gen-bl-img.py +util/nvidia/cbootimage/src/aes_ref.c +util/nvramtool/accessors/layout-bin.c +util/riscvtools/make-spike-elf.sh +util/rockchip/make_idb.py +util/romcc/do_tests.sh +util/romcc/test.sh +util/romcc/tests/include/linux_console.h +util/romcc/tests/linux_console.h +util/romcc/tests/linux_test5.c +util/romcc/tests/raminit_test6.c +util/romcc/tests/raminit_test7.c +util/romcc/tests/simple_test14.c +util/romcc/tests/simple_test30.c +util/romcc/tests/simple_test38.c +util/romcc/tests/simple_test39.c +util/romcc/tests/simple_test54.c +util/romcc/tests/simple_test59.c +util/romcc/tests/simple_test72.c +util/romcc/tests/simple_test73.c +util/sconfig/lex.yy.c_shipped +util/sconfig/sconfig.tab.c_shipped +util/superiotool/fintek.c +util/superiotool/ite.c +util/superiotool/nuvoton.c +util/superiotool/smsc.c +util/superiotool/winbond.c +util/xcompile/xcompile diff --git a/projects/coreboot/configs/blobs-ignore-notes.txt b/projects/coreboot/configs/blobs-ignore-notes.txt new file mode 100644 index 00000000..551da4a8 --- /dev/null +++ b/projects/coreboot/configs/blobs-ignore-notes.txt @@ -0,0 +1,15 @@ +.spd.hex files - serial presence detect. These are not blobs +see JEDEC standard or https://en.wikipedia.org/wiki/Serial_presence_detect +These are added to the nonblobs file + +src/northbridge/intel/nehalem/raminit_tables.c" +src/northbridge/intel/sandybridge/raminit_patterns.h +These are used by native raminit for the relevant platforms, and are not blobs + +"src/southbridge/nvidia/mcp55/early_setup_ss.h" \ +"src/southbridge/nvidia/ck804/early_setup_ss.h" \ +"src/southbridge/sis/sis966/early_setup_ss.h" +not blobs + +The text in this file is CC-BY-SA 4.0 or higher. All contributions to it must +be made under the same license. diff --git a/projects/coreboot/configs/depthcharge/nyan/arch b/projects/coreboot/configs/depthcharge/nyan/arch new file mode 100644 index 00000000..fb05f39d --- /dev/null +++ b/projects/coreboot/configs/depthcharge/nyan/arch @@ -0,0 +1 @@ +arm diff --git a/projects/coreboot/configs/depthcharge/nyan/big/config b/projects/coreboot/configs/depthcharge/nyan/big/config new file mode 100644 index 00000000..41b4eeeb --- /dev/null +++ b/projects/coreboot/configs/depthcharge/nyan/big/config @@ -0,0 +1,7 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_NYAN_BIG=y +CONFIG_CHROMEOS=y +CONFIG_PAYLOAD_ELF=y +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-nyan-big/depthcharge.elf" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="$(obj)/../cros-ec-nyan-big/ec.RW.bin" diff --git a/projects/coreboot/configs/depthcharge/nyan/blaze/config b/projects/coreboot/configs/depthcharge/nyan/blaze/config new file mode 100644 index 00000000..10814c6e --- /dev/null +++ b/projects/coreboot/configs/depthcharge/nyan/blaze/config @@ -0,0 +1,12 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_NYAN_BLAZE=y +CONFIG_CHROMEOS=y +CONFIG_PAYLOAD_ELF=y +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-nyan-blaze/depthcharge.elf" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="$(obj)/../cros-ec-nyan-blaze/ec.RW.bin" +CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y +CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y +CONFIG_GBB_FLAG_FORCE_DEV_BOOT_USB=y +CONFIG_GBB_FLAG_DISABLE_FW_ROLLBACK_CHECK=y +CONFIG_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC=y diff --git a/projects/coreboot/configs/depthcharge/nyan/ec b/projects/coreboot/configs/depthcharge/nyan/ec new file mode 100644 index 00000000..903761a1 --- /dev/null +++ b/projects/coreboot/configs/depthcharge/nyan/ec @@ -0,0 +1 @@ +cros-ec diff --git a/projects/coreboot/configs/depthcharge/nyan/targets b/projects/coreboot/configs/depthcharge/nyan/targets new file mode 100644 index 00000000..419aafc5 --- /dev/null +++ b/projects/coreboot/configs/depthcharge/nyan/targets @@ -0,0 +1,2 @@ +big +blaze diff --git a/projects/coreboot/configs/depthcharge/targets b/projects/coreboot/configs/depthcharge/targets new file mode 100644 index 00000000..792768c4 --- /dev/null +++ b/projects/coreboot/configs/depthcharge/targets @@ -0,0 +1,2 @@ +nyan +veyron diff --git a/projects/coreboot/configs/depthcharge/veyron/arch b/projects/coreboot/configs/depthcharge/veyron/arch new file mode 100644 index 00000000..fb05f39d --- /dev/null +++ b/projects/coreboot/configs/depthcharge/veyron/arch @@ -0,0 +1 @@ +arm diff --git a/projects/coreboot/configs/depthcharge/veyron/jerry/config b/projects/coreboot/configs/depthcharge/veyron/jerry/config new file mode 100644 index 00000000..0ef0b86b --- /dev/null +++ b/projects/coreboot/configs/depthcharge/veyron/jerry/config @@ -0,0 +1,12 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_VEYRON_JERRY=y +CONFIG_CHROMEOS=y +CONFIG_PAYLOAD_ELF=y +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-jerry/depthcharge.elf" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="$(obj)/../cros-ec-veyron-jerry/ec.RW.bin" +CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y +CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y +CONFIG_GBB_FLAG_FORCE_DEV_BOOT_USB=y +CONFIG_GBB_FLAG_DISABLE_FW_ROLLBACK_CHECK=y +CONFIG_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC=y diff --git a/projects/coreboot/configs/depthcharge/veyron/jerry/ec b/projects/coreboot/configs/depthcharge/veyron/jerry/ec new file mode 100644 index 00000000..903761a1 --- /dev/null +++ b/projects/coreboot/configs/depthcharge/veyron/jerry/ec @@ -0,0 +1 @@ +cros-ec diff --git a/projects/coreboot/configs/depthcharge/veyron/mickey/config b/projects/coreboot/configs/depthcharge/veyron/mickey/config new file mode 100644 index 00000000..764ebdd8 --- /dev/null +++ b/projects/coreboot/configs/depthcharge/veyron/mickey/config @@ -0,0 +1,5 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_VEYRON_MICKEY=y +CONFIG_CHROMEOS=y +CONFIG_PAYLOAD_ELF=y +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-mickey/depthcharge.elf" diff --git a/projects/coreboot/configs/depthcharge/veyron/minnie/config b/projects/coreboot/configs/depthcharge/veyron/minnie/config new file mode 100644 index 00000000..fc6125fa --- /dev/null +++ b/projects/coreboot/configs/depthcharge/veyron/minnie/config @@ -0,0 +1,7 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_VEYRON_MINNIE=y +CONFIG_CHROMEOS=y +CONFIG_PAYLOAD_ELF=y +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-minnie/depthcharge.elf" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="$(obj)/../cros-ec-veyron-minnie/ec.RW.bin" diff --git a/projects/coreboot/configs/depthcharge/veyron/minnie/ec b/projects/coreboot/configs/depthcharge/veyron/minnie/ec new file mode 100644 index 00000000..903761a1 --- /dev/null +++ b/projects/coreboot/configs/depthcharge/veyron/minnie/ec @@ -0,0 +1 @@ +cros-ec diff --git a/projects/coreboot/configs/depthcharge/veyron/speedy/config b/projects/coreboot/configs/depthcharge/veyron/speedy/config new file mode 100644 index 00000000..9f45963d --- /dev/null +++ b/projects/coreboot/configs/depthcharge/veyron/speedy/config @@ -0,0 +1,7 @@ +CONFIG_VENDOR_GOOGLE=y +CONFIG_BOARD_GOOGLE_VEYRON_SPEEDY=y +CONFIG_CHROMEOS=y +CONFIG_PAYLOAD_ELF=y +CONFIG_PAYLOAD_FILE="$(obj)/../depthcharge-veyron-speedy/depthcharge.elf" +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL=y +CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_FILE="$(obj)/../cros-ec-veyron-speedy/ec.RW.bin" diff --git a/projects/coreboot/configs/depthcharge/veyron/speedy/ec b/projects/coreboot/configs/depthcharge/veyron/speedy/ec new file mode 100644 index 00000000..903761a1 --- /dev/null +++ b/projects/coreboot/configs/depthcharge/veyron/speedy/ec @@ -0,0 +1 @@ +cros-ec diff --git a/projects/coreboot/configs/depthcharge/veyron/targets b/projects/coreboot/configs/depthcharge/veyron/targets new file mode 100644 index 00000000..e4c9ca9e --- /dev/null +++ b/projects/coreboot/configs/depthcharge/veyron/targets @@ -0,0 +1,4 @@ +jerry +mickey +minnie +speedy diff --git a/projects/coreboot/configs/install b/projects/coreboot/configs/install new file mode 100644 index 00000000..bae9991d --- /dev/null +++ b/projects/coreboot/configs/install @@ -0,0 +1 @@ +coreboot.rom:coreboot.rom diff --git a/projects/coreboot/configs/revision b/projects/coreboot/configs/revision new file mode 100644 index 00000000..504b1b31 --- /dev/null +++ b/projects/coreboot/configs/revision @@ -0,0 +1 @@ +dcd2f17ff47cc1a4b26f253fb11a991cfe4ff6f5 diff --git a/projects/coreboot/configs/targets b/projects/coreboot/configs/targets new file mode 100644 index 00000000..d7e90413 --- /dev/null +++ b/projects/coreboot/configs/targets @@ -0,0 +1 @@ +depthcharge diff --git a/projects/coreboot/coreboot b/projects/coreboot/coreboot new file mode 100755 index 00000000..2a414dee --- /dev/null +++ b/projects/coreboot/coreboot @@ -0,0 +1,135 @@ +#!/bin/bash + +# Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. + +arguments() { + project_arguments_targets "$project" "$@" +} + +usage() { + project_usage_actions "$project" + project_usage_arguments "$project" "$@" +} + +download() { + local repository=$project + + project_download_git "$project" "$repository" "https://review.coreboot.org/coreboot https://github.com/coreboot/coreboot.git" "$@" +} + +download_check() { + local repository=$project + + project_download_check_git "$project" "$repository" "$@" +} + +extract() { + project_extract "$project" "$@" +} + +extract_check() { + project_extract_check "$project" "$@" +} + +update() { + local repository=$project + + project_update_git "$project" "$repository" "$@" +} + +update_check() { + local repository=$project + + project_update_check_git "$project" "$repository" "$@" +} + +build() { + local payload=$1 + shift + + local repository=$project + + project_sources_directory_missing_empty_error "$project" "$repository" "$payload" "$@" + + local sources_path=$( project_sources_path "$project" "$repository" "$payload" "$@" ) + local build_path=$( project_build_path "$project" "$payload" "$@" ) + local config_path=$( coreboot_config_path "$payload" "$@" ) + + local arch=$( coreboot_arch "$payload" "$@" ) + + local crossgcc_build_path=$( project_build_path "crossgcc" "$arch" ) + local crossgcc_bin_path="$crossgcc_build_path/bin/" + local vboot_sources_path=$( project_sources_path "vboot" "vboot" "devices" ) + + project_action "build" "crossgcc" "$arch" + + if git_project_check "$repository" + then + git_project_checkout "$project" "$repository" "$payload" "$@" + fi + + project_action "checkout" "vboot" "devices" + + project_action "build" "$payload" "$@" + + if coreboot_ec_check "$payload" "$@" + then + ec=$( coreboot_ec "$payload" "$@" ) + + project_action "build" "$ec" "$@" + fi + + rm -f "$sources_path/.xcompile" + + mkdir -p "$build_path" + + make -C "$sources_path" obj="$build_path" DOTCONFIG="$build_path/.config" XGCCPATH="$crossgcc_bin_path" BUILD_TIMELESS=1 KERNELVERSION="$VERSION" KBUILD_DEFCONFIG="$config_path" "defconfig" + make -C "$sources_path" obj="$build_path" DOTCONFIG="$build_path/.config" XGCCPATH="$crossgcc_bin_path" BUILD_TIMELESS=1 KERNELVERSION="$VERSION" VBOOT_SOURCE="$vboot_sources_path" -j$TASKS + + rm -f "$sources_path/.xcompile" +} + +build_check() { + project_build_check "$project" "$@" +} + +install() { + project_install "$project" "$@" +} + +install_check() { + project_install_check "$project" "$@" +} + +release() { + local repository=$project + + project_release_install_archive "$project" "$IMAGES" "$@" + + project_release_sources_git "$project" "$repository" "$@" +} + +release_check() { + local repository=$project + + project_release_install_archive_check "$project" "$IMAGES" "$@" + + project_release_check_sources_git "$project" "$repository" "$@" +} + +clean() { + project_clean "$project" "$@" +} diff --git a/projects/coreboot/coreboot-helper b/projects/coreboot/coreboot-helper new file mode 100644 index 00000000..b7849373 --- /dev/null +++ b/projects/coreboot/coreboot-helper @@ -0,0 +1,38 @@ +#!/bin/bash + +# Copyright (C) 2016 Paul Kocialkowski <contact@paulk.fr> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. + +DEVICES="devices" +PAYLOADS="payloads" +CONFIG="config" +ARCH="arch" +EC="ec" + +coreboot_arch() { + project_file_contents "$project" "$CONFIGS" "$ARCH" "$@" +} + +coreboot_config_path() { + project_file_path "$project" "$CONFIGS" "$CONFIG" "$@" +} + +coreboot_ec_check() { + project_file_test "$project" "$CONFIGS" "$EC" "$@" +} + +coreboot_ec() { + project_file_contents "$project" "$CONFIGS" "$EC" "$@" +} diff --git a/projects/coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch b/projects/coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch new file mode 100644 index 00000000..2e46141e --- /dev/null +++ b/projects/coreboot/patches/0001-Avoid-using-git-submodules-for-3rdparty.patch @@ -0,0 +1,122 @@ +From 95248477726f4a866b04a760f68930bc5ebd55ff Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski <contact@paulk.fr> +Date: Wed, 20 Jul 2016 16:03:30 +0200 +Subject: [PATCH 1/4] Avoid using git submodules for 3rdparty + +This gets rid of git submodules entirely, to avoid the nuisance caused +by automatically checking them out. + +Change-Id: I54de09656bd2dd9c308bd6c8dce554945aa8e535 +Signed-off-by: Paul Kocialkowski <contact@paulk.fr> +--- + .gitmodules | 20 -------------------- + 3rdparty/arm-trusted-firmware | 1 - + 3rdparty/blobs | 1 - + 3rdparty/chromeec | 1 - + 3rdparty/libgfxinit | 1 - + 3rdparty/libhwbase | 1 - + 3rdparty/vboot | 1 - + Makefile.inc | 11 ----------- + 8 files changed, 37 deletions(-) + delete mode 160000 3rdparty/arm-trusted-firmware + delete mode 160000 3rdparty/blobs + delete mode 160000 3rdparty/chromeec + delete mode 160000 3rdparty/libgfxinit + delete mode 160000 3rdparty/libhwbase + delete mode 160000 3rdparty/vboot + +diff --git a/.gitmodules b/.gitmodules +index c3270e6..3a617c7 100644 +--- a/.gitmodules ++++ b/.gitmodules +@@ -1,23 +1,3 @@ +-[submodule "3rdparty/blobs"] +- path = 3rdparty/blobs +- url = ../blobs.git +- update = none +- ignore = dirty + [submodule "util/nvidia-cbootimage"] + path = util/nvidia/cbootimage + url = ../nvidia-cbootimage.git +-[submodule "vboot"] +- path = 3rdparty/vboot +- url = ../vboot.git +-[submodule "arm-trusted-firmware"] +- path = 3rdparty/arm-trusted-firmware +- url = ../arm-trusted-firmware.git +-[submodule "3rdparty/chromeec"] +- path = 3rdparty/chromeec +- url = ../chrome-ec.git +-[submodule "libhwbase"] +- path = 3rdparty/libhwbase +- url = ../libhwbase.git +-[submodule "libgfxinit"] +- path = 3rdparty/libgfxinit +- url = ../libgfxinit.git +diff --git a/3rdparty/arm-trusted-firmware b/3rdparty/arm-trusted-firmware +deleted file mode 160000 +index bfd9251..0000000 +--- a/3rdparty/arm-trusted-firmware ++++ /dev/null +@@ -1 +0,0 @@ +-Subproject commit bfd925139fdbc2e87979849907b34843aa326994 +diff --git a/3rdparty/blobs b/3rdparty/blobs +deleted file mode 160000 +index 8090bdd..0000000 +--- a/3rdparty/blobs ++++ /dev/null +@@ -1 +0,0 @@ +-Subproject commit 8090bdd59853599e469b7503ea473ca12e8c681b +diff --git a/3rdparty/chromeec b/3rdparty/chromeec +deleted file mode 160000 +index ea1a869..0000000 +--- a/3rdparty/chromeec ++++ /dev/null +@@ -1 +0,0 @@ +-Subproject commit ea1a8699e96425806abdd532d04da254ae093f6e +diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit +deleted file mode 160000 +index 88a7f17..0000000 +--- a/3rdparty/libgfxinit ++++ /dev/null +@@ -1 +0,0 @@ +-Subproject commit 88a7f17b7d7a4f8a4d25ef6b87c71236b0862f5d +diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase +deleted file mode 160000 +index aab715f..0000000 +--- a/3rdparty/libhwbase ++++ /dev/null +@@ -1 +0,0 @@ +-Subproject commit aab715f166bf1b54cfbd6982e8df49248ea544d8 +diff --git a/3rdparty/vboot b/3rdparty/vboot +deleted file mode 160000 +index adfafba..0000000 +--- a/3rdparty/vboot ++++ /dev/null +@@ -1 +0,0 @@ +-Subproject commit adfafba793684ed92965dfbd86b3fb3463975d8c +diff --git a/Makefile.inc b/Makefile.inc +index c5ce30f..919a5d4 100644 +--- a/Makefile.inc ++++ b/Makefile.inc +@@ -183,17 +183,6 @@ ifeq ($(CONFIG_COVERAGE),y) + ramstage-c-ccopts += -fprofile-arcs -ftest-coverage + endif + +-ifneq ($(UPDATED_SUBMODULES),1) +-# try to fetch non-optional submodules if the source is under git +-forgetthis:=$(if $(GIT),$(shell git submodule update --init)) +-ifeq ($(CONFIG_USE_BLOBS),y) +-# this is necessary because 3rdparty/blobs is update=none, and so is ignored +-# unless explicitly requested and enabled through --checkout +-forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs)) +-endif +-export UPDATED_SUBMODULES:=1 +-endif +- + ramstage-c-deps:=$$(OPTION_TABLE_H) + romstage-c-deps:=$$(OPTION_TABLE_H) + libverstage-c-deps:=$$(OPTION_TABLE_H) +-- +2.10.2 + diff --git a/projects/coreboot/patches/0002-libpayload-Update-ARM-CrOS-devices-configuration.patch b/projects/coreboot/patches/0002-libpayload-Update-ARM-CrOS-devices-configuration.patch new file mode 100644 index 00000000..88f4013a --- /dev/null +++ b/projects/coreboot/patches/0002-libpayload-Update-ARM-CrOS-devices-configuration.patch @@ -0,0 +1,56 @@ +From fc26e7861ec756614e27a82895b60724a8173757 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski <contact@paulk.fr> +Date: Mon, 19 Dec 2016 18:03:23 +0100 +Subject: [PATCH 2/4] libpayload: Update ARM CrOS devices configuration + +This updates the configuration for ARM CrOS devices (nyans and veyrons) +by using the CHROMEOS Kconfig option, thus reducing the number of +options to select. It also brings proper serial console support. + +Change-Id: Iffc84c44a1d339c5bb575fbaffc40bc2d56bb6cf +Signed-off-by: Paul Kocialkowski <contact@paulk.fr> +--- + payloads/libpayload/configs/config.nyan | 10 +++------- + payloads/libpayload/configs/config.veyron | 10 +++------- + 2 files changed, 6 insertions(+), 14 deletions(-) + +diff --git a/payloads/libpayload/configs/config.nyan b/payloads/libpayload/configs/config.nyan +index 6e593e5..caad2b6 100644 +--- a/payloads/libpayload/configs/config.nyan ++++ b/payloads/libpayload/configs/config.nyan +@@ -1,10 +1,6 @@ +-CONFIG_LP_GPL=y ++CONFIG_LP_CHROMEOS=y + CONFIG_LP_ARCH_ARM=y +-# CONFIG_LP_CURSES is not set +-CONFIG_LP_SKIP_CONSOLE_INIT=y +-CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y +-# CONFIG_LP_STORAGE is not set ++CONFIG_LP_8250_SERIAL_CONSOLE=y + CONFIG_LP_TIMER_TEGRA_1US=y +-# CONFIG_LP_USB_OHCI is not set +-# CONFIG_LP_USB_XHCI is not set ++CONFIG_LP_USB_EHCI=y + CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT=y +diff --git a/payloads/libpayload/configs/config.veyron b/payloads/libpayload/configs/config.veyron +index 793907f..e80535c 100644 +--- a/payloads/libpayload/configs/config.veyron ++++ b/payloads/libpayload/configs/config.veyron +@@ -1,11 +1,7 @@ +-CONFIG_LP_GPL=y ++CONFIG_LP_CHROMEOS=y + CONFIG_LP_ARCH_ARM=y +-# CONFIG_LP_CURSES is not set +-CONFIG_LP_SKIP_CONSOLE_INIT=y +-CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y +-# CONFIG_LP_STORAGE is not set +-CONFIG_LP_TIMER_RK=y +-CONFIG_LP_USB=y ++CONFIG_LP_8250_SERIAL_CONSOLE=y ++CONFIG_LP_TIMER_RK3288=y + CONFIG_LP_USB_EHCI=y + CONFIG_LP_USB_DWC2=y + # CONFIG_LP_USB_HID is not set +-- +2.10.2 + diff --git a/projects/coreboot/patches/0003-libpayload-Get-current-tick-from-high-register-in-ge.patch b/projects/coreboot/patches/0003-libpayload-Get-current-tick-from-high-register-in-ge.patch new file mode 100644 index 00000000..4fb09c79 --- /dev/null +++ b/projects/coreboot/patches/0003-libpayload-Get-current-tick-from-high-register-in-ge.patch @@ -0,0 +1,32 @@ +From 03a830aad1cdf4325781aa60566bebcf5aa57238 Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski <contact@paulk.fr> +Date: Mon, 19 Dec 2016 19:22:39 +0100 +Subject: [PATCH 3/4] libpayload: Get current tick from high register in + generic timer + +This fixes the generic timer driver to get the current tick from the +high register, so that comparison with the high count value (obtained +previously from the same register) has a chance to succeed. + +Change-Id: I5ce02bfa15a91ad34641b8e24813a5b7ca790ec3 +Signed-off-by: Paul Kocialkowski <contact@paulk.fr> +--- + payloads/libpayload/drivers/timer/generic.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/payloads/libpayload/drivers/timer/generic.c b/payloads/libpayload/drivers/timer/generic.c +index 4c06618..ac26f40 100644 +--- a/payloads/libpayload/drivers/timer/generic.c ++++ b/payloads/libpayload/drivers/timer/generic.c +@@ -53,7 +53,7 @@ uint64_t timer_raw_value(void) + do { + count_h = readl(phys_to_virt(CONFIG_LP_TIMER_GENERIC_HIGH_REG)); + count_l = readl(phys_to_virt(CONFIG_LP_TIMER_GENERIC_REG)); +- cur_tick = readl(phys_to_virt(CONFIG_LP_TIMER_GENERIC_REG)); ++ cur_tick = readl(phys_to_virt(CONFIG_LP_TIMER_GENERIC_HIGH_REG)); + } while (cur_tick != count_h); + + return (cur_tick << 32) + count_l; +-- +2.10.2 + diff --git a/projects/coreboot/patches/0004-libpayload-Enable-USB-HID-in-veyron-configuration.patch b/projects/coreboot/patches/0004-libpayload-Enable-USB-HID-in-veyron-configuration.patch new file mode 100644 index 00000000..af00a42d --- /dev/null +++ b/projects/coreboot/patches/0004-libpayload-Enable-USB-HID-in-veyron-configuration.patch @@ -0,0 +1,27 @@ +From 552b999c7b32363cbc51722f33a0de189baf27fe Mon Sep 17 00:00:00 2001 +From: Paul Kocialkowski <contact@paulk.fr> +Date: Mon, 19 Dec 2016 20:23:44 +0100 +Subject: [PATCH 4/4] libpayload: Enable USB HID in veyron configuration + +This enables USB HID support in the veyron config, since it seems to +work correctly and is needed for interaction with depthcharge on devices +without an embedded keyboard (such as veyron_jerry). + +Change-Id: Icae829e3a132005df17bcb6f7e6f8a190912576d +Signed-off-by: Paul Kocialkowski <contact@paulk.fr> +--- + payloads/libpayload/configs/config.veyron | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/payloads/libpayload/configs/config.veyron b/payloads/libpayload/configs/config.veyron +index e80535c..b643e92 100644 +--- a/payloads/libpayload/configs/config.veyron ++++ b/payloads/libpayload/configs/config.veyron +@@ -4,4 +4,3 @@ CONFIG_LP_8250_SERIAL_CONSOLE=y + CONFIG_LP_TIMER_RK3288=y + CONFIG_LP_USB_EHCI=y + CONFIG_LP_USB_DWC2=y +-# CONFIG_LP_USB_HID is not set +-- +2.10.2 + |