diff options
Diffstat (limited to 'resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub')
38 files changed, 1656 insertions, 0 deletions
diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/macbook21/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/macbook21/reused.list new file mode 100644 index 00000000..0b8c8e70 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/macbook21/reused.list @@ -0,0 +1,2 @@ +/resources/libreboot/patch/coreboot/8ba2010d126ce7a6d32504bcb2a0e1b231732c0f/grub/x60/0001-i945-Enable-changing-VRAM-size.patch +/resources/libreboot/patch/coreboot/8ba2010d126ce7a6d32504bcb2a0e1b231732c0f/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_16mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_16mb/INFO new file mode 100644 index 00000000..ad7d12f4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_16mb/INFO @@ -0,0 +1,4 @@ +# NOTE: remove this when updating coreboot. This has been merged upstream +printf "ThinkPad R400 support (clone of the T400)\n" +git am "../resources/libreboot/patch/misc/0007-lenovo-r400-Add-clone-of-Lenovo-T400.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/93/8393/5 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_16mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_16mb/reused.list new file mode 100644 index 00000000..e9ff2499 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_16mb/reused.list @@ -0,0 +1,6 @@ +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb//0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_4mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_4mb/reused.list new file mode 100644 index 00000000..0f4bf368 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_4mb/reused.list @@ -0,0 +1,6 @@ +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_8mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_8mb/INFO new file mode 100644 index 00000000..ad7d12f4 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_8mb/INFO @@ -0,0 +1,4 @@ +# NOTE: remove this when updating coreboot. This has been merged upstream +printf "ThinkPad R400 support (clone of the T400)\n" +git am "../resources/libreboot/patch/misc/0007-lenovo-r400-Add-clone-of-Lenovo-T400.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/93/8393/5 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_8mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_8mb/reused.list new file mode 100644 index 00000000..0f4bf368 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/r400_8mb/reused.list @@ -0,0 +1,6 @@ +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_16mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_16mb/INFO new file mode 100644 index 00000000..9ef6d54a --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_16mb/INFO @@ -0,0 +1,8 @@ +# NOTE: merged upstream already +printf "mainboard/lenovo/t400: Add initial hybrid graphics support\n" +git am "../resources/libreboot/patch/misc/0001-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/19/9319/18 && git cherry-pick FETCH_HEAD + +printf "NOTFORMERGE: lenovo/t400: hard-code enable integrated-only video\n" +git am "../resources/libreboot/patch/misc/0002-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/50/10550/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_16mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_16mb/reused.list new file mode 100644 index 00000000..0f4bf368 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_16mb/reused.list @@ -0,0 +1,6 @@ +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_4mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_4mb/reused.list new file mode 100644 index 00000000..0f4bf368 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_4mb/reused.list @@ -0,0 +1,6 @@ +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0001-Revert-hybrid-driver.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0001-Revert-hybrid-driver.patch new file mode 100644 index 00000000..67420ca7 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0001-Revert-hybrid-driver.patch @@ -0,0 +1,601 @@ +From fbbc8d6a278c733eca475c17cbf95a8946e2c173 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 4 Aug 2016 11:00:13 +0200 +Subject: [PATCH 1/3] Revert "drivers/lenovo: Add hybrid graphics driver" + +This reverts commit 5919ba42ed0ce5b1b13717514698444232c6036c. + +Change-Id: I027581ef769ca8232e72f89738c1bdec13f62687 + +diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig +index f8eddf2..f20f3b2 100644 +--- a/src/drivers/lenovo/Kconfig ++++ b/src/drivers/lenovo/Kconfig +@@ -27,16 +27,3 @@ config DIGITIZER_ABSENT + endchoice + + endif +- +-config DRIVERS_LENOVO_HYBRID_GRAPHICS +- bool +- default n +- +-config HYBRID_GRAPHICS_GPIO_NUM +- depends on DRIVERS_LENOVO_HYBRID_GRAPHICS +- int +- default 52 +- help +- Set a default GPIO that sets the panel LVDS signal routing to +- integrated or discrete GPU. +- +diff --git a/src/drivers/lenovo/Makefile.inc b/src/drivers/lenovo/Makefile.inc +index 66f8594..c50db5b 100644 +--- a/src/drivers/lenovo/Makefile.inc ++++ b/src/drivers/lenovo/Makefile.inc +@@ -1,2 +1 @@ + ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c +-ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c +diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c +deleted file mode 100644 +index 9b46646..0000000 +--- a/src/drivers/lenovo/hybrid_graphics.c ++++ /dev/null +@@ -1,125 +0,0 @@ +-/* +- * This file is part of the coreboot project. +- * +- * Copyright (C) 2015-2016 Patrick Rudolph +- * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering +- * +- * This program is free software; you can redistribute it and/or modify +- * it under the terms of the GNU General Public License as published by +- * the Free Software Foundation; version 2 of the License. +- * +- * This program is distributed in the hope that it will be useful, +- * but WITHOUT ANY WARRANTY; without even the implied warranty of +- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +- * GNU General Public License for more details. +- */ +- +-#include <types.h> +-#include <string.h> +-#include <option.h> +-#include <device/device.h> +-#include <device/pci_def.h> +-#include <device/pci_ops.h> +-#include <device/pci_ids.h> +-#include <device/pci.h> +-#include <console/console.h> +-#include <southbridge/intel/common/gpio.h> +- +-/* Hybrid graphics allows to connect LVDS interface to either iGPU +- * or dGPU depending on GPIO level. +- * Nvidia is calling this functionality "muxed Optimus". +- * Some devices, like T430s, only support "muxless Optimus" where the +- * Intel GPU is always connected to the panel. +- * As it is only linked on lenovo and only executed if the GPU exists +- * we know for sure that the dGPU is there and connected to first PEG slot. +- * +- * Note: Once native gfx init is done for AMD or Nvida graphic +- * cards, merge this code. +- */ +- +-#define HYBRID_GRAPHICS_INTEGRATED 0 +-#define HYBRID_GRAPHICS_DISCRETE 1 +- +-static void hybrid_graphics_disable_peg(struct device *dev) +-{ +- struct device *peg_dev; +- +- /* connect LVDS interface to iGPU */ +- set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); +- printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); +- dev->enabled = 0; +- +- /* Disable PEG10 */ +- peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); +- if (peg_dev) +- peg_dev->enabled = 0; +- +- printk(BIOS_DEBUG, "Hybrid graphics: Disabled PEG10.\n"); +-} +- +-/* Called before VGA enable bits are set and only if dGPU +- * is present. Enable/disable VGA devices here. */ +-static void hybrid_graphics_enable_peg(struct device *dev) +-{ +- u8 hybrid_graphics_mode; +- +- hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; +- get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); +- +- if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { +- /* connect LVDS interface to dGPU */ +- set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); +- printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); +- dev->enabled = 1; +- +- /* Disable IGD */ +- dev = dev_find_slot(0, PCI_DEVFN(2, 0)); +- if (dev && dev->ops->disable) +- dev->ops->disable(dev); +- dev->enabled = 0; +- +- printk(BIOS_DEBUG, "Hybrid graphics: Disabled IGD.\n"); +- } else +- hybrid_graphics_disable_peg(dev); +-} +- +-static struct pci_operations pci_dev_ops_pci = { +- .set_subsystem = pci_dev_set_subsystem, +-}; +- +-struct device_operations hybrid_graphics_ops = { +- .read_resources = pci_dev_read_resources, +- .set_resources = pci_dev_set_resources, +- .enable_resources = pci_dev_enable_resources, +- .init = pci_dev_init, +- .scan_bus = 0, +- .enable = hybrid_graphics_enable_peg, +- .disable = hybrid_graphics_disable_peg, +- .ops_pci = &pci_dev_ops_pci, +-}; +- +-static const unsigned short pci_device_ids_nvidia[] = { +- 0x0ffc, /* Nvidia NVS Quadro K1000m Lenovo W530 */ +- 0x0def, /* NVidia NVS 5400m Lenovo T430/T530 */ +- 0x0dfc, /* NVidia NVS 5200m Lenovo T430s */ +- 0x1056, /* NVidia NVS 4200m Lenovo T420/T520 */ +- 0x1057, /* NVidia NVS 4200m Lenovo T420/T520 */ +- 0x0a6c, /* NVidia NVS 3100m Lenovo T410/T510 */ +- 0 }; +- +-static const struct pci_driver hybrid_peg_nvidia __pci_driver = { +- .ops = &hybrid_graphics_ops, +- .vendor = PCI_VENDOR_ID_NVIDIA, +- .devices = pci_device_ids_nvidia, +-}; +- +-static const unsigned short pci_device_ids_amd[] = { +- 0x9591, /* ATI Mobility Radeon HD 3650 Lenovo T500/W500 */ +- 0x95c4, /* ATI Mobility Radeon HD 3470 Lenovo T400/R400 */ +- 0 }; +- +-static const struct pci_driver hybrid_peg_amd __pci_driver = { +- .ops = &hybrid_graphics_ops, +- .vendor = PCI_VENDOR_ID_ATI, +- .devices = pci_device_ids_amd, +-}; +diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig +index a444bf8..d74a813 100644 +--- a/src/mainboard/lenovo/t400/Kconfig ++++ b/src/mainboard/lenovo/t400/Kconfig +@@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select INTEL_INT15 + select SUPERIO_NSC_PC87382 +- select DRIVERS_LENOVO_HYBRID_GRAPHICS + + config MAINBOARD_DIR + string +diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default +index 5cf3e63..ac9f96d 100644 +--- a/src/mainboard/lenovo/t400/cmos.default ++++ b/src/mainboard/lenovo/t400/cmos.default +@@ -13,5 +13,3 @@ sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI +-hybrid_graphics_mode=Integrated Only +-gfx_uma_size=32M +\ No newline at end of file +diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout +index b4b7766..e1a088d 100644 +--- a/src/mainboard/lenovo/t400/cmos.layout ++++ b/src/mainboard/lenovo/t400/cmos.layout +@@ -77,8 +77,7 @@ entries + 940 1 e 1 uwb + + # coreboot config options: northbridge +-944 2 e 12 hybrid_graphics_mode +-946 4 e 11 gfx_uma_size ++941 4 e 11 gfx_uma_size + + # coreboot config options: EC + 952 8 h 0 volume +diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default +index 3a82c97..1b8e212 100644 +--- a/src/mainboard/lenovo/t420/cmos.default ++++ b/src/mainboard/lenovo/t420/cmos.default +@@ -14,4 +14,3 @@ fn_ctrl_swap=Disable + sticky_fn=Disable + trackpoint=Enable + hyper_threading=Enable +-hybrid_graphics_mode=Integrated Only +\ No newline at end of file +diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout +index 58a4abe..bf0f195 100644 +--- a/src/mainboard/lenovo/t420/cmos.layout ++++ b/src/mainboard/lenovo/t420/cmos.layout +@@ -77,8 +77,7 @@ entries + + # coreboot config options: northbridge + 432 3 e 11 gfx_uma_size +-435 2 e 12 hybrid_graphics_mode +-#437 3 r 0 unused ++#435 5 r 0 unused + + 440 8 h 0 volume + +@@ -136,8 +135,6 @@ enumerations + 11 4 160M + 11 5 192M + 11 6 224M +-12 0 Integrated Only +-12 1 Discrete Only + + # ----------------------------------------------------------------- + checksums +diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig +index feacb51..935e659 100644 +--- a/src/mainboard/lenovo/t420s/Kconfig ++++ b/src/mainboard/lenovo/t420s/Kconfig +@@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy + select INTEL_INT15 + select SANDYBRIDGE_IVYBRIDGE_LVDS + select MAINBOARD_HAS_LPC_TPM +- select DRIVERS_LENOVO_HYBRID_GRAPHICS + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE +diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default +index 3a82c97..1b8e212 100644 +--- a/src/mainboard/lenovo/t420s/cmos.default ++++ b/src/mainboard/lenovo/t420s/cmos.default +@@ -14,4 +14,3 @@ fn_ctrl_swap=Disable + sticky_fn=Disable + trackpoint=Enable + hyper_threading=Enable +-hybrid_graphics_mode=Integrated Only +\ No newline at end of file +diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout +index 3521849..43628406 100644 +--- a/src/mainboard/lenovo/t420s/cmos.layout ++++ b/src/mainboard/lenovo/t420s/cmos.layout +@@ -77,8 +77,7 @@ entries + + # coreboot config options: northbridge + 432 3 e 11 gfx_uma_size +-435 2 e 12 hybrid_graphics_mode +-#437 3 r 0 unused ++#435 5 r 0 unused + + 440 8 h 0 volume + +@@ -136,8 +135,6 @@ enumerations + 11 4 160M + 11 5 192M + 11 6 224M +-12 0 Integrated Only +-12 1 Discrete Only + + # ----------------------------------------------------------------- + checksums +diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig +index ee5dd81..c70581a 100644 +--- a/src/mainboard/lenovo/t520/Kconfig ++++ b/src/mainboard/lenovo/t520/Kconfig +@@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy + select INTEL_INT15 + select SANDYBRIDGE_IVYBRIDGE_LVDS + select MAINBOARD_HAS_LPC_TPM +- select DRIVERS_LENOVO_HYBRID_GRAPHICS + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE +diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default +index ad7dcf5..00e8863 100644 +--- a/src/mainboard/lenovo/t520/cmos.default ++++ b/src/mainboard/lenovo/t520/cmos.default +@@ -15,4 +15,3 @@ sticky_fn=Disable + trackpoint=Enable + hyper_threading=Enable + backlight=Both +-hybrid_graphics_mode=Integrated Only +\ No newline at end of file +diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout +index 044c310..2cf3629 100644 +--- a/src/mainboard/lenovo/t520/cmos.layout ++++ b/src/mainboard/lenovo/t520/cmos.layout +@@ -77,8 +77,7 @@ entries + + # coreboot config options: northbridge + 432 3 e 11 gfx_uma_size +-435 2 e 12 hybrid_graphics_mode +-#437 3 r 0 unused ++#435 5 r 0 unused + 440 8 h 0 volume + + # SandyBridge MRC Scrambler Seed values +@@ -135,8 +134,6 @@ enumerations + 11 4 160M + 11 5 192M + 11 6 224M +-12 0 Integrated Only +-12 1 Discrete Only + # ----------------------------------------------------------------- + checksums + +diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig +index 76147fc..030c01f 100644 +--- a/src/mainboard/lenovo/t530/Kconfig ++++ b/src/mainboard/lenovo/t530/Kconfig +@@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy + select SANDYBRIDGE_IVYBRIDGE_LVDS + select ENABLE_VMX + select MAINBOARD_HAS_LPC_TPM +- select DRIVERS_LENOVO_HYBRID_GRAPHICS + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE +diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default +index ad7dcf5..00e8863 100644 +--- a/src/mainboard/lenovo/t530/cmos.default ++++ b/src/mainboard/lenovo/t530/cmos.default +@@ -15,4 +15,3 @@ sticky_fn=Disable + trackpoint=Enable + hyper_threading=Enable + backlight=Both +-hybrid_graphics_mode=Integrated Only +\ No newline at end of file +diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout +index 0e28bdd..e21c197 100644 +--- a/src/mainboard/lenovo/t530/cmos.layout ++++ b/src/mainboard/lenovo/t530/cmos.layout +@@ -77,8 +77,7 @@ entries + + # coreboot config options: northbridge + 432 3 e 11 gfx_uma_size +-435 2 e 12 hybrid_graphics_mode +-#437 3 r 0 unused ++#435 5 r 0 unused + + 440 8 h 0 volume + +@@ -136,9 +135,6 @@ enumerations + 11 4 160M + 11 5 192M + 11 6 224M +-12 0 Integrated Only +-12 1 Discrete Only +- + # ----------------------------------------------------------------- + checksums + +diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig +index b3e5069..2822774 100644 +--- a/src/southbridge/intel/i82801ix/Kconfig ++++ b/src/southbridge/intel/i82801ix/Kconfig +@@ -23,7 +23,6 @@ config SOUTHBRIDGE_INTEL_I82801IX + select USE_WATCHDOG_ON_BOOT + select HAVE_SMI_HANDLER + select HAVE_USBDEBUG_OPTIONS +- select SOUTHBRIDGE_INTEL_COMMON_GPIO + + if SOUTHBRIDGE_INTEL_I82801IX + +-- +2.9.2 + +From 90f5f34629ff88506bb803988da1552f3373d4f0 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Thu, 4 Aug 2016 11:01:53 +0200 +Subject: [PATCH 2/3] Revert "Revert "mainboard/lenovo/t400: Add initial hybrid + graphics support"" + +This reverts commit 14d1a93e444b91311eeed2a25953bf6c0779cdcb. + +Change-Id: I965ea55bddb7cf919e7b02ecf8e160c9ad3ea3d4 + +diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default +index ac9f96d..98ce970 100644 +--- a/src/mainboard/lenovo/t400/cmos.default ++++ b/src/mainboard/lenovo/t400/cmos.default +@@ -13,3 +13,4 @@ sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI ++hybrid_graphics_mode=Integrated Only +\ No newline at end of file +diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout +index e1a088d..b4b7766 100644 +--- a/src/mainboard/lenovo/t400/cmos.layout ++++ b/src/mainboard/lenovo/t400/cmos.layout +@@ -77,7 +77,8 @@ entries + 940 1 e 1 uwb + + # coreboot config options: northbridge +-941 4 e 11 gfx_uma_size ++944 2 e 12 hybrid_graphics_mode ++946 4 e 11 gfx_uma_size + + # coreboot config options: EC + 952 8 h 0 volume +diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c +index f518775..fcc545b 100644 +--- a/src/mainboard/lenovo/t400/romstage.c ++++ b/src/mainboard/lenovo/t400/romstage.c +@@ -1,6 +1,7 @@ + /* + * This file is part of the coreboot project. + * ++ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or +@@ -34,6 +35,118 @@ + #define LPC_DEV PCI_DEV(0, 0x1f, 0) + #define MCH_DEV PCI_DEV(0, 0, 0) + ++#define HYBRID_GRAPHICS_INTEGRATED_ONLY 0 ++#define HYBRID_GRAPHICS_DISCRETE_ONLY 1 ++#define HYBRID_GRAPHICS_SWITCHABLE 2 ++ ++#define HYBRID_GRAPHICS_GP_LVL_BITS 0x004a0000 ++#define HYBRID_GRAPHICS_GP_LVL2_BITS 0x00020000 ++ ++#define HYBRID_GRAPHICS_DETECT_GP_BITS 0x00000010 ++ ++#define HYBRID_GRAPHICS_INT_CLAIM_VGA 0x2 ++#define HYBRID_GRAPHICS_SEC_VGA_EN 0x2 ++ ++static void hybrid_graphics_configure_switchable_graphics(bool enable) ++{ ++ uint32_t tmp; ++ ++ if (enable) { ++ /* Disable integrated graphics legacy VGA cycles */ ++ tmp = pci_read_config16(MCH_DEV, D0F0_GGC); ++ pci_write_config16(MCH_DEV, D0F0_GGC, tmp | HYBRID_GRAPHICS_INT_CLAIM_VGA); ++ ++ /* Enable secondary VGA controller */ ++ tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); ++ pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp | HYBRID_GRAPHICS_SEC_VGA_EN); ++ } ++ else { ++ /* Enable integrated graphics legacy VGA cycles */ ++ tmp = pci_read_config16(MCH_DEV, D0F0_GGC); ++ pci_write_config16(MCH_DEV, D0F0_GGC, tmp & ~HYBRID_GRAPHICS_INT_CLAIM_VGA); ++ ++ /* Disable secondary VGA controller */ ++ tmp = pci_read_config16(MCH_DEV, D0F0_DEVEN); ++ pci_write_config16(MCH_DEV, D0F0_DEVEN, tmp & ~HYBRID_GRAPHICS_SEC_VGA_EN); ++ } ++} ++ ++static void hybrid_graphics_set_up_gpio(void) ++{ ++ uint32_t tmp; ++ ++ /* Enable hybrid graphics GPIO lines */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL); ++ tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL); ++ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_USE_SEL2); ++ tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_USE_SEL2); ++ ++ /* Set hybrid graphics control GPIO lines to output */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); ++ tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); ++ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL2); ++ tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL2); ++ ++ /* Set hybrid graphics detect GPIO lines to input */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_IO_SEL); ++ tmp = tmp | HYBRID_GRAPHICS_DETECT_GP_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_IO_SEL); ++} ++ ++static bool hybrid_graphics_installed(void) ++{ ++ if (inl(DEFAULT_GPIOBASE + GP_LVL) & HYBRID_GRAPHICS_DETECT_GP_BITS) ++ return false; ++ else ++ return true; ++} ++ ++static void hybrid_graphics_switch_to_integrated_graphics(void) ++{ ++ uint32_t tmp; ++ ++ /* Disable switchable graphics */ ++ hybrid_graphics_configure_switchable_graphics(false); ++ ++ /* Configure muxes */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_LVL); ++ tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_LVL); ++ ++ tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); ++ tmp = tmp & ~HYBRID_GRAPHICS_GP_LVL2_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); ++} ++ ++static void hybrid_graphics_switch_to_discrete_graphics(void) ++{ ++ uint32_t tmp; ++ ++ /* Disable switchable graphics */ ++ hybrid_graphics_configure_switchable_graphics(false); ++ ++ /* Configure muxes */ ++ tmp = inl(DEFAULT_GPIOBASE + GP_LVL); ++ tmp = tmp | HYBRID_GRAPHICS_GP_LVL_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_LVL); ++ ++ tmp = inl(DEFAULT_GPIOBASE + GP_LVL2); ++ tmp = tmp | HYBRID_GRAPHICS_GP_LVL2_BITS; ++ outl(tmp, DEFAULT_GPIOBASE + GP_LVL2); ++} ++ ++static void hybrid_graphics_switch_to_dual_graphics(void) ++{ ++ /* Enable switchable graphics */ ++ hybrid_graphics_configure_switchable_graphics(true); ++} ++ + static void default_southbridge_gpio_setup(void) + { + outl(0x197e23fe, DEFAULT_GPIOBASE + GP_IO_USE_SEL); +@@ -95,6 +208,31 @@ void mainboard_romstage_entry(unsigned long bist) + + default_southbridge_gpio_setup(); + ++ uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; ++ get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); ++ ++ /* Set up hybrid graphics */ ++ hybrid_graphics_set_up_gpio(); ++ if (hybrid_graphics_installed()) { ++ /* Select appropriate hybrid graphics device */ ++ printk(BIOS_DEBUG, "Hybrid graphics available, setting mode %d\n", hybrid_graphics_mode); ++ if (hybrid_graphics_mode == HYBRID_GRAPHICS_INTEGRATED_ONLY) ++ hybrid_graphics_switch_to_integrated_graphics(); ++ else if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE_ONLY) ++ hybrid_graphics_switch_to_discrete_graphics(); ++ else if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) ++ hybrid_graphics_switch_to_integrated_graphics(); ++ /* Switchable graphics are fully enabled after raminit */ ++ /* FIXME ++ * Enabling switchable graphics prevents bootup! ++ * Debug and fix appropriately... ++ */ ++ } ++ else { ++ printk(BIOS_DEBUG, "Hybrid graphics not installed\n"); ++ hybrid_graphics_switch_to_integrated_graphics(); ++ } ++ + /* ASPM related setting, set early by original BIOS. */ + DMIBAR16(0x204) &= ~(3 << 10); + +@@ -174,6 +312,11 @@ void mainboard_romstage_entry(unsigned long bist) + outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38); + + cbmem_initted = !cbmem_recovery(s3resume); ++ ++ if (hybrid_graphics_installed()) ++ if (hybrid_graphics_mode == HYBRID_GRAPHICS_SWITCHABLE) ++ hybrid_graphics_switch_to_dual_graphics(); ++ + #if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. +-- +2.9.2 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch new file mode 100644 index 00000000..49b9549a --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch @@ -0,0 +1,35 @@ +From 873402fb594f06e748563ebf3abc7970613b9bda Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 8 Aug 2016 23:55:13 +0200 +Subject: [PATCH] make 256M vram the default for gm45 laptops + +Change-Id: Id213807d1ed3260846118f69b459bcad7a146c30 + +diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default +index 98ce970..90d796f 100644 +--- a/src/mainboard/lenovo/t400/cmos.default ++++ b/src/mainboard/lenovo/t400/cmos.default +@@ -13,4 +13,5 @@ sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI +-hybrid_graphics_mode=Integrated Only +\ No newline at end of file ++hybrid_graphics_mode=Integrated Only ++gfx_uma_size=256M +\ No newline at end of file +diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default +index 1d7b420..ec7ab46 100644 +--- a/src/mainboard/lenovo/x200/cmos.default ++++ b/src/mainboard/lenovo/x200/cmos.default +@@ -13,4 +13,4 @@ sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI +-gfx_uma_size=32M +\ No newline at end of file ++gfx_uma_size=256M +\ No newline at end of file +-- +2.9.2 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch new file mode 100644 index 00000000..76463937 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch @@ -0,0 +1,27 @@ +From 99b8fb271fd244d8e349ca956819c7e1b3420d80 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Mon, 8 Aug 2016 21:51:34 +0200 +Subject: [PATCH] hardcode use on intel integrated graphic device on t400 + +Change-Id: I2ff2d93b024866063715d26aedf510a9753a5445 +--- + src/mainboard/lenovo/t400/romstage.c | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c +index 147131f..1316d69 100644 +--- a/src/mainboard/lenovo/t400/romstage.c ++++ b/src/mainboard/lenovo/t400/romstage.c +@@ -208,7 +208,8 @@ void main(unsigned long bist) + default_southbridge_gpio_setup(); + + uint8_t hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED_ONLY; +- get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); ++ /* hardcode use of integrated graphic device for libreboot */ ++ /* get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); */ + + /* Set up hybrid graphics */ + hybrid_graphics_set_up_gpio(); +-- +2.9.2 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/INFO new file mode 100644 index 00000000..9ef6d54a --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/INFO @@ -0,0 +1,8 @@ +# NOTE: merged upstream already +printf "mainboard/lenovo/t400: Add initial hybrid graphics support\n" +git am "../resources/libreboot/patch/misc/0001-mainboard-lenovo-t400-Add-initial-hybrid-graphics-su.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/19/9319/18 && git cherry-pick FETCH_HEAD + +printf "NOTFORMERGE: lenovo/t400: hard-code enable integrated-only video\n" +git am "../resources/libreboot/patch/misc/0002-NOTFORMERGE-lenovo-t400-hard-code-enable-integrated-.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/50/10550/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/reused.list new file mode 100644 index 00000000..524ef8f6 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/reused.list @@ -0,0 +1,3 @@ +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_16mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_16mb/INFO new file mode 100644 index 00000000..0537bbc8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_16mb/INFO @@ -0,0 +1,4 @@ +# NOTE: remove this when updating coreboot. This has been merged upstream +printf "ThinkPad T500 (depends on T400 patch)\n" +git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_16mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_16mb/reused.list new file mode 100644 index 00000000..0f4bf368 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_16mb/reused.list @@ -0,0 +1,6 @@ +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_4mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_4mb/reused.list new file mode 100644 index 00000000..0f4bf368 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_4mb/reused.list @@ -0,0 +1,6 @@ +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_8mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_8mb/INFO new file mode 100644 index 00000000..0537bbc8 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_8mb/INFO @@ -0,0 +1,4 @@ +# NOTE: remove this when updating coreboot. This has been merged upstream +printf "ThinkPad T500 (depends on T400 patch)\n" +git am "../resources/libreboot/patch/misc/0008-lenovo-t500-Add-clone-of-Lenovo-T400.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/45/10545/1 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_8mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_8mb/reused.list new file mode 100644 index 00000000..0f4bf368 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t500_8mb/reused.list @@ -0,0 +1,6 @@ +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0001-Revert-hybrid-driver.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0002-make-256M-vram-the-default-for-gm45-laptops.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t400_8mb/0003-hardcode-use-on-intel-integrated-graphic-device-on-t.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/0001-lenovo-t60-Enable-brightness-controls-native-graphic.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/0001-lenovo-t60-Enable-brightness-controls-native-graphic.patch new file mode 100644 index 00000000..2e3ee65b --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/0001-lenovo-t60-Enable-brightness-controls-native-graphic.patch @@ -0,0 +1,36 @@ +From 770021ce66a0fddebb9639c4df0696ecfca45488 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Mon, 15 Jun 2015 19:59:46 +0100 +Subject: [PATCH 4/9] lenovo/t60: Enable brightness controls (native graphics) + +This makes the Fn Home/End keys work for controlling the +brightness of the display. Value obtained by reading +BLC_PWM_CTL when running the VBIOS (option ROM). + +On i945 legacy brightness control is enabled by a single +bit in BLC_PWM_CTL. It's bit 16 or bit 0 (the other one +reverses polarity). Set the bit to enable brightness +controls. + +Change-Id: I22e261f2ce28ec81cd208a73e6311ec67146eb72 +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/mainboard/lenovo/t60/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb +index b28f1ad..9e6ce02 100644 +--- a/src/mainboard/lenovo/t60/devicetree.cb ++++ b/src/mainboard/lenovo/t60/devicetree.cb +@@ -26,7 +26,7 @@ chip northbridge/intel/i945 + + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "1" +- register "gpu_backlight" = "0x1280128" ++ register "gpu_backlight" = "0x58BF58BE" + + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch new file mode 100644 index 00000000..0b8e146a --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/0001-lenovo-t60-add-hda_verb.c.patch @@ -0,0 +1,53 @@ +From bbd04909524d7b9fd2e2b4dbd804801bbde66e44 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Wed, 7 Sep 2016 21:16:21 +0200 +Subject: [PATCH] lenovo/t60: add hda_verb.c + +This creates a config for the Lenovo T60 sound card based +on values taken from vendor bios +(in /sys/class/sound/hwC0D0/init_pin_configs on linux 3.16). +The sound card configuration on the vendor bios is the same +as the one on the Lenovo x60. + +It improves the default behavior of the sound card: +- internal microphone is chosen by default +- when jack is inserted it is chosen instead of internal speaker + +Change-Id: I44e3eaac437fe4ad97ff2b0eb32d36b33222c09b +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/mainboard/lenovo/t60/hda_verb.c | 19 +++++++++++++++++-- + 1 file changed, 17 insertions(+), 2 deletions(-) + +diff --git a/src/mainboard/lenovo/t60/hda_verb.c b/src/mainboard/lenovo/t60/hda_verb.c +index 072a306..dee3e80 100644 +--- a/src/mainboard/lenovo/t60/hda_verb.c ++++ b/src/mainboard/lenovo/t60/hda_verb.c +@@ -1,7 +1,22 @@ + #include <device/azalia_device.h> + +-const u32 cim_verb_data[0] = {}; ++const u32 cim_verb_data[] = { ++ 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ ++ 0x17aa2025, /* Subsystem ID */ ++ 0x0000000b, /* Number of 4 dword sets */ + +-const u32 pc_beep_verbs[0] = {}; ++ AZALIA_SUBVENDOR(0x0, 0x17aa2025), + ++ AZALIA_PIN_CFG(0, 0x05, 0xc3014110), ++ AZALIA_PIN_CFG(0, 0x06, 0x4221401f), ++ AZALIA_PIN_CFG(0, 0x07, 0x591311f0), ++ AZALIA_PIN_CFG(0, 0x08, 0xc3a15020), ++ AZALIA_PIN_CFG(0, 0x09, 0x41813021), ++ AZALIA_PIN_CFG(0, 0x0a, 0x014470f0), ++ AZALIA_PIN_CFG(0, 0x16, 0x59f311f0), ++ AZALIA_PIN_CFG(0, 0x17, 0x59931122), ++ AZALIA_PIN_CFG(0, 0x18, 0x41a19023), ++ AZALIA_PIN_CFG(0, 0x19, 0x9933e12e) ++}; ++const u32 pc_beep_verbs[0] = {}; + AZALIA_ARRAY_SIZES; +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/INFO new file mode 100644 index 00000000..cb543aae --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/INFO @@ -0,0 +1,3 @@ +printf "lenovo/t60: Enable brightness controls (native graphics)\n" +git am "../resources/libreboot/patch/misc/0004-lenovo-t60-Enable-brightness-controls-native-graphic.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/52/10552/2 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/reused.list new file mode 100644 index 00000000..4777e941 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/t60/reused.list @@ -0,0 +1,4 @@ +/resources/libreboot/patch/coreboot/8ba2010d126ce7a6d32504bcb2a0e1b231732c0f/grub/x60/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/8ba2010d126ce7a6d32504bcb2a0e1b231732c0f/grub/x60/0001-i945-Enable-changing-VRAM-size.patch +/resources/libreboot/patch/coreboot/8ba2010d126ce7a6d32504bcb2a0e1b231732c0f/grub/x60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch +/resources/libreboot/patch/coreboot/8ba2010d126ce7a6d32504bcb2a0e1b231732c0f/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_16mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_16mb/INFO new file mode 100644 index 00000000..220b8583 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_16mb/INFO @@ -0,0 +1,5 @@ +# NOTE: remove this when updating to the latest version of coreboot. this patch +# makes the patch below redundant: https://review.coreboot.org/#/c/12814/ +printf "northbridge/gm45/raminit.c: enable GS45 high-perf (i.e. add X200S support to libreboot)\n" +git am "../resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/35/11135/3 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_16mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_16mb/reused.list new file mode 100644 index 00000000..fd3c8133 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_16mb/reused.list @@ -0,0 +1,4 @@ +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-set-default-vram-to-256M.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_4mb/reused.list b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_4mb/reused.list new file mode 100644 index 00000000..fd3c8133 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_4mb/reused.list @@ -0,0 +1,4 @@ +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-set-default-vram-to-256M.patch +/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch new file mode 100644 index 00000000..8e5e1dca --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch @@ -0,0 +1,88 @@ +From 63db6e96d846b8cab2df30afdccc6b6b18232e33 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Mon, 13 Oct 2014 00:14:53 +0100 +Subject: [PATCH] NOTFORMERGE: ec/lenovo/h8: + wlan/trackpoint/touchpad/bluetooth/wwan + +Permanently enable them. + +Change-Id: Ic76ab9ab9c865f30312378e18af58bece6c3260a +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/ec/lenovo/h8/h8.c | 21 +++++++++++---------- + src/ec/lenovo/pmh7/pmh7.c | 11 ++++------- + 2 files changed, 15 insertions(+), 17 deletions(-) + +diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c +index 943bdd4..32285ac 100644 +--- a/src/ec/lenovo/h8/h8.c ++++ b/src/ec/lenovo/h8/h8.c +@@ -252,9 +252,11 @@ static void h8_enable(struct device *dev) + + ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); + +- if (get_option(&val, "wlan") != CB_SUCCESS) +- val = 1; +- h8_wlan_enable(val); ++ // Permanently enable wifi ++ // Intel wifi could be a security risk because it uses firmware. Wlan chip has DMA ++ // and could leak data over a side-channel. Using another manufacturer is recommended. ++ // see http://libreboot.org/docs/index.html#recommended_wifi ++ h8_wlan_enable(1); + + h8_trackpoint_enable(1); + h8_usb_power_enable(1); +@@ -262,14 +264,13 @@ static void h8_enable(struct device *dev) + if (get_option(&val, "volume") == CB_SUCCESS && !acpi_is_wakeup_s3()) + ec_write(H8_VOLUME_CONTROL, val); + +- if (get_option(&val, "bluetooth") != CB_SUCCESS) +- val = 1; +- h8_bluetooth_enable(val); +- +- if (get_option(&val, "wwan") != CB_SUCCESS) +- val = 1; ++ // Permanently enable bluetooth. ++ // NOTE: bluetooth is a potential security risk. Physical removal of the bluetooth module is recommended. ++ h8_bluetooth_enable(1); + +- h8_wwan_enable(val); ++ // Permanently enable wwan. ++ // NOTE: wwan is a security risk (remove access plus DMA). Physical removal of both the wwan and sim card is recommended. ++ h8_wwan_enable(1); + + if (conf->has_uwb) { + if (get_option(&val, "uwb") != CB_SUCCESS) +diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c +index b2c3c08..1570cd6 100644 +--- a/src/ec/lenovo/pmh7/pmh7.c ++++ b/src/ec/lenovo/pmh7/pmh7.c +@@ -102,7 +102,6 @@ static void enable_dev(struct device *dev) + { + struct ec_lenovo_pmh7_config *conf = dev->chip_info; + struct resource *resource; +- u8 val; + + resource = new_resource(dev, EC_LENOVO_PMH7_INDEX); + resource->flags = IORESOURCE_IO | IORESOURCE_FIXED; +@@ -114,13 +113,11 @@ static void enable_dev(struct device *dev) + pmh7_backlight_enable(conf->backlight_enable); + pmh7_dock_event_enable(conf->dock_event_enable); + +- if (get_option(&val, "touchpad") != CB_SUCCESS) +- val = 1; +- pmh7_touchpad_enable(val); ++ // Permanently enable touchpad ++ pmh7_touchpad_enable(1); + +- if (get_option(&val, "trackpoint") != CB_SUCCESS) +- val = 1; +- pmh7_trackpoint_enable(val); ++ // Permanently enable trackpoint ++ pmh7_trackpoint_enable(1); + } + + struct chip_operations ec_lenovo_pmh7_ops = { +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch new file mode 100644 index 00000000..046192dd --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-add-acpi-c3-cpu-c4-state-for-gm45-thinpads.patch @@ -0,0 +1,45 @@ +From c63113e56ad2d5f6b318a837e4345e0e962a5c1b Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Wed, 4 May 2016 22:49:07 +0200 +Subject: [PATCH 1/1] add acpi c3 / cpu c4 state for gm45 thinpads + +--- + src/mainboard/lenovo/t400/cstates.c | 5 +++++ + src/mainboard/lenovo/x200/cstates.c | 5 +++++ + 2 files changed, 10 insertions(+) + +diff --git a/src/mainboard/lenovo/t400/cstates.c b/src/mainboard/lenovo/t400/cstates.c +index 827f76e..7d92d6f 100644 +--- a/src/mainboard/lenovo/t400/cstates.c ++++ b/src/mainboard/lenovo/t400/cstates.c +@@ -27,6 +27,11 @@ static acpi_cstate_t cst_entries[] = { + /* acpi C2 / cpu C2 */ + 2, 0x01, 500, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } ++ }, ++ { ++ /* acpi C3 / cpu C4 */ ++ 3, 0x02, 300, ++ { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x30, 0 } + }, + }; + +diff --git a/src/mainboard/lenovo/x200/cstates.c b/src/mainboard/lenovo/x200/cstates.c +index 827f76e..7d92d6f 100644 +--- a/src/mainboard/lenovo/x200/cstates.c ++++ b/src/mainboard/lenovo/x200/cstates.c +@@ -27,6 +27,11 @@ static acpi_cstate_t cst_entries[] = { + /* acpi C2 / cpu C2 */ + 2, 0x01, 500, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } ++ }, ++ { ++ /* acpi C3 / cpu C4 */ ++ 3, 0x02, 300, ++ { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x30, 0 } + }, + }; + +-- +2.8.2 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch new file mode 100644 index 00000000..d89e4884 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-nb-intel-gm45-Fix-IOMMU.patch @@ -0,0 +1,50 @@ +From 0821d0290e7e17e375ffdb48a86b56504db4f77e Mon Sep 17 00:00:00 2001 +From: Damien Zammit <damien@zamaudio.com> +Date: Sat, 27 Aug 2016 00:35:48 +1000 +Subject: [PATCH] nb/intel/gm45: Fix IOMMU + +Previously the ME was being reported as present in ACPI +even when it's firmware was missing. Now we do a check via the pci device +(HECI) to verify if the ME is there or not. + +Note that this test could fail if ME is present but disabled in devicetree, +but in that case you won't see it in the lspci tree anyway so it shouldn't +be an issue. + +Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0 +Signed-off-by: Damien Zammit <damien@zamaudio.com> +--- + src/northbridge/intel/gm45/acpi.c | 3 ++- + src/northbridge/intel/gm45/iommu.c | 2 ++ + 2 files changed, 4 insertions(+), 1 deletion(-) + +diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c +index 8990c3b..b90afca 100644 +--- a/src/northbridge/intel/gm45/acpi.c ++++ b/src/northbridge/intel/gm45/acpi.c +@@ -72,7 +72,8 @@ unsigned long acpi_fill_mcfg(unsigned long current) + + static unsigned long acpi_fill_dmar(unsigned long current) + { +- int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL); ++ int me_active = (dev_find_slot(0, PCI_DEVFN(3, 0)) != NULL) && ++ (pci_read_config8(dev_find_slot(0, PCI_DEVFN(3, 0)), PCI_CLASS_REVISION) != 0xff); + int stepping = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), PCI_CLASS_REVISION); + + unsigned long tmp = current; +diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c +index 10548f4..0c3c18e 100644 +--- a/src/northbridge/intel/gm45/iommu.c ++++ b/src/northbridge/intel/gm45/iommu.c +@@ -40,6 +40,8 @@ void init_iommu() + } + if (me_active) { + MCHBAR32(0x10) = IOMMU_BASE3 | 1; /* ME @ 0:3.0-3 */ ++ } else { ++ MCHBAR32(0x10) = 0; /* disable IOMMU for ME */ + } + MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */ + +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-set-default-vram-to-256M.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-set-default-vram-to-256M.patch new file mode 100644 index 00000000..01124c34 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/0001-set-default-vram-to-256M.patch @@ -0,0 +1,38 @@ +From c98d8745d4dca650709e76269cf014e5ffbc1443 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Tue, 9 Aug 2016 00:54:37 +0200 +Subject: [PATCH] set default vram to 256M + +Change-Id: Ife906c47f32493d9a647a4f12f25982623eba189 +--- + src/mainboard/lenovo/t400/cmos.default | 2 +- + src/mainboard/lenovo/x200/cmos.default | 2 +- + 2 files changed, 2 insertions(+), 2 deletions(-) + +diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default +index 5cf3e63..90d796f 100644 +--- a/src/mainboard/lenovo/t400/cmos.default ++++ b/src/mainboard/lenovo/t400/cmos.default +@@ -14,4 +14,4 @@ power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI + hybrid_graphics_mode=Integrated Only +-gfx_uma_size=32M +\ No newline at end of file ++gfx_uma_size=256M +\ No newline at end of file +diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default +index 1d7b420..ec7ab46 100644 +--- a/src/mainboard/lenovo/x200/cmos.default ++++ b/src/mainboard/lenovo/x200/cmos.default +@@ -13,4 +13,4 @@ sticky_fn=Disable + power_management_beeps=Enable + low_battery_beep=Enable + sata_mode=AHCI +-gfx_uma_size=32M +\ No newline at end of file ++gfx_uma_size=256M +\ No newline at end of file +-- +2.9.2 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/INFO new file mode 100644 index 00000000..220b8583 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x200_8mb/INFO @@ -0,0 +1,5 @@ +# NOTE: remove this when updating to the latest version of coreboot. this patch +# makes the patch below redundant: https://review.coreboot.org/#/c/12814/ +printf "northbridge/gm45/raminit.c: enable GS45 high-perf (i.e. add X200S support to libreboot)\n" +git am "../resources/libreboot/patch/misc/0006-northbridge-gm45-raminit.c-enable-GS45-high-performa.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/35/11135/3 && git cherry-pick FETCH_HEAD diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch new file mode 100644 index 00000000..6f8b5307 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0001-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch @@ -0,0 +1,88 @@ +From 1024b5e6c476dcc195dca742746735277f63236b Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Mon, 13 Oct 2014 00:14:53 +0100 +Subject: [PATCH 5/9] NOTFORMERGE: ec/lenovo/h8: + wlan/trackpoint/touchpad/bluetooth/wwan + +Permanently enable them. + +Change-Id: Ic76ab9ab9c865f30312378e18af58bece6c3260a +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/ec/lenovo/h8/h8.c | 21 +++++++++++---------- + src/ec/lenovo/pmh7/pmh7.c | 11 ++++------- + 2 files changed, 15 insertions(+), 17 deletions(-) + +diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c +index 2cafc88..a6cb6b6 100644 +--- a/src/ec/lenovo/h8/h8.c ++++ b/src/ec/lenovo/h8/h8.c +@@ -255,9 +255,11 @@ static void h8_enable(struct device *dev) + + ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); + +- if (get_option(&val, "wlan") != CB_SUCCESS) +- val = 1; +- h8_wlan_enable(val); ++ // Permanently enable wifi ++ // Intel wifi could be a security risk because it uses firmware. Wlan chip has DMA ++ // and could leak data over a side-channel. Using another manufacturer is recommended. ++ // see http://libreboot.org/docs/index.html#recommended_wifi ++ h8_wlan_enable(1); + + h8_trackpoint_enable(1); + h8_usb_power_enable(1); +@@ -265,14 +267,13 @@ static void h8_enable(struct device *dev) + if (get_option(&val, "volume") == CB_SUCCESS) + ec_write(H8_VOLUME_CONTROL, val); + +- if (get_option(&val, "bluetooth") != CB_SUCCESS) +- val = 1; +- h8_bluetooth_enable(val); +- +- if (get_option(&val, "wwan") != CB_SUCCESS) +- val = 1; ++ // Permanently enable bluetooth. ++ // NOTE: bluetooth is a potential security risk. Physical removal of the bluetooth module is recommended. ++ h8_bluetooth_enable(1); + +- h8_wwan_enable(val); ++ // Permanently enable wwan. ++ // NOTE: wwan is a security risk (remove access plus DMA). Physical removal of both the wwan and sim card is recommended. ++ h8_wwan_enable(1); + + if (conf->has_uwb) { + if (get_option(&val, "uwb") != CB_SUCCESS) +diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c +index cc6e891..38aef16 100644 +--- a/src/ec/lenovo/pmh7/pmh7.c ++++ b/src/ec/lenovo/pmh7/pmh7.c +@@ -106,7 +106,6 @@ static void enable_dev(struct device *dev) + { + struct ec_lenovo_pmh7_config *conf = dev->chip_info; + struct resource *resource; +- u8 val; + + resource = new_resource(dev, EC_LENOVO_PMH7_INDEX); + resource->flags = IORESOURCE_IO | IORESOURCE_FIXED; +@@ -118,13 +117,11 @@ static void enable_dev(struct device *dev) + pmh7_backlight_enable(conf->backlight_enable); + pmh7_dock_event_enable(conf->dock_event_enable); + +- if (get_option(&val, "touchpad") != CB_SUCCESS) +- val = 1; +- pmh7_touchpad_enable(val); ++ // Permanently enable touchpad ++ pmh7_touchpad_enable(1); + +- if (get_option(&val, "trackpoint") != CB_SUCCESS) +- val = 1; +- pmh7_trackpoint_enable(val); ++ // Permanently enable trackpoint ++ pmh7_trackpoint_enable(1); + } + + struct chip_operations ec_lenovo_pmh7_ops = { +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0001-i945-Enable-changing-VRAM-size.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0001-i945-Enable-changing-VRAM-size.patch new file mode 100644 index 00000000..ce1d37c0 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0001-i945-Enable-changing-VRAM-size.patch @@ -0,0 +1,158 @@ +From 44b3d02a49bc25dc8e9119a11bd948db2c37a931 Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Sun, 15 May 2016 02:17:12 +0200 +Subject: [PATCH] i945: Enable changing VRAM size + +On i945 the vram size was the default 8mb. It was also possible +to set it 1mb or 0mb hardcoding the GGC register in early_init.c + +The intel documentation on i945 only documents those three options. +They are set using 3 bits. The documententation also makes mention +of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it. + +The other non documented (straight forward) bit combinations allows +to change the VRAM size to those other states. + +Change-Id: I5e510e81322a4c8315c01b7963ac4b5f7f58a17e +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> + +diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig +index 6e8d35b..484ed78 100644 +--- a/src/northbridge/intel/i945/Kconfig ++++ b/src/northbridge/intel/i945/Kconfig +@@ -72,3 +72,56 @@ config CHECK_SLFRCS_ON_RESUME + effectively making it impossible to resume. + + endif ++ ++config VRAM_CHOICE ++ bool ++choice ++ prompt "VRAM Size" ++ depends on NORTHBRIDGE_INTEL_I945 ++ default VRAM_SIZE_8MB ++ help ++ Set the size of vram that the integrated graphic device can use ++ for a framebuffer. ++ ++config VRAM_SIZE_1MB ++ bool "1 MB" ++ help ++ Set VRAM size to 1MB. ++config VRAM_SIZE_4MB ++ bool "4 MB" ++ help ++ Set VRAM size to 4MB. ++config VRAM_SIZE_8MB ++ bool "8 MB" ++ help ++ Set VRAM size to 8MB. ++config VRAM_SIZE_16MB ++ bool "16 MB" ++ help ++ Set VRAM size to 16MB. ++config VRAM_SIZE_32MB ++ bool "32 MB" ++ help ++ Set VRAM size to 32MB. ++config VRAM_SIZE_48MB ++ bool "48 MB" ++ help ++ Set VRAM size to 48MB. ++config VRAM_SIZE_64MB ++ bool "64 MB" ++ help ++ Set VRAM size to 64MB. ++ ++endchoice ++ ++config VRAM_SIZE ++ hex ++ default 0x10 if VRAM_SIZE_1MB ++ default 0x20 if VRAM_SIZE_4MB ++ default 0x30 if VRAM_SIZE_8MB ++ default 0x40 if VRAM_SIZE_16MB ++ default 0x50 if VRAM_SIZE_32MB ++ default 0x60 if VRAM_SIZE_48MB ++ default 0x70 if VRAM_SIZE_64MB ++ help ++ map the vram sizes to an integer. +diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c +index 475e88a..bd062ad 100644 +--- a/src/northbridge/intel/i945/early_init.c ++++ b/src/northbridge/intel/i945/early_init.c +@@ -177,11 +177,8 @@ static void i945_setup_bars(void) + pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); + pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); + +- /* Hardware default is 8MB UMA. If someone wants to make this a +- * CMOS or compile time option, send a patch. +- * pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, 0x30); +- */ +- ++ /* Sets up VRAM size from the build option VRAM_SIZE */ ++ pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, CONFIG_VRAM_SIZE); + /* Set C0000-FFFFF to access RAM on both reads and writes */ + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); + pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index df13ef4..f853cc8 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -359,9 +359,24 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + case 1: + uma_size = 1024; + break; ++ case 2: ++ uma_size = 4096; ++ break; + case 3: + uma_size = 8192; + break; ++ case 4: ++ uma_size = 16384; ++ break; ++ case 5: ++ uma_size = 32768; ++ break; ++ case 6: ++ uma_size = 49152; ++ break; ++ case 7: ++ uma_size = 65536; ++ break; + } + + printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); +diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c +index 514f88c..4be9827 100644 +--- a/src/northbridge/intel/i945/northbridge.c ++++ b/src/northbridge/intel/i945/northbridge.c +@@ -112,9 +112,24 @@ static void pci_domain_set_resources(device_t dev) + case 1: + uma_size = 1024; + break; ++ case 2: ++ uma_size = 4096; ++ break; + case 3: + uma_size = 8192; + break; ++ case 4: ++ uma_size = 16384; ++ break; ++ case 5: ++ uma_size = 32768; ++ break; ++ case 6: ++ uma_size = 49152; ++ break; ++ case 7: ++ uma_size = 65536; ++ break; + } + + printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10); +-- +2.8.2 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0001-lenovo-x60-add-hda_verb.c.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0001-lenovo-x60-add-hda_verb.c.patch new file mode 100644 index 00000000..80eda28b --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0001-lenovo-x60-add-hda_verb.c.patch @@ -0,0 +1,65 @@ +From 4f3452fc544d4e799445c3271b1022496932473c Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Fri, 3 Jun 2016 18:37:38 +0200 +Subject: [PATCH] lenovo/x60: add hda_verb.c + +This creates a config for the x60 audio based +on values taken from vendor bios. + +What is improved: +- internal microphone is chosen by default +- when jack is inserted it chosen instead of internal speaker + +Before this had to be done manually. + +Change-Id: Id3b700fd84905a72cc1f69e7d8bfa6145f231756 +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> + +diff --git a/src/mainboard/lenovo/x60/hda_verb.c b/src/mainboard/lenovo/x60/hda_verb.c +index 072a306..c4b1f3a 100644 +--- a/src/mainboard/lenovo/x60/hda_verb.c ++++ b/src/mainboard/lenovo/x60/hda_verb.c +@@ -1,7 +1,38 @@ ++/* ++ * This file is part of the coreboot project. ++ * ++ * Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; version 2 of ++ * the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ + #include <device/azalia_device.h> + +-const u32 cim_verb_data[0] = {}; ++const u32 cim_verb_data[] = { ++ 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ ++ 0x17aa2025, /* Subsystem ID */ ++ 0x0000000b, /* Number of 4 dword sets */ + +-const u32 pc_beep_verbs[0] = {}; ++ AZALIA_SUBVENDOR(0x0, 0x17aa2025), + ++ AZALIA_PIN_CFG(0, 0x05, 0xc3014110), ++ AZALIA_PIN_CFG(0, 0x06, 0x4221401f), ++ AZALIA_PIN_CFG(0, 0x07, 0x591311f0), ++ AZALIA_PIN_CFG(0, 0x08, 0xc3a15020), ++ AZALIA_PIN_CFG(0, 0x09, 0x41813021), ++ AZALIA_PIN_CFG(0, 0x0a, 0x014470f0), ++ AZALIA_PIN_CFG(0, 0x16, 0x59f311f0), ++ AZALIA_PIN_CFG(0, 0x17, 0x59931122), ++ AZALIA_PIN_CFG(0, 0x18, 0x41a19023), ++ AZALIA_PIN_CFG(0, 0x19, 0x9933e12e) ++}; ++const u32 pc_beep_verbs[0] = {}; + AZALIA_ARRAY_SIZES; +-- +2.8.3 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0002-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0002-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch new file mode 100644 index 00000000..7470dd60 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0002-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch @@ -0,0 +1,31 @@ +From e4b5b65c93122126344771f2042f8d7a3468be19 Mon Sep 17 00:00:00 2001 +From: Leah Rowe <info@minifree.org> +Date: Mon, 22 Jun 2015 17:37:06 +0100 +Subject: [PATCH 3/9] lenovo/x60: use correct BLC_PWM_CTL value + +Bit 16 in BLC_PWM_CTL enables brightness controls, but the +current value is generic. Use the proper value, obtained +by reading BLC_PWM_CTL while running the VBIOS. + +Change-Id: Ib273359e1c285b405a9bb26fc217c2f7e255b99f +Signed-off-by: Leah Rowe <info@minifree.org> +--- + src/mainboard/lenovo/x60/devicetree.cb | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb +index b4d1144..4d62116 100644 +--- a/src/mainboard/lenovo/x60/devicetree.cb ++++ b/src/mainboard/lenovo/x60/devicetree.cb +@@ -26,7 +26,7 @@ chip northbridge/intel/i945 + + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "1" +- register "gpu_backlight" = "0x1290128" ++ register "gpu_backlight" = "0x879F879E" + + device cpu_cluster 0 on + chip cpu/intel/socket_mFCPGA478 +-- +1.9.1 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch new file mode 100644 index 00000000..86bd6cb0 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0003-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch @@ -0,0 +1,174 @@ +From 34f8cdbc30f1fdf4700c73aad26e0fc159af70ab Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Fri, 2 Sep 2016 22:35:32 +0200 +Subject: [PATCH] i945/gma.c use latest linux code to calculate divisors. + +The code to compute n, m1, m2, p1 divisors is not correct in coreboot and +on some targets hits a working mode at lower refresh rate, which is why +display is working on some targets. +This patch also fixes reference frequency. + +This patch reuses linux code to correctly compute divisors. + +The result is that some previously not working displays (Lenovo T60 with +1024x786, 1400x1050, 2048x1536) + +TESTED on T60 with 1024x786. + +Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e +Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> +--- + src/northbridge/intel/i945/gma.c | 82 +++++++++++++++++++--------------------- + 1 file changed, 38 insertions(+), 44 deletions(-) + +diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c +index 02caa0a..3f0b5b4 100644 +--- a/src/northbridge/intel/i945/gma.c ++++ b/src/northbridge/intel/i945/gma.c +@@ -26,6 +26,8 @@ + #include <string.h> + #include <pc80/vga.h> + #include <pc80/vga_io.h> ++#include <commonlib/helpers.h> ++ + + #include "i945.h" + #include "chip.h" +@@ -43,7 +45,7 @@ + #define PGETBL_CTL 0x2020 + #define PGETBL_ENABLED 0x00000001 + +-#define BASE_FREQUENCY 120000 ++#define BASE_FREQUENCY 100000 + + #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT + +@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + u8 edid_data[128]; + unsigned long temp; + int hpolarity, vpolarity; +- u32 candp1, candn; +- u32 best_delta = 0xffffffff; ++ u32 smallest_err = 0xffffffff; + u32 target_frequency; + u32 pixel_p1 = 1; ++ u32 pixel_p2; + u32 pixel_n = 1; + u32 pixel_m1 = 1; + u32 pixel_m2 = 1; +@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug); + write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS); + +- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock +- : (2 * mode->pixel_clock); +- +- /* Find suitable divisors. */ +- for (candp1 = 1; candp1 <= 8; candp1++) { +- for (candn = 5; candn <= 10; candn++) { +- u32 cur_frequency; +- u32 m; /* 77 - 131. */ +- u32 denom; /* 35 - 560. */ +- u32 current_delta; +- +- denom = candn * candp1 * 7; +- /* Doesnt overflow for up to +- 5000000 kHz = 5 GHz. */ +- m = (target_frequency * denom +- + BASE_FREQUENCY / 2) / BASE_FREQUENCY; +- +- if (m < 77 || m > 131) +- continue; +- +- cur_frequency = (BASE_FREQUENCY * m) / denom; +- if (target_frequency > cur_frequency) +- current_delta = target_frequency - cur_frequency; +- else +- current_delta = cur_frequency - target_frequency; +- +- if (best_delta > current_delta) { +- best_delta = current_delta; +- pixel_n = candn; +- pixel_p1 = candp1; +- pixel_m2 = ((m + 3) % 5) + 7; +- pixel_m1 = (m - pixel_m2) / 5; ++ pixel_p2 = mode->lvds_dual_channel ? 7 : 14; ++ target_frequency = mode->pixel_clock; ++ ++ /* Find suitable divisors, m1, m2, p1, n. */ ++ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */ ++ /* should be closest to target frequency as possible */ ++ u32 candn, candm1, candm2, candp1; ++ for (candm1 = 8; candm1 <= 18; candm1++) { ++ for (candm2 = 3; candm2 <= 7; candm2++) { ++ for (candn = 1; candn <= 6; candn++) { ++ for (candp1 = 1; candp1 <= 8; candp1++) { ++ u32 m = 5 * (candm1 + 2) + (candm2 + 2); ++ u32 p = candp1 * pixel_p2; ++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2); ++ u32 dot = DIV_ROUND_CLOSEST(vco, p); ++ u32 this_err = ABS(dot - target_frequency); ++ if ((m < 70) || (m > 120)) ++ continue; ++ if (this_err < smallest_err) { ++ smallest_err = this_err; ++ pixel_n = candn; ++ pixel_m1 = candm1; ++ pixel_m2 = candm2; ++ pixel_p1 = candp1; ++ } ++ } + } + } + } + +- if (best_delta == 0xffffffff) { ++ if (smallest_err == 0xffffffff) { + printk (BIOS_ERR, "Couldn't find GFX clock divisors\n"); + return -1; + } +@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", + pixel_n, pixel_m1, pixel_m2, pixel_p1); + printk(BIOS_DEBUG, "Pixel clock %d kHz\n", +- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n +- / (pixel_p1 * 7)); ++ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) / ++ (pixel_n + 2) / (pixel_p1 * pixel_p2)); + + #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) + write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16)); +@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS + | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK)); + write32(pmmio + FP0(1), +- ((pixel_n - 2) << 16) +- | ((pixel_m1 - 2) << 8) | pixel_m2); ++ (pixel_n << 16) ++ | (pixel_m1 << 8) | pixel_m2); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | + DPLL_VCO_ENABLE | DPLLB_MODE_LVDS +@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + | (conf->gpu_lvds_use_spread_spectrum_clock + ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV + : 0) +- | (pixel_p1 << 16) +- | (pixel_p1)); ++ | (0x10000 << pixel_p1)); + mdelay(1); + write32(pmmio + DPLL(1), + DPLL_VGA_MODE_DIS | +@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf, + | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 + : DPLLB_LVDS_P2_CLOCK_DIV_14) + | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13) +- | (pixel_p1 << 16) +- | (pixel_p1)); ++ | (0x10000 << pixel_p1)); + mdelay(1); + write32(pmmio + HTOTAL(1), + ((hactive + right_border + hblank - 1) << 16) +-- +2.9.3 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch new file mode 100644 index 00000000..14f809a9 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/0004-model_6ex-enable-C2E-C4E-dynamic-lvl-2-cache.patch @@ -0,0 +1,50 @@ +From 483bbb3ec7965ca2416fda9e11687bcd655d078d Mon Sep 17 00:00:00 2001 +From: Arthur Heymans <arthur@aheymans.xyz> +Date: Tue, 31 May 2016 16:51:59 +0200 +Subject: [PATCH] model_6ex: enable C2E, C4E, dynamic lvl 2 cache. + +Change-Id: Ie538d2145640c7b50ac0a0fa432d98ae2c4be060 + +diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c +index 6fa6d3a..8ff276a 100644 +--- a/src/cpu/intel/model_6ex/model_6ex_init.c ++++ b/src/cpu/intel/model_6ex/model_6ex_init.c +@@ -67,9 +67,10 @@ static void configure_c_states(void) + + msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr.lo |= (1 << 15); // config lock until next reset. ++ msr.lo |= (1 << 14); // Deeper Sleep + msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States + msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk +- // TODO Do we want Deep C4 and Dynamic L2 shrinking? ++ msr.lo |= (1 << 3); // Dynamic L2 + + /* Number of supported C-States */ + msr.lo &= ~7; +@@ -94,16 +95,20 @@ static void configure_misc(void) + msr_t msr; + + msr = rdmsr(IA32_MISC_ENABLE); +- msr.lo |= (1 << 3); /* TM1 enable */ ++ msr.lo |= (1 << 3); /* TM1 enable */ + msr.lo |= (1 << 13); /* TM2 enable */ + msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */ + + msr.lo |= (1 << 10); /* FERR# multiplexing */ + +- // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1 + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ ++ /* Enable C2E */ ++ msr.lo |= (1 << 26); ++ ++ /* Enable C4E */ ++ msr.hi |= (1 << (32 - 32)); // C4E ++ msr.hi |= (1 << (33 - 32)); // Hard C4E + +- // TODO Do we want Deep C4 and Dynamic L2 shrinking? + wrmsr(IA32_MISC_ENABLE, msr); + + msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ +-- +2.8.3 + diff --git a/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/INFO b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/INFO new file mode 100644 index 00000000..4f5931f9 --- /dev/null +++ b/resources/libreboot/patch/coreboot/29fc9bb855cb878aee263cd1fe110e3bb3e98c80/grub/x60/INFO @@ -0,0 +1,7 @@ +printf "lenovo/x60: use correct BLC_PWM_CTL value\n" +git am "../resources/libreboot/patch/misc/0003-lenovo-x60-use-correct-BLC_PWM_CTL-value.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/24/10624/2 && git cherry-pick FETCH_HEAD + +printf "ec/lenovo/h8: permanently enable wifi/trackpoint/touchpad/bluetooth/wwan\n" +git am "../resources/libreboot/patch/misc/0005-NOTFORMERGE-ec-lenovo-h8-wlan-trackpoint-touchpad-bl.patch" +# git fetch http://review.coreboot.org/coreboot refs/changes/58/7058/9 && git cherry-pick FETCH_HEAD |