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-rw-r--r--resources/libreboot/config/seabios/d945gclf/architecture1
-rw-r--r--resources/libreboot/config/seabios/d945gclf/cbrevision1
-rw-r--r--resources/libreboot/config/seabios/d945gclf/config598
-rw-r--r--resources/libreboot/config/seabios/d945gclf/vbootrevision1
-rw-r--r--resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-mb-intel-d945gclf-Disable-combined-mode-to-fix-SATA.patch31
-rw-r--r--resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-move-DIV_ROUND-macros-to-commonlib.patch93
-rw-r--r--resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0002-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch171
-rw-r--r--resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0003-i945-gma.c-add-native-VGA-init.patch238
-rw-r--r--resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0004-mb-intel-d945gclf-Allow-use-of-native-graphic-init.patch40
-rw-r--r--resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0005-i945-gma.c-Only-init-LVDS-if-it-is-present-on-the-de.patch97
10 files changed, 1271 insertions, 0 deletions
diff --git a/resources/libreboot/config/seabios/d945gclf/architecture b/resources/libreboot/config/seabios/d945gclf/architecture
new file mode 100644
index 00000000..5a9a476a
--- /dev/null
+++ b/resources/libreboot/config/seabios/d945gclf/architecture
@@ -0,0 +1 @@
+i386
diff --git a/resources/libreboot/config/seabios/d945gclf/cbrevision b/resources/libreboot/config/seabios/d945gclf/cbrevision
new file mode 100644
index 00000000..f6e726f0
--- /dev/null
+++ b/resources/libreboot/config/seabios/d945gclf/cbrevision
@@ -0,0 +1 @@
+36d405268f040208cd26902f3c0b5346f7d4d25b
diff --git a/resources/libreboot/config/seabios/d945gclf/config b/resources/libreboot/config/seabios/d945gclf/config
new file mode 100644
index 00000000..11151e71
--- /dev/null
+++ b/resources/libreboot/config/seabios/d945gclf/config
@@ -0,0 +1,598 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+CONFIG_USE_OPTION_TABLE=y
+# CONFIG_STATIC_OPTION_TABLE is not set
+# CONFIG_UNCOMPRESSED_RAMSTAGE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+# CONFIG_NO_XIP_EARLY_STAGES is not set
+CONFIG_EARLY_CBMEM_INIT=y
+# CONFIG_EARLY_CBMEM_LIST is not set
+# CONFIG_COLLECT_TIMESTAMPS is not set
+# CONFIG_USE_BLOBS is not set
+# CONFIG_COVERAGE is not set
+# CONFIG_RELOCATABLE_MODULES is not set
+# CONFIG_RELOCATABLE_RAMSTAGE is not set
+# CONFIG_NO_STAGE_CACHE is not set
+CONFIG_BOOTBLOCK_SIMPLE=y
+# CONFIG_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_CUSTOM=y
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_GENERIC_GPIO_LIB is not set
+# CONFIG_BOARD_ID_AUTO is not set
+# CONFIG_BOARD_ID_MANUAL is not set
+CONFIG_DEVICETREE="devicetree.cb"
+# CONFIG_RAM_CODE_SUPPORT is not set
+# CONFIG_BOOTSPLASH_IMAGE is not set
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AAEON is not set
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADI is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ARTECGROUP is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BACHMANN is not set
+# CONFIG_VENDOR_BAP is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIFFEROS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_CUBIETECH is not set
+# CONFIG_VENDOR_DIGITALLOGIC is not set
+# CONFIG_VENDOR_DMP is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_ESD is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GIZMOSPHERE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IEI is not set
+CONFIG_VENDOR_INTEL=y
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LINUTOP is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_PURISM is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="intel/d945gclf"
+CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
+CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_MAINBOARD_VENDOR="Intel"
+CONFIG_MAX_CPUS=4
+CONFIG_CACHE_ROM_SIZE_OVERRIDE=0
+CONFIG_CBFS_SIZE=0x80000
+CONFIG_UART_FOR_CONSOLE=0
+CONFIG_VGA_BIOS_ID="8086,27a2"
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+# CONFIG_VGA_BIOS is not set
+CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
+CONFIG_DCACHE_RAM_BASE=0xffaf8000
+CONFIG_DCACHE_RAM_SIZE=0x8000
+# CONFIG_HAS_LVDS is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
+CONFIG_POST_IO=y
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
+CONFIG_ID_SECTION_OFFSET=0x80
+# CONFIG_BOARD_EMULATION_QEMU_ARMV7 is not set
+# CONFIG_BOARD_EMULATION_QEMU_X86_I440FX is not set
+# CONFIG_BOARD_EMULATION_QEMU_POWER8 is not set
+# CONFIG_BOARD_EMULATION_QEMU_X86_Q35 is not set
+# CONFIG_BOARD_EMULATION_QEMU_UCB_RISCV is not set
+# CONFIG_BOARD_EMULATION_SPIKE_UCB_RISCV is not set
+CONFIG_POST_DEVICE=y
+# CONFIG_DRIVERS_PS2_KEYBOARD is not set
+CONFIG_TTYS0_LCS=3
+# CONFIG_BOARD_INTEL_AMENIA is not set
+# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
+# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
+# CONFIG_BOARD_INTEL_BAKERSPORT_FSP is not set
+# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
+# CONFIG_BOARD_INTEL_BAYLEYBAY_FSP is not set
+# CONFIG_BOARD_INTEL_CAMELBACKMOUNTAIN_FSP is not set
+# CONFIG_BOARD_INTEL_COUGAR_CANYON2 is not set
+# CONFIG_BOARD_INTEL_D510MO is not set
+# CONFIG_BOARD_INTEL_D810E2CB is not set
+CONFIG_BOARD_INTEL_D945GCLF=y
+# CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set
+# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
+# CONFIG_BOARD_INTEL_GALILEO is not set
+# CONFIG_BOARD_INTEL_KUNIMITSU is not set
+# CONFIG_BOARD_INTEL_LITTLEPLAINS is not set
+# CONFIG_BOARD_INTEL_MINNOWMAX is not set
+# CONFIG_BOARD_INTEL_MOHONPEAK is not set
+# CONFIG_BOARD_INTEL_MTARVON is not set
+# CONFIG_BOARD_INTEL_STARGO2 is not set
+# CONFIG_BOARD_INTEL_STRAGO is not set
+# CONFIG_BOARD_INTEL_TRUXTON is not set
+# CONFIG_BOARD_INTEL_WTM2 is not set
+# CONFIG_CONSOLE_POST is not set
+CONFIG_DRIVERS_UART_8250IO=y
+CONFIG_CPU_ADDR_BITS=32
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+# CONFIG_USBDEBUG is not set
+CONFIG_MAINBOARD_VERSION="1.0"
+# CONFIG_NO_POST is not set
+CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_BOARD_ROMSIZE_KB_512=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_512=y
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=512
+CONFIG_ROM_SIZE=0x80000
+CONFIG_FMDFILE=""
+# CONFIG_MAINBOARD_HAS_TPM2 is not set
+# CONFIG_SYSTEM_TYPE_LAPTOP is not set
+# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+# CONFIG_SOC_BROADCOM_CYGNUS is not set
+CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000
+CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_ROMSTAGE_ADDR=0x2000000
+CONFIG_VERSTAGE_ADDR=0x2000000
+CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/i945/bootblock.c"
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c"
+CONFIG_TTYS0_BASE=0x3f8
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_RAMTOP=0x200000
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_UART_PCI_ADDR=0
+CONFIG_HPET_MIN_TICKS=0x80
+# CONFIG_SOC_MARVELL_ARMADA38X is not set
+# CONFIG_SOC_MARVELL_BG4CD is not set
+# CONFIG_SOC_MEDIATEK_MT8173 is not set
+# CONFIG_SOC_NVIDIA_TEGRA124 is not set
+# CONFIG_SOC_NVIDIA_TEGRA210 is not set
+# CONFIG_SOC_QC_IPQ40XX is not set
+# CONFIG_SOC_QC_IPQ806X is not set
+# CONFIG_SOC_ROCKCHIP_RK3288 is not set
+# CONFIG_SOC_ROCKCHIP_RK3399 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set
+# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set
+# CONFIG_SOC_UCB_RISCV is not set
+
+#
+# CPU
+#
+# CONFIG_CPU_ALLWINNER_A10 is not set
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_NUM_IPI_STARTS=2
+# CONFIG_CPU_AMD_AGESA is not set
+# CONFIG_CPU_AMD_PI is not set
+# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set
+CONFIG_CPU_INTEL_MODEL_106CX=y
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_441=y
+# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set
+# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set
+# CONFIG_CPU_TI_AM335X is not set
+# CONFIG_PARALLEL_CPU_INIT is not set
+# CONFIG_PARALLEL_MP is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_UDELAY_LAPIC=y
+CONFIG_LAPIC_MONOTONIC_TIMER=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+# CONFIG_TSC_SYNC_LFENCE is not set
+CONFIG_TSC_SYNC_MFENCE=y
+# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set
+CONFIG_LOGICAL_CPUS=y
+# CONFIG_SMM_TSEG is not set
+CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
+CONFIG_SERIALIZED_SMM_INITIALIZATION=y
+# CONFIG_X86_AMD_FIXED_MTRRS is not set
+# CONFIG_PLATFORM_USES_FSP1_0 is not set
+# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set
+# CONFIG_SOC_SETS_MSRS is not set
+CONFIG_CACHE_AS_RAM=y
+CONFIG_SMP=y
+CONFIG_AP_SIPI_VECTOR=0xfffff000
+CONFIG_MMX=y
+CONFIG_SSE=y
+CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
+# CONFIG_USES_MICROCODE_HEADER_FILES is not set
+# CONFIG_CPU_MICROCODE_CBFS_GENERATE is not set
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
+CONFIG_CPU_MICROCODE_CBFS_NONE=y
+
+#
+# Northbridge
+#
+# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
+# CONFIG_AMD_NB_CIMX is not set
+# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set
+CONFIG_VIDEO_MB=0
+# CONFIG_NORTHBRIDGE_AMD_PI is not set
+CONFIG_RAMBASE=0x100000
+# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set
+CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y
+CONFIG_NORTHBRIDGE_INTEL_I945=y
+CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y
+# CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM is not set
+CONFIG_CHANNEL_XOR_RANDOMIZATION=y
+# CONFIG_OVERRIDE_CLOCK_DISABLE is not set
+CONFIG_CHECK_SLFRCS_ON_RESUME=y
+CONFIG_HPET_ADDRESS=0xfed00000
+CONFIG_MAX_PIRQ_LINKS=4
+
+#
+# Southbridge
+#
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+CONFIG_SOUTHBRIDGE_INTEL_COMMON=y
+# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set
+CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
+
+#
+# Super I/O
+#
+CONFIG_SUPERIO_SMSC_LPC47M15X=y
+
+#
+# Embedded Controllers
+#
+CONFIG_VBOOT_VBNV_OFFSET=0x26
+# CONFIG_VBOOT_VBNV_CMOS is not set
+# CONFIG_VBOOT_VBNV_EC is not set
+# CONFIG_VBOOT is not set
+# CONFIG_MAINBOARD_HAS_CHROMEOS is not set
+# CONFIG_UEFI_2_4_BINDING is not set
+# CONFIG_UDK_2015_BINDING is not set
+# CONFIG_USE_SIEMENS_HWILIB is not set
+# CONFIG_ARCH_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM is not set
+# CONFIG_ARCH_VERSTAGE_ARM is not set
+# CONFIG_ARCH_ROMSTAGE_ARM is not set
+# CONFIG_ARCH_RAMSTAGE_ARM is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV4 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set
+# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set
+# CONFIG_ARM_LPAE is not set
+# CONFIG_ARCH_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set
+# CONFIG_ARCH_VERSTAGE_ARM64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARM64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARM64 is not set
+# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set
+# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set
+# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set
+# CONFIG_ARM64_A53_ERRATUM_843419 is not set
+# CONFIG_ARCH_MIPS is not set
+# CONFIG_ARCH_BOOTBLOCK_MIPS is not set
+# CONFIG_ARCH_VERSTAGE_MIPS is not set
+# CONFIG_ARCH_ROMSTAGE_MIPS is not set
+# CONFIG_ARCH_RAMSTAGE_MIPS is not set
+# CONFIG_ARCH_POWER8 is not set
+# CONFIG_ARCH_BOOTBLOCK_POWER8 is not set
+# CONFIG_ARCH_VERSTAGE_POWER8 is not set
+# CONFIG_ARCH_ROMSTAGE_POWER8 is not set
+# CONFIG_ARCH_RAMSTAGE_POWER8 is not set
+# CONFIG_ARCH_RISCV is not set
+# CONFIG_ARCH_BOOTBLOCK_RISCV is not set
+# CONFIG_ARCH_VERSTAGE_RISCV is not set
+# CONFIG_ARCH_ROMSTAGE_RISCV is not set
+# CONFIG_ARCH_RAMSTAGE_RISCV is not set
+CONFIG_ARCH_X86=y
+CONFIG_ARCH_BOOTBLOCK_X86_32=y
+CONFIG_ARCH_VERSTAGE_X86_32=y
+CONFIG_ARCH_ROMSTAGE_X86_32=y
+CONFIG_ARCH_RAMSTAGE_X86_32=y
+# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set
+# CONFIG_ARCH_VERSTAGE_X86_64 is not set
+# CONFIG_ARCH_ROMSTAGE_X86_64 is not set
+# CONFIG_ARCH_RAMSTAGE_X86_64 is not set
+# CONFIG_USE_MARCH_586 is not set
+CONFIG_AP_IN_SIPI_WAIT=y
+CONFIG_SIPI_VECTOR_IN_ROM=y
+# CONFIG_ROMCC is not set
+# CONFIG_LATE_CBMEM_INIT is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set
+# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_POSTCAR_STAGE is not set
+# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set
+# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set
+
+#
+# Devices
+#
+CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
+CONFIG_NATIVE_VGA_INIT_USE_EDID=y
+# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG is not set
+CONFIG_ON_DEVICE_ROM_LOAD=y
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set
+# CONFIG_SPD_CACHE is not set
+CONFIG_PCI=y
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+# CONFIG_AZALIA_PLUGIN_SUPPORT is not set
+# CONFIG_PCIEXP_COMMON_CLOCK is not set
+# CONFIG_PCIEXP_ASPM is not set
+# CONFIG_PCIEXP_CLK_PM is not set
+# CONFIG_EARLY_PCI_BRIDGE is not set
+# CONFIG_PCIEXP_L1_SUB_STATE is not set
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+# CONFIG_SOFTWARE_I2C is not set
+
+#
+# Display
+#
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_AS3722_RTC is not set
+# CONFIG_GIC is not set
+# CONFIG_IPMI_KCS is not set
+# CONFIG_DRIVERS_LENOVO_WACOM is not set
+# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set
+# CONFIG_REALTEK_8168_RESET is not set
+# CONFIG_SPI_FLASH is not set
+# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set
+CONFIG_DRIVERS_UART=y
+# CONFIG_NO_UART_ON_SUPERIO is not set
+# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set
+# CONFIG_UART_OVERRIDE_REFCLK is not set
+# CONFIG_DRIVERS_UART_8250MEM is not set
+# CONFIG_DRIVERS_UART_8250MEM_32 is not set
+# CONFIG_HAVE_UART_SPECIAL is not set
+# CONFIG_DRIVERS_UART_OXPCIE is not set
+# CONFIG_DRIVERS_UART_PL011 is not set
+# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set
+CONFIG_HAVE_USBDEBUG=y
+# CONFIG_HAVE_USBDEBUG_OPTIONS is not set
+# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set
+# CONFIG_DRIVERS_I2C_PCF8523 is not set
+# CONFIG_DRIVERS_I2C_RTD2132 is not set
+# CONFIG_INTEL_DP is not set
+# CONFIG_INTEL_DDI is not set
+CONFIG_INTEL_EDID=y
+# CONFIG_INTEL_INT15 is not set
+CONFIG_INTEL_GMA_ACPI=y
+# CONFIG_DRIVER_INTEL_I210 is not set
+CONFIG_DRIVERS_INTEL_WIFI=y
+# CONFIG_DRIVER_MAXIM_MAX77686 is not set
+# CONFIG_DRIVER_PARADE_PS8625 is not set
+# CONFIG_DRIVER_PARADE_PS8640 is not set
+CONFIG_DRIVERS_MC146818=y
+# CONFIG_MAINBOARD_HAS_LPC_TPM is not set
+# CONFIG_DRIVERS_RICOH_RCE822 is not set
+# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+# CONFIG_DRIVER_TI_TPS65090 is not set
+# CONFIG_DRIVERS_TI_TPS65913 is not set
+# CONFIG_DRIVERS_TI_TPS65913_RTC is not set
+# CONFIG_DRIVER_XPOWERS_AXP209 is not set
+# CONFIG_ACPI_SATA_GENERATOR is not set
+CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
+# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set
+CONFIG_BOOT_DEVICE_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
+# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set
+# CONFIG_RTC is not set
+# CONFIG_TPM is not set
+CONFIG_STACK_SIZE=0x1000
+CONFIG_MMCONF_SUPPORT_DEFAULT=y
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_SQUELCH_EARLY_SMP=y
+CONFIG_CONSOLE_SERIAL=y
+
+#
+# I/O mapped, 8250-compatible
+#
+
+#
+# Serial port base address = 0x3f8
+#
+# CONFIG_CONSOLE_SERIAL_921600 is not set
+# CONFIG_CONSOLE_SERIAL_460800 is not set
+# CONFIG_CONSOLE_SERIAL_230400 is not set
+CONFIG_CONSOLE_SERIAL_115200=y
+# CONFIG_CONSOLE_SERIAL_57600 is not set
+# CONFIG_CONSOLE_SERIAL_38400 is not set
+# CONFIG_CONSOLE_SERIAL_19200 is not set
+# CONFIG_CONSOLE_SERIAL_9600 is not set
+CONFIG_TTYS0_BAUD=115200
+# CONFIG_SPKMODEM is not set
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CMOS_POST is not set
+CONFIG_POST_DEVICE_NONE=y
+# CONFIG_POST_DEVICE_LPC is not set
+# CONFIG_POST_DEVICE_PCI_PCIE is not set
+CONFIG_POST_IO_PORT=0x80
+# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set
+CONFIG_HAVE_ACPI_RESUME=y
+CONFIG_RESUME_PATH_SAME_AS_BOOT=y
+CONFIG_HAVE_HARD_RESET=y
+# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set
+# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set
+# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set
+CONFIG_HAVE_MONOTONIC_TIMER=y
+# CONFIG_GENERIC_UDELAY is not set
+# CONFIG_TIMER_QUEUE is not set
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_IOAPIC=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+CONFIG_VGA=y
+# CONFIG_GFXUMA is not set
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_HAVE_MP_TABLE=y
+CONFIG_HAVE_PIRQ_TABLE=y
+CONFIG_COMMON_FADT=y
+# CONFIG_ACPI_NHLT is not set
+
+#
+# System tables
+#
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_SMBIOS_TABLES=y
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
+
+#
+# Payload
+#
+# CONFIG_PAYLOAD_NONE is not set
+CONFIG_PAYLOAD_ELF=y
+# CONFIG_PAYLOAD_BAYOU is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_PAYLOAD_GRUB2 is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_UBOOT is not set
+# CONFIG_PAYLOAD_LINUX is not set
+# CONFIG_PAYLOAD_TIANOCORE is not set
+CONFIG_PAYLOAD_FILE="payload.elf"
+# CONFIG_SEABIOS_STABLE is not set
+# CONFIG_SEABIOS_MASTER is not set
+# CONFIG_SEABIOS_REVISION is not set
+CONFIG_PAYLOAD_OPTIONS=""
+# CONFIG_PXE is not set
+CONFIG_COMPRESSED_PAYLOAD_LZMA=y
+# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set
+
+#
+# Secondary Payloads
+#
+# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
+# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
+# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
+# CONFIG_TINT_SECONDARY_PAYLOAD is not set
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_FATAL_ASSERTS is not set
+# CONFIG_DEBUG_CBFS is not set
+CONFIG_HAVE_DEBUG_RAM_SETUP=y
+# CONFIG_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_DEBUG_PIRQ is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_TRACE is not set
+# CONFIG_DEBUG_BOOT_STATE is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+CONFIG_WARNINGS_ARE_ERRORS=y
+CONFIG_IASL_WARNINGS_ARE_ERRORS=y
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+# CONFIG_REG_SCRIPT is not set
+# CONFIG_CREATE_BOARD_CHECKLIST is not set
+# CONFIG_MAKE_CHECKLIST_PUBLIC is not set
diff --git a/resources/libreboot/config/seabios/d945gclf/vbootrevision b/resources/libreboot/config/seabios/d945gclf/vbootrevision
new file mode 100644
index 00000000..67bdb13d
--- /dev/null
+++ b/resources/libreboot/config/seabios/d945gclf/vbootrevision
@@ -0,0 +1 @@
+f7559e4b4652134b1e15de3ce31ee50a3de00f69
diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-mb-intel-d945gclf-Disable-combined-mode-to-fix-SATA.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-mb-intel-d945gclf-Disable-combined-mode-to-fix-SATA.patch
new file mode 100644
index 00000000..4c75bcd5
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-mb-intel-d945gclf-Disable-combined-mode-to-fix-SATA.patch
@@ -0,0 +1,31 @@
+From b6b2f9a9775029305f88f927f93e95046594f9b9 Mon Sep 17 00:00:00 2001
+From: Arthur Heymans <arthur@aheymans.xyz>
+Date: Thu, 25 Aug 2016 09:24:15 +0200
+Subject: [PATCH] mb/intel/d945gclf: Disable combined mode to fix SATA
+
+Similarly to 2b2f465fcb1afe4960c613b8ca91e868c64592d4
+"mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA"
+SATA must function in "plain" mode because it does not work in
+"combined" mode.
+
+Tested on d945gclf
+
+Change-Id: I2e051a632a1341c4932cf86855006ae517dbf064
+Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
+
+diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb
+index 823a240..aa8c441 100644
+--- a/src/mainboard/intel/d945gclf/devicetree.cb
++++ b/src/mainboard/intel/d945gclf/devicetree.cb
+@@ -45,7 +45,7 @@ chip northbridge/intel/i945
+ register "gpi13_routing" = "1"
+ register "gpe0_en" = "0x20000601"
+
+- register "ide_legacy_combined" = "0x1"
++ register "ide_legacy_combined" = "0x0"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x0"
+--
+2.9.3
+
diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-move-DIV_ROUND-macros-to-commonlib.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-move-DIV_ROUND-macros-to-commonlib.patch
new file mode 100644
index 00000000..ea4db001
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0001-move-DIV_ROUND-macros-to-commonlib.patch
@@ -0,0 +1,93 @@
+From c82d4fa874322d70dec0e9d28c050e4c351de157 Mon Sep 17 00:00:00 2001
+From: Arthur Heymans <arthur@aheymans.xyz>
+Date: Fri, 2 Sep 2016 23:14:54 +0200
+Subject: [PATCH 1/5] move DIV_ROUND macros to commonlib
+
+DIV_ROUND_CLOSEST and DIV_ROUND_UP are useful macros for other
+architectures. This patch moves them from soc/nvidia/tegra/types.h
+to commonlib/include/commonlib/helpers.h .
+
+Change-Id: I54521d9b197934cef8e352f9a5c4823015d85f01
+Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
+
+diff --git a/src/commonlib/include/commonlib/helpers.h b/src/commonlib/include/commonlib/helpers.h
+index 0318e44..0b2395b 100644
+--- a/src/commonlib/include/commonlib/helpers.h
++++ b/src/commonlib/include/commonlib/helpers.h
+@@ -34,6 +34,22 @@
+ #define ABS(a) (((a) < 0) ? (-(a)) : (a))
+ #define CEIL_DIV(a, b) (((a) + (b) - 1) / (b))
+ #define IS_POWER_OF_2(x) (((x) & ((x) - 1)) == 0)
++#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
++/*
++ * Divide positive or negative dividend by positive divisor and round
++ * to closest integer. Result is undefined for negative divisors and
++ * for negative dividends if the divisor variable type is unsigned.
++ */
++#define DIV_ROUND_CLOSEST(x, divisor)( \
++{ \
++ typeof(x) __x = x; \
++ typeof(divisor) __d = divisor; \
++ (((typeof(x))-1) > 0 || \
++ ((typeof(divisor))-1) > 0 || (__x) > 0) ? \
++ (((__x) + ((__d) / 2)) / (__d)) : \
++ (((__x) - ((__d) / 2)) / (__d)); \
++} \
++)
+
+ /* Standard units. */
+ #define KiB (1<<10)
+diff --git a/src/soc/nvidia/tegra/types.h b/src/soc/nvidia/tegra/types.h
+index dab474d..bfeebae 100644
+--- a/src/soc/nvidia/tegra/types.h
++++ b/src/soc/nvidia/tegra/types.h
+@@ -51,22 +51,4 @@
+ (type *)( (char *)__mptr - offsetof(type,member) );})
+ #endif
+
+-#define DIV_ROUND_UP(x, y) (((x) + (y) - 1) / (y))
+-
+-/*
+- * Divide positive or negative dividend by positive divisor and round
+- * to closest integer. Result is undefined for negative divisors and
+- * for negative dividends if the divisor variable type is unsigned.
+- */
+-#define DIV_ROUND_CLOSEST(x, divisor)( \
+-{ \
+- typeof(x) __x = x; \
+- typeof(divisor) __d = divisor; \
+- (((typeof(x))-1) > 0 || \
+- ((typeof(divisor))-1) > 0 || (__x) > 0) ? \
+- (((__x) + ((__d) / 2)) / (__d)) : \
+- (((__x) - ((__d) / 2)) / (__d)); \
+-} \
+-)
+-
+ #endif /* __TEGRA_MISC_TYPES_H__ */
+diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c
+index e803e1b..b47c5c5 100644
+--- a/src/soc/nvidia/tegra210/addressmap.c
++++ b/src/soc/nvidia/tegra210/addressmap.c
+@@ -23,6 +23,7 @@
+ #include <stdlib.h>
+ #include <symbols.h>
+ #include <soc/nvidia/tegra/types.h>
++#include <commonlib/helpers.h>
+
+ static uintptr_t tz_base_mib;
+ static const size_t tz_size_mib = CONFIG_TRUSTZONE_CARVEOUT_SIZE_MB;
+diff --git a/src/soc/nvidia/tegra210/dsi.c b/src/soc/nvidia/tegra210/dsi.c
+index 3b771c9..5504b4d 100644
+--- a/src/soc/nvidia/tegra210/dsi.c
++++ b/src/soc/nvidia/tegra210/dsi.c
+@@ -32,6 +32,7 @@
+ #include <soc/tegra_dsi.h>
+ #include <soc/mipi-phy.h>
+ #include "jdi_25x18_display/panel-jdi-lpm102a188a.h"
++#include <commonlib/helpers.h>
+
+ struct tegra_mipi_device mipi_device_data[NUM_DSI];
+
+--
+2.9.3
+
diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0002-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0002-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch
new file mode 100644
index 00000000..6a8b9920
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0002-i945-gma.c-use-latest-linux-code-to-calculate-diviso.patch
@@ -0,0 +1,171 @@
+From f09ce5870025a98b6e497fd232adffde468c735a Mon Sep 17 00:00:00 2001
+From: Arthur Heymans <arthur@aheymans.xyz>
+Date: Fri, 2 Sep 2016 22:35:32 +0200
+Subject: [PATCH 2/5] i945/gma.c use latest linux code to calculate divisors.
+
+The code to compute n, m1, m2, p1 divisors is not correct in coreboot and
+on some targets hits a working mode at lower refresh rate, which is why
+display is working on some targets.
+This patch also fixes reference frequency.
+
+This patch reuses linux code to correctly compute divisors.
+
+The result is that some previously not working displays (Lenovo T60 with
+1024x786, 1400x1050, 2048x1536)
+
+TESTED on T60 with 1024x786.
+
+Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e
+Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
+
+diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
+index 02caa0a..d1d68d4 100644
+--- a/src/northbridge/intel/i945/gma.c
++++ b/src/northbridge/intel/i945/gma.c
+@@ -26,6 +26,8 @@
+ #include <string.h>
+ #include <pc80/vga.h>
+ #include <pc80/vga_io.h>
++#include <commonlib/helpers.h>
++
+
+ #include "i945.h"
+ #include "chip.h"
+@@ -43,7 +45,7 @@
+ #define PGETBL_CTL 0x2020
+ #define PGETBL_ENABLED 0x00000001
+
+-#define BASE_FREQUENCY 120000
++#define BASE_FREQUENCY 100000
+
+ #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+
+@@ -85,10 +87,10 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
+ u8 edid_data[128];
+ unsigned long temp;
+ int hpolarity, vpolarity;
+- u32 candp1, candn;
+- u32 best_delta = 0xffffffff;
++ u32 err_most = 0xffffffff;
+ u32 target_frequency;
+ u32 pixel_p1 = 1;
++ u32 pixel_p2;
+ u32 pixel_n = 1;
+ u32 pixel_m1 = 1;
+ u32 pixel_m2 = 1;
+@@ -158,43 +160,37 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
+ write32(pmmio + PORT_HOTPLUG_EN, conf->gpu_hotplug);
+ write32(pmmio + INSTPM, 0x08000000 | INSTPM_AGPBUSY_DIS);
+
+- target_frequency = mode->lvds_dual_channel ? mode->pixel_clock
+- : (2 * mode->pixel_clock);
+-
+- /* Find suitable divisors. */
+- for (candp1 = 1; candp1 <= 8; candp1++) {
+- for (candn = 5; candn <= 10; candn++) {
+- u32 cur_frequency;
+- u32 m; /* 77 - 131. */
+- u32 denom; /* 35 - 560. */
+- u32 current_delta;
+-
+- denom = candn * candp1 * 7;
+- /* Doesnt overflow for up to
+- 5000000 kHz = 5 GHz. */
+- m = (target_frequency * denom
+- + BASE_FREQUENCY / 2) / BASE_FREQUENCY;
+-
+- if (m < 77 || m > 131)
+- continue;
+-
+- cur_frequency = (BASE_FREQUENCY * m) / denom;
+- if (target_frequency > cur_frequency)
+- current_delta = target_frequency - cur_frequency;
+- else
+- current_delta = cur_frequency - target_frequency;
+-
+- if (best_delta > current_delta) {
+- best_delta = current_delta;
+- pixel_n = candn;
+- pixel_p1 = candp1;
+- pixel_m2 = ((m + 3) % 5) + 7;
+- pixel_m1 = (m - pixel_m2) / 5;
++ pixel_p2 = mode->lvds_dual_channel ? 7 : 14;
++ target_frequency = mode->pixel_clock;
++
++ /* Find suitable divisors, m1, m2, p1, n. */
++ /* refclock * (5 * (m1 + 2) + (m1 + 2)) / (n + 2) / p1 / p2 */
++ /* should be closest to target frequency as possible */
++ u32 candn, candm1, candm2, candp1;
++ for (candm1 = 8; candm1 <= 18; candm1++) {
++ for (candm2 = 3; candm2 <= 7; candm2++) {
++ for (candn = 1; candn <= 6; candn++) {
++ for (candp1 = 1; candp1 <= 8; candp1++) {
++ u32 m = 5 * (candm1 + 2) + (candm2 + 2);
++ u32 p = candp1 * pixel_p2;
++ u32 vco = DIV_ROUND_CLOSEST(BASE_FREQUENCY * m, candn + 2);
++ u32 dot = DIV_ROUND_CLOSEST(vco, p);
++ u32 this_err = ABS(dot - target_frequency);
++ if ((m < 70) || (m > 120))
++ continue;
++ if (this_err < err_most) {
++ err_most = this_err;
++ pixel_n = candn;
++ pixel_m1 = candm1;
++ pixel_m2 = candm2;
++ pixel_p1 = candp1;
++ }
++ }
+ }
+ }
+ }
+
+- if (best_delta == 0xffffffff) {
++ if (err_most == 0xffffffff) {
+ printk (BIOS_ERR, "Couldn't find GFX clock divisors\n");
+ return -1;
+ }
+@@ -216,8 +212,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
+ printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n",
+ pixel_n, pixel_m1, pixel_m2, pixel_p1);
+ printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
+- BASE_FREQUENCY * (5 * pixel_m1 + pixel_m2) / pixel_n
+- / (pixel_p1 * 7));
++ BASE_FREQUENCY * (5 * (pixel_m1 + 2) + (pixel_m2 + 2)) /
++ (pixel_n + 2) / (pixel_p1 * pixel_p2));
+
+ #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
+ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16));
+@@ -242,8 +238,8 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
+ write32(pmmio + PP_CONTROL, PANEL_UNLOCK_REGS
+ | (read32(pmmio + PP_CONTROL) & ~PANEL_UNLOCK_MASK));
+ write32(pmmio + FP0(1),
+- ((pixel_n - 2) << 16)
+- | ((pixel_m1 - 2) << 8) | pixel_m2);
++ (pixel_n << 16)
++ | (pixel_m1 << 8) | pixel_m2);
+ write32(pmmio + DPLL(1),
+ DPLL_VGA_MODE_DIS |
+ DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
+@@ -252,8 +248,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
+ | (conf->gpu_lvds_use_spread_spectrum_clock
+ ? DPLL_INTEGRATED_CLOCK_VLV | DPLL_INTEGRATED_CRI_CLK_VLV
+ : 0)
+- | (pixel_p1 << 16)
+- | (pixel_p1));
++ | (0x10000 << pixel_p1));
+ mdelay(1);
+ write32(pmmio + DPLL(1),
+ DPLL_VGA_MODE_DIS |
+@@ -261,8 +256,7 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
+ | (mode->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+ : DPLLB_LVDS_P2_CLOCK_DIV_14)
+ | ((conf->gpu_lvds_use_spread_spectrum_clock ? 3 : 0) << 13)
+- | (pixel_p1 << 16)
+- | (pixel_p1));
++ | (0x10000 << pixel_p1));
+ mdelay(1);
+ write32(pmmio + HTOTAL(1),
+ ((hactive + right_border + hblank - 1) << 16)
+--
+2.9.3
+
diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0003-i945-gma.c-add-native-VGA-init.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0003-i945-gma.c-add-native-VGA-init.patch
new file mode 100644
index 00000000..24a01442
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0003-i945-gma.c-add-native-VGA-init.patch
@@ -0,0 +1,238 @@
+From 09546d389511350d1b33b3c6bd9230de8bbbe317 Mon Sep 17 00:00:00 2001
+From: Arthur Heymans <arthur@aheymans.xyz>
+Date: Mon, 5 Sep 2016 22:46:11 +0200
+Subject: [PATCH 3/5] i945/gma.c: add native VGA init
+
+This reuses the intel pineview native graphic initialization
+to have output on the VGA connector of i945 devices.
+
+The behavior is the same as with the vbios blob.
+It uses the external VGA display if it is connected.
+
+Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495
+Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
+
+diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
+index d1d68d4..37674d7 100644
+--- a/src/northbridge/intel/i945/gma.c
++++ b/src/northbridge/intel/i945/gma.c
+@@ -78,7 +78,7 @@ static int gtt_setup(void *mmiobase)
+ return 0;
+ }
+
+-static int intel_gma_init(struct northbridge_intel_i945_config *conf,
++static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
+ unsigned int pphysbase, unsigned int piobase,
+ void *pmmio, unsigned int pgfx)
+ {
+@@ -382,6 +382,194 @@ static int intel_gma_init(struct northbridge_intel_i945_config *conf,
+ #endif
+ return 0;
+ }
++
++static int intel_gma_init_vga(struct northbridge_intel_i945_config *conf,
++ unsigned int pphysbase, unsigned int piobase,
++ void *pmmio, unsigned int pgfx)
++{
++ int i;
++ u32 hactive, vactive;
++ u16 reg16;
++ u32 uma_size;
++
++ printk(BIOS_SPEW, "pmmio %x addrport %x physbase %x\n",
++ (u32)pmmio, piobase, pphysbase);
++
++ gtt_setup(pmmio);
++
++ /* Disable VGA. */
++ write32(pmmio + VGACNTRL, VGA_DISP_DISABLE);
++
++ /* Disable pipes. */
++ write32(pmmio + PIPECONF(0), 0);
++ write32(pmmio + PIPECONF(1), 0);
++
++ write32(pmmio + INSTPM, 0x800);
++
++ vga_gr_write(0x18, 0);
++
++ write32(pmmio + VGA0, 0x200074);
++ write32(pmmio + VGA1, 0x200074);
++
++ write32(pmmio + DSPFW3, 0x7f3f00c1 & ~PINEVIEW_SELF_REFRESH_EN);
++ write32(pmmio + DSPCLK_GATE_D, 0);
++ write32(pmmio + FW_BLC, 0x03060106);
++ write32(pmmio + FW_BLC2, 0x00000306);
++
++ write32(pmmio + ADPA, ADPA_DAC_ENABLE
++ | ADPA_PIPE_A_SELECT
++ | ADPA_USE_VGA_HVPOLARITY
++ | ADPA_VSYNC_CNTL_ENABLE
++ | ADPA_HSYNC_CNTL_ENABLE
++ | ADPA_DPMS_ON
++ );
++
++ write32(pmmio + 0x7041c, 0x0);
++
++ write32(pmmio + DPLL_MD(0), 0x3);
++ write32(pmmio + DPLL_MD(1), 0x3);
++ write32(pmmio + DSPCNTR(1), 0x1000000);
++ write32(pmmio + PIPESRC(1), 0x027f01df);
++
++ vga_misc_write(0x67);
++ const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
++ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
++ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
++ 0xff
++ };
++ vga_cr_write(0x11, 0);
++
++ for (i = 0; i <= 0x18; i++)
++ vga_cr_write(i, cr[i]);
++
++ // Disable screen memory to prevent garbage from appearing.
++ vga_sr_write(1, vga_sr_read(1) | 0x20);
++ hactive = 640;
++ vactive = 400;
++
++ mdelay(1);
++ write32(pmmio + DPLL(0),
++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
++ | DPLL_VGA_MODE_DIS
++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
++ | 0x400601
++ );
++ mdelay(1);
++ write32(pmmio + DPLL(0),
++ DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL
++ | DPLL_VGA_MODE_DIS
++ | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
++ | 0x400601
++ );
++
++ write32(pmmio + ADPA, ADPA_DAC_ENABLE
++ | ADPA_PIPE_A_SELECT
++ | ADPA_USE_VGA_HVPOLARITY
++ | ADPA_VSYNC_CNTL_ENABLE
++ | ADPA_HSYNC_CNTL_ENABLE
++ | ADPA_DPMS_ON
++ );
++
++ write32(pmmio + HTOTAL(0),
++ ((hactive - 1) << 16)
++ | (hactive - 1));
++ write32(pmmio + HBLANK(0),
++ ((hactive - 1) << 16)
++ | (hactive - 1));
++ write32(pmmio + HSYNC(0),
++ ((hactive - 1) << 16)
++ | (hactive - 1));
++
++ write32(pmmio + VTOTAL(0), ((vactive - 1) << 16)
++ | (vactive - 1));
++ write32(pmmio + VBLANK(0), ((vactive - 1) << 16)
++ | (vactive - 1));
++ write32(pmmio + VSYNC(0),
++ ((vactive - 1) << 16)
++ | (vactive - 1));
++
++ write32(pmmio + PF_WIN_POS(0), 0);
++
++ write32(pmmio + PIPESRC(0), (639 << 16) | 399);
++ write32(pmmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3);
++ write32(pmmio + PF_WIN_SZ(0), vactive | (hactive << 16));
++ write32(pmmio + PFIT_CONTROL, 0x0);
++
++ mdelay(1);
++
++ write32(pmmio + FDI_RX_CTL(0), 0x00002040);
++ mdelay(1);
++ write32(pmmio + FDI_RX_CTL(0), 0x80002050);
++ write32(pmmio + FDI_TX_CTL(0), 0x00044000);
++ mdelay(1);
++ write32(pmmio + FDI_TX_CTL(0), 0x80044000);
++ write32(pmmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
++
++ write32(pmmio + VGACNTRL, 0x0);
++ write32(pmmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888);
++ mdelay(1);
++
++ write32(pmmio + ADPA, ADPA_DAC_ENABLE
++ | ADPA_PIPE_A_SELECT
++ | ADPA_USE_VGA_HVPOLARITY
++ | ADPA_VSYNC_CNTL_ENABLE
++ | ADPA_HSYNC_CNTL_ENABLE
++ | ADPA_DPMS_ON
++ );
++
++ write32(pmmio + DSPFW3, 0x7f3f00c1);
++ write32(pmmio + MI_MODE, 0x200 | VS_TIMER_DISPATCH);
++ write32(pmmio + CACHE_MODE_0, (0x6820 | (1 << 9)) & ~(1 << 5));
++ write32(pmmio + CACHE_MODE_1, 0x380 & ~(1 << 9));
++
++ /* Set up GTT. */
++
++ reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
++ uma_size = 0;
++ if (!(reg16 & 2)) {
++ uma_size = decode_igd_memory_size((reg16 >> 4) & 7);
++ printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
++ }
++
++ for (i = 0; i < (uma_size - 256) / 4; i++)
++ {
++ outl((i << 2) | 1, piobase);
++ outl(pphysbase + (i << 12) + 1, piobase + 4);
++ }
++
++ /* Clear interrupts. */
++ write32(pmmio + DEIIR, 0xffffffff);
++ write32(pmmio + SDEIIR, 0xffffffff);
++ write32(pmmio + IIR, 0xffffffff);
++ write32(pmmio + IMR, 0xffffffff);
++ write32(pmmio + EIR, 0xffffffff);
++
++ vga_textmode_init();
++
++ /* Enable screen memory. */
++ vga_sr_write(1, vga_sr_read(1) & ~0x20);
++
++ return 0;
++
++}
++
++/* compare the header of the vga edid header */
++/* if vga is not connected it should have a correct header */
++static int vga_connected(u8 *pmmio) {
++ u8 vga_edid[128];
++ u8 header[8] = {0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00};
++ intel_gmbus_read_edid(pmmio + GMBUS0, 2, 0x50, vga_edid, 128);
++ intel_gmbus_stop(pmmio + GMBUS0);
++ for (int i = 0; i < 8; i++) {
++ if (vga_edid[i] != header[i]) {
++ printk(BIOS_DEBUG, "VGA not connected. Using LVDS display\n");
++ return 0;
++ }
++ }
++ printk(BIOS_SPEW, "VGA display connected\n");
++ return 1;
++}
++
+ #endif
+
+ static void gma_func0_init(struct device *dev)
+@@ -423,7 +611,11 @@ static void gma_func0_init(struct device *dev)
+ );
+
+ int err;
+- err = intel_gma_init(conf, pci_read_config32(dev, 0x5c) & ~0xf,
++ if (vga_connected(mmiobase))
++ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf,
++ iobase, mmiobase, graphics_base);
++ else
++ err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf,
+ iobase, mmiobase, graphics_base);
+ if (err == 0)
+ gfx_set_init_done(1);
+--
+2.9.3
+
diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0004-mb-intel-d945gclf-Allow-use-of-native-graphic-init.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0004-mb-intel-d945gclf-Allow-use-of-native-graphic-init.patch
new file mode 100644
index 00000000..bda565f9
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0004-mb-intel-d945gclf-Allow-use-of-native-graphic-init.patch
@@ -0,0 +1,40 @@
+From d80a39744d7aad734e8d53f2b2d6cb6b5eeee834 Mon Sep 17 00:00:00 2001
+From: Arthur Heymans <arthur@aheymans.xyz>
+Date: Tue, 6 Sep 2016 23:03:04 +0200
+Subject: [PATCH 4/5] mb/intel/d945gclf: Allow use of native graphic init
+
+Adds pci device id to native graphic init and add a Native graphic init
+option in Kconfig.
+
+Change-Id: I136122daef70547830bcc87f568406be7162461f
+Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
+
+diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig
+index 429a304..a83e613 100644
+--- a/src/mainboard/intel/d945gclf/Kconfig
++++ b/src/mainboard/intel/d945gclf/Kconfig
+@@ -29,6 +29,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy
+ select HAVE_ACPI_RESUME
+ select BOARD_ROMSIZE_KB_512
+ select CHANNEL_XOR_RANDOMIZATION
++ select MAINBOARD_HAS_NATIVE_VGA_INIT
++ select INTEL_EDID
+
+ config MAINBOARD_DIR
+ string
+diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
+index 37674d7..abe7dd6 100644
+--- a/src/northbridge/intel/i945/gma.c
++++ b/src/northbridge/intel/i945/gma.c
+@@ -716,7 +716,7 @@ static struct device_operations gma_func1_ops = {
+ .ops_pci = &gma_pci_ops,
+ };
+
+-static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0 };
++static const unsigned short pci_device_ids[] = { 0x27a2, 0x27ae, 0x2772, 0 };
+
+ static const struct pci_driver i945_gma_func0_driver __pci_driver = {
+ .ops = &gma_func0_ops,
+--
+2.9.3
+
diff --git a/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0005-i945-gma.c-Only-init-LVDS-if-it-is-present-on-the-de.patch b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0005-i945-gma.c-Only-init-LVDS-if-it-is-present-on-the-de.patch
new file mode 100644
index 00000000..3155ef90
--- /dev/null
+++ b/resources/libreboot/patch/coreboot/36d405268f040208cd26902f3c0b5346f7d4d25b/seabios/d945gclf/0005-i945-gma.c-Only-init-LVDS-if-it-is-present-on-the-de.patch
@@ -0,0 +1,97 @@
+From 603387a7650a80c92f1064f17fbbf06d60c06f30 Mon Sep 17 00:00:00 2001
+From: Arthur Heymans <arthur@aheymans.xyz>
+Date: Tue, 6 Sep 2016 23:53:32 +0200
+Subject: [PATCH 5/5] i945/gma.c: Only init LVDS if it is present on the device
+
+Some devices have no LVDS output but if no VGA is connected or
+no edid can be found, it will try to init LVDS.
+
+This patch makes sure only devices that have an LVDS connector can use LVDS
+graphic initialisation.
+
+Change-Id: Ie15631514535bab6c881c1f52e9edbfb8aaa5db7
+Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
+
+diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
+index e653c08..8ba3d77 100644
+--- a/src/mainboard/apple/macbook21/Kconfig
++++ b/src/mainboard/apple/macbook21/Kconfig
+@@ -35,6 +35,10 @@ config DCACHE_RAM_SIZE
+ hex
+ default 0x8000
+
++config HAS_LVDS
++ bool
++ default y
++
+ if BOARD_APPLE_MACBOOK21
+
+ config MAINBOARD_PART_NUMBER
+diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig
+index ea68bed..e74b70c 100644
+--- a/src/mainboard/getac/p470/Kconfig
++++ b/src/mainboard/getac/p470/Kconfig
+@@ -64,4 +64,8 @@ config VGA_BIOS_FILE
+ string
+ default "getac-pci8086,27a2.rom"
+
++config HAS_LVDS
++ bool
++ default y
++
+ endif # BOARD_GETAC_P470
+diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig
+index 52eeda3..e5a7554 100644
+--- a/src/mainboard/lenovo/t60/Kconfig
++++ b/src/mainboard/lenovo/t60/Kconfig
+@@ -54,4 +54,8 @@ config SEABIOS_PS2_TIMEOUT
+ int
+ default 3000
+
++config HAS_LVDS
++ bool
++ default y
++
+ endif
+diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig
+index ab4b58e..152e6b2 100644
+--- a/src/mainboard/lenovo/x60/Kconfig
++++ b/src/mainboard/lenovo/x60/Kconfig
+@@ -61,4 +61,8 @@ config SEABIOS_PS2_TIMEOUT
+ int
+ default 3000
+
++config HAS_LVDS
++ bool
++ default y
++
+ endif
+diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
+index 6e8d35b..ae7961f 100644
+--- a/src/northbridge/intel/i945/Kconfig
++++ b/src/northbridge/intel/i945/Kconfig
+@@ -71,4 +71,8 @@ config CHECK_SLFRCS_ON_RESUME
+ On other boards the check always creates a false positive,
+ effectively making it impossible to resume.
+
++config HAS_LVDS
++ bool
++ default n
++
+ endif
+diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
+index abe7dd6..be299f4 100644
+--- a/src/northbridge/intel/i945/gma.c
++++ b/src/northbridge/intel/i945/gma.c
+@@ -611,7 +611,7 @@ static void gma_func0_init(struct device *dev)
+ );
+
+ int err;
+- if (vga_connected(mmiobase))
++ if (!CONFIG_HAS_LVDS || vga_connected(mmiobase))
+ err = intel_gma_init_vga(conf, pci_read_config32(dev, 0x5c) & ~0xf,
+ iobase, mmiobase, graphics_base);
+ else
+--
+2.9.3
+