diff options
Diffstat (limited to 'resources/utilities/coreboot-libre/blobs/coreboot')
3 files changed, 402 insertions, 0 deletions
diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/blobs.list b/resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/blobs.list new file mode 100644 index 00000000..a8a9a964 --- /dev/null +++ b/resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/blobs.list @@ -0,0 +1,52 @@ +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000d9.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000624_Enc.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch0600050D_Enc.c +src/vendorcode/amd/agesa/f15/Proc/CPU/Family/0x15/OR/F15OrMicrocodePatch06000425.c +src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600110F_Enc.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c6.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c8.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE/F10MicrocodePatch010000bf.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch03000002.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000f.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x12/F12MicrocodePatch0300000e.c +src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000c7.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000085.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch010000b6.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000098.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevC/F10MicrocodePatch01000086.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c4.c +src/vendorcode/amd/agesa/f10/Proc/CPU/Family/0x10/RevD/F10MicrocodePatch010000c5.c +src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c +src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c +src/vendorcode/amd/agesa/f12/Proc/GNB/Nb/Family/LN/F12NbSmuFirmware.h +src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h +src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h 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+src/mainboard/siemens/mc_tcu3/lcd_panel.c +src/mainboard/siemens/mc_tcu3/modhwinfo.c +src/mainboard/pcengines/apu1/Kconfig +src/mainboard/asus/kfsn4-dre/get_bus_conf.c +src/mainboard/google/samus/spd/spd.c +src/mainboard/hp/abm/mptable.c +src/northbridge/amd/pi/00630F01/Kconfig +src/cpu/amd/microcode/microcode.c +src/lib/tlcl_structures.h +util/rockchip/make_idb.py +util/autoport/readme.md +util/bimgtool/bimgtool.c +util/cbfstool/fmd_parser.c_shipped +util/cbfstool/fmd_scanner.c_shipped +Documentation/CorebootBuildingGuide.tex +Documentation/hypertransport.svg +Documentation/codeflow.svg +src/soc/broadcom/cygnus/ddr_init.c +src/soc/broadcom/cygnus/ddr_init_table.c +src/soc/qualcomm/ipq806x/lcc.c +src/soc/intel/braswell/acpi.c +src/soc/intel/braswell/Kconfig +src/vendorcode/amd/pi/Kconfig +src/drivers/intel/fsp1_1/Kconfig +src/drivers/intel/fsp1_1/fsp_gop.c +src/drivers/i2c/ww_ring/ww_ring_programs.c +src/mainboard/google/auron/spd/spd.c +src/mainboard/google/jecht/lan.c +src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +src/mainboard/amd/lamar/Kconfig +payloads/external/GRUB2/Kconfig +payloads/external/FILO/Kconfig +payloads/external/SeaBIOS/Kconfig +src/soc/intel/common/fsp_ramstage.c +src/soc/intel/skylake/Kconfig +src/soc/intel/braswell/gpio.c +src/soc/nvidia/tegra210/Kconfig +src/soc/nvidia/tegra210/mtc.c +src/southbridge/intel/common/firmware/Kconfig +src/mainboard/google/cyan/spd/spd.c +src/mainboard/google/cyan/Kconfig +src/mainboard/google/glados/spd/spd.c +src/mainboard/intel/sklrvp/spd/spd.c +src/mainboard/intel/kunimitsu/spd/spd.c +src/mainboard/intel/strago/spd/spd.c +src/mainboard/intel/strago/Kconfig +src/mainboard/amd/bettong/mptable.c +src/northbridge/amd/pi/00660F01/Kconfig +util/crossgcc/patches/gcc-5.2.0_riscv.patch +util/xcompile/xcompile +src/northbridge/intel/sandybridge/raminit_mrc.c +src/northbridge/intel/fsp_rangeley/fsp/Kconfig +src/drivers/intel/fsp1_1/car.c +src/mainboard/intel/mohonpeak/Kconfig +src/mainboard/apple/macbookair4_2/early_southbridge.c +src/cpu/intel/fsp_model_406dx/acpi.c +src/northbridge/intel/fsp_sandybridge/fsp/Kconfig +src/drivers/aspeed/common/ast_dram_tables.h +src/drivers/aspeed/common/ast_tables.h +src/mainboard/intel/cougar_canyon2/Kconfig +src/cpu/amd/family_10h-family_15h/processor_name.c +src/cpu/amd/family_10h-family_15h/init_cpus.c +src/cpu/intel/fsp_model_206ax/acpi.c diff --git a/resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/nonblobs_notes b/resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/nonblobs_notes new file mode 100644 index 00000000..551da4a8 --- /dev/null +++ b/resources/utilities/coreboot-libre/blobs/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/nonblobs_notes @@ -0,0 +1,15 @@ +.spd.hex files - serial presence detect. These are not blobs +see JEDEC standard or https://en.wikipedia.org/wiki/Serial_presence_detect +These are added to the nonblobs file + +src/northbridge/intel/nehalem/raminit_tables.c" +src/northbridge/intel/sandybridge/raminit_patterns.h +These are used by native raminit for the relevant platforms, and are not blobs + +"src/southbridge/nvidia/mcp55/early_setup_ss.h" \ +"src/southbridge/nvidia/ck804/early_setup_ss.h" \ +"src/southbridge/sis/sis966/early_setup_ss.h" +not blobs + +The text in this file is CC-BY-SA 4.0 or higher. All contributions to it must +be made under the same license. |