diff options
Diffstat (limited to 'resources')
4 files changed, 377 insertions, 30 deletions
diff --git a/resources/libreboot/config/grub/ga-g41m-es2l/config b/resources/libreboot/config/grub/ga-g41m-es2l/config index 03b81c97..4d051275 100644 --- a/resources/libreboot/config/grub/ga-g41m-es2l/config +++ b/resources/libreboot/config/grub/ga-g41m-es2l/config @@ -17,7 +17,6 @@ CONFIG_COMPILER_GCC=y # CONFIG_SCONFIG_GENPARSER is not set # CONFIG_UNCOMPRESSED_RAMSTAGE is not set CONFIG_COMPRESS_RAMSTAGE=y -# CONFIG_COMPRESS_PRERAM_STAGES is not set CONFIG_INCLUDE_CONFIG_FILE=y CONFIG_EARLY_CBMEM_INIT=y # CONFIG_COLLECT_TIMESTAMPS is not set @@ -115,7 +114,6 @@ CONFIG_MAX_CPUS=1 CONFIG_VGA_BIOS_ID="8086,2e32" # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set # CONFIG_VGA_BIOS is not set -# CONFIG_UDELAY_IO is not set CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" CONFIG_DCACHE_RAM_BASE=0xfeffc000 CONFIG_DCACHE_RAM_SIZE=0x4000 @@ -142,12 +140,13 @@ CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y # CONFIG_BOARD_GIGABYTE_MA78GM is not set CONFIG_USBDEBUG_HCD_INDEX=0 CONFIG_TTYS0_LCS=3 +# CONFIG_CONSOLE_POST is not set +CONFIG_DRIVERS_UART_8250IO=y CONFIG_CPU_ADDR_BITS=36 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 CONFIG_USBDEBUG=y CONFIG_MAINBOARD_VERSION="1.0" # CONFIG_DRIVERS_PS2_KEYBOARD is not set -CONFIG_DRIVERS_UART_8250IO=y # CONFIG_NO_POST is not set CONFIG_BOARD_ROMSIZE_KB_1024=y # CONFIG_COREBOOT_ROMSIZE_KB_64 is not set @@ -175,11 +174,14 @@ CONFIG_FMDFILE="" # # CONFIG_SOC_BROADCOM_CYGNUS is not set CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT="northbridge/intel/x4x/bootblock.c" CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/i82801gx/bootblock.c" CONFIG_TTYS0_BASE=0x3f8 CONFIG_EHCI_BAR=0xfef00000 CONFIG_HEAP_SIZE=0x4000 +CONFIG_CONSOLE_CBMEM=y # CONFIG_SOC_MARVELL_ARMADA38X is not set # CONFIG_SOC_MARVELL_BG4CD is not set # CONFIG_SOC_MEDIATEK_MT8173 is not set @@ -188,6 +190,7 @@ CONFIG_HEAP_SIZE=0x4000 # CONFIG_SOC_NVIDIA_TEGRA210 is not set # CONFIG_SOC_QC_IPQ806X is not set # CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set # CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set # CONFIG_SOC_UCB_RISCV is not set @@ -213,21 +216,21 @@ CONFIG_CPU_INTEL_SOCKET_LGA775=y # CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set # CONFIG_CPU_TI_AM335X is not set # CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set CONFIG_UDELAY_LAPIC=y # CONFIG_LAPIC_MONOTONIC_TIMER is not set # CONFIG_UDELAY_TSC is not set # CONFIG_UDELAY_TIMER2 is not set -# CONFIG_TSC_CALIBRATE_WITH_IO is not set # CONFIG_TSC_SYNC_LFENCE is not set CONFIG_TSC_SYNC_MFENCE=y +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set CONFIG_LOGICAL_CPUS=y # CONFIG_SMM_TSEG is not set # CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set # CONFIG_SERIALIZED_SMM_INITIALIZATION is not set # CONFIG_X86_AMD_FIXED_MTRRS is not set # CONFIG_PLATFORM_USES_FSP1_0 is not set -# CONFIG_PARALLEL_MP is not set -# CONFIG_BACKUP_DEFAULT_SMM_REGION is not set # CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set CONFIG_CACHE_AS_RAM=y CONFIG_SMP=y @@ -249,6 +252,7 @@ CONFIG_CPU_MICROCODE_CBFS_NONE=y CONFIG_VIDEO_MB=0 # CONFIG_NORTHBRIDGE_AMD_PI is not set CONFIG_RAMBASE=0x100000 +# CONFIG_NORTHBRIDGE_INTEL_COMMON_MRC_CACHE is not set CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y CONFIG_NORTHBRIDGE_INTEL_X4X=y CONFIG_HPET_ADDRESS=0xfed00000 @@ -276,6 +280,7 @@ CONFIG_SUPERIO_ITE_IT8718F=y # # CONFIG_MAINBOARD_HAS_CHROMEOS is not set # CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_USE_SIEMENS_HWILIB is not set # CONFIG_ARCH_ARM is not set # CONFIG_ARCH_BOOTBLOCK_ARM is not set # CONFIG_ARCH_VERSTAGE_ARM is not set @@ -329,16 +334,14 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y # CONFIG_USE_MARCH_586 is not set CONFIG_AP_IN_SIPI_WAIT=y CONFIG_SIPI_VECTOR_IN_ROM=y -CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y # CONFIG_ROMCC is not set # CONFIG_LATE_CBMEM_INIT is not set CONFIG_PC80_SYSTEM=y # CONFIG_HAVE_CMOS_DEFAULT is not set CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y # CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set -# CONFIG_COMPILE_IN_DSDT is not set -CONFIG_ROMSTAGE_ADDR=0x2000000 CONFIG_VERSTAGE_ADDR=0x2000000 +# CONFIG_POSTCAR_STAGE is not set # # Devices @@ -363,7 +366,6 @@ CONFIG_CARDBUS_PLUGIN_SUPPORT=y # CONFIG_PCIEXP_L1_SUB_STATE is not set CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 -# CONFIG_PXE_ROM is not set # CONFIG_SOFTWARE_I2C is not set # @@ -375,27 +377,11 @@ CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 # # CONFIG_DRIVERS_AS3722_RTC is not set # CONFIG_GIC is not set -# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set -# CONFIG_DRIVERS_I2C_RTD2132 is not set -# CONFIG_INTEL_DP is not set -# CONFIG_INTEL_DDI is not set -CONFIG_INTEL_EDID=y -# CONFIG_INTEL_INT15 is not set -CONFIG_INTEL_GMA_ACPI=y -# CONFIG_DRIVER_INTEL_I210 is not set # CONFIG_IPMI_KCS is not set # CONFIG_DRIVERS_LENOVO_WACOM is not set -# CONFIG_DRIVER_MAXIM_MAX77686 is not set -# CONFIG_DRIVER_PARADE_PS8625 is not set -CONFIG_DRIVERS_MC146818=y -# CONFIG_MAINBOARD_HAS_LPC_TPM is not set -# CONFIG_DRIVERS_RICOH_RCE822 is not set -# CONFIG_DRIVERS_SIL_3114 is not set +CONFIG_REALTEK_8168_RESET=y # CONFIG_SPI_FLASH is not set # CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set -# CONFIG_DRIVER_TI_TPS65090 is not set -# CONFIG_DRIVERS_TI_TPS65913 is not set -# CONFIG_DRIVERS_TI_TPS65913_RTC is not set CONFIG_DRIVERS_UART=y # CONFIG_NO_UART_ON_SUPERIO is not set # CONFIG_DRIVERS_UART_8250MEM is not set @@ -412,8 +398,26 @@ CONFIG_USBDEBUG_DONGLE_STD=y # CONFIG_USBDEBUG_DONGLE_BEAGLEBONE_BLACK is not set # CONFIG_USBDEBUG_DONGLE_FTDI_FT232H is not set CONFIG_USBDEBUG_OPTIONAL_HUB_PORT=0 +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_INTEL_DP is not set +# CONFIG_INTEL_DDI is not set +CONFIG_INTEL_EDID=y +# CONFIG_INTEL_INT15 is not set +CONFIG_INTEL_GMA_ACPI=y +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +# CONFIG_MAINBOARD_HAS_LPC_TPM is not set +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set # CONFIG_DRIVER_XPOWERS_AXP209 is not set -CONFIG_RTC=y +# CONFIG_RTC is not set # CONFIG_TPM is not set CONFIG_STACK_SIZE=0x1000 CONFIG_MMCONF_SUPPORT_DEFAULT=y @@ -445,7 +449,6 @@ CONFIG_TTYS0_BAUD=115200 # CONFIG_SPKMODEM is not set CONFIG_CONSOLE_USB=y # CONFIG_CONSOLE_NE2K is not set -CONFIG_CONSOLE_CBMEM=y CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set @@ -457,7 +460,6 @@ CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set # CONFIG_CMOS_POST is not set -# CONFIG_CONSOLE_POST is not set CONFIG_POST_DEVICE_NONE=y # CONFIG_POST_DEVICE_LPC is not set # CONFIG_POST_DEVICE_PCI_PCIE is not set @@ -504,8 +506,13 @@ CONFIG_PAYLOAD_FILE="seabios.elf" CONFIG_PAYLOAD_OPTIONS="" CONFIG_COMPRESSED_PAYLOAD_LZMA=y # CONFIG_PAYLOAD_IS_FLAT_BINARY is not set + +# +# Secondary Payloads +# # CONFIG_COREINFO_SECONDARY_PAYLOAD is not set # CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set # # Debugging diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch new file mode 100644 index 00000000..acdc33bc --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0002-add-dmi-init.patch @@ -0,0 +1,200 @@ +From a7fcc0967128317b5c3dcdfffa7fb8e28210573f Mon Sep 17 00:00:00 2001 +From: Damien Zammit <damien@zamaudio.com> +Date: Sat, 21 May 2016 01:56:01 +1000 +Subject: [PATCH] nb/intel/x4x: Add DMI init + +Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8 +Signed-off-by: Damien Zammit <damien@zamaudio.com> +--- + +diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc +index 34d9b0f..3520944 100644 +--- a/src/northbridge/intel/x4x/Makefile.inc ++++ b/src/northbridge/intel/x4x/Makefile.inc +@@ -20,6 +20,7 @@ + romstage-y += raminit.c + romstage-y += raminit_ddr2.c + romstage-y += ram_calc.c ++romstage-y += pcie.c + + ramstage-y += acpi.c + ramstage-y += ram_calc.c +diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c +new file mode 100644 +index 0000000..69a2741 +--- /dev/null ++++ b/src/northbridge/intel/x4x/pcie.c +@@ -0,0 +1,161 @@ ++/* ++ * This file is part of the coreboot project. ++ * ++ * Copyright (C) 2016 Damien Zammit <damien@zamaudio.com> ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; version 2 of ++ * the License. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ */ ++ ++#include <stdint.h> ++#include <stddef.h> ++#include <string.h> ++#include <arch/io.h> ++#include <device/pci_def.h> ++#include <device/pnp_def.h> ++#include <console/console.h> ++ ++#include "iomap.h" ++#include "x4x.h" ++ ++#define DEFAULT_RCBA 0xfed1c000 ++ ++static void init_egress(void) ++{ ++ EPBAR32(0x00) = 0x04010002; ++ EPBAR32(0x04) = 0x00000001; ++ EPBAR32(0x10) = 0x00000001; ++ EPBAR32(0x14) = 0x80000001; ++ EPBAR32(0x1c) = 0x00008001; ++ EPBAR32(0x40) = 0x00010005; ++ EPBAR32(0x44) = 0x00010301; ++ EPBAR32(0x50) = 0x01010001; ++ EPBAR32(0x58) = DEFAULT_DMIBAR; ++ EPBAR32(0x60) = 0x02010003; ++ EPBAR32(0x68) = 0x00008000; ++ EPBAR32(0x70) = 0x03000002; ++ EPBAR32(0x78) = 0x00030000; ++ ++ EPBAR32(0x20) = 0x81000080; ++} ++ ++static void init_dmi(void) ++{ ++ DMIBAR32(0x0000) = 0x04010002; ++ DMIBAR32(0x0004) = 0x00000001; ++ DMIBAR32(0x0010) = 0x00000001; ++ DMIBAR32(0x0014) = 0x80000001; ++ DMIBAR32(0x001c) = 0x00008001; ++ ++ DMIBAR32(0x0020) = 0x81000080; ++ ++ DMIBAR32(0x0028) = 0x00000001; ++ DMIBAR32(0x002c) = 0x86000000; ++ DMIBAR32(0x0040) = 0x08010005; ++ DMIBAR32(0x0044) = 0x01010202; ++ DMIBAR32(0x0050) = 0x00020001; ++ DMIBAR32(0x0058) = DEFAULT_RCBA; ++ DMIBAR32(0x0060) = 0x00010001; ++ DMIBAR32(0x0068) = DEFAULT_EPBAR; ++ DMIBAR32(0x0080) = 0x00010006; ++ DMIBAR32(0x0084) = 0x00012c41; ++ DMIBAR32(0x0088) = 0x00410000; ++ DMIBAR32(0x00f0) = 0x00012000; ++ DMIBAR32(0x00f4) = 0x33fe0037; ++ DMIBAR32(0x00fc) = 0xf000f004; ++ ++ DMIBAR32(0x01b0) = 0x00400000; ++ DMIBAR32(0x01b4) = 0x00008000; ++ DMIBAR32(0x01b8) = 0x000018f2; ++ DMIBAR32(0x01bc) = 0x00000018; ++ DMIBAR32(0x01cc) = 0x00060010; ++ DMIBAR32(0x01d4) = 0x00002000; ++ DMIBAR32(0x0200) = 0x00400f26; ++ DMIBAR32(0x0204) = 0x0001313f; ++ DMIBAR32(0x0208) = 0x00007cb0; ++ DMIBAR32(0x0210) = 0x00000101; ++ DMIBAR32(0x0214) = 0x0007000f; ++ DMIBAR32(0x0224) = 0x00030005; ++ DMIBAR32(0x0230) = 0x2800000e; ++ DMIBAR32(0x0234) = 0x4abcb5bc; ++ DMIBAR32(0x0250) = 0x00000007; ++ ++ DMIBAR32(0x0c00) = 0x0000003c; ++ DMIBAR32(0x0c04) = 0x16000000; ++ DMIBAR32(0x0c0c) = 0x00001fff; ++ DMIBAR32(0x0c10) = 0x0000b100; ++ DMIBAR32(0x0c24) = 0xffff0038; ++ DMIBAR32(0x0c28) = 0x0000000e; ++ DMIBAR32(0x0c2c) = 0x003c0008; ++ DMIBAR32(0x0c30) = 0x02000180; ++ DMIBAR32(0x0c34) = 0x10040071; ++ DMIBAR32(0x0d60) = 0x00000001; ++ DMIBAR32(0x0d6c) = 0x00000300; ++ DMIBAR32(0x0d74) = 0x00000020; ++ DMIBAR32(0x0d78) = 0x00220000; ++ DMIBAR32(0x0d7c) = 0x111f727c; ++ DMIBAR32(0x0d80) = 0x00001409; ++ DMIBAR32(0x0d88) = 0x000f1867; ++ DMIBAR32(0x0d8c) = 0x013000fc; ++ DMIBAR32(0x0da4) = 0x00009757; ++ DMIBAR32(0x0da8) = 0x00000078; ++ DMIBAR32(0x0e00) = 0x000d034e; ++ DMIBAR32(0x0e04) = 0x01880880; ++ DMIBAR32(0x0e08) = 0x01000060; ++ DMIBAR32(0x0e0c) = 0x00000080; ++ DMIBAR32(0x0e10) = 0xbe000000; ++ DMIBAR32(0x0e18) = 0x000000e3; ++ DMIBAR32(0x0e20) = 0x000d034e; ++ DMIBAR32(0x0e24) = 0x01880880; ++ DMIBAR32(0x0e28) = 0x01000060; ++ DMIBAR32(0x0e2c) = 0x00000080; ++ DMIBAR32(0x0e30) = 0xbe000000; ++ DMIBAR32(0x0e38) = 0x000000e3; ++ DMIBAR32(0x0e40) = 0x000d034e; ++ DMIBAR32(0x0e44) = 0x01880880; ++ DMIBAR32(0x0e48) = 0x01000060; ++ DMIBAR32(0x0e4c) = 0x00000080; ++ DMIBAR32(0x0e50) = 0xbe000000; ++ DMIBAR32(0x0e58) = 0x000000e3; ++ DMIBAR32(0x0e60) = 0x000d034e; ++ DMIBAR32(0x0e64) = 0x01880880; ++ DMIBAR32(0x0e68) = 0x01000060; ++ DMIBAR32(0x0e6c) = 0x00000080; ++ DMIBAR32(0x0e70) = 0xbe000000; ++ DMIBAR32(0x0e78) = 0x000000e3; ++ ++ DMIBAR32(0x0e14) = 0xce00381b; ++ DMIBAR32(0x0e34) = 0x4000781b; ++ DMIBAR32(0x0e54) = 0x5c00781b; ++ DMIBAR32(0x0e74) = 0x5400381b; ++ ++ DMIBAR32(0x0218) = 0x0b6202c1; ++ DMIBAR32(0x021c) = 0x02c202c2; ++ ++ DMIBAR32(0x0334) = 0x00b904b3; ++ DMIBAR32(0x0338) = 0x004e0000; ++ ++ DMIBAR32(0x0300) = 0x00a70f4c; ++ DMIBAR32(0x0304) = 0x00a90f54; ++ DMIBAR32(0x0308) = 0x00d103c4; ++ DMIBAR32(0x030c) = 0x003c0e10; ++ DMIBAR32(0x0310) = 0x003d0e11; ++ DMIBAR32(0x0314) = 0x00640000; ++ DMIBAR32(0x0318) = 0x00320c86; ++ DMIBAR32(0x031c) = 0x003a0ca6; ++ DMIBAR32(0x0324) = 0x00040010; ++ DMIBAR32(0x0328) = 0x00040000; ++} ++ ++void x4x_late_init(void) ++{ ++ init_egress(); ++ init_dmi(); ++} +diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h +index e1ef745..17810aa 100644 +--- a/src/northbridge/intel/x4x/x4x.h ++++ b/src/northbridge/intel/x4x/x4x.h +@@ -315,6 +315,7 @@ + + #ifndef __BOOTBLOCK__ + void x4x_early_init(void); ++void x4x_late_init(void); + u32 decode_igd_memory_size(u32 gms); + u32 decode_igd_gtt_size(u32 gsm); + u8 decode_pciebar(u32 *const base, u32 *const len); diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0003-use-x4x-late-init.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0003-use-x4x-late-init.patch new file mode 100644 index 00000000..120fd226 --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/0003-use-x4x-late-init.patch @@ -0,0 +1,60 @@ +From bbea7db476854e3979a60c9a3e173eb8a52a8fa5 Mon Sep 17 00:00:00 2001 +From: Damien Zammit <damien@zamaudio.com> +Date: Sat, 21 May 2016 01:56:53 +1000 +Subject: [PATCH] mb/gigabyte/ga-g41m-es2l: Use x4x_late_init() + +Change-Id: I10d0f6ce747b60499680e4dc229b7fcbb16cc039 +Signed-off-by: Damien Zammit <damien@zamaudio.com> +--- + +diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +index bff481f..425b176 100644 +--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c ++++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +@@ -50,9 +50,10 @@ + pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); + +- outl(0x1f15f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ ++ outl(0x1f35f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe2e9ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ +- outl(0xe0d7fcc3, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ ++ outl(0xe0d7ec02, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ ++ outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ + outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000e7, DEFAULT_GPIOBASE + 0x30); + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); +@@ -98,10 +99,23 @@ + RCBA32(0x3110) = 0x00000001; + RCBA32(0x3140) = 0x00410032; + RCBA32(0x3144) = 0x32100237; ++ RCBA32(0x3148) = 0x00000000; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + RCBA8(0x31ff); ++ ++ RCBA32(0x3410) = 0x00190464; ++ RCBA32(0x3418) = 0x003c0063; ++ RCBA32(0x341c) = 0x00000000; ++ RCBA32(0x3430) = 0x00000001; ++ RCBA32(0x3e00) = 0xff000001; ++ RCBA32(0x3e08) = 0x00000080; ++ RCBA32(0x3e0c) = 0x00800000; ++ RCBA32(0x3e40) = 0xff000001; ++ RCBA32(0x3e48) = 0x00000080; ++ RCBA32(0x3e4c) = 0x00800000; ++ RCBA32(0x3f00) = 0x0000000b; + } + + static void ich7_enable_lpc(void) +@@ -146,4 +160,9 @@ + quick_ram_check(); + cbmem_initialize_empty(); + printk(BIOS_DEBUG, "Memory initialized\n"); ++ ++ x4x_late_init(); ++ ++ printk(BIOS_DEBUG, "x4x late init complete\n"); ++ + } diff --git a/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/004-add-driver-to-reset-nic.patch b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/004-add-driver-to-reset-nic.patch new file mode 100644 index 00000000..279d2f2a --- /dev/null +++ b/resources/libreboot/patch/coreboot/2a6f251f4d8d41d13051ec2c897aea800c07275a/grub/ga-g41m-es2l/004-add-driver-to-reset-nic.patch @@ -0,0 +1,80 @@ +From 5e99bbbf3140b198b2c4b68e646e7042f76806e3 Mon Sep 17 00:00:00 2001 +From: Damien Zammit <damien@zamaudio.com> +Date: Sat, 21 May 2016 02:24:19 +1000 +Subject: [PATCH] drivers/net/r8168: Add driver for 10ec:8168 to reset the NIC + +Change-Id: I32e070b545b4c6369686a7087b7ff838d00764e3 +Signed-off-by: Damien Zammit <damien@zamaudio.com> +--- + +diff --git a/src/drivers/net/Kconfig b/src/drivers/net/Kconfig +new file mode 100644 +index 0000000..b4bafd2 +--- /dev/null ++++ b/src/drivers/net/Kconfig +@@ -0,0 +1,5 @@ ++config REALTEK_8168_RESET ++ bool "Realtek 8168 reset" ++ help ++ This forces a realtek 10ec:8168 card to reset to ensure power state ++ is correct at boot. +diff --git a/src/drivers/net/Makefile.inc b/src/drivers/net/Makefile.inc +index 9b3008d..e435d48 100644 +--- a/src/drivers/net/Makefile.inc ++++ b/src/drivers/net/Makefile.inc +@@ -1,2 +1,3 @@ + romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c + ramstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c ++ramstage-$(CONFIG_REALTEK_8168_RESET) += r8168.c +diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c +new file mode 100644 +index 0000000..be5a7b8 +--- /dev/null ++++ b/src/drivers/net/r8168.c +@@ -0,0 +1,46 @@ ++/* ++ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> ++ * ++ * This driver simply forces the 10ec:8168 device to reset so that it goes ++ * into a proper power state. ++ */ ++ ++#include <arch/io.h> ++#include <device/device.h> ++#include <device/pci.h> ++#include <device/pci_ids.h> ++#include <device/pci_ops.h> ++#include <stdlib.h> ++#include <string.h> ++ ++#define CMD_REG 0x37 ++ ++static void r8168_init(struct device *dev) ++{ ++ u32 cnt = 0; ++ ++ /* Get the resource of the NIC mmio */ ++ struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0); ++ u32 nic_mmio = (u32)res2mmio(nic_res, 0, 0); ++ ++ /* Reset */ ++ outb(0x10, nic_mmio + CMD_REG); ++ ++ /* Poll for reset, with timeout */ ++ while (cnt < 1000 && (inb(nic_mmio + CMD_REG) & 0x10)) ++ cnt++; ++} ++ ++static struct device_operations r8168_ops = { ++ .read_resources = pci_dev_read_resources, ++ .set_resources = pci_dev_set_resources, ++ .enable_resources = pci_dev_enable_resources, ++ .init = r8168_init, ++ .scan_bus = 0, ++}; ++ ++static const struct pci_driver r8168_driver __pci_driver = { ++ .ops = &r8168_ops, ++ .vendor = 0x10ec, ++ .device = 0x8168, ++}; |