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| * | | | | Move MAC address parts into its own document, signal that modifying itFedja Beader2018-10-246-38/+104
| | |_|/ / | |/| | | | | | | | | | | | | is optional and in addition tell users how to do so in their operating system.
* | | | | Merge branch 'doc_panic' of specing/libreboot into masterSwift Geek2018-11-051-0/+81
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| * | | | Add information about panics/freezes on some *00 laptops.Fedja Beader2018-11-031-0/+15
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| * | | | Add kernel panic/netconsole info to FAQFedja Beader2018-11-031-0/+66
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* | | | Merge branch 'cyberbits' of infertux/libreboot into masterAndrew Robbins2018-11-041-0/+4
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| * | | | Add mirror.cyberbits.eu to download pageCédric Félizard2018-11-031-0/+4
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* | | | make freenode a linkLeah Rowe2018-11-021-6/+6
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* | | | typofixes on last news article, per swiftgeek and JohnMH suggestionsLeah Rowe2018-11-021-5/+5
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* | | | news post about freenode 2018 libreboot workshopLeah Rowe2018-11-022-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PR would have been unwise for this, because it's urgent that this is merged right away swiftgeek and and_who: if you disapprove, feel free to revert this commit and I'll put it to pull request instead
* | | | Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-3033-3/+61
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| * | | | Create Coreboot Depthcharge target for Veyron SpeedyAndrew Robbins2018-10-304-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Veyron Speedy ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron speedy corebootfb 4mb depthcharge'
| * | | | Create 4,16MiB Coreboot configs/targets for Veyron SpeedyAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Speedy Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron speedy corebootfb 4mb'
| * | | | Correct CBFS_SIZE in Veyron Speedy Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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| * | | | Create Coreboot Depthcharge target for Veyron MinnieAndrew Robbins2018-10-304-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Veyron Minnie ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron minnie corebootfb 4mb depthcharge'
| * | | | Create 4,16MiB Coreboot configs/targets for Veyron MinnieAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Minnie Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron minnie corebootfb 4mb'
| * | | | Correct CBFS_SIZE in Veyron Minnie Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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| * | | | Create Coreboot Depthcharge target for Veyron MickeyAndrew Robbins2018-10-302-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Veyron Mickey ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron mickey corebootfb 4mb depthcharge'
| * | | | Create 4MiB Coreboot config/target for Veyron MickeyAndrew Robbins2018-10-303-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is not included (yet) as I was unable to find a teardown of this device (Asus Chromebit CS10) online to be sure that reassembly is possible. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Mickey Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron mickey corebootfb 4mb'
| * | | | Create Coreboot Depthcharge target for Veyron JerryAndrew Robbins2018-10-304-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Veyron Jerry ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot veyron jerry corebootfb 4mb depthcharge'
| * | | | Create 4,16MiB Coreboot configs/targets for Veyron JerryAndrew Robbins2018-10-304-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Veyron Jerry Coreboot ROMs can be built with, e.g.: './libreboot build coreboot veyron jerry corebootfb 4mb'
| * | | | Correct CBFS_SIZE in Veyron Jerry Coreboot ConfigAndrew Robbins2018-10-301-1/+1
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| * | | | Add Veyron Jerry/Mickey Depthcharge targetsAndrew Robbins2018-10-301-0/+2
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* | | | Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-3017-0/+34
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| * | | Create Coreboot Depthcharge target for Nyan BlazeAndrew Robbins2018-10-294-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Nyan Blaze ROMs are built with Depthcharge as the default payload, e.g.: './libreboot build coreboot nyan blaze corebootfb 4mb depthcharge'
| * | | Create 4,16MiB Coreboot configs/targets for Nyan BlazeAndrew Robbins2018-10-294-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Nyan Blaze Coreboot ROMs can be built with, e.g.: './libreboot build coreboot nyan blaze corebootfb 4mb'
| * | | Create Coreboot Depthcharge target for Nyan BigAndrew Robbins2018-10-294-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Nyan Big ROMs are built with Depthcharge as its default payload, e.g.: './libreboot build coreboot nyan big corebootfb 4mb depthcharge'
| * | | Create 4,16MiB Coreboot configs/targets for Nyan BigAndrew Robbins2018-10-294-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, corebootfb is the only display mode available for this board; as such, inclusion of the corebootfb subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. Nyan Big Coreboot ROMs can be built with, e.g.: './libreboot build coreboot nyan big corebootfb 4mb'
| * | | Add targets file for Nyan Depthcharge targetAndrew Robbins2018-10-291-0/+2
|/ / / | | | | | | | | | | | | Necessary to build Depthcharge for Nyan Big and Nyan Blaze with their respective defconfig.
* | | Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-262-5/+1458
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| * | Enable additional options in Nyan Blaze configAndrew Robbins2018-10-251-2/+2
| | | | | | | | | | | | | | | | | | Options updated (with new values): CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" # CONFIG_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is not set
| * | Update Nyan Blaze Coreboot configAndrew Robbins2018-10-251-2/+726
| | | | | | | | | | | | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
| * | Enable additional options in Nyan Big configAndrew Robbins2018-10-251-3/+3
| | | | | | | | | | | | | | | | | | | | | Options updated (with new values): CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
| * | Update Nyan Big Coreboot configAndrew Robbins2018-10-251-2/+731
|/ / | | | | | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* | Merge branch 'coreboot-rework' of and_who/libreboot into masterLeah Rowe2018-10-254-7/+2887
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| * Enable additional options in Veyron Mickey configAndrew Robbins2018-10-251-4/+4
| | | | | | | | | | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
| * Update Veyron Mickey Coreboot configAndrew Robbins2018-10-251-0/+710
| | | | | | | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
| * Enable additional options in Veyron Jerry configAndrew Robbins2018-10-251-3/+3
| | | | | | | | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" # CONFIG_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is not set
| * Update Veyron Jerry Coreboot configAndrew Robbins2018-10-251-2/+722
| | | | | | | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
| * Enable additional options in Veyron Speedy configAndrew Robbins2018-10-251-4/+4
| | | | | | | | | | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
| * Update Veyron Speedy Coreboot configAndrew Robbins2018-10-251-2/+727
| | | | | | | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
| * Enable additional options in Veyron Minnie configAndrew Robbins2018-10-251-4/+4
| | | | | | | | | | | | | | | | Options updated (with new values): CONFIG_COMPRESS_RAMSTAGE=y CONFIG_VBOOT_FWID_VERSION="$(KERNELVERSION)" CONFIG_GBB_FLAG_ENABLE_ALTERNATE_OS=y CONFIG_GBB_FLAG_FORCE_DEV_SWITCH_ON=y
| * Update Veyron Minnie Coreboot configAndrew Robbins2018-10-251-2/+727
|/ | | | | Config updated using 'olddefconfig' make target with revision located at "projects/coreboot/configs/revision"
* Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-2310-0/+20
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| * Create SeaBIOS/GRUB targets for D510MO CorebootAndrew Robbins2018-10-226-0/+8
| | | | | | | | | | | | | | D510MO ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot d510mo textmode 1mb seabios'
| * Create 1,16MiB Coreboot configs/targets for D510MOAndrew Robbins2018-10-224-0/+12
|/ | | | | | | | | | | | | | 1MiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. D510MO Coreboot ROMs can be built with, e.g.: './libreboot build coreboot d510mo textmode 1mb'
* Merge branch 'coreboot-rework' of and_who/libreboot into masterLeah Rowe2018-10-228-0/+17
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| * Create SeaBIOS/GRUB targets for D945GCLF CorebootAndrew Robbins2018-10-215-0/+6
| | | | | | | | | | | | | | | | | | | | | | Due to the limited flash space on the board, SeaBIOS is currently the sole payload option when building 512KiB-sized ROMs. D945GCLF ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot d945gclf textmode 512kb seabios', or './libreboot build coreboot d945gclf textmode 16mb grub'
| * Create 512KiB,16MiB Coreboot configs/targets for D945GCLFAndrew Robbins2018-10-213-0/+11
|/ | | | | | | | | | | | | | 512KiB flash is the default for this board. A 16MiB config is included for those looking to modify their board with a larger flash chip. Also, text mode is the only display mode available for this board; as such, inclusion of the textmode subtarget serves only to explicitly indicate the display mode when packaging ROMs upon release. D945GCLF Coreboot ROMs can be built with, e.g.: './libreboot build coreboot d945gclf textmode 512kb'
* Merge branch 'coreboot-rework' of and_who/libreboot into masterSwift Geek2018-10-2121-0/+44
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| * Create SeaBIOS/GRUB targets for GA-G41M-ES2L CorebootAndrew Robbins2018-10-2012-0/+16
| | | | | | | | | | | | | | GA-G41M-ES2L ROMs can now be built with either SeaBIOS or GRUB as a default payload, e.g.: './libreboot build coreboot ga-g41m-es2l corebootfb 1mb seabios'
generated by cgit v1.2.3-70-g09d2 (git 2.47.0) at 2024-11-19 07:31:10 +0000