| Commit message (Collapse) | Author | Age | Files | Lines |
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The release archives will be bigger, but this is a necessary change
that makes libreboot development easier.
At present, there are boards maintained in libreboot by different
people. By doing it this way, that becomes much easier. This is in
contrast to the present situation, where a change to one board
potentially affects all other boards, especially when updating to
a new version of coreboot.
Coreboot-libre scripts, download scripts, build scripts - everything.
The entire build system has been modified to reflect this change
of development.
For reasons of consistency, cbfstool and nvramtool are no longer
included in the util archives.
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Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
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More microcode blobs were deleted upstream, which are therefore no
longer deleted by coreboot-libre.
util/broadcom/secimage/misc.c is not a blob.
Some non-blobs were deleted upstream, which are therefore no
longer listed in libreboot's nonblobs list.
New non-blobs were found, added to the nonblobs list.
vboot submodule was added, since there are parts of it that
cbfstool needs. This submodule is now deblobbed by libreboot.
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The ich9deblob and ich9gen utilities were modified, so that they
support reading and/or writing descriptor images where the GbE
region is not defined. These utilities were also re-factored
and tidied up a bit.
A quick was noticed during the course of this work, in that
Compenent 1 Density was being set to 8MiB constantly, even
on systems with 4MiB flash chips. Component 2 Density was
set statically to 2MiB. ich9gen now sets both to 4MiB or 8MiB,
depending on whether building the descriptor for a 4MiB or
8MiB ROM image.
There are still some ACPI bugs (see docs/hcl/r500.html), which
will have to be fixed upstream. TODO: get hw reg dumps from
a factory R500, and compare with the X200 or T400 dumps.
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Rebase all patches. Remove the ones that are no longer needed.
More CPU microcode updates were moved to coreboot's 3rdparty
repository, so there are less blobs for libreboot to delete
now (because the 3rdparty repository is not checked out in
libreboot).
Correct HDA verbs used for T400 (also R400, T500) (patch is in
coreboot, merged).
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Based on the style used for the script in
resources/scripts/helpers/build/release/
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Update to new coreboot revision:
83b05eb0a85d7b7ac0837cece67afabbdb46ea65
Intel microcode updates are no longer deleted, because these no
longer exist in the main coreboot branch. Instead, they exist in
the optional 3rdparty repository which libreboot does not merge.
note: the microcode in src/soc/intel/ still exists and is still
deleted in libreboot, therefore
TODO: delete the instructions in coreboot that download the
3rdparty branch
MacBook2,1 cstate patch is no longer cherry picked, because this
is now merged in the main coreboot repository.
The patch to disable use of timestamps in non-git is now removed,
because a better version of patch was submitted to and merged in
coreboot.
coreboot-libre:
These blobs either don't exist in coreboot anymore, or have had
their names changed. They are no longer listed in the deblob
script:
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000025.c
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000028.c
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000101.c
src/cpu/amd/model_10xxx/mc_patch_01000086.h
src/cpu/amd/model_10xxx/mc_patch_0100009f.h
src/cpu/amd/model_10xxx/mc_patch_010000b6.h
src/cpu/amd/model_10xxx/mc_patch_010000bf.h
src/cpu/amd/model_10xxx/mc_patch_010000c4.h
src/northbridge/amd/agesa/family12/ssdt.asl
coreboot-libre:
These nonblobs either don't exist in coreboot anymore, or have had
their names changed. They are no longer listed in the nonblobs
or nonblobs_notes files:
./src/mainboard/digitallogic/msm586seg/mainboard.c
./src/mainboard/intel/jarrell/irq_tables.c
./src/mainboard/supermicro/x6dai_g/irq_tables.c
./src/mainboard/technologic/ts5300/mainboard.c
./src/mainboard/via/epia/irq_tables.c
./src/northbridge/via/vx800/examples/chipset_init.c
./src/southbridge/amd/cs5530/bitmap.c
./src/southbridge/amd/pi/avalon/Kconfig
./src/mainboard/google/samus/samsung_8Gb.spd.hex
./src/mainboard/google/samus/empty.spd.hex
./src/mainboard/google/samus/elpida_4Gb.spd.hex
./src/mainboard/google/samus/elpida_8Gb.spd.hex
./src/mainboard/google/samus/samsung_4Gb.spd.hex
coreboot-libre:
The following were added to the nonblobs file:
./src/mainboard/google/samus/spd/samsung_4Gb.spd.hex
./src/mainboard/google/samus/spd/empty.spd.hex
./src/mainboard/google/samus/spd/elpida_8Gb.spd.hex
./src/mainboard/google/samus/spd/hynix_4Gb.spd.hex
./src/mainboard/google/samus/spd/samsung_8Gb.spd.hex
./src/mainboard/google/samus/spd/hynix_8Gb.spd.hex
./src/mainboard/google/samus/spd/elpida_4Gb.spd.hex
./src/drivers/xgi/common/vb_table.h
./src/drivers/xgi/common/vb_setmode.c
./src/drivers/xgi/common/XGI_main.h
./src/mainboard/siemens/mc_tcu3/romstage.c
./src/mainboard/siemens/mc_tcu3/lcd_panel.c
./src/mainboard/siemens/mc_tcu3/modhwinfo.c
./src/mainboard/pcengines/apu1/Kconfig
./src/mainboard/asus/kfsn4-dre/get_bus_conf.c
./src/mainboard/google/samus/spd/spd.c
./src/mainboard/hp/abm/mptable.c
./src/northbridge/amd/pi/00630F01/Kconfig
./src/cpu/amd/microcode/microcode.c
./src/lib/tlcl_structures.h
coreboot-libre:
New blobs in coreboot are now deleted in libreboot:
src/soc/intel/baytrail/microcode/M0C3067_0000031E.h
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c
src/cpu/amd/model_10xxx/mc_patch_010000d9.h
src/cpu/amd/model_10xxx/mc_patch_010000dc.h
src/cpu/amd/model_10xxx/mc_patch_010000db.h
src/cpu/amd/model_10xxx/mc_patch_010000c7.h
src/cpu/amd/model_10xxx/mc_patch_010000c8.h
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List it separately instead.
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These are deleted in a later coreboot, moved to its 3rdparty repo
See 5818da262dc0ce56bb1d5439b6d139bc08c25554 in coreboot or
http://review.coreboot.org/#/c/4531/
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These are not blobs!
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These are not blobs!
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These are not blobs
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